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New RHF1401 ADC driver (with simple filter)
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r400:fc21de09fe8a JC
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1 #
2 # Automatically generated make config: don't edit
3 #
4
5 #
6 # Synthesis
7 #
8 # CONFIG_SYN_INFERRED is not set
9 # CONFIG_SYN_STRATIX is not set
10 # CONFIG_SYN_STRATIXII is not set
11 # CONFIG_SYN_STRATIXIII is not set
12 # CONFIG_SYN_CYCLONEIII is not set
13 # CONFIG_SYN_ALTERA is not set
14 # CONFIG_SYN_AXCEL is not set
15 # CONFIG_SYN_PROASIC is not set
16 # CONFIG_SYN_PROASICPLUS is not set
17 CONFIG_SYN_PROASIC3=y
18 # CONFIG_SYN_UT025CRH is not set
19 # CONFIG_SYN_ATC18 is not set
20 # CONFIG_SYN_ATC18RHA is not set
21 # CONFIG_SYN_CUSTOM1 is not set
22 # CONFIG_SYN_EASIC90 is not set
23 # CONFIG_SYN_IHP25 is not set
24 # CONFIG_SYN_IHP25RH is not set
25 # CONFIG_SYN_LATTICE is not set
26 # CONFIG_SYN_ECLIPSE is not set
27 # CONFIG_SYN_PEREGRINE is not set
28 # CONFIG_SYN_RH_LIB18T is not set
29 # CONFIG_SYN_RHUMC is not set
30 # CONFIG_SYN_SMIC13 is not set
31 # CONFIG_SYN_SPARTAN2 is not set
32 # CONFIG_SYN_SPARTAN3 is not set
33 # CONFIG_SYN_SPARTAN3E is not set
34 # CONFIG_SYN_VIRTEX is not set
35 # CONFIG_SYN_VIRTEXE is not set
36 # CONFIG_SYN_VIRTEX2 is not set
37 # CONFIG_SYN_VIRTEX4 is not set
38 # CONFIG_SYN_VIRTEX5 is not set
39 # CONFIG_SYN_UMC is not set
40 # CONFIG_SYN_TSMC90 is not set
41 # CONFIG_SYN_INFER_RAM is not set
42 # CONFIG_SYN_INFER_PADS is not set
43 # CONFIG_SYN_NO_ASYNC is not set
44 # CONFIG_SYN_SCAN is not set
45
46 #
47 # Clock generation
48 #
49 # CONFIG_CLK_INFERRED is not set
50 # CONFIG_CLK_HCLKBUF is not set
51 # CONFIG_CLK_ALTDLL is not set
52 # CONFIG_CLK_LATDLL is not set
53 CONFIG_CLK_PRO3PLL=y
54 # CONFIG_CLK_LIB18T is not set
55 # CONFIG_CLK_RHUMC is not set
56 # CONFIG_CLK_CLKDLL is not set
57 # CONFIG_CLK_DCM is not set
58 CONFIG_CLK_MUL=2
59 CONFIG_CLK_DIV=8
60 CONFIG_OCLK_DIV=2
61 # CONFIG_PCI_SYSCLK is not set
62 CONFIG_LEON3=y
63 CONFIG_PROC_NUM=1
64
65 #
66 # Processor
67 #
68
69 #
70 # Integer unit
71 #
72 CONFIG_IU_NWINDOWS=8
73 # CONFIG_IU_V8MULDIV is not set
74 # CONFIG_IU_SVT is not set
75 CONFIG_IU_LDELAY=1
76 CONFIG_IU_WATCHPOINTS=0
77 # CONFIG_PWD is not set
78 CONFIG_IU_RSTADDR=00000
79
80 #
81 # Floating-point unit
82 #
83 # CONFIG_FPU_ENABLE is not set
84
85 #
86 # Cache system
87 #
88 CONFIG_ICACHE_ENABLE=y
89 CONFIG_ICACHE_ASSO1=y
90 # CONFIG_ICACHE_ASSO2 is not set
91 # CONFIG_ICACHE_ASSO3 is not set
92 # CONFIG_ICACHE_ASSO4 is not set
93 # CONFIG_ICACHE_SZ1 is not set
94 # CONFIG_ICACHE_SZ2 is not set
95 CONFIG_ICACHE_SZ4=y
96 # CONFIG_ICACHE_SZ8 is not set
97 # CONFIG_ICACHE_SZ16 is not set
98 # CONFIG_ICACHE_SZ32 is not set
99 # CONFIG_ICACHE_SZ64 is not set
100 # CONFIG_ICACHE_SZ128 is not set
101 # CONFIG_ICACHE_SZ256 is not set
102 # CONFIG_ICACHE_LZ16 is not set
103 CONFIG_ICACHE_LZ32=y
104 CONFIG_DCACHE_ENABLE=y
105 CONFIG_DCACHE_ASSO1=y
106 # CONFIG_DCACHE_ASSO2 is not set
107 # CONFIG_DCACHE_ASSO3 is not set
108 # CONFIG_DCACHE_ASSO4 is not set
109 # CONFIG_DCACHE_SZ1 is not set
110 # CONFIG_DCACHE_SZ2 is not set
111 CONFIG_DCACHE_SZ4=y
112 # CONFIG_DCACHE_SZ8 is not set
113 # CONFIG_DCACHE_SZ16 is not set
114 # CONFIG_DCACHE_SZ32 is not set
115 # CONFIG_DCACHE_SZ64 is not set
116 # CONFIG_DCACHE_SZ128 is not set
117 # CONFIG_DCACHE_SZ256 is not set
118 # CONFIG_DCACHE_LZ16 is not set
119 CONFIG_DCACHE_LZ32=y
120 # CONFIG_DCACHE_SNOOP is not set
121 CONFIG_CACHE_FIXED=0
122
123 #
124 # MMU
125 #
126 CONFIG_MMU_ENABLE=y
127 # CONFIG_MMU_COMBINED is not set
128 CONFIG_MMU_SPLIT=y
129 # CONFIG_MMU_REPARRAY is not set
130 CONFIG_MMU_REPINCREMENT=y
131 # CONFIG_MMU_I2 is not set
132 # CONFIG_MMU_I4 is not set
133 CONFIG_MMU_I8=y
134 # CONFIG_MMU_I16 is not set
135 # CONFIG_MMU_I32 is not set
136 # CONFIG_MMU_D2 is not set
137 # CONFIG_MMU_D4 is not set
138 CONFIG_MMU_D8=y
139 # CONFIG_MMU_D16 is not set
140 # CONFIG_MMU_D32 is not set
141 CONFIG_MMU_FASTWB=y
142 CONFIG_MMU_PAGE_4K=y
143 # CONFIG_MMU_PAGE_8K is not set
144 # CONFIG_MMU_PAGE_16K is not set
145 # CONFIG_MMU_PAGE_32K is not set
146 # CONFIG_MMU_PAGE_PROG is not set
147
148 #
149 # Debug Support Unit
150 #
151 # CONFIG_DSU_ENABLE is not set
152
153 #
154 # Fault-tolerance
155 #
156
157 #
158 # VHDL debug settings
159 #
160 # CONFIG_IU_DISAS is not set
161 # CONFIG_DEBUG_PC32 is not set
162
163 #
164 # AMBA configuration
165 #
166 CONFIG_AHB_DEFMST=0
167 CONFIG_AHB_RROBIN=y
168 # CONFIG_AHB_SPLIT is not set
169 CONFIG_AHB_IOADDR=FFF
170 CONFIG_APB_HADDR=800
171 # CONFIG_AHB_MON is not set
172
173 #
174 # Debug Link
175 #
176 CONFIG_DSU_UART=y
177 # CONFIG_DSU_JTAG is not set
178
179 #
180 # Peripherals
181 #
182
183 #
184 # Memory controllers
185 #
186
187 #
188 # 8/32-bit PROM/SRAM controller
189 #
190 CONFIG_SRCTRL=y
191 # CONFIG_SRCTRL_8BIT is not set
192 CONFIG_SRCTRL_PROMWS=3
193 CONFIG_SRCTRL_RAMWS=0
194 CONFIG_SRCTRL_IOWS=0
195 # CONFIG_SRCTRL_RMW is not set
196 CONFIG_SRCTRL_SRBANKS1=y
197 # CONFIG_SRCTRL_SRBANKS2 is not set
198 # CONFIG_SRCTRL_SRBANKS3 is not set
199 # CONFIG_SRCTRL_SRBANKS4 is not set
200 # CONFIG_SRCTRL_SRBANKS5 is not set
201 # CONFIG_SRCTRL_BANKSZ0 is not set
202 # CONFIG_SRCTRL_BANKSZ1 is not set
203 # CONFIG_SRCTRL_BANKSZ2 is not set
204 # CONFIG_SRCTRL_BANKSZ3 is not set
205 # CONFIG_SRCTRL_BANKSZ4 is not set
206 # CONFIG_SRCTRL_BANKSZ5 is not set
207 # CONFIG_SRCTRL_BANKSZ6 is not set
208 # CONFIG_SRCTRL_BANKSZ7 is not set
209 # CONFIG_SRCTRL_BANKSZ8 is not set
210 # CONFIG_SRCTRL_BANKSZ9 is not set
211 # CONFIG_SRCTRL_BANKSZ10 is not set
212 # CONFIG_SRCTRL_BANKSZ11 is not set
213 # CONFIG_SRCTRL_BANKSZ12 is not set
214 # CONFIG_SRCTRL_BANKSZ13 is not set
215 CONFIG_SRCTRL_ROMASEL=19
216
217 #
218 # Leon2 memory controller
219 #
220 CONFIG_MCTRL_LEON2=y
221 # CONFIG_MCTRL_8BIT is not set
222 # CONFIG_MCTRL_16BIT is not set
223 # CONFIG_MCTRL_5CS is not set
224 # CONFIG_MCTRL_SDRAM is not set
225
226 #
227 # PC133 SDRAM controller
228 #
229 # CONFIG_SDCTRL is not set
230
231 #
232 # On-chip RAM/ROM
233 #
234 # CONFIG_AHBROM_ENABLE is not set
235 # CONFIG_AHBRAM_ENABLE is not set
236
237 #
238 # Ethernet
239 #
240 # CONFIG_GRETH_ENABLE is not set
241
242 #
243 # CAN
244 #
245 # CONFIG_CAN_ENABLE is not set
246
247 #
248 # PCI
249 #
250 # CONFIG_PCI_SIMPLE_TARGET is not set
251 # CONFIG_PCI_MASTER_TARGET is not set
252 # CONFIG_PCI_ARBITER is not set
253 # CONFIG_PCI_TRACE is not set
254
255 #
256 # Spacewire
257 #
258 # CONFIG_SPW_ENABLE is not set
259
260 #
261 # UARTs, timers and irq control
262 #
263 CONFIG_UART1_ENABLE=y
264 # CONFIG_UA1_FIFO1 is not set
265 # CONFIG_UA1_FIFO2 is not set
266 CONFIG_UA1_FIFO4=y
267 # CONFIG_UA1_FIFO8 is not set
268 # CONFIG_UA1_FIFO16 is not set
269 # CONFIG_UA1_FIFO32 is not set
270 # CONFIG_UART2_ENABLE is not set
271 CONFIG_IRQ3_ENABLE=y
272 # CONFIG_IRQ3_SEC is not set
273 CONFIG_GPT_ENABLE=y
274 CONFIG_GPT_NTIM=2
275 CONFIG_GPT_SW=8
276 CONFIG_GPT_TW=32
277 CONFIG_GPT_IRQ=8
278 CONFIG_GPT_SEPIRQ=y
279 CONFIG_GPT_WDOGEN=y
280 CONFIG_GPT_WDOG=FFFF
281 CONFIG_GRGPIO_ENABLE=y
282 CONFIG_GRGPIO_WIDTH=8
283 CONFIG_GRGPIO_IMASK=0000
284
285 #
286 # VHDL Debugging
287 #
288 # CONFIG_DEBUG_UART is not set
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1 #GRLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=leon3mp
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
7 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 VHDLSYNFILES=config.vhd leon3mp.vhd
16 VHDLSIMFILES=testbench_package.vhd tb_waveform.vhd ../../lib/lpp/dsp/lpp_fft/actram.vhd
17 SIMTOP=testbench
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
20 PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
22 CLEAN=soft-clean
23
24 TECHLIBS = proasic3e
25
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 tmtc openchip hynix ihp gleichmann micron usbhc
28
29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
30 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
31 ./amba_lcd_16x2_ctrlr \
32 ./general_purpose/lpp_AMR \
33 ./general_purpose/lpp_balise \
34 ./general_purpose/lpp_delay \
35 ./lpp_bootloader \
36 ./lpp_cna \
37 ./lpp_uart \
38 ./lpp_usb \
39
40 FILESKIP = i2cmst.vhd \
41 APB_MULTI_DIODE.vhd \
42 APB_MULTI_DIODE.vhd \
43 Top_MatrixSpec.vhd \
44 APB_FFT.vhd
45
46 include $(GRLIB)/bin/Makefile
47 include $(GRLIB)/software/leon3/Makefile
48
49 ################## project specific targets ##########################
50
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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design test bench configuration
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 ------------------------------------------------------------------------------
15
16
17 library techmap;
18 use techmap.gencomp.all;
19
20 package config is
21
22
23 -- Technology and synthesis options
24 constant CFG_FABTECH : integer := apa3e;
25 constant CFG_MEMTECH : integer := apa3e;
26 constant CFG_PADTECH : integer := inferred;
27 constant CFG_NOASYNC : integer := 0;
28 constant CFG_SCAN : integer := 0;
29
30 -- Clock generator
31 constant CFG_CLKTECH : integer := inferred;
32 constant CFG_CLKMUL : integer := (1);
33 constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
34 constant CFG_OCLKDIV : integer := (1);
35 constant CFG_PCIDLL : integer := 0;
36 constant CFG_PCISYSCLK: integer := 0;
37 constant CFG_CLK_NOFB : integer := 0;
38
39 -- LEON3 processor core
40 constant CFG_LEON3 : integer := 1;
41 constant CFG_NCPU : integer := (1);
42 --constant CFG_NWIN : integer := (7); -- PLE
43 constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC
44 constant CFG_V8 : integer := 0;
45 constant CFG_MAC : integer := 0;
46 constant CFG_SVT : integer := 0;
47 constant CFG_RSTADDR : integer := 16#00000#;
48 constant CFG_LDDEL : integer := (1);
49 constant CFG_NWP : integer := (0);
50 constant CFG_PWD : integer := 1*2;
51 constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist
52 --constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE
53 constant CFG_GRFPUSH : integer := 0;
54 constant CFG_ICEN : integer := 1;
55 constant CFG_ISETS : integer := 1;
56 constant CFG_ISETSZ : integer := 4;
57 constant CFG_ILINE : integer := 4;
58 constant CFG_IREPL : integer := 0;
59 constant CFG_ILOCK : integer := 0;
60 constant CFG_ILRAMEN : integer := 0;
61 constant CFG_ILRAMADDR: integer := 16#8E#;
62 constant CFG_ILRAMSZ : integer := 1;
63 constant CFG_DCEN : integer := 1;
64 constant CFG_DSETS : integer := 1;
65 constant CFG_DSETSZ : integer := 4;
66 constant CFG_DLINE : integer := 4;
67 constant CFG_DREPL : integer := 0;
68 constant CFG_DLOCK : integer := 0;
69 constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
70 constant CFG_DFIXED : integer := 16#00F3#;
71 constant CFG_DLRAMEN : integer := 0;
72 constant CFG_DLRAMADDR: integer := 16#8F#;
73 constant CFG_DLRAMSZ : integer := 1;
74 constant CFG_MMUEN : integer := 0;
75 constant CFG_ITLBNUM : integer := 2;
76 constant CFG_DTLBNUM : integer := 2;
77 constant CFG_TLB_TYPE : integer := 1 + 0*2;
78 constant CFG_TLB_REP : integer := 1;
79 constant CFG_DSU : integer := 1;
80 constant CFG_ITBSZ : integer := 0;
81 constant CFG_ATBSZ : integer := 0;
82 constant CFG_LEON3FT_EN : integer := 0;
83 constant CFG_IUFT_EN : integer := 0;
84 constant CFG_FPUFT_EN : integer := 0;
85 constant CFG_RF_ERRINJ : integer := 0;
86 constant CFG_CACHE_FT_EN : integer := 0;
87 constant CFG_CACHE_ERRINJ : integer := 0;
88 constant CFG_LEON3_NETLIST: integer := 0;
89 constant CFG_DISAS : integer := 0 + 0;
90 constant CFG_PCLOW : integer := 2;
91
92 -- AMBA settings
93 constant CFG_DEFMST : integer := (0);
94 constant CFG_RROBIN : integer := 1;
95 constant CFG_SPLIT : integer := 0;
96 constant CFG_AHBIO : integer := 16#FFF#;
97 constant CFG_APBADDR : integer := 16#800#;
98 constant CFG_AHB_MON : integer := 0;
99 constant CFG_AHB_MONERR : integer := 0;
100 constant CFG_AHB_MONWAR : integer := 0;
101
102 -- DSU UART
103 constant CFG_AHB_UART : integer := 1;
104
105 -- JTAG based DSU interface
106 constant CFG_AHB_JTAG : integer := 0;
107
108 -- Ethernet DSU
109 constant CFG_DSU_ETH : integer := 0 + 0;
110 constant CFG_ETH_BUF : integer := 1;
111 constant CFG_ETH_IPM : integer := 16#C0A8#;
112 constant CFG_ETH_IPL : integer := 16#0033#;
113 constant CFG_ETH_ENM : integer := 16#00007A#;
114 constant CFG_ETH_ENL : integer := 16#CC0001#;
115
116 -- LEON2 memory controller
117 constant CFG_MCTRL_LEON2 : integer := 1;
118 constant CFG_MCTRL_RAM8BIT : integer := 0;
119 constant CFG_MCTRL_RAM16BIT : integer := 0;
120 constant CFG_MCTRL_5CS : integer := 0;
121 constant CFG_MCTRL_SDEN : integer := 0;
122 constant CFG_MCTRL_SEPBUS : integer := 0;
123 constant CFG_MCTRL_INVCLK : integer := 0;
124 constant CFG_MCTRL_SD64 : integer := 0;
125 constant CFG_MCTRL_PAGE : integer := 0 + 0;
126
127 -- SSRAM controller
128 constant CFG_SSCTRL : integer := 0;
129 constant CFG_SSCTRLP16 : integer := 0;
130
131 -- AHB ROM
132 constant CFG_AHBROMEN : integer := 0;
133 constant CFG_AHBROPIP : integer := 0;
134 constant CFG_AHBRODDR : integer := 16#000#;
135 constant CFG_ROMADDR : integer := 16#000#;
136 constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
137
138 -- AHB RAM
139 constant CFG_AHBRAMEN : integer := 0;
140 constant CFG_AHBRSZ : integer := 1;
141 constant CFG_AHBRADDR : integer := 16#A00#;
142
143 -- Gaisler Ethernet core
144 constant CFG_GRETH : integer := 0;
145 constant CFG_GRETH1G : integer := 0;
146 constant CFG_ETH_FIFO : integer := 8;
147
148 -- CAN 2.0 interface
149 constant CFG_CAN : integer := 0;
150 constant CFG_CANIO : integer := 16#0#;
151 constant CFG_CANIRQ : integer := 0;
152 constant CFG_CANLOOP : integer := 0;
153 constant CFG_CAN_SYNCRST : integer := 0;
154 constant CFG_CANFT : integer := 0;
155
156 -- UART 1
157 constant CFG_UART1_ENABLE : integer := 1;
158 constant CFG_UART1_FIFO : integer := 1;
159
160 -- LEON3 interrupt controller
161 constant CFG_IRQ3_ENABLE : integer := 1;
162
163 -- Modular timer
164 constant CFG_GPT_ENABLE : integer := 1;
165 constant CFG_GPT_NTIM : integer := (3);
166 constant CFG_GPT_SW : integer := (8);
167 constant CFG_GPT_TW : integer := (32);
168 constant CFG_GPT_IRQ : integer := (8);
169 constant CFG_GPT_SEPIRQ : integer := 1;
170 constant CFG_GPT_WDOGEN : integer := 0;
171 constant CFG_GPT_WDOG : integer := 16#0#;
172
173 -- GPIO port
174 constant CFG_GRGPIO_ENABLE : integer := 1;
175 constant CFG_GRGPIO_IMASK : integer := 16#0000#;
176 constant CFG_GRGPIO_WIDTH : integer := (7);
177
178 -- GRLIB debugging
179 constant CFG_DUART : integer := 0;
180
181
182 end;
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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19
20
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
36 USE work.config.ALL;
37 LIBRARY lpp;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_lfr_pkg.ALL;
41 USE lpp.iir_filter.ALL;
42 USE lpp.general_purpose.ALL;
43 USE lpp.lpp_lfr_time_management.ALL;
44
45 ENTITY leon3mp IS
46 GENERIC (
47 fabtech : INTEGER := CFG_FABTECH;
48 memtech : INTEGER := CFG_MEMTECH;
49 padtech : INTEGER := CFG_PADTECH;
50 clktech : INTEGER := CFG_CLKTECH;
51 disas : INTEGER := CFG_DISAS; -- Enable disassembly to console
52 dbguart : INTEGER := CFG_DUART; -- Print UART on console
53 pclow : INTEGER := CFG_PCLOW
54 );
55 PORT (
56 clk100MHz : IN STD_ULOGIC;
57 clk49_152MHz : IN STD_ULOGIC;
58 reset : IN STD_ULOGIC;
59
60 errorn : OUT STD_ULOGIC;
61
62 -- UART AHB ---------------------------------------------------------------
63 ahbrxd : IN STD_ULOGIC; -- DSU rx data
64 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
65
66 -- UART APB ---------------------------------------------------------------
67 urxd1 : IN STD_ULOGIC; -- UART1 rx data
68 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
69
70 -- RAM --------------------------------------------------------------------
71 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
72 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 nSRAM_BE0 : OUT STD_LOGIC;
74 nSRAM_BE1 : OUT STD_LOGIC;
75 nSRAM_BE2 : OUT STD_LOGIC;
76 nSRAM_BE3 : OUT STD_LOGIC;
77 nSRAM_WE : OUT STD_LOGIC;
78 nSRAM_CE : OUT STD_LOGIC;
79 nSRAM_OE : OUT STD_LOGIC;
80
81 -- SPW --------------------------------------------------------------------
82 spw1_din : IN STD_LOGIC; -- PLE
83 spw1_sin : IN STD_LOGIC; -- PLE
84 spw1_dout : OUT STD_LOGIC; -- PLE
85 spw1_sout : OUT STD_LOGIC; -- PLE
86
87 spw2_din : IN STD_LOGIC; -- JCPE --TODO
88 spw2_sin : IN STD_LOGIC; -- JCPE --TODO
89 spw2_dout : OUT STD_LOGIC; -- JCPE --TODO
90 spw2_sout : OUT STD_LOGIC; -- JCPE --TODO
91
92 -- ADC --------------------------------------------------------------------
93 bias_fail_sw : OUT STD_LOGIC;
94 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
95 ADC_smpclk : OUT STD_LOGIC;
96 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
97
98 ---------------------------------------------------------------------------
99 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
100 );
101 END;
102
103 ARCHITECTURE Behavioral OF leon3mp IS
104
105 --constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
106 -- CFG_GRETH+CFG_AHB_JTAG;
107 CONSTANT maxahbmsp : INTEGER := CFG_NCPU+
108 CFG_AHB_UART
109 +2;
110 -- 1 is for the SpaceWire module grspw, which is a master
111 -- 1 is for the LFR
112
113 CONSTANT maxahbm : INTEGER := maxahbmsp;
114
115 --Clk & Rst g�n�
116 SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0);
117 SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 SIGNAL resetnl : STD_ULOGIC;
119 SIGNAL clk2x : STD_ULOGIC;
120 SIGNAL lclk2x : STD_ULOGIC;
121 SIGNAL lclk25MHz : STD_ULOGIC;
122 SIGNAL lclk50MHz : STD_ULOGIC;
123 SIGNAL lclk100MHz : STD_ULOGIC;
124 SIGNAL clkm : STD_ULOGIC;
125 SIGNAL rstn : STD_ULOGIC;
126 SIGNAL rstraw : STD_ULOGIC;
127 SIGNAL pciclk : STD_ULOGIC;
128 SIGNAL sdclkl : STD_ULOGIC;
129 SIGNAL cgi : clkgen_in_type;
130 SIGNAL cgo : clkgen_out_type;
131 --- AHB / APB
132 SIGNAL apbi : apb_slv_in_type;
133 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
134 SIGNAL ahbsi : ahb_slv_in_type;
135 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
136 SIGNAL ahbmi : ahb_mst_in_type;
137 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
138 --UART
139 SIGNAL ahbuarti : uart_in_type;
140 SIGNAL ahbuarto : uart_out_type;
141 SIGNAL apbuarti : uart_in_type;
142 SIGNAL apbuarto : uart_out_type;
143 --MEM CTRLR
144 SIGNAL memi : memory_in_type;
145 SIGNAL memo : memory_out_type;
146 SIGNAL wpo : wprot_out_type;
147 SIGNAL sdo : sdram_out_type;
148 SIGNAL ramcs : STD_ULOGIC;
149 --IRQ
150 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
151 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
152 --Timer
153 SIGNAL gpti : gptimer_in_type;
154 SIGNAL gpto : gptimer_out_type;
155 --GPIO
156 SIGNAL gpioi : gpio_in_type;
157 SIGNAL gpioo : gpio_out_type;
158 --DSU
159 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
160 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
161 SIGNAL dsui : dsu_in_type;
162 SIGNAL dsuo : dsu_out_type;
163
164 ---------------------------------------------------------------------
165 --- AJOUT TEST ------------------------Signaux----------------------
166 ---------------------------------------------------------------------
167
168 ---------------------------------------------------------------------
169 CONSTANT IOAEN : INTEGER := CFG_CAN;
170 CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz
171
172 -- time management signal
173 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
175
176 -- Spacewire signals
177 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
178 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
179 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
180 SIGNAL spw_rxtxclk : STD_ULOGIC;
181 SIGNAL spw_rxclkn : STD_ULOGIC;
182 SIGNAL spw_clk : STD_LOGIC;
183 SIGNAL swni : grspw_in_type; -- PLE
184 SIGNAL swno : grspw_out_type; -- PLE
185 SIGNAL clkmn : STD_ULOGIC; -- PLE
186 SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14
187
188 -- AD Converter RHF1401
189 SIGNAL sample : Samples14v(7 DOWNTO 0);
190 SIGNAL sample_val : STD_LOGIC;
191 -----------------------------------------------------------------------------
192 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
193
194 BEGIN
195
196
197 ----------------------------------------------------------------------
198 --- Reset and Clock generation -------------------------------------
199 ----------------------------------------------------------------------
200
201 vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0');
202 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
203
204 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
205
206
207 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz);
208
209 clkgen0 : clkgen -- clock generator
210 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
211 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
212 PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
213
214 PROCESS(lclk100MHz)
215 BEGIN
216 IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN
217 lclk50MHz <= NOT lclk50MHz;
218 END IF;
219 END PROCESS;
220
221 PROCESS(lclk50MHz)
222 BEGIN
223 IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN
224 lclk25MHz <= NOT lclk25MHz;
225 END IF;
226 END PROCESS;
227
228 lclk2x <= lclk50MHz;
229 spw_clk <= lclk50MHz;
230
231 ----------------------------------------------------------------------
232 --- LEON3 processor / DSU / IRQ ------------------------------------
233 ----------------------------------------------------------------------
234
235 l3 : IF CFG_LEON3 = 1 GENERATE
236 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
237 u0 : leon3s -- LEON3 processor
238 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
239 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
240 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
241 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
242 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
243 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
244 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
245 irqi(i), irqo(i), dbgi(i), dbgo(i));
246 END GENERATE;
247 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
248
249 dsugen : IF CFG_DSU = 1 GENERATE
250 dsu0 : dsu3 -- LEON3 Debug Support Unit
251 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
252 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
253 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
254 dsui.enable <= '1';
255 dsui.break <= '0';
256 led(2) <= dsuo.active;
257 END GENERATE;
258 END GENERATE;
259
260 nodsu : IF CFG_DSU = 0 GENERATE
261 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
262 END GENERATE;
263
264 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
265 irqctrl0 : irqmp -- interrupt controller
266 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
267 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
268 END GENERATE;
269 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
270 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
271 irqi(i).irl <= "0000";
272 END GENERATE;
273 apbo(2) <= apb_none;
274 END GENERATE;
275
276 ----------------------------------------------------------------------
277 --- Memory controllers ---------------------------------------------
278 ----------------------------------------------------------------------
279 memctrlr : mctrl GENERIC MAP (
280 hindex => 0,
281 pindex => 0,
282 paddr => 0,
283 srbanks => 1
284 )
285 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
286
287 memi.brdyn <= '1';
288 memi.bexcn <= '1';
289 memi.writen <= '1';
290 memi.wrn <= "1111";
291 memi.bwidth <= "10";
292
293 bdr : FOR i IN 0 TO 3 GENERATE
294 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
295 PORT MAP (
296 data(31-i*8 DOWNTO 24-i*8),
297 memo.data(31-i*8 DOWNTO 24-i*8),
298 memo.bdrive(i),
299 memi.data(31-i*8 DOWNTO 24-i*8));
300 END GENERATE;
301
302 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
303 PORT MAP (address, memo.address(21 DOWNTO 2));
304
305 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
306 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
307 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
308 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
309 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
310 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
311 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
312
313 ----------------------------------------------------------------------
314 --- AHB CONTROLLER -------------------------------------------------
315 ----------------------------------------------------------------------
316 ahb0 : ahbctrl -- AHB arbiter/multiplexer
317 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
318 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
319 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
320 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
321
322 ----------------------------------------------------------------------
323 --- AHB UART -------------------------------------------------------
324 ----------------------------------------------------------------------
325 dcomgen : IF CFG_AHB_UART = 1 GENERATE
326 dcom0 : ahbuart
327 GENERIC MAP (hindex => 3, pindex => 4, paddr => 4)
328 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3));
329 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
330 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
331 led(0) <= NOT ahbuarti.rxd;
332 led(1) <= NOT ahbuarto.txd;
333 END GENERATE;
334 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
335
336 ----------------------------------------------------------------------
337 --- APB Bridge -----------------------------------------------------
338 ----------------------------------------------------------------------
339 apb0 : apbctrl -- AHB/APB bridge
340 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
341 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
342
343 ----------------------------------------------------------------------
344 --- GPT Timer ------------------------------------------------------
345 ----------------------------------------------------------------------
346 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
347 timer0 : gptimer -- timer unit
348 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
349 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
350 nbits => CFG_GPT_TW)
351 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
352 gpti.dhalt <= dsuo.tstop;
353 gpti.extclk <= '0';
354 END GENERATE;
355 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
356
357
358 ----------------------------------------------------------------------
359 --- APB UART -------------------------------------------------------
360 ----------------------------------------------------------------------
361 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
362 uart1 : apbuart -- UART 1
363 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
364 fifosize => CFG_UART1_FIFO)
365 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
366 apbuarti.rxd <= urxd1;
367 apbuarti.extclk <= '0';
368 utxd1 <= apbuarto.txd;
369 apbuarti.ctsn <= '0';
370 END GENERATE;
371 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
372
373 -------------------------------------------------------------------------------
374 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
375 -------------------------------------------------------------------------------
376 apb_lfr_time_management_1: apb_lfr_time_management
377 GENERIC MAP (
378 pindex => 6,
379 paddr => 6,
380 pmask => 16#fff#,
381 pirq => 12)
382 PORT MAP (
383 clk25MHz => clkm,
384 clk49_152MHz => clk49_152MHz,
385 resetn => rstn,
386 grspw_tick => swno.tickout,
387 apbi => apbi,
388 apbo => apbo(6),
389 coarse_time => coarse_time,
390 fine_time => fine_time);
391
392 -----------------------------------------------------------------------
393 --- SpaceWire --------------------------------------------------------
394 -----------------------------------------------------------------------
395
396 spw_rxtxclk <= spw_clk;
397 spw_rxclkn <= NOT spw_rxtxclk;
398
399 -- PADS for SPW1
400 spw1_rxd_pad : inpad GENERIC MAP (tech => padtech)
401 PORT MAP (spw1_din, dtmp(0));
402 spw1_rxs_pad : inpad GENERIC MAP (tech => padtech)
403 PORT MAP (spw1_sin, stmp(0));
404 spw1_txd_pad : outpad GENERIC MAP (tech => padtech)
405 PORT MAP (spw1_dout, swno.d(0));
406 spw1_txs_pad : outpad GENERIC MAP (tech => padtech)
407 PORT MAP (spw1_sout, swno.s(0));
408 -- PADS FOR SPW2
409 spw2_rxd_pad : inpad GENERIC MAP (tech => padtech)
410 PORT MAP (spw2_din, dtmp(1));
411 spw2_rxs_pad : inpad GENERIC MAP (tech => padtech)
412 PORT MAP (spw2_sin, stmp(1));
413 spw2_txd_pad : outpad GENERIC MAP (tech => padtech)
414 PORT MAP (spw2_dout, swno.d(1));
415 spw2_txs_pad : outpad GENERIC MAP (tech => padtech)
416 PORT MAP (spw2_sout, swno.s(1));
417
418 -- GRSPW PHY
419 --spw1_input: if CFG_SPW_GRSPW = 1 generate
420 spw_inputloop : FOR j IN 0 TO 1 GENERATE
421 spw_phy0 : grspw_phy
422 GENERIC MAP(
423 tech => fabtech,
424 rxclkbuftype => 1,
425 scantest => 0)
426 PORT MAP(
427 rxrst => swno.rxrst,
428 di => dtmp(j),
429 si => stmp(j),
430 rxclko => spw_rxclk(j),
431 do => swni.d(j),
432 ndo => swni.nd(j*5+4 DOWNTO j*5),
433 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
434 END GENERATE spw_inputloop;
435
436 -- SPW core
437 sw0 : grspwm
438 GENERIC MAP(
439 tech => apa3e,
440 hindex => 1,
441 pindex => 5,
442 paddr => 5,
443 pirq => 11,
444 sysfreq => 25000, -- CPU_FREQ
445 rmap => 1,
446 rmapcrc => 1,
447 fifosize1 => 16,
448 fifosize2 => 16,
449 rxclkbuftype => 1,
450 rxunaligned => 0,
451 rmapbufs => 4,
452 ft => 0,
453 netlist => 0,
454 ports => 2,
455 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
456 memtech => apa3e,
457 destkey => 2,
458 spwcore => 1
459 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
460 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
461 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
462 )
463 PORT MAP(rstn, clkm, spw_rxclk(0),
464 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
465 ahbmi, ahbmo(1), apbi, apbo(5),
466 swni, swno);
467
468 swni.tickin <= '0';
469 swni.rmapen <= '1';
470 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
471 swni.tickinraw <= '0';
472 swni.timein <= (OTHERS => '0');
473 swni.dcrstval <= (OTHERS => '0');
474 swni.timerrstval <= (OTHERS => '0');
475
476 -------------------------------------------------------------------------------
477 -- LFR
478 -------------------------------------------------------------------------------
479 lpp_lfr_1 : lpp_lfr
480 GENERIC MAP (
481 Mem_use => use_RAM,
482 nb_data_by_buffer_size => 32,
483 nb_word_by_buffer_size => 30,
484 nb_snapshot_param_size => 32,
485 delta_vector_size => 32,
486 delta_vector_size_f0_2 => 7, -- log2(96)
487 pindex => 15,
488 paddr => 15,
489 pmask => 16#fff#,
490 pirq_ms => 6,
491 pirq_wfp => 14,
492 hindex => 2,
493 top_lfr_version => X"00000002")
494 PORT MAP (
495 clk => clkm,
496 rstn => rstn,
497 sample_B => sample(2 DOWNTO 0),
498 sample_E => sample(7 DOWNTO 3),
499 sample_val => sample_val,
500 apbi => apbi,
501 apbo => apbo(15),
502 ahbi => ahbmi,
503 ahbo => ahbmo(2),
504 coarse_time => coarse_time,
505 fine_time => fine_time,
506 data_shaping_BW => bias_fail_sw);
507
508 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
509 GENERIC MAP (
510 ChanelCount => 8,
511 ncycle_cnv_high => 79,
512 ncycle_cnv => 500)
513 PORT MAP (
514 cnv_clk => clk49_152MHz,
515 cnv_rstn => rstn,
516 cnv => ADC_smpclk,
517 clk => clkm,
518 rstn => rstn,
519 ADC_data => ADC_data,
520 ADC_nOE => ADC_OEB_bar_CH,
521 sample => sample,
522 sample_val => sample_val);
523
524 END Behavioral;
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@@ -0,0 +1,27
1 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd
2 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/fifo_latency_correction.vhd
3 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma.vhd
4 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_ip.vhd
5 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_send_16word.vhd
6 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_send_1word.vhd
7 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_singleOrBurst.vhd
8
9 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_snapshot.vhd
10
11 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
12 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr.vhd
13 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd
14 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
15
16 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL_N.vhd
17 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_fft/CoreFFT_simu.vhd
18
19 vcom -quiet -93 -work lpp testbench_package.vhd
20 vcom -quiet -93 -work lpp tb_memory.vhd
21 vcom -quiet -93 -work work tb_ms.vhd
22
23 vsim work.testbench
24
25 log -r *
26 do wave_ms.do
27 ##run 15 ms
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@@ -0,0 +1,146
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
6 USE grlib.stdlib.ALL;
7 USE grlib.AMBA_TestPackage.ALL;
8
9 LIBRARY gaisler;
10 USE gaisler.memctrl.ALL;
11 USE gaisler.leon3.ALL;
12 USE gaisler.uart.ALL;
13 USE gaisler.misc.ALL;
14 USE gaisler.libdcom.ALL;
15 USE gaisler.sim.ALL;
16 USE gaisler.jtagtst.ALL;
17 USE gaisler.misc.ALL;
18
19 LIBRARY techmap;
20 USE techmap.gencomp.ALL;
21
22 LIBRARY esa;
23 USE esa.memoryctrl.ALL;
24
25 LIBRARY lpp;
26 USE lpp.lpp_waveform_pkg.ALL;
27 USE lpp.lpp_memory.ALL;
28 USE lpp.lpp_ad_conv.ALL;
29 USE lpp.testbench_package.ALL;
30 USE lpp.lpp_lfr_pkg.ALL;
31 USE lpp.iir_filter.ALL;
32 USE lpp.general_purpose.ALL;
33 USE lpp.CY7C1061DV33_pkg.ALL;
34
35
36 ENTITY tb_memory IS
37 GENERIC (
38 n_ahb_m : INTEGER := 2;
39 n_ahb_s : INTEGER := 1);
40 PORT (
41 clk : IN STD_LOGIC;
42 rstn : IN STD_LOGIC;
43
44 ahbsi : OUT ahb_slv_in_type;
45 ahbso : IN ahb_slv_out_vector := (OTHERS => ahbs_none);
46 ahbmi : OUT ahb_mst_in_type;
47 ahbmo : IN ahb_mst_out_vector := (OTHERS => ahbm_none)
48 );
49 END tb_memory;
50
51 ARCHITECTURE beh OF tb_memory IS
52 -----------------------------------------------------------------------------
53 SIGNAL memi : memory_in_type;
54 SIGNAL memo : memory_out_type;
55 SIGNAL wpo : wprot_out_type;
56 SIGNAL sdo : sdram_out_type;
57 -----------------------------------------------------------------------------
58 SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0) := "00000000000000000000";
59 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
60 SIGNAL nSRAM_BE0 : STD_LOGIC;
61 SIGNAL nSRAM_BE1 : STD_LOGIC;
62 SIGNAL nSRAM_BE2 : STD_LOGIC;
63 SIGNAL nSRAM_BE3 : STD_LOGIC;
64 SIGNAL nSRAM_WE : STD_LOGIC;
65 SIGNAL nSRAM_CE : STD_LOGIC;
66 SIGNAL nSRAM_OE : STD_LOGIC;
67 -----------------------------------------------------------------------------
68 BEGIN -- beh
69 ahb0 : ahbctrl
70 GENERIC MAP (
71 defmast => 0,
72 split => 0,
73 rrobin => 1,
74 ioaddr => 16#FFF#,
75 ioen => 0,
76 nahbm => n_ahb_s,
77 nahbs => n_ahb_m)
78 PORT MAP (
79 rstn,
80 clk,
81 ahbmi,
82 ahbmo,
83 ahbsi,
84 ahbso);
85
86 memi.brdyn <= '1';
87 memi.bexcn <= '1';
88 memi.writen <= '1';
89 memi.wrn <= "1111";
90 memi.bwidth <= "10";
91
92 bdr : FOR i IN 0 TO 3 GENERATE
93 data_pad : iopadv GENERIC MAP (tech => inferred, width => 8)
94 PORT MAP (
95 data(31-i*8 DOWNTO 24-i*8),
96 memo.data(31-i*8 DOWNTO 24-i*8),
97 memo.bdrive(i),
98 memi.data(31-i*8 DOWNTO 24-i*8));
99 END GENERATE;
100
101 address <= memo.address(21 DOWNTO 2);
102 nSRAM_CE <= NOT(memo.ramsn(0));
103 nSRAM_OE <= memo.ramoen(0);
104 nSRAM_WE <= memo.writen;
105 nSRAM_BE0 <= memo.mben(3);
106 nSRAM_BE1 <= memo.mben(2);
107 nSRAM_BE2 <= memo.mben(1);
108 nSRAM_BE3 <= memo.mben(0);
109
110 async_1Mx16_0: CY7C1061DV33
111 GENERIC MAP (
112 ADDR_BITS => 20,
113 DATA_BITS => 16,
114 depth => 1048576,
115 MEM_ARRAY_DEBUG => 32,
116 TimingInfo => TRUE,
117 TimingChecks => '1')
118 PORT MAP (
119 CE1_b => '0',
120 CE2 => nSRAM_CE,
121 WE_b => nSRAM_WE,
122 OE_b => nSRAM_OE,
123 BHE_b => nSRAM_BE1,
124 BLE_b => nSRAM_BE0,
125 A => address,
126 DQ => data(15 DOWNTO 0));
127
128 async_1Mx16_1: CY7C1061DV33
129 GENERIC MAP (
130 ADDR_BITS => 20,
131 DATA_BITS => 16,
132 depth => 1048576,
133 MEM_ARRAY_DEBUG => 32,
134 TimingInfo => TRUE,
135 TimingChecks => '1')
136 PORT MAP (
137 CE1_b => '0',
138 CE2 => nSRAM_CE,
139 WE_b => nSRAM_WE,
140 OE_b => nSRAM_OE,
141 BHE_b => nSRAM_BE3,
142 BLE_b => nSRAM_BE2,
143 A => address,
144 DQ => data(31 DOWNTO 16));
145
146 END beh;
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
6 USE grlib.stdlib.ALL;
7 USE grlib.AMBA_TestPackage.ALL;
8
9 LIBRARY gaisler;
10 USE gaisler.memctrl.ALL;
11 USE gaisler.leon3.ALL;
12 USE gaisler.uart.ALL;
13 USE gaisler.misc.ALL;
14 USE gaisler.libdcom.ALL;
15 USE gaisler.sim.ALL;
16 USE gaisler.jtagtst.ALL;
17 USE gaisler.misc.ALL;
18
19 LIBRARY techmap;
20 USE techmap.gencomp.ALL;
21
22 LIBRARY esa;
23 USE esa.memoryctrl.ALL;
24
25 LIBRARY lpp;
26 USE lpp.lpp_waveform_pkg.ALL;
27 USE lpp.lpp_memory.ALL;
28 USE lpp.lpp_ad_conv.ALL;
29 USE lpp.testbench_package.ALL;
30 USE lpp.lpp_lfr_pkg.ALL;
31 USE lpp.iir_filter.ALL;
32 USE lpp.general_purpose.ALL;
33 USE lpp.CY7C1061DV33_pkg.ALL;
34
35 USE lpp.FILTERcfg.ALL;
36 USE lpp.lpp_dma_pkg.ALL;
37 USE lpp.lpp_top_lfr_pkg.ALL;
38
39 ENTITY testbench IS
40 END;
41
42 ARCHITECTURE behav OF testbench IS
43
44 SIGNAL clk : STD_LOGIC := '0';
45 SIGNAL rstn : STD_LOGIC := '0';
46 -----------------------------------------------------------------------------
47 SIGNAL apbi : apb_slv_in_type;
48 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
49 SIGNAL ahbsi : ahb_slv_in_type;
50 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
51 SIGNAL ahbmi : ahb_mst_in_type;
52 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
53 -----------------------------------------------------------------------------
54
55 -----------------------------------------------------------------------------
56 -- DMA
57 -----------------------------------------------------------------------------
58 SIGNAL dma_send : STD_LOGIC;
59 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
60 SIGNAL dma_done : STD_LOGIC;
61 SIGNAL dma_ren : STD_LOGIC;
62 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
63 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
64
65 -----------------------------------------------------------------------------
66 -- WFP
67 -----------------------------------------------------------------------------
68 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
69 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
70 SIGNAL data_f0_data_out_valid : STD_LOGIC := '0';
71 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC := '0';
72 SIGNAL data_f0_data_out_ren : STD_LOGIC;
73 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
74 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
75 SIGNAL data_f1_data_out_valid : STD_LOGIC := '0';
76 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC := '0';
77 SIGNAL data_f1_data_out_ren : STD_LOGIC;
78 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
79 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
80 SIGNAL data_f2_data_out_valid : STD_LOGIC := '0';
81 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC := '0';
82 SIGNAL data_f2_data_out_ren : STD_LOGIC;
83 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
84 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
85 SIGNAL data_f3_data_out_valid : STD_LOGIC := '0';
86 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC := '0';
87 SIGNAL data_f3_data_out_ren : STD_LOGIC;
88
89 -----------------------------------------------------------------------------
90 -- ARBITER
91 -----------------------------------------------------------------------------
92 SIGNAL dma_sel_valid : STD_LOGIC;
93 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
94 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
95 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
96 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
97
98 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
100
101 -----------------------------------------------------------------------------
102 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
103 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
104 -----------------------------------------------------------------------------
105
106 -----------------------------------------------------------------------------
107 -- MS
108 -----------------------------------------------------------------------------
109 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
110 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
111 SIGNAL ready_matrix_f1 : STD_LOGIC;
112 SIGNAL ready_matrix_f2 : STD_LOGIC;
113 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
114 SIGNAL error_bad_component_error : STD_LOGIC;
115 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
116 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
117 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
118 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
119 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
120 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
121 SIGNAL status_error_bad_component_error : STD_LOGIC;
122 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
123 SIGNAL config_active_interruption_onError : STD_LOGIC;
124 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
125 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
127 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
128 -----------------------------------------------------------------------------
129 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
130 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
131 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
132 --
133 SIGNAL sample_f0_val : STD_LOGIC;
134 SIGNAL sample_f1_val : STD_LOGIC;
135 SIGNAL sample_f3_val : STD_LOGIC;
136 --
137 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
138 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
139 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
140 --
141 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
142 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
143 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
144 -----------------------------------------------------------------------------
145 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 SIGNAL data_ms_valid : STD_LOGIC;
148 SIGNAL data_ms_valid_burst : STD_LOGIC;
149 SIGNAL data_ms_ren : STD_LOGIC;
150 SIGNAL data_ms_done : STD_LOGIC;
151 -----------------------------------------------------------------------------
152 SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
153 SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
154 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
155 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
156
157 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 SIGNAL run : STD_LOGIC := '1';
159 -----------------------------------------------------------------------------
160 SIGNAL dma_counter : INTEGER;
161 SIGNAL dma_done_reg : STD_LOGIC;
162 -----------------------------------------------------------------------------
163 SIGNAL sample_counter_24k : INTEGER;
164 SIGNAL s_24576Hz : STD_LOGIC;
165 SIGNAL clk49_152MHz : STD_LOGIC := '0';
166
167 SIGNAL s_24_sync_reg_0 : STD_LOGIC;
168 SIGNAL s_24_sync_reg_1 : STD_LOGIC;
169
170 SIGNAL s_24576Hz_sync : STD_LOGIC;
171
172
173 SIGNAL sample_counter_f1 : INTEGER;
174 SIGNAL sample_counter_f2 : INTEGER;
175 -----------------------------------------------------------------------------
176 BEGIN
177
178 -----------------------------------------------------------------------------
179 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
180 clk <= NOT clk AFTER 5 ns; -- 100 MHz
181 rstn <= '1' AFTER 30 ns;
182 -----------------------------------------------------------------------------
183 PROCESS (clk49_152MHz, rstn)
184 BEGIN -- PROCESS
185 IF rstn = '0' THEN -- asynchronous reset (active low)
186 sample_counter_24k <= 0;
187 s_24576Hz <= '0';
188 ELSIF clk49_152MHz'event AND clk49_152MHz = '1' THEN -- rising clock edge
189 IF sample_counter_24k = 0 THEN
190 sample_counter_24k <= 2000;
191 s_24576Hz <= NOT s_24576Hz;
192 ELSE
193 sample_counter_24k <= sample_counter_24k - 1;
194 END IF;
195 END IF;
196 END PROCESS;
197
198 PROCESS (clk, rstn)
199 BEGIN -- PROCESS
200 IF rstn = '0' THEN -- asynchronous reset (active low)
201 s_24_sync_reg_0 <= '0';
202 s_24_sync_reg_1 <= '0';
203 s_24576Hz_sync <= '0';
204 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
205 s_24_sync_reg_0 <= s_24576Hz;
206 s_24_sync_reg_1 <= s_24_sync_reg_0;
207 s_24576Hz_sync <= s_24_sync_reg_0 XOR s_24_sync_reg_1;
208 END IF;
209 END PROCESS;
210
211 PROCESS (clk, rstn)
212 BEGIN -- PROCESS
213 IF rstn = '0' THEN -- asynchronous reset (active low)
214 sample_f0_val <= '0';
215 sample_f1_val <= '0';
216 sample_f3_val <= '0';
217
218 sample_counter_f1 <= 0;
219 sample_counter_f2 <= 0;
220 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
221 IF s_24576Hz_sync = '1' THEN
222 sample_f0_val <= '1';
223 IF sample_counter_f1 = 0 THEN
224 sample_f1_val <= '1';
225 sample_counter_f1 <= 5;
226 ELSE
227 sample_f1_val <= '0';
228 sample_counter_f1 <= sample_counter_f1 -1;
229 END IF;
230 IF sample_counter_f2 = 0 THEN
231 sample_f3_val <= '1';
232 sample_counter_f2 <= 95;
233 ELSE
234 sample_f3_val <= '0';
235 sample_counter_f2 <= sample_counter_f2 -1;
236 END IF;
237 ELSE
238 sample_f0_val <= '0';
239 sample_f1_val <= '0';
240 sample_f3_val <= '0';
241 END IF;
242 END IF;
243 END PROCESS;
244
245 sample_f0_data <= (OTHERS => '0');
246 sample_f1_data <= (OTHERS => '0');
247 sample_f3_data <= (OTHERS => '0');
248 -----------------------------------------------------------------------------
249 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val);
250 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val);
251 sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val);
252
253 -- (MSB) E2 E1 B2 B1 B0 (LSB)
254 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16));
255 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
256 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
257
258 -----------------------------------------------------------------------------
259 tb: PROCESS
260 BEGIN
261 WAIT UNTIL rstn = '1';
262 WAIT UNTIL clk = '1';
263 WAIT UNTIL clk = '1';
264 status_ready_matrix_f0_0 <= '0';
265 status_ready_matrix_f0_1 <= '0';
266 status_ready_matrix_f1 <= '0';
267 status_ready_matrix_f2 <= '0';
268 status_error_anticipating_empty_fifo <= '0';
269 status_error_bad_component_error <= '0';
270 config_active_interruption_onNewMatrix <= '1';
271 config_active_interruption_onError <= '0';
272
273 addr_matrix_f0_0 <= X"40000000";
274 addr_matrix_f0_1 <= X"40020000";
275 addr_matrix_f1 <= X"40040000";
276 addr_matrix_f2 <= X"40060000";
277 WAIT UNTIL clk = '1';
278 END PROCESS tb;
279
280 -----------------------------------------------------------------------------
281 -- MS
282 -----------------------------------------------------------------------------
283 lpp_lfr_ms_1 : lpp_lfr_ms
284 GENERIC MAP (
285 Mem_use => use_RAM)
286 PORT MAP (
287 clk => clk,
288 rstn => rstn,
289
290 coarse_time => coarse_time,
291 fine_time => fine_time,
292
293 sample_f0_wen => sample_f0_wen,
294 sample_f0_wdata => sample_f0_wdata,
295 sample_f1_wen => sample_f1_wen,
296 sample_f1_wdata => sample_f1_wdata,
297 sample_f3_wen => sample_f3_wen,
298 sample_f3_wdata => sample_f3_wdata,
299
300 dma_addr => data_ms_addr, --
301 dma_data => data_ms_data, --
302 dma_valid => data_ms_valid, --
303 dma_valid_burst => data_ms_valid_burst, --
304 dma_ren => data_ms_ren, --
305 dma_done => data_ms_done, --
306
307 -- reg out
308 ready_matrix_f0_0 => ready_matrix_f0_0,
309 ready_matrix_f0_1 => ready_matrix_f0_1,
310 ready_matrix_f1 => ready_matrix_f1,
311 ready_matrix_f2 => ready_matrix_f2,
312 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
313 error_bad_component_error => error_bad_component_error,
314 debug_reg => observation_reg, --debug_reg,
315
316 -- reg in
317 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
318 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
319 status_ready_matrix_f1 => status_ready_matrix_f1,
320 status_ready_matrix_f2 => status_ready_matrix_f2,
321 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
322 status_error_bad_component_error => status_error_bad_component_error,
323 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
324 config_active_interruption_onError => config_active_interruption_onError,
325 addr_matrix_f0_0 => addr_matrix_f0_0,
326 addr_matrix_f0_1 => addr_matrix_f0_1,
327 addr_matrix_f1 => addr_matrix_f1,
328 addr_matrix_f2 => addr_matrix_f2,
329
330 matrix_time_f0_0 => matrix_time_f0_0,
331 matrix_time_f0_1 => matrix_time_f0_1,
332 matrix_time_f1 => matrix_time_f1,
333 matrix_time_f2 => matrix_time_f2);
334
335 -----------------------------------------------------------------------------
336 -- ARBITER
337 -----------------------------------------------------------------------------
338 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
339 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
340 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
341 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
342
343 RR_Arbiter_4_1 : RR_Arbiter_4
344 PORT MAP (
345 clk => clk,
346 rstn => rstn,
347 in_valid => dma_rr_valid,
348 out_grant => dma_rr_grant_s);
349
350 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
351 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
352 dma_rr_valid_ms(2) <= '0';
353 dma_rr_valid_ms(3) <= '0';
354
355 RR_Arbiter_4_2 : RR_Arbiter_4
356 PORT MAP (
357 clk => clk,
358 rstn => rstn,
359 in_valid => dma_rr_valid_ms,
360 out_grant => dma_rr_grant_ms);
361
362 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
363
364 PROCESS (clk, rstn)
365 BEGIN -- PROCESS
366 IF rstn = '0' THEN -- asynchronous reset (active low)
367 dma_sel <= (OTHERS => '0');
368 dma_send <= '0';
369 dma_valid_burst <= '0';
370 data_ms_done <= '0';
371 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
372 IF run = '1' THEN
373 data_ms_done <= '0';
374 IF dma_sel = "00000" OR dma_done = '1' THEN
375 dma_sel <= dma_rr_grant;
376 IF dma_rr_grant(0) = '1' THEN
377 dma_send <= '1';
378 dma_valid_burst <= data_f0_data_out_valid_burst;
379 dma_sel_valid <= data_f0_data_out_valid;
380 ELSIF dma_rr_grant(1) = '1' THEN
381 dma_send <= '1';
382 dma_valid_burst <= data_f1_data_out_valid_burst;
383 dma_sel_valid <= data_f1_data_out_valid;
384 ELSIF dma_rr_grant(2) = '1' THEN
385 dma_send <= '1';
386 dma_valid_burst <= data_f2_data_out_valid_burst;
387 dma_sel_valid <= data_f2_data_out_valid;
388 ELSIF dma_rr_grant(3) = '1' THEN
389 dma_send <= '1';
390 dma_valid_burst <= data_f3_data_out_valid_burst;
391 dma_sel_valid <= data_f3_data_out_valid;
392 ELSIF dma_rr_grant(4) = '1' THEN
393 dma_send <= '1';
394 dma_valid_burst <= data_ms_valid_burst;
395 dma_sel_valid <= data_ms_valid;
396 END IF;
397
398 IF dma_sel(4) = '1' THEN
399 data_ms_done <= '1';
400 END IF;
401 ELSE
402 dma_sel <= dma_sel;
403 dma_send <= '0';
404 END IF;
405 ELSE
406 data_ms_done <= '0';
407 dma_sel <= (OTHERS => '0');
408 dma_send <= '0';
409 dma_valid_burst <= '0';
410 END IF;
411 END IF;
412 END PROCESS;
413
414
415 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
416 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
417 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
418 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
419 data_ms_addr;
420
421 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
422 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
423 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
424 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
425 data_ms_data;
426
427 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
428 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
429 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
430 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
431 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
432
433 -----------------------------------------------------------------------------
434 -- DMA
435 -----------------------------------------------------------------------------
436 --lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
437 -- GENERIC MAP (
438 -- tech => inferred,
439 -- hindex => 0)
440 -- PORT MAP (
441 -- HCLK => clk,
442 -- HRESETn => rstn,
443 -- run => run,
444 -- AHB_Master_In => ahbmi,
445 -- AHB_Master_Out => ahbmo(0),
446
447 -- send => dma_send,
448 -- valid_burst => dma_valid_burst,
449 -- done => dma_done,
450 -- ren => dma_ren,
451 -- address => dma_address,
452 -- data => dma_data);
453
454 PROCESS (clk, rstn)
455 BEGIN -- PROCESS
456 IF rstn = '0' THEN -- asynchronous reset (active low)
457 dma_counter <= 0;
458 dma_done_reg <= '0';
459 dma_done <= '0';
460 dma_ren <= '1';
461 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
462 dma_done_reg <= '0';
463 dma_ren <= '1';
464
465 IF dma_send = '1' THEN
466 dma_counter <= 15;
467 dma_done_reg <= '0';
468 dma_ren <= '0';
469 END IF;
470
471 IF dma_counter > 0 THEN
472 IF dma_counter = 1 THEN
473 dma_done_reg <= '1';
474 END IF;
475 dma_ren <= '0';
476 dma_counter <= dma_counter - 1;
477 END IF;
478
479 dma_done <= dma_done_reg;
480 END IF;
481 END PROCESS;
482
483 -----------------------------------------------------------------------------
484 -- MEMORY + AHB CTRL
485 -----------------------------------------------------------------------------
486 --tb_memory_1: tb_memory
487 -- GENERIC MAP (
488 -- n_ahb_m => 2,
489 -- n_ahb_s => 1)
490 -- PORT MAP (
491 -- clk => clk,
492 -- rstn => rstn,
493 -- ahbsi => ahbsi,
494 -- ahbso => ahbso,
495 -- ahbmi => ahbmi,
496 -- ahbmo => ahbmo);
497 -----------------------------------------------------------------------------
498 END;
Show file before | Show file after | Hide comments
@@ -0,0 +1,54
1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot
4 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/run
5 add wave -noupdate -group DATA_OUT /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out
6 add wave -noupdate -group DATA_OUT /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out
7 add wave -noupdate -group DATA_OUT /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out
8 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out_valid
9 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out_valid
10 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out_valid
11 add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd
12 add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/address
13 add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in
14 add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out
15 add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/data
16 add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/debug_dmaout_okay
17 add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/done
18 add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/hindex
19 add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/hresetn
20 add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ren
21 add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/run
22 add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/send
23 add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/valid_burst
24 add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbin
25 add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbout
26 add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain
27 add wave -noupdate -label data -radix hexadecimal /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data
28 add wave -noupdate -label grant /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout.grant
29 add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout
30 add wave -noupdate -radix hexadecimal /testbench/async_1mx16_0/mem_array_0
31 add wave -noupdate -radix hexadecimal /testbench/async_1mx16_1/mem_array_0
32 add wave -noupdate -radix hexadecimal /testbench/async_1mx16_0/mem_array_1
33 add wave -noupdate -radix hexadecimal /testbench/async_1mx16_1/mem_array_1
34 add wave -noupdate -radix hexadecimal /testbench/async_1mx16_0/mem_array_2
35 add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/async_1mx16_1/mem_array_2(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_2
36 add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/async_1mx16_0/mem_array_3(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_3
37 add wave -noupdate -radix hexadecimal /testbench/async_1mx16_1/mem_array_3
38 TreeUpdate [SetDefaultTree]
39 WaveRestoreCursors {{Cursor 1} {340947831721 ps} 0}
40 configure wave -namecolwidth 540
41 configure wave -valuecolwidth 316
42 configure wave -justifyvalue left
43 configure wave -signalnamewidth 0
44 configure wave -snapdistance 10
45 configure wave -datasetprefix 0
46 configure wave -rowmargin 4
47 configure wave -childrowmargin 2
48 configure wave -gridoffset 0
49 configure wave -gridperiod 1
50 configure wave -griddelta 40
51 configure wave -timeline 0
52 configure wave -timelineunits ns
53 update
54 WaveRestoreZoom {0 ps} {628873035 ns}
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@@ -0,0 +1,147
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
6 USE grlib.stdlib.ALL;
7 USE grlib.AMBA_TestPackage.ALL;
8
9 LIBRARY gaisler;
10 USE gaisler.memctrl.ALL;
11 USE gaisler.leon3.ALL;
12 USE gaisler.uart.ALL;
13 USE gaisler.misc.ALL;
14 USE gaisler.libdcom.ALL;
15 USE gaisler.sim.ALL;
16 USE gaisler.jtagtst.ALL;
17 USE gaisler.misc.ALL;
18
19 LIBRARY techmap;
20 USE techmap.gencomp.ALL;
21
22 LIBRARY esa;
23 USE esa.memoryctrl.ALL;
24
25 LIBRARY lpp;
26 USE lpp.lpp_waveform_pkg.ALL;
27 USE lpp.lpp_memory.ALL;
28 USE lpp.lpp_ad_conv.ALL;
29 USE lpp.testbench_package.ALL;
30 USE lpp.lpp_lfr_pkg.ALL;
31 USE lpp.iir_filter.ALL;
32 USE lpp.general_purpose.ALL;
33 USE lpp.CY7C1061DV33_pkg.ALL;
34
35 ENTITY testbench IS
36 END;
37
38 ARCHITECTURE behav OF testbench IS
39
40 SIGNAL clk25MHz : STD_LOGIC;
41 SIGNAL rstn : STD_LOGIC := '0';
42 -----------------------------------------------------------------------------
43 SIGNAL apbi : apb_slv_in_type;
44 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
45 SIGNAL ahbsi : ahb_slv_in_type;
46 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
47 SIGNAL ahbmi : ahb_mst_in_type;
48 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
49 -----------------------------------------------------------------------------
50 SIGNAL memi : memory_in_type;
51 SIGNAL memo : memory_out_type;
52 SIGNAL wpo : wprot_out_type;
53 SIGNAL sdo : sdram_out_type;
54 -----------------------------------------------------------------------------
55 SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0) := "00000000000000000000";
56 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
57 SIGNAL nSRAM_BE0 : STD_LOGIC;
58 SIGNAL nSRAM_BE1 : STD_LOGIC;
59 SIGNAL nSRAM_BE2 : STD_LOGIC;
60 SIGNAL nSRAM_BE3 : STD_LOGIC;
61 SIGNAL nSRAM_WE : STD_LOGIC;
62 SIGNAL nSRAM_CE : STD_LOGIC;
63 SIGNAL nSRAM_OE : STD_LOGIC;
64 -----------------------------------------------------------------------------
65
66 BEGIN
67
68 -----------------------------------------------------------------------------
69 clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz
70 -----------------------------------------------------------------------------
71
72
73
74 -----------------------------------------------------------------------------
75 -----------------------------------------------------------------------------
76 -----------------------------------------------------------------------------
77 ahb0 : ahbctrl
78 GENERIC MAP (defmast => 0, split => 0, rrobin => 1, ioaddr => 16#FFF#, ioen => 0, nahbm => 2, nahbs => 1)
79 PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso);
80
81 ----------------------------------------------------------------------
82 memctrlr : mctrl
83 GENERIC MAP (hindex => 0, pindex => 0, paddr => 0, srbanks => 1)
84 PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
85
86 memi.brdyn <= '1';
87 memi.bexcn <= '1';
88 memi.writen <= '1';
89 memi.wrn <= "1111";
90 memi.bwidth <= "10";
91
92 bdr : FOR i IN 0 TO 3 GENERATE
93 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
94 PORT MAP (
95 data(31-i*8 DOWNTO 24-i*8),
96 memo.data(31-i*8 DOWNTO 24-i*8),
97 memo.bdrive(i),
98 memi.data(31-i*8 DOWNTO 24-i*8));
99 END GENERATE;
100
101 address <= memo.address(21 DOWNTO 2);
102 nSRAM_CE <= NOT(memo.ramsn(0));
103 nSRAM_OE <= memo.ramoen(0);
104 nSRAM_WE <= memo.writen;
105 nSRAM_BE0 <= memo.mben(3);
106 nSRAM_BE1 <= memo.mben(2);
107 nSRAM_BE2 <= memo.mben(1);
108 nSRAM_BE3 <= memo.mben(0);
109
110 async_1Mx16_0: CY7C1061DV33
111 GENERIC MAP (
112 ADDR_BITS => 20,
113 DATA_BITS => 16,
114 depth => 1048576,
115 MEM_ARRAY_DEBUG => 32,
116 TimingInfo => TRUE,
117 TimingChecks => '1')
118 PORT MAP (
119 CE1_b => '0',
120 CE2 => nSRAM_CE,
121 WE_b => nSRAM_WE,
122 OE_b => nSRAM_OE,
123 BHE_b => nSRAM_BE1,
124 BLE_b => nSRAM_BE0,
125 A => address,
126 DQ => data(15 DOWNTO 0));
127
128 async_1Mx16_1: CY7C1061DV33
129 GENERIC MAP (
130 ADDR_BITS => 20,
131 DATA_BITS => 16,
132 depth => 1048576,
133 MEM_ARRAY_DEBUG => 32,
134 TimingInfo => TRUE,
135 TimingChecks => '1')
136 PORT MAP (
137 CE1_b => '0',
138 CE2 => nSRAM_CE,
139 WE_b => nSRAM_WE,
140 OE_b => nSRAM_OE,
141 BHE_b => nSRAM_BE3,
142 BLE_b => nSRAM_BE2,
143 A => address,
144 DQ => data(31 DOWNTO 16));
145 -----------------------------------------------------------------------------
146
147 END;
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@@ -0,0 +1,144
1
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
6 USE grlib.stdlib.ALL;
7
8
9 PACKAGE testbench_package IS
10
11 COMPONENT tb_memory
12 GENERIC (
13 n_ahb_m : INTEGER;
14 n_ahb_s : INTEGER);
15 PORT (
16 clk : IN STD_LOGIC;
17 rstn : IN STD_LOGIC;
18 ahbsi : OUT ahb_slv_in_type;
19 ahbso : IN ahb_slv_out_vector := (OTHERS => ahbs_none);
20 ahbmi : OUT ahb_mst_in_type;
21 ahbmo : IN ahb_mst_out_vector := (OTHERS => ahbm_none));
22 END COMPONENT;
23
24
25 PROCEDURE APB_WRITE (
26 SIGNAL clk : IN STD_LOGIC;
27 CONSTANT pindex : IN INTEGER;
28 SIGNAL apbi : OUT apb_slv_in_type;
29 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
30 CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
31 );
32
33 PROCEDURE APB_READ (
34 SIGNAL clk : IN STD_LOGIC;
35 CONSTANT pindex : IN INTEGER;
36 SIGNAL apbi : OUT apb_slv_in_type;
37 SIGNAL apbo : IN apb_slv_out_type;
38 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
39 SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
40 );
41
42 PROCEDURE AHB_READ (
43 SIGNAL clk : IN STD_LOGIC;
44 CONSTANT hindex : IN INTEGER;
45 SIGNAL ahbmi : IN ahb_mst_in_type;
46 SIGNAL ahbmo : OUT ahb_mst_out_type;
47 CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
48 SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
49 );
50
51 END testbench_package;
52
53 PACKAGE BODY testbench_package IS
54
55 PROCEDURE APB_WRITE (
56 SIGNAL clk : IN STD_LOGIC;
57 CONSTANT pindex : IN INTEGER;
58 SIGNAL apbi : OUT apb_slv_in_type;
59 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
61 ) IS
62 BEGIN
63 apbi.psel(pindex) <= '1';
64 apbi.pwrite <= '1';
65 apbi.penable <= '1';
66 apbi.paddr <= paddr;
67 apbi.pwdata <= pwdata;
68 WAIT UNTIL clk = '0';
69 WAIT UNTIL clk = '1';
70 apbi.psel(pindex) <= '0';
71 apbi.pwrite <= '0';
72 apbi.penable <= '0';
73 apbi.paddr <= (OTHERS => '0');
74 apbi.pwdata <= (OTHERS => '0');
75 WAIT UNTIL clk = '0';
76 WAIT UNTIL clk = '1';
77
78 END APB_WRITE;
79
80 PROCEDURE APB_READ (
81 SIGNAL clk : IN STD_LOGIC;
82 CONSTANT pindex : IN INTEGER;
83 SIGNAL apbi : OUT apb_slv_in_type;
84 SIGNAL apbo : IN apb_slv_out_type;
85 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
86 SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
87 ) IS
88 BEGIN
89 apbi.psel(pindex) <= '1';
90 apbi.pwrite <= '0';
91 apbi.penable <= '1';
92 apbi.paddr <= paddr;
93 WAIT UNTIL clk = '0';
94 WAIT UNTIL clk = '1';
95 apbi.psel(pindex) <= '0';
96 apbi.pwrite <= '0';
97 apbi.penable <= '0';
98 apbi.paddr <= (OTHERS => '0');
99 WAIT UNTIL clk = '0';
100 WAIT UNTIL clk = '1';
101 prdata <= apbo.prdata;
102 END APB_READ;
103
104 PROCEDURE AHB_READ (
105 SIGNAL clk : IN STD_LOGIC;
106 CONSTANT hindex : IN INTEGER;
107 SIGNAL ahbmi : IN ahb_mst_in_type;
108 SIGNAL ahbmo : OUT ahb_mst_out_type;
109 CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
111 ) IS
112 BEGIN
113 WAIT UNTIL clk = '1';
114 ahbmo.HADDR <= haddr;
115 ahbmo.HPROT <= "0011";
116 ahbmo.HIRQ <= (OTHERS => '0');
117 ahbmo.HCONFIG <= (0 => (OTHERS => '0'), OTHERS => (OTHERS => '0'));
118 ahbmo.HINDEX <= hindex;
119 ahbmo.HBUSREQ <= '1';
120 ahbmo.HLOCK <= '1';
121 ahbmo.HSIZE <= HSIZE_WORD;
122 ahbmo.HBURST <= HBURST_SINGLE;
123 ahbmo.HTRANS <= HTRANS_NONSEQ;
124 ahbmo.HWRITE <= '0';
125 WHILE ahbmi.HREADY = '0' LOOP
126 WAIT UNTIL clk = '1';
127 END LOOP;
128 WAIT UNTIL clk = '1';
129 --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1';
130 ahbmo.HBUSREQ <= '0';
131 ahbmo.HLOCK <= '0';
132 ahbmo.HTRANS <= HTRANS_IDLE;
133 WHILE ahbmi.HREADY = '0' LOOP
134 WAIT UNTIL clk = '1';
135 END LOOP;
136 WAIT UNTIL clk = '1';
137 hrdata <= ahbmi.HRDATA;
138 --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1';
139 ahbmo.HLOCK <= '0';
140 WAIT UNTIL clk = '1';
141
142 END AHB_READ;
143
144 END testbench_package;
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@@ -0,0 +1,96
1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -expand -group FIFO_IN_f0 /testbench/lpp_lfr_ms_1/memf0/reuse
4 add wave -noupdate -expand -group FIFO_IN_f0 /testbench/lpp_lfr_ms_1/memf0/wen
5 add wave -noupdate -expand -group FIFO_IN_f0 /testbench/lpp_lfr_ms_1/memf0/ren
6 add wave -noupdate -expand -group FIFO_IN_f0 /testbench/lpp_lfr_ms_1/memf0/full
7 add wave -noupdate -expand -group FIFO_IN_f0 -expand /testbench/lpp_lfr_ms_1/memf0/empty
8 add wave -noupdate -expand -group FIFO_IN_f1 /testbench/lpp_lfr_ms_1/memf1/reuse
9 add wave -noupdate -expand -group FIFO_IN_f1 /testbench/lpp_lfr_ms_1/memf1/wen
10 add wave -noupdate -expand -group FIFO_IN_f1 /testbench/lpp_lfr_ms_1/memf1/ren
11 add wave -noupdate -expand -group FIFO_IN_f1 /testbench/lpp_lfr_ms_1/memf1/full
12 add wave -noupdate -expand -group FIFO_IN_f1 /testbench/lpp_lfr_ms_1/memf1/empty
13 add wave -noupdate -expand -group FIFO_IN_f2 /testbench/lpp_lfr_ms_1/memf2/reuse
14 add wave -noupdate -expand -group FIFO_IN_f2 /testbench/lpp_lfr_ms_1/memf2/wen
15 add wave -noupdate -expand -group FIFO_IN_f2 /testbench/lpp_lfr_ms_1/memf2/ren
16 add wave -noupdate -expand -group FIFO_IN_f2 /testbench/lpp_lfr_ms_1/memf2/full
17 add wave -noupdate -expand -group FIFO_IN_f2 /testbench/lpp_lfr_ms_1/memf2/empty
18 add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/ect
19 add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/countf1
20 add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/countf0
21 add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/load
22 add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/load_reg
23 add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/i
24 add wave -noupdate -expand -group DRIVE /testbench/lpp_lfr_ms_1/fft0/drive/ect
25 add wave -noupdate -expand -group DRIVE /testbench/lpp_lfr_ms_1/fft0/drive/load
26 add wave -noupdate -expand -group DRIVE /testbench/lpp_lfr_ms_1/fft0/drive/sload
27 add wave -noupdate -expand -group DRIVE /testbench/lpp_lfr_ms_1/fft0/drive/fifocpt
28 add wave -noupdate -expand -group DRIVE -format Analog-Step -max 256.0 /testbench/lpp_lfr_ms_1/fft0/drive/datacount
29 add wave -noupdate -expand -group CORE_FFT -expand -group FFT_IN /testbench/lpp_lfr_ms_1/fft0/drive_write
30 add wave -noupdate -expand -group CORE_FFT -expand -group FFT_IN /testbench/lpp_lfr_ms_1/fft0/drive_datare
31 add wave -noupdate -expand -group CORE_FFT -expand -group FFT_IN /testbench/lpp_lfr_ms_1/fft0/drive_dataim
32 add wave -noupdate -expand -group CORE_FFT -expand -group FFT_IN /testbench/lpp_lfr_ms_1/fft0/fft_load
33 add wave -noupdate -expand -group CORE_FFT -expand -group FFT_OUT /testbench/lpp_lfr_ms_1/fft0/fft_dataim
34 add wave -noupdate -expand -group CORE_FFT -expand -group FFT_OUT /testbench/lpp_lfr_ms_1/fft0/fft_datare
35 add wave -noupdate -expand -group CORE_FFT -expand -group FFT_OUT /testbench/lpp_lfr_ms_1/fft0/fft_valid
36 add wave -noupdate -expand -group CORE_FFT -expand -group FFT_OUT /testbench/lpp_lfr_ms_1/fft0/fft_ready
37 add wave -noupdate -expand -group CORE_FFT -expand -group FFT_OUT /testbench/lpp_lfr_ms_1/fft0/link_read
38 add wave -noupdate /testbench/lpp_lfr_ms_1/fft0/fft0/fft_ongoing
39 add wave -noupdate /testbench/lpp_lfr_ms_1/fft0/link/ect
40 add wave -noupdate /testbench/lpp_lfr_ms_1/fft0/link/fifocpt
41 add wave -noupdate /testbench/lpp_lfr_ms_1/fft0/link/full
42 add wave -noupdate -divider HeaderBuilder
43 add wave -noupdate -expand -group HeaderBuilder -expand -group in -radix hexadecimal /testbench/lpp_lfr_ms_1/head0/statu
44 add wave -noupdate -expand -group HeaderBuilder -expand -group in /testbench/lpp_lfr_ms_1/head0/matrix_type
45 add wave -noupdate -expand -group HeaderBuilder -expand -group in /testbench/lpp_lfr_ms_1/head0/matrix_write
46 add wave -noupdate -expand -group HeaderBuilder -expand -group in /testbench/lpp_lfr_ms_1/head0/valid
47 add wave -noupdate -expand -group HeaderBuilder -expand -group data_in /testbench/lpp_lfr_ms_1/head0/datain
48 add wave -noupdate -expand -group HeaderBuilder -expand -group data_in /testbench/lpp_lfr_ms_1/head0/emptyin
49 add wave -noupdate -expand -group HeaderBuilder -expand -group data_in /testbench/lpp_lfr_ms_1/head0/renout
50 add wave -noupdate -expand -group HeaderBuilder -expand -group data_out /testbench/lpp_lfr_ms_1/head0/emptyout
51 add wave -noupdate -expand -group HeaderBuilder -expand -group data_out /testbench/lpp_lfr_ms_1/head0/renout
52 add wave -noupdate -expand -group HeaderBuilder -expand -group data_out /testbench/lpp_lfr_ms_1/head0/dataout
53 add wave -noupdate -expand -group HeaderBuilder -expand -group HeaderOut /testbench/lpp_lfr_ms_1/head0/header_ack
54 add wave -noupdate -expand -group HeaderBuilder -expand -group HeaderOut /testbench/lpp_lfr_ms_1/head0/header
55 add wave -noupdate -expand -group HeaderBuilder -expand -group HeaderOut /testbench/lpp_lfr_ms_1/head0/header_val
56 add wave -noupdate -expand -group HeaderBuilder /testbench/lpp_lfr_ms_1/head0/write_reg
57 add wave -noupdate -expand -group HeaderBuilder /testbench/lpp_lfr_ms_1/head0/max
58 add wave -noupdate -expand -group HeaderBuilder -radix hexadecimal /testbench/lpp_lfr_ms_1/head0/matrix_param
59 add wave -noupdate -expand -group HeaderBuilder /testbench/lpp_lfr_ms_1/head0/data_cpt
60 add wave -noupdate -expand -group HeaderBuilder /testbench/lpp_lfr_ms_1/head0/ect
61 add wave -noupdate -divider FSM_DMA
62 add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state
63 add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_reg_ack
64 add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_reg_val
65 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_reg
66 add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_ack
67 add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_val
68 add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state
69 add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_done
70 add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_addr
71 add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_data
72 add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_ren
73 add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_valid
74 add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_valid_burst
75 add wave -noupdate -expand -group FIFO /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_data
76 add wave -noupdate -expand -group FIFO /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_empty
77 add wave -noupdate -expand -group FIFO /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_ren
78 add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_send
79 add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_select
80 TreeUpdate [SetDefaultTree]
81 WaveRestoreCursors {{Cursor 1} {10070925926 ps} 0} {{Cursor 2} {22280568302 ps} 0}
82 configure wave -namecolwidth 374
83 configure wave -valuecolwidth 44
84 configure wave -justifyvalue left
85 configure wave -signalnamewidth 0
86 configure wave -snapdistance 10
87 configure wave -datasetprefix 0
88 configure wave -rowmargin 4
89 configure wave -childrowmargin 2
90 configure wave -gridoffset 0
91 configure wave -gridperiod 1
92 configure wave -griddelta 40
93 configure wave -timeline 0
94 configure wave -timelineunits ns
95 update
96 WaveRestoreZoom {10392795757 ps} {10479958650 ps}
Show file before | Show file after | Hide comments
@@ -0,0 +1,99
1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -expand -group FIFO_IN_f0 /testbench/lpp_lfr_ms_1/memf0/reuse
4 add wave -noupdate -expand -group FIFO_IN_f0 /testbench/lpp_lfr_ms_1/memf0/wen
5 add wave -noupdate -expand -group FIFO_IN_f0 /testbench/lpp_lfr_ms_1/memf0/ren
6 add wave -noupdate -expand -group FIFO_IN_f0 /testbench/lpp_lfr_ms_1/memf0/full
7 add wave -noupdate -expand -group FIFO_IN_f0 -expand /testbench/lpp_lfr_ms_1/memf0/empty
8 add wave -noupdate -expand -group FIFO_IN_f1 /testbench/lpp_lfr_ms_1/memf1/reuse
9 add wave -noupdate -expand -group FIFO_IN_f1 /testbench/lpp_lfr_ms_1/memf1/wen
10 add wave -noupdate -expand -group FIFO_IN_f1 /testbench/lpp_lfr_ms_1/memf1/ren
11 add wave -noupdate -expand -group FIFO_IN_f1 /testbench/lpp_lfr_ms_1/memf1/full
12 add wave -noupdate -expand -group FIFO_IN_f1 /testbench/lpp_lfr_ms_1/memf1/empty
13 add wave -noupdate -expand -group FIFO_IN_f2 /testbench/lpp_lfr_ms_1/memf2/reuse
14 add wave -noupdate -expand -group FIFO_IN_f2 /testbench/lpp_lfr_ms_1/memf2/wen
15 add wave -noupdate -expand -group FIFO_IN_f2 /testbench/lpp_lfr_ms_1/memf2/ren
16 add wave -noupdate -expand -group FIFO_IN_f2 /testbench/lpp_lfr_ms_1/memf2/full
17 add wave -noupdate -expand -group FIFO_IN_f2 /testbench/lpp_lfr_ms_1/memf2/empty
18 add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/ect
19 add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/countf1
20 add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/countf0
21 add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/load
22 add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/load_reg
23 add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/i
24 add wave -noupdate -expand -group DRIVE /testbench/lpp_lfr_ms_1/fft0/drive/ect
25 add wave -noupdate -expand -group DRIVE /testbench/lpp_lfr_ms_1/fft0/drive/load
26 add wave -noupdate -expand -group DRIVE /testbench/lpp_lfr_ms_1/fft0/drive/sload
27 add wave -noupdate -expand -group DRIVE /testbench/lpp_lfr_ms_1/fft0/drive/fifocpt
28 add wave -noupdate -expand -group DRIVE -format Analog-Step -max 256.0 /testbench/lpp_lfr_ms_1/fft0/drive/datacount
29 add wave -noupdate -expand -group CORE_FFT -expand -group FFT_IN /testbench/lpp_lfr_ms_1/fft0/drive_write
30 add wave -noupdate -expand -group CORE_FFT -expand -group FFT_IN /testbench/lpp_lfr_ms_1/fft0/drive_datare
31 add wave -noupdate -expand -group CORE_FFT -expand -group FFT_IN /testbench/lpp_lfr_ms_1/fft0/drive_dataim
32 add wave -noupdate -expand -group CORE_FFT -expand -group FFT_IN /testbench/lpp_lfr_ms_1/fft0/fft_load
33 add wave -noupdate -expand -group CORE_FFT -expand -group FFT_OUT /testbench/lpp_lfr_ms_1/fft0/fft_dataim
34 add wave -noupdate -expand -group CORE_FFT -expand -group FFT_OUT /testbench/lpp_lfr_ms_1/fft0/fft_datare
35 add wave -noupdate -expand -group CORE_FFT -expand -group FFT_OUT /testbench/lpp_lfr_ms_1/fft0/fft_valid
36 add wave -noupdate -expand -group CORE_FFT -expand -group FFT_OUT /testbench/lpp_lfr_ms_1/fft0/fft_ready
37 add wave -noupdate -expand -group CORE_FFT -expand -group FFT_OUT /testbench/lpp_lfr_ms_1/fft0/link_read
38 add wave -noupdate /testbench/lpp_lfr_ms_1/fft0/fft0/fft_ongoing
39 add wave -noupdate /testbench/lpp_lfr_ms_1/fft0/link/ect
40 add wave -noupdate /testbench/lpp_lfr_ms_1/fft0/link/fifocpt
41 add wave -noupdate /testbench/lpp_lfr_ms_1/fft0/link/full
42 add wave -noupdate -divider HeaderBuilder
43 add wave -noupdate -expand -group HeaderBuilder -expand -group in -radix hexadecimal /testbench/lpp_lfr_ms_1/head0/statu
44 add wave -noupdate -expand -group HeaderBuilder -expand -group in /testbench/lpp_lfr_ms_1/head0/matrix_type
45 add wave -noupdate -expand -group HeaderBuilder -expand -group in /testbench/lpp_lfr_ms_1/head0/matrix_write
46 add wave -noupdate -expand -group HeaderBuilder -expand -group in /testbench/lpp_lfr_ms_1/head0/valid
47 add wave -noupdate -expand -group HeaderBuilder -expand -group data_in /testbench/lpp_lfr_ms_1/head0/datain
48 add wave -noupdate -expand -group HeaderBuilder -expand -group data_in /testbench/lpp_lfr_ms_1/head0/emptyin
49 add wave -noupdate -expand -group HeaderBuilder -expand -group data_in /testbench/lpp_lfr_ms_1/head0/renout
50 add wave -noupdate -expand -group HeaderBuilder -expand -group data_out /testbench/lpp_lfr_ms_1/head0/emptyout
51 add wave -noupdate -expand -group HeaderBuilder -expand -group data_out /testbench/lpp_lfr_ms_1/head0/renout
52 add wave -noupdate -expand -group HeaderBuilder -expand -group data_out /testbench/lpp_lfr_ms_1/head0/dataout
53 add wave -noupdate -expand -group HeaderBuilder -expand -group HeaderOut /testbench/lpp_lfr_ms_1/head0/header_ack
54 add wave -noupdate -expand -group HeaderBuilder -expand -group HeaderOut /testbench/lpp_lfr_ms_1/head0/header
55 add wave -noupdate -expand -group HeaderBuilder -expand -group HeaderOut /testbench/lpp_lfr_ms_1/head0/header_val
56 add wave -noupdate -expand -group HeaderBuilder /testbench/lpp_lfr_ms_1/head0/write_reg
57 add wave -noupdate -expand -group HeaderBuilder /testbench/lpp_lfr_ms_1/head0/max
58 add wave -noupdate -expand -group HeaderBuilder -radix hexadecimal /testbench/lpp_lfr_ms_1/head0/matrix_param
59 add wave -noupdate -expand -group HeaderBuilder /testbench/lpp_lfr_ms_1/head0/data_cpt
60 add wave -noupdate -expand -group HeaderBuilder /testbench/lpp_lfr_ms_1/head0/ect
61 add wave -noupdate -divider FSM_DMA
62 add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state
63 add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_reg_ack
64 add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_reg_val
65 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_reg
66 add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_ack
67 add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_val
68 add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state
69 add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_done
70 add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_addr
71 add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_data
72 add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_ren
73 add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_valid
74 add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_valid_burst
75 add wave -noupdate -expand -group FIFO /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_data
76 add wave -noupdate -expand -group FIFO /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_empty
77 add wave -noupdate -expand -group FIFO /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_ren
78 add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_send
79 add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_select
80 add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_check_ok
81 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type
82 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type_pre
83 TreeUpdate [SetDefaultTree]
84 WaveRestoreCursors {{Cursor 1} {10452115000 ps} 0} {{Cursor 2} {20841165000 ps} 0}
85 configure wave -namecolwidth 374
86 configure wave -valuecolwidth 44
87 configure wave -justifyvalue left
88 configure wave -signalnamewidth 0
89 configure wave -snapdistance 10
90 configure wave -datasetprefix 0
91 configure wave -rowmargin 4
92 configure wave -childrowmargin 2
93 configure wave -gridoffset 0
94 configure wave -gridperiod 1
95 configure wave -griddelta 40
96 configure wave -timeline 0
97 configure wave -timelineunits ns
98 update
99 WaveRestoreZoom {20841123375 ps} {20841198726 ps}
Show file before | Show file after | Hide comments
@@ -0,0 +1,70
1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot
4 add wave -noupdate /testbench/lpp_lfr_1/lpp_lfr_apbreg_1/status_full
5 add wave -noupdate /testbench/state_read_buffer_on_going
6 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot
7 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/run
8 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out_valid
9 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out_valid
10 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out_valid
11 add wave -noupdate -expand -group MEM -expand -group f2 -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_2(193) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(192) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(191) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(190) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(189) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(188) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(187) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(186) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(185) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(184) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(183) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(182) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(181) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(180) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(179) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(178) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(177) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(176) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(175) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(174) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(173) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(172) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(171) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(170) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(169) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(168) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(167) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(166) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(165) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(164) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(163) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(162) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(161) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(160) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(159) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(158) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(157) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(156) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(155) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(154) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(153) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(152) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(151) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(150) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(149) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(148) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(147) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(146) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(145) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(144) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(143) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(142) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(141) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(140) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(139) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(138) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(137) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(136) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(135) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(134) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(133) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(132) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(131) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(130) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(129) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(128) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(127) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(126) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(125) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(124) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(123) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(122) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(121) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(120) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(119) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(118) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(117) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(116) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(115) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(114) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(113) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(112) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(111) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(110) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(109) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(108) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(107) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(106) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(105) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(104) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(103) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(102) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(101) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(100) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(99) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(98) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(97) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(96) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(95) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(94) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(93) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(92) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(91) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(90) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(89) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(88) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(87) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(86) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(85) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(84) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(83) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(82) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(81) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(80) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(79) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(78) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(77) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(76) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(75) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(74) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(73) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(72) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(71) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(70) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(69) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(68) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(67) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(66) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(65) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(64) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(63) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(62) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(61) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(60) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(59) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(58) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(57) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(56) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(55) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(54) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(53) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(52) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(51) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(50) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(49) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(48) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(47) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(46) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(45) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(44) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(43) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(42) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(41) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(40) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(39) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(38) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(37) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(36) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(35) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(34) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(33) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(32) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(31) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(30) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(29) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(28) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(27) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(26) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(25) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(24) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(23) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(22) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(21) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(20) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(19) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(18) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(17) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(16) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(15) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(14) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(13) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(12) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(11) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(10) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(9) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(8) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(7) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(6) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(5) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(4) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(3) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(2) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(1) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(0) {-radix hexadecimal}} /testbench/async_1mx16_0/mem_array_2
12 add wave -noupdate -expand -group MEM -expand -group f2 -radix hexadecimal -expand -subitemconfig {/testbench/async_1mx16_1/mem_array_2(193) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(192) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(191) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(190) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(189) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(188) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(187) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(186) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(185) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(184) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(183) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(182) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(181) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(180) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(179) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(178) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(177) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(176) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(175) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(174) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(173) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(172) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(171) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(170) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(169) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(168) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(167) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(166) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(165) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(164) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(163) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(162) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(161) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(160) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(159) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(158) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(157) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(156) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(155) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(154) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(153) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(152) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(151) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(150) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(149) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(148) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(147) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(146) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(145) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(144) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(143) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(142) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(141) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(140) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(139) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(138) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(137) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(136) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(135) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(134) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(133) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(132) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(131) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(130) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(129) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(128) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(127) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(126) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(125) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(124) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(123) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(122) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(121) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(120) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(119) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(118) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(117) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(116) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(115) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(114) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(113) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(112) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(111) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(110) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(109) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(108) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(107) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(106) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(105) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(104) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(103) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(102) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(101) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(100) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(99) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(98) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(97) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(96) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(95) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(94) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(93) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(92) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(91) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(90) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(89) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(88) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(87) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(86) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(85) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(84) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(83) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(82) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(81) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(80) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(79) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(78) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(77) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(76) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(75) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(74) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(73) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(72) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(71) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(70) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(69) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(68) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(67) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(66) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(65) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(64) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(63) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(62) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(61) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(60) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(59) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(58) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(57) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(56) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(55) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(54) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(53) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(52) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(51) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(50) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(49) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(48) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(47) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(46) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(45) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(44) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(43) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(42) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(41) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(40) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(39) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(38) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(37) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(36) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(35) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(34) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(33) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(32) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(31) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(30) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(29) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(28) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(27) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(26) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(25) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(24) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(23) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(22) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(21) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(20) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(19) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(18) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(17) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(16) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(15) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(14) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(13) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(12) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(11) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(10) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(9) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(8) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(7) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(6) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(5) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(4) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(3) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(2) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(1) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(0) {-radix hexadecimal}} /testbench/async_1mx16_1/mem_array_2
13 add wave -noupdate -expand -group MEM -expand -group f1 -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_1(193) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(192) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(191) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(190) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(189) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(188) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(187) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(186) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(185) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(184) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(183) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(182) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(181) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(180) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(179) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(178) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(177) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(176) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(175) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(174) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(173) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(172) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(171) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(170) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(169) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(168) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(167) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(166) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(165) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(164) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(163) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(162) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(161) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(160) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(159) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(158) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(157) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(156) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(155) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(154) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(153) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(152) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(151) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(150) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(149) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(148) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(147) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(146) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(145) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(144) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(143) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(142) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(141) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(140) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(139) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(138) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(137) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(136) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(135) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(134) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(133) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(132) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(131) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(130) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(129) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(128) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(127) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(126) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(125) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(124) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(123) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(122) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(121) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(120) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(119) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(118) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(117) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(116) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(115) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(114) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(113) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(112) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(111) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(110) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(109) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(108) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(107) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(106) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(105) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(104) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(103) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(102) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(101) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(100) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(99) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(98) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(97) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(96) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(95) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(94) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(93) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(92) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(91) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(90) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(89) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(88) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(87) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(86) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(85) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(84) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(83) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(82) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(81) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(80) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(79) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(78) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(77) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(76) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(75) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(74) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(73) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(72) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(71) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(70) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(69) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(68) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(67) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(66) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(65) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(64) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(63) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(62) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(61) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(60) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(59) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(58) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(57) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(56) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(55) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(54) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(53) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(52) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(51) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(50) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(49) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(48) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(47) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(46) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(45) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(44) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(43) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(42) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(41) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(40) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(39) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(38) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(37) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(36) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(35) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(34) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(33) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(32) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(31) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(30) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(29) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(28) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(27) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(26) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(25) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(24) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(23) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(22) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(21) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(20) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(19) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(18) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(17) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(16) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(15) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(14) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(13) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(12) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(11) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(10) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(9) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(8) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(7) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(6) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(5) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(4) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(3) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(2) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(1) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(0) {-radix hexadecimal}} /testbench/async_1mx16_0/mem_array_1
14 add wave -noupdate -expand -group MEM -expand -group f1 -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_1(193) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(192) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(191) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(190) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(189) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(188) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(187) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(186) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(185) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(184) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(183) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(182) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(181) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(180) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(179) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(178) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(177) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(176) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(175) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(174) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(173) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(172) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(171) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(170) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(169) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(168) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(167) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(166) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(165) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(164) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(163) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(162) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(161) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(160) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(159) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(158) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(157) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(156) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(155) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(154) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(153) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(152) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(151) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(150) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(149) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(148) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(147) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(146) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(145) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(144) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(143) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(142) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(141) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(140) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(139) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(138) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(137) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(136) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(135) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(134) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(133) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(132) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(131) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(130) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(129) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(128) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(127) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(126) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(125) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(124) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(123) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(122) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(121) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(120) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(119) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(118) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(117) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(116) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(115) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(114) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(113) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(112) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(111) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(110) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(109) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(108) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(107) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(106) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(105) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(104) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(103) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(102) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(101) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(100) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(99) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(98) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(97) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(96) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(95) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(94) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(93) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(92) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(91) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(90) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(89) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(88) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(87) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(86) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(85) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(84) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(83) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(82) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(81) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(80) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(79) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(78) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(77) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(76) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(75) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(74) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(73) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(72) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(71) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(70) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(69) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(68) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(67) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(66) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(65) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(64) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(63) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(62) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(61) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(60) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(59) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(58) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(57) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(56) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(55) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(54) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(53) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(52) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(51) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(50) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(49) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(48) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(47) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(46) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(45) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(44) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(43) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(42) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(41) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(40) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(39) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(38) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(37) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(36) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(35) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(34) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(33) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(32) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(31) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(30) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(29) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(28) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(27) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(26) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(25) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(24) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(23) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(22) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(21) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(20) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(19) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(18) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(17) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(16) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(15) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(14) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(13) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(12) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(11) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(10) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(9) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(8) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(7) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(6) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(5) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(4) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(3) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(2) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(1) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(0) {-radix hexadecimal}} /testbench/async_1mx16_1/mem_array_1
15 add wave -noupdate -expand -group MEM -expand -group f0 -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_0(193) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(192) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(191) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(190) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(189) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(188) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(187) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(186) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(185) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(184) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(183) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(182) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(181) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(180) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(179) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(178) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(177) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(176) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(175) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(174) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(173) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(172) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(171) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(170) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(169) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(168) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(167) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(166) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(165) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(164) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(163) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(162) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(161) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(160) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(159) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(158) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(157) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(156) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(155) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(154) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(153) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(152) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(151) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(150) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(149) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(148) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(147) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(146) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(145) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(144) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(143) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(142) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(141) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(140) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(139) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(138) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(137) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(136) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(135) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(134) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(133) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(132) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(131) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(130) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(129) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(128) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(127) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(126) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(125) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(124) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(123) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(122) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(121) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(120) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(119) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(118) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(117) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(116) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(115) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(114) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(113) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(112) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(111) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(110) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(109) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(108) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(107) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(106) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(105) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(104) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(103) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(102) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(101) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(100) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(99) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(98) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(97) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(96) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(95) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(94) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(93) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(92) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(91) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(90) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(89) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(88) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(87) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(86) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(85) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(84) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(83) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(82) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(81) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(80) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(79) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(78) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(77) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(76) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(75) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(74) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(73) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(72) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(71) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(70) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(69) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(68) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(67) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(66) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(65) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(64) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(63) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(62) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(61) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(60) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(59) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(58) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(57) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(56) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(55) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(54) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(53) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(52) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(51) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(50) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(49) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(48) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(47) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(46) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(45) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(44) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(43) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(42) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(41) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(40) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(39) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(38) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(37) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(36) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(35) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(34) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(33) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(32) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(31) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(30) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(29) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(28) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(27) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(26) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(25) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(24) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(23) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(22) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(21) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(20) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(19) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(18) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(17) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(16) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(15) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(14) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(13) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(12) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(11) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(10) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(9) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(8) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(7) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(6) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(5) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(4) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(3) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(2) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(1) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(0) {-radix hexadecimal}} /testbench/async_1mx16_0/mem_array_0
16 add wave -noupdate -expand -group MEM -expand -group f0 -radix hexadecimal /testbench/async_1mx16_1/mem_array_0
17 add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hbusreq {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hlock {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.htrans {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.haddr {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hwrite {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hsize {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hburst {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hprot {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hwdata {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hirq {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hconfig {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hindex {-radix hexadecimal}} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out
18 add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in.hgrant {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in.hready {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in.hresp {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in.hrdata {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in.hirq {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in.testen {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in.testrst {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in.scanen {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in.testoen {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in.testin {-radix hexadecimal}} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in
19 add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/ahbso(0).hready {-radix hexadecimal} /testbench/ahbso(0).hresp {-radix hexadecimal} /testbench/ahbso(0).hrdata {-radix hexadecimal} /testbench/ahbso(0).hsplit {-radix hexadecimal} /testbench/ahbso(0).hirq {-radix hexadecimal} /testbench/ahbso(0).hconfig {-radix hexadecimal} /testbench/ahbso(0).hindex {-radix hexadecimal}} /testbench/ahbso(0)
20 add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/ahbsi.hsel {-radix hexadecimal} /testbench/ahbsi.haddr {-radix hexadecimal} /testbench/ahbsi.hwrite {-radix hexadecimal} /testbench/ahbsi.htrans {-radix hexadecimal} /testbench/ahbsi.hsize {-radix hexadecimal} /testbench/ahbsi.hburst {-radix hexadecimal} /testbench/ahbsi.hwdata {-radix hexadecimal} /testbench/ahbsi.hprot {-radix hexadecimal} /testbench/ahbsi.hready {-radix hexadecimal} /testbench/ahbsi.hmaster {-radix hexadecimal} /testbench/ahbsi.hmastlock {-radix hexadecimal} /testbench/ahbsi.hmbsel {-radix hexadecimal} /testbench/ahbsi.hirq {-radix hexadecimal} /testbench/ahbsi.testen {-radix hexadecimal} /testbench/ahbsi.testrst {-radix hexadecimal} /testbench/ahbsi.scanen {-radix hexadecimal} /testbench/ahbsi.testoen {-radix hexadecimal} /testbench/ahbsi.testin {-radix hexadecimal}} /testbench/ahbsi
21 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_headreg_1/o_rdata_3
22 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_headreg_1/o_rdata_2
23 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_headreg_1/o_rdata_1
24 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_headreg_1/o_rdata_0
25 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_headreg_1/o_empty_almost
26 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_headreg_1/o_empty
27 add wave -noupdate -expand /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_headreg_1/o_data_ren
28 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_ren
29 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_f3_data_out_valid_burst
30 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_f3_data_out_valid
31 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_f3_addr_out
32 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_f2_data_out_valid_burst
33 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_f2_data_out_valid
34 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_f2_addr_out
35 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_f1_data_out_valid_burst
36 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_f1_data_out_valid
37 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_f1_addr_out
38 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_f0_data_out_valid_burst
39 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_f0_data_out_valid
40 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/address
41 add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/state
42 add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/send_ok
43 add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/send_ko
44 add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/send
45 add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/ren
46 add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/hresetn
47 add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/hclk
48 add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/grant_counter
49 add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/dmaout
50 add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/dmain
51 add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/data_counter
52 add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/data
53 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/address
54 TreeUpdate [SetDefaultTree]
55 WaveRestoreCursors {{Cursor 1} {130825265 ns} 1} {{Cursor 2} {130825145 ns} 1} {{Cursor 3} {130825745 ns} 0}
56 configure wave -namecolwidth 530
57 configure wave -valuecolwidth 64
58 configure wave -justifyvalue left
59 configure wave -signalnamewidth 0
60 configure wave -snapdistance 10
61 configure wave -datasetprefix 0
62 configure wave -rowmargin 4
63 configure wave -childrowmargin 2
64 configure wave -gridoffset 0
65 configure wave -gridperiod 1
66 configure wave -griddelta 40
67 configure wave -timeline 0
68 configure wave -timelineunits ns
69 update
70 WaveRestoreZoom {130825588 ns} {130825885 ns}
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
48 ENTITY MINI_LFR_top IS
49
50 PORT (
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
111
112 END MINI_LFR_top;
113
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
116
117 COMPONENT lpp_lfr_ms_tb
118 GENERIC (
119 Mem_use : INTEGER);
120 PORT (
121 clk : IN STD_LOGIC;
122 rstn : IN STD_LOGIC;
123 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
124 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
125 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
126 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
127 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
128 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
129 MEM_OUT_SM_Read : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
130 MEM_OUT_SM_Data_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
131 MEM_OUT_SM_Full_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
132 MEM_OUT_SM_Full_pad_2 : OUT STD_LOGIC;
133 MEM_OUT_SM_Empty_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
134 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
135 observation_vector_0 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
136 observation_vector_1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
137 END COMPONENT;
138
139 COMPONENT lpp_lfr_apbreg_tb
140 GENERIC (
141 pindex : INTEGER;
142 paddr : INTEGER;
143 pmask : INTEGER);
144 PORT (
145 HCLK : IN STD_ULOGIC;
146 HRESETn : IN STD_ULOGIC;
147 apbi : IN apb_slv_in_type;
148 apbo : OUT apb_slv_out_type;
149 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
150 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
151 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
152 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
153 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
154 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
155 MEM_OUT_SM_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
156 MEM_OUT_SM_Data_out : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
157 MEM_OUT_SM_Full : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
158 MEM_OUT_SM_Full_2 : IN STD_LOGIC;
159 MEM_OUT_SM_Empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0));
160 END COMPONENT;
161
162
163
164 SIGNAL clk_50_s : STD_LOGIC := '0';
165 SIGNAL clk_25 : STD_LOGIC := '0';
166 SIGNAL clk_24 : STD_LOGIC := '0';
167 -----------------------------------------------------------------------------
168 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
170 --
171 SIGNAL errorn : STD_LOGIC;
172 -- UART AHB ---------------------------------------------------------------
173 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
174 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
175
176 -- UART APB ---------------------------------------------------------------
177 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
178 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
179 --
180 SIGNAL I00_s : STD_LOGIC;
181
182 -- CONSTANTS
183 CONSTANT CFG_PADTECH : INTEGER := inferred;
184 --
185 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
186 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
187 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
188
189 SIGNAL apbi_ext : apb_slv_in_type;
190 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
191 SIGNAL ahbi_s_ext : ahb_slv_in_type;
192 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
193 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
194 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
195
196 -- Spacewire signals
197 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
198 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
199 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
200 SIGNAL spw_rxtxclk : STD_ULOGIC;
201 SIGNAL spw_rxclkn : STD_ULOGIC;
202 SIGNAL spw_clk : STD_LOGIC;
203 SIGNAL swni : grspw_in_type;
204 SIGNAL swno : grspw_out_type;
205 -- SIGNAL clkmn : STD_ULOGIC;
206 -- SIGNAL txclk : STD_ULOGIC;
207
208 --GPIO
209 SIGNAL gpioi : gpio_in_type;
210 SIGNAL gpioo : gpio_out_type;
211
212 -- AD Converter ADS7886
213 SIGNAL sample : Samples14v(7 DOWNTO 0);
214 SIGNAL sample_s : Samples(7 DOWNTO 0);
215 SIGNAL sample_val : STD_LOGIC;
216 SIGNAL ADC_nCS_sig : STD_LOGIC;
217 SIGNAL ADC_CLK_sig : STD_LOGIC;
218 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
219
220 SIGNAL bias_fail_sw_sig : STD_LOGIC;
221
222 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
223 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
224 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
225 -----------------------------------------------------------------------------
226
227
228 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
229 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
230 --
231 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
232 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
233 --
234 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
235 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
236
237
238 ---------------------------------------------------------------------------
239 --
240 ---------------------------------------------------------------------------
241 SIGNAL MEM_OUT_SM_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
242 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
243 SIGNAL MEM_OUT_SM_Full_pad : STD_LOGIC_VECTOR(1 DOWNTO 0);
244 SIGNAL MEM_OUT_SM_Full_pad_2 : STD_LOGIC;
245 SIGNAL MEM_OUT_SM_Empty_pad : STD_LOGIC_VECTOR(1 DOWNTO 0);
246
247
248
249 BEGIN -- beh
250
251 -----------------------------------------------------------------------------
252 -- CLK
253 -----------------------------------------------------------------------------
254
255 PROCESS(clk_50)
256 BEGIN
257 IF clk_50'EVENT AND clk_50 = '1' THEN
258 clk_50_s <= NOT clk_50_s;
259 END IF;
260 END PROCESS;
261
262 PROCESS(clk_50_s)
263 BEGIN
264 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
265 clk_25 <= NOT clk_25;
266 END IF;
267 END PROCESS;
268
269 PROCESS(clk_49)
270 BEGIN
271 IF clk_49'EVENT AND clk_49 = '1' THEN
272 clk_24 <= NOT clk_24;
273 END IF;
274 END PROCESS;
275
276 -----------------------------------------------------------------------------
277
278 PROCESS (clk_25, reset)
279 BEGIN -- PROCESS
280 IF reset = '0' THEN -- asynchronous reset (active low)
281 LED0 <= '0';
282 LED1 <= '0';
283 LED2 <= '0';
284 --IO1 <= '0';
285 --IO2 <= '1';
286 --IO3 <= '0';
287 --IO4 <= '0';
288 --IO5 <= '0';
289 --IO6 <= '0';
290 --IO7 <= '0';
291 --IO8 <= '0';
292 --IO9 <= '0';
293 --IO10 <= '0';
294 --IO11 <= '0';
295 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
296 LED0 <= '0';
297 LED1 <= '1';
298 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
299 --IO1 <= '1';
300 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
301 --IO3 <= ADC_SDO(0);
302 --IO4 <= ADC_SDO(1);
303 --IO5 <= ADC_SDO(2);
304 --IO6 <= ADC_SDO(3);
305 --IO7 <= ADC_SDO(4);
306 --IO8 <= ADC_SDO(5);
307 --IO9 <= ADC_SDO(6);
308 --IO10 <= ADC_SDO(7);
309 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
310 END IF;
311 END PROCESS;
312
313 PROCESS (clk_24, reset)
314 BEGIN -- PROCESS
315 IF reset = '0' THEN -- asynchronous reset (active low)
316 I00_s <= '0';
317 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
318 I00_s <= NOT I00_s;
319 END IF;
320 END PROCESS;
321 -- IO0 <= I00_s;
322
323 --UARTs
324 nCTS1 <= '1';
325 nCTS2 <= '1';
326 nDCD2 <= '1';
327
328 --EXT CONNECTOR
329
330 --SPACE WIRE
331
332 leon3_soc_1 : leon3_soc
333 GENERIC MAP (
334 fabtech => apa3e,
335 memtech => apa3e,
336 padtech => inferred,
337 clktech => inferred,
338 disas => 0,
339 dbguart => 0,
340 pclow => 2,
341 clk_freq => 25000,
342 NB_CPU => 1,
343 ENABLE_FPU => 1,
344 FPU_NETLIST => 0,
345 ENABLE_DSU => 1,
346 ENABLE_AHB_UART => 1,
347 ENABLE_APB_UART => 1,
348 ENABLE_IRQMP => 1,
349 ENABLE_GPT => 1,
350 NB_AHB_MASTER => NB_AHB_MASTER,
351 NB_AHB_SLAVE => NB_AHB_SLAVE,
352 NB_APB_SLAVE => NB_APB_SLAVE)
353 PORT MAP (
354 clk => clk_25,
355 reset => reset,
356 errorn => errorn,
357 ahbrxd => TXD1,
358 ahbtxd => RXD1,
359 urxd1 => TXD2,
360 utxd1 => RXD2,
361 address => SRAM_A,
362 data => SRAM_DQ,
363 nSRAM_BE0 => SRAM_nBE(0),
364 nSRAM_BE1 => SRAM_nBE(1),
365 nSRAM_BE2 => SRAM_nBE(2),
366 nSRAM_BE3 => SRAM_nBE(3),
367 nSRAM_WE => SRAM_nWE,
368 nSRAM_CE => SRAM_CE,
369 nSRAM_OE => SRAM_nOE,
370
371 apbi_ext => apbi_ext,
372 apbo_ext => apbo_ext,
373 ahbi_s_ext => ahbi_s_ext,
374 ahbo_s_ext => ahbo_s_ext,
375 ahbi_m_ext => ahbi_m_ext,
376 ahbo_m_ext => ahbo_m_ext);
377
378 -------------------------------------------------------------------------------
379 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
380 -------------------------------------------------------------------------------
381 apb_lfr_time_management_1 : apb_lfr_time_management
382 GENERIC MAP (
383 pindex => 6,
384 paddr => 6,
385 pmask => 16#fff#,
386 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
387 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
388 PORT MAP (
389 clk25MHz => clk_25,
390 clk24_576MHz => clk_24, -- 49.152MHz/2
391 resetn => reset,
392 grspw_tick => swno.tickout,
393 apbi => apbi_ext,
394 apbo => apbo_ext(6),
395 coarse_time => coarse_time,
396 fine_time => fine_time);
397
398 -----------------------------------------------------------------------
399 --- SpaceWire --------------------------------------------------------
400 -----------------------------------------------------------------------
401
402 SPW_EN <= '1';
403
404 spw_clk <= clk_50_s;
405 spw_rxtxclk <= spw_clk;
406 spw_rxclkn <= NOT spw_rxtxclk;
407
408 -- PADS for SPW1
409 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
410 PORT MAP (SPW_NOM_DIN, dtmp(0));
411 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
412 PORT MAP (SPW_NOM_SIN, stmp(0));
413 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
414 PORT MAP (SPW_NOM_DOUT, swno.d(0));
415 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
416 PORT MAP (SPW_NOM_SOUT, swno.s(0));
417 -- PADS FOR SPW2
418 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
419 PORT MAP (SPW_RED_SIN, dtmp(1));
420 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
421 PORT MAP (SPW_RED_DIN, stmp(1));
422 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
423 PORT MAP (SPW_RED_DOUT, swno.d(1));
424 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
425 PORT MAP (SPW_RED_SOUT, swno.s(1));
426
427 -- GRSPW PHY
428 --spw1_input: if CFG_SPW_GRSPW = 1 generate
429 spw_inputloop : FOR j IN 0 TO 1 GENERATE
430 spw_phy0 : grspw_phy
431 GENERIC MAP(
432 tech => apa3e,
433 rxclkbuftype => 1,
434 scantest => 0)
435 PORT MAP(
436 rxrst => swno.rxrst,
437 di => dtmp(j),
438 si => stmp(j),
439 rxclko => spw_rxclk(j),
440 do => swni.d(j),
441 ndo => swni.nd(j*5+4 DOWNTO j*5),
442 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
443 END GENERATE spw_inputloop;
444
445 -- SPW core
446 sw0 : grspwm GENERIC MAP(
447 tech => apa3e,
448 hindex => 1,
449 pindex => 5,
450 paddr => 5,
451 pirq => 11,
452 sysfreq => 25000, -- CPU_FREQ
453 rmap => 1,
454 rmapcrc => 1,
455 fifosize1 => 16,
456 fifosize2 => 16,
457 rxclkbuftype => 1,
458 rxunaligned => 0,
459 rmapbufs => 4,
460 ft => 0,
461 netlist => 0,
462 ports => 2,
463 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
464 memtech => apa3e,
465 destkey => 2,
466 spwcore => 1
467 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
468 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
469 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
470 )
471 PORT MAP(reset, clk_25, spw_rxclk(0),
472 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
473 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
474 swni, swno);
475
476 swni.tickin <= '0';
477 swni.rmapen <= '1';
478 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
479 swni.tickinraw <= '0';
480 swni.timein <= (OTHERS => '0');
481 swni.dcrstval <= (OTHERS => '0');
482 swni.timerrstval <= (OTHERS => '0');
483
484 -------------------------------------------------------------------------------
485 -- LFR ------------------------------------------------------------------------
486 -------------------------------------------------------------------------------
487
488 lpp_lfr_apbreg_1 : lpp_lfr_apbreg_tb
489 GENERIC MAP (
490 pindex => 15,
491 paddr => 15,
492 pmask => 16#fff#)
493 PORT MAP (
494 HCLK => clk_25,
495 HRESETn => reset,
496 apbi => apbi_ext,
497 apbo => apbo_ext(15),
498
499 sample_f0_wen => sample_f0_wen,
500 sample_f1_wen => sample_f1_wen,
501 sample_f2_wen => sample_f2_wen,
502 sample_f0_wdata => sample_f0_wdata,
503 sample_f1_wdata => sample_f1_wdata,
504 sample_f2_wdata => sample_f2_wdata,
505
506 MEM_OUT_SM_ren => MEM_OUT_SM_ren ,
507 MEM_OUT_SM_Data_out => MEM_OUT_SM_Data_out ,
508 MEM_OUT_SM_Full => MEM_OUT_SM_Full_pad ,
509 MEM_OUT_SM_Full_2 => MEM_OUT_SM_Full_pad_2 ,
510 MEM_OUT_SM_Empty => MEM_OUT_SM_Empty_pad);
511
512 lpp_lfr_ms_tb_1 : lpp_lfr_ms_tb
513 GENERIC MAP (
514 Mem_use =>use_RAM)
515 PORT MAP (
516 clk => clk_25,
517 rstn => reset,
518 sample_f0_wen => sample_f0_wen,
519 sample_f0_wdata => sample_f0_wdata,
520 sample_f1_wen => sample_f1_wen,
521 sample_f1_wdata => sample_f1_wdata,
522 sample_f2_wen => sample_f2_wen,
523 sample_f2_wdata => sample_f2_wdata,
524
525 MEM_OUT_SM_Read => MEM_OUT_SM_ren ,
526 MEM_OUT_SM_Data_out => MEM_OUT_SM_Data_out ,
527 MEM_OUT_SM_Full_pad => MEM_OUT_SM_Full_pad ,
528 MEM_OUT_SM_Full_pad_2 => MEM_OUT_SM_Full_pad_2 ,
529 MEM_OUT_SM_Empty_pad => MEM_OUT_SM_Empty_pad,
530
531 error_input_fifo_write => OPEN,
532 observation_vector_0 => observation_vector_0,
533 observation_vector_1 => observation_vector_1);
534
535 -----------------------------------------------------------------------------
536
537
538
539
540
541 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
542 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
543 END GENERATE all_sample;
544
545
546
547 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
548 GENERIC MAP(
549 ChannelCount => 8,
550 SampleNbBits => 14,
551 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
552 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
553 PORT MAP (
554 -- CONV
555 cnv_clk => clk_24,
556 cnv_rstn => reset,
557 cnv => ADC_nCS_sig,
558 -- DATA
559 clk => clk_25,
560 rstn => reset,
561 sck => ADC_CLK_sig,
562 sdo => ADC_SDO_sig,
563 -- SAMPLE
564 sample => sample,
565 sample_val => sample_val);
566
567 --IO10 <= ADC_SDO_sig(5);
568 --IO9 <= ADC_SDO_sig(4);
569 --IO8 <= ADC_SDO_sig(3);
570
571 ADC_nCS <= ADC_nCS_sig;
572 ADC_CLK <= ADC_CLK_sig;
573 ADC_SDO_sig <= ADC_SDO;
574
575 ----------------------------------------------------------------------
576 --- GPIO -----------------------------------------------------------
577 ----------------------------------------------------------------------
578
579 grgpio0 : grgpio
580 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
581 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
582
583 --pio_pad_0 : iopad
584 -- GENERIC MAP (tech => CFG_PADTECH)
585 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
586 --pio_pad_1 : iopad
587 -- GENERIC MAP (tech => CFG_PADTECH)
588 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
589 --pio_pad_2 : iopad
590 -- GENERIC MAP (tech => CFG_PADTECH)
591 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
592 --pio_pad_3 : iopad
593 -- GENERIC MAP (tech => CFG_PADTECH)
594 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
595 --pio_pad_4 : iopad
596 -- GENERIC MAP (tech => CFG_PADTECH)
597 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
598 --pio_pad_5 : iopad
599 -- GENERIC MAP (tech => CFG_PADTECH)
600 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
601 --pio_pad_6 : iopad
602 -- GENERIC MAP (tech => CFG_PADTECH)
603 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
604 --pio_pad_7 : iopad
605 -- GENERIC MAP (tech => CFG_PADTECH)
606 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
607
608 PROCESS (clk_25, reset)
609 BEGIN -- PROCESS
610 IF reset = '0' THEN -- asynchronous reset (active low)
611 IO0 <= '0';
612 IO1 <= '0';
613 IO2 <= '0';
614 IO3 <= '0';
615 IO4 <= '0';
616 IO5 <= '0';
617 IO6 <= '0';
618 IO7 <= '0';
619 IO8 <= '0';
620 IO9 <= '0';
621 IO10 <= '0';
622 IO11 <= '0';
623 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
624 CASE gpioo.dout(2 DOWNTO 0) IS
625 WHEN "011" =>
626 IO0 <= observation_reg(0);
627 IO1 <= observation_reg(1);
628 IO2 <= observation_reg(2);
629 IO3 <= observation_reg(3);
630 IO4 <= observation_reg(4);
631 IO5 <= observation_reg(5);
632 IO6 <= observation_reg(6);
633 IO7 <= observation_reg(7);
634 IO8 <= observation_reg(8);
635 IO9 <= observation_reg(9);
636 IO10 <= observation_reg(10);
637 IO11 <= observation_reg(11);
638 WHEN "001" =>
639 IO0 <= observation_reg(0 + 12);
640 IO1 <= observation_reg(1 + 12);
641 IO2 <= observation_reg(2 + 12);
642 IO3 <= observation_reg(3 + 12);
643 IO4 <= observation_reg(4 + 12);
644 IO5 <= observation_reg(5 + 12);
645 IO6 <= observation_reg(6 + 12);
646 IO7 <= observation_reg(7 + 12);
647 IO8 <= observation_reg(8 + 12);
648 IO9 <= observation_reg(9 + 12);
649 IO10 <= observation_reg(10 + 12);
650 IO11 <= observation_reg(11 + 12);
651 WHEN "010" =>
652 IO0 <= observation_reg(0 + 12 + 12);
653 IO1 <= observation_reg(1 + 12 + 12);
654 IO2 <= observation_reg(2 + 12 + 12);
655 IO3 <= observation_reg(3 + 12 + 12);
656 IO4 <= observation_reg(4 + 12 + 12);
657 IO5 <= observation_reg(5 + 12 + 12);
658 IO6 <= observation_reg(6 + 12 + 12);
659 IO7 <= observation_reg(7 + 12 + 12);
660 IO8 <= ADC_SDO(0) OR ADC_SDO(1) OR ADC_SDO(2);
661 IO9 <= ADC_SDO(3) OR ADC_SDO(4) OR ADC_SDO(5);
662 IO10 <= ADC_SDO(6) OR ADC_SDO(7) ;
663 IO11 <= '0';
664 WHEN "000" =>
665 IO0 <= observation_vector_0(0);
666 IO1 <= observation_vector_0(1);
667 IO2 <= observation_vector_0(2);
668 IO3 <= observation_vector_0(3);
669 IO4 <= observation_vector_0(4);
670 IO5 <= observation_vector_0(5);
671 IO6 <= observation_vector_0(6);
672 IO7 <= observation_vector_0(7);
673 IO8 <= observation_vector_0(8);
674 IO9 <= observation_vector_0(9);
675 IO10 <= observation_vector_0(10);
676 IO11 <= observation_vector_0(11);
677 WHEN "100" =>
678 IO0 <= observation_vector_1(0);
679 IO1 <= observation_vector_1(1);
680 IO2 <= observation_vector_1(2);
681 IO3 <= observation_vector_1(3);
682 IO4 <= observation_vector_1(4);
683 IO5 <= observation_vector_1(5);
684 IO6 <= observation_vector_1(6);
685 IO7 <= observation_vector_1(7);
686 IO8 <= observation_vector_1(8);
687 IO9 <= observation_vector_1(9);
688 IO10 <= observation_vector_1(10);
689 IO11 <= observation_vector_1(11);
690 WHEN OTHERS => NULL;
691 END CASE;
692
693 END IF;
694 END PROCESS;
695
696 END beh; No newline at end of file
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1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=MINI_LFR_top
5 BOARD=MINI-LFR
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 EFFORT=high
11 XSTOPT=
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES= MINI_LFR_top.vhd lpp_lfr_apbreg.vhd lpp_lfr_ms_validation.vhd
14
15 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
16 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
17 CLEAN=soft-clean
18
19 TECHLIBS = proasic3e
20
21 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
22 tmtc openchip hynix ihp gleichmann micron usbhc
23
24 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
25 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
26 ./amba_lcd_16x2_ctrlr \
27 ./general_purpose/lpp_AMR \
28 ./general_purpose/lpp_balise \
29 ./general_purpose/lpp_delay \
30 ./lpp_bootloader \
31 ./lpp_cna \
32 ./lpp_uart \
33 ./lpp_usb \
34 ./dsp/lpp_fft_rtax \
35 ./lpp_sim/CY7C1061DV33 \
36
37 FILESKIP =i2cmst.vhd \
38 APB_MULTI_DIODE.vhd \
39 APB_SIMPLE_DIODE.vhd \
40 Top_MatrixSpec.vhd \
41 APB_FFT.vhd
42
43 include $(GRLIB)/bin/Makefile
44 include $(GRLIB)/software/leon3/Makefile
45
46 ################## project specific targets ##########################
47
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4
5 LIBRARY lpp;
6 USE lpp.lpp_memory.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.spectral_matrix_package.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
10 USE lpp.lpp_Header.ALL;
11 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_fft.ALL;
15 USE lpp.fft_components.ALL;
16
17 ENTITY lpp_lfr_ms IS
18 GENERIC (
19 Mem_use : INTEGER := use_RAM
20 );
21 PORT (
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24
25 );
26 END;
27
28 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
29
30 BEGIN
31
32 -----------------------------------------------------------------------------
33
34 lppFIFOxN_f0_a : lppFIFOxN
35 GENERIC MAP (
36 tech => 0,
37 Mem_use => Mem_use,
38 Data_sz => 16,
39 Addr_sz => 8,
40 FifoCnt => 5)
41 PORT MAP (
42 clk => clk,
43 rstn => rstn,
44
45 ReUse => (OTHERS => '0'),
46
47 wen => sample_f0_A_wen,
48 wdata => sample_f0_wdata,
49
50 ren => sample_f0_A_ren,
51 rdata => sample_f0_A_rdata,
52
53 empty => sample_f0_A_empty,
54 full => sample_f0_A_full,
55 almost_full => OPEN);
56
57 -----------------------------------------------------------------------------
58
59 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
60 PORT MAP (
61 clk => clk,
62 rstn => rstn,
63 sample_valid => sample_valid, -- WRITE in
64 fft_read => fft_read, -- READ in
65 sample_data => sample_data, -- WRITE in
66 sample_load => sample_load, -- WRITE out
67 fft_pong => fft_pong, -- READ out
68 fft_data_im => fft_data_im, -- READ out
69 fft_data_re => fft_data_re, -- READ out
70 fft_data_valid => fft_data_valid, -- READ out
71 fft_ready => fft_ready); -- READ out
72
73 -----------------------------------------------------------------------------
74
75 END Behavioral;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
31 USE lpp.lpp_lfr_pkg.ALL;
32 --USE lpp.lpp_amba.ALL;
33 USE lpp.apb_devices_list.ALL;
34 USE lpp.lpp_memory.ALL;
35 LIBRARY techmap;
36 USE techmap.gencomp.ALL;
37
38 ENTITY lpp_lfr_apbreg_tb IS
39 GENERIC (
40 pindex : INTEGER := 4;
41 paddr : INTEGER := 4;
42 pmask : INTEGER := 16#fff#);
43 PORT (
44 -- AMBA AHB system signals
45 HCLK : IN STD_ULOGIC;
46 HRESETn : IN STD_ULOGIC;
47
48 -- AMBA APB Slave Interface
49 apbi : IN apb_slv_in_type;
50 apbo : OUT apb_slv_out_type;
51
52 ---------------------------------------------------------------------------
53 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
54 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
55 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
56
57 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
58 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
59 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
60 ---------------------------------------------------------------------------
61 MEM_OUT_SM_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
62 MEM_OUT_SM_Data_out : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
63 MEM_OUT_SM_Full : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
64 MEM_OUT_SM_Full_2 : IN STD_LOGIC;
65 MEM_OUT_SM_Empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
66 ---------------------------------------------------------------------------
67 );
68
69 END lpp_lfr_apbreg_tb;
70
71 ARCHITECTURE beh OF lpp_lfr_apbreg_tb IS
72
73 CONSTANT REVISION : INTEGER := 1;
74
75 CONSTANT pconfig : apb_config_type := (
76 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, 1),
77 1 => apb_iobar(paddr, pmask));
78
79 TYPE reg_debug_fft IS RECORD
80 in_data_f0 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
81 in_data_f1 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
82 in_data_f2 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
83
84 in_wen_f0 : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 in_wen_f1 : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 in_wen_f2 : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 --
88 out_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
89 END RECORD;
90 SIGNAL reg_ftt : reg_debug_fft;
91
92 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
93
94 BEGIN -- beh
95
96 ---------------------------------------------------------------------------
97 sample_f0_wen <= reg_ftt.in_wen_f0;
98 sample_f1_wen <= reg_ftt.in_wen_f1;
99 sample_f2_wen <= reg_ftt.in_wen_f2;
100
101 sample_f0_wdata <= reg_ftt.in_data_f0;
102 sample_f1_wdata <= reg_ftt.in_data_f1;
103 sample_f2_wdata <= reg_ftt.in_data_f2;
104 ---------------------------------------------------------------------------
105 MEM_OUT_SM_ren <= reg_ftt.out_ren;
106 ---------------------------------------------------------------------------
107
108 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
109 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
110 BEGIN
111 IF HRESETn = '0' THEN
112
113 reg_ftt.in_data_f0 <= (OTHERS => '0');
114 reg_ftt.in_data_f1 <= (OTHERS => '0');
115 reg_ftt.in_data_f2 <= (OTHERS => '0');
116
117 reg_ftt.in_wen_f0 <= (OTHERS => '1');
118 reg_ftt.in_wen_f1 <= (OTHERS => '1');
119 reg_ftt.in_wen_f2 <= (OTHERS => '1');
120
121 reg_ftt.out_ren <= (OTHERS => '1');
122
123 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
124
125
126 reg_ftt.in_wen_f0 <= (OTHERS => '1');
127 reg_ftt.in_wen_f1 <= (OTHERS => '1');
128 reg_ftt.in_wen_f2 <= (OTHERS => '1');
129 reg_ftt.out_ren <= (OTHERS => '1');
130
131 paddr := "000000";
132 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
133 prdata <= (OTHERS => '0');
134 IF apbi.psel(pindex) = '1' THEN
135 -- APB DMA READ --
136 CASE paddr(7 DOWNTO 2) IS
137 --0
138 WHEN "000000" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f0(31 DOWNTO 0);
139 WHEN "000001" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f0(63 DOWNTO 32);
140 WHEN "000010" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f0(79 DOWNTO 64);
141 WHEN "000011" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f0;
142
143 WHEN "000100" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f1(31 DOWNTO 0);
144 WHEN "000101" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f1(63 DOWNTO 32);
145 WHEN "000110" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f1(79 DOWNTO 64);
146 WHEN "000111" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f1;
147
148 WHEN "001000" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f2(31 DOWNTO 0);
149 WHEN "001001" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f2(63 DOWNTO 32);
150 WHEN "001010" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f2(79 DOWNTO 64);
151 WHEN "001011" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f2;
152
153 WHEN "001100" => prdata(31 DOWNTO 0) <= MEM_OUT_SM_Data_out(32*1-1 DOWNTO 32*0);
154 WHEN "001101" => prdata(31 DOWNTO 0) <= MEM_OUT_SM_Data_out(32*2-1 DOWNTO 32*1);
155
156 WHEN "001110" => prdata(1 DOWNTO 0) <= reg_ftt.out_ren;
157 prdata(3 DOWNTO 2) <= MEM_OUT_SM_Full;
158 prdata(5 DOWNTO 4) <= MEM_OUT_SM_Empty;
159 prdata(6) <= MEM_OUT_SM_Full_2;
160 WHEN OTHERS => NULL;
161
162 END CASE;
163 IF (apbi.pwrite AND apbi.penable) = '1' THEN
164 -- APB DMA WRITE --
165 CASE paddr(7 DOWNTO 2) IS
166 WHEN "000000" => reg_ftt.in_data_f0(31 DOWNTO 0) <= apbi.pwdata;
167 WHEN "000001" => reg_ftt.in_data_f0(63 DOWNTO 32) <= apbi.pwdata;
168 WHEN "000010" => reg_ftt.in_data_f0(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0);
169 WHEN "000011" => reg_ftt.in_wen_f0 <= apbi.pwdata(4 DOWNTO 0);
170
171 WHEN "000100" => reg_ftt.in_data_f1(31 DOWNTO 0) <= apbi.pwdata;
172 WHEN "000101" => reg_ftt.in_data_f1(63 DOWNTO 32) <= apbi.pwdata;
173 WHEN "000110" => reg_ftt.in_data_f1(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0);
174 WHEN "000111" => reg_ftt.in_wen_f1 <= apbi.pwdata(4 DOWNTO 0);
175
176 WHEN "001000" => reg_ftt.in_data_f2(31 DOWNTO 0) <= apbi.pwdata;
177 WHEN "001001" => reg_ftt.in_data_f2(63 DOWNTO 32) <= apbi.pwdata;
178 WHEN "001010" => reg_ftt.in_data_f2(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0);
179 WHEN "001011" => reg_ftt.in_wen_f2 <= apbi.pwdata(4 DOWNTO 0);
180
181 WHEN "001110" => reg_ftt.out_ren <= apbi.pwdata(1 DOWNTO 0);
182
183 WHEN OTHERS => NULL;
184 END CASE;
185 END IF;
186 END IF;
187
188 END IF;
189 END PROCESS lpp_lfr_apbreg;
190
191 apbo.pindex <= pindex;
192 apbo.pconfig <= pconfig;
193 apbo.prdata <= prdata;
194
195 END beh; No newline at end of file
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4
5 LIBRARY lpp;
6 USE lpp.lpp_memory.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.spectral_matrix_package.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
10 USE lpp.lpp_Header.ALL;
11 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_fft.ALL;
15 USE lpp.fft_components.ALL;
16
17 ENTITY lpp_lfr_ms_tb IS
18 GENERIC (
19 Mem_use : INTEGER := use_RAM
20 );
21 PORT (
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24
25 ---------------------------------------------------------------------------
26 --
27 ---------------------------------------------------------------------------
28 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
30 --
31 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
33 --
34 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36
37
38 ---------------------------------------------------------------------------
39 --
40 ---------------------------------------------------------------------------
41 MEM_OUT_SM_Read : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
42 MEM_OUT_SM_Data_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
43 MEM_OUT_SM_Full_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
44 MEM_OUT_SM_Full_pad_2 : OUT STD_LOGIC;
45 MEM_OUT_SM_Empty_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
46
47 ---------------------------------------------------------------------------
48 --
49 ---------------------------------------------------------------------------
50 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
51 --
52 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
53 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
54 );
55 END;
56
57 ARCHITECTURE Behavioral OF lpp_lfr_ms_tb IS
58
59 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
60 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
61 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
62 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
63 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
64
65 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
66 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
67 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
68 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
69 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
70
71 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
72 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
73 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
74 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
75
76 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
77
78 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
79 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
80 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
81 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
82
83 SIGNAL error_wen_f0 : STD_LOGIC;
84 SIGNAL error_wen_f1 : STD_LOGIC;
85 SIGNAL error_wen_f2 : STD_LOGIC;
86
87 SIGNAL one_sample_f1_full : STD_LOGIC;
88 SIGNAL one_sample_f1_wen : STD_LOGIC;
89 SIGNAL one_sample_f2_full : STD_LOGIC;
90 SIGNAL one_sample_f2_wen : STD_LOGIC;
91
92 -----------------------------------------------------------------------------
93 -- FSM / SWITCH SELECT CHANNEL
94 -----------------------------------------------------------------------------
95 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
96 SIGNAL state_fsm_select_channel : fsm_select_channel;
97 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
98
99 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
100 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
101 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
102 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
103
104 -----------------------------------------------------------------------------
105 -- FSM LOAD FFT
106 -----------------------------------------------------------------------------
107 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
108 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
109 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
110
111 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
112 SIGNAL sample_load : STD_LOGIC;
113 SIGNAL sample_valid : STD_LOGIC;
114 SIGNAL sample_valid_r : STD_LOGIC;
115 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
116
117
118 -----------------------------------------------------------------------------
119 -- FFT
120 -----------------------------------------------------------------------------
121 SIGNAL fft_read : STD_LOGIC;
122 SIGNAL fft_pong : STD_LOGIC;
123 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
124 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
125 SIGNAL fft_data_valid : STD_LOGIC;
126 SIGNAL fft_ready : STD_LOGIC;
127 -----------------------------------------------------------------------------
128 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
129 -----------------------------------------------------------------------------
130 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
131 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
132 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
133 SIGNAL current_fifo_empty : STD_LOGIC;
134 SIGNAL current_fifo_locked : STD_LOGIC;
135 SIGNAL current_fifo_full : STD_LOGIC;
136 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
137
138 -----------------------------------------------------------------------------
139 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
140 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
141 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
142 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
143 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
144 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
145 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
146 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
147 -----------------------------------------------------------------------------
148 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
149 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
151
152 SIGNAL SM_correlation_start : STD_LOGIC;
153 SIGNAL SM_correlation_auto : STD_LOGIC;
154 SIGNAL SM_correlation_done : STD_LOGIC;
155 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
156 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
157 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
158 SIGNAL SM_correlation_begin : STD_LOGIC;
159
160 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
161 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
162 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
163
164 SIGNAL current_matrix_write : STD_LOGIC;
165 SIGNAL current_matrix_wait_empty : STD_LOGIC;
166 -----------------------------------------------------------------------------
167 SIGNAL fifo_0_ready : STD_LOGIC;
168 SIGNAL fifo_1_ready : STD_LOGIC;
169 SIGNAL fifo_ongoing : STD_LOGIC;
170
171 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
172 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
173 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
175 -----------------------------------------------------------------------------
176 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
177 -- SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
178 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
179 -- SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
180 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
181 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
182
183 -----------------------------------------------------------------------------
184 -- TIME REG & INFOs
185 -----------------------------------------------------------------------------
186 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
187
188 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
189 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
190 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
191 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
192
193 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
194 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
195 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
196 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
197
198 --SIGNAL time_update_f0_A : STD_LOGIC;
199 --SIGNAL time_update_f0_B : STD_LOGIC;
200 --SIGNAL time_update_f1 : STD_LOGIC;
201 --SIGNAL time_update_f2 : STD_LOGIC;
202 --
203 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
204 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
205 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
206
207 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
208 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
209 SIGNAL status_component_fifo_0_end : STD_LOGIC;
210 SIGNAL status_component_fifo_1_end : STD_LOGIC;
211 -----------------------------------------------------------------------------
212 SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
213
214 SIGNAL fft_ready_reg : STD_LOGIC;
215 SIGNAL fft_ready_rising_down : STD_LOGIC;
216
217 SIGNAL sample_load_reg : STD_LOGIC;
218 SIGNAL sample_load_rising_down : STD_LOGIC;
219
220 -----------------------------------------------------------------------------
221 SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0);
222 SIGNAL sample_f1_wen_head_in : STD_LOGIC;
223 SIGNAL sample_f1_wen_head_out : STD_LOGIC;
224 SIGNAL sample_f1_full_head_in : STD_LOGIC;
225 SIGNAL sample_f1_full_head_out : STD_LOGIC;
226 SIGNAL sample_f1_empty_head_in : STD_LOGIC;
227
228 SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
229
230 BEGIN
231
232
233 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
234
235
236 switch_f0_inst : spectral_matrix_switch_f0
237 PORT MAP (
238 clk => clk,
239 rstn => rstn,
240
241 sample_wen => sample_f0_wen,
242
243 fifo_A_empty => sample_f0_A_empty,
244 fifo_A_full => sample_f0_A_full,
245 fifo_A_wen => sample_f0_A_wen,
246
247 fifo_B_empty => sample_f0_B_empty,
248 fifo_B_full => sample_f0_B_full,
249 fifo_B_wen => sample_f0_B_wen,
250
251 error_wen => error_wen_f0); -- TODO
252
253 -----------------------------------------------------------------------------
254 -- FIFO IN
255 -----------------------------------------------------------------------------
256 lppFIFOxN_f0_a : lppFIFOxN
257 GENERIC MAP (
258 tech => 0,
259 Mem_use => Mem_use,
260 Data_sz => 16,
261 Addr_sz => 8,
262 FifoCnt => 5)
263 PORT MAP (
264 clk => clk,
265 rstn => rstn,
266
267 ReUse => (OTHERS => '0'),
268
269 wen => sample_f0_A_wen,
270 wdata => sample_f0_wdata,
271
272 ren => sample_f0_A_ren,
273 rdata => sample_f0_A_rdata,
274
275 empty => sample_f0_A_empty,
276 full => sample_f0_A_full,
277 almost_full => OPEN);
278
279 lppFIFOxN_f0_b : lppFIFOxN
280 GENERIC MAP (
281 tech => 0,
282 Mem_use => Mem_use,
283 Data_sz => 16,
284 Addr_sz => 8,
285 FifoCnt => 5)
286 PORT MAP (
287 clk => clk,
288 rstn => rstn,
289
290 ReUse => (OTHERS => '0'),
291
292 wen => sample_f0_B_wen,
293 wdata => sample_f0_wdata,
294 ren => sample_f0_B_ren,
295 rdata => sample_f0_B_rdata,
296 empty => sample_f0_B_empty,
297 full => sample_f0_B_full,
298 almost_full => OPEN);
299
300 -----------------------------------------------------------------------------
301 -- sample_f1_wen in
302 -- sample_f1_wdata in
303 -- sample_f1_full OUT
304
305 sample_f1_wen_head_in <= '0' WHEN sample_f1_wen = "00000" ELSE '1';
306 sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1';
307 sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
308
309 lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
310 PORT MAP (
311 clk => clk,
312 rstn => rstn,
313 in_wen => sample_f1_wen_head_in,
314 in_data => sample_f1_wdata,
315 in_full => sample_f1_full_head_in,
316 in_empty => sample_f1_empty_head_in,
317 out_wen => sample_f1_wen_head_out,
318 out_data => sample_f1_wdata_head,
319 out_full => sample_f1_full_head_out);
320
321 sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
322
323
324 lppFIFOxN_f1 : lppFIFOxN
325 GENERIC MAP (
326 tech => 0,
327 Mem_use => Mem_use,
328 Data_sz => 16,
329 Addr_sz => 8,
330 FifoCnt => 5)
331 PORT MAP (
332 clk => clk,
333 rstn => rstn,
334
335 ReUse => (OTHERS => '0'),
336
337 wen => sample_f1_wen_head,
338 wdata => sample_f1_wdata_head,
339 ren => sample_f1_ren,
340 rdata => sample_f1_rdata,
341 empty => sample_f1_empty,
342 full => sample_f1_full,
343 almost_full => sample_f1_almost_full);
344
345
346 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
347
348 PROCESS (clk, rstn)
349 BEGIN -- PROCESS
350 IF rstn = '0' THEN -- asynchronous reset (active low)
351 one_sample_f1_full <= '0';
352 error_wen_f1 <= '0';
353 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
354 IF sample_f1_full_head_out = '0' THEN
355 one_sample_f1_full <= '0';
356 ELSE
357 one_sample_f1_full <= '1';
358 END IF;
359 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
360 END IF;
361 END PROCESS;
362
363 -----------------------------------------------------------------------------
364
365
366 lppFIFOxN_f2 : lppFIFOxN
367 GENERIC MAP (
368 tech => 0,
369 Mem_use => Mem_use,
370 Data_sz => 16,
371 Addr_sz => 8,
372 FifoCnt => 5)
373 PORT MAP (
374 clk => clk,
375 rstn => rstn,
376
377 ReUse => (OTHERS => '0'),
378
379 wen => sample_f2_wen,
380 wdata => sample_f2_wdata,
381 ren => sample_f2_ren,
382 rdata => sample_f2_rdata,
383 empty => sample_f2_empty,
384 full => sample_f2_full,
385 almost_full => OPEN);
386
387
388 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
389
390 PROCESS (clk, rstn)
391 BEGIN -- PROCESS
392 IF rstn = '0' THEN -- asynchronous reset (active low)
393 one_sample_f2_full <= '0';
394 error_wen_f2 <= '0';
395 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
396 IF sample_f2_full = "00000" THEN
397 one_sample_f2_full <= '0';
398 ELSE
399 one_sample_f2_full <= '1';
400 END IF;
401 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
402 END IF;
403 END PROCESS;
404
405 -----------------------------------------------------------------------------
406 -- FSM SELECT CHANNEL
407 -----------------------------------------------------------------------------
408 PROCESS (clk, rstn)
409 BEGIN
410 IF rstn = '0' THEN
411 state_fsm_select_channel <= IDLE;
412 ELSIF clk'EVENT AND clk = '1' THEN
413 CASE state_fsm_select_channel IS
414 WHEN IDLE =>
415 IF sample_f1_full = "11111" THEN
416 state_fsm_select_channel <= SWITCH_F1;
417 ELSIF sample_f1_almost_full = "00000" THEN
418 IF sample_f0_A_full = "11111" THEN
419 state_fsm_select_channel <= SWITCH_F0_A;
420 ELSIF sample_f0_B_full = "11111" THEN
421 state_fsm_select_channel <= SWITCH_F0_B;
422 ELSIF sample_f2_full = "11111" THEN
423 state_fsm_select_channel <= SWITCH_F2;
424 END IF;
425 END IF;
426
427 WHEN SWITCH_F0_A =>
428 IF sample_f0_A_empty = "11111" THEN
429 state_fsm_select_channel <= IDLE;
430 END IF;
431 WHEN SWITCH_F0_B =>
432 IF sample_f0_B_empty = "11111" THEN
433 state_fsm_select_channel <= IDLE;
434 END IF;
435 WHEN SWITCH_F1 =>
436 IF sample_f1_empty = "11111" THEN
437 state_fsm_select_channel <= IDLE;
438 END IF;
439 WHEN SWITCH_F2 =>
440 IF sample_f2_empty = "11111" THEN
441 state_fsm_select_channel <= IDLE;
442 END IF;
443 WHEN OTHERS => NULL;
444 END CASE;
445
446 END IF;
447 END PROCESS;
448
449 PROCESS (clk, rstn)
450 BEGIN
451 IF rstn = '0' THEN
452 pre_state_fsm_select_channel <= IDLE;
453 ELSIF clk'EVENT AND clk = '1' THEN
454 pre_state_fsm_select_channel <= state_fsm_select_channel;
455 END IF;
456 END PROCESS;
457
458
459 -----------------------------------------------------------------------------
460 -- SWITCH SELECT CHANNEL
461 -----------------------------------------------------------------------------
462 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
463 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
464 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
465 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
466 (OTHERS => '1');
467
468 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
469 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
470 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
471 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
472 (OTHERS => '0');
473
474 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
475 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
476 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
477 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
478
479
480 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
481 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
482 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
483 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
484
485
486 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
487 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
488 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
489 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
490
491 -----------------------------------------------------------------------------
492 -- FSM LOAD FFT
493 -----------------------------------------------------------------------------
494
495 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
496 sample_ren_s WHEN sample_load = '1' ELSE
497 (OTHERS => '1');
498
499 PROCESS (clk, rstn)
500 BEGIN
501 IF rstn = '0' THEN
502 sample_ren_s <= (OTHERS => '1');
503 state_fsm_load_FFT <= IDLE;
504 status_MS_input <= (OTHERS => '0');
505 --next_state_fsm_load_FFT <= IDLE;
506 --sample_valid <= '0';
507 ELSIF clk'EVENT AND clk = '1' THEN
508 CASE state_fsm_load_FFT IS
509 WHEN IDLE =>
510 --sample_valid <= '0';
511 sample_ren_s <= (OTHERS => '1');
512 IF sample_full = "11111" AND sample_load = '1' THEN
513 state_fsm_load_FFT <= FIFO_1;
514 status_MS_input <= status_channel;
515 END IF;
516
517 WHEN FIFO_1 =>
518 sample_ren_s <= "1111" & NOT(sample_load);
519 IF sample_empty(0) = '1' THEN
520 sample_ren_s <= (OTHERS => '1');
521 state_fsm_load_FFT <= FIFO_2;
522 END IF;
523
524 WHEN FIFO_2 =>
525 sample_ren_s <= "111" & NOT(sample_load) & '1';
526 IF sample_empty(1) = '1' THEN
527 sample_ren_s <= (OTHERS => '1');
528 state_fsm_load_FFT <= FIFO_3;
529 END IF;
530
531 WHEN FIFO_3 =>
532 sample_ren_s <= "11" & NOT(sample_load) & "11";
533 IF sample_empty(2) = '1' THEN
534 sample_ren_s <= (OTHERS => '1');
535 state_fsm_load_FFT <= FIFO_4;
536 END IF;
537
538 WHEN FIFO_4 =>
539 sample_ren_s <= '1' & NOT(sample_load) & "111";
540 IF sample_empty(3) = '1' THEN
541 sample_ren_s <= (OTHERS => '1');
542 state_fsm_load_FFT <= FIFO_5;
543 END IF;
544
545 WHEN FIFO_5 =>
546 sample_ren_s <= NOT(sample_load) & "1111";
547 IF sample_empty(4) = '1' THEN
548 sample_ren_s <= (OTHERS => '1');
549 state_fsm_load_FFT <= IDLE;
550 END IF;
551 WHEN OTHERS => NULL;
552 END CASE;
553 END IF;
554 END PROCESS;
555
556 PROCESS (clk, rstn)
557 BEGIN
558 IF rstn = '0' THEN
559 sample_valid_r <= '0';
560 next_state_fsm_load_FFT <= IDLE;
561 ELSIF clk'EVENT AND clk = '1' THEN
562 next_state_fsm_load_FFT <= state_fsm_load_FFT;
563 IF sample_ren_s = "11111" THEN
564 sample_valid_r <= '0';
565 ELSE
566 sample_valid_r <= '1';
567 END IF;
568 END IF;
569 END PROCESS;
570
571 sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
572
573 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
574 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
575 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
576 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
577 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
578
579 -----------------------------------------------------------------------------
580 -- FFT
581 -----------------------------------------------------------------------------
582 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
583 PORT MAP (
584 clk => clk,
585 rstn => rstn,
586 sample_valid => sample_valid,
587 fft_read => fft_read,
588 sample_data => sample_data,
589 sample_load => sample_load,
590 fft_pong => fft_pong,
591 fft_data_im => fft_data_im,
592 fft_data_re => fft_data_re,
593 fft_data_valid => fft_data_valid,
594 fft_ready => fft_ready);
595
596 observation_vector_0(11 DOWNTO 0) <= "000" & --11 10
597 fft_ongoing_counter & --9 8
598 sample_load_rising_down & --7
599 fft_ready_rising_down & --6
600 fft_ready & --5
601 fft_data_valid & --4
602 fft_pong & --3
603 sample_load & --2
604 fft_read & --1
605 sample_valid; --0
606
607 -----------------------------------------------------------------------------
608 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
609 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
610
611 PROCESS (clk, rstn)
612 BEGIN
613 IF rstn = '0' THEN
614 fft_ready_reg <= '0';
615 sample_load_reg <= '0';
616
617 fft_ongoing_counter <= '0';
618 ELSIF clk'event AND clk = '1' THEN
619 fft_ready_reg <= fft_ready;
620 sample_load_reg <= sample_load;
621
622 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
623 fft_ongoing_counter <= '0';
624
625 -- CASE fft_ongoing_counter IS
626 -- WHEN "01" => fft_ongoing_counter <= "00";
627 ---- WHEN "10" => fft_ongoing_counter <= "01";
628 -- WHEN OTHERS => NULL;
629 -- END CASE;
630 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
631 fft_ongoing_counter <= '1';
632 -- CASE fft_ongoing_counter IS
633 -- WHEN "00" => fft_ongoing_counter <= "01";
634 ---- WHEN "01" => fft_ongoing_counter <= "10";
635 -- WHEN OTHERS => NULL;
636 -- END CASE;
637 END IF;
638
639 END IF;
640 END PROCESS;
641
642 -----------------------------------------------------------------------------
643 PROCESS (clk, rstn)
644 BEGIN
645 IF rstn = '0' THEN
646 state_fsm_load_MS_memory <= IDLE;
647 current_fifo_load <= "00001";
648 ELSIF clk'EVENT AND clk = '1' THEN
649 CASE state_fsm_load_MS_memory IS
650 WHEN IDLE =>
651 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
652 state_fsm_load_MS_memory <= LOAD_FIFO;
653 END IF;
654 WHEN LOAD_FIFO =>
655 IF current_fifo_full = '1' THEN
656 state_fsm_load_MS_memory <= TRASH_FFT;
657 END IF;
658 WHEN TRASH_FFT =>
659 IF fft_ready = '0' THEN
660 state_fsm_load_MS_memory <= IDLE;
661 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
662 END IF;
663 WHEN OTHERS => NULL;
664 END CASE;
665
666 END IF;
667 END PROCESS;
668
669 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
670 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
671 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
672 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
673 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
674
675 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
676 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
677 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
678 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
679 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
680
681 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
682 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
683 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
684 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
685 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
686
687 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
688
689 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
690 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
691 AND state_fsm_load_MS_memory = LOAD_FIFO
692 AND current_fifo_load(I) = '1'
693 ELSE '1';
694 END GENERATE all_fifo;
695
696 PROCESS (clk, rstn)
697 BEGIN
698 IF rstn = '0' THEN
699 MEM_IN_SM_wen <= (OTHERS => '1');
700 ELSIF clk'EVENT AND clk = '1' THEN
701 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
702 END IF;
703 END PROCESS;
704
705 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
706 (fft_data_im & fft_data_re) &
707 (fft_data_im & fft_data_re) &
708 (fft_data_im & fft_data_re) &
709 (fft_data_im & fft_data_re);
710 -----------------------------------------------------------------------------
711
712
713 -----------------------------------------------------------------------------
714 Mem_In_SpectralMatrix : lppFIFOxN
715 GENERIC MAP (
716 tech => 0,
717 Mem_use => Mem_use,
718 Data_sz => 32, --16,
719 Addr_sz => 7, --8
720 FifoCnt => 5)
721 PORT MAP (
722 clk => clk,
723 rstn => rstn,
724
725 ReUse => MEM_IN_SM_ReUse,
726
727 wen => MEM_IN_SM_wen,
728 wdata => MEM_IN_SM_wData,
729
730 ren => MEM_IN_SM_ren,
731 rdata => MEM_IN_SM_rData,
732 full => MEM_IN_SM_Full,
733 empty => MEM_IN_SM_Empty,
734 almost_full => OPEN);
735
736 -----------------------------------------------------------------------------
737
738 observation_vector_1(11 DOWNTO 0) <= '0' &
739 SM_correlation_done & --4
740 SM_correlation_auto & --3
741 SM_correlation_start &
742 SM_correlation_start & --7
743 status_MS_input(1 DOWNTO 0)& --6..5
744 MEM_IN_SM_locked(4 DOWNTO 0); --4..0
745
746 -----------------------------------------------------------------------------
747 MS_control_1 : MS_control
748 PORT MAP (
749 clk => clk,
750 rstn => rstn,
751
752 current_status_ms => status_MS_input,
753
754 fifo_in_lock => MEM_IN_SM_locked,
755 fifo_in_data => MEM_IN_SM_rdata,
756 fifo_in_full => MEM_IN_SM_Full,
757 fifo_in_empty => MEM_IN_SM_Empty,
758 fifo_in_ren => MEM_IN_SM_ren,
759 fifo_in_reuse => MEM_IN_SM_ReUse,
760
761 fifo_out_data => SM_in_data,
762 fifo_out_ren => SM_in_ren,
763 fifo_out_empty => SM_in_empty,
764
765 current_status_component => status_component,
766
767 correlation_start => SM_correlation_start,
768 correlation_auto => SM_correlation_auto,
769 correlation_done => SM_correlation_done);
770
771
772 MS_calculation_1 : MS_calculation
773 PORT MAP (
774 clk => clk,
775 rstn => rstn,
776
777 fifo_in_data => SM_in_data,
778 fifo_in_ren => SM_in_ren,
779 fifo_in_empty => SM_in_empty,
780
781 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
782 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
783 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
784
785 correlation_start => SM_correlation_start,
786 correlation_auto => SM_correlation_auto,
787 correlation_begin => SM_correlation_begin,
788 correlation_done => SM_correlation_done);
789
790 -----------------------------------------------------------------------------
791 PROCESS (clk, rstn)
792 BEGIN -- PROCESS
793 IF rstn = '0' THEN -- asynchronous reset (active low)
794 current_matrix_write <= '0';
795 current_matrix_wait_empty <= '1';
796 status_component_fifo_0 <= (OTHERS => '0');
797 status_component_fifo_1 <= (OTHERS => '0');
798 status_component_fifo_0_end <= '0';
799 status_component_fifo_1_end <= '0';
800 SM_correlation_done_reg1 <= '0';
801 SM_correlation_done_reg2 <= '0';
802 SM_correlation_done_reg3 <= '0';
803
804 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
805 SM_correlation_done_reg1 <= SM_correlation_done;
806 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
807 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
808 status_component_fifo_0_end <= '0';
809 status_component_fifo_1_end <= '0';
810 IF SM_correlation_begin = '1' THEN
811 IF current_matrix_write = '0' THEN
812 status_component_fifo_0 <= status_component;
813 ELSE
814 status_component_fifo_1 <= status_component;
815 END IF;
816 END IF;
817
818 IF SM_correlation_done_reg3 = '1' THEN
819 IF current_matrix_write = '0' THEN
820 status_component_fifo_0_end <= '1';
821 ELSE
822 status_component_fifo_1_end <= '1';
823 END IF;
824 current_matrix_wait_empty <= '1';
825 current_matrix_write <= NOT current_matrix_write;
826 END IF;
827
828 IF current_matrix_wait_empty <= '1' THEN
829 IF current_matrix_write = '0' THEN
830 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
831 ELSE
832 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
833 END IF;
834 END IF;
835
836 END IF;
837 END PROCESS;
838
839 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
840 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
841 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
842 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
843 '1' WHEN current_matrix_wait_empty = '1' ELSE
844 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
845 MEM_OUT_SM_Full(1);
846
847 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
848 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
849
850 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
851 -----------------------------------------------------------------------------
852
853 Mem_Out_SpectralMatrix : lppFIFOxN
854 GENERIC MAP (
855 tech => 0,
856 Mem_use => Mem_use,
857 Data_sz => 32,
858 Addr_sz => 8,
859 FifoCnt => 2)
860 PORT MAP (
861 clk => clk,
862 rstn => rstn,
863
864 ReUse => (OTHERS => '0'),
865
866 wen => MEM_OUT_SM_Write,
867 wdata => MEM_OUT_SM_Data_in,
868
869 ren => MEM_OUT_SM_Read,
870 rdata => MEM_OUT_SM_Data_out,
871
872 full => MEM_OUT_SM_Full,
873 empty => MEM_OUT_SM_Empty,
874 almost_full => OPEN);
875
876 MEM_OUT_SM_Full_pad <= MEM_OUT_SM_Full;
877 MEM_OUT_SM_Full_pad_2 <= MEM_OUT_SM_Full_s;
878 MEM_OUT_SM_Empty_pad <= MEM_OUT_SM_Empty;
879
880 -- -----------------------------------------------------------------------------
881 ---- MEM_OUT_SM_Read <= "00";
882 -- PROCESS (clk, rstn)
883 -- BEGIN
884 -- IF rstn = '0' THEN
885 -- fifo_0_ready <= '0';
886 -- fifo_1_ready <= '0';
887 -- fifo_ongoing <= '0';
888 -- ELSIF clk'EVENT AND clk = '1' THEN
889 -- IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
890 -- fifo_ongoing <= '1';
891 -- fifo_0_ready <= '0';
892 -- ELSIF status_component_fifo_0_end = '1' THEN
893 -- fifo_0_ready <= '1';
894 -- END IF;
895
896 -- IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
897 -- fifo_ongoing <= '0';
898 -- fifo_1_ready <= '0';
899 -- ELSIF status_component_fifo_1_end = '1' THEN
900 -- fifo_1_ready <= '1';
901 -- END IF;
902
903 -- END IF;
904 -- END PROCESS;
905
906 -- MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
907 -- '1' WHEN fifo_0_ready = '0' ELSE
908 -- FSM_DMA_fifo_ren;
909
910 -- MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
911 -- '1' WHEN fifo_1_ready = '0' ELSE
912 -- FSM_DMA_fifo_ren;
913
914 -- FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
915 -- MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
916 -- '1';
917
918 -- FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
919 -- status_component_fifo_1;
920
921 -- FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
922 -- MEM_OUT_SM_Data_out(63 DOWNTO 32);
923
924 -- -----------------------------------------------------------------------------
925 -- lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
926 -- PORT MAP (
927 -- HCLK => clk,
928 -- HRESETn => rstn,
929
930 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
931 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
932 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
933 -- fifo_data => FSM_DMA_fifo_data,
934 -- fifo_empty => FSM_DMA_fifo_empty,
935 -- fifo_ren => FSM_DMA_fifo_ren,
936
937 -- dma_addr => dma_addr,
938 -- dma_data => dma_data,
939 -- dma_valid => dma_valid,
940 -- dma_valid_burst => dma_valid_burst,
941 -- dma_ren => dma_ren,
942 -- dma_done => dma_done,
943
944 -- ready_matrix_f0 => ready_matrix_f0,
945 -- ready_matrix_f1 => ready_matrix_f1,
946 -- ready_matrix_f2 => ready_matrix_f2,
947
948 -- error_bad_component_error => error_bad_component_error,
949 -- error_buffer_full => error_buffer_full,
950
951 -- debug_reg => debug_reg,
952 -- status_ready_matrix_f0 => status_ready_matrix_f0,
953 -- status_ready_matrix_f1 => status_ready_matrix_f1,
954 -- status_ready_matrix_f2 => status_ready_matrix_f2,
955
956 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
957 -- config_active_interruption_onError => config_active_interruption_onError,
958
959 -- addr_matrix_f0 => addr_matrix_f0,
960 -- addr_matrix_f1 => addr_matrix_f1,
961 -- addr_matrix_f2 => addr_matrix_f2,
962
963 -- matrix_time_f0 => matrix_time_f0,
964 -- matrix_time_f1 => matrix_time_f1,
965 -- matrix_time_f2 => matrix_time_f2
966 -- );
967 -- -----------------------------------------------------------------------------
968
969
970
971
972
973 -- -----------------------------------------------------------------------------
974 -- -- TIME MANAGMENT
975 -- -----------------------------------------------------------------------------
976 -- all_time <= coarse_time & fine_time;
977 -- --
978 -- f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
979 -- f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
980 -- f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
981 -- f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
982
983 -- all_time_reg: FOR I IN 0 TO 3 GENERATE
984
985 -- PROCESS (clk, rstn)
986 -- BEGIN
987 -- IF rstn = '0' THEN
988 -- f_empty_reg(I) <= '1';
989 -- ELSIF clk'event AND clk = '1' THEN
990 -- f_empty_reg(I) <= f_empty(I);
991 -- END IF;
992 -- END PROCESS;
993
994 -- time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
995
996 -- s_m_t_m_f0_A : spectral_matrix_time_managment
997 -- PORT MAP (
998 -- clk => clk,
999 -- rstn => rstn,
1000 -- time_in => all_time,
1001 -- update_1 => time_update_f(I),
1002 -- time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1003 -- );
1004
1005 -- END GENERATE all_time_reg;
1006
1007 -- time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
1008 -- time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
1009 -- time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
1010 -- time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
1011
1012 -- -----------------------------------------------------------------------------
1013
1014 END Behavioral; No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,221
1
2 LIBRARY IEEE;
3 USE IEEE.STD_LOGIC_1164.ALL;
4 USE IEEE.numeric_std.ALL;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.general_purpose.SYNC_FF;
8
9 ENTITY top_ad_conv_RHF1401_withFilter IS
10 GENERIC(
11 ChanelCount : INTEGER := 8;
12 ncycle_cnv_high : INTEGER := 13;
13 ncycle_cnv : INTEGER := 25);
14 PORT (
15 cnv_clk : IN STD_LOGIC; -- 24Mhz
16 cnv_rstn : IN STD_LOGIC;
17
18 cnv : OUT STD_LOGIC;
19
20 clk : IN STD_LOGIC; -- 25MHz
21 rstn : IN STD_LOGIC;
22 ADC_data : IN Samples14;
23 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
24 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
25 sample_val : OUT STD_LOGIC
26 );
27 END top_ad_conv_RHF1401_withFilter;
28
29 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
30
31 SIGNAL cnv_cycle_counter : INTEGER;
32 SIGNAL cnv_s : STD_LOGIC;
33 SIGNAL cnv_sync : STD_LOGIC;
34 SIGNAL cnv_sync_pre : STD_LOGIC;
35
36 SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
37 SIGNAL enable_ADC : STD_LOGIC;
38
39
40 SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
41
42 SIGNAL channel_counter : INTEGER;
43 CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
44
45 SIGNAL ADC_data_selected : Samples14;
46 SIGNAL ADC_data_result : Samples14;
47
48 SIGNAL sample_counter : INTEGER;
49
50 BEGIN
51
52
53 -----------------------------------------------------------------------------
54 -- CNV GEN
55 -----------------------------------------------------------------------------
56 PROCESS (cnv_clk, cnv_rstn)
57 BEGIN -- PROCESS
58 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
59 cnv_cycle_counter <= 0;
60 cnv_s <= '0';
61 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
62 IF cnv_cycle_counter < ncycle_cnv-1 THEN
63 cnv_cycle_counter <= cnv_cycle_counter + 1;
64 IF cnv_cycle_counter < ncycle_cnv_high THEN
65 cnv_s <= '1';
66 ELSE
67 cnv_s <= '0';
68 END IF;
69 ELSE
70 cnv_s <= '1';
71 cnv_cycle_counter <= 0;
72 END IF;
73 END IF;
74 END PROCESS;
75
76 cnv <= cnv_s;
77
78
79 -----------------------------------------------------------------------------
80 -- SYNC CNV
81 -----------------------------------------------------------------------------
82
83 SYNC_FF_cnv : SYNC_FF
84 GENERIC MAP (
85 NB_FF_OF_SYNC => 2)
86 PORT MAP (
87 clk => clk,
88 rstn => rstn,
89 A => cnv_s,
90 A_sync => cnv_sync);
91
92
93 -----------------------------------------------------------------------------
94 -- DATA GEN Output Enable
95 -----------------------------------------------------------------------------
96 PROCESS (clk, rstn)
97 BEGIN -- PROCESS
98 IF rstn = '0' THEN -- asynchronous reset (active low)
99 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1');
100 cnv_sync_pre <= '0';
101 enable_ADC <= '0';
102 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
103 cnv_sync_pre <= cnv_sync;
104 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
105 enable_ADC <= '1';
106 ADC_nOE_reg(0) <= '0';
107 ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1');
108 ELSE
109 enable_ADC <= NOT enable_ADC;
110 IF enable_ADC = '0' THEN
111 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= ADC_nOE_reg(ChanelCount-2 DOWNTO 0) & '1';
112 END IF;
113 END IF;
114
115 END IF;
116 END PROCESS;
117
118 ADC_nOE <= (OTHERS => '1') WHEN enable_ADC = '0' ELSE ADC_nOE_reg;
119
120 -----------------------------------------------------------------------------
121 -- ADC READ DATA
122 -----------------------------------------------------------------------------
123 PROCESS (clk, rstn)
124 BEGIN -- PROCESS
125 IF rstn = '0' THEN -- asynchronous reset (active low)
126 channel_counter <= MAX_COUNTER;
127 sample_reg(0) <= (OTHERS => '0');
128 sample_reg(1) <= (OTHERS => '0');
129 sample_reg(2) <= (OTHERS => '0');
130 sample_reg(3) <= (OTHERS => '0');
131 sample_reg(4) <= (OTHERS => '0');
132 sample_reg(5) <= (OTHERS => '0');
133 sample_reg(6) <= (OTHERS => '0');
134 sample_reg(7) <= (OTHERS => '0');
135
136 sample_val <= '0';
137 sample_counter <= 0;
138 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
139 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
140 channel_counter <= 0;
141 ELSE
142 IF channel_counter < MAX_COUNTER THEN
143 channel_counter <= channel_counter + 1;
144 END IF;
145 END IF;
146 sample_val <= '0';
147
148 CASE channel_counter IS
149 WHEN 0*2 => sample_reg(0) <= ADC_data_result;
150 WHEN 1*2 => sample_reg(1) <= ADC_data_result;
151 WHEN 2*2 => sample_reg(2) <= ADC_data_result;
152 WHEN 3*2 => sample_reg(3) <= ADC_data_result;
153 WHEN 4*2 => sample_reg(4) <= ADC_data_result;
154 WHEN 5*2 => sample_reg(5) <= ADC_data_result;
155 WHEN 6*2 => sample_reg(6) <= ADC_data_result;
156 WHEN 7*2 => sample_reg(7) <= ADC_data_result;
157 IF sample_counter = 9 THEN
158 sample_counter <= 0 ;
159 sample_val <= '1';
160 ELSE
161 sample_counter <= sample_counter +1;
162 END IF;
163
164 WHEN OTHERS => NULL;
165 END CASE;
166
167 END IF;
168 END PROCESS;
169
170
171 WITH channel_counter SELECT
172 ADC_data_selected <= sample_reg(0) WHEN 0*2,
173 sample_reg(1) WHEN 1*2,
174 sample_reg(2) WHEN 2*2,
175 sample_reg(3) WHEN 3*2,
176 sample_reg(4) WHEN 4*2,
177 sample_reg(5) WHEN 5*2,
178 sample_reg(6) WHEN 6*2,
179 sample_reg(7) WHEN OTHERS ;
180
181
182 ADC_data_result <= std_logic_vector( (signed(ADC_data_selected) + signed(ADC_data)) / 2);
183
184 sample <= sample_reg;
185
186
187
188
189 --RHF1401_drvr_1: RHF1401_drvr
190 -- GENERIC MAP (
191 -- ChanelCount => ChanelCount)
192 -- PORT MAP (
193 -- cnv_clk => cnv_sync,
194 -- clk => clk,
195 -- rstn => rstn,
196 -- ADC_data => ADC_data,
197 -- --ADC_smpclk => OPEN,
198 -- ADC_nOE => ADC_nOE,
199 -- sample => sample,
200 -- sample_val => sample_val);
201
202
203
204
205 END ar_top_ad_conv_RHF1401;
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
Show file before | Show file after | Hide comments
@@ -386,21 +386,40 BEGIN -- beh
386 -----------------------------------------------------------------------------
386 -----------------------------------------------------------------------------
387 --
387 --
388 -----------------------------------------------------------------------------
388 -----------------------------------------------------------------------------
389 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
389 top_ad_conv_RHF1401_withFilter_1: top_ad_conv_RHF1401_withFilter
390 GENERIC MAP (
390 GENERIC MAP (
391 ChanelCount => 8,
391 ChanelCount => 8,
392 ncycle_cnv_high => 40, -- TODO : 79
392 ncycle_cnv_high => 13,
393 ncycle_cnv => 250) -- TODO : 500
393 ncycle_cnv => 25)
394 PORT MAP (
394 PORT MAP (
395 cnv_clk => clk_24, -- TODO : 49.152
395 cnv_clk => clk_24,
396 cnv_rstn => rstn, -- ok
396 cnv_rstn => rstn,
397 cnv => ADC_smpclk_s, -- ok
397 cnv => ADC_smpclk_s,
398 clk => clk_25, -- ok
398 clk => clk_25,
399 rstn => rstn, -- ok
399 rstn => rstn,
400 ADC_data => ADC_data, -- ok
400 ADC_data => ADC_data,
401 ADC_nOE => ADC_OEB_bar_CH, -- ok
401 ADC_nOE => ADC_OEB_bar_CH,
402 sample => sample, -- ok
402 sample => sample,
403 sample_val => sample_val); -- ok
403 sample_val => sample_val);
404
405
406
407
408 --top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
409 -- GENERIC MAP (
410 -- ChanelCount => 8,
411 -- ncycle_cnv_high => 40, -- TODO : 79
412 -- ncycle_cnv => 250) -- TODO : 500
413 -- PORT MAP (
414 -- cnv_clk => clk_24, -- TODO : 49.152
415 -- cnv_rstn => rstn, -- ok
416 -- cnv => ADC_smpclk_s, -- ok
417 -- clk => clk_25, -- ok
418 -- rstn => rstn, -- ok
419 -- ADC_data => ADC_data, -- ok
420 -- ADC_nOE => ADC_OEB_bar_CH, -- ok
421 -- sample => sample, -- ok
422 -- sample_val => sample_val); -- ok
404
423
405 ADC_smpclk <= ADC_smpclk_s;
424 ADC_smpclk <= ADC_smpclk_s;
406
425
Show file before | Show file after | Hide comments
@@ -338,6 +338,24 COMPONENT ADS7886_drvr_v2 IS
338 sample_val : OUT STD_LOGIC
338 sample_val : OUT STD_LOGIC
339 );
339 );
340 END COMPONENT;
340 END COMPONENT;
341
342 COMPONENT top_ad_conv_RHF1401_withFilter
343 GENERIC (
344 ChanelCount : INTEGER;
345 ncycle_cnv_high : INTEGER;
346 ncycle_cnv : INTEGER);
347 PORT (
348 cnv_clk : IN STD_LOGIC;
349 cnv_rstn : IN STD_LOGIC;
350 cnv : OUT STD_LOGIC;
351 clk : IN STD_LOGIC;
352 rstn : IN STD_LOGIC;
353 ADC_data : IN Samples14;
354 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
355 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
356 sample_val : OUT STD_LOGIC);
357 END COMPONENT;
358
341
359
342 END lpp_ad_conv;
360 END lpp_ad_conv;
343
361
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@@ -1,6 +1,7
1 lpp_ad_Conv.vhd
1 lpp_ad_Conv.vhd
2 RHF1401.vhd
2 RHF1401.vhd
3 top_ad_conv_RHF1401.vhd
3 top_ad_conv_RHF1401.vhd
4 top_ad_conv_RHF1401_withFilter.vhd
4 TestModule_RHF1401.vhd
5 TestModule_RHF1401.vhd
5 top_ad_conv_ADS7886_v2.vhd
6 top_ad_conv_ADS7886_v2.vhd
6 ADS7886_drvr_v2.vhd
7 ADS7886_drvr_v2.vhd
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