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Clean LFR-EQM boards...
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.sim.ALL;
32 32 USE gaisler.memctrl.ALL;
33 33 USE gaisler.leon3.ALL;
34 34 USE gaisler.uart.ALL;
35 35 USE gaisler.misc.ALL;
36 36 USE gaisler.spacewire.ALL;
37 37 LIBRARY esa;
38 38 USE esa.memoryctrl.ALL;
39 39 LIBRARY lpp;
40 40 USE lpp.lpp_memory.ALL;
41 41 USE lpp.lpp_ad_conv.ALL;
42 42 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
43 43 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
44 44 USE lpp.iir_filter.ALL;
45 45 USE lpp.general_purpose.ALL;
46 46 USE lpp.lpp_lfr_management.ALL;
47 47 USE lpp.lpp_leon3_soc_pkg.ALL;
48 48 USE lpp.lpp_bootloader_pkg.ALL;
49 49
50 50 --library proasic3l;
51 51 --use proasic3l.all;
52 52
53 53 ENTITY LFR_EQM IS
54 54 GENERIC (
55 55 Mem_use : INTEGER := use_RAM;
56 56 USE_BOOTLOADER : INTEGER := 0;
57 57 USE_ADCDRIVER : INTEGER := 1;
58 58 tech : INTEGER := apa3e;
59 59 tech_leon : INTEGER := apa3e;
60 60 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
61 61 USE_DEBUG_VECTOR : INTEGER := 0
62 62 );
63 63
64 64 PORT (
65 65 clk50MHz : IN STD_ULOGIC;
66 66 clk49_152MHz : IN STD_ULOGIC;
67 67 reset : IN STD_ULOGIC;
68 68
69 69 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
70 70
71 71 -- TAG --------------------------------------------------------------------
72 72 --TAG1 : IN STD_ULOGIC; -- DSU rx data
73 73 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
74 74 -- UART APB ---------------------------------------------------------------
75 75 --TAG2 : IN STD_ULOGIC; -- UART1 rx data
76 76 --TAG4 : OUT STD_ULOGIC; -- UART1 tx data
77 77 -- RAM --------------------------------------------------------------------
78 78 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
79 79 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 80
81 81 nSRAM_MBE : INOUT STD_LOGIC; -- new
82 82 nSRAM_E1 : OUT STD_LOGIC; -- new
83 83 nSRAM_E2 : OUT STD_LOGIC; -- new
84 84 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
85 85 nSRAM_W : OUT STD_LOGIC; -- new
86 86 nSRAM_G : OUT STD_LOGIC; -- new
87 87 nSRAM_BUSY : IN STD_LOGIC; -- new
88 88 -- SPW --------------------------------------------------------------------
89 89 spw1_en : OUT STD_LOGIC; -- new
90 90 spw1_din : IN STD_LOGIC;
91 91 spw1_sin : IN STD_LOGIC;
92 92 spw1_dout : OUT STD_LOGIC;
93 93 spw1_sout : OUT STD_LOGIC;
94 94 spw2_en : OUT STD_LOGIC; -- new
95 95 spw2_din : IN STD_LOGIC;
96 96 spw2_sin : IN STD_LOGIC;
97 97 spw2_dout : OUT STD_LOGIC;
98 98 spw2_sout : OUT STD_LOGIC;
99 99 -- ADC --------------------------------------------------------------------
100 100 bias_fail_sw : OUT STD_LOGIC;
101 101 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102 ADC_smpclk : OUT STD_LOGIC;
103 103 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
104 104 -- DAC --------------------------------------------------------------------
105 105 DAC_SDO : OUT STD_LOGIC;
106 106 DAC_SCK : OUT STD_LOGIC;
107 107 DAC_SYNC : OUT STD_LOGIC;
108 108 DAC_CAL_EN : OUT STD_LOGIC;
109 109 -- HK ---------------------------------------------------------------------
110 110 HK_smpclk : OUT STD_LOGIC;
111 111 ADC_OEB_bar_HK : OUT STD_LOGIC;
112 112 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--;
113 113 ---------------------------------------------------------------------------
114 114 -- TAG8 : OUT STD_LOGIC
115 115 );
116 116
117 117 END LFR_EQM;
118 118
119 119
120 120 ARCHITECTURE beh OF LFR_EQM IS
121 121
122 122 SIGNAL clk_25 : STD_LOGIC := '0';
123 123 SIGNAL clk_24 : STD_LOGIC := '0';
124 124 -----------------------------------------------------------------------------
125 125 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 126 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
127 127
128 128 -- CONSTANTS
129 129 CONSTANT CFG_PADTECH : INTEGER := inferred;
130 130 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
131 131 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
132 132 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
133 133
134 134 SIGNAL apbi_ext : apb_slv_in_type;
135 135 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
136 136 SIGNAL ahbi_s_ext : ahb_slv_in_type;
137 137 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
138 138 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
139 139 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
140 140
141 141 -- Spacewire signals
142 142 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
143 143 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
144 144 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
145 145 SIGNAL spw_rxtxclk : STD_ULOGIC;
146 146 SIGNAL spw_rxclkn : STD_ULOGIC;
147 147 SIGNAL spw_clk : STD_LOGIC;
148 148 SIGNAL swni : grspw_in_type;
149 149 SIGNAL swno : grspw_out_type;
150 150
151 151 --GPIO
152 152 SIGNAL gpioi : gpio_in_type;
153 153 SIGNAL gpioo : gpio_out_type;
154 154
155 155 -- AD Converter ADS7886
156 156 SIGNAL sample : Samples14v(8 DOWNTO 0);
157 157 SIGNAL sample_s : Samples(8 DOWNTO 0);
158 158 SIGNAL sample_val : STD_LOGIC;
159 159 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
160 160
161 161 -----------------------------------------------------------------------------
162 162 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
163 163
164 164 -----------------------------------------------------------------------------
165 165 SIGNAL rstn_25 : STD_LOGIC;
166 166 SIGNAL rstn_24 : STD_LOGIC;
167 167
168 168 SIGNAL LFR_soft_rstn : STD_LOGIC;
169 169 SIGNAL LFR_rstn : STD_LOGIC;
170 170
171 171 SIGNAL ADC_smpclk_s : STD_LOGIC;
172 172
173 173 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
174 174
175 175 SIGNAL clk50MHz_int : STD_LOGIC := '0';
176 176 SIGNAL clk_25_int : STD_LOGIC := '0';
177 177
178 178 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
179 179
180 180 SIGNAL rstn_50 : STD_LOGIC;
181 181 SIGNAL clk_lock : STD_LOGIC;
182 182 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
183 183 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
184 184
185 185 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
186 186 SIGNAL ahbrxd: STD_LOGIC;
187 187 SIGNAL ahbtxd: STD_LOGIC;
188 188 SIGNAL urxd1 : STD_LOGIC;
189 189 SIGNAL utxd1 : STD_LOGIC;
190 190 BEGIN -- beh
191 191
192 192 -----------------------------------------------------------------------------
193 193 -- CLK_LOCK
194 194 -----------------------------------------------------------------------------
195 195 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
196 196
197 197 PROCESS (clk50MHz_int, rstn_50)
198 198 BEGIN -- PROCESS
199 199 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
200 200 clk_lock <= '0';
201 201 clk_busy_counter <= (OTHERS => '0');
202 202 nSRAM_BUSY_reg <= '0';
203 203 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
204 204 nSRAM_BUSY_reg <= nSRAM_BUSY;
205 205 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
206 206 IF clk_busy_counter = "1111" THEN
207 207 clk_lock <= '1';
208 208 ELSE
209 209 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
210 210 END IF;
211 211 END IF;
212 212 END IF;
213 213 END PROCESS;
214 214
215 215 -----------------------------------------------------------------------------
216 216 -- CLK
217 217 -----------------------------------------------------------------------------
218 218 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
219 219 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
220 220
221 221 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
222 222 clk50MHz_int <= clk50MHz;
223 223
224 224 PROCESS(clk50MHz_int)
225 225 BEGIN
226 226 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
227 227 --clk_25_int <= NOT clk_25_int;
228 228 clk_25 <= NOT clk_25;
229 229 END IF;
230 230 END PROCESS;
231 231 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
232 232
233 233 PROCESS(clk49_152MHz)
234 234 BEGIN
235 235 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
236 236 clk_24 <= NOT clk_24;
237 237 END IF;
238 238 END PROCESS;
239 239 -- clk_49 <= clk49_152MHz;
240 240
241 241 -----------------------------------------------------------------------------
242 242 --
243 243 leon3_soc_1 : leon3_soc
244 244 GENERIC MAP (
245 245 fabtech => tech_leon,
246 246 memtech => tech_leon,
247 247 padtech => inferred,
248 248 clktech => inferred,
249 249 disas => 0,
250 250 dbguart => 0,
251 251 pclow => 2,
252 252 clk_freq => 25000,
253 253 IS_RADHARD => 0,
254 254 NB_CPU => 1,
255 255 ENABLE_FPU => 1,
256 256 FPU_NETLIST => 0,
257 257 ENABLE_DSU => 1,
258 258 ENABLE_AHB_UART => 1,
259 259 ENABLE_APB_UART => 1,
260 260 ENABLE_IRQMP => 1,
261 261 ENABLE_GPT => 1,
262 262 NB_AHB_MASTER => NB_AHB_MASTER,
263 263 NB_AHB_SLAVE => NB_AHB_SLAVE,
264 264 NB_APB_SLAVE => NB_APB_SLAVE,
265 265 ADDRESS_SIZE => 19,
266 266 USES_IAP_MEMCTRLR => 1,
267 267 BYPASS_EDAC_MEMCTRLR => '0',
268 268 SRBANKSZ => 8,
269 269 SLOW_TIMING_EMULATION => 0
270 270 )
271 271 PORT MAP (
272 272 clk => clk_25,
273 273 reset => rstn_25,
274 274 errorn => OPEN,
275 275
276 276 ahbrxd => ahbrxd, -- INPUT
277 277 ahbtxd => ahbtxd, -- OUTPUT
278 278 urxd1 => urxd1, -- INPUT
279 279 utxd1 => utxd1, -- OUTPUT
280 280
281 281 address => address,
282 282 data => data,
283 283 nSRAM_BE0 => OPEN,
284 284 nSRAM_BE1 => OPEN,
285 285 nSRAM_BE2 => OPEN,
286 286 nSRAM_BE3 => OPEN,
287 287 nSRAM_WE => nSRAM_W,
288 288 nSRAM_CE => nSRAM_CE,
289 289 nSRAM_OE => nSRAM_G,
290 290 nSRAM_READY => nSRAM_BUSY,
291 291 SRAM_MBE => nSRAM_MBE,
292 292
293 293 apbi_ext => apbi_ext,
294 294 apbo_ext => apbo_ext,
295 295 ahbi_s_ext => ahbi_s_ext,
296 296 ahbo_s_ext => ahbo_s_ext,
297 297 ahbi_m_ext => ahbi_m_ext,
298 298 ahbo_m_ext => ahbo_m_ext);
299 299
300 300
301 301 nSRAM_E1 <= nSRAM_CE(0);
302 302 nSRAM_E2 <= nSRAM_CE(1);
303 303
304 304 -------------------------------------------------------------------------------
305 305 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
306 306 -------------------------------------------------------------------------------
307 307 apb_lfr_management_1 : apb_lfr_management
308 308 GENERIC MAP (
309 309 tech => tech,
310 310 pindex => 6,
311 311 paddr => 6,
312 312 pmask => 16#fff#,
313 313 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
314 314 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
315 315 PORT MAP (
316 316 clk25MHz => clk_25,
317 317 resetn_25MHz => rstn_25, -- TODO
318 318 --clk24_576MHz => clk_24, -- 49.152MHz/2
319 319 --resetn_24_576MHz => rstn_24, -- TODO
320 320
321 321 grspw_tick => swno.tickout,
322 322 apbi => apbi_ext,
323 323 apbo => apbo_ext(6),
324 324
325 325 HK_sample => sample_s(8),
326 326 HK_val => sample_val,
327 327 HK_sel => HK_SEL,
328 328
329 329 DAC_SDO => DAC_SDO,
330 330 DAC_SCK => DAC_SCK,
331 331 DAC_SYNC => DAC_SYNC,
332 332 DAC_CAL_EN => DAC_CAL_EN,
333 333
334 334 coarse_time => coarse_time,
335 335 fine_time => fine_time,
336 336 LFR_soft_rstn => LFR_soft_rstn
337 337 );
338 338
339 339 -----------------------------------------------------------------------
340 340 --- SpaceWire --------------------------------------------------------
341 341 -----------------------------------------------------------------------
342 342
343 343 ------------------------------------------------------------------------------
344 344 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
345 345 ------------------------------------------------------------------------------
346 346 spw1_en <= '1';
347 347 spw2_en <= '1';
348 348 ------------------------------------------------------------------------------
349 349 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
350 350 ------------------------------------------------------------------------------
351 351
352 352 --spw_clk <= clk50MHz;
353 353 --spw_rxtxclk <= spw_clk;
354 354 --spw_rxclkn <= NOT spw_rxtxclk;
355 355
356 356 -- PADS for SPW1
357 357 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
358 358 PORT MAP (spw1_din, dtmp(0));
359 359 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
360 360 PORT MAP (spw1_sin, stmp(0));
361 361 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
362 362 PORT MAP (spw1_dout, swno.d(0));
363 363 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
364 364 PORT MAP (spw1_sout, swno.s(0));
365 365 -- PADS FOR SPW2
366 366 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
367 367 PORT MAP (spw2_din, dtmp(1));
368 368 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
369 369 PORT MAP (spw2_sin, stmp(1));
370 370 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
371 371 PORT MAP (spw2_dout, swno.d(1));
372 372 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
373 373 PORT MAP (spw2_sout, swno.s(1));
374 374
375 375 -- GRSPW PHY
376 376 --spw1_input: if CFG_SPW_GRSPW = 1 generate
377 377 spw_inputloop : FOR j IN 0 TO 1 GENERATE
378 378 spw_phy0 : grspw_phy
379 379 GENERIC MAP(
380 380 tech => tech_leon,
381 381 rxclkbuftype => 1,
382 382 scantest => 0)
383 383 PORT MAP(
384 384 rxrst => swno.rxrst,
385 385 di => dtmp(j),
386 386 si => stmp(j),
387 387 rxclko => spw_rxclk(j),
388 388 do => swni.d(j),
389 389 ndo => swni.nd(j*5+4 DOWNTO j*5),
390 390 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
391 391 END GENERATE spw_inputloop;
392 392
393 393 -- SPW core
394 394 sw0 : grspwm GENERIC MAP(
395 395 tech => tech_leon,
396 396 hindex => 1,
397 397 pindex => 5,
398 398 paddr => 5,
399 399 pirq => 11,
400 400 sysfreq => 25000, -- CPU_FREQ
401 401 rmap => 1,
402 402 rmapcrc => 1,
403 403 fifosize1 => 16,
404 404 fifosize2 => 16,
405 405 rxclkbuftype => 1,
406 406 rxunaligned => 0,
407 407 rmapbufs => 4,
408 408 ft => 0,
409 409 netlist => 0,
410 410 ports => 2,
411 411 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
412 412 memtech => tech_leon,
413 413 destkey => 2,
414 414 spwcore => 1
415 415 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
416 416 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
417 417 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
418 418 )
419 419 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
420 420 spw_rxclk(1),
421 421 clk50MHz_int,
422 422 clk50MHz_int,
423 423 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
424 424 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
425 425 swni, swno);
426 426
427 427 swni.tickin <= '0';
428 428 swni.rmapen <= '1';
429 429 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
430 430 swni.tickinraw <= '0';
431 431 swni.timein <= (OTHERS => '0');
432 432 swni.dcrstval <= (OTHERS => '0');
433 433 swni.timerrstval <= (OTHERS => '0');
434 434
435 435 -------------------------------------------------------------------------------
436 436 -- LFR ------------------------------------------------------------------------
437 437 -------------------------------------------------------------------------------
438 438 LFR_rstn <= LFR_soft_rstn AND rstn_25;
439 439
440 440 lpp_lfr_1 : lpp_lfr
441 441 GENERIC MAP (
442 442 Mem_use => Mem_use,
443 443 tech => tech,
444 444 nb_data_by_buffer_size => 32,
445 445 --nb_word_by_buffer_size => 30,
446 446 nb_snapshot_param_size => 32,
447 447 delta_vector_size => 32,
448 448 delta_vector_size_f0_2 => 7, -- log2(96)
449 449 pindex => 15,
450 450 paddr => 15,
451 451 pmask => 16#fff#,
452 452 pirq_ms => 6,
453 453 pirq_wfp => 14,
454 454 hindex => 2,
455 top_lfr_version => X"020153", -- aa.bb.cc version
456 -- AA : BOARD NUMBER
457 -- 0 => MINI_LFR
458 -- 1 => EM
459 -- 2 => EQM (with A3PE3000)
460 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA)
455 top_lfr_version => LPP_LFR_BOARD_LFR_EQM & "015B",
456 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA,
457 DATA_SHAPING_SATURATION => 1)
461 458 PORT MAP (
462 459 clk => clk_25,
463 460 rstn => LFR_rstn,
464 461 sample_B => sample_s(2 DOWNTO 0),
465 462 sample_E => sample_s(7 DOWNTO 3),
466 463 sample_val => sample_val,
467 464 apbi => apbi_ext,
468 465 apbo => apbo_ext(15),
469 466 ahbi => ahbi_m_ext,
470 467 ahbo => ahbo_m_ext(2),
471 468 coarse_time => coarse_time,
472 469 fine_time => fine_time,
473 470 data_shaping_BW => bias_fail_sw,
474 471 debug_vector => debug_vector,
475 472 debug_vector_ms => OPEN); --,
476 473 --observation_vector_0 => OPEN,
477 474 --observation_vector_1 => OPEN,
478 475 --observation_reg => observation_reg);
479 476
480 477
481 478 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
482 479 sample_s(I) <= sample(I) & '0' & '0';
483 480 END GENERATE all_sample;
484 481 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
485 482
486 483 -----------------------------------------------------------------------------
487 484 --
488 485 -----------------------------------------------------------------------------
489 486 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
490 487 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
491 488 GENERIC MAP (
492 489 ChanelCount => 9,
493 490 ncycle_cnv_high => 12,
494 491 ncycle_cnv => 25,
495 492 FILTER_ENABLED => 16#FF#)
496 493 PORT MAP (
497 494 cnv_clk => clk_24,
498 495 cnv_rstn => rstn_24,
499 496 cnv => ADC_smpclk_s,
500 497 clk => clk_25,
501 498 rstn => rstn_25,
502 499 ADC_data => ADC_data,
503 500 ADC_nOE => ADC_OEB_bar_CH_s,
504 501 sample => sample,
505 502 sample_val => sample_val);
506 503
507 504 END GENERATE USE_ADCDRIVER_true;
508 505
509 506 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
510 507 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
511 508 GENERIC MAP (
512 509 ChanelCount => 9,
513 510 ncycle_cnv_high => 25,
514 511 ncycle_cnv => 50,
515 512 FILTER_ENABLED => 16#FF#)
516 513 PORT MAP (
517 514 cnv_clk => clk_24,
518 515 cnv_rstn => rstn_24,
519 516 cnv => ADC_smpclk_s,
520 517 clk => clk_25,
521 518 rstn => rstn_25,
522 519 ADC_data => ADC_data,
523 520 ADC_nOE => OPEN,
524 521 sample => OPEN,
525 522 sample_val => sample_val);
526 523
527 524 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
528 525
529 526 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
530 527 ramp_generator_1: ramp_generator
531 528 GENERIC MAP (
532 529 DATA_SIZE => 14,
533 530 VALUE_UNSIGNED_INIT => 2**I,
534 531 VALUE_UNSIGNED_INCR => 0,
535 532 VALUE_UNSIGNED_MASK => 16#3FFF#)
536 533 PORT MAP (
537 534 clk => clk_25,
538 535 rstn => rstn_25,
539 536 new_data => sample_val,
540 537 output_data => sample(I) );
541 538 END GENERATE all_sample;
542 539
543 540
544 541 END GENERATE USE_ADCDRIVER_false;
545 542
546 543
547 544
548 545
549 546 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
550 547
551 548 ADC_smpclk <= ADC_smpclk_s;
552 549 HK_smpclk <= ADC_smpclk_s;
553 550
554 551
555 552 -----------------------------------------------------------------------------
556 553 -- HK
557 554 -----------------------------------------------------------------------------
558 555 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
559 556
560 557 -----------------------------------------------------------------------------
561 558 --
562 559 -----------------------------------------------------------------------------
563 560 inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
564 561 lpp_bootloader_1: lpp_bootloader
565 562 GENERIC MAP (
566 563 pindex => 13,
567 564 paddr => 13,
568 565 pmask => 16#fff#,
569 566 hindex => 3,
570 567 haddr => 0,
571 568 hmask => 16#fff#)
572 569 PORT MAP (
573 570 HCLK => clk_25,
574 571 HRESETn => rstn_25,
575 572 apbi => apbi_ext,
576 573 apbo => apbo_ext(13),
577 574 ahbsi => ahbi_s_ext,
578 575 ahbso => ahbo_s_ext(3));
579 576 END GENERATE inst_bootloader;
580 577
581 578 -----------------------------------------------------------------------------
582 579 --
583 580 -----------------------------------------------------------------------------
584 581 USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
585 582 PROCESS (clk_25, rstn_25)
586 583 BEGIN -- PROCESS
587 584 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
588 585 TAG <= (OTHERS => '0');
589 586 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
590 587 TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
591 588 END IF;
592 589 END PROCESS;
593 590
594 591
595 592 END GENERATE USE_DEBUG_VECTOR_IF;
596 593
597 594 USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
598 595 ahbrxd <= TAG(1);
599 596 TAG(3) <= ahbtxd;
600 597 urxd1 <= TAG(2);
601 598 TAG(4) <= utxd1;
602 599 TAG(8) <= nSRAM_BUSY;
603 600 END GENERATE USE_DEBUG_VECTOR_IF2;
604 601
605 602 END beh;
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