# HG changeset patch # User Alexis Jeandet # Date 2016-12-13 10:38:06 # Node ID fb1595662984d1cc18d94d229b960ddeeaccf2f1 # Parent b68575ae3d3bb07b07d96d7faab2103b056dad4d Clean LFR-EQM boards Updated SOLO_LFR_LFR-EQM top (changed lfr-version number) diff --git a/boards/LFR-EQM/LFR_EQM.pdc b/boards/LFR-EQM/LFR_EQM.pdc deleted file mode 100644 --- a/boards/LFR-EQM/LFR_EQM.pdc +++ /dev/null @@ -1,122 +0,0 @@ -set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout -set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout -set_io reset -pinname N18 -fixed yes -DIRECTION Inout - -set_io {address[0]} -pinname H16 -fixed yes -DIRECTION Inout -set_io {address[1]} -pinname J15 -fixed yes -DIRECTION Inout -set_io {address[2]} -pinname B18 -fixed yes -DIRECTION Inout -set_io {address[3]} -pinname C17 -fixed yes -DIRECTION Inout -set_io {address[4]} -pinname C18 -fixed yes -DIRECTION Inout -set_io {address[5]} -pinname U2 -fixed yes -DIRECTION Inout -set_io {address[6]} -pinname U3 -fixed yes -DIRECTION Inout -set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout -set_io {address[8]} -pinname N11 -fixed yes -DIRECTION Inout -set_io {address[9]} -pinname R13 -fixed yes -DIRECTION Inout -set_io {address[10]} -pinname V13 -fixed yes -DIRECTION Inout -set_io {address[11]} -pinname U13 -fixed yes -DIRECTION Inout -set_io {address[12]} -pinname V15 -fixed yes -DIRECTION Inout -set_io {address[13]} -pinname V16 -fixed yes -DIRECTION Inout -set_io {address[14]} -pinname V17 -fixed yes -DIRECTION Inout -set_io {address[15]} -pinname N1 -fixed yes -DIRECTION Inout -set_io {address[16]} -pinname R3 -fixed yes -DIRECTION Inout -set_io {address[17]} -pinname P4 -fixed yes -DIRECTION Inout -set_io {address[18]} -pinname N3 -fixed yes -DIRECTION Inout -set_io {address[19]} -pinname M7 -fixed yes -DIRECTION Inout - -set_io {data[0]} -pinname P17 -fixed yes -DIRECTION Inout -set_io {data[1]} -pinname R18 -fixed yes -DIRECTION Inout -set_io {data[2]} -pinname T18 -fixed yes -DIRECTION Inout -set_io {data[3]} -pinname J13 -fixed yes -DIRECTION Inout -set_io {data[4]} -pinname T13 -fixed yes -DIRECTION Inout -set_io {data[5]} -pinname T12 -fixed yes -DIRECTION Inout -set_io {data[6]} -pinname R12 -fixed yes -DIRECTION Inout -set_io {data[7]} -pinname T11 -fixed yes -DIRECTION Inout -set_io {data[8]} -pinname N2 -fixed yes -DIRECTION Inout -set_io {data[9]} -pinname P1 -fixed yes -DIRECTION Inout -set_io {data[10]} -pinname R1 -fixed yes -DIRECTION Inout -set_io {data[11]} -pinname T1 -fixed yes -DIRECTION Inout -set_io {data[12]} -pinname M4 -fixed yes -DIRECTION Inout -set_io {data[13]} -pinname K1 -fixed yes -DIRECTION Inout -set_io {data[14]} -pinname J1 -fixed yes -DIRECTION Inout -set_io {data[15]} -pinname H1 -fixed yes -DIRECTION Inout -set_io {data[16]} -pinname H15 -fixed yes -DIRECTION Inout -set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout -set_io {data[18]} -pinname H13 -fixed yes -DIRECTION Inout -set_io {data[19]} -pinname G12 -fixed yes -DIRECTION Inout -set_io {data[20]} -pinname V14 -fixed yes -DIRECTION Inout -set_io {data[21]} -pinname N9 -fixed yes -DIRECTION Inout -set_io {data[22]} -pinname M13 -fixed yes -DIRECTION Inout -set_io {data[23]} -pinname M15 -fixed yes -DIRECTION Inout -set_io {data[24]} -pinname J17 -fixed yes -DIRECTION Inout -set_io {data[25]} -pinname K15 -fixed yes -DIRECTION Inout -set_io {data[26]} -pinname J14 -fixed yes -DIRECTION Inout -set_io {data[27]} -pinname U18 -fixed yes -DIRECTION Inout -set_io {data[28]} -pinname H18 -fixed yes -DIRECTION Inout -set_io {data[29]} -pinname J18 -fixed yes -DIRECTION Inout -set_io {data[30]} -pinname G17 -fixed yes -DIRECTION Inout -set_io {data[31]} -pinname F18 -fixed yes -DIRECTION Inout - -set_io nSRAM_BE0 -pinname U12 -fixed yes -DIRECTION Inout -set_io nSRAM_BE1 -pinname K18 -fixed yes -DIRECTION Inout -set_io nSRAM_BE2 -pinname K12 -fixed yes -DIRECTION Inout -set_io nSRAM_BE3 -pinname F17 -fixed yes -DIRECTION Inout -set_io nSRAM_WE -pinname D18 -fixed yes -DIRECTION Inout -set_io nSRAM_CE -pinname M6 -fixed yes -DIRECTION Inout -set_io nSRAM_OE -pinname N12 -fixed yes -DIRECTION Inout - -set_io spw1_din -pinname D6 -fixed yes -DIRECTION Inout -set_io spw1_sin -pinname C6 -fixed yes -DIRECTION Inout -set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout -set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout - -set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout -set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout -set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout -set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout - -set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout -set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout -set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout - -set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout -set_io TAG2 -pinname K13 -fixed yes -DIRECTION Inout -set_io TAG3 -pinname L16 -fixed yes -DIRECTION Inout -set_io TAG4 -pinname L15 -fixed yes -DIRECTION Inout -#set_io TAG5 -pinname M16 -fixed yes -DIRECTION Inout -#set_io TAG6 -pinname L13 -fixed yes -DIRECTION Inout -#set_io TAG7 -pinname P6 -fixed yes -DIRECTION Inout -set_io TAG8 -pinname R6 -fixed yes -DIRECTION Inout -#set_io TAG9 -pinname T4 -fixed yes -DIRECTION Inout - -set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout - -set_io {ADC_OEB_bar_CH[0]} -pinname A13 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[1]} -pinname A14 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[2]} -pinname A10 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[3]} -pinname B10 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[5]} -pinname D13 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[6]} -pinname A11 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[7]} -pinname B12 -fixed yes -DIRECTION Inout - -set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout - -set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout -set_io ADC_OEB_bar_HK -pinname D14 -fixed yes -DIRECTION Inout -set_io {HK_SEL[0]} -pinname A2 -fixed yes -DIRECTION Inout -set_io {HK_SEL[1]} -pinname C3 -fixed yes -DIRECTION Inout - -set_io {ADC_data[0]} -pinname A16 -fixed yes -DIRECTION Inout -set_io {ADC_data[1]} -pinname B16 -fixed yes -DIRECTION Inout -set_io {ADC_data[2]} -pinname A17 -fixed yes -DIRECTION Inout -set_io {ADC_data[3]} -pinname C12 -fixed yes -DIRECTION Inout -set_io {ADC_data[4]} -pinname B17 -fixed yes -DIRECTION Inout -set_io {ADC_data[5]} -pinname C13 -fixed yes -DIRECTION Inout -set_io {ADC_data[6]} -pinname D15 -fixed yes -DIRECTION Inout -set_io {ADC_data[7]} -pinname E15 -fixed yes -DIRECTION Inout -set_io {ADC_data[8]} -pinname D16 -fixed yes -DIRECTION Inout -set_io {ADC_data[9]} -pinname F16 -fixed yes -DIRECTION Inout -set_io {ADC_data[10]} -pinname F15 -fixed yes -DIRECTION Inout -set_io {ADC_data[11]} -pinname G16 -fixed yes -DIRECTION Inout -set_io {ADC_data[12]} -pinname F13 -fixed yes -DIRECTION Inout -set_io {ADC_data[13]} -pinname G13 -fixed yes -DIRECTION Inout diff --git a/boards/LFR-EQM/LFR_EQM.sdc b/boards/LFR-EQM/LFR_EQM.sdc deleted file mode 100644 --- a/boards/LFR-EQM/LFR_EQM.sdc +++ /dev/null @@ -1,30 +0,0 @@ -# Top Level Design Parameters - -# Clocks - -create_clock -period 10.000000 -waveform {0.000000 5.000000} clk50MHz -create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz -create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25:Q -create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q -create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin} - - -# False Paths Between Clocks - - -# False Path Constraints - - -# Maximum Delay Constraints - - -# Multicycle Constraints - - -# Virtual Clocks -# Output Load Constraints -# Driving Cell Constraints -# Wire Loads -# set_wire_load_mode top - -# Other Constraints diff --git a/boards/LFR-EQM/LFR_EQM_A3PE3000_NoADC.pdc b/boards/LFR-EQM/LFR_EQM_A3PE3000_NoADC.pdc deleted file mode 100644 --- a/boards/LFR-EQM/LFR_EQM_A3PE3000_NoADC.pdc +++ /dev/null @@ -1,124 +0,0 @@ -set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout -set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout -set_io reset -pinname R4 -fixed yes -DIRECTION Inout -SCHMITT_TRIGGER On - -set_io {address[0]} -pinname U3 -fixed yes -DIRECTION Inout -set_io {address[1]} -pinname V14 -fixed yes -DIRECTION Inout -set_io {address[2]} -pinname V13 -fixed yes -DIRECTION Inout -set_io {address[3]} -pinname V16 -fixed yes -DIRECTION Inout -set_io {address[4]} -pinname N9 -fixed yes -DIRECTION Inout -set_io {address[5]} -pinname T11 -fixed yes -DIRECTION Inout -set_io {address[6]} -pinname U13 -fixed yes -DIRECTION Inout -set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout -set_io {address[8]} -pinname U2 -fixed yes -DIRECTION Inout -set_io {address[9]} -pinname N11 -fixed yes -DIRECTION Inout -set_io {address[10]} -pinname R13 -fixed yes -DIRECTION Inout -set_io {address[11]} -pinname R12 -fixed yes -DIRECTION Inout -set_io {address[12]} -pinname M15 -fixed yes -DIRECTION Inout -set_io {address[13]} -pinname T12 -fixed yes -DIRECTION Inout -set_io {address[14]} -pinname M13 -fixed yes -DIRECTION Inout -set_io {address[15]} -pinname T13 -fixed yes -DIRECTION Inout -set_io {address[16]} -pinname L13 -fixed yes -DIRECTION Inout -set_io {address[17]} -pinname V17 -fixed yes -DIRECTION Inout -set_io {address[18]} -pinname V15 -fixed yes -DIRECTION Inout - -set_io {data[0]} -pinname V4 -fixed yes -DIRECTION Inout -set_io {data[1]} -pinname V3 -fixed yes -DIRECTION Inout -set_io {data[2]} -pinname V2 -fixed yes -DIRECTION Inout -set_io {data[3]} -pinname T3 -fixed yes -DIRECTION Inout -set_io {data[4]} -pinname N6 -fixed yes -DIRECTION Inout -set_io {data[5]} -pinname P6 -fixed yes -DIRECTION Inout -set_io {data[6]} -pinname R6 -fixed yes -DIRECTION Inout -set_io {data[7]} -pinname T4 -fixed yes -DIRECTION Inout -set_io {data[8]} -pinname T1 -fixed yes -DIRECTION Inout -set_io {data[9]} -pinname R1 -fixed yes -DIRECTION Inout -set_io {data[10]} -pinname P1 -fixed yes -DIRECTION Inout -set_io {data[11]} -pinname N2 -fixed yes -DIRECTION Inout -set_io {data[12]} -pinname R3 -fixed yes -DIRECTION Inout -set_io {data[13]} -pinname P4 -fixed yes -DIRECTION Inout -set_io {data[14]} -pinname N4 -fixed yes -DIRECTION Inout -set_io {data[15]} -pinname N3 -fixed yes -DIRECTION Inout -set_io {data[16]} -pinname G12 -fixed yes -DIRECTION Inout -set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout -set_io {data[18]} -pinname H15 -fixed yes -DIRECTION Inout -set_io {data[19]} -pinname F17 -fixed yes -DIRECTION Inout -set_io {data[20]} -pinname F18 -fixed yes -DIRECTION Inout -set_io {data[21]} -pinname G17 -fixed yes -DIRECTION Inout -set_io {data[22]} -pinname H18 -fixed yes -DIRECTION Inout -set_io {data[23]} -pinname J18 -fixed yes -DIRECTION Inout -set_io {data[24]} -pinname R18 -fixed yes -DIRECTION Inout -set_io {data[25]} -pinname N18 -fixed yes -DIRECTION Inout -set_io {data[26]} -pinname P17 -fixed yes -DIRECTION Inout -set_io {data[27]} -pinname N17 -fixed yes -DIRECTION Inout -set_io {data[28]} -pinname T18 -fixed yes -DIRECTION Inout -set_io {data[29]} -pinname M17 -fixed yes -DIRECTION Inout -set_io {data[30]} -pinname U18 -fixed yes -DIRECTION Inout -set_io {data[31]} -pinname L18 -fixed yes -DIRECTION Inout - -set_io nSRAM_MBE -pinname E4 -fixed yes -DIRECTION Inout -set_io nSRAM_E1 -pinname D1 -fixed yes -DIRECTION Inout -set_io nSRAM_E2 -pinname C1 -fixed yes -DIRECTION Inout -#set_io nSRAM_SCRUB -pinname C2 -fixed yes -DIRECTION Inout -set_io nSRAM_W -pinname D4 -fixed yes -DIRECTION Inout -set_io nSRAM_G -pinname E1 -fixed yes -DIRECTION Inout -set_io nSRAM_BUSY -pinname F4 -fixed yes -DIRECTION Inout - -set_io spw1_en -pinname G4 -fixed yes -DIRECTION Inout -set_io spw1_din -pinname D13 -fixed yes -DIRECTION Inout -set_io spw1_sin -pinname D14 -fixed yes -DIRECTION Inout -set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout -set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout - -set_io spw2_en -pinname G3 -fixed yes -DIRECTION Inout -set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout -set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout -set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout -set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout - -set_io {TAG[1]} -pinname J12 -fixed yes -DIRECTION Inout -set_io {TAG[2]} -pinname K12 -fixed yes -DIRECTION Inout -set_io {TAG[3]} -pinname K13 -fixed yes -DIRECTION Inout -set_io {TAG[4]} -pinname L16 -fixed yes -DIRECTION Inout -set_io {TAG[5]} -pinname L15 -fixed yes -DIRECTION Inout -set_io {TAG[6]} -pinname M16 -fixed yes -DIRECTION Inout -set_io {TAG[7]} -pinname J14 -fixed yes -DIRECTION Inout -set_io {TAG[8]} -pinname K15 -fixed yes -DIRECTION Inout -set_io {TAG[9]} -pinname J17 -fixed yes -DIRECTION Inout - -set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout - -set_io {ADC_OEB_bar_CH[0]} -pinname A10 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[1]} -pinname B10 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[2]} -pinname B12 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[3]} -pinname A11 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[5]} -pinname C6 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[6]} -pinname A13 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[7]} -pinname A14 -fixed yes -DIRECTION Inout - -set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout - -set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout -set_io ADC_OEB_bar_HK -pinname D6 -fixed yes -DIRECTION Inout -set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout -set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout - -#set_io {ADC_data[0]} -pinname G13 -fixed yes -DIRECTION Inout -#set_io {ADC_data[1]} -pinname G16 -fixed yes -DIRECTION Inout -#set_io {ADC_data[2]} -pinname F16 -fixed yes -DIRECTION Inout -#set_io {ADC_data[3]} -pinname E15 -fixed yes -DIRECTION Inout -#set_io {ADC_data[4]} -pinname F13 -fixed yes -DIRECTION Inout -#set_io {ADC_data[5]} -pinname F15 -fixed yes -DIRECTION Inout -#set_io {ADC_data[6]} -pinname D16 -fixed yes -DIRECTION Inout -#set_io {ADC_data[7]} -pinname D15 -fixed yes -DIRECTION Inout -#set_io {ADC_data[8]} -pinname B17 -fixed yes -DIRECTION Inout -#set_io {ADC_data[9]} -pinname A17 -fixed yes -DIRECTION Inout -#set_io {ADC_data[10]} -pinname A16 -fixed yes -DIRECTION Inout -#set_io {ADC_data[11]} -pinname B16 -fixed yes -DIRECTION Inout -#set_io {ADC_data[12]} -pinname C12 -fixed yes -DIRECTION Inout -#set_io {ADC_data[13]} -pinname C13 -fixed yes -DIRECTION Inout - -set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout -set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout -set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout -set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout diff --git a/boards/LFR-EQM/LFR_EQM_A3PE3000_debug.pdc b/boards/LFR-EQM/LFR_EQM_A3PE3000_debug.pdc deleted file mode 100644 --- a/boards/LFR-EQM/LFR_EQM_A3PE3000_debug.pdc +++ /dev/null @@ -1,124 +0,0 @@ -#set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout -set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout -set_io reset -pinname R4 -fixed yes -DIRECTION Inout - -set_io {address[0]} -pinname U3 -fixed yes -DIRECTION Inout -set_io {address[1]} -pinname V14 -fixed yes -DIRECTION Inout -set_io {address[2]} -pinname V13 -fixed yes -DIRECTION Inout -set_io {address[3]} -pinname V16 -fixed yes -DIRECTION Inout -set_io {address[4]} -pinname N9 -fixed yes -DIRECTION Inout -set_io {address[5]} -pinname T11 -fixed yes -DIRECTION Inout -set_io {address[6]} -pinname U13 -fixed yes -DIRECTION Inout -set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout -set_io {address[8]} -pinname U2 -fixed yes -DIRECTION Inout -set_io {address[9]} -pinname N11 -fixed yes -DIRECTION Inout -set_io {address[10]} -pinname R13 -fixed yes -DIRECTION Inout -set_io {address[11]} -pinname R12 -fixed yes -DIRECTION Inout -set_io {address[12]} -pinname M15 -fixed yes -DIRECTION Inout -set_io {address[13]} -pinname T12 -fixed yes -DIRECTION Inout -set_io {address[14]} -pinname M13 -fixed yes -DIRECTION Inout -set_io {address[15]} -pinname T13 -fixed yes -DIRECTION Inout -set_io {address[16]} -pinname L13 -fixed yes -DIRECTION Inout -set_io {address[17]} -pinname V17 -fixed yes -DIRECTION Inout -set_io {address[18]} -pinname V15 -fixed yes -DIRECTION Inout - -set_io {data[0]} -pinname V4 -fixed yes -DIRECTION Inout -set_io {data[1]} -pinname V3 -fixed yes -DIRECTION Inout -set_io {data[2]} -pinname V2 -fixed yes -DIRECTION Inout -set_io {data[3]} -pinname T3 -fixed yes -DIRECTION Inout -set_io {data[4]} -pinname N6 -fixed yes -DIRECTION Inout -set_io {data[5]} -pinname P6 -fixed yes -DIRECTION Inout -set_io {data[6]} -pinname R6 -fixed yes -DIRECTION Inout -set_io {data[7]} -pinname T4 -fixed yes -DIRECTION Inout -set_io {data[8]} -pinname T1 -fixed yes -DIRECTION Inout -set_io {data[9]} -pinname R1 -fixed yes -DIRECTION Inout -set_io {data[10]} -pinname P1 -fixed yes -DIRECTION Inout -set_io {data[11]} -pinname N2 -fixed yes -DIRECTION Inout -set_io {data[12]} -pinname R3 -fixed yes -DIRECTION Inout -set_io {data[13]} -pinname P4 -fixed yes -DIRECTION Inout -set_io {data[14]} -pinname N4 -fixed yes -DIRECTION Inout -set_io {data[15]} -pinname N3 -fixed yes -DIRECTION Inout -set_io {data[16]} -pinname G12 -fixed yes -DIRECTION Inout -set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout -set_io {data[18]} -pinname H15 -fixed yes -DIRECTION Inout -set_io {data[19]} -pinname F17 -fixed yes -DIRECTION Inout -set_io {data[20]} -pinname F18 -fixed yes -DIRECTION Inout -set_io {data[21]} -pinname G17 -fixed yes -DIRECTION Inout -set_io {data[22]} -pinname H18 -fixed yes -DIRECTION Inout -set_io {data[23]} -pinname J18 -fixed yes -DIRECTION Inout -set_io {data[24]} -pinname R18 -fixed yes -DIRECTION Inout -set_io {data[25]} -pinname N18 -fixed yes -DIRECTION Inout -set_io {data[26]} -pinname P17 -fixed yes -DIRECTION Inout -set_io {data[27]} -pinname N17 -fixed yes -DIRECTION Inout -set_io {data[28]} -pinname T18 -fixed yes -DIRECTION Inout -set_io {data[29]} -pinname M17 -fixed yes -DIRECTION Inout -set_io {data[30]} -pinname U18 -fixed yes -DIRECTION Inout -set_io {data[31]} -pinname L18 -fixed yes -DIRECTION Inout - -set_io nSRAM_MBE -pinname E4 -fixed yes -DIRECTION Inout -set_io nSRAM_E1 -pinname D1 -fixed yes -DIRECTION Inout -set_io nSRAM_E2 -pinname C1 -fixed yes -DIRECTION Inout -#set_io nSRAM_SCRUB -pinname C2 -fixed yes -DIRECTION Inout -set_io nSRAM_W -pinname D4 -fixed yes -DIRECTION Inout -set_io nSRAM_G -pinname E1 -fixed yes -DIRECTION Inout -set_io nSRAM_BUSY -pinname F4 -fixed yes -DIRECTION Inout - -set_io spw1_en -pinname G4 -fixed yes -DIRECTION Inout -set_io spw1_din -pinname D13 -fixed yes -DIRECTION Inout -set_io spw1_sin -pinname D14 -fixed yes -DIRECTION Inout -set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout -set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout - -set_io spw2_en -pinname G3 -fixed yes -DIRECTION Inout -set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout -set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout -set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout -set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout - -set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout -set_io TAG2 -pinname K12 -fixed yes -DIRECTION Inout -set_io TAG3 -pinname K13 -fixed yes -DIRECTION Inout -set_io TAG4 -pinname L16 -fixed yes -DIRECTION Inout -#set_io TAG5 -pinname L15 -fixed yes -DIRECTION Inout -set_io TAG6 -pinname M16 -fixed yes -DIRECTION Inout -set_io TAG7 -pinname J14 -fixed yes -DIRECTION Inout -set_io TAG8 -pinname K15 -fixed yes -DIRECTION Inout -#set_io TAG9 -pinname J17 -fixed yes -DIRECTION Inout - -set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout - -set_io {ADC_OEB_bar_CH[0]} -pinname A10 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[1]} -pinname B10 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[2]} -pinname B12 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[3]} -pinname A11 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[5]} -pinname C6 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[6]} -pinname A13 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[7]} -pinname A14 -fixed yes -DIRECTION Inout - -set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout - -set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout -set_io ADC_OEB_bar_HK -pinname D6 -fixed yes -DIRECTION Inout -set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout -set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout - -#set_io {ADC_data[0]} -pinname G13 -fixed yes -DIRECTION Inout -#set_io {ADC_data[1]} -pinname G16 -fixed yes -DIRECTION Inout -#set_io {ADC_data[2]} -pinname F16 -fixed yes -DIRECTION Inout -#set_io {ADC_data[3]} -pinname E15 -fixed yes -DIRECTION Inout -#set_io {ADC_data[4]} -pinname F13 -fixed yes -DIRECTION Inout -#set_io {ADC_data[5]} -pinname F15 -fixed yes -DIRECTION Inout -#set_io {ADC_data[6]} -pinname D16 -fixed yes -DIRECTION Inout -#set_io {ADC_data[7]} -pinname D15 -fixed yes -DIRECTION Inout -#set_io {ADC_data[8]} -pinname B17 -fixed yes -DIRECTION Inout -#set_io {ADC_data[9]} -pinname A17 -fixed yes -DIRECTION Inout -#set_io {ADC_data[10]} -pinname A16 -fixed yes -DIRECTION Inout -#set_io {ADC_data[11]} -pinname B16 -fixed yes -DIRECTION Inout -#set_io {ADC_data[12]} -pinname C12 -fixed yes -DIRECTION Inout -#set_io {ADC_data[13]} -pinname C13 -fixed yes -DIRECTION Inout - -set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout -set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout -set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout -set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout diff --git a/boards/LFR-EQM/LFR_EQM_A3PE3000_no49.pdc b/boards/LFR-EQM/LFR_EQM_A3PE3000_no49.pdc deleted file mode 100644 --- a/boards/LFR-EQM/LFR_EQM_A3PE3000_no49.pdc +++ /dev/null @@ -1,123 +0,0 @@ -set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout -set_io reset -pinname R4 -fixed yes -DIRECTION Inout -SCHMITT_TRIGGER On - -set_io {address[0]} -pinname U3 -fixed yes -DIRECTION Inout -set_io {address[1]} -pinname V14 -fixed yes -DIRECTION Inout -set_io {address[2]} -pinname V13 -fixed yes -DIRECTION Inout -set_io {address[3]} -pinname V16 -fixed yes -DIRECTION Inout -set_io {address[4]} -pinname N9 -fixed yes -DIRECTION Inout -set_io {address[5]} -pinname T11 -fixed yes -DIRECTION Inout -set_io {address[6]} -pinname U13 -fixed yes -DIRECTION Inout -set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout -set_io {address[8]} -pinname U2 -fixed yes -DIRECTION Inout -set_io {address[9]} -pinname N11 -fixed yes -DIRECTION Inout -set_io {address[10]} -pinname R13 -fixed yes -DIRECTION Inout -set_io {address[11]} -pinname R12 -fixed yes -DIRECTION Inout -set_io {address[12]} -pinname M15 -fixed yes -DIRECTION Inout -set_io {address[13]} -pinname T12 -fixed yes -DIRECTION Inout -set_io {address[14]} -pinname M13 -fixed yes -DIRECTION Inout -set_io {address[15]} -pinname T13 -fixed yes -DIRECTION Inout -set_io {address[16]} -pinname L13 -fixed yes -DIRECTION Inout -set_io {address[17]} -pinname V17 -fixed yes -DIRECTION Inout -set_io {address[18]} -pinname V15 -fixed yes -DIRECTION Inout - -set_io {data[0]} -pinname V4 -fixed yes -DIRECTION Inout -set_io {data[1]} -pinname V3 -fixed yes -DIRECTION Inout -set_io {data[2]} -pinname V2 -fixed yes -DIRECTION Inout -set_io {data[3]} -pinname T3 -fixed yes -DIRECTION Inout -set_io {data[4]} -pinname N6 -fixed yes -DIRECTION Inout -set_io {data[5]} -pinname P6 -fixed yes -DIRECTION Inout -set_io {data[6]} -pinname R6 -fixed yes -DIRECTION Inout -set_io {data[7]} -pinname T4 -fixed yes -DIRECTION Inout -set_io {data[8]} -pinname T1 -fixed yes -DIRECTION Inout -set_io {data[9]} -pinname R1 -fixed yes -DIRECTION Inout -set_io {data[10]} -pinname P1 -fixed yes -DIRECTION Inout -set_io {data[11]} -pinname N2 -fixed yes -DIRECTION Inout -set_io {data[12]} -pinname R3 -fixed yes -DIRECTION Inout -set_io {data[13]} -pinname P4 -fixed yes -DIRECTION Inout -set_io {data[14]} -pinname N4 -fixed yes -DIRECTION Inout -set_io {data[15]} -pinname N3 -fixed yes -DIRECTION Inout -set_io {data[16]} -pinname G12 -fixed yes -DIRECTION Inout -set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout -set_io {data[18]} -pinname H15 -fixed yes -DIRECTION Inout -set_io {data[19]} -pinname F17 -fixed yes -DIRECTION Inout -set_io {data[20]} -pinname F18 -fixed yes -DIRECTION Inout -set_io {data[21]} -pinname G17 -fixed yes -DIRECTION Inout -set_io {data[22]} -pinname H18 -fixed yes -DIRECTION Inout -set_io {data[23]} -pinname J18 -fixed yes -DIRECTION Inout -set_io {data[24]} -pinname R18 -fixed yes -DIRECTION Inout -set_io {data[25]} -pinname N18 -fixed yes -DIRECTION Inout -set_io {data[26]} -pinname P17 -fixed yes -DIRECTION Inout -set_io {data[27]} -pinname N17 -fixed yes -DIRECTION Inout -set_io {data[28]} -pinname T18 -fixed yes -DIRECTION Inout -set_io {data[29]} -pinname M17 -fixed yes -DIRECTION Inout -set_io {data[30]} -pinname U18 -fixed yes -DIRECTION Inout -set_io {data[31]} -pinname L18 -fixed yes -DIRECTION Inout - -set_io nSRAM_MBE -pinname E4 -fixed yes -DIRECTION Inout -set_io nSRAM_E1 -pinname D1 -fixed yes -DIRECTION Inout -set_io nSRAM_E2 -pinname C1 -fixed yes -DIRECTION Inout -#set_io nSRAM_SCRUB -pinname C2 -fixed yes -DIRECTION Inout -set_io nSRAM_W -pinname D4 -fixed yes -DIRECTION Inout -set_io nSRAM_G -pinname E1 -fixed yes -DIRECTION Inout -set_io nSRAM_BUSY -pinname F4 -fixed yes -DIRECTION Inout - -set_io spw1_en -pinname G4 -fixed yes -DIRECTION Inout -set_io spw1_din -pinname D13 -fixed yes -DIRECTION Inout -set_io spw1_sin -pinname D14 -fixed yes -DIRECTION Inout -set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout -set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout - -set_io spw2_en -pinname G3 -fixed yes -DIRECTION Inout -set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout -set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout -set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout -set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout - -set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout -set_io TAG2 -pinname K12 -fixed yes -DIRECTION Inout -set_io TAG3 -pinname K13 -fixed yes -DIRECTION Inout -set_io TAG4 -pinname L16 -fixed yes -DIRECTION Inout -#set_io TAG5 -pinname L15 -fixed yes -DIRECTION Inout -#set_io TAG6 -pinname M16 -fixed yes -DIRECTION Inout -#set_io TAG7 -pinname J14 -fixed yes -DIRECTION Inout -set_io TAG8 -pinname K15 -fixed yes -DIRECTION Inout -#set_io TAG9 -pinname J17 -fixed yes -DIRECTION Inout - -set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout - -set_io {ADC_OEB_bar_CH[0]} -pinname A10 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[1]} -pinname B10 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[2]} -pinname B12 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[3]} -pinname A11 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[5]} -pinname C6 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[6]} -pinname A13 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[7]} -pinname A14 -fixed yes -DIRECTION Inout - -set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout - -set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout -set_io ADC_OEB_bar_HK -pinname D6 -fixed yes -DIRECTION Inout -set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout -set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout - -set_io {ADC_data[0]} -pinname G13 -fixed yes -DIRECTION Inout -set_io {ADC_data[1]} -pinname G16 -fixed yes -DIRECTION Inout -set_io {ADC_data[2]} -pinname F16 -fixed yes -DIRECTION Inout -set_io {ADC_data[3]} -pinname E15 -fixed yes -DIRECTION Inout -set_io {ADC_data[4]} -pinname F13 -fixed yes -DIRECTION Inout -set_io {ADC_data[5]} -pinname F15 -fixed yes -DIRECTION Inout -set_io {ADC_data[6]} -pinname D16 -fixed yes -DIRECTION Inout -set_io {ADC_data[7]} -pinname D15 -fixed yes -DIRECTION Inout -set_io {ADC_data[8]} -pinname B17 -fixed yes -DIRECTION Inout -set_io {ADC_data[9]} -pinname A17 -fixed yes -DIRECTION Inout -set_io {ADC_data[10]} -pinname A16 -fixed yes -DIRECTION Inout -set_io {ADC_data[11]} -pinname B16 -fixed yes -DIRECTION Inout -set_io {ADC_data[12]} -pinname C12 -fixed yes -DIRECTION Inout -set_io {ADC_data[13]} -pinname C13 -fixed yes -DIRECTION Inout - -set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout -set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout -set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout -set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout diff --git a/boards/LFR-EQM/LFR_EQM_RTAX.pdc b/boards/LFR-EQM/LFR_EQM_RTAX.pdc deleted file mode 100644 --- a/boards/LFR-EQM/LFR_EQM_RTAX.pdc +++ /dev/null @@ -1,124 +0,0 @@ -set_io clk49_152MHz -pinname 314 -fixed yes -DIRECTION Inout -set_io clk50MHz -pinname 318 -fixed yes -DIRECTION Inout -set_io reset -pinname 128 -fixed yes -DIRECTION Inout - -set_io {address[0]} -pinname 124 -fixed yes -DIRECTION Inout -set_io {address[1]} -pinname 156 -fixed yes -DIRECTION Inout -set_io {address[2]} -pinname 154 -fixed yes -DIRECTION Inout -set_io {address[3]} -pinname 160 -fixed yes -DIRECTION Inout -set_io {address[4]} -pinname 162 -fixed yes -DIRECTION Inout -set_io {address[5]} -pinname 165 -fixed yes -DIRECTION Inout -set_io {address[6]} -pinname 155 -fixed yes -DIRECTION Inout -set_io {address[7]} -pinname 127 -fixed yes -DIRECTION Inout -set_io {address[8]} -pinname 123 -fixed yes -DIRECTION Inout -set_io {address[9]} -pinname 137 -fixed yes -DIRECTION Inout -set_io {address[10]} -pinname 141 -fixed yes -DIRECTION Inout -set_io {address[11]} -pinname 166 -fixed yes -DIRECTION Inout -set_io {address[12]} -pinname 182 -fixed yes -DIRECTION Inout -set_io {address[13]} -pinname 167 -fixed yes -DIRECTION Inout -set_io {address[14]} -pinname 181 -fixed yes -DIRECTION Inout -set_io {address[15]} -pinname 171 -fixed yes -DIRECTION Inout -set_io {address[16]} -pinname 183 -fixed yes -DIRECTION Inout -set_io {address[17]} -pinname 161 -fixed yes -DIRECTION Inout -set_io {address[18]} -pinname 159 -fixed yes -DIRECTION Inout - -set_io {data[0]} -pinname 103 -fixed yes -DIRECTION Inout -set_io {data[1]} -pinname 100 -fixed yes -DIRECTION Inout -set_io {data[2]} -pinname 99 -fixed yes -DIRECTION Inout -set_io {data[3]} -pinname 98 -fixed yes -DIRECTION Inout -set_io {data[4]} -pinname 97 -fixed yes -DIRECTION Inout -set_io {data[5]} -pinname 94 -fixed yes -DIRECTION Inout -set_io {data[6]} -pinname 93 -fixed yes -DIRECTION Inout -set_io {data[7]} -pinname 92 -fixed yes -DIRECTION Inout -set_io {data[8]} -pinname 82 -fixed yes -DIRECTION Inout -set_io {data[9]} -pinname 79 -fixed yes -DIRECTION Inout -set_io {data[10]} -pinname 78 -fixed yes -DIRECTION Inout -set_io {data[11]} -pinname 77 -fixed yes -DIRECTION Inout -set_io {data[12]} -pinname 71 -fixed yes -DIRECTION Inout -set_io {data[13]} -pinname 70 -fixed yes -DIRECTION Inout -set_io {data[14]} -pinname 67 -fixed yes -DIRECTION Inout -set_io {data[15]} -pinname 66 -fixed yes -DIRECTION Inout -set_io {data[16]} -pinname 246 -fixed yes -DIRECTION Inout -set_io {data[17]} -pinname 242 -fixed yes -DIRECTION Inout -set_io {data[18]} -pinname 241 -fixed yes -DIRECTION Inout -set_io {data[19]} -pinname 229 -fixed yes -DIRECTION Inout -set_io {data[20]} -pinname 228 -fixed yes -DIRECTION Inout -set_io {data[21]} -pinname 227 -fixed yes -DIRECTION Inout -set_io {data[22]} -pinname 224 -fixed yes -DIRECTION Inout -set_io {data[23]} -pinname 223 -fixed yes -DIRECTION Inout -set_io {data[24]} -pinname 206 -fixed yes -DIRECTION Inout -set_io {data[25]} -pinname 212 -fixed yes -DIRECTION Inout -set_io {data[26]} -pinname 207 -fixed yes -DIRECTION Inout -set_io {data[27]} -pinname 211 -fixed yes -DIRECTION Inout -set_io {data[28]} -pinname 205 -fixed yes -DIRECTION Inout -set_io {data[29]} -pinname 213 -fixed yes -DIRECTION Inout -set_io {data[30]} -pinname 202 -fixed yes -DIRECTION Inout -set_io {data[31]} -pinname 214 -fixed yes -DIRECTION Inout - -set_io nSRAM_MBE -pinname 9 -fixed yes -DIRECTION Inout -set_io nSRAM_E1 -pinname 20 -fixed yes -DIRECTION Inout -set_io nSRAM_E2 -pinname 15 -fixed yes -DIRECTION Inout -#set_io nSRAM_SCRUB -pinname 14 -fixed yes -DIRECTION Inout -set_io nSRAM_W -pinname 8 -fixed yes -DIRECTION Inout -set_io nSRAM_G -pinname 21 -fixed yes -DIRECTION Inout -set_io nSRAM_BUSY -pinname 24 -fixed yes -DIRECTION Inout - -set_io spw1_en -pinname 31 -fixed yes -DIRECTION Inout -set_io spw1_din -pinname 300 -fixed yes -DIRECTION Inout -set_io spw1_sin -pinname 299 -fixed yes -DIRECTION Inout -set_io spw1_dout -pinname 303 -fixed yes -DIRECTION Inout -set_io spw1_sout -pinname 317 -fixed yes -DIRECTION Inout - -set_io spw2_en -pinname 30 -fixed yes -DIRECTION Inout -set_io spw2_din -pinname 313 -fixed yes -DIRECTION Inout -set_io spw2_sin -pinname 304 -fixed yes -DIRECTION Inout -set_io spw2_dout -pinname 335 -fixed yes -DIRECTION Inout -set_io spw2_sout -pinname 330 -fixed yes -DIRECTION Inout - -#set_io {TAG[1]} -pinname 195 -fixed yes -DIRECTION Inout -set_io {TAG[2]} -pinname 190 -fixed yes -DIRECTION Inout -#set_io {TAG[3]} -pinname 189 -fixed yes -DIRECTION Inout -set_io {TAG[4]} -pinname 188 -fixed yes -DIRECTION Inout -#set_io {TAG[5]} -pinname 187 -fixed yes -DIRECTION Inout -#set_io {TAG[6]} -pinname 184 -fixed yes -DIRECTION Inout -#set_io {TAG[7]} -pinname 200 -fixed yes -DIRECTION Inout -#set_io {TAG[8]} -pinname 199 -fixed yes -DIRECTION Inout -#set_io {TAG[9]} -pinname 196 -fixed yes -DIRECTION Inout - -set_io bias_fail_sw -pinname 342 -fixed yes -DIRECTION Inout - -set_io {ADC_OEB_bar_CH[0]} -pinname 288 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[1]} -pinname 287 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[2]} -pinname 285 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[3]} -pinname 286 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[4]} -pinname 281 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[5]} -pinname 332 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[6]} -pinname 282 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[7]} -pinname 280 -fixed yes -DIRECTION Inout - -set_io ADC_smpclk -pinname 279 -fixed yes -DIRECTION Inout - -set_io HK_smpclk -pinname 172 -fixed yes -DIRECTION Inout -set_io ADC_OEB_bar_HK -pinname 331 -fixed yes -DIRECTION Inout -set_io {HK_SEL[0]} -pinname 6 -fixed yes -DIRECTION Inout -set_io {HK_SEL[1]} -pinname 343 -fixed yes -DIRECTION Inout - -set_io {ADC_data[0]} -pinname 251 -fixed yes -DIRECTION Inout -set_io {ADC_data[1]} -pinname 253 -fixed yes -DIRECTION Inout -set_io {ADC_data[2]} -pinname 257 -fixed yes -DIRECTION Inout -set_io {ADC_data[3]} -pinname 259 -fixed yes -DIRECTION Inout -set_io {ADC_data[4]} -pinname 252 -fixed yes -DIRECTION Inout -set_io {ADC_data[5]} -pinname 254 -fixed yes -DIRECTION Inout -set_io {ADC_data[6]} -pinname 258 -fixed yes -DIRECTION Inout -set_io {ADC_data[7]} -pinname 260 -fixed yes -DIRECTION Inout -set_io {ADC_data[8]} -pinname 270 -fixed yes -DIRECTION Inout -set_io {ADC_data[9]} -pinname 274 -fixed yes -DIRECTION Inout -set_io {ADC_data[10]} -pinname 276 -fixed yes -DIRECTION Inout -set_io {ADC_data[11]} -pinname 275 -fixed yes -DIRECTION Inout -set_io {ADC_data[12]} -pinname 273 -fixed yes -DIRECTION Inout -set_io {ADC_data[13]} -pinname 269 -fixed yes -DIRECTION Inout - -set_io DAC_SDO -pinname 341 -fixed yes -DIRECTION Inout -set_io DAC_SCK -pinname 338 -fixed yes -DIRECTION Inout -set_io DAC_SYNC -pinname 337 -fixed yes -DIRECTION Inout -set_io DAC_CAL_EN -pinname 336 -fixed yes -DIRECTION Inout diff --git a/boards/LFR-EQM/LFR_EQM_RTAX_layout.sdc b/boards/LFR-EQM/LFR_EQM_RTAX_layout.sdc deleted file mode 100644 --- a/boards/LFR-EQM/LFR_EQM_RTAX_layout.sdc +++ /dev/null @@ -1,77 +0,0 @@ -################################################################################ -# SDC WRITER VERSION "3.1"; -# DESIGN "LFR_EQM"; -# Timing constraints scenario: "Primary"; -# DATE "Fri Jul 24 14:50:40 2015"; -# VENDOR "Actel"; -# PROGRAM "Actel Designer Software Release v9.1 SP5"; -# VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. -################################################################################ - - -set sdc_version 1.7 - - -######## Clock Constraints ######## - -create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz } - -create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } - -create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_pad_25/U0:Y } - -create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } - -create_clock -name { spw_inputloop.1.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_1:Y } - -create_clock -name { spw_inputloop.0.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_1:Y } - - - -######## Generated Clock Constraints ######## - - - -######## Clock Source Latency Constraints ######### - - - -######## Input Delay Constraints ######## - - - -######## Output Delay Constraints ######## -set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address }] - -set_min_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 }] - - - -######## Delay Constraints ######## - - - -######## Delay Constraints ######## - - - -######## Multicycle Constraints ######## - - - -######## False Path Constraints ######## - - - -######## Output load Constraints ######## - - - -######## Disable Timing Constraints ######### - - - -######## Clock Uncertainty Constraints ######### - - - diff --git a/boards/LFR-EQM/LFR_EQM_altran.sdc b/boards/LFR-EQM/LFR_EQM_altran.sdc deleted file mode 100644 --- a/boards/LFR-EQM/LFR_EQM_altran.sdc +++ /dev/null @@ -1,97 +0,0 @@ -################################################################################ -# SDC WRITER VERSION "3.1"; -# DESIGN "LFR_EQM"; -# Timing constraints scenario: "Primary"; -# DATE "Thu Jun 04 11:49:44 2015"; -# VENDOR "Actel"; -# PROGRAM "Actel Designer Software Release v9.1 SP5"; -# VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. -################################################################################ - - -set sdc_version 1.7 - - -######## Clock Constraints ######## - -create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz } - -create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } - -create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q } - -create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } - -create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } - -create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } - - -######## Generated Clock Constraints ######## - - - -######## Clock Source Latency Constraints ######### - - - -######## Input Delay Constraints ######## - -set_input_delay -max 35.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] - -set_input_delay -max 35.000 -clock { clk_25:Q } [get_ports { ADC_data }] - - - -######## Output Delay Constraints ######## - -set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ -data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ -data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ -data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] - -set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ -address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ -address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ -address[7] address[8] address[9] }] - -set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W nSRAM_G nSRAM_MBE}] - -set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH ADC_OEB_bar_HK }] - -set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { DAC_SCK DAC_SDO DAC_SYNC }] - - -######## Delay Constraints ######## - -set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \ -[get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}] - -set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \ -[get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}] - - -######## Delay Constraints ######## - - - -######## Multicycle Constraints ######## - - - -######## False Path Constraints ######## - - - -######## Output load Constraints ######## - - - -######## Disable Timing Constraints ######### - - - -######## Clock Uncertainty Constraints ######### - - - diff --git a/boards/LFR-EQM/LFR_EQM_altran_RTAX.sdc b/boards/LFR-EQM/LFR_EQM_altran_RTAX.sdc deleted file mode 100644 --- a/boards/LFR-EQM/LFR_EQM_altran_RTAX.sdc +++ /dev/null @@ -1,97 +0,0 @@ -################################################################################ -# SDC WRITER VERSION "3.1"; -# DESIGN "LFR_EQM"; -# Timing constraints scenario: "Primary"; -# DATE "Thu Jun 04 11:49:44 2015"; -# VENDOR "Actel"; -# PROGRAM "Actel Designer Software Release v9.1 SP5"; -# VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. -################################################################################ - - -set sdc_version 1.7 - - -######## Clock Constraints ######## - -create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz } - -create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } - -create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q } - -create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } - -create_clock -name { spw_inputloop.1.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_1_0:Y } - -create_clock -name { spw_inputloop.0.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_1_0:Y } - - -######## Generated Clock Constraints ######## - - - -######## Clock Source Latency Constraints ######### - - - -######## Input Delay Constraints ######## - -set_input_delay -max 35.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] - -set_input_delay -max 35.000 -clock { clk_25:Q } [get_ports { ADC_data }] - - - -######## Output Delay Constraints ######## - -set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ -data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ -data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ -data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] - -set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ -address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ -address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ -address[7] address[8] address[9] }] - -set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W nSRAM_G nSRAM_MBE}] - -set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH ADC_OEB_bar_HK }] - -set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { DAC_SCK DAC_SDO DAC_SYNC }] - - -######## Delay Constraints ######## - -set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \ -[get_clocks {spw_inputloop.0.spw_phy0/rxclki_1_0:Y}] - -set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \ -[get_clocks {spw_inputloop.1.spw_phy0/rxclki_1_0:Y}] - - -######## Delay Constraints ######## - - - -######## Multicycle Constraints ######## - - - -######## False Path Constraints ######## - - - -######## Output load Constraints ######## - - - -######## Disable Timing Constraints ######### - - - -######## Clock Uncertainty Constraints ######### - - - diff --git a/boards/LFR-EQM/LFR_EQM_altran_clock.sdc b/boards/LFR-EQM/LFR_EQM_altran_clock.sdc deleted file mode 100644 --- a/boards/LFR-EQM/LFR_EQM_altran_clock.sdc +++ /dev/null @@ -1,25 +0,0 @@ -################################################################################ -# SDC WRITER VERSION "3.1"; -# DESIGN "LFR_EQM"; -# Timing constraints scenario: "Primary"; -# DATE "Thu Jun 04 11:49:44 2015"; -# VENDOR "Actel"; -# PROGRAM "Actel Designer Software Release v9.1 SP5"; -# VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. -################################################################################ - - -set sdc_version 1.7 - - -######## Clock Constraints ######## - -create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz } -create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } -create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q } -create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } -create_clock -name { spw_inputloop.1.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_1_0:Y } -create_clock -name { spw_inputloop.0.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_1_0:Y } - - - diff --git a/boards/LFR-EQM/LFR_EQM_altran_final_postlayout.sdc b/boards/LFR-EQM/LFR_EQM_altran_final_postlayout.sdc deleted file mode 100644 --- a/boards/LFR-EQM/LFR_EQM_altran_final_postlayout.sdc +++ /dev/null @@ -1,97 +0,0 @@ -################################################################################ -# SDC WRITER VERSION "3.1"; -# DESIGN "LFR_EQM"; -# Timing constraints scenario: "Primary"; -# DATE "Thu Jun 04 11:49:44 2015"; -# VENDOR "Actel"; -# PROGRAM "Actel Designer Software Release v9.1 SP5"; -# VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. -################################################################################ - - -set sdc_version 1.7 - - -######## Clock Constraints ######## - -create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz } - -create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } - -create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_pad_25/U0:Y } - -create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } - -create_clock -name { spw_inputloop.1.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_1:Y } - -create_clock -name { spw_inputloop.0.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_1:Y } - - -######## Generated Clock Constraints ######## - - - -######## Clock Source Latency Constraints ######### - - - -######## Input Delay Constraints ######## - -set_input_delay -max 10.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] - -set_input_delay -max 10.000 -clock { clk_25:Q } [get_ports { ADC_data }] - - - -######## Output Delay Constraints ######## - -set_max_delay 25.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ -data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ -data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ -data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] - -set_max_delay 25.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ -address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ -address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ -address[7] address[8] address[9] }] - -set_max_delay 25.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W nSRAM_G nSRAM_MBE}] - -set_max_delay 25.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH ADC_OEB_bar_HK }] - -set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { DAC_SCK DAC_SDO DAC_SYNC }] - - -######## Delay Constraints ######## - -set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \ -[get_clocks {spw_inputloop.0.spw_phy0/rxclki_1_0:Y}] - -set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \ -[get_clocks {spw_inputloop.1.spw_phy0/rxclki_1_0:Y}] - - -######## Delay Constraints ######## - - - -######## Multicycle Constraints ######## - - - -######## False Path Constraints ######## - - - -######## Output load Constraints ######## - - - -######## Disable Timing Constraints ######### - - - -######## Clock Uncertainty Constraints ######### - - - diff --git a/boards/LFR-EQM/LFR_EQM_altran_syn.sdc b/boards/LFR-EQM/LFR_EQM_altran_syn.sdc deleted file mode 100644 --- a/boards/LFR-EQM/LFR_EQM_altran_syn.sdc +++ /dev/null @@ -1,51 +0,0 @@ -# Synopsys, Inc. constraint file -# E:\opt\tortoiseHG_vhdlib\boards\LFR-EQM\LFR_EQM_altran_syn.sdc -# Written on Fri Jun 12 10:24:30 2015 -# by Synplify Pro, E-2010.09A-1 Scope Editor - -# -# Collections -# - -# -# Clocks -# -define_clock {clk50MHz} -freq 50 -clockgroup default_clkgroup_0 -define_clock {n:clk_25} -freq 25 -clockgroup default_clkgroup_1 -define_clock {n:clk_24} -freq 24.576 -clockgroup default_clkgroup_2 -define_clock {n:spw_inputloop\.0\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_3 -define_clock {n:spw_inputloop\.1\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_4 -define_clock {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup_5 - -# -# Clock to Clock -# - -# -# Inputs/Outputs -# - -# -# Registers -# - -# -# Delay Paths -# - -# -# Attributes -# - -# -# I/O Standards -# - - -# -# Compile Points -# - -# -# Other -# \ No newline at end of file diff --git a/boards/LFR-EQM/LFR_EQM_altran_syn_fanout.sdc b/boards/LFR-EQM/LFR_EQM_altran_syn_fanout.sdc deleted file mode 100644 --- a/boards/LFR-EQM/LFR_EQM_altran_syn_fanout.sdc +++ /dev/null @@ -1,56 +0,0 @@ -# Synopsys, Inc. constraint file -# E:/opt/tortoiseHG_vhdlib/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_5/../../../boards/LFR-EQM/LFR_EQM_altran_syn_fanout.sdc -# Written on Fri Jun 26 12:55:35 2015 -# by Synplify Pro, E-2010.09A-1 Scope Editor - -# -# Collections -# - -# -# Clocks -# -define_clock {clk50MHz} -name {clk50MHz} -freq 50 -clockgroup default_clkgroup_0 -define_clock {n:clk_25} -name {n:clk_25} -freq 25 -clockgroup default_clkgroup_1 -define_clock {n:clk_24} -name {n:clk_24} -freq 24.576 -clockgroup default_clkgroup_2 -define_clock {n:spw_inputloop\.0\.spw_phy0.rxclki_1} -name {n:spw_inputloop\.0\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_3 -define_clock {n:spw_inputloop\.1\.spw_phy0.rxclki_1} -name {n:spw_inputloop\.1\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_4 -define_clock {clk49_152MHz} -name {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup_5 - -# -# Clock to Clock -# - -# -# Inputs/Outputs -# - -# -# Registers -# - -# -# Delay Paths -# - -# -# Attributes -# -define_global_attribute {syn_useioff} {1} -define_attribute {n:leon3_soc_1\.l3\.cpu.0.leon3_radhard_i.cpu.holdn} {syn_maxfan} {10000} -define_attribute {n:spw_inputloop\.0\.spw_phy0.rxclki_1} {syn_maxfan} {10000} -define_attribute {n:spw_inputloop\.1\.spw_phy0.rxclki_1} {syn_maxfan} {10000} -define_attribute {n:leon3_soc_1\.l3\.cpu.0.leon3_radhard_i.cpu} {syn_hier} {flatten} -define_global_attribute -disable {syn_netlist_hierarchy} {1} - -# -# I/O Standards -# - -# -# Compile Points -# - -# -# Other -# diff --git a/boards/LFR-EQM/LFR_EQM_place_and_route-debug.sdc b/boards/LFR-EQM/LFR_EQM_place_and_route-debug.sdc deleted file mode 100644 --- a/boards/LFR-EQM/LFR_EQM_place_and_route-debug.sdc +++ /dev/null @@ -1,40 +0,0 @@ -# Top Level Design Parameters - -# Clocks - -create_clock -period 20.000000 -waveform {0.000000 10.000000} clk50MHz -create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz - - - -#create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25 -#create_generated_clock -name{clk_domain_25} -divide_by 2 -source{clk_25_int:CLK}{clk_25_int:Q} -#create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q -#create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin} - - -# False Paths Between Clocks - - -# False Path Constraints - - -# Maximum Delay Constraints - -# Multicycle Constraints - - -# Virtual Clocks -# Output Load Constraints -# Driving Cell Constraints -# Wire Loads -# set_wire_load_mode top - -# Other Constraints - - -## GRSPW constraints -create_clock -period 100.00 {spw_inputloop.1.spw_phy0/rxclki_RNO:Y} -create_clock -period 100.00 {spw_inputloop.0.spw_phy0/rxclki_RNO:Y} -set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.0.spw_phy0/rxclki_RNO:Y] -set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.1.spw_phy0/rxclki_RNO:Y] diff --git a/boards/LFR-EQM/LFR_EQM_place_and_route_19-5-2015.sdc b/boards/LFR-EQM/LFR_EQM_place_and_route_19-5-2015.sdc deleted file mode 100644 --- a/boards/LFR-EQM/LFR_EQM_place_and_route_19-5-2015.sdc +++ /dev/null @@ -1,151 +0,0 @@ -################################################################################ -# SDC WRITER VERSION "3.1"; -# DESIGN "LFR_EQM"; -# Timing constraints scenario: "Primary"; -# DATE "Tue May 19 15:46:14 2015"; -# VENDOR "Actel"; -# PROGRAM "Actel Designer Software Release v9.1 SP5"; -# VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. -################################################################################ - - -set sdc_version 1.7 - - -######## Clock Constraints ######## - -create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz } - -create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } - -create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q } - -create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } - -create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } - -create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } - - - -######## Generated Clock Constraints ######## - - - -######## Clock Source Latency Constraints ######### - - - -######## Input Delay Constraints ######## - -set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] - -set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }] - -set_input_delay -max 35.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }] -set_input_delay -min 15.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }] - - - -######## Output Delay Constraints ######## - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { ADC_OEB_bar_CH[0] ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }] -set_max_delay 25.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \ -ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \ -ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }] -set_min_delay 8.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \ -ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \ -ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }] - - - -######## Delay Constraints ######## - -set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ -data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ -data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ -data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] - -set_max_delay 12.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] - -set_max_delay 12.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ -data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ -data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ -data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] - -set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ -address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ -address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ -address[7] address[8] address[9] }] - -set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] - -set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] - -set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] - -set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \ -[get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}] - -set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \ -[get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}] - - - -######## Delay Constraints ######## - -set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ -data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ -data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ -data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] - -set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] - -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ -data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ -data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ -data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] - -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ -address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ -address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ -address[7] address[8] address[9] }] - -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] - -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] - -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] - - - -######## Multicycle Constraints ######## - - - -######## False Path Constraints ######## - - - -######## Output load Constraints ######## - - - -######## Disable Timing Constraints ######### - - - -######## Clock Uncertainty Constraints ######### - - - diff --git a/boards/LFR-EQM/LFR_EQM_place_and_route_5-5-2015.sdc b/boards/LFR-EQM/LFR_EQM_place_and_route_5-5-2015.sdc deleted file mode 100644 --- a/boards/LFR-EQM/LFR_EQM_place_and_route_5-5-2015.sdc +++ /dev/null @@ -1,156 +0,0 @@ -################################################################################ -# SDC WRITER VERSION "3.1"; -# DESIGN "LFR_EQM"; -# Timing constraints scenario: "Primary"; -# DATE "Tue May 05 13:46:34 2015"; -# VENDOR "Actel"; -# PROGRAM "Actel Designer Software Release v9.1 SP5"; -# VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. -################################################################################ - - -set sdc_version 1.7 - - -######## Clock Constraints ######## - -create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz } - -create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } - -create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q } - -create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } - -create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } - -create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } - - - -######## Generated Clock Constraints ######## - - - -######## Clock Source Latency Constraints ######### - - - -######## Input Delay Constraints ######## - -set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] - -set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }] - -set_input_delay -max 20.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }] - - - -######## Output Delay Constraints ######## - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { ADC_OEB_bar_CH[0] ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }] -set_max_delay 35.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \ -ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \ -ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }] -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \ -ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \ -ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }] - - - -######## Delay Constraints ######## - -set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ -data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ -data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ -data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] - -set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] - -set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ -data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ -data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ -data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] - -set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ -address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ -address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ -address[7] address[8] address[9] }] - -set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] - -set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] - -set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] - -set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \ -[get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}] - -set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \ -[get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}] - - - -######## Delay Constraints ######## - -set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ -data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ -data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ -data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] - -set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] - -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ -data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ -data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ -data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] - -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ -address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ -address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ -address[7] address[8] address[9] }] - -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] - -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] - -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] - - - -######## Multicycle Constraints ######## - - - -######## False Path Constraints ######## - -set_false_path -from [get_pins { \ -USE_ADCDRIVER_true.top_ad_conv_RHF1401_withFilter_1/cnv_s_reg:CLK }] -to [get_pins { \ -USE_ADCDRIVER_true.top_ad_conv_RHF1401_withFilter_1/SYNC_FF_cnv/sync_loop.1.A_temp[1]:D \ -}] -# SYNC PATH of ADC_CNV signal from CLK_domain_24 to CLK_domain_25 - - - -######## Output load Constraints ######## - - - -######## Disable Timing Constraints ######### - - - -######## Clock Uncertainty Constraints ######### - - - diff --git a/boards/LFR-EQM/LFR_EQM_place_and_route_ALTRAN.sdc b/boards/LFR-EQM/LFR_EQM_place_and_route_ALTRAN.sdc deleted file mode 100644 --- a/boards/LFR-EQM/LFR_EQM_place_and_route_ALTRAN.sdc +++ /dev/null @@ -1,128 +0,0 @@ -################################################################################ -# SDC WRITER VERSION "3.1"; -# DESIGN "LFR_EQM"; -# Timing constraints scenario: "Primary"; -# DATE "Fri Apr 24 16:02:16 2015"; -# VENDOR "Actel"; -# PROGRAM "Actel Designer Software Release v9.1 SP5"; -# VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. -################################################################################ - - -set sdc_version 1.7 - - -######## Clock Constraints ######## - -create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz } - -create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } - -create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q } - -create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } - -create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } - -create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } - - - -######## Generated Clock Constraints ######## - - - -######## Clock Source Latency Constraints ######### - - - -######## Input Delay Constraints ######## - -set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] -set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ -data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ -data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ -data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] -set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ -data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ -data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ -data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] - -set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }] -set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] -set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] - - - -######## Output Delay Constraints ######## - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] -set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ -data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ -data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ -data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ -data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ -data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ -data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }] -set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ -address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ -address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ -address[7] address[8] address[9] }] -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ -address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ -address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ -address[7] address[8] address[9] }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] -set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }] -set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }] -set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] - - - -######## Delay Constraints ######## - -set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \ -nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \ -{spw_inputloop.0.spw_phy0/rxclki_RNO:Y}] - -set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \ -nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \ -{spw_inputloop.1.spw_phy0/rxclki_RNO:Y}] - - - -######## Delay Constraints ######## - - - -######## Multicycle Constraints ######## - - - -######## False Path Constraints ######## - - - -######## Output load Constraints ######## - - - -######## Disable Timing Constraints ######### - - - -######## Clock Uncertainty Constraints ######### - - - diff --git a/boards/LFR-EQM/LFR_EQM_place_and_route_RTAX_ALTRAN.sdc b/boards/LFR-EQM/LFR_EQM_place_and_route_RTAX_ALTRAN.sdc deleted file mode 100644 --- a/boards/LFR-EQM/LFR_EQM_place_and_route_RTAX_ALTRAN.sdc +++ /dev/null @@ -1,129 +0,0 @@ -################################################################################ -# SDC WRITER VERSION "3.1"; -# DESIGN "LFR_EQM"; -# Timing constraints scenario: "Primary"; -# DATE "Fri Apr 24 16:02:16 2015"; -# VENDOR "Actel"; -# PROGRAM "Actel Designer Software Release v9.1 SP5"; -# VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. -################################################################################ - - -set sdc_version 1.7 - - -######## Clock Constraints ######## - -create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz } - -create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } - -create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q } - -create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } - - -create_clock -name { spw_inputloop.0.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_1_0:Y } - -create_clock -name { spw_inputloop.1.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_1_0:Y } - - - -######## Generated Clock Constraints ######## - - - -######## Clock Source Latency Constraints ######### - - - -######## Input Delay Constraints ######## - -set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] -set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ -data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ -data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ -data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] -set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ -data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ -data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ -data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] - -set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }] -set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] -set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] - - - -######## Output Delay Constraints ######## - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] -set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ -data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ -data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ -data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ -data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ -data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ -data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }] -set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ -address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ -address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ -address[7] address[8] address[9] }] -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ -address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ -address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ -address[7] address[8] address[9] }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] -set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }] -set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }] -set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] - - - -######## Delay Constraints ######## - -set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \ -nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \ -{spw_inputloop.0.spw_phy0/rxclki_1_0:Y}] - -set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \ -nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \ -{spw_inputloop.1.spw_phy0/rxclki_1_0:YY}] - - - -######## Delay Constraints ######## - - - -######## Multicycle Constraints ######## - - - -######## False Path Constraints ######## - - - -######## Output load Constraints ######## - - - -######## Disable Timing Constraints ######### - - - -######## Clock Uncertainty Constraints ######### - - - diff --git a/boards/LFR-EQM/LFR_EQM_place_and_route_no49.sdc b/boards/LFR-EQM/LFR_EQM_place_and_route_no49.sdc deleted file mode 100644 --- a/boards/LFR-EQM/LFR_EQM_place_and_route_no49.sdc +++ /dev/null @@ -1,124 +0,0 @@ -################################################################################ -# SDC WRITER VERSION "3.1"; -# DESIGN "LFR_EQM"; -# Timing constraints scenario: "Primary"; -# DATE "Fri Apr 24 16:02:16 2015"; -# VENDOR "Actel"; -# PROGRAM "Actel Designer Software Release v9.1 SP5"; -# VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. -################################################################################ - - -set sdc_version 1.7 - - -######## Clock Constraints ######## - -create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz } - -##create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } - -create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q } - -##create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } - -create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } - -create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } - - - -######## Generated Clock Constraints ######## - - - -######## Clock Source Latency Constraints ######### - - - -######## Input Delay Constraints ######## - -set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] -set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ -data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ -data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ -data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] -set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ -data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ -data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ -data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] - -set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }] -set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] -set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] - - - -######## Output Delay Constraints ######## - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] -set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ -data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ -data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ -data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ -data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ -data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ -data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }] -set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ -address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ -address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ -address[7] address[8] address[9] }] -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ -address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ -address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ -address[7] address[8] address[9] }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] -set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }] -set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }] -set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] - - - -######## Delay Constraints ######## - -set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}] - -set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}] - - - -######## Delay Constraints ######## - - - -######## Multicycle Constraints ######## - - - -######## False Path Constraints ######## - - - -######## Output load Constraints ######## - - - -######## Disable Timing Constraints ######### - - - -######## Clock Uncertainty Constraints ######### - - - diff --git a/boards/LFR-EQM/LFR_EQM_place_and_route_no49_GUI.sdc b/boards/LFR-EQM/LFR_EQM_place_and_route_no49_GUI.sdc deleted file mode 100644 --- a/boards/LFR-EQM/LFR_EQM_place_and_route_no49_GUI.sdc +++ /dev/null @@ -1,157 +0,0 @@ -################################################################################ -# SDC WRITER VERSION "3.1"; -# DESIGN "LFR_EQM"; -# Timing constraints scenario: "Primary"; -# DATE "Wed May 13 13:09:37 2015"; -# VENDOR "Actel"; -# PROGRAM "Actel Designer Software Release v9.1 SP5"; -# VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. -################################################################################ - - -set sdc_version 1.7 - - -######## Clock Constraints ######## - -create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz } - -create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q } - -create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } - -create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } - - - -######## Generated Clock Constraints ######## - - - -######## Clock Source Latency Constraints ######### - - - -######## Input Delay Constraints ######## - -set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] - -set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }] - -set_input_delay -max 0.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }] -set_input_delay -min 0.000 -clock { clk_25:Q } [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] ADC_data[7] ADC_data[8] ADC_data[9] }] - - - -######## Output Delay Constraints ######## - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { ADC_OEB_bar_CH[0] ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }] - - - -######## Delay Constraints ######## - -set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ -data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ -data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ -data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] - -set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] - -set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ -data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ -data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ -data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] - -set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ -address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ -address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ -address[7] address[8] address[9] }] - -set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] - -set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] - -set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] - -set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \ -[get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}] - -set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \ -[get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}] - -set_max_delay 30.000 -from [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] \ -ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] \ -ADC_data[7] ADC_data[8] ADC_data[9] }] -to [get_clocks {clk_25:Q}] - -set_max_delay 15.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \ -ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \ -ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }] - - - -######## Delay Constraints ######## - -set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ -data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ -data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ -data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] - -set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] - -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ -data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ -data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ -data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] - -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ -address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ -address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ -address[7] address[8] address[9] }] - -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] - -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] - -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] - -set_min_delay 0.000 -from [get_ports { ADC_data[0] ADC_data[10] ADC_data[11] ADC_data[12] \ -ADC_data[13] ADC_data[1] ADC_data[2] ADC_data[3] ADC_data[4] ADC_data[5] ADC_data[6] \ -ADC_data[7] ADC_data[8] ADC_data[9] }] -to [get_clocks {clk_25:Q}] - -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH[0] \ -ADC_OEB_bar_CH[1] ADC_OEB_bar_CH[2] ADC_OEB_bar_CH[3] ADC_OEB_bar_CH[4] \ -ADC_OEB_bar_CH[5] ADC_OEB_bar_CH[6] ADC_OEB_bar_CH[7] ADC_OEB_bar_HK }] - - - -######## Multicycle Constraints ######## - - - -######## False Path Constraints ######## - - - -######## Output load Constraints ######## - - - -######## Disable Timing Constraints ######### - - - -######## Clock Uncertainty Constraints ######### - - - diff --git a/boards/LFR-EQM/LFR_EQM_place_and_route_test.sdc b/boards/LFR-EQM/LFR_EQM_place_and_route_test.sdc deleted file mode 100644 --- a/boards/LFR-EQM/LFR_EQM_place_and_route_test.sdc +++ /dev/null @@ -1,39 +0,0 @@ -# Top Level Design Parameters - -# Clocks -create_clock -name{clk_50} -period 20.000000 -waveform { 0.000 10.000000 } {clk50MHz} -create_clock -name{clk_49} -period 20.344999 -waveform { 0.000 10.172500 } {clk49_152MHz} -create_clock -name{spw_rx_clk} -period 100.00000 -waveform { 0.000 50.000000 } {spw_inputloop_0_spw_phy0/rxclki spw_inputloop_1_spw_phy0/rxclki} - -create_generated_clock -name{clk_25:Q} -divide_by 2 -source{clk_25:CLK}{clk_25:Q} -create_generated_clock -name{clk_24:Q} -divide_by 2 -source{clk_24:CLK}{clk_24:Q} - - - - -#create_clock -period 10.000000 -waveform {0.000000 5.000000} clk50MHz -#create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz -#create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25:Q -#create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q -#create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin} - - -# False Paths Between Clocks - - -# False Path Constraints - - -# Maximum Delay Constraints - - -# Multicycle Constraints - - -# Virtual Clocks -# Output Load Constraints -# Driving Cell Constraints -# Wire Loads -# set_wire_load_mode top - -# Other Constraints diff --git a/boards/LFR-EQM/LFR_EQM_synthesis.sdc b/boards/LFR-EQM/LFR_EQM_synthesis.sdc deleted file mode 100644 --- a/boards/LFR-EQM/LFR_EQM_synthesis.sdc +++ /dev/null @@ -1,61 +0,0 @@ -# Synplicity, Inc. constraint file -# /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc -# Written on Wed Aug 1 19:29:24 2007 -# by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor - -# -# Collections -# - -# -# Clocks -# - -define_clock -name {clk50MHz} -freq 50 -clockgroup default_clkgroup_50 -route 5 -define_clock -name {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup_49 -route 5 - -# -# Clock to Clock -# - -# -# Inputs/Outputs -# - - -# -# Registers -# - -# -# Multicycle Path -# - -# -# False Path -# - -set_false_path -from reset - -# -# Path Delay -# - -# -# Attributes -# - -define_global_attribute syn_useioff {1} -define_global_attribute -disable syn_netlist_hierarchy {0} - -# -# I/O standards -# - -# -# Compile Points -# - -# -# Other Constraints -# diff --git a/boards/LFR-EQM/Makefile_RTAX.inc b/boards/LFR-EQM/Makefile_RTAX.inc deleted file mode 100644 --- a/boards/LFR-EQM/Makefile_RTAX.inc +++ /dev/null @@ -1,41 +0,0 @@ -PACKAGE=CQFP352 -SPEED=Std -SYNFREQ=50 - -TECHNOLOGY=Axcelerator - -DESIGNER_PACKAGE=CQFP -DESIGNER_PINS=352 -DESIGNER_VOLTAGE=COM -DESIGNER_TEMP=COM - -#ifeq ("$(FPGA_RTAX4000)","S") -# LIBERO_DIE=70800rts -# PART=RTAX4000S -# LIBERO_PACKAGE=cqfp$(DESIGNER_PINS)r -#endif - -#ifeq ("$(FPGA_RTAX4000)","D") -LIBERO_DIE=70800d -PART=RTAX4000D -LIBERO_PACKAGE=cq$(DESIGNER_PINS) -#endif - -MANUFACTURER=Actel -MGCPART=$(PART) -MGCTECHNOLOGY=Axcelerator -MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)} - -## RTAX4000S OPTIONS -#LIBERO_DIE=70800rts -#PART=RTAX4000S - -## RTAX4000D OPTIONS -#LIBERO_DIE=70800d -#PART=RTAX4000D - -# RTAX4000D -#LIBERO_PACKAGE=cq$(DESIGNER_PINS) - -# RTAX4000S -#LIBERO_PACKAGE=cqfp$(DESIGNER_PINS)r diff --git a/designs/SOLO_LFR_LFR-EQM/LFR-EQM.vhd b/designs/SOLO_LFR_LFR-EQM/LFR-EQM.vhd --- a/designs/SOLO_LFR_LFR-EQM/LFR-EQM.vhd +++ b/designs/SOLO_LFR_LFR-EQM/LFR-EQM.vhd @@ -452,12 +452,9 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"020153", -- aa.bb.cc version - -- AA : BOARD NUMBER - -- 0 => MINI_LFR - -- 1 => EM - -- 2 => EQM (with A3PE3000) - DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA) + top_lfr_version => LPP_LFR_BOARD_LFR_EQM & "015B", + DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA, + DATA_SHAPING_SATURATION => 1) PORT MAP ( clk => clk_25, rstn => LFR_rstn,