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@@
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+1,602
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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4
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--
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-- This program is free software; you can redistribute it and/or modify
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful,
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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LIBRARY IEEE;
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LIBRARY IEEE;
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USE IEEE.numeric_std.ALL;
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USE IEEE.numeric_std.ALL;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.std_logic_1164.ALL;
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LIBRARY grlib;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.stdlib.ALL;
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LIBRARY techmap;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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USE techmap.gencomp.ALL;
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LIBRARY gaisler;
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LIBRARY gaisler;
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USE gaisler.sim.ALL;
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USE gaisler.sim.ALL;
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USE gaisler.memctrl.ALL;
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USE gaisler.memctrl.ALL;
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USE gaisler.leon3.ALL;
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USE gaisler.leon3.ALL;
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USE gaisler.uart.ALL;
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USE gaisler.uart.ALL;
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USE gaisler.misc.ALL;
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USE gaisler.misc.ALL;
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USE gaisler.spacewire.ALL;
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USE gaisler.spacewire.ALL;
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LIBRARY esa;
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LIBRARY esa;
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USE esa.memoryctrl.ALL;
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USE esa.memoryctrl.ALL;
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LIBRARY lpp;
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LIBRARY lpp;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
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USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
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USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
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USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
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USE lpp.iir_filter.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.general_purpose.ALL;
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USE lpp.general_purpose.ALL;
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USE lpp.lpp_lfr_management.ALL;
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USE lpp.lpp_lfr_management.ALL;
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USE lpp.lpp_leon3_soc_pkg.ALL;
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USE lpp.lpp_leon3_soc_pkg.ALL;
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USE lpp.lpp_bootloader_pkg.ALL;
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USE lpp.lpp_bootloader_pkg.ALL;
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--library proasic3l;
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--library proasic3l;
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--use proasic3l.all;
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--use proasic3l.all;
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ENTITY LFR_EQM IS
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ENTITY LFR_EQM IS
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GENERIC (
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GENERIC (
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Mem_use : INTEGER := use_RAM;
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Mem_use : INTEGER := use_RAM;
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USE_BOOTLOADER : INTEGER := 0;
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USE_BOOTLOADER : INTEGER := 0;
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USE_ADCDRIVER : INTEGER := 1;
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USE_ADCDRIVER : INTEGER := 1;
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tech : INTEGER := apa3e;
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tech : INTEGER := apa3e;
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tech_leon : INTEGER := apa3e;
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tech_leon : INTEGER := apa3e;
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DEBUG_FORCE_DATA_DMA : INTEGER := 0;
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DEBUG_FORCE_DATA_DMA : INTEGER := 0;
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USE_DEBUG_VECTOR : INTEGER := 0
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USE_DEBUG_VECTOR : INTEGER := 0
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);
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);
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PORT (
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PORT (
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clk50MHz : IN STD_ULOGIC;
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clk50MHz : IN STD_ULOGIC;
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clk49_152MHz : IN STD_ULOGIC;
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clk49_152MHz : IN STD_ULOGIC;
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reset : IN STD_ULOGIC;
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reset : IN STD_ULOGIC;
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TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
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TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
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-- TAG --------------------------------------------------------------------
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-- TAG --------------------------------------------------------------------
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--TAG1 : IN STD_ULOGIC; -- DSU rx data
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--TAG1 : IN STD_ULOGIC; -- DSU rx data
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--TAG3 : OUT STD_ULOGIC; -- DSU tx data
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--TAG3 : OUT STD_ULOGIC; -- DSU tx data
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-- UART APB ---------------------------------------------------------------
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-- UART APB ---------------------------------------------------------------
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--TAG2 : IN STD_ULOGIC; -- UART1 rx data
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--TAG2 : IN STD_ULOGIC; -- UART1 rx data
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--TAG4 : OUT STD_ULOGIC; -- UART1 tx data
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--TAG4 : OUT STD_ULOGIC; -- UART1 tx data
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-- RAM --------------------------------------------------------------------
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-- RAM --------------------------------------------------------------------
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address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
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address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
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data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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nSRAM_MBE : INOUT STD_LOGIC; -- new
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nSRAM_MBE : INOUT STD_LOGIC; -- new
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nSRAM_E1 : OUT STD_LOGIC; -- new
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nSRAM_E1 : OUT STD_LOGIC; -- new
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nSRAM_E2 : OUT STD_LOGIC; -- new
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nSRAM_E2 : OUT STD_LOGIC; -- new
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-- nSRAM_SCRUB : OUT STD_LOGIC; -- new
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-- nSRAM_SCRUB : OUT STD_LOGIC; -- new
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nSRAM_W : OUT STD_LOGIC; -- new
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nSRAM_W : OUT STD_LOGIC; -- new
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nSRAM_G : OUT STD_LOGIC; -- new
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nSRAM_G : OUT STD_LOGIC; -- new
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nSRAM_BUSY : IN STD_LOGIC; -- new
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nSRAM_BUSY : IN STD_LOGIC; -- new
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-- SPW --------------------------------------------------------------------
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-- SPW --------------------------------------------------------------------
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spw1_en : OUT STD_LOGIC; -- new
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spw1_en : OUT STD_LOGIC; -- new
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spw1_din : IN STD_LOGIC;
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spw1_din : IN STD_LOGIC;
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spw1_sin : IN STD_LOGIC;
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spw1_sin : IN STD_LOGIC;
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spw1_dout : OUT STD_LOGIC;
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spw1_dout : OUT STD_LOGIC;
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spw1_sout : OUT STD_LOGIC;
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spw1_sout : OUT STD_LOGIC;
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spw2_en : OUT STD_LOGIC; -- new
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spw2_en : OUT STD_LOGIC; -- new
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spw2_din : IN STD_LOGIC;
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spw2_din : IN STD_LOGIC;
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spw2_sin : IN STD_LOGIC;
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spw2_sin : IN STD_LOGIC;
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spw2_dout : OUT STD_LOGIC;
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spw2_dout : OUT STD_LOGIC;
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spw2_sout : OUT STD_LOGIC;
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spw2_sout : OUT STD_LOGIC;
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-- ADC --------------------------------------------------------------------
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-- ADC --------------------------------------------------------------------
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bias_fail_sw : OUT STD_LOGIC;
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bias_fail_sw : OUT STD_LOGIC;
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ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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ADC_smpclk : OUT STD_LOGIC;
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ADC_smpclk : OUT STD_LOGIC;
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ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
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ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
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-- DAC --------------------------------------------------------------------
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-- DAC --------------------------------------------------------------------
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DAC_SDO : OUT STD_LOGIC;
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DAC_SDO : OUT STD_LOGIC;
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DAC_SCK : OUT STD_LOGIC;
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DAC_SCK : OUT STD_LOGIC;
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DAC_SYNC : OUT STD_LOGIC;
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DAC_SYNC : OUT STD_LOGIC;
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DAC_CAL_EN : OUT STD_LOGIC;
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DAC_CAL_EN : OUT STD_LOGIC;
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-- HK ---------------------------------------------------------------------
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-- HK ---------------------------------------------------------------------
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HK_smpclk : OUT STD_LOGIC;
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HK_smpclk : OUT STD_LOGIC;
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ADC_OEB_bar_HK : OUT STD_LOGIC;
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ADC_OEB_bar_HK : OUT STD_LOGIC;
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HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--;
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HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--;
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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-- TAG8 : OUT STD_LOGIC
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-- TAG8 : OUT STD_LOGIC
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);
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);
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END LFR_EQM;
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END LFR_EQM;
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ARCHITECTURE beh OF LFR_EQM IS
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ARCHITECTURE beh OF LFR_EQM IS
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121
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SIGNAL clk_25 : STD_LOGIC := '0';
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SIGNAL clk_25 : STD_LOGIC := '0';
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SIGNAL clk_24 : STD_LOGIC := '0';
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SIGNAL clk_24 : STD_LOGIC := '0';
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
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127
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127
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-- CONSTANTS
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128
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-- CONSTANTS
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CONSTANT CFG_PADTECH : INTEGER := inferred;
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129
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CONSTANT CFG_PADTECH : INTEGER := inferred;
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CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
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CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
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CONSTANT NB_AHB_SLAVE : INTEGER := 1;
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CONSTANT NB_AHB_SLAVE : INTEGER := 1;
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CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
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CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
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133
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133
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SIGNAL apbi_ext : apb_slv_in_type;
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SIGNAL apbi_ext : apb_slv_in_type;
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SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
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SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
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SIGNAL ahbi_s_ext : ahb_slv_in_type;
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SIGNAL ahbi_s_ext : ahb_slv_in_type;
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SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
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SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
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SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
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138
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SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
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SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
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SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
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140
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140
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141
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-- Spacewire signals
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141
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-- Spacewire signals
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SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
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142
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SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
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143
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SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
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143
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SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
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144
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SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
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144
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SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
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145
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SIGNAL spw_rxtxclk : STD_ULOGIC;
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145
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SIGNAL spw_rxtxclk : STD_ULOGIC;
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146
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SIGNAL spw_rxclkn : STD_ULOGIC;
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146
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SIGNAL spw_rxclkn : STD_ULOGIC;
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147
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SIGNAL spw_clk : STD_LOGIC;
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147
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SIGNAL spw_clk : STD_LOGIC;
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148
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SIGNAL swni : grspw_in_type;
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148
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SIGNAL swni : grspw_in_type;
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149
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SIGNAL swno : grspw_out_type;
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149
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SIGNAL swno : grspw_out_type;
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150
|
|
|
150
|
|
|
|
151
|
--GPIO
|
|
151
|
--GPIO
|
|
|
152
|
SIGNAL gpioi : gpio_in_type;
|
|
152
|
SIGNAL gpioi : gpio_in_type;
|
|
|
153
|
SIGNAL gpioo : gpio_out_type;
|
|
153
|
SIGNAL gpioo : gpio_out_type;
|
|
|
154
|
|
|
154
|
|
|
|
155
|
-- AD Converter ADS7886
|
|
155
|
-- AD Converter ADS7886
|
|
|
156
|
SIGNAL sample : Samples14v(8 DOWNTO 0);
|
|
156
|
SIGNAL sample : Samples14v(8 DOWNTO 0);
|
|
|
157
|
SIGNAL sample_s : Samples(8 DOWNTO 0);
|
|
157
|
SIGNAL sample_s : Samples(8 DOWNTO 0);
|
|
|
158
|
SIGNAL sample_val : STD_LOGIC;
|
|
158
|
SIGNAL sample_val : STD_LOGIC;
|
|
|
159
|
SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
|
|
159
|
SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
|
|
|
160
|
|
|
160
|
|
|
|
161
|
-----------------------------------------------------------------------------
|
|
161
|
-----------------------------------------------------------------------------
|
|
|
162
|
SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
|
162
|
SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
|
|
163
|
|
|
163
|
|
|
|
164
|
-----------------------------------------------------------------------------
|
|
164
|
-----------------------------------------------------------------------------
|
|
|
165
|
SIGNAL rstn_25 : STD_LOGIC;
|
|
165
|
SIGNAL rstn_25 : STD_LOGIC;
|
|
|
166
|
SIGNAL rstn_24 : STD_LOGIC;
|
|
166
|
SIGNAL rstn_24 : STD_LOGIC;
|
|
|
167
|
|
|
167
|
|
|
|
168
|
SIGNAL LFR_soft_rstn : STD_LOGIC;
|
|
168
|
SIGNAL LFR_soft_rstn : STD_LOGIC;
|
|
|
169
|
SIGNAL LFR_rstn : STD_LOGIC;
|
|
169
|
SIGNAL LFR_rstn : STD_LOGIC;
|
|
|
170
|
|
|
170
|
|
|
|
171
|
SIGNAL ADC_smpclk_s : STD_LOGIC;
|
|
171
|
SIGNAL ADC_smpclk_s : STD_LOGIC;
|
|
|
172
|
|
|
172
|
|
|
|
173
|
SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
|
|
173
|
SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
|
|
|
174
|
|
|
174
|
|
|
|
175
|
SIGNAL clk50MHz_int : STD_LOGIC := '0';
|
|
175
|
SIGNAL clk50MHz_int : STD_LOGIC := '0';
|
|
|
176
|
SIGNAL clk_25_int : STD_LOGIC := '0';
|
|
176
|
SIGNAL clk_25_int : STD_LOGIC := '0';
|
|
|
177
|
|
|
177
|
|
|
|
178
|
component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
|
|
178
|
component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
|
|
|
179
|
|
|
179
|
|
|
|
180
|
SIGNAL rstn_50 : STD_LOGIC;
|
|
180
|
SIGNAL rstn_50 : STD_LOGIC;
|
|
|
181
|
SIGNAL clk_lock : STD_LOGIC;
|
|
181
|
SIGNAL clk_lock : STD_LOGIC;
|
|
|
182
|
SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
|
|
182
|
SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
|
|
|
183
|
SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
|
|
183
|
SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
|
|
|
184
|
|
|
184
|
|
|
|
185
|
SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
|
|
185
|
SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
|
|
|
186
|
SIGNAL ahbrxd: STD_LOGIC;
|
|
186
|
SIGNAL ahbrxd: STD_LOGIC;
|
|
|
187
|
SIGNAL ahbtxd: STD_LOGIC;
|
|
187
|
SIGNAL ahbtxd: STD_LOGIC;
|
|
|
188
|
SIGNAL urxd1 : STD_LOGIC;
|
|
188
|
SIGNAL urxd1 : STD_LOGIC;
|
|
|
189
|
SIGNAL utxd1 : STD_LOGIC;
|
|
189
|
SIGNAL utxd1 : STD_LOGIC;
|
|
|
190
|
BEGIN -- beh
|
|
190
|
BEGIN -- beh
|
|
|
191
|
|
|
191
|
|
|
|
192
|
-----------------------------------------------------------------------------
|
|
192
|
-----------------------------------------------------------------------------
|
|
|
193
|
-- CLK_LOCK
|
|
193
|
-- CLK_LOCK
|
|
|
194
|
-----------------------------------------------------------------------------
|
|
194
|
-----------------------------------------------------------------------------
|
|
|
195
|
rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
|
|
195
|
rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
|
|
|
196
|
|
|
196
|
|
|
|
197
|
PROCESS (clk50MHz_int, rstn_50)
|
|
197
|
PROCESS (clk50MHz_int, rstn_50)
|
|
|
198
|
BEGIN -- PROCESS
|
|
198
|
BEGIN -- PROCESS
|
|
|
199
|
IF rstn_50 = '0' THEN -- asynchronous reset (active low)
|
|
199
|
IF rstn_50 = '0' THEN -- asynchronous reset (active low)
|
|
|
200
|
clk_lock <= '0';
|
|
200
|
clk_lock <= '0';
|
|
|
201
|
clk_busy_counter <= (OTHERS => '0');
|
|
201
|
clk_busy_counter <= (OTHERS => '0');
|
|
|
202
|
nSRAM_BUSY_reg <= '0';
|
|
202
|
nSRAM_BUSY_reg <= '0';
|
|
|
203
|
ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
|
|
203
|
ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
|
|
|
204
|
nSRAM_BUSY_reg <= nSRAM_BUSY;
|
|
204
|
nSRAM_BUSY_reg <= nSRAM_BUSY;
|
|
|
205
|
IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
|
|
205
|
IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
|
|
|
206
|
IF clk_busy_counter = "1111" THEN
|
|
206
|
IF clk_busy_counter = "1111" THEN
|
|
|
207
|
clk_lock <= '1';
|
|
207
|
clk_lock <= '1';
|
|
|
208
|
ELSE
|
|
208
|
ELSE
|
|
|
209
|
clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
|
|
209
|
clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
|
|
|
210
|
END IF;
|
|
210
|
END IF;
|
|
|
211
|
END IF;
|
|
211
|
END IF;
|
|
|
212
|
END IF;
|
|
212
|
END IF;
|
|
|
213
|
END PROCESS;
|
|
213
|
END PROCESS;
|
|
|
214
|
|
|
214
|
|
|
|
215
|
-----------------------------------------------------------------------------
|
|
215
|
-----------------------------------------------------------------------------
|
|
|
216
|
-- CLK
|
|
216
|
-- CLK
|
|
|
217
|
-----------------------------------------------------------------------------
|
|
217
|
-----------------------------------------------------------------------------
|
|
|
218
|
rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
|
|
218
|
rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
|
|
|
219
|
rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
|
|
219
|
rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
|
|
|
220
|
|
|
220
|
|
|
|
221
|
--clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
|
|
221
|
--clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
|
|
|
222
|
clk50MHz_int <= clk50MHz;
|
|
222
|
clk50MHz_int <= clk50MHz;
|
|
|
223
|
|
|
223
|
|
|
|
224
|
PROCESS(clk50MHz_int)
|
|
224
|
PROCESS(clk50MHz_int)
|
|
|
225
|
BEGIN
|
|
225
|
BEGIN
|
|
|
226
|
IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
|
|
226
|
IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
|
|
|
227
|
--clk_25_int <= NOT clk_25_int;
|
|
227
|
--clk_25_int <= NOT clk_25_int;
|
|
|
228
|
clk_25 <= NOT clk_25;
|
|
228
|
clk_25 <= NOT clk_25;
|
|
|
229
|
END IF;
|
|
229
|
END IF;
|
|
|
230
|
END PROCESS;
|
|
230
|
END PROCESS;
|
|
|
231
|
--clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
|
|
231
|
--clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
|
|
|
232
|
|
|
232
|
|
|
|
233
|
PROCESS(clk49_152MHz)
|
|
233
|
PROCESS(clk49_152MHz)
|
|
|
234
|
BEGIN
|
|
234
|
BEGIN
|
|
|
235
|
IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
|
|
235
|
IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
|
|
|
236
|
clk_24 <= NOT clk_24;
|
|
236
|
clk_24 <= NOT clk_24;
|
|
|
237
|
END IF;
|
|
237
|
END IF;
|
|
|
238
|
END PROCESS;
|
|
238
|
END PROCESS;
|
|
|
239
|
-- clk_49 <= clk49_152MHz;
|
|
239
|
-- clk_49 <= clk49_152MHz;
|
|
|
240
|
|
|
240
|
|
|
|
241
|
-----------------------------------------------------------------------------
|
|
241
|
-----------------------------------------------------------------------------
|
|
|
242
|
--
|
|
242
|
--
|
|
|
243
|
leon3_soc_1 : leon3_soc
|
|
243
|
leon3_soc_1 : leon3_soc
|
|
|
244
|
GENERIC MAP (
|
|
244
|
GENERIC MAP (
|
|
|
245
|
fabtech => tech_leon,
|
|
245
|
fabtech => tech_leon,
|
|
|
246
|
memtech => tech_leon,
|
|
246
|
memtech => tech_leon,
|
|
|
247
|
padtech => inferred,
|
|
247
|
padtech => inferred,
|
|
|
248
|
clktech => inferred,
|
|
248
|
clktech => inferred,
|
|
|
249
|
disas => 0,
|
|
249
|
disas => 0,
|
|
|
250
|
dbguart => 0,
|
|
250
|
dbguart => 0,
|
|
|
251
|
pclow => 2,
|
|
251
|
pclow => 2,
|
|
|
252
|
clk_freq => 25000,
|
|
252
|
clk_freq => 25000,
|
|
|
253
|
IS_RADHARD => 0,
|
|
253
|
IS_RADHARD => 0,
|
|
|
254
|
NB_CPU => 1,
|
|
254
|
NB_CPU => 1,
|
|
|
255
|
ENABLE_FPU => 1,
|
|
255
|
ENABLE_FPU => 1,
|
|
|
256
|
FPU_NETLIST => 0,
|
|
256
|
FPU_NETLIST => 0,
|
|
|
257
|
ENABLE_DSU => 1,
|
|
257
|
ENABLE_DSU => 1,
|
|
|
258
|
ENABLE_AHB_UART => 1,
|
|
258
|
ENABLE_AHB_UART => 1,
|
|
|
259
|
ENABLE_APB_UART => 1,
|
|
259
|
ENABLE_APB_UART => 1,
|
|
|
260
|
ENABLE_IRQMP => 1,
|
|
260
|
ENABLE_IRQMP => 1,
|
|
|
261
|
ENABLE_GPT => 1,
|
|
261
|
ENABLE_GPT => 1,
|
|
|
262
|
NB_AHB_MASTER => NB_AHB_MASTER,
|
|
262
|
NB_AHB_MASTER => NB_AHB_MASTER,
|
|
|
263
|
NB_AHB_SLAVE => NB_AHB_SLAVE,
|
|
263
|
NB_AHB_SLAVE => NB_AHB_SLAVE,
|
|
|
264
|
NB_APB_SLAVE => NB_APB_SLAVE,
|
|
264
|
NB_APB_SLAVE => NB_APB_SLAVE,
|
|
|
265
|
ADDRESS_SIZE => 19,
|
|
265
|
ADDRESS_SIZE => 19,
|
|
|
266
|
USES_IAP_MEMCTRLR => 1,
|
|
266
|
USES_IAP_MEMCTRLR => 1,
|
|
|
267
|
BYPASS_EDAC_MEMCTRLR => '0',
|
|
267
|
BYPASS_EDAC_MEMCTRLR => '0',
|
|
|
268
|
SRBANKSZ => 8,
|
|
268
|
SRBANKSZ => 8,
|
|
|
269
|
SLOW_TIMING_EMULATION => 0
|
|
269
|
SLOW_TIMING_EMULATION => 0
|
|
|
270
|
)
|
|
270
|
)
|
|
|
271
|
PORT MAP (
|
|
271
|
PORT MAP (
|
|
|
272
|
clk => clk_25,
|
|
272
|
clk => clk_25,
|
|
|
273
|
reset => rstn_25,
|
|
273
|
reset => rstn_25,
|
|
|
274
|
errorn => OPEN,
|
|
274
|
errorn => OPEN,
|
|
|
275
|
|
|
275
|
|
|
|
276
|
ahbrxd => ahbrxd, -- INPUT
|
|
276
|
ahbrxd => ahbrxd, -- INPUT
|
|
|
277
|
ahbtxd => ahbtxd, -- OUTPUT
|
|
277
|
ahbtxd => ahbtxd, -- OUTPUT
|
|
|
278
|
urxd1 => urxd1, -- INPUT
|
|
278
|
urxd1 => urxd1, -- INPUT
|
|
|
279
|
utxd1 => utxd1, -- OUTPUT
|
|
279
|
utxd1 => utxd1, -- OUTPUT
|
|
|
280
|
|
|
280
|
|
|
|
281
|
address => address,
|
|
281
|
address => address,
|
|
|
282
|
data => data,
|
|
282
|
data => data,
|
|
|
283
|
nSRAM_BE0 => OPEN,
|
|
283
|
nSRAM_BE0 => OPEN,
|
|
|
284
|
nSRAM_BE1 => OPEN,
|
|
284
|
nSRAM_BE1 => OPEN,
|
|
|
285
|
nSRAM_BE2 => OPEN,
|
|
285
|
nSRAM_BE2 => OPEN,
|
|
|
286
|
nSRAM_BE3 => OPEN,
|
|
286
|
nSRAM_BE3 => OPEN,
|
|
|
287
|
nSRAM_WE => nSRAM_W,
|
|
287
|
nSRAM_WE => nSRAM_W,
|
|
|
288
|
nSRAM_CE => nSRAM_CE,
|
|
288
|
nSRAM_CE => nSRAM_CE,
|
|
|
289
|
nSRAM_OE => nSRAM_G,
|
|
289
|
nSRAM_OE => nSRAM_G,
|
|
|
290
|
nSRAM_READY => nSRAM_BUSY,
|
|
290
|
nSRAM_READY => nSRAM_BUSY,
|
|
|
291
|
SRAM_MBE => nSRAM_MBE,
|
|
291
|
SRAM_MBE => nSRAM_MBE,
|
|
|
292
|
|
|
292
|
|
|
|
293
|
apbi_ext => apbi_ext,
|
|
293
|
apbi_ext => apbi_ext,
|
|
|
294
|
apbo_ext => apbo_ext,
|
|
294
|
apbo_ext => apbo_ext,
|
|
|
295
|
ahbi_s_ext => ahbi_s_ext,
|
|
295
|
ahbi_s_ext => ahbi_s_ext,
|
|
|
296
|
ahbo_s_ext => ahbo_s_ext,
|
|
296
|
ahbo_s_ext => ahbo_s_ext,
|
|
|
297
|
ahbi_m_ext => ahbi_m_ext,
|
|
297
|
ahbi_m_ext => ahbi_m_ext,
|
|
|
298
|
ahbo_m_ext => ahbo_m_ext);
|
|
298
|
ahbo_m_ext => ahbo_m_ext);
|
|
|
299
|
|
|
299
|
|
|
|
300
|
|
|
300
|
|
|
|
301
|
nSRAM_E1 <= nSRAM_CE(0);
|
|
301
|
nSRAM_E1 <= nSRAM_CE(0);
|
|
|
302
|
nSRAM_E2 <= nSRAM_CE(1);
|
|
302
|
nSRAM_E2 <= nSRAM_CE(1);
|
|
|
303
|
|
|
303
|
|
|
|
304
|
-------------------------------------------------------------------------------
|
|
304
|
-------------------------------------------------------------------------------
|
|
|
305
|
-- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
|
|
305
|
-- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
|
|
|
306
|
-------------------------------------------------------------------------------
|
|
306
|
-------------------------------------------------------------------------------
|
|
|
307
|
apb_lfr_management_1 : apb_lfr_management
|
|
307
|
apb_lfr_management_1 : apb_lfr_management
|
|
|
308
|
GENERIC MAP (
|
|
308
|
GENERIC MAP (
|
|
|
309
|
tech => tech,
|
|
309
|
tech => tech,
|
|
|
310
|
pindex => 6,
|
|
310
|
pindex => 6,
|
|
|
311
|
paddr => 6,
|
|
311
|
paddr => 6,
|
|
|
312
|
pmask => 16#fff#,
|
|
312
|
pmask => 16#fff#,
|
|
|
313
|
--FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
|
|
313
|
--FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
|
|
|
314
|
NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
|
|
314
|
NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
|
|
|
315
|
PORT MAP (
|
|
315
|
PORT MAP (
|
|
|
316
|
clk25MHz => clk_25,
|
|
316
|
clk25MHz => clk_25,
|
|
|
317
|
resetn_25MHz => rstn_25, -- TODO
|
|
317
|
resetn_25MHz => rstn_25, -- TODO
|
|
|
318
|
--clk24_576MHz => clk_24, -- 49.152MHz/2
|
|
318
|
--clk24_576MHz => clk_24, -- 49.152MHz/2
|
|
|
319
|
--resetn_24_576MHz => rstn_24, -- TODO
|
|
319
|
--resetn_24_576MHz => rstn_24, -- TODO
|
|
|
320
|
|
|
320
|
|
|
|
321
|
grspw_tick => swno.tickout,
|
|
321
|
grspw_tick => swno.tickout,
|
|
|
322
|
apbi => apbi_ext,
|
|
322
|
apbi => apbi_ext,
|
|
|
323
|
apbo => apbo_ext(6),
|
|
323
|
apbo => apbo_ext(6),
|
|
|
324
|
|
|
324
|
|
|
|
325
|
HK_sample => sample_s(8),
|
|
325
|
HK_sample => sample_s(8),
|
|
|
326
|
HK_val => sample_val,
|
|
326
|
HK_val => sample_val,
|
|
|
327
|
HK_sel => HK_SEL,
|
|
327
|
HK_sel => HK_SEL,
|
|
|
328
|
|
|
328
|
|
|
|
329
|
DAC_SDO => DAC_SDO,
|
|
329
|
DAC_SDO => DAC_SDO,
|
|
|
330
|
DAC_SCK => DAC_SCK,
|
|
330
|
DAC_SCK => DAC_SCK,
|
|
|
331
|
DAC_SYNC => DAC_SYNC,
|
|
331
|
DAC_SYNC => DAC_SYNC,
|
|
|
332
|
DAC_CAL_EN => DAC_CAL_EN,
|
|
332
|
DAC_CAL_EN => DAC_CAL_EN,
|
|
|
333
|
|
|
333
|
|
|
|
334
|
coarse_time => coarse_time,
|
|
334
|
coarse_time => coarse_time,
|
|
|
335
|
fine_time => fine_time,
|
|
335
|
fine_time => fine_time,
|
|
|
336
|
LFR_soft_rstn => LFR_soft_rstn
|
|
336
|
LFR_soft_rstn => LFR_soft_rstn
|
|
|
337
|
);
|
|
337
|
);
|
|
|
338
|
|
|
338
|
|
|
|
339
|
-----------------------------------------------------------------------
|
|
339
|
-----------------------------------------------------------------------
|
|
|
340
|
--- SpaceWire --------------------------------------------------------
|
|
340
|
--- SpaceWire --------------------------------------------------------
|
|
|
341
|
-----------------------------------------------------------------------
|
|
341
|
-----------------------------------------------------------------------
|
|
|
342
|
|
|
342
|
|
|
|
343
|
------------------------------------------------------------------------------
|
|
343
|
------------------------------------------------------------------------------
|
|
|
344
|
-- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
|
|
344
|
-- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
|
|
|
345
|
------------------------------------------------------------------------------
|
|
345
|
------------------------------------------------------------------------------
|
|
|
346
|
spw1_en <= '1';
|
|
346
|
spw1_en <= '1';
|
|
|
347
|
spw2_en <= '1';
|
|
347
|
spw2_en <= '1';
|
|
|
348
|
------------------------------------------------------------------------------
|
|
348
|
------------------------------------------------------------------------------
|
|
|
349
|
-- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
|
|
349
|
-- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
|
|
|
350
|
------------------------------------------------------------------------------
|
|
350
|
------------------------------------------------------------------------------
|
|
|
351
|
|
|
351
|
|
|
|
352
|
--spw_clk <= clk50MHz;
|
|
352
|
--spw_clk <= clk50MHz;
|
|
|
353
|
--spw_rxtxclk <= spw_clk;
|
|
353
|
--spw_rxtxclk <= spw_clk;
|
|
|
354
|
--spw_rxclkn <= NOT spw_rxtxclk;
|
|
354
|
--spw_rxclkn <= NOT spw_rxtxclk;
|
|
|
355
|
|
|
355
|
|
|
|
356
|
-- PADS for SPW1
|
|
356
|
-- PADS for SPW1
|
|
|
357
|
spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
|
|
357
|
spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
|
|
|
358
|
PORT MAP (spw1_din, dtmp(0));
|
|
358
|
PORT MAP (spw1_din, dtmp(0));
|
|
|
359
|
spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
|
|
359
|
spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
|
|
|
360
|
PORT MAP (spw1_sin, stmp(0));
|
|
360
|
PORT MAP (spw1_sin, stmp(0));
|
|
|
361
|
spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
|
|
361
|
spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
|
|
|
362
|
PORT MAP (spw1_dout, swno.d(0));
|
|
362
|
PORT MAP (spw1_dout, swno.d(0));
|
|
|
363
|
spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
|
|
363
|
spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
|
|
|
364
|
PORT MAP (spw1_sout, swno.s(0));
|
|
364
|
PORT MAP (spw1_sout, swno.s(0));
|
|
|
365
|
-- PADS FOR SPW2
|
|
365
|
-- PADS FOR SPW2
|
|
|
366
|
spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
|
|
366
|
spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
|
|
|
367
|
PORT MAP (spw2_din, dtmp(1));
|
|
367
|
PORT MAP (spw2_din, dtmp(1));
|
|
|
368
|
spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
|
|
368
|
spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
|
|
|
369
|
PORT MAP (spw2_sin, stmp(1));
|
|
369
|
PORT MAP (spw2_sin, stmp(1));
|
|
|
370
|
spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
|
|
370
|
spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
|
|
|
371
|
PORT MAP (spw2_dout, swno.d(1));
|
|
371
|
PORT MAP (spw2_dout, swno.d(1));
|
|
|
372
|
spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
|
|
372
|
spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
|
|
|
373
|
PORT MAP (spw2_sout, swno.s(1));
|
|
373
|
PORT MAP (spw2_sout, swno.s(1));
|
|
|
374
|
|
|
374
|
|
|
|
375
|
-- GRSPW PHY
|
|
375
|
-- GRSPW PHY
|
|
|
376
|
--spw1_input: if CFG_SPW_GRSPW = 1 generate
|
|
376
|
--spw1_input: if CFG_SPW_GRSPW = 1 generate
|
|
|
377
|
spw_inputloop : FOR j IN 0 TO 1 GENERATE
|
|
377
|
spw_inputloop : FOR j IN 0 TO 1 GENERATE
|
|
|
378
|
spw_phy0 : grspw_phy
|
|
378
|
spw_phy0 : grspw_phy
|
|
|
379
|
GENERIC MAP(
|
|
379
|
GENERIC MAP(
|
|
|
380
|
tech => tech_leon,
|
|
380
|
tech => tech_leon,
|
|
|
381
|
rxclkbuftype => 1,
|
|
381
|
rxclkbuftype => 1,
|
|
|
382
|
scantest => 0)
|
|
382
|
scantest => 0)
|
|
|
383
|
PORT MAP(
|
|
383
|
PORT MAP(
|
|
|
384
|
rxrst => swno.rxrst,
|
|
384
|
rxrst => swno.rxrst,
|
|
|
385
|
di => dtmp(j),
|
|
385
|
di => dtmp(j),
|
|
|
386
|
si => stmp(j),
|
|
386
|
si => stmp(j),
|
|
|
387
|
rxclko => spw_rxclk(j),
|
|
387
|
rxclko => spw_rxclk(j),
|
|
|
388
|
do => swni.d(j),
|
|
388
|
do => swni.d(j),
|
|
|
389
|
ndo => swni.nd(j*5+4 DOWNTO j*5),
|
|
389
|
ndo => swni.nd(j*5+4 DOWNTO j*5),
|
|
|
390
|
dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
|
|
390
|
dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
|
|
|
391
|
END GENERATE spw_inputloop;
|
|
391
|
END GENERATE spw_inputloop;
|
|
|
392
|
|
|
392
|
|
|
|
393
|
-- SPW core
|
|
393
|
-- SPW core
|
|
|
394
|
sw0 : grspwm GENERIC MAP(
|
|
394
|
sw0 : grspwm GENERIC MAP(
|
|
|
395
|
tech => tech_leon,
|
|
395
|
tech => tech_leon,
|
|
|
396
|
hindex => 1,
|
|
396
|
hindex => 1,
|
|
|
397
|
pindex => 5,
|
|
397
|
pindex => 5,
|
|
|
398
|
paddr => 5,
|
|
398
|
paddr => 5,
|
|
|
399
|
pirq => 11,
|
|
399
|
pirq => 11,
|
|
|
400
|
sysfreq => 25000, -- CPU_FREQ
|
|
400
|
sysfreq => 25000, -- CPU_FREQ
|
|
|
401
|
rmap => 1,
|
|
401
|
rmap => 1,
|
|
|
402
|
rmapcrc => 1,
|
|
402
|
rmapcrc => 1,
|
|
|
403
|
fifosize1 => 16,
|
|
403
|
fifosize1 => 16,
|
|
|
404
|
fifosize2 => 16,
|
|
404
|
fifosize2 => 16,
|
|
|
405
|
rxclkbuftype => 1,
|
|
405
|
rxclkbuftype => 1,
|
|
|
406
|
rxunaligned => 0,
|
|
406
|
rxunaligned => 0,
|
|
|
407
|
rmapbufs => 4,
|
|
407
|
rmapbufs => 4,
|
|
|
408
|
ft => 0,
|
|
408
|
ft => 0,
|
|
|
409
|
netlist => 0,
|
|
409
|
netlist => 0,
|
|
|
410
|
ports => 2,
|
|
410
|
ports => 2,
|
|
|
411
|
--dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
|
|
411
|
--dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
|
|
|
412
|
memtech => tech_leon,
|
|
412
|
memtech => tech_leon,
|
|
|
413
|
destkey => 2,
|
|
413
|
destkey => 2,
|
|
|
414
|
spwcore => 1
|
|
414
|
spwcore => 1
|
|
|
415
|
--input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
|
|
415
|
--input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
|
|
|
416
|
--output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
|
|
416
|
--output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
|
|
|
417
|
--rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
|
|
417
|
--rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
|
|
|
418
|
)
|
|
418
|
)
|
|
|
419
|
PORT MAP(rstn_25, clk_25, spw_rxclk(0),
|
|
419
|
PORT MAP(rstn_25, clk_25, spw_rxclk(0),
|
|
|
420
|
spw_rxclk(1),
|
|
420
|
spw_rxclk(1),
|
|
|
421
|
clk50MHz_int,
|
|
421
|
clk50MHz_int,
|
|
|
422
|
clk50MHz_int,
|
|
422
|
clk50MHz_int,
|
|
|
423
|
-- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
|
|
423
|
-- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
|
|
|
424
|
ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
|
|
424
|
ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
|
|
|
425
|
swni, swno);
|
|
425
|
swni, swno);
|
|
|
426
|
|
|
426
|
|
|
|
427
|
swni.tickin <= '0';
|
|
427
|
swni.tickin <= '0';
|
|
|
428
|
swni.rmapen <= '1';
|
|
428
|
swni.rmapen <= '1';
|
|
|
429
|
swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
|
|
429
|
swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
|
|
|
430
|
swni.tickinraw <= '0';
|
|
430
|
swni.tickinraw <= '0';
|
|
|
431
|
swni.timein <= (OTHERS => '0');
|
|
431
|
swni.timein <= (OTHERS => '0');
|
|
|
432
|
swni.dcrstval <= (OTHERS => '0');
|
|
432
|
swni.dcrstval <= (OTHERS => '0');
|
|
|
433
|
swni.timerrstval <= (OTHERS => '0');
|
|
433
|
swni.timerrstval <= (OTHERS => '0');
|
|
|
434
|
|
|
434
|
|
|
|
435
|
-------------------------------------------------------------------------------
|
|
435
|
-------------------------------------------------------------------------------
|
|
|
436
|
-- LFR ------------------------------------------------------------------------
|
|
436
|
-- LFR ------------------------------------------------------------------------
|
|
|
437
|
-------------------------------------------------------------------------------
|
|
437
|
-------------------------------------------------------------------------------
|
|
|
438
|
LFR_rstn <= LFR_soft_rstn AND rstn_25;
|
|
438
|
LFR_rstn <= LFR_soft_rstn AND rstn_25;
|
|
|
439
|
|
|
439
|
|
|
|
440
|
lpp_lfr_1 : lpp_lfr
|
|
440
|
lpp_lfr_1 : lpp_lfr
|
|
|
441
|
GENERIC MAP (
|
|
441
|
GENERIC MAP (
|
|
|
442
|
Mem_use => Mem_use,
|
|
442
|
Mem_use => Mem_use,
|
|
|
443
|
tech => tech,
|
|
443
|
tech => tech,
|
|
|
444
|
nb_data_by_buffer_size => 32,
|
|
444
|
nb_data_by_buffer_size => 32,
|
|
|
445
|
--nb_word_by_buffer_size => 30,
|
|
445
|
--nb_word_by_buffer_size => 30,
|
|
|
446
|
nb_snapshot_param_size => 32,
|
|
446
|
nb_snapshot_param_size => 32,
|
|
|
447
|
delta_vector_size => 32,
|
|
447
|
delta_vector_size => 32,
|
|
|
448
|
delta_vector_size_f0_2 => 7, -- log2(96)
|
|
448
|
delta_vector_size_f0_2 => 7, -- log2(96)
|
|
|
449
|
pindex => 15,
|
|
449
|
pindex => 15,
|
|
|
450
|
paddr => 15,
|
|
450
|
paddr => 15,
|
|
|
451
|
pmask => 16#fff#,
|
|
451
|
pmask => 16#fff#,
|
|
|
452
|
pirq_ms => 6,
|
|
452
|
pirq_ms => 6,
|
|
|
453
|
pirq_wfp => 14,
|
|
453
|
pirq_wfp => 14,
|
|
|
454
|
hindex => 2,
|
|
454
|
hindex => 2,
|
|
|
455
|
top_lfr_version => X"020153", -- aa.bb.cc version
|
|
455
|
top_lfr_version => LPP_LFR_BOARD_LFR_EQM & "015B",
|
|
|
456
|
-- AA : BOARD NUMBER
|
|
456
|
DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA,
|
|
|
457
|
-- 0 => MINI_LFR
|
|
457
|
DATA_SHAPING_SATURATION => 1)
|
|
|
458
|
-- 1 => EM
|
|
|
|
|
|
459
|
-- 2 => EQM (with A3PE3000)
|
|
|
|
|
|
460
|
DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA)
|
|
|
|
|
|
461
|
PORT MAP (
|
|
458
|
PORT MAP (
|
|
|
462
|
clk => clk_25,
|
|
459
|
clk => clk_25,
|
|
|
463
|
rstn => LFR_rstn,
|
|
460
|
rstn => LFR_rstn,
|
|
|
464
|
sample_B => sample_s(2 DOWNTO 0),
|
|
461
|
sample_B => sample_s(2 DOWNTO 0),
|
|
|
465
|
sample_E => sample_s(7 DOWNTO 3),
|
|
462
|
sample_E => sample_s(7 DOWNTO 3),
|
|
|
466
|
sample_val => sample_val,
|
|
463
|
sample_val => sample_val,
|
|
|
467
|
apbi => apbi_ext,
|
|
464
|
apbi => apbi_ext,
|
|
|
468
|
apbo => apbo_ext(15),
|
|
465
|
apbo => apbo_ext(15),
|
|
|
469
|
ahbi => ahbi_m_ext,
|
|
466
|
ahbi => ahbi_m_ext,
|
|
|
470
|
ahbo => ahbo_m_ext(2),
|
|
467
|
ahbo => ahbo_m_ext(2),
|
|
|
471
|
coarse_time => coarse_time,
|
|
468
|
coarse_time => coarse_time,
|
|
|
472
|
fine_time => fine_time,
|
|
469
|
fine_time => fine_time,
|
|
|
473
|
data_shaping_BW => bias_fail_sw,
|
|
470
|
data_shaping_BW => bias_fail_sw,
|
|
|
474
|
debug_vector => debug_vector,
|
|
471
|
debug_vector => debug_vector,
|
|
|
475
|
debug_vector_ms => OPEN); --,
|
|
472
|
debug_vector_ms => OPEN); --,
|
|
|
476
|
--observation_vector_0 => OPEN,
|
|
473
|
--observation_vector_0 => OPEN,
|
|
|
477
|
--observation_vector_1 => OPEN,
|
|
474
|
--observation_vector_1 => OPEN,
|
|
|
478
|
--observation_reg => observation_reg);
|
|
475
|
--observation_reg => observation_reg);
|
|
|
479
|
|
|
476
|
|
|
|
480
|
|
|
477
|
|
|
|
481
|
all_sample : FOR I IN 7 DOWNTO 0 GENERATE
|
|
478
|
all_sample : FOR I IN 7 DOWNTO 0 GENERATE
|
|
|
482
|
sample_s(I) <= sample(I) & '0' & '0';
|
|
479
|
sample_s(I) <= sample(I) & '0' & '0';
|
|
|
483
|
END GENERATE all_sample;
|
|
480
|
END GENERATE all_sample;
|
|
|
484
|
sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
|
|
481
|
sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
|
|
|
485
|
|
|
482
|
|
|
|
486
|
-----------------------------------------------------------------------------
|
|
483
|
-----------------------------------------------------------------------------
|
|
|
487
|
--
|
|
484
|
--
|
|
|
488
|
-----------------------------------------------------------------------------
|
|
485
|
-----------------------------------------------------------------------------
|
|
|
489
|
USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
|
|
486
|
USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
|
|
|
490
|
top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
|
|
487
|
top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
|
|
|
491
|
GENERIC MAP (
|
|
488
|
GENERIC MAP (
|
|
|
492
|
ChanelCount => 9,
|
|
489
|
ChanelCount => 9,
|
|
|
493
|
ncycle_cnv_high => 12,
|
|
490
|
ncycle_cnv_high => 12,
|
|
|
494
|
ncycle_cnv => 25,
|
|
491
|
ncycle_cnv => 25,
|
|
|
495
|
FILTER_ENABLED => 16#FF#)
|
|
492
|
FILTER_ENABLED => 16#FF#)
|
|
|
496
|
PORT MAP (
|
|
493
|
PORT MAP (
|
|
|
497
|
cnv_clk => clk_24,
|
|
494
|
cnv_clk => clk_24,
|
|
|
498
|
cnv_rstn => rstn_24,
|
|
495
|
cnv_rstn => rstn_24,
|
|
|
499
|
cnv => ADC_smpclk_s,
|
|
496
|
cnv => ADC_smpclk_s,
|
|
|
500
|
clk => clk_25,
|
|
497
|
clk => clk_25,
|
|
|
501
|
rstn => rstn_25,
|
|
498
|
rstn => rstn_25,
|
|
|
502
|
ADC_data => ADC_data,
|
|
499
|
ADC_data => ADC_data,
|
|
|
503
|
ADC_nOE => ADC_OEB_bar_CH_s,
|
|
500
|
ADC_nOE => ADC_OEB_bar_CH_s,
|
|
|
504
|
sample => sample,
|
|
501
|
sample => sample,
|
|
|
505
|
sample_val => sample_val);
|
|
502
|
sample_val => sample_val);
|
|
|
506
|
|
|
503
|
|
|
|
507
|
END GENERATE USE_ADCDRIVER_true;
|
|
504
|
END GENERATE USE_ADCDRIVER_true;
|
|
|
508
|
|
|
505
|
|
|
|
509
|
USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
|
|
506
|
USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
|
|
|
510
|
top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
|
|
507
|
top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
|
|
|
511
|
GENERIC MAP (
|
|
508
|
GENERIC MAP (
|
|
|
512
|
ChanelCount => 9,
|
|
509
|
ChanelCount => 9,
|
|
|
513
|
ncycle_cnv_high => 25,
|
|
510
|
ncycle_cnv_high => 25,
|
|
|
514
|
ncycle_cnv => 50,
|
|
511
|
ncycle_cnv => 50,
|
|
|
515
|
FILTER_ENABLED => 16#FF#)
|
|
512
|
FILTER_ENABLED => 16#FF#)
|
|
|
516
|
PORT MAP (
|
|
513
|
PORT MAP (
|
|
|
517
|
cnv_clk => clk_24,
|
|
514
|
cnv_clk => clk_24,
|
|
|
518
|
cnv_rstn => rstn_24,
|
|
515
|
cnv_rstn => rstn_24,
|
|
|
519
|
cnv => ADC_smpclk_s,
|
|
516
|
cnv => ADC_smpclk_s,
|
|
|
520
|
clk => clk_25,
|
|
517
|
clk => clk_25,
|
|
|
521
|
rstn => rstn_25,
|
|
518
|
rstn => rstn_25,
|
|
|
522
|
ADC_data => ADC_data,
|
|
519
|
ADC_data => ADC_data,
|
|
|
523
|
ADC_nOE => OPEN,
|
|
520
|
ADC_nOE => OPEN,
|
|
|
524
|
sample => OPEN,
|
|
521
|
sample => OPEN,
|
|
|
525
|
sample_val => sample_val);
|
|
522
|
sample_val => sample_val);
|
|
|
526
|
|
|
523
|
|
|
|
527
|
ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
|
|
524
|
ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
|
|
|
528
|
|
|
525
|
|
|
|
529
|
all_sample: FOR I IN 8 DOWNTO 0 GENERATE
|
|
526
|
all_sample: FOR I IN 8 DOWNTO 0 GENERATE
|
|
|
530
|
ramp_generator_1: ramp_generator
|
|
527
|
ramp_generator_1: ramp_generator
|
|
|
531
|
GENERIC MAP (
|
|
528
|
GENERIC MAP (
|
|
|
532
|
DATA_SIZE => 14,
|
|
529
|
DATA_SIZE => 14,
|
|
|
533
|
VALUE_UNSIGNED_INIT => 2**I,
|
|
530
|
VALUE_UNSIGNED_INIT => 2**I,
|
|
|
534
|
VALUE_UNSIGNED_INCR => 0,
|
|
531
|
VALUE_UNSIGNED_INCR => 0,
|
|
|
535
|
VALUE_UNSIGNED_MASK => 16#3FFF#)
|
|
532
|
VALUE_UNSIGNED_MASK => 16#3FFF#)
|
|
|
536
|
PORT MAP (
|
|
533
|
PORT MAP (
|
|
|
537
|
clk => clk_25,
|
|
534
|
clk => clk_25,
|
|
|
538
|
rstn => rstn_25,
|
|
535
|
rstn => rstn_25,
|
|
|
539
|
new_data => sample_val,
|
|
536
|
new_data => sample_val,
|
|
|
540
|
output_data => sample(I) );
|
|
537
|
output_data => sample(I) );
|
|
|
541
|
END GENERATE all_sample;
|
|
538
|
END GENERATE all_sample;
|
|
|
542
|
|
|
539
|
|
|
|
543
|
|
|
540
|
|
|
|
544
|
END GENERATE USE_ADCDRIVER_false;
|
|
541
|
END GENERATE USE_ADCDRIVER_false;
|
|
|
545
|
|
|
542
|
|
|
|
546
|
|
|
543
|
|
|
|
547
|
|
|
544
|
|
|
|
548
|
|
|
545
|
|
|
|
549
|
ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
|
|
546
|
ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
|
|
|
550
|
|
|
547
|
|
|
|
551
|
ADC_smpclk <= ADC_smpclk_s;
|
|
548
|
ADC_smpclk <= ADC_smpclk_s;
|
|
|
552
|
HK_smpclk <= ADC_smpclk_s;
|
|
549
|
HK_smpclk <= ADC_smpclk_s;
|
|
|
553
|
|
|
550
|
|
|
|
554
|
|
|
551
|
|
|
|
555
|
-----------------------------------------------------------------------------
|
|
552
|
-----------------------------------------------------------------------------
|
|
|
556
|
-- HK
|
|
553
|
-- HK
|
|
|
557
|
-----------------------------------------------------------------------------
|
|
554
|
-----------------------------------------------------------------------------
|
|
|
558
|
ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
|
|
555
|
ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
|
|
|
559
|
|
|
556
|
|
|
|
560
|
-----------------------------------------------------------------------------
|
|
557
|
-----------------------------------------------------------------------------
|
|
|
561
|
--
|
|
558
|
--
|
|
|
562
|
-----------------------------------------------------------------------------
|
|
559
|
-----------------------------------------------------------------------------
|
|
|
563
|
inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
|
|
560
|
inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
|
|
|
564
|
lpp_bootloader_1: lpp_bootloader
|
|
561
|
lpp_bootloader_1: lpp_bootloader
|
|
|
565
|
GENERIC MAP (
|
|
562
|
GENERIC MAP (
|
|
|
566
|
pindex => 13,
|
|
563
|
pindex => 13,
|
|
|
567
|
paddr => 13,
|
|
564
|
paddr => 13,
|
|
|
568
|
pmask => 16#fff#,
|
|
565
|
pmask => 16#fff#,
|
|
|
569
|
hindex => 3,
|
|
566
|
hindex => 3,
|
|
|
570
|
haddr => 0,
|
|
567
|
haddr => 0,
|
|
|
571
|
hmask => 16#fff#)
|
|
568
|
hmask => 16#fff#)
|
|
|
572
|
PORT MAP (
|
|
569
|
PORT MAP (
|
|
|
573
|
HCLK => clk_25,
|
|
570
|
HCLK => clk_25,
|
|
|
574
|
HRESETn => rstn_25,
|
|
571
|
HRESETn => rstn_25,
|
|
|
575
|
apbi => apbi_ext,
|
|
572
|
apbi => apbi_ext,
|
|
|
576
|
apbo => apbo_ext(13),
|
|
573
|
apbo => apbo_ext(13),
|
|
|
577
|
ahbsi => ahbi_s_ext,
|
|
574
|
ahbsi => ahbi_s_ext,
|
|
|
578
|
ahbso => ahbo_s_ext(3));
|
|
575
|
ahbso => ahbo_s_ext(3));
|
|
|
579
|
END GENERATE inst_bootloader;
|
|
576
|
END GENERATE inst_bootloader;
|
|
|
580
|
|
|
577
|
|
|
|
581
|
-----------------------------------------------------------------------------
|
|
578
|
-----------------------------------------------------------------------------
|
|
|
582
|
--
|
|
579
|
--
|
|
|
583
|
-----------------------------------------------------------------------------
|
|
580
|
-----------------------------------------------------------------------------
|
|
|
584
|
USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
|
|
581
|
USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
|
|
|
585
|
PROCESS (clk_25, rstn_25)
|
|
582
|
PROCESS (clk_25, rstn_25)
|
|
|
586
|
BEGIN -- PROCESS
|
|
583
|
BEGIN -- PROCESS
|
|
|
587
|
IF rstn_25 = '0' THEN -- asynchronous reset (active low)
|
|
584
|
IF rstn_25 = '0' THEN -- asynchronous reset (active low)
|
|
|
588
|
TAG <= (OTHERS => '0');
|
|
585
|
TAG <= (OTHERS => '0');
|
|
|
589
|
ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
|
|
586
|
ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
|
|
|
590
|
TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
|
|
587
|
TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
|
|
|
591
|
END IF;
|
|
588
|
END IF;
|
|
|
592
|
END PROCESS;
|
|
589
|
END PROCESS;
|
|
|
593
|
|
|
590
|
|
|
|
594
|
|
|
591
|
|
|
|
595
|
END GENERATE USE_DEBUG_VECTOR_IF;
|
|
592
|
END GENERATE USE_DEBUG_VECTOR_IF;
|
|
|
596
|
|
|
593
|
|
|
|
597
|
USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
|
|
594
|
USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
|
|
|
598
|
ahbrxd <= TAG(1);
|
|
595
|
ahbrxd <= TAG(1);
|
|
|
599
|
TAG(3) <= ahbtxd;
|
|
596
|
TAG(3) <= ahbtxd;
|
|
|
600
|
urxd1 <= TAG(2);
|
|
597
|
urxd1 <= TAG(2);
|
|
|
601
|
TAG(4) <= utxd1;
|
|
598
|
TAG(4) <= utxd1;
|
|
|
602
|
TAG(8) <= nSRAM_BUSY;
|
|
599
|
TAG(8) <= nSRAM_BUSY;
|
|
|
603
|
END GENERATE USE_DEBUG_VECTOR_IF2;
|
|
600
|
END GENERATE USE_DEBUG_VECTOR_IF2;
|
|
|
604
|
|
|
601
|
|
|
|
605
|
END beh;
|
|
602
|
END beh;
|
