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EQM 2.1.67
pellion -
r561:fafb37280653 (MINI-LFR) 0-1-68 (LFR-EQM) 2-1-68 (LFR-EM) 1-1-68 JC
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1 # Synplicity, Inc. constraint file
1 # Synplicity, Inc. constraint file
2 # /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc
2 # /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc
3 # Written on Wed Aug 1 19:29:24 2007
3 # Written on Wed Aug 1 19:29:24 2007
4 # by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor
4 # by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor
5
5
6 #
6 #
7 # Collections
7 # Collections
8 #
8 #
9
9
10 #
10 #
11 # Clocks
11 # Clocks
12 #
12 #
13
13
14
14 define_clock -name {clk100MHz} -freq 100 -clockgroup default_clkgroup_50 -route 5
15 define_clock {clk100MHz} -name {clk100MHz} -freq 100 -clockgroup default_clkgroup -route 5
15 define_clock -name {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup_49 -route 5
16 define_clock {clk49_152MHz} -name {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup -route 5
17
16
18 #
17 #
19 # Clock to Clock
18 # Clock to Clock
20 #
19 #
21
20
22 #
21 #
23 # Inputs/Outputs
22 # Inputs/Outputs
24 #
23 #
25 define_output_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r}
26 define_input_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r}
27
24
28
25
29 #
26 #
30 # Registers
27 # Registers
31 #
28 #
32
29
33 #
30 #
34 # Multicycle Path
31 # Multicycle Path
35 #
32 #
36
33
37 #
34 #
38 # False Path
35 # False Path
39 #
36 #
40
37
38 set_false_path -from reset
39
41 #
40 #
42 # Path Delay
41 # Path Delay
43 #
42 #
44
43
45 #
44 #
46 # Attributes
45 # Attributes
47 #
46 #
47
48 define_global_attribute syn_useioff {1}
48 define_global_attribute syn_useioff {1}
49 define_global_attribute -disable syn_netlist_hierarchy {0}
49 define_global_attribute -disable syn_netlist_hierarchy {0}
50 define_attribute {etx_clk} syn_noclockbuf {1}
51
50
52 #
51 #
53 # I/O standards
52 # I/O standards
54 #
53 #
55
54
56 #
55 #
57 # Compile Points
56 # Compile Points
58 #
57 #
59
58
60 #
59 #
61 # Other Constraints
60 # Other Constraints
62 #
61 #
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@@ -1,445 +1,449
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY LFR_EQM IS
48 ENTITY LFR_EQM IS
49
49
50 PORT (
50 PORT (
51 clk50MHz : IN STD_ULOGIC;
51 clk50MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
54
54
55 -- TAG --------------------------------------------------------------------
55 -- TAG --------------------------------------------------------------------
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 -- UART APB ---------------------------------------------------------------
58 -- UART APB ---------------------------------------------------------------
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 -- RAM --------------------------------------------------------------------
61 -- RAM --------------------------------------------------------------------
62 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
62 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64
64
65 nSRAM_MBE : INOUT STD_LOGIC; -- new
65 nSRAM_MBE : INOUT STD_LOGIC; -- new
66 nSRAM_E1 : OUT STD_LOGIC; -- new
66 nSRAM_E1 : OUT STD_LOGIC; -- new
67 nSRAM_E2 : OUT STD_LOGIC; -- new
67 nSRAM_E2 : OUT STD_LOGIC; -- new
68 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
68 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
69 nSRAM_W : OUT STD_LOGIC; -- new
69 nSRAM_W : OUT STD_LOGIC; -- new
70 nSRAM_G : OUT STD_LOGIC; -- new
70 nSRAM_G : OUT STD_LOGIC; -- new
71 nSRAM_BUSY : IN STD_LOGIC; -- new
71 nSRAM_BUSY : IN STD_LOGIC; -- new
72 -- SPW --------------------------------------------------------------------
72 -- SPW --------------------------------------------------------------------
73 spw1_en : OUT STD_LOGIC; -- new
73 spw1_en : OUT STD_LOGIC; -- new
74 spw1_din : IN STD_LOGIC;
74 spw1_din : IN STD_LOGIC;
75 spw1_sin : IN STD_LOGIC;
75 spw1_sin : IN STD_LOGIC;
76 spw1_dout : OUT STD_LOGIC;
76 spw1_dout : OUT STD_LOGIC;
77 spw1_sout : OUT STD_LOGIC;
77 spw1_sout : OUT STD_LOGIC;
78 spw2_en : OUT STD_LOGIC; -- new
78 spw2_en : OUT STD_LOGIC; -- new
79 spw2_din : IN STD_LOGIC;
79 spw2_din : IN STD_LOGIC;
80 spw2_sin : IN STD_LOGIC;
80 spw2_sin : IN STD_LOGIC;
81 spw2_dout : OUT STD_LOGIC;
81 spw2_dout : OUT STD_LOGIC;
82 spw2_sout : OUT STD_LOGIC;
82 spw2_sout : OUT STD_LOGIC;
83 -- ADC --------------------------------------------------------------------
83 -- ADC --------------------------------------------------------------------
84 bias_fail_sw : OUT STD_LOGIC;
84 bias_fail_sw : OUT STD_LOGIC;
85 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
85 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
86 ADC_smpclk : OUT STD_LOGIC;
86 ADC_smpclk : OUT STD_LOGIC;
87 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
87 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
88 -- DAC --------------------------------------------------------------------
88 -- DAC --------------------------------------------------------------------
89 DAC_SDO : OUT STD_LOGIC;
89 DAC_SDO : OUT STD_LOGIC;
90 DAC_SCK : OUT STD_LOGIC;
90 DAC_SCK : OUT STD_LOGIC;
91 DAC_SYNC : OUT STD_LOGIC;
91 DAC_SYNC : OUT STD_LOGIC;
92 DAC_CAL_EN : OUT STD_LOGIC;
92 DAC_CAL_EN : OUT STD_LOGIC;
93 -- HK ---------------------------------------------------------------------
93 -- HK ---------------------------------------------------------------------
94 HK_smpclk : OUT STD_LOGIC;
94 HK_smpclk : OUT STD_LOGIC;
95 ADC_OEB_bar_HK : OUT STD_LOGIC;
95 ADC_OEB_bar_HK : OUT STD_LOGIC;
96 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
96 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
97 ---------------------------------------------------------------------------
97 ---------------------------------------------------------------------------
98 TAG8 : OUT STD_LOGIC
98 TAG8 : OUT STD_LOGIC
99 );
99 );
100
100
101 END LFR_EQM;
101 END LFR_EQM;
102
102
103
103
104 ARCHITECTURE beh OF LFR_EQM IS
104 ARCHITECTURE beh OF LFR_EQM IS
105
105
106 SIGNAL clk_25 : STD_LOGIC := '0';
106 SIGNAL clk_25 : STD_LOGIC := '0';
107 SIGNAL clk_24 : STD_LOGIC := '0';
107 SIGNAL clk_24 : STD_LOGIC := '0';
108 -----------------------------------------------------------------------------
108 -----------------------------------------------------------------------------
109 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
110 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
111
111
112 -- CONSTANTS
112 -- CONSTANTS
113 CONSTANT CFG_PADTECH : INTEGER := inferred;
113 CONSTANT CFG_PADTECH : INTEGER := inferred;
114 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
114 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
115 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
115 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
116 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
116 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
117
117
118 SIGNAL apbi_ext : apb_slv_in_type;
118 SIGNAL apbi_ext : apb_slv_in_type;
119 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
119 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
120 SIGNAL ahbi_s_ext : ahb_slv_in_type;
120 SIGNAL ahbi_s_ext : ahb_slv_in_type;
121 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
121 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
122 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
122 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
123 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
123 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
124
124
125 -- Spacewire signals
125 -- Spacewire signals
126 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
126 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
127 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
127 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
128 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
128 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 SIGNAL spw_rxtxclk : STD_ULOGIC;
129 SIGNAL spw_rxtxclk : STD_ULOGIC;
130 SIGNAL spw_rxclkn : STD_ULOGIC;
130 SIGNAL spw_rxclkn : STD_ULOGIC;
131 SIGNAL spw_clk : STD_LOGIC;
131 SIGNAL spw_clk : STD_LOGIC;
132 SIGNAL swni : grspw_in_type;
132 SIGNAL swni : grspw_in_type;
133 SIGNAL swno : grspw_out_type;
133 SIGNAL swno : grspw_out_type;
134
134
135 --GPIO
135 --GPIO
136 SIGNAL gpioi : gpio_in_type;
136 SIGNAL gpioi : gpio_in_type;
137 SIGNAL gpioo : gpio_out_type;
137 SIGNAL gpioo : gpio_out_type;
138
138
139 -- AD Converter ADS7886
139 -- AD Converter ADS7886
140 SIGNAL sample : Samples14v(8 DOWNTO 0);
140 SIGNAL sample : Samples14v(8 DOWNTO 0);
141 SIGNAL sample_s : Samples(8 DOWNTO 0);
141 SIGNAL sample_s : Samples(8 DOWNTO 0);
142 SIGNAL sample_val : STD_LOGIC;
142 SIGNAL sample_val : STD_LOGIC;
143 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
143 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
144
144
145 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
146 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
147
147
148 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
149 SIGNAL rstn : STD_LOGIC;
149 SIGNAL rstn_25 : STD_LOGIC;
150 SIGNAL rstn_24 : STD_LOGIC;
150
151
151 SIGNAL LFR_soft_rstn : STD_LOGIC;
152 SIGNAL LFR_soft_rstn : STD_LOGIC;
152 SIGNAL LFR_rstn : STD_LOGIC;
153 SIGNAL LFR_rstn : STD_LOGIC;
153
154
154 SIGNAL ADC_smpclk_s : STD_LOGIC;
155 SIGNAL ADC_smpclk_s : STD_LOGIC;
155
156
156 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
157 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
157
158
158 BEGIN -- beh
159 BEGIN -- beh
159
160
160 -----------------------------------------------------------------------------
161 -----------------------------------------------------------------------------
161 -- CLK
162 -- CLK
162 -----------------------------------------------------------------------------
163 -----------------------------------------------------------------------------
163 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
164 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
165 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
164
166
165 PROCESS(clk50MHz)
167 PROCESS(clk50MHz)
166 BEGIN
168 BEGIN
167 IF clk50MHz'EVENT AND clk50MHz = '1' THEN
169 IF clk50MHz'EVENT AND clk50MHz = '1' THEN
168 clk_25 <= NOT clk_25;
170 clk_25 <= NOT clk_25;
169 END IF;
171 END IF;
170 END PROCESS;
172 END PROCESS;
171
173
172 PROCESS(clk49_152MHz)
174 PROCESS(clk49_152MHz)
173 BEGIN
175 BEGIN
174 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
176 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
175 clk_24 <= NOT clk_24;
177 clk_24 <= NOT clk_24;
176 END IF;
178 END IF;
177 END PROCESS;
179 END PROCESS;
178
180
179 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
180 --
182 --
181 leon3_soc_1 : leon3_soc
183 leon3_soc_1 : leon3_soc
182 GENERIC MAP (
184 GENERIC MAP (
183 fabtech => apa3e,
185 fabtech => apa3e,
184 memtech => apa3e,
186 memtech => apa3e,
185 padtech => inferred,
187 padtech => inferred,
186 clktech => inferred,
188 clktech => inferred,
187 disas => 0,
189 disas => 0,
188 dbguart => 0,
190 dbguart => 0,
189 pclow => 2,
191 pclow => 2,
190 clk_freq => 25000,
192 clk_freq => 25000,
191 IS_RADHARD => 0,
193 IS_RADHARD => 0,
192 NB_CPU => 1,
194 NB_CPU => 1,
193 ENABLE_FPU => 1,
195 ENABLE_FPU => 1,
194 FPU_NETLIST => 0,
196 FPU_NETLIST => 0,
195 ENABLE_DSU => 1,
197 ENABLE_DSU => 1,
196 ENABLE_AHB_UART => 1,
198 ENABLE_AHB_UART => 1,
197 ENABLE_APB_UART => 1,
199 ENABLE_APB_UART => 1,
198 ENABLE_IRQMP => 1,
200 ENABLE_IRQMP => 1,
199 ENABLE_GPT => 1,
201 ENABLE_GPT => 1,
200 NB_AHB_MASTER => NB_AHB_MASTER,
202 NB_AHB_MASTER => NB_AHB_MASTER,
201 NB_AHB_SLAVE => NB_AHB_SLAVE,
203 NB_AHB_SLAVE => NB_AHB_SLAVE,
202 NB_APB_SLAVE => NB_APB_SLAVE,
204 NB_APB_SLAVE => NB_APB_SLAVE,
203 ADDRESS_SIZE => 19,
205 ADDRESS_SIZE => 19,
204 USES_IAP_MEMCTRLR => 1)
206 USES_IAP_MEMCTRLR => 1)
205 PORT MAP (
207 PORT MAP (
206 clk => clk_25,
208 clk => clk_25,
207 reset => rstn,
209 reset => rstn_25,
208 errorn => OPEN,
210 errorn => OPEN,
209
211
210 ahbrxd => TAG1,
212 ahbrxd => TAG1,
211 ahbtxd => TAG3,
213 ahbtxd => TAG3,
212 urxd1 => TAG2,
214 urxd1 => TAG2,
213 utxd1 => TAG4,
215 utxd1 => TAG4,
214
216
215 address => address,
217 address => address,
216 data => data,
218 data => data,
217 nSRAM_BE0 => OPEN,
219 nSRAM_BE0 => OPEN,
218 nSRAM_BE1 => OPEN,
220 nSRAM_BE1 => OPEN,
219 nSRAM_BE2 => OPEN,
221 nSRAM_BE2 => OPEN,
220 nSRAM_BE3 => OPEN,
222 nSRAM_BE3 => OPEN,
221 nSRAM_WE => nSRAM_W,
223 nSRAM_WE => nSRAM_W,
222 nSRAM_CE => nSRAM_CE,
224 nSRAM_CE => nSRAM_CE,
223 nSRAM_OE => nSRAM_G,
225 nSRAM_OE => nSRAM_G,
224 nSRAM_READY => nSRAM_BUSY,
226 nSRAM_READY => nSRAM_BUSY,
225 SRAM_MBE => nSRAM_MBE,
227 SRAM_MBE => nSRAM_MBE,
226
228
227 apbi_ext => apbi_ext,
229 apbi_ext => apbi_ext,
228 apbo_ext => apbo_ext,
230 apbo_ext => apbo_ext,
229 ahbi_s_ext => ahbi_s_ext,
231 ahbi_s_ext => ahbi_s_ext,
230 ahbo_s_ext => ahbo_s_ext,
232 ahbo_s_ext => ahbo_s_ext,
231 ahbi_m_ext => ahbi_m_ext,
233 ahbi_m_ext => ahbi_m_ext,
232 ahbo_m_ext => ahbo_m_ext);
234 ahbo_m_ext => ahbo_m_ext);
233
235
234
236
235 nSRAM_E1 <= nSRAM_CE(0);
237 nSRAM_E1 <= nSRAM_CE(0);
236 nSRAM_E2 <= nSRAM_CE(1);
238 nSRAM_E2 <= nSRAM_CE(1);
237
239
238 -------------------------------------------------------------------------------
240 -------------------------------------------------------------------------------
239 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
241 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
240 -------------------------------------------------------------------------------
242 -------------------------------------------------------------------------------
241 apb_lfr_management_1 : apb_lfr_management
243 apb_lfr_management_1 : apb_lfr_management
242 GENERIC MAP (
244 GENERIC MAP (
243 tech => apa3e,
245 tech => apa3e,
244 pindex => 6,
246 pindex => 6,
245 paddr => 6,
247 paddr => 6,
246 pmask => 16#fff#,
248 pmask => 16#fff#,
247 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
249 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
248 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
250 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
249 PORT MAP (
251 PORT MAP (
250 clk25MHz => clk_25,
252 clk25MHz => clk_25,
251 clk24_576MHz => clk_24, -- 49.152MHz/2
253 resetn_25MHz => rstn_25, -- TODO
252 resetn => rstn,
254 clk24_576MHz => clk_24, -- 49.152MHz/2
255 resetn_24_576MHz => rstn_24, -- TODO
256
253 grspw_tick => swno.tickout,
257 grspw_tick => swno.tickout,
254 apbi => apbi_ext,
258 apbi => apbi_ext,
255 apbo => apbo_ext(6),
259 apbo => apbo_ext(6),
256
260
257 HK_sample => sample_s(8),
261 HK_sample => sample_s(8),
258 HK_val => sample_val,
262 HK_val => sample_val,
259 HK_sel => HK_SEL,
263 HK_sel => HK_SEL,
260
264
261 DAC_SDO => DAC_SDO,
265 DAC_SDO => DAC_SDO,
262 DAC_SCK => DAC_SCK,
266 DAC_SCK => DAC_SCK,
263 DAC_SYNC => DAC_SYNC,
267 DAC_SYNC => DAC_SYNC,
264 DAC_CAL_EN => DAC_CAL_EN,
268 DAC_CAL_EN => DAC_CAL_EN,
265
269
266 coarse_time => coarse_time,
270 coarse_time => coarse_time,
267 fine_time => fine_time,
271 fine_time => fine_time,
268 LFR_soft_rstn => LFR_soft_rstn
272 LFR_soft_rstn => LFR_soft_rstn
269 );
273 );
270
274
271 -----------------------------------------------------------------------
275 -----------------------------------------------------------------------
272 --- SpaceWire --------------------------------------------------------
276 --- SpaceWire --------------------------------------------------------
273 -----------------------------------------------------------------------
277 -----------------------------------------------------------------------
274
278
275 ------------------------------------------------------------------------------
279 ------------------------------------------------------------------------------
276 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
280 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
277 ------------------------------------------------------------------------------
281 ------------------------------------------------------------------------------
278 spw1_en <= '1';
282 spw1_en <= '1';
279 spw2_en <= '1';
283 spw2_en <= '1';
280 ------------------------------------------------------------------------------
284 ------------------------------------------------------------------------------
281 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
285 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
282 ------------------------------------------------------------------------------
286 ------------------------------------------------------------------------------
283
287
284 spw_clk <= clk50MHz;
288 spw_clk <= clk50MHz;
285 spw_rxtxclk <= spw_clk;
289 spw_rxtxclk <= spw_clk;
286 spw_rxclkn <= NOT spw_rxtxclk;
290 spw_rxclkn <= NOT spw_rxtxclk;
287
291
288 -- PADS for SPW1
292 -- PADS for SPW1
289 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
293 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
290 PORT MAP (spw1_din, dtmp(0));
294 PORT MAP (spw1_din, dtmp(0));
291 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
295 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
292 PORT MAP (spw1_sin, stmp(0));
296 PORT MAP (spw1_sin, stmp(0));
293 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
297 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
294 PORT MAP (spw1_dout, swno.d(0));
298 PORT MAP (spw1_dout, swno.d(0));
295 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
299 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
296 PORT MAP (spw1_sout, swno.s(0));
300 PORT MAP (spw1_sout, swno.s(0));
297 -- PADS FOR SPW2
301 -- PADS FOR SPW2
298 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
302 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
299 PORT MAP (spw2_din, dtmp(1));
303 PORT MAP (spw2_din, dtmp(1));
300 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
304 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
301 PORT MAP (spw2_sin, stmp(1));
305 PORT MAP (spw2_sin, stmp(1));
302 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
306 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
303 PORT MAP (spw2_dout, swno.d(1));
307 PORT MAP (spw2_dout, swno.d(1));
304 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
308 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
305 PORT MAP (spw2_sout, swno.s(1));
309 PORT MAP (spw2_sout, swno.s(1));
306
310
307 -- GRSPW PHY
311 -- GRSPW PHY
308 --spw1_input: if CFG_SPW_GRSPW = 1 generate
312 --spw1_input: if CFG_SPW_GRSPW = 1 generate
309 spw_inputloop : FOR j IN 0 TO 1 GENERATE
313 spw_inputloop : FOR j IN 0 TO 1 GENERATE
310 spw_phy0 : grspw_phy
314 spw_phy0 : grspw_phy
311 GENERIC MAP(
315 GENERIC MAP(
312 tech => apa3e,
316 tech => apa3e,
313 rxclkbuftype => 1,
317 rxclkbuftype => 1,
314 scantest => 0)
318 scantest => 0)
315 PORT MAP(
319 PORT MAP(
316 rxrst => swno.rxrst,
320 rxrst => swno.rxrst,
317 di => dtmp(j),
321 di => dtmp(j),
318 si => stmp(j),
322 si => stmp(j),
319 rxclko => spw_rxclk(j),
323 rxclko => spw_rxclk(j),
320 do => swni.d(j),
324 do => swni.d(j),
321 ndo => swni.nd(j*5+4 DOWNTO j*5),
325 ndo => swni.nd(j*5+4 DOWNTO j*5),
322 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
326 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
323 END GENERATE spw_inputloop;
327 END GENERATE spw_inputloop;
324
328
325 -- SPW core
329 -- SPW core
326 sw0 : grspwm GENERIC MAP(
330 sw0 : grspwm GENERIC MAP(
327 tech => apa3e,
331 tech => apa3e,
328 hindex => 1,
332 hindex => 1,
329 pindex => 5,
333 pindex => 5,
330 paddr => 5,
334 paddr => 5,
331 pirq => 11,
335 pirq => 11,
332 sysfreq => 25000, -- CPU_FREQ
336 sysfreq => 25000, -- CPU_FREQ
333 rmap => 1,
337 rmap => 1,
334 rmapcrc => 1,
338 rmapcrc => 1,
335 fifosize1 => 16,
339 fifosize1 => 16,
336 fifosize2 => 16,
340 fifosize2 => 16,
337 rxclkbuftype => 1,
341 rxclkbuftype => 1,
338 rxunaligned => 0,
342 rxunaligned => 0,
339 rmapbufs => 4,
343 rmapbufs => 4,
340 ft => 0,
344 ft => 0,
341 netlist => 0,
345 netlist => 0,
342 ports => 2,
346 ports => 2,
343 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
347 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
344 memtech => apa3e,
348 memtech => apa3e,
345 destkey => 2,
349 destkey => 2,
346 spwcore => 1
350 spwcore => 1
347 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
351 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
348 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
352 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
349 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
353 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
350 )
354 )
351 PORT MAP(rstn, clk_25, spw_rxclk(0),
355 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
352 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
356 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
353 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
357 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
354 swni, swno);
358 swni, swno);
355
359
356 swni.tickin <= '0';
360 swni.tickin <= '0';
357 swni.rmapen <= '1';
361 swni.rmapen <= '1';
358 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
362 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
359 swni.tickinraw <= '0';
363 swni.tickinraw <= '0';
360 swni.timein <= (OTHERS => '0');
364 swni.timein <= (OTHERS => '0');
361 swni.dcrstval <= (OTHERS => '0');
365 swni.dcrstval <= (OTHERS => '0');
362 swni.timerrstval <= (OTHERS => '0');
366 swni.timerrstval <= (OTHERS => '0');
363
367
364 -------------------------------------------------------------------------------
368 -------------------------------------------------------------------------------
365 -- LFR ------------------------------------------------------------------------
369 -- LFR ------------------------------------------------------------------------
366 -------------------------------------------------------------------------------
370 -------------------------------------------------------------------------------
367 LFR_rstn <= LFR_soft_rstn AND rstn;
371 LFR_rstn <= LFR_soft_rstn AND rstn_25;
368
372
369 lpp_lfr_1 : lpp_lfr
373 lpp_lfr_1 : lpp_lfr
370 GENERIC MAP (
374 GENERIC MAP (
371 Mem_use => use_RAM,
375 Mem_use => use_RAM,
372 nb_data_by_buffer_size => 32,
376 nb_data_by_buffer_size => 32,
373 --nb_word_by_buffer_size => 30,
377 --nb_word_by_buffer_size => 30,
374 nb_snapshot_param_size => 32,
378 nb_snapshot_param_size => 32,
375 delta_vector_size => 32,
379 delta_vector_size => 32,
376 delta_vector_size_f0_2 => 7, -- log2(96)
380 delta_vector_size_f0_2 => 7, -- log2(96)
377 pindex => 15,
381 pindex => 15,
378 paddr => 15,
382 paddr => 15,
379 pmask => 16#fff#,
383 pmask => 16#fff#,
380 pirq_ms => 6,
384 pirq_ms => 6,
381 pirq_wfp => 14,
385 pirq_wfp => 14,
382 hindex => 2,
386 hindex => 2,
383 top_lfr_version => X"02013F") -- aa.bb.cc version
387 top_lfr_version => X"020144") -- aa.bb.cc version
384 -- AA : BOARD NUMBER
388 -- AA : BOARD NUMBER
385 -- 0 => MINI_LFR
389 -- 0 => MINI_LFR
386 -- 1 => EM
390 -- 1 => EM
387 -- 1 => EQM (with A3PE3000)
391 -- 1 => EQM (with A3PE3000)
388 PORT MAP (
392 PORT MAP (
389 clk => clk_25,
393 clk => clk_25,
390 rstn => LFR_rstn,
394 rstn => LFR_rstn,
391 sample_B => sample_s(2 DOWNTO 0),
395 sample_B => sample_s(2 DOWNTO 0),
392 sample_E => sample_s(7 DOWNTO 3),
396 sample_E => sample_s(7 DOWNTO 3),
393 sample_val => sample_val,
397 sample_val => sample_val,
394 apbi => apbi_ext,
398 apbi => apbi_ext,
395 apbo => apbo_ext(15),
399 apbo => apbo_ext(15),
396 ahbi => ahbi_m_ext,
400 ahbi => ahbi_m_ext,
397 ahbo => ahbo_m_ext(2),
401 ahbo => ahbo_m_ext(2),
398 coarse_time => coarse_time,
402 coarse_time => coarse_time,
399 fine_time => fine_time,
403 fine_time => fine_time,
400 data_shaping_BW => bias_fail_sw,
404 data_shaping_BW => bias_fail_sw,
401 debug_vector => OPEN,
405 debug_vector => OPEN,
402 debug_vector_ms => OPEN); --,
406 debug_vector_ms => OPEN); --,
403 --observation_vector_0 => OPEN,
407 --observation_vector_0 => OPEN,
404 --observation_vector_1 => OPEN,
408 --observation_vector_1 => OPEN,
405 --observation_reg => observation_reg);
409 --observation_reg => observation_reg);
406
410
407
411
408 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
412 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
409 sample_s(I) <= sample(I) & '0' & '0';
413 sample_s(I) <= sample(I) & '0' & '0';
410 END GENERATE all_sample;
414 END GENERATE all_sample;
411 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
415 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
412
416
413 -----------------------------------------------------------------------------
417 -----------------------------------------------------------------------------
414 --
418 --
415 -----------------------------------------------------------------------------
419 -----------------------------------------------------------------------------
416 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
420 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
417 GENERIC MAP (
421 GENERIC MAP (
418 ChanelCount => 9,
422 ChanelCount => 9,
419 ncycle_cnv_high => 13,
423 ncycle_cnv_high => 13,
420 ncycle_cnv => 25,
424 ncycle_cnv => 25,
421 FILTER_ENABLED => 16#FF#)
425 FILTER_ENABLED => 16#FF#)
422 PORT MAP (
426 PORT MAP (
423 cnv_clk => clk_24,
427 cnv_clk => clk_24,
424 cnv_rstn => rstn,
428 cnv_rstn => rstn_24,
425 cnv => ADC_smpclk_s,
429 cnv => ADC_smpclk_s,
426 clk => clk_25,
430 clk => clk_25,
427 rstn => rstn,
431 rstn => rstn_25,
428 ADC_data => ADC_data,
432 ADC_data => ADC_data,
429 ADC_nOE => ADC_OEB_bar_CH_s,
433 ADC_nOE => ADC_OEB_bar_CH_s,
430 sample => sample,
434 sample => sample,
431 sample_val => sample_val);
435 sample_val => sample_val);
432
436
433 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
437 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
434
438
435 ADC_smpclk <= ADC_smpclk_s;
439 ADC_smpclk <= ADC_smpclk_s;
436 HK_smpclk <= ADC_smpclk_s;
440 HK_smpclk <= ADC_smpclk_s;
437
441
438 TAG8 <= ADC_smpclk_s;
442 TAG8 <= ADC_smpclk_s;
439
443
440 -----------------------------------------------------------------------------
444 -----------------------------------------------------------------------------
441 -- HK
445 -- HK
442 -----------------------------------------------------------------------------
446 -----------------------------------------------------------------------------
443 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
447 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
444
448
445 END beh;
449 END beh;
Show file before | Show file after | Hide comments
@@ -1,455 +1,459
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY LFR_em IS
48 ENTITY LFR_em IS
49
49
50 PORT (
50 PORT (
51 clk100MHz : IN STD_ULOGIC;
51 clk100MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
54
54
55 -- TAG --------------------------------------------------------------------
55 -- TAG --------------------------------------------------------------------
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 -- UART APB ---------------------------------------------------------------
58 -- UART APB ---------------------------------------------------------------
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 -- RAM --------------------------------------------------------------------
61 -- RAM --------------------------------------------------------------------
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 nSRAM_BE0 : OUT STD_LOGIC;
64 nSRAM_BE0 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
71 -- SPW --------------------------------------------------------------------
71 -- SPW --------------------------------------------------------------------
72 spw1_din : IN STD_LOGIC;
72 spw1_din : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
80 -- ADC --------------------------------------------------------------------
80 -- ADC --------------------------------------------------------------------
81 bias_fail_sw : OUT STD_LOGIC;
81 bias_fail_sw : OUT STD_LOGIC;
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 ADC_smpclk : OUT STD_LOGIC;
83 ADC_smpclk : OUT STD_LOGIC;
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 -- DAC --------------------------------------------------------------------
85 -- DAC --------------------------------------------------------------------
86 DAC_SDO : OUT STD_LOGIC;
86 DAC_SDO : OUT STD_LOGIC;
87 DAC_SCK : OUT STD_LOGIC;
87 DAC_SCK : OUT STD_LOGIC;
88 DAC_SYNC : OUT STD_LOGIC;
88 DAC_SYNC : OUT STD_LOGIC;
89 DAC_CAL_EN : OUT STD_LOGIC;
89 DAC_CAL_EN : OUT STD_LOGIC;
90 -- HK ---------------------------------------------------------------------
90 -- HK ---------------------------------------------------------------------
91 HK_smpclk : OUT STD_LOGIC;
91 HK_smpclk : OUT STD_LOGIC;
92 ADC_OEB_bar_HK : OUT STD_LOGIC;
92 ADC_OEB_bar_HK : OUT STD_LOGIC;
93 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
93 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
94 ---------------------------------------------------------------------------
94 ---------------------------------------------------------------------------
95 TAG8 : OUT STD_LOGIC;
95 TAG8 : OUT STD_LOGIC;
96 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
96 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
97 );
97 );
98
98
99 END LFR_em;
99 END LFR_em;
100
100
101
101
102 ARCHITECTURE beh OF LFR_em IS
102 ARCHITECTURE beh OF LFR_em IS
103 SIGNAL clk_50_s : STD_LOGIC := '0';
103 SIGNAL clk_50_s : STD_LOGIC := '0';
104 SIGNAL clk_25 : STD_LOGIC := '0';
104 SIGNAL clk_25 : STD_LOGIC := '0';
105 SIGNAL clk_24 : STD_LOGIC := '0';
105 SIGNAL clk_24 : STD_LOGIC := '0';
106 -----------------------------------------------------------------------------
106 -----------------------------------------------------------------------------
107 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
107 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
108 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
109
109
110 -- CONSTANTS
110 -- CONSTANTS
111 CONSTANT CFG_PADTECH : INTEGER := inferred;
111 CONSTANT CFG_PADTECH : INTEGER := inferred;
112 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
112 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
113 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
113 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
114 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
114 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
115
115
116 SIGNAL apbi_ext : apb_slv_in_type;
116 SIGNAL apbi_ext : apb_slv_in_type;
117 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
117 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
118 SIGNAL ahbi_s_ext : ahb_slv_in_type;
118 SIGNAL ahbi_s_ext : ahb_slv_in_type;
119 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
119 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
120 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
120 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
121 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
121 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
122
122
123 -- Spacewire signals
123 -- Spacewire signals
124 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
124 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
125 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
125 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
126 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
126 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
127 SIGNAL spw_rxtxclk : STD_ULOGIC;
127 SIGNAL spw_rxtxclk : STD_ULOGIC;
128 SIGNAL spw_rxclkn : STD_ULOGIC;
128 SIGNAL spw_rxclkn : STD_ULOGIC;
129 SIGNAL spw_clk : STD_LOGIC;
129 SIGNAL spw_clk : STD_LOGIC;
130 SIGNAL swni : grspw_in_type;
130 SIGNAL swni : grspw_in_type;
131 SIGNAL swno : grspw_out_type;
131 SIGNAL swno : grspw_out_type;
132
132
133 --GPIO
133 --GPIO
134 SIGNAL gpioi : gpio_in_type;
134 SIGNAL gpioi : gpio_in_type;
135 SIGNAL gpioo : gpio_out_type;
135 SIGNAL gpioo : gpio_out_type;
136
136
137 -- AD Converter ADS7886
137 -- AD Converter ADS7886
138 SIGNAL sample : Samples14v(8 DOWNTO 0);
138 SIGNAL sample : Samples14v(8 DOWNTO 0);
139 SIGNAL sample_s : Samples(8 DOWNTO 0);
139 SIGNAL sample_s : Samples(8 DOWNTO 0);
140 SIGNAL sample_val : STD_LOGIC;
140 SIGNAL sample_val : STD_LOGIC;
141 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
141 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
142
142
143 -----------------------------------------------------------------------------
143 -----------------------------------------------------------------------------
144 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
144 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
145
145
146 -----------------------------------------------------------------------------
146 -----------------------------------------------------------------------------
147 SIGNAL rstn : STD_LOGIC;
147 SIGNAL rstn_25 : STD_LOGIC;
148 SIGNAL rstn_24 : STD_LOGIC;
148
149
149 SIGNAL LFR_soft_rstn : STD_LOGIC;
150 SIGNAL LFR_soft_rstn : STD_LOGIC;
150 SIGNAL LFR_rstn : STD_LOGIC;
151 SIGNAL LFR_rstn : STD_LOGIC;
151
152
152 SIGNAL ADC_smpclk_s : STD_LOGIC;
153 SIGNAL ADC_smpclk_s : STD_LOGIC;
153 -----------------------------------------------------------------------------
154 ----------------------------------------------------------------------------
154 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
155 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
155
156
156 BEGIN -- beh
157 BEGIN -- beh
157
158
158 -----------------------------------------------------------------------------
159 -----------------------------------------------------------------------------
159 -- CLK
160 -- CLK
160 -----------------------------------------------------------------------------
161 -----------------------------------------------------------------------------
161 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
162 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
163 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
162
164
163 PROCESS(clk100MHz)
165 PROCESS(clk100MHz)
164 BEGIN
166 BEGIN
165 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
167 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
166 clk_50_s <= NOT clk_50_s;
168 clk_50_s <= NOT clk_50_s;
167 END IF;
169 END IF;
168 END PROCESS;
170 END PROCESS;
169
171
170 PROCESS(clk_50_s)
172 PROCESS(clk_50_s)
171 BEGIN
173 BEGIN
172 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
174 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
173 clk_25 <= NOT clk_25;
175 clk_25 <= NOT clk_25;
174 END IF;
176 END IF;
175 END PROCESS;
177 END PROCESS;
176
178
177 PROCESS(clk49_152MHz)
179 PROCESS(clk49_152MHz)
178 BEGIN
180 BEGIN
179 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
181 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
180 clk_24 <= NOT clk_24;
182 clk_24 <= NOT clk_24;
181 END IF;
183 END IF;
182 END PROCESS;
184 END PROCESS;
183
185
184 -----------------------------------------------------------------------------
186 -----------------------------------------------------------------------------
185
187
186 PROCESS (clk_25, rstn)
188 PROCESS (clk_25, rstn_25)
187 BEGIN -- PROCESS
189 BEGIN -- PROCESS
188 IF rstn = '0' THEN -- asynchronous reset (active low)
190 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
189 led(0) <= '0';
191 led(0) <= '0';
190 led(1) <= '0';
192 led(1) <= '0';
191 led(2) <= '0';
193 led(2) <= '0';
192 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
194 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
193 led(0) <= '0';
195 led(0) <= '0';
194 led(1) <= '1';
196 led(1) <= '1';
195 led(2) <= '1';
197 led(2) <= '1';
196 END IF;
198 END IF;
197 END PROCESS;
199 END PROCESS;
198
200
199 --
201 --
200 leon3_soc_1 : leon3_soc
202 leon3_soc_1 : leon3_soc
201 GENERIC MAP (
203 GENERIC MAP (
202 fabtech => apa3e,
204 fabtech => apa3e,
203 memtech => apa3e,
205 memtech => apa3e,
204 padtech => inferred,
206 padtech => inferred,
205 clktech => inferred,
207 clktech => inferred,
206 disas => 0,
208 disas => 0,
207 dbguart => 0,
209 dbguart => 0,
208 pclow => 2,
210 pclow => 2,
209 clk_freq => 25000,
211 clk_freq => 25000,
210 IS_RADHARD => 0,
212 IS_RADHARD => 0,
211 NB_CPU => 1,
213 NB_CPU => 1,
212 ENABLE_FPU => 1,
214 ENABLE_FPU => 1,
213 FPU_NETLIST => 0,
215 FPU_NETLIST => 0,
214 ENABLE_DSU => 1,
216 ENABLE_DSU => 1,
215 ENABLE_AHB_UART => 1,
217 ENABLE_AHB_UART => 1,
216 ENABLE_APB_UART => 1,
218 ENABLE_APB_UART => 1,
217 ENABLE_IRQMP => 1,
219 ENABLE_IRQMP => 1,
218 ENABLE_GPT => 1,
220 ENABLE_GPT => 1,
219 NB_AHB_MASTER => NB_AHB_MASTER,
221 NB_AHB_MASTER => NB_AHB_MASTER,
220 NB_AHB_SLAVE => NB_AHB_SLAVE,
222 NB_AHB_SLAVE => NB_AHB_SLAVE,
221 NB_APB_SLAVE => NB_APB_SLAVE,
223 NB_APB_SLAVE => NB_APB_SLAVE,
222 ADDRESS_SIZE => 20,
224 ADDRESS_SIZE => 20,
223 USES_IAP_MEMCTRLR => 0)
225 USES_IAP_MEMCTRLR => 0)
224 PORT MAP (
226 PORT MAP (
225 clk => clk_25,
227 clk => clk_25,
226 reset => rstn,
228 reset => rstn_25,
227 errorn => OPEN,
229 errorn => OPEN,
228
230
229 ahbrxd => TAG1,
231 ahbrxd => TAG1,
230 ahbtxd => TAG3,
232 ahbtxd => TAG3,
231 urxd1 => TAG2,
233 urxd1 => TAG2,
232 utxd1 => TAG4,
234 utxd1 => TAG4,
233
235
234 address => address,
236 address => address,
235 data => data,
237 data => data,
236 nSRAM_BE0 => nSRAM_BE0,
238 nSRAM_BE0 => nSRAM_BE0,
237 nSRAM_BE1 => nSRAM_BE1,
239 nSRAM_BE1 => nSRAM_BE1,
238 nSRAM_BE2 => nSRAM_BE2,
240 nSRAM_BE2 => nSRAM_BE2,
239 nSRAM_BE3 => nSRAM_BE3,
241 nSRAM_BE3 => nSRAM_BE3,
240 nSRAM_WE => nSRAM_WE,
242 nSRAM_WE => nSRAM_WE,
241 nSRAM_CE => nSRAM_CE_s,
243 nSRAM_CE => nSRAM_CE_s,
242 nSRAM_OE => nSRAM_OE,
244 nSRAM_OE => nSRAM_OE,
243 nSRAM_READY => '0',
245 nSRAM_READY => '0',
244 SRAM_MBE => OPEN,
246 SRAM_MBE => OPEN,
245
247
246 apbi_ext => apbi_ext,
248 apbi_ext => apbi_ext,
247 apbo_ext => apbo_ext,
249 apbo_ext => apbo_ext,
248 ahbi_s_ext => ahbi_s_ext,
250 ahbi_s_ext => ahbi_s_ext,
249 ahbo_s_ext => ahbo_s_ext,
251 ahbo_s_ext => ahbo_s_ext,
250 ahbi_m_ext => ahbi_m_ext,
252 ahbi_m_ext => ahbi_m_ext,
251 ahbo_m_ext => ahbo_m_ext);
253 ahbo_m_ext => ahbo_m_ext);
252
254
253
255
254 nSRAM_CE <= nSRAM_CE_s(0);
256 nSRAM_CE <= nSRAM_CE_s(0);
255
257
256 -------------------------------------------------------------------------------
258 -------------------------------------------------------------------------------
257 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
259 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
258 -------------------------------------------------------------------------------
260 -------------------------------------------------------------------------------
259 apb_lfr_management_1 : apb_lfr_management
261 apb_lfr_management_1 : apb_lfr_management
260 GENERIC MAP (
262 GENERIC MAP (
261 tech => apa3e,
263 tech => apa3e,
262 pindex => 6,
264 pindex => 6,
263 paddr => 6,
265 paddr => 6,
264 pmask => 16#fff#,
266 pmask => 16#fff#,
265 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
267 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
266 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
268 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
267 PORT MAP (
269 PORT MAP (
268 clk25MHz => clk_25,
270 clk25MHz => clk_25,
269 clk24_576MHz => clk_24, -- 49.152MHz/2
271 resetn_25MHz => rstn_25, -- TODO
270 resetn => rstn,
272 clk24_576MHz => clk_24, -- 49.152MHz/2
273 resetn_24_576MHz => rstn_24, -- TODO
274
271 grspw_tick => swno.tickout,
275 grspw_tick => swno.tickout,
272 apbi => apbi_ext,
276 apbi => apbi_ext,
273 apbo => apbo_ext(6),
277 apbo => apbo_ext(6),
274
278
275 HK_sample => sample_s(8),
279 HK_sample => sample_s(8),
276 HK_val => sample_val,
280 HK_val => sample_val,
277 HK_sel => HK_SEL,
281 HK_sel => HK_SEL,
278
282
279 DAC_SDO => DAC_SDO,
283 DAC_SDO => DAC_SDO,
280 DAC_SCK => DAC_SCK,
284 DAC_SCK => DAC_SCK,
281 DAC_SYNC => DAC_SYNC,
285 DAC_SYNC => DAC_SYNC,
282 DAC_CAL_EN => DAC_CAL_EN,
286 DAC_CAL_EN => DAC_CAL_EN,
283
287
284 coarse_time => coarse_time,
288 coarse_time => coarse_time,
285 fine_time => fine_time,
289 fine_time => fine_time,
286 LFR_soft_rstn => LFR_soft_rstn
290 LFR_soft_rstn => LFR_soft_rstn
287 );
291 );
288
292
289 -----------------------------------------------------------------------
293 -----------------------------------------------------------------------
290 --- SpaceWire --------------------------------------------------------
294 --- SpaceWire --------------------------------------------------------
291 -----------------------------------------------------------------------
295 -----------------------------------------------------------------------
292
296
293 -- SPW_EN <= '1';
297 -- SPW_EN <= '1';
294
298
295 spw_clk <= clk_50_s;
299 spw_clk <= clk_50_s;
296 spw_rxtxclk <= spw_clk;
300 spw_rxtxclk <= spw_clk;
297 spw_rxclkn <= NOT spw_rxtxclk;
301 spw_rxclkn <= NOT spw_rxtxclk;
298
302
299 -- PADS for SPW1
303 -- PADS for SPW1
300 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
304 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
301 PORT MAP (spw1_din, dtmp(0));
305 PORT MAP (spw1_din, dtmp(0));
302 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
306 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
303 PORT MAP (spw1_sin, stmp(0));
307 PORT MAP (spw1_sin, stmp(0));
304 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
308 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
305 PORT MAP (spw1_dout, swno.d(0));
309 PORT MAP (spw1_dout, swno.d(0));
306 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
310 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
307 PORT MAP (spw1_sout, swno.s(0));
311 PORT MAP (spw1_sout, swno.s(0));
308 -- PADS FOR SPW2
312 -- PADS FOR SPW2
309 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
313 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
310 PORT MAP (spw2_din, dtmp(1));
314 PORT MAP (spw2_din, dtmp(1));
311 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
315 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
312 PORT MAP (spw2_sin, stmp(1));
316 PORT MAP (spw2_sin, stmp(1));
313 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
317 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
314 PORT MAP (spw2_dout, swno.d(1));
318 PORT MAP (spw2_dout, swno.d(1));
315 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
319 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
316 PORT MAP (spw2_sout, swno.s(1));
320 PORT MAP (spw2_sout, swno.s(1));
317
321
318 -- GRSPW PHY
322 -- GRSPW PHY
319 --spw1_input: if CFG_SPW_GRSPW = 1 generate
323 --spw1_input: if CFG_SPW_GRSPW = 1 generate
320 spw_inputloop : FOR j IN 0 TO 1 GENERATE
324 spw_inputloop : FOR j IN 0 TO 1 GENERATE
321 spw_phy0 : grspw_phy
325 spw_phy0 : grspw_phy
322 GENERIC MAP(
326 GENERIC MAP(
323 tech => apa3e,
327 tech => apa3e,
324 rxclkbuftype => 1,
328 rxclkbuftype => 1,
325 scantest => 0)
329 scantest => 0)
326 PORT MAP(
330 PORT MAP(
327 rxrst => swno.rxrst,
331 rxrst => swno.rxrst,
328 di => dtmp(j),
332 di => dtmp(j),
329 si => stmp(j),
333 si => stmp(j),
330 rxclko => spw_rxclk(j),
334 rxclko => spw_rxclk(j),
331 do => swni.d(j),
335 do => swni.d(j),
332 ndo => swni.nd(j*5+4 DOWNTO j*5),
336 ndo => swni.nd(j*5+4 DOWNTO j*5),
333 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
337 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
334 END GENERATE spw_inputloop;
338 END GENERATE spw_inputloop;
335
339
336 -- SPW core
340 -- SPW core
337 sw0 : grspwm GENERIC MAP(
341 sw0 : grspwm GENERIC MAP(
338 tech => apa3e,
342 tech => apa3e,
339 hindex => 1,
343 hindex => 1,
340 pindex => 5,
344 pindex => 5,
341 paddr => 5,
345 paddr => 5,
342 pirq => 11,
346 pirq => 11,
343 sysfreq => 25000, -- CPU_FREQ
347 sysfreq => 25000, -- CPU_FREQ
344 rmap => 1,
348 rmap => 1,
345 rmapcrc => 1,
349 rmapcrc => 1,
346 fifosize1 => 16,
350 fifosize1 => 16,
347 fifosize2 => 16,
351 fifosize2 => 16,
348 rxclkbuftype => 1,
352 rxclkbuftype => 1,
349 rxunaligned => 0,
353 rxunaligned => 0,
350 rmapbufs => 4,
354 rmapbufs => 4,
351 ft => 0,
355 ft => 0,
352 netlist => 0,
356 netlist => 0,
353 ports => 2,
357 ports => 2,
354 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
358 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
355 memtech => apa3e,
359 memtech => apa3e,
356 destkey => 2,
360 destkey => 2,
357 spwcore => 1
361 spwcore => 1
358 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
362 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
359 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
363 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
360 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
364 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
361 )
365 )
362 PORT MAP(rstn, clk_25, spw_rxclk(0),
366 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
363 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
367 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
364 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
368 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
365 swni, swno);
369 swni, swno);
366
370
367 swni.tickin <= '0';
371 swni.tickin <= '0';
368 swni.rmapen <= '1';
372 swni.rmapen <= '1';
369 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
373 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
370 swni.tickinraw <= '0';
374 swni.tickinraw <= '0';
371 swni.timein <= (OTHERS => '0');
375 swni.timein <= (OTHERS => '0');
372 swni.dcrstval <= (OTHERS => '0');
376 swni.dcrstval <= (OTHERS => '0');
373 swni.timerrstval <= (OTHERS => '0');
377 swni.timerrstval <= (OTHERS => '0');
374
378
375 -------------------------------------------------------------------------------
379 -------------------------------------------------------------------------------
376 -- LFR ------------------------------------------------------------------------
380 -- LFR ------------------------------------------------------------------------
377 -------------------------------------------------------------------------------
381 -------------------------------------------------------------------------------
378 LFR_rstn <= LFR_soft_rstn AND rstn;
382 LFR_rstn <= LFR_soft_rstn AND rstn_25;
379
383
380 lpp_lfr_1 : lpp_lfr
384 lpp_lfr_1 : lpp_lfr
381 GENERIC MAP (
385 GENERIC MAP (
382 Mem_use => use_RAM,
386 Mem_use => use_RAM,
383 nb_data_by_buffer_size => 32,
387 nb_data_by_buffer_size => 32,
384 --nb_word_by_buffer_size => 30,
388 --nb_word_by_buffer_size => 30,
385 nb_snapshot_param_size => 32,
389 nb_snapshot_param_size => 32,
386 delta_vector_size => 32,
390 delta_vector_size => 32,
387 delta_vector_size_f0_2 => 7, -- log2(96)
391 delta_vector_size_f0_2 => 7, -- log2(96)
388 pindex => 15,
392 pindex => 15,
389 paddr => 15,
393 paddr => 15,
390 pmask => 16#fff#,
394 pmask => 16#fff#,
391 pirq_ms => 6,
395 pirq_ms => 6,
392 pirq_wfp => 14,
396 pirq_wfp => 14,
393 hindex => 2,
397 hindex => 2,
394 top_lfr_version => X"010143") -- aa.bb.cc version
398 top_lfr_version => X"010144") -- aa.bb.cc version
395 -- AA : BOARD NUMBER
399 -- AA : BOARD NUMBER
396 -- 0 => MINI_LFR
400 -- 0 => MINI_LFR
397 -- 1 => EM
401 -- 1 => EM
398 PORT MAP (
402 PORT MAP (
399 clk => clk_25,
403 clk => clk_25,
400 rstn => LFR_rstn,
404 rstn => LFR_rstn,
401 sample_B => sample_s(2 DOWNTO 0),
405 sample_B => sample_s(2 DOWNTO 0),
402 sample_E => sample_s(7 DOWNTO 3),
406 sample_E => sample_s(7 DOWNTO 3),
403 sample_val => sample_val,
407 sample_val => sample_val,
404 apbi => apbi_ext,
408 apbi => apbi_ext,
405 apbo => apbo_ext(15),
409 apbo => apbo_ext(15),
406 ahbi => ahbi_m_ext,
410 ahbi => ahbi_m_ext,
407 ahbo => ahbo_m_ext(2),
411 ahbo => ahbo_m_ext(2),
408 coarse_time => coarse_time,
412 coarse_time => coarse_time,
409 fine_time => fine_time,
413 fine_time => fine_time,
410 data_shaping_BW => bias_fail_sw,
414 data_shaping_BW => bias_fail_sw,
411 debug_vector => OPEN,
415 debug_vector => OPEN,
412 debug_vector_ms => OPEN); --,
416 debug_vector_ms => OPEN); --,
413 --observation_vector_0 => OPEN,
417 --observation_vector_0 => OPEN,
414 --observation_vector_1 => OPEN,
418 --observation_vector_1 => OPEN,
415 --observation_reg => observation_reg);
419 --observation_reg => observation_reg);
416
420
417
421
418 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
422 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
419 sample_s(I) <= sample(I) & '0' & '0';
423 sample_s(I) <= sample(I) & '0' & '0';
420 END GENERATE all_sample;
424 END GENERATE all_sample;
421 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
425 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
422
426
423 -----------------------------------------------------------------------------
427 -----------------------------------------------------------------------------
424 --
428 --
425 -----------------------------------------------------------------------------
429 -----------------------------------------------------------------------------
426 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
430 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
427 GENERIC MAP (
431 GENERIC MAP (
428 ChanelCount => 9,
432 ChanelCount => 9,
429 ncycle_cnv_high => 13,
433 ncycle_cnv_high => 13,
430 ncycle_cnv => 25,
434 ncycle_cnv => 25,
431 FILTER_ENABLED => 16#FF#)
435 FILTER_ENABLED => 16#FF#)
432 PORT MAP (
436 PORT MAP (
433 cnv_clk => clk_24,
437 cnv_clk => clk_24,
434 cnv_rstn => rstn,
438 cnv_rstn => rstn_24,
435 cnv => ADC_smpclk_s,
439 cnv => ADC_smpclk_s,
436 clk => clk_25,
440 clk => clk_25,
437 rstn => rstn,
441 rstn => rstn_25,
438 ADC_data => ADC_data,
442 ADC_data => ADC_data,
439 ADC_nOE => ADC_OEB_bar_CH_s,
443 ADC_nOE => ADC_OEB_bar_CH_s,
440 sample => sample,
444 sample => sample,
441 sample_val => sample_val);
445 sample_val => sample_val);
442
446
443 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
447 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
444
448
445 ADC_smpclk <= ADC_smpclk_s;
449 ADC_smpclk <= ADC_smpclk_s;
446 HK_smpclk <= ADC_smpclk_s;
450 HK_smpclk <= ADC_smpclk_s;
447
451
448 TAG8 <= ADC_smpclk_s;
452 TAG8 <= ADC_smpclk_s;
449
453
450 -----------------------------------------------------------------------------
454 -----------------------------------------------------------------------------
451 -- HK
455 -- HK
452 -----------------------------------------------------------------------------
456 -----------------------------------------------------------------------------
453 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
457 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
454
458
455 END beh;
459 END beh;
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@@ -1,58 +1,58
1 #GRLIB=../..
1 #GRLIB=../..
2 VHDLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=LFR_em
5 TOP=LFR_em
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
11 EFFORT=high
12 XSTOPT=
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
16 VHDLSYNFILES=LFR-em.vhd
16 VHDLSYNFILES=LFR-em.vhd
17 VHDLSIMFILES=testbench.vhd
17 VHDLSIMFILES=testbench.vhd
18 #SIMTOP=testbench
18 #SIMTOP=testbench
19 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
20 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
20 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
21 PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL_withHK-DAC.pdc
21 PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL_withHK-DAC.pdc
22
22
23 #SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
23 SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
24 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc
24 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc
25
25
26 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
26 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
27 CLEAN=soft-clean
27 CLEAN=soft-clean
28
28
29 TECHLIBS = proasic3e
29 TECHLIBS = proasic3e
30
30
31 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
31 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
32 tmtc openchip hynix ihp gleichmann micron usbhc
32 tmtc openchip hynix ihp gleichmann micron usbhc
33
33
34 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
34 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
35 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
35 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
36 ./amba_lcd_16x2_ctrlr \
36 ./amba_lcd_16x2_ctrlr \
37 ./general_purpose/lpp_AMR \
37 ./general_purpose/lpp_AMR \
38 ./general_purpose/lpp_balise \
38 ./general_purpose/lpp_balise \
39 ./general_purpose/lpp_delay \
39 ./general_purpose/lpp_delay \
40 ./lpp_bootloader \
40 ./lpp_bootloader \
41 ./dsp/lpp_fft_rtax \
41 ./dsp/lpp_fft_rtax \
42 ./lpp_uart \
42 ./lpp_uart \
43 ./lpp_usb \
43 ./lpp_usb \
44 ./lpp_sim/CY7C1061DV33 \
44 ./lpp_sim/CY7C1061DV33 \
45
45
46 FILESKIP = i2cmst.vhd \
46 FILESKIP = i2cmst.vhd \
47 APB_MULTI_DIODE.vhd \
47 APB_MULTI_DIODE.vhd \
48 APB_MULTI_DIODE.vhd \
48 APB_MULTI_DIODE.vhd \
49 Top_MatrixSpec.vhd \
49 Top_MatrixSpec.vhd \
50 APB_FFT.vhd\
50 APB_FFT.vhd\
51 CoreFFT_simu.vhd \
51 CoreFFT_simu.vhd \
52 lpp_lfr_apbreg_simu.vhd
52 lpp_lfr_apbreg_simu.vhd
53
53
54 include $(GRLIB)/bin/Makefile
54 include $(GRLIB)/bin/Makefile
55 include $(GRLIB)/software/leon3/Makefile
55 include $(GRLIB)/software/leon3/Makefile
56
56
57 ################## project specific targets ##########################
57 ################## project specific targets ##########################
58
58
Show file before | Show file after | Hide comments
@@ -1,751 +1,740
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178
178
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
181
181
182
182
183 SIGNAL rstn_25 : STD_LOGIC;
183 SIGNAL rstn_25 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
187
187
188 SIGNAL rstn_24 : STD_LOGIC;
188 SIGNAL rstn_24 : STD_LOGIC;
189 SIGNAL rstn_24_d1 : STD_LOGIC;
189 SIGNAL rstn_24_d1 : STD_LOGIC;
190 SIGNAL rstn_24_d2 : STD_LOGIC;
190 SIGNAL rstn_24_d2 : STD_LOGIC;
191 SIGNAL rstn_24_d3 : STD_LOGIC;
191 SIGNAL rstn_24_d3 : STD_LOGIC;
192
192
193 SIGNAL rstn_50 : STD_LOGIC;
193 SIGNAL rstn_50 : STD_LOGIC;
194 SIGNAL rstn_50_d1 : STD_LOGIC;
194 SIGNAL rstn_50_d1 : STD_LOGIC;
195 SIGNAL rstn_50_d2 : STD_LOGIC;
195 SIGNAL rstn_50_d2 : STD_LOGIC;
196 SIGNAL rstn_50_d3 : STD_LOGIC;
196 SIGNAL rstn_50_d3 : STD_LOGIC;
197
197
198 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
198 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
199 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
199 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
200
200
201 --
201 --
202 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
202 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
203
203
204 --
204 --
205 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
205 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
206 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
206 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
207
207
208 BEGIN -- beh
208 BEGIN -- beh
209
209
210 -----------------------------------------------------------------------------
210 -----------------------------------------------------------------------------
211 -- CLK
211 -- CLK
212 -----------------------------------------------------------------------------
212 -----------------------------------------------------------------------------
213
213
214 --PROCESS(clk_50)
214 --PROCESS(clk_50)
215 --BEGIN
215 --BEGIN
216 -- IF clk_50'EVENT AND clk_50 = '1' THEN
216 -- IF clk_50'EVENT AND clk_50 = '1' THEN
217 -- clk_50_s <= NOT clk_50_s;
217 -- clk_50_s <= NOT clk_50_s;
218 -- END IF;
218 -- END IF;
219 --END PROCESS;
219 --END PROCESS;
220
220
221 --PROCESS(clk_50_s)
221 --PROCESS(clk_50_s)
222 --BEGIN
222 --BEGIN
223 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
223 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
224 -- clk_25 <= NOT clk_25;
224 -- clk_25 <= NOT clk_25;
225 -- END IF;
225 -- END IF;
226 --END PROCESS;
226 --END PROCESS;
227
227
228 --PROCESS(clk_49)
228 --PROCESS(clk_49)
229 --BEGIN
229 --BEGIN
230 -- IF clk_49'EVENT AND clk_49 = '1' THEN
230 -- IF clk_49'EVENT AND clk_49 = '1' THEN
231 -- clk_24 <= NOT clk_24;
231 -- clk_24 <= NOT clk_24;
232 -- END IF;
232 -- END IF;
233 --END PROCESS;
233 --END PROCESS;
234
234
235 --PROCESS(clk_25)
235 --PROCESS(clk_25)
236 --BEGIN
236 --BEGIN
237 -- IF clk_25'EVENT AND clk_25 = '1' THEN
237 -- IF clk_25'EVENT AND clk_25 = '1' THEN
238 -- rstn_25 <= reset;
238 -- rstn_25 <= reset;
239 -- END IF;
239 -- END IF;
240 --END PROCESS;
240 --END PROCESS;
241
241
242 PROCESS (clk_50, reset)
242 PROCESS (clk_50, reset)
243 BEGIN -- PROCESS
243 BEGIN -- PROCESS
244 IF reset = '0' THEN -- asynchronous reset (active low)
244 IF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
245 clk_50_s <= '0';
246 rstn_50 <= '0';
247 rstn_50_d1 <= '0';
248 rstn_50_d2 <= '0';
249 rstn_50_d3 <= '0';
250
251 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
252 clk_50_s <= NOT clk_50_s;
245 clk_50_s <= NOT clk_50_s;
253 rstn_50_d1 <= '1';
254 rstn_50_d2 <= rstn_50_d1;
255 rstn_50_d3 <= rstn_50_d2;
256 rstn_50 <= rstn_50_d3;
257 END IF;
246 END IF;
258 END PROCESS;
247 END PROCESS;
259
248
260 PROCESS (clk_50_s, rstn_50)
249 PROCESS (clk_50_s, reset)
261 BEGIN -- PROCESS
250 BEGIN -- PROCESS
262 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
251 IF reset = '0' THEN -- asynchronous reset (active low)
263 clk_25 <= '0';
252 clk_25 <= '0';
264 rstn_25 <= '0';
253 rstn_25 <= '0';
265 rstn_25_d1 <= '0';
254 rstn_25_d1 <= '0';
266 rstn_25_d2 <= '0';
255 rstn_25_d2 <= '0';
267 rstn_25_d3 <= '0';
256 rstn_25_d3 <= '0';
268 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
257 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
269 clk_25 <= NOT clk_25;
258 clk_25 <= NOT clk_25;
270 rstn_25_d1 <= '1';
259 rstn_25_d1 <= '1';
271 rstn_25_d2 <= rstn_25_d1;
260 rstn_25_d2 <= rstn_25_d1;
272 rstn_25_d3 <= rstn_25_d2;
261 rstn_25_d3 <= rstn_25_d2;
273 rstn_25 <= rstn_25_d3;
262 rstn_25 <= rstn_25_d3;
274 END IF;
263 END IF;
275 END PROCESS;
264 END PROCESS;
276
265
277 PROCESS (clk_49, reset)
266 PROCESS (clk_49, reset)
278 BEGIN -- PROCESS
267 BEGIN -- PROCESS
279 IF reset = '0' THEN -- asynchronous reset (active low)
268 IF reset = '0' THEN -- asynchronous reset (active low)
280 clk_24 <= '0';
269 clk_24 <= '0';
281 rstn_24_d1 <= '0';
270 rstn_24_d1 <= '0';
282 rstn_24_d2 <= '0';
271 rstn_24_d2 <= '0';
283 rstn_24_d3 <= '0';
272 rstn_24_d3 <= '0';
284 rstn_24 <= '0';
273 rstn_24 <= '0';
285 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
274 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
286 clk_24 <= NOT clk_24;
275 clk_24 <= NOT clk_24;
287 rstn_24_d1 <= '1';
276 rstn_24_d1 <= '1';
288 rstn_24_d2 <= rstn_24_d1;
277 rstn_24_d2 <= rstn_24_d1;
289 rstn_24_d3 <= rstn_24_d2;
278 rstn_24_d3 <= rstn_24_d2;
290 rstn_24 <= rstn_24_d3;
279 rstn_24 <= rstn_24_d3;
291 END IF;
280 END IF;
292 END PROCESS;
281 END PROCESS;
293
282
294 -----------------------------------------------------------------------------
283 -----------------------------------------------------------------------------
295
284
296 PROCESS (clk_25, rstn_25)
285 PROCESS (clk_25, rstn_25)
297 BEGIN -- PROCESS
286 BEGIN -- PROCESS
298 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
287 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
299 LED0 <= '0';
288 LED0 <= '0';
300 LED1 <= '0';
289 LED1 <= '0';
301 LED2 <= '0';
290 LED2 <= '0';
302 --IO1 <= '0';
291 --IO1 <= '0';
303 --IO2 <= '1';
292 --IO2 <= '1';
304 --IO3 <= '0';
293 --IO3 <= '0';
305 --IO4 <= '0';
294 --IO4 <= '0';
306 --IO5 <= '0';
295 --IO5 <= '0';
307 --IO6 <= '0';
296 --IO6 <= '0';
308 --IO7 <= '0';
297 --IO7 <= '0';
309 --IO8 <= '0';
298 --IO8 <= '0';
310 --IO9 <= '0';
299 --IO9 <= '0';
311 --IO10 <= '0';
300 --IO10 <= '0';
312 --IO11 <= '0';
301 --IO11 <= '0';
313 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
302 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
314 LED0 <= '0';
303 LED0 <= '0';
315 LED1 <= '1';
304 LED1 <= '1';
316 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
305 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
317 --IO1 <= '1';
306 --IO1 <= '1';
318 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
307 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
319 --IO3 <= ADC_SDO(0);
308 --IO3 <= ADC_SDO(0);
320 --IO4 <= ADC_SDO(1);
309 --IO4 <= ADC_SDO(1);
321 --IO5 <= ADC_SDO(2);
310 --IO5 <= ADC_SDO(2);
322 --IO6 <= ADC_SDO(3);
311 --IO6 <= ADC_SDO(3);
323 --IO7 <= ADC_SDO(4);
312 --IO7 <= ADC_SDO(4);
324 --IO8 <= ADC_SDO(5);
313 --IO8 <= ADC_SDO(5);
325 --IO9 <= ADC_SDO(6);
314 --IO9 <= ADC_SDO(6);
326 --IO10 <= ADC_SDO(7);
315 --IO10 <= ADC_SDO(7);
327 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
316 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
328 END IF;
317 END IF;
329 END PROCESS;
318 END PROCESS;
330
319
331 PROCESS (clk_24, rstn_24)
320 PROCESS (clk_24, rstn_24)
332 BEGIN -- PROCESS
321 BEGIN -- PROCESS
333 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
322 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
334 I00_s <= '0';
323 I00_s <= '0';
335 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
324 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
336 I00_s <= NOT I00_s;
325 I00_s <= NOT I00_s;
337 END IF;
326 END IF;
338 END PROCESS;
327 END PROCESS;
339 -- IO0 <= I00_s;
328 -- IO0 <= I00_s;
340
329
341 --UARTs
330 --UARTs
342 nCTS1 <= '1';
331 nCTS1 <= '1';
343 nCTS2 <= '1';
332 nCTS2 <= '1';
344 nDCD2 <= '1';
333 nDCD2 <= '1';
345
334
346 --
335 --
347
336
348 leon3_soc_1 : leon3_soc
337 leon3_soc_1 : leon3_soc
349 GENERIC MAP (
338 GENERIC MAP (
350 fabtech => apa3e,
339 fabtech => apa3e,
351 memtech => apa3e,
340 memtech => apa3e,
352 padtech => inferred,
341 padtech => inferred,
353 clktech => inferred,
342 clktech => inferred,
354 disas => 0,
343 disas => 0,
355 dbguart => 0,
344 dbguart => 0,
356 pclow => 2,
345 pclow => 2,
357 clk_freq => 25000,
346 clk_freq => 25000,
358 IS_RADHARD => 0,
347 IS_RADHARD => 0,
359 NB_CPU => 1,
348 NB_CPU => 1,
360 ENABLE_FPU => 1,
349 ENABLE_FPU => 1,
361 FPU_NETLIST => 0,
350 FPU_NETLIST => 0,
362 ENABLE_DSU => 1,
351 ENABLE_DSU => 1,
363 ENABLE_AHB_UART => 1,
352 ENABLE_AHB_UART => 1,
364 ENABLE_APB_UART => 1,
353 ENABLE_APB_UART => 1,
365 ENABLE_IRQMP => 1,
354 ENABLE_IRQMP => 1,
366 ENABLE_GPT => 1,
355 ENABLE_GPT => 1,
367 NB_AHB_MASTER => NB_AHB_MASTER,
356 NB_AHB_MASTER => NB_AHB_MASTER,
368 NB_AHB_SLAVE => NB_AHB_SLAVE,
357 NB_AHB_SLAVE => NB_AHB_SLAVE,
369 NB_APB_SLAVE => NB_APB_SLAVE,
358 NB_APB_SLAVE => NB_APB_SLAVE,
370 ADDRESS_SIZE => 20,
359 ADDRESS_SIZE => 20,
371 USES_IAP_MEMCTRLR => 0)
360 USES_IAP_MEMCTRLR => 0)
372 PORT MAP (
361 PORT MAP (
373 clk => clk_25,
362 clk => clk_25,
374 reset => rstn_25,
363 reset => rstn_25,
375 errorn => errorn,
364 errorn => errorn,
376 ahbrxd => TXD1,
365 ahbrxd => TXD1,
377 ahbtxd => RXD1,
366 ahbtxd => RXD1,
378 urxd1 => TXD2,
367 urxd1 => TXD2,
379 utxd1 => RXD2,
368 utxd1 => RXD2,
380 address => SRAM_A,
369 address => SRAM_A,
381 data => SRAM_DQ,
370 data => SRAM_DQ,
382 nSRAM_BE0 => SRAM_nBE(0),
371 nSRAM_BE0 => SRAM_nBE(0),
383 nSRAM_BE1 => SRAM_nBE(1),
372 nSRAM_BE1 => SRAM_nBE(1),
384 nSRAM_BE2 => SRAM_nBE(2),
373 nSRAM_BE2 => SRAM_nBE(2),
385 nSRAM_BE3 => SRAM_nBE(3),
374 nSRAM_BE3 => SRAM_nBE(3),
386 nSRAM_WE => SRAM_nWE,
375 nSRAM_WE => SRAM_nWE,
387 nSRAM_CE => SRAM_CE_s,
376 nSRAM_CE => SRAM_CE_s,
388 nSRAM_OE => SRAM_nOE,
377 nSRAM_OE => SRAM_nOE,
389 nSRAM_READY => '0',
378 nSRAM_READY => '0',
390 SRAM_MBE => OPEN,
379 SRAM_MBE => OPEN,
391 apbi_ext => apbi_ext,
380 apbi_ext => apbi_ext,
392 apbo_ext => apbo_ext,
381 apbo_ext => apbo_ext,
393 ahbi_s_ext => ahbi_s_ext,
382 ahbi_s_ext => ahbi_s_ext,
394 ahbo_s_ext => ahbo_s_ext,
383 ahbo_s_ext => ahbo_s_ext,
395 ahbi_m_ext => ahbi_m_ext,
384 ahbi_m_ext => ahbi_m_ext,
396 ahbo_m_ext => ahbo_m_ext);
385 ahbo_m_ext => ahbo_m_ext);
397
386
398 SRAM_CE <= SRAM_CE_s(0);
387 SRAM_CE <= SRAM_CE_s(0);
399 -------------------------------------------------------------------------------
388 -------------------------------------------------------------------------------
400 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
389 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
401 -------------------------------------------------------------------------------
390 -------------------------------------------------------------------------------
402 apb_lfr_management_1 : apb_lfr_management
391 apb_lfr_management_1 : apb_lfr_management
403 GENERIC MAP (
392 GENERIC MAP (
404 tech => apa3e,
393 tech => apa3e,
405 pindex => 6,
394 pindex => 6,
406 paddr => 6,
395 paddr => 6,
407 pmask => 16#fff#,
396 pmask => 16#fff#,
408 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
397 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
409 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
398 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
410 PORT MAP (
399 PORT MAP (
411 clk25MHz => clk_25,
400 clk25MHz => clk_25,
412 resetn_25MHz => rstn_25, -- TODO
401 resetn_25MHz => rstn_25, -- TODO
413 clk24_576MHz => clk_24, -- 49.152MHz/2
402 clk24_576MHz => clk_24, -- 49.152MHz/2
414 resetn_24_576MHz => rstn_24, -- TODO
403 resetn_24_576MHz => rstn_24, -- TODO
415 grspw_tick => swno.tickout,
404 grspw_tick => swno.tickout,
416 apbi => apbi_ext,
405 apbi => apbi_ext,
417 apbo => apbo_ext(6),
406 apbo => apbo_ext(6),
418 HK_sample => sample_hk,
407 HK_sample => sample_hk,
419 HK_val => sample_val,
408 HK_val => sample_val,
420 HK_sel => HK_SEL,
409 HK_sel => HK_SEL,
421 DAC_SDO => OPEN,
410 DAC_SDO => OPEN,
422 DAC_SCK => OPEN,
411 DAC_SCK => OPEN,
423 DAC_SYNC => OPEN,
412 DAC_SYNC => OPEN,
424 DAC_CAL_EN => OPEN,
413 DAC_CAL_EN => OPEN,
425 coarse_time => coarse_time,
414 coarse_time => coarse_time,
426 fine_time => fine_time,
415 fine_time => fine_time,
427 LFR_soft_rstn => LFR_soft_rstn
416 LFR_soft_rstn => LFR_soft_rstn
428 );
417 );
429
418
430 -----------------------------------------------------------------------
419 -----------------------------------------------------------------------
431 --- SpaceWire --------------------------------------------------------
420 --- SpaceWire --------------------------------------------------------
432 -----------------------------------------------------------------------
421 -----------------------------------------------------------------------
433
422
434 SPW_EN <= '1';
423 SPW_EN <= '1';
435
424
436 spw_clk <= clk_50_s;
425 spw_clk <= clk_50_s;
437 spw_rxtxclk <= spw_clk;
426 spw_rxtxclk <= spw_clk;
438 spw_rxclkn <= NOT spw_rxtxclk;
427 spw_rxclkn <= NOT spw_rxtxclk;
439
428
440 -- PADS for SPW1
429 -- PADS for SPW1
441 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
430 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
442 PORT MAP (SPW_NOM_DIN, dtmp(0));
431 PORT MAP (SPW_NOM_DIN, dtmp(0));
443 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
432 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
444 PORT MAP (SPW_NOM_SIN, stmp(0));
433 PORT MAP (SPW_NOM_SIN, stmp(0));
445 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
434 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
446 PORT MAP (SPW_NOM_DOUT, swno.d(0));
435 PORT MAP (SPW_NOM_DOUT, swno.d(0));
447 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
436 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
448 PORT MAP (SPW_NOM_SOUT, swno.s(0));
437 PORT MAP (SPW_NOM_SOUT, swno.s(0));
449 -- PADS FOR SPW2
438 -- PADS FOR SPW2
450 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
439 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
451 PORT MAP (SPW_RED_SIN, dtmp(1));
440 PORT MAP (SPW_RED_SIN, dtmp(1));
452 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
441 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
453 PORT MAP (SPW_RED_DIN, stmp(1));
442 PORT MAP (SPW_RED_DIN, stmp(1));
454 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
443 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
455 PORT MAP (SPW_RED_DOUT, swno.d(1));
444 PORT MAP (SPW_RED_DOUT, swno.d(1));
456 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
445 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
457 PORT MAP (SPW_RED_SOUT, swno.s(1));
446 PORT MAP (SPW_RED_SOUT, swno.s(1));
458
447
459 -- GRSPW PHY
448 -- GRSPW PHY
460 --spw1_input: if CFG_SPW_GRSPW = 1 generate
449 --spw1_input: if CFG_SPW_GRSPW = 1 generate
461 spw_inputloop : FOR j IN 0 TO 1 GENERATE
450 spw_inputloop : FOR j IN 0 TO 1 GENERATE
462 spw_phy0 : grspw_phy
451 spw_phy0 : grspw_phy
463 GENERIC MAP(
452 GENERIC MAP(
464 tech => apa3e,
453 tech => apa3e,
465 rxclkbuftype => 1,
454 rxclkbuftype => 1,
466 scantest => 0)
455 scantest => 0)
467 PORT MAP(
456 PORT MAP(
468 rxrst => swno.rxrst,
457 rxrst => swno.rxrst,
469 di => dtmp(j),
458 di => dtmp(j),
470 si => stmp(j),
459 si => stmp(j),
471 rxclko => spw_rxclk(j),
460 rxclko => spw_rxclk(j),
472 do => swni.d(j),
461 do => swni.d(j),
473 ndo => swni.nd(j*5+4 DOWNTO j*5),
462 ndo => swni.nd(j*5+4 DOWNTO j*5),
474 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
463 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
475 END GENERATE spw_inputloop;
464 END GENERATE spw_inputloop;
476
465
477 swni.rmapnodeaddr <= (OTHERS => '0');
466 swni.rmapnodeaddr <= (OTHERS => '0');
478
467
479 -- SPW core
468 -- SPW core
480 sw0 : grspwm GENERIC MAP(
469 sw0 : grspwm GENERIC MAP(
481 tech => apa3e,
470 tech => apa3e,
482 hindex => 1,
471 hindex => 1,
483 pindex => 5,
472 pindex => 5,
484 paddr => 5,
473 paddr => 5,
485 pirq => 11,
474 pirq => 11,
486 sysfreq => 25000, -- CPU_FREQ
475 sysfreq => 25000, -- CPU_FREQ
487 rmap => 1,
476 rmap => 1,
488 rmapcrc => 1,
477 rmapcrc => 1,
489 fifosize1 => 16,
478 fifosize1 => 16,
490 fifosize2 => 16,
479 fifosize2 => 16,
491 rxclkbuftype => 1,
480 rxclkbuftype => 1,
492 rxunaligned => 0,
481 rxunaligned => 0,
493 rmapbufs => 4,
482 rmapbufs => 4,
494 ft => 0,
483 ft => 0,
495 netlist => 0,
484 netlist => 0,
496 ports => 2,
485 ports => 2,
497 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
486 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
498 memtech => apa3e,
487 memtech => apa3e,
499 destkey => 2,
488 destkey => 2,
500 spwcore => 1
489 spwcore => 1
501 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
490 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
502 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
491 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
503 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
492 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
504 )
493 )
505 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
494 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
506 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
495 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
507 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
496 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
508 swni, swno);
497 swni, swno);
509
498
510 swni.tickin <= '0';
499 swni.tickin <= '0';
511 swni.rmapen <= '1';
500 swni.rmapen <= '1';
512 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
501 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
513 swni.tickinraw <= '0';
502 swni.tickinraw <= '0';
514 swni.timein <= (OTHERS => '0');
503 swni.timein <= (OTHERS => '0');
515 swni.dcrstval <= (OTHERS => '0');
504 swni.dcrstval <= (OTHERS => '0');
516 swni.timerrstval <= (OTHERS => '0');
505 swni.timerrstval <= (OTHERS => '0');
517
506
518 -------------------------------------------------------------------------------
507 -------------------------------------------------------------------------------
519 -- LFR ------------------------------------------------------------------------
508 -- LFR ------------------------------------------------------------------------
520 -------------------------------------------------------------------------------
509 -------------------------------------------------------------------------------
521
510
522
511
523 LFR_rstn <= LFR_soft_rstn AND rstn_25;
512 LFR_rstn <= LFR_soft_rstn AND rstn_25;
524 --LFR_rstn <= rstn_25;
513 --LFR_rstn <= rstn_25;
525
514
526 lpp_lfr_1 : lpp_lfr
515 lpp_lfr_1 : lpp_lfr
527 GENERIC MAP (
516 GENERIC MAP (
528 Mem_use => use_RAM,
517 Mem_use => use_RAM,
529 nb_data_by_buffer_size => 32,
518 nb_data_by_buffer_size => 32,
530 nb_snapshot_param_size => 32,
519 nb_snapshot_param_size => 32,
531 delta_vector_size => 32,
520 delta_vector_size => 32,
532 delta_vector_size_f0_2 => 7, -- log2(96)
521 delta_vector_size_f0_2 => 7, -- log2(96)
533 pindex => 15,
522 pindex => 15,
534 paddr => 15,
523 paddr => 15,
535 pmask => 16#fff#,
524 pmask => 16#fff#,
536 pirq_ms => 6,
525 pirq_ms => 6,
537 pirq_wfp => 14,
526 pirq_wfp => 14,
538 hindex => 2,
527 hindex => 2,
539 top_lfr_version => X"000144") -- aa.bb.cc version
528 top_lfr_version => X"000144") -- aa.bb.cc version
540 PORT MAP (
529 PORT MAP (
541 clk => clk_25,
530 clk => clk_25,
542 rstn => LFR_rstn,
531 rstn => LFR_rstn,
543 sample_B => sample_s(2 DOWNTO 0),
532 sample_B => sample_s(2 DOWNTO 0),
544 sample_E => sample_s(7 DOWNTO 3),
533 sample_E => sample_s(7 DOWNTO 3),
545 sample_val => sample_val,
534 sample_val => sample_val,
546 apbi => apbi_ext,
535 apbi => apbi_ext,
547 apbo => apbo_ext(15),
536 apbo => apbo_ext(15),
548 ahbi => ahbi_m_ext,
537 ahbi => ahbi_m_ext,
549 ahbo => ahbo_m_ext(2),
538 ahbo => ahbo_m_ext(2),
550 coarse_time => coarse_time,
539 coarse_time => coarse_time,
551 fine_time => fine_time,
540 fine_time => fine_time,
552 data_shaping_BW => bias_fail_sw_sig,
541 data_shaping_BW => bias_fail_sw_sig,
553 debug_vector => lfr_debug_vector,
542 debug_vector => lfr_debug_vector,
554 debug_vector_ms => lfr_debug_vector_ms
543 debug_vector_ms => lfr_debug_vector_ms
555 );
544 );
556
545
557 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
546 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
558 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
547 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
559 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
548 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
560 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
549 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
561 IO0 <= rstn_25;
550 IO0 <= rstn_25;
562 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
551 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
563 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
552 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
564 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
553 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
565 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
554 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
566 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
555 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
567 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
556 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
568 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
557 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
569
558
570 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
559 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
571 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
560 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
572 END GENERATE all_sample;
561 END GENERATE all_sample;
573
562
574 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
563 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
575 GENERIC MAP(
564 GENERIC MAP(
576 ChannelCount => 8,
565 ChannelCount => 8,
577 SampleNbBits => 14,
566 SampleNbBits => 14,
578 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
567 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
579 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
568 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
580 PORT MAP (
569 PORT MAP (
581 -- CONV
570 -- CONV
582 cnv_clk => clk_24,
571 cnv_clk => clk_24,
583 cnv_rstn => rstn_24,
572 cnv_rstn => rstn_24,
584 cnv => ADC_nCS_sig,
573 cnv => ADC_nCS_sig,
585 -- DATA
574 -- DATA
586 clk => clk_25,
575 clk => clk_25,
587 rstn => rstn_25,
576 rstn => rstn_25,
588 sck => ADC_CLK_sig,
577 sck => ADC_CLK_sig,
589 sdo => ADC_SDO_sig,
578 sdo => ADC_SDO_sig,
590 -- SAMPLE
579 -- SAMPLE
591 sample => sample,
580 sample => sample,
592 sample_val => sample_val);
581 sample_val => sample_val);
593
582
594 --IO10 <= ADC_SDO_sig(5);
583 --IO10 <= ADC_SDO_sig(5);
595 --IO9 <= ADC_SDO_sig(4);
584 --IO9 <= ADC_SDO_sig(4);
596 --IO8 <= ADC_SDO_sig(3);
585 --IO8 <= ADC_SDO_sig(3);
597
586
598 ADC_nCS <= ADC_nCS_sig;
587 ADC_nCS <= ADC_nCS_sig;
599 ADC_CLK <= ADC_CLK_sig;
588 ADC_CLK <= ADC_CLK_sig;
600 ADC_SDO_sig <= ADC_SDO;
589 ADC_SDO_sig <= ADC_SDO;
601
590
602 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
591 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
603 "0010001000100010" WHEN HK_SEL = "01" ELSE
592 "0010001000100010" WHEN HK_SEL = "01" ELSE
604 "0100010001000100" WHEN HK_SEL = "10" ELSE
593 "0100010001000100" WHEN HK_SEL = "10" ELSE
605 (OTHERS => '0');
594 (OTHERS => '0');
606
595
607
596
608 ----------------------------------------------------------------------
597 ----------------------------------------------------------------------
609 --- GPIO -----------------------------------------------------------
598 --- GPIO -----------------------------------------------------------
610 ----------------------------------------------------------------------
599 ----------------------------------------------------------------------
611
600
612 grgpio0 : grgpio
601 grgpio0 : grgpio
613 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
602 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
614 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
603 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
615
604
616 gpioi.sig_en <= (OTHERS => '0');
605 gpioi.sig_en <= (OTHERS => '0');
617 gpioi.sig_in <= (OTHERS => '0');
606 gpioi.sig_in <= (OTHERS => '0');
618 gpioi.din <= (OTHERS => '0');
607 gpioi.din <= (OTHERS => '0');
619 --pio_pad_0 : iopad
608 --pio_pad_0 : iopad
620 -- GENERIC MAP (tech => CFG_PADTECH)
609 -- GENERIC MAP (tech => CFG_PADTECH)
621 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
610 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
622 --pio_pad_1 : iopad
611 --pio_pad_1 : iopad
623 -- GENERIC MAP (tech => CFG_PADTECH)
612 -- GENERIC MAP (tech => CFG_PADTECH)
624 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
613 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
625 --pio_pad_2 : iopad
614 --pio_pad_2 : iopad
626 -- GENERIC MAP (tech => CFG_PADTECH)
615 -- GENERIC MAP (tech => CFG_PADTECH)
627 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
616 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
628 --pio_pad_3 : iopad
617 --pio_pad_3 : iopad
629 -- GENERIC MAP (tech => CFG_PADTECH)
618 -- GENERIC MAP (tech => CFG_PADTECH)
630 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
619 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
631 --pio_pad_4 : iopad
620 --pio_pad_4 : iopad
632 -- GENERIC MAP (tech => CFG_PADTECH)
621 -- GENERIC MAP (tech => CFG_PADTECH)
633 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
622 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
634 --pio_pad_5 : iopad
623 --pio_pad_5 : iopad
635 -- GENERIC MAP (tech => CFG_PADTECH)
624 -- GENERIC MAP (tech => CFG_PADTECH)
636 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
625 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
637 --pio_pad_6 : iopad
626 --pio_pad_6 : iopad
638 -- GENERIC MAP (tech => CFG_PADTECH)
627 -- GENERIC MAP (tech => CFG_PADTECH)
639 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
628 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
640 --pio_pad_7 : iopad
629 --pio_pad_7 : iopad
641 -- GENERIC MAP (tech => CFG_PADTECH)
630 -- GENERIC MAP (tech => CFG_PADTECH)
642 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
631 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
643
632
644 PROCESS (clk_25, rstn_25)
633 PROCESS (clk_25, rstn_25)
645 BEGIN -- PROCESS
634 BEGIN -- PROCESS
646 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
635 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
647 -- --IO0 <= '0';
636 -- --IO0 <= '0';
648 -- IO1 <= '0';
637 -- IO1 <= '0';
649 -- IO2 <= '0';
638 -- IO2 <= '0';
650 -- IO3 <= '0';
639 -- IO3 <= '0';
651 -- IO4 <= '0';
640 -- IO4 <= '0';
652 -- IO5 <= '0';
641 -- IO5 <= '0';
653 -- IO6 <= '0';
642 -- IO6 <= '0';
654 -- IO7 <= '0';
643 -- IO7 <= '0';
655 IO8 <= '0';
644 IO8 <= '0';
656 IO9 <= '0';
645 IO9 <= '0';
657 IO10 <= '0';
646 IO10 <= '0';
658 IO11 <= '0';
647 IO11 <= '0';
659 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
648 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
660 CASE gpioo.dout(2 DOWNTO 0) IS
649 CASE gpioo.dout(2 DOWNTO 0) IS
661 WHEN "011" =>
650 WHEN "011" =>
662 -- --IO0 <= observation_reg(0 );
651 -- --IO0 <= observation_reg(0 );
663 -- IO1 <= observation_reg(1 );
652 -- IO1 <= observation_reg(1 );
664 -- IO2 <= observation_reg(2 );
653 -- IO2 <= observation_reg(2 );
665 -- IO3 <= observation_reg(3 );
654 -- IO3 <= observation_reg(3 );
666 -- IO4 <= observation_reg(4 );
655 -- IO4 <= observation_reg(4 );
667 -- IO5 <= observation_reg(5 );
656 -- IO5 <= observation_reg(5 );
668 -- IO6 <= observation_reg(6 );
657 -- IO6 <= observation_reg(6 );
669 -- IO7 <= observation_reg(7 );
658 -- IO7 <= observation_reg(7 );
670 IO8 <= observation_reg(8);
659 IO8 <= observation_reg(8);
671 IO9 <= observation_reg(9);
660 IO9 <= observation_reg(9);
672 IO10 <= observation_reg(10);
661 IO10 <= observation_reg(10);
673 IO11 <= observation_reg(11);
662 IO11 <= observation_reg(11);
674 WHEN "001" =>
663 WHEN "001" =>
675 -- --IO0 <= observation_reg(0 + 12);
664 -- --IO0 <= observation_reg(0 + 12);
676 -- IO1 <= observation_reg(1 + 12);
665 -- IO1 <= observation_reg(1 + 12);
677 -- IO2 <= observation_reg(2 + 12);
666 -- IO2 <= observation_reg(2 + 12);
678 -- IO3 <= observation_reg(3 + 12);
667 -- IO3 <= observation_reg(3 + 12);
679 -- IO4 <= observation_reg(4 + 12);
668 -- IO4 <= observation_reg(4 + 12);
680 -- IO5 <= observation_reg(5 + 12);
669 -- IO5 <= observation_reg(5 + 12);
681 -- IO6 <= observation_reg(6 + 12);
670 -- IO6 <= observation_reg(6 + 12);
682 -- IO7 <= observation_reg(7 + 12);
671 -- IO7 <= observation_reg(7 + 12);
683 IO8 <= observation_reg(8 + 12);
672 IO8 <= observation_reg(8 + 12);
684 IO9 <= observation_reg(9 + 12);
673 IO9 <= observation_reg(9 + 12);
685 IO10 <= observation_reg(10 + 12);
674 IO10 <= observation_reg(10 + 12);
686 IO11 <= observation_reg(11 + 12);
675 IO11 <= observation_reg(11 + 12);
687 WHEN "010" =>
676 WHEN "010" =>
688 -- --IO0 <= observation_reg(0 + 12 + 12);
677 -- --IO0 <= observation_reg(0 + 12 + 12);
689 -- IO1 <= observation_reg(1 + 12 + 12);
678 -- IO1 <= observation_reg(1 + 12 + 12);
690 -- IO2 <= observation_reg(2 + 12 + 12);
679 -- IO2 <= observation_reg(2 + 12 + 12);
691 -- IO3 <= observation_reg(3 + 12 + 12);
680 -- IO3 <= observation_reg(3 + 12 + 12);
692 -- IO4 <= observation_reg(4 + 12 + 12);
681 -- IO4 <= observation_reg(4 + 12 + 12);
693 -- IO5 <= observation_reg(5 + 12 + 12);
682 -- IO5 <= observation_reg(5 + 12 + 12);
694 -- IO6 <= observation_reg(6 + 12 + 12);
683 -- IO6 <= observation_reg(6 + 12 + 12);
695 -- IO7 <= observation_reg(7 + 12 + 12);
684 -- IO7 <= observation_reg(7 + 12 + 12);
696 IO8 <= '0';
685 IO8 <= '0';
697 IO9 <= '0';
686 IO9 <= '0';
698 IO10 <= '0';
687 IO10 <= '0';
699 IO11 <= '0';
688 IO11 <= '0';
700 WHEN "000" =>
689 WHEN "000" =>
701 -- --IO0 <= observation_vector_0(0 );
690 -- --IO0 <= observation_vector_0(0 );
702 -- IO1 <= observation_vector_0(1 );
691 -- IO1 <= observation_vector_0(1 );
703 -- IO2 <= observation_vector_0(2 );
692 -- IO2 <= observation_vector_0(2 );
704 -- IO3 <= observation_vector_0(3 );
693 -- IO3 <= observation_vector_0(3 );
705 -- IO4 <= observation_vector_0(4 );
694 -- IO4 <= observation_vector_0(4 );
706 -- IO5 <= observation_vector_0(5 );
695 -- IO5 <= observation_vector_0(5 );
707 -- IO6 <= observation_vector_0(6 );
696 -- IO6 <= observation_vector_0(6 );
708 -- IO7 <= observation_vector_0(7 );
697 -- IO7 <= observation_vector_0(7 );
709 IO8 <= observation_vector_0(8);
698 IO8 <= observation_vector_0(8);
710 IO9 <= observation_vector_0(9);
699 IO9 <= observation_vector_0(9);
711 IO10 <= observation_vector_0(10);
700 IO10 <= observation_vector_0(10);
712 IO11 <= observation_vector_0(11);
701 IO11 <= observation_vector_0(11);
713 WHEN "100" =>
702 WHEN "100" =>
714 -- --IO0 <= observation_vector_1(0 );
703 -- --IO0 <= observation_vector_1(0 );
715 -- IO1 <= observation_vector_1(1 );
704 -- IO1 <= observation_vector_1(1 );
716 -- IO2 <= observation_vector_1(2 );
705 -- IO2 <= observation_vector_1(2 );
717 -- IO3 <= observation_vector_1(3 );
706 -- IO3 <= observation_vector_1(3 );
718 -- IO4 <= observation_vector_1(4 );
707 -- IO4 <= observation_vector_1(4 );
719 -- IO5 <= observation_vector_1(5 );
708 -- IO5 <= observation_vector_1(5 );
720 -- IO6 <= observation_vector_1(6 );
709 -- IO6 <= observation_vector_1(6 );
721 -- IO7 <= observation_vector_1(7 );
710 -- IO7 <= observation_vector_1(7 );
722 IO8 <= observation_vector_1(8);
711 IO8 <= observation_vector_1(8);
723 IO9 <= observation_vector_1(9);
712 IO9 <= observation_vector_1(9);
724 IO10 <= observation_vector_1(10);
713 IO10 <= observation_vector_1(10);
725 IO11 <= observation_vector_1(11);
714 IO11 <= observation_vector_1(11);
726 WHEN OTHERS => NULL;
715 WHEN OTHERS => NULL;
727 END CASE;
716 END CASE;
728
717
729 END IF;
718 END IF;
730 END PROCESS;
719 END PROCESS;
731 -----------------------------------------------------------------------------
720 -----------------------------------------------------------------------------
732 --
721 --
733 -----------------------------------------------------------------------------
722 -----------------------------------------------------------------------------
734 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
723 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
735 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
724 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
736 apbo_ext(I) <= apb_none;
725 apbo_ext(I) <= apb_none;
737 END GENERATE apbo_ext_not_used;
726 END GENERATE apbo_ext_not_used;
738 END GENERATE all_apbo_ext;
727 END GENERATE all_apbo_ext;
739
728
740
729
741 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
730 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
742 ahbo_s_ext(I) <= ahbs_none;
731 ahbo_s_ext(I) <= ahbs_none;
743 END GENERATE all_ahbo_ext;
732 END GENERATE all_ahbo_ext;
744
733
745 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
734 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
746 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
735 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
747 ahbo_m_ext(I) <= ahbm_none;
736 ahbo_m_ext(I) <= ahbm_none;
748 END GENERATE ahbo_m_ext_not_used;
737 END GENERATE ahbo_m_ext_not_used;
749 END GENERATE all_ahbo_m_ext;
738 END GENERATE all_ahbo_m_ext;
750
739
751 END beh;
740 END beh;
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