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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
24 USE IEEE.numeric_std.ALL;
25
25
26 LIBRARY lpp;
26 LIBRARY lpp;
27 USE lpp.lpp_waveform_pkg.ALL;
27 USE lpp.lpp_waveform_pkg.ALL;
28 USE lpp.general_purpose.ALL;
28 USE lpp.general_purpose.ALL;
29
29
30 ENTITY lpp_waveform_fifo_arbiter IS
30 ENTITY lpp_waveform_fifo_arbiter IS
31 GENERIC(
31 GENERIC(
32 tech : INTEGER := 0;
32 tech : INTEGER := 0;
33 nb_data_by_buffer_size : INTEGER
33 nb_data_by_buffer_size : INTEGER
34 );
34 );
35 PORT(
35 PORT(
36 clk : IN STD_LOGIC;
36 clk : IN STD_LOGIC;
37 rstn : IN STD_LOGIC;
37 rstn : IN STD_LOGIC;
38 ---------------------------------------------------------------------------
38 ---------------------------------------------------------------------------
39 run : IN STD_LOGIC;
39 run : IN STD_LOGIC;
40 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
40 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
41 ---------------------------------------------------------------------------
41 ---------------------------------------------------------------------------
42 -- SNAPSHOT INTERFACE (INPUT)
42 -- SNAPSHOT INTERFACE (INPUT)
43 ---------------------------------------------------------------------------
43 ---------------------------------------------------------------------------
44 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
44 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
45 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
45 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
46 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
46 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
47 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
47 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
48
48
49 ---------------------------------------------------------------------------
49 ---------------------------------------------------------------------------
50 -- FIFO INTERFACE (OUTPUT)
50 -- FIFO INTERFACE (OUTPUT)
51 ---------------------------------------------------------------------------
51 ---------------------------------------------------------------------------
52 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
52 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
53 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
53 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
54 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
54 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
55
55
56 );
56 );
57 END ENTITY;
57 END ENTITY;
58
58
59
59
60 ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS
60 ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS
61
61
62 -----------------------------------------------------------------------------
62 -----------------------------------------------------------------------------
63 -- DATA FLOW
63 -- DATA FLOW
64 -----------------------------------------------------------------------------
64 -----------------------------------------------------------------------------
65 TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
65 TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
66 SIGNAL time_temp_0 : WORD_VECTOR(3 DOWNTO 0);
66 SIGNAL time_temp_0 : WORD_VECTOR(3 DOWNTO 0);
67 SIGNAL time_temp_1 : WORD_VECTOR(3 DOWNTO 0);
67 SIGNAL time_temp_1 : WORD_VECTOR(3 DOWNTO 0);
68 SIGNAL data_temp_0 : WORD_VECTOR(3 DOWNTO 0);
68 SIGNAL data_temp_0 : WORD_VECTOR(3 DOWNTO 0);
69 SIGNAL data_temp_1 : WORD_VECTOR(3 DOWNTO 0);
69 SIGNAL data_temp_1 : WORD_VECTOR(3 DOWNTO 0);
70 SIGNAL data_temp_2 : WORD_VECTOR(3 DOWNTO 0);
70 SIGNAL data_temp_2 : WORD_VECTOR(3 DOWNTO 0);
71 SIGNAL data_temp_v : WORD_VECTOR(3 DOWNTO 0);
71 SIGNAL data_temp_v : WORD_VECTOR(3 DOWNTO 0);
72 SIGNAL sel_input : STD_LOGIC_VECTOR(3 DOWNTO 0);
72 SIGNAL sel_input : STD_LOGIC_VECTOR(3 DOWNTO 0);
73 -----------------------------------------------------------------------------
73 -----------------------------------------------------------------------------
74 -- CHANNEL SELECTION (RoundRobin)
74 -- CHANNEL SELECTION (RoundRobin)
75 -----------------------------------------------------------------------------
75 -----------------------------------------------------------------------------
76 SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0);
76 SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0);
77 SIGNAL valid_out_rr : STD_LOGIC_VECTOR(3 DOWNTO 0);
77 SIGNAL valid_out_rr : STD_LOGIC_VECTOR(3 DOWNTO 0);
78 -----------------------------------------------------------------------------
78 -----------------------------------------------------------------------------
79 -- FSM CONTROL
79 -- FSM CONTROL
80 -----------------------------------------------------------------------------
80 -----------------------------------------------------------------------------
81 TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
81 TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
82 SIGNAL reg_shift_data : Counter_Vector(3 DOWNTO 0);
82 SIGNAL reg_shift_data : Counter_Vector(3 DOWNTO 0);
83 SIGNAL reg_shift_time : Counter_Vector(3 DOWNTO 0);
83 SIGNAL reg_shift_time : Counter_Vector(3 DOWNTO 0);
84 SIGNAL reg_count_data : Counter_Vector(3 DOWNTO 0);
84 SIGNAL reg_count_data : Counter_Vector(3 DOWNTO 0);
85 -- SHIFT_DATA ---------------------------------------------------------------
85 -- SHIFT_DATA ---------------------------------------------------------------
86 SIGNAL shift_data_pre : INTEGER;
86 SIGNAL shift_data_pre : INTEGER;
87 SIGNAL shift_data : INTEGER;
87 SIGNAL shift_data : INTEGER;
88 SIGNAL reg_shift_data_s : Counter_Vector(3 DOWNTO 0);
88 SIGNAL reg_shift_data_s : Counter_Vector(3 DOWNTO 0);
89 -- SHIFT_TIME ---------------------------------------------------------------
89 -- SHIFT_TIME ---------------------------------------------------------------
90 SIGNAL reg_shift_time_pre : INTEGER;
90 SIGNAL shift_time_pre : INTEGER;
91 SIGNAL shift_time_pre : INTEGER;
91 SIGNAL shift_time : INTEGER;
92 SIGNAL shift_time : INTEGER;
92 SIGNAL reg_shift_time_s : Counter_Vector(3 DOWNTO 0);
93 SIGNAL reg_shift_time_s : Counter_Vector(3 DOWNTO 0);
93 -- COUNT_DATA ---------------------------------------------------------------
94 -- COUNT_DATA ---------------------------------------------------------------
94 SIGNAL count_data_pre : INTEGER;
95 SIGNAL count_data_pre : INTEGER;
95 SIGNAL count_data : INTEGER;
96 SIGNAL count_data : INTEGER;
96 SIGNAL reg_count_data_s : Counter_Vector(3 DOWNTO 0);
97 SIGNAL reg_count_data_s : Counter_Vector(3 DOWNTO 0);
97
98
98 BEGIN
99 BEGIN
99
100
100 -----------------------------------------------------------------------------
101 -----------------------------------------------------------------------------
101 -- DATA FLOW
102 -- DATA FLOW
102 -----------------------------------------------------------------------------
103 -----------------------------------------------------------------------------
103
104
104
105
105 all_input : FOR I IN 3 DOWNTO 0 GENERATE
106 all_input : FOR I IN 3 DOWNTO 0 GENERATE
106
107
107 all_bit_of_time: FOR J IN 31 DOWNTO 0 GENERATE
108 all_bit_of_time: FOR J IN 31 DOWNTO 0 GENERATE
108 time_temp_0(I)(J) <= time_in(I,J);
109 time_temp_0(I)(J) <= time_in(I,J);
109 J_47DOWNTO32: IF J+32 < 48 GENERATE
110 J_47DOWNTO32: IF J+32 < 48 GENERATE
110 time_temp_1(I)(J) <= time_in(I,32+J);
111 time_temp_1(I)(J) <= time_in(I,32+J);
111 END GENERATE J_47DOWNTO32;
112 END GENERATE J_47DOWNTO32;
112 J_63DOWNTO48: IF J+32 > 47 GENERATE
113 J_63DOWNTO48: IF J+32 > 47 GENERATE
113 time_temp_1(I)(J) <= '0';
114 time_temp_1(I)(J) <= '0';
114 END GENERATE J_63DOWNTO48;
115 END GENERATE J_63DOWNTO48;
115 data_temp_0(I)(J) <= data_in(I,J);
116 data_temp_0(I)(J) <= data_in(I,J);
116 data_temp_1(I)(J) <= data_in(I,J+32);
117 data_temp_1(I)(J) <= data_in(I,J+32);
117 data_temp_2(I)(J) <= data_in(I,J+32*2);
118 data_temp_2(I)(J) <= data_in(I,J+32*2);
118 END GENERATE all_bit_of_time;
119 END GENERATE all_bit_of_time;
119
120
120 data_temp_v(I) <= time_temp_0(I) WHEN shift_time = 0 ELSE
121 data_temp_v(I) <= time_temp_0(I) WHEN reg_shift_time_pre = 0 ELSE
121 time_temp_1(I) WHEN shift_time = 1 ELSE
122 time_temp_1(I) WHEN reg_shift_time_pre = 1 ELSE
122 data_temp_0(I) WHEN shift_data = 0 ELSE
123 data_temp_0(I) WHEN shift_data = 0 ELSE
123 data_temp_1(I) WHEN shift_data = 1 ELSE
124 data_temp_1(I) WHEN shift_data = 1 ELSE
124 data_temp_2(I);
125 data_temp_2(I);
125 END GENERATE all_input;
126 END GENERATE all_input;
126
127
127 data_out <= data_temp_v(0) WHEN sel_input = "0001" ELSE
128 data_out <= data_temp_v(0) WHEN sel_input = "0001" ELSE
128 data_temp_v(1) WHEN sel_input = "0010" ELSE
129 data_temp_v(1) WHEN sel_input = "0010" ELSE
129 data_temp_v(2) WHEN sel_input = "0100" ELSE
130 data_temp_v(2) WHEN sel_input = "0100" ELSE
130 data_temp_v(3);
131 data_temp_v(3);
131
132
132 -----------------------------------------------------------------------------
133 -----------------------------------------------------------------------------
133 -- CHANNEL SELECTION (RoundRobin)
134 -- CHANNEL SELECTION (RoundRobin)
134 -----------------------------------------------------------------------------
135 -----------------------------------------------------------------------------
135 all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE
136 all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE
136 -- valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I);
137 -- valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I);
137 valid_in_rr(I) <= data_in_valid(I) AND NOT full(I);
138 valid_in_rr(I) <= data_in_valid(I) AND NOT full(I);
138 END GENERATE all_input_rr;
139 END GENERATE all_input_rr;
139
140
140 RR_Arbiter_4_1 : RR_Arbiter_4
141 RR_Arbiter_4_1 : RR_Arbiter_4
141 PORT MAP (
142 PORT MAP (
142 clk => clk,
143 clk => clk,
143 rstn => rstn,
144 rstn => rstn,
144 in_valid => valid_in_rr,
145 in_valid => valid_in_rr,
145 out_grant => valid_out_rr);
146 out_grant => valid_out_rr);
146
147
147 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
148 -- FSM CONTROL
149 -- FSM CONTROL
149 -----------------------------------------------------------------------------
150 -----------------------------------------------------------------------------
150
151
151 PROCESS (clk, rstn)
152 PROCESS (clk, rstn)
152 BEGIN -- PROCESS
153 BEGIN -- PROCESS
153 IF rstn = '0' THEN -- asynchronous reset (active low)
154 IF rstn = '0' THEN -- asynchronous reset (active low)
154 reg_shift_data <= (0, 0, 0, 0);
155 reg_shift_data <= (0, 0, 0, 0);
155 reg_shift_time <= (0, 0, 0, 0);
156 reg_shift_time <= (0, 0, 0, 0);
156 reg_count_data <= (0, 0, 0, 0);
157 reg_count_data <= (0, 0, 0, 0);
157 sel_input <= (OTHERS => '0');
158 sel_input <= (OTHERS => '0');
158 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
159 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
159 IF run = '0' THEN
160 IF run = '0' THEN
160 reg_shift_data <= (0, 0, 0, 0);
161 reg_shift_data <= (0, 0, 0, 0);
161 reg_shift_time <= (0, 0, 0, 0);
162 reg_shift_time <= (0, 0, 0, 0);
162 reg_count_data <= (0, 0, 0, 0);
163 reg_count_data <= (0, 0, 0, 0);
163 sel_input <= (OTHERS => '0');
164 sel_input <= (OTHERS => '0');
164 ELSE
165 ELSE
165 sel_input <= valid_out_rr;
166 sel_input <= valid_out_rr;
166
167
167 IF count_data_pre = 0 THEN -- first buffer data
168 IF count_data_pre = 0 THEN -- first buffer data
168 IF shift_time_pre < 2 THEN -- TIME not completly send
169 IF shift_time_pre < 2 THEN -- TIME not completly send
169 reg_shift_time <= reg_shift_time_s;
170 reg_shift_time <= reg_shift_time_s;
170 ELSE
171 ELSE
171 reg_shift_data <= reg_shift_data_s;
172 reg_shift_data <= reg_shift_data_s;
172 IF shift_data_pre = 2 THEN
173 IF shift_data_pre = 2 THEN
173 reg_count_data <= reg_count_data_s;
174 reg_count_data <= reg_count_data_s;
174 END IF;
175 END IF;
175 END IF;
176 END IF;
176 ELSE
177 ELSE
177 reg_shift_data <= reg_shift_data_s;
178 reg_shift_data <= reg_shift_data_s;
178 IF shift_data_pre = 2 THEN
179 IF shift_data_pre = 2 THEN
179 reg_count_data <= reg_count_data_s;
180 reg_count_data <= reg_count_data_s;
180 IF count_data = 0 THEN
181 IF count_data = 0 THEN
181 reg_shift_time <= reg_shift_time_s;
182 reg_shift_time <= reg_shift_time_s;
182 END IF;
183 END IF;
183 END IF;
184 END IF;
184 END IF;
185 END IF;
185 END IF;
186 END IF;
186 END IF;
187 END IF;
187 END PROCESS;
188 END PROCESS;
188
189
189 -----------------------------------------------------------------------------
190 -----------------------------------------------------------------------------
190 data_out_wen <= NOT sel_input;
191 data_out_wen <= NOT sel_input;
191 data_in_ack <= sel_input;
192 data_in_ack <= sel_input;
192
193
193 -- SHIFT_DATA ---------------------------------------------------------------
194 -- SHIFT_DATA ---------------------------------------------------------------
194 shift_data_pre <= reg_shift_data(0) WHEN valid_out_rr(0) = '1' ELSE
195 shift_data_pre <= reg_shift_data(0) WHEN valid_out_rr(0) = '1' ELSE
195 reg_shift_data(1) WHEN valid_out_rr(1) = '1' ELSE
196 reg_shift_data(1) WHEN valid_out_rr(1) = '1' ELSE
196 reg_shift_data(2) WHEN valid_out_rr(2) = '1' ELSE
197 reg_shift_data(2) WHEN valid_out_rr(2) = '1' ELSE
197 reg_shift_data(3);
198 reg_shift_data(3);
198
199
199 shift_data <= shift_data_pre + 1 WHEN shift_data_pre < 2 ELSE 0;
200 shift_data <= shift_data_pre + 1 WHEN shift_data_pre < 2 ELSE 0;
200
201
201 reg_shift_data_s(0) <= shift_data WHEN valid_out_rr(0) = '1' ELSE reg_shift_data_s(0);
202 reg_shift_data_s(0) <= shift_data WHEN valid_out_rr(0) = '1' ELSE reg_shift_data(0);--_s
202 reg_shift_data_s(1) <= shift_data WHEN valid_out_rr(1) = '1' ELSE reg_shift_data_s(1);
203 reg_shift_data_s(1) <= shift_data WHEN valid_out_rr(1) = '1' ELSE reg_shift_data(1);--_s
203 reg_shift_data_s(2) <= shift_data WHEN valid_out_rr(2) = '1' ELSE reg_shift_data_s(2);
204 reg_shift_data_s(2) <= shift_data WHEN valid_out_rr(2) = '1' ELSE reg_shift_data(2);--_s
204 reg_shift_data_s(3) <= shift_data WHEN valid_out_rr(3) = '1' ELSE reg_shift_data_s(3);
205 reg_shift_data_s(3) <= shift_data WHEN valid_out_rr(3) = '1' ELSE reg_shift_data(3);--_s
205
206
206 -- SHIFT_TIME ---------------------------------------------------------------
207 -- SHIFT_TIME ---------------------------------------------------------------
207 shift_time_pre <= reg_shift_time(0) WHEN valid_out_rr(0) = '1' ELSE
208 shift_time_pre <= reg_shift_time(0) WHEN valid_out_rr(0) = '1' ELSE
208 reg_shift_time(1) WHEN valid_out_rr(1) = '1' ELSE
209 reg_shift_time(1) WHEN valid_out_rr(1) = '1' ELSE
209 reg_shift_time(2) WHEN valid_out_rr(2) = '1' ELSE
210 reg_shift_time(2) WHEN valid_out_rr(2) = '1' ELSE
210 reg_shift_time(3);
211 reg_shift_time(3);
211
212
212 shift_time <= shift_time_pre + 1 WHEN shift_time_pre < 2 ELSE 0;
213 shift_time <= shift_time_pre + 1 WHEN shift_time_pre < 2 ELSE 0;
213
214
214 reg_shift_time_s(0) <= shift_time WHEN valid_out_rr(0) = '1' ELSE reg_shift_time_s(0);
215 reg_shift_time_s(0) <= shift_time WHEN valid_out_rr(0) = '1' ELSE reg_shift_time(0);--_s
215 reg_shift_time_s(1) <= shift_time WHEN valid_out_rr(1) = '1' ELSE reg_shift_time_s(1);
216 reg_shift_time_s(1) <= shift_time WHEN valid_out_rr(1) = '1' ELSE reg_shift_time(1);--_s
216 reg_shift_time_s(2) <= shift_time WHEN valid_out_rr(2) = '1' ELSE reg_shift_time_s(2);
217 reg_shift_time_s(2) <= shift_time WHEN valid_out_rr(2) = '1' ELSE reg_shift_time(2);--_s
217 reg_shift_time_s(3) <= shift_time WHEN valid_out_rr(3) = '1' ELSE reg_shift_time_s(3);
218 reg_shift_time_s(3) <= shift_time WHEN valid_out_rr(3) = '1' ELSE reg_shift_time(3);--_s
218
219
219 -- COUNT_DATA ---------------------------------------------------------------
220 -- COUNT_DATA ---------------------------------------------------------------
220 count_data_pre <= reg_count_data(0) WHEN valid_out_rr(0) = '1' ELSE
221 count_data_pre <= reg_count_data(0) WHEN valid_out_rr(0) = '1' ELSE
221 reg_count_data(1) WHEN valid_out_rr(1) = '1' ELSE
222 reg_count_data(1) WHEN valid_out_rr(1) = '1' ELSE
222 reg_count_data(2) WHEN valid_out_rr(2) = '1' ELSE
223 reg_count_data(2) WHEN valid_out_rr(2) = '1' ELSE
223 reg_count_data(3);
224 reg_count_data(3);
224
225
225 count_data <= count_data_pre + 1 WHEN count_data_pre < UNSIGNED(nb_data_by_buffer) ELSE 0;
226 count_data <= count_data_pre + 1 WHEN count_data_pre < UNSIGNED(nb_data_by_buffer) ELSE 0;
226
227
227 reg_count_data_s(0) <= count_data WHEN valid_out_rr(0) = '1' ELSE reg_count_data_s(0);
228 reg_count_data_s(0) <= count_data WHEN valid_out_rr(0) = '1' ELSE reg_count_data(0);--_s
228 reg_count_data_s(1) <= count_data WHEN valid_out_rr(1) = '1' ELSE reg_count_data_s(1);
229 reg_count_data_s(1) <= count_data WHEN valid_out_rr(1) = '1' ELSE reg_count_data(1);--_s
229 reg_count_data_s(2) <= count_data WHEN valid_out_rr(2) = '1' ELSE reg_count_data_s(2);
230 reg_count_data_s(2) <= count_data WHEN valid_out_rr(2) = '1' ELSE reg_count_data(2);--_s
230 reg_count_data_s(3) <= count_data WHEN valid_out_rr(3) = '1' ELSE reg_count_data_s(3);
231 reg_count_data_s(3) <= count_data WHEN valid_out_rr(3) = '1' ELSE reg_count_data(3);--_s
231 -----------------------------------------------------------------------------
232 -----------------------------------------------------------------------------
232
233
234 PROCESS (clk, rstn)
235 BEGIN -- PROCESS
236 IF rstn = '0' THEN -- asynchronous reset (active low)
237 reg_shift_time_pre <= 0;
238 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
239 reg_shift_time_pre <= shift_time_pre;
240 END IF;
241 END PROCESS ;
242
233 END ARCHITECTURE;
243 END ARCHITECTURE;
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