HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r231:fae59f69d00e

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SIGNAL shift_data : INTEGER;

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SIGNAL shift_data : INTEGER;

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SIGNAL reg_shift_data_s : Counter_Vector(3 DOWNTO 0);

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SIGNAL reg_shift_data_s : Counter_Vector(3 DOWNTO 0);

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-- SHIFT_TIME ---------------------------------------------------------------

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-- SHIFT_TIME ---------------------------------------------------------------

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SIGNAL reg_shift_time_pre : INTEGER;

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SIGNAL shift_time_pre : INTEGER;

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SIGNAL shift_time_pre : INTEGER;

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SIGNAL shift_time : INTEGER;

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SIGNAL shift_time : INTEGER;

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SIGNAL reg_shift_time_s : Counter_Vector(3 DOWNTO 0);

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SIGNAL reg_shift_time_s : Counter_Vector(3 DOWNTO 0);

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data_temp_2(I)(J) <= data_in(I,J+32*2);

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data_temp_2(I)(J) <= data_in(I,J+32*2);

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END GENERATE all_bit_of_time;

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END GENERATE all_bit_of_time;

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data_temp_v(I) <= time_temp_0(I) WHEN shift_time = 0 ELSE

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data_temp_v(I) <= time_temp_0(I) WHEN reg_shift_time_pre = 0 ELSE

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time_temp_1(I) WHEN shift_time = 1 ELSE

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time_temp_1(I) WHEN reg_shift_time_pre = 1 ELSE

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data_temp_0(I) WHEN shift_data = 0 ELSE

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data_temp_0(I) WHEN shift_data = 0 ELSE

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data_temp_1(I) WHEN shift_data = 1 ELSE

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data_temp_1(I) WHEN shift_data = 1 ELSE

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data_temp_2(I);

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data_temp_2(I);

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END GENERATE all_input;

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END GENERATE all_input;

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shift_data <= shift_data_pre + 1 WHEN shift_data_pre < 2 ELSE 0;

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shift_data <= shift_data_pre + 1 WHEN shift_data_pre < 2 ELSE 0;

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reg_shift_data_s(0) <= shift_data WHEN valid_out_rr(0) = '1' ELSE reg_shift_data_s(0);

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reg_shift_data_s(0) <= shift_data WHEN valid_out_rr(0) = '1' ELSE reg_shift_data(0);--_s

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reg_shift_data_s(1) <= shift_data WHEN valid_out_rr(1) = '1' ELSE reg_shift_data_s(1);

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reg_shift_data_s(1) <= shift_data WHEN valid_out_rr(1) = '1' ELSE reg_shift_data(1);--_s

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reg_shift_data_s(2) <= shift_data WHEN valid_out_rr(2) = '1' ELSE reg_shift_data_s(2);

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reg_shift_data_s(2) <= shift_data WHEN valid_out_rr(2) = '1' ELSE reg_shift_data(2);--_s

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reg_shift_data_s(3) <= shift_data WHEN valid_out_rr(3) = '1' ELSE reg_shift_data_s(3);

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reg_shift_data_s(3) <= shift_data WHEN valid_out_rr(3) = '1' ELSE reg_shift_data(3);--_s

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-- SHIFT_TIME ---------------------------------------------------------------

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-- SHIFT_TIME ---------------------------------------------------------------

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shift_time_pre <= reg_shift_time(0) WHEN valid_out_rr(0) = '1' ELSE

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shift_time_pre <= reg_shift_time(0) WHEN valid_out_rr(0) = '1' ELSE

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shift_time <= shift_time_pre + 1 WHEN shift_time_pre < 2 ELSE 0;

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shift_time <= shift_time_pre + 1 WHEN shift_time_pre < 2 ELSE 0;

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reg_shift_time_s(0) <= shift_time WHEN valid_out_rr(0) = '1' ELSE reg_shift_time_s(0);

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reg_shift_time_s(0) <= shift_time WHEN valid_out_rr(0) = '1' ELSE reg_shift_time(0);--_s

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reg_shift_time_s(1) <= shift_time WHEN valid_out_rr(1) = '1' ELSE reg_shift_time_s(1);

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reg_shift_time_s(1) <= shift_time WHEN valid_out_rr(1) = '1' ELSE reg_shift_time(1);--_s

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reg_shift_time_s(2) <= shift_time WHEN valid_out_rr(2) = '1' ELSE reg_shift_time_s(2);

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reg_shift_time_s(2) <= shift_time WHEN valid_out_rr(2) = '1' ELSE reg_shift_time(2);--_s

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reg_shift_time_s(3) <= shift_time WHEN valid_out_rr(3) = '1' ELSE reg_shift_time_s(3);

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reg_shift_time_s(3) <= shift_time WHEN valid_out_rr(3) = '1' ELSE reg_shift_time(3);--_s

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-- COUNT_DATA ---------------------------------------------------------------

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-- COUNT_DATA ---------------------------------------------------------------

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count_data_pre <= reg_count_data(0) WHEN valid_out_rr(0) = '1' ELSE

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count_data_pre <= reg_count_data(0) WHEN valid_out_rr(0) = '1' ELSE

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count_data <= count_data_pre + 1 WHEN count_data_pre < UNSIGNED(nb_data_by_buffer) ELSE 0;

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count_data <= count_data_pre + 1 WHEN count_data_pre < UNSIGNED(nb_data_by_buffer) ELSE 0;

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reg_count_data_s(0) <= count_data WHEN valid_out_rr(0) = '1' ELSE reg_count_data_s(0);

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reg_count_data_s(0) <= count_data WHEN valid_out_rr(0) = '1' ELSE reg_count_data(0);--_s

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reg_count_data_s(1) <= count_data WHEN valid_out_rr(1) = '1' ELSE reg_count_data_s(1);

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reg_count_data_s(1) <= count_data WHEN valid_out_rr(1) = '1' ELSE reg_count_data(1);--_s

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reg_count_data_s(2) <= count_data WHEN valid_out_rr(2) = '1' ELSE reg_count_data_s(2);

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reg_count_data_s(2) <= count_data WHEN valid_out_rr(2) = '1' ELSE reg_count_data(2);--_s

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reg_count_data_s(3) <= count_data WHEN valid_out_rr(3) = '1' ELSE reg_count_data_s(3);

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reg_count_data_s(3) <= count_data WHEN valid_out_rr(3) = '1' ELSE reg_count_data(3);--_s

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-----------------------------------------------------------------------------

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-----------------------------------------------------------------------------

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PROCESS (clk, rstn)

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BEGIN -- PROCESS

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IF rstn = '0' THEN -- asynchronous reset (active low)

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reg_shift_time_pre <= 0;

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ELSIF clk'event AND clk = '1' THEN -- rising clock edge

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reg_shift_time_pre <= shift_time_pre;

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END IF;

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END PROCESS ;

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END ARCHITECTURE;

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END ARCHITECTURE;

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               SIGNAL shift_data       : INTEGER;
               SIGNAL reg_shift_data_s : Counter_Vector(3 DOWNTO 0);
               -- SHIFT_TIME ---------------------------------------------------------------
+              SIGNAL reg_shift_time_pre   : INTEGER;
               SIGNAL shift_time_pre   : INTEGER;
               SIGNAL shift_time       : INTEGER;
               SIGNAL reg_shift_time_s : Counter_Vector(3 DOWNTO 0);
                   data_temp_2(I)(J) <= data_in(I,J+32*2);
                 END GENERATE all_bit_of_time;
-                data_temp_v(I) <= time_temp_0(I)                     WHEN shift_time = 0 ELSE
+                data_temp_v(I) <= time_temp_0(I)   WHEN reg_shift_time_pre = 0 ELSE
-                                  time_temp_1(I)                     WHEN shift_time = 1 ELSE
+                                  time_temp_1(I)   WHEN reg_shift_time_pre = 1 ELSE
-                                  data_temp_0(I)            WHEN shift_data = 0 ELSE
+                                  data_temp_0(I)   WHEN shift_data = 0 ELSE
-                                  data_temp_1(I)           WHEN shift_data = 1 ELSE
+                                  data_temp_1(I)   WHEN shift_data = 1 ELSE
                                   data_temp_2(I);
               END GENERATE all_input;
               shift_data <= shift_data_pre + 1 WHEN shift_data_pre < 2 ELSE 0;
-              reg_shift_data_s(0) <= shift_data WHEN valid_out_rr(0) = '1' ELSE reg_shift_data_s(0);
+              reg_shift_data_s(0) <= shift_data WHEN valid_out_rr(0) = '1' ELSE reg_shift_data(0);--_s
-              reg_shift_data_s(1) <= shift_data WHEN valid_out_rr(1) = '1' ELSE reg_shift_data_s(1);
+              reg_shift_data_s(1) <= shift_data WHEN valid_out_rr(1) = '1' ELSE reg_shift_data(1);--_s
-              reg_shift_data_s(2) <= shift_data WHEN valid_out_rr(2) = '1' ELSE reg_shift_data_s(2);
+              reg_shift_data_s(2) <= shift_data WHEN valid_out_rr(2) = '1' ELSE reg_shift_data(2);--_s
-              reg_shift_data_s(3) <= shift_data WHEN valid_out_rr(3) = '1' ELSE reg_shift_data_s(3);
+              reg_shift_data_s(3) <= shift_data WHEN valid_out_rr(3) = '1' ELSE reg_shift_data(3);--_s
               -- SHIFT_TIME ---------------------------------------------------------------
               shift_time_pre <= reg_shift_time(0) WHEN valid_out_rr(0) = '1' ELSE
               shift_time <= shift_time_pre + 1 WHEN shift_time_pre < 2 ELSE 0;
-              reg_shift_time_s(0) <= shift_time WHEN valid_out_rr(0) = '1' ELSE reg_shift_time_s(0);
+              reg_shift_time_s(0) <= shift_time WHEN valid_out_rr(0) = '1' ELSE reg_shift_time(0);--_s
-              reg_shift_time_s(1) <= shift_time WHEN valid_out_rr(1) = '1' ELSE reg_shift_time_s(1);
+              reg_shift_time_s(1) <= shift_time WHEN valid_out_rr(1) = '1' ELSE reg_shift_time(1);--_s
-              reg_shift_time_s(2) <= shift_time WHEN valid_out_rr(2) = '1' ELSE reg_shift_time_s(2);
+              reg_shift_time_s(2) <= shift_time WHEN valid_out_rr(2) = '1' ELSE reg_shift_time(2);--_s
-              reg_shift_time_s(3) <= shift_time WHEN valid_out_rr(3) = '1' ELSE reg_shift_time_s(3);
+              reg_shift_time_s(3) <= shift_time WHEN valid_out_rr(3) = '1' ELSE reg_shift_time(3);--_s
               -- COUNT_DATA ---------------------------------------------------------------
               count_data_pre <= reg_count_data(0) WHEN valid_out_rr(0) = '1' ELSE
               count_data <= count_data_pre + 1 WHEN count_data_pre < UNSIGNED(nb_data_by_buffer) ELSE 0;
-              reg_count_data_s(0) <= count_data WHEN valid_out_rr(0) = '1' ELSE reg_count_data_s(0);
+              reg_count_data_s(0) <= count_data WHEN valid_out_rr(0) = '1' ELSE reg_count_data(0);--_s
-              reg_count_data_s(1) <= count_data WHEN valid_out_rr(1) = '1' ELSE reg_count_data_s(1);
+              reg_count_data_s(1) <= count_data WHEN valid_out_rr(1) = '1' ELSE reg_count_data(1);--_s
-              reg_count_data_s(2) <= count_data WHEN valid_out_rr(2) = '1' ELSE reg_count_data_s(2);
+              reg_count_data_s(2) <= count_data WHEN valid_out_rr(2) = '1' ELSE reg_count_data(2);--_s
-              reg_count_data_s(3) <= count_data WHEN valid_out_rr(3) = '1' ELSE reg_count_data_s(3);
+              reg_count_data_s(3) <= count_data WHEN valid_out_rr(3) = '1' ELSE reg_count_data(3);--_s
               -----------------------------------------------------------------------------
+              PROCESS (clk, rstn)
+              BEGIN  -- PROCESS
+                IF rstn = '0' THEN                  -- asynchronous reset (active low)
+                  reg_shift_time_pre <= 0;
+                ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
+                  reg_shift_time_pre <= shift_time_pre;
+                END IF;
+              END PROCESS 	;
             END ARCHITECTURE;