@@ -87,6 +87,7 ARCHITECTURE ar_lpp_waveform_fifo_arbite | |||
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87 | 87 | SIGNAL shift_data : INTEGER; |
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88 | 88 | SIGNAL reg_shift_data_s : Counter_Vector(3 DOWNTO 0); |
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89 | 89 | -- SHIFT_TIME --------------------------------------------------------------- |
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90 | SIGNAL reg_shift_time_pre : INTEGER; | |
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90 | 91 | SIGNAL shift_time_pre : INTEGER; |
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91 | 92 | SIGNAL shift_time : INTEGER; |
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92 | 93 | SIGNAL reg_shift_time_s : Counter_Vector(3 DOWNTO 0); |
@@ -117,8 +118,8 BEGIN | |||
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117 | 118 | data_temp_2(I)(J) <= data_in(I,J+32*2); |
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118 | 119 | END GENERATE all_bit_of_time; |
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119 | 120 | |
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120 |
data_temp_v(I) <= time_temp_0(I) |
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121 |
time_temp_1(I) |
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121 | data_temp_v(I) <= time_temp_0(I) WHEN reg_shift_time_pre = 0 ELSE | |
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122 | time_temp_1(I) WHEN reg_shift_time_pre = 1 ELSE | |
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122 | 123 |
data_temp_0(I) |
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123 | 124 |
data_temp_1(I) |
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124 | 125 | data_temp_2(I); |
@@ -198,10 +199,10 BEGIN | |||
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198 | 199 | |
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199 | 200 | shift_data <= shift_data_pre + 1 WHEN shift_data_pre < 2 ELSE 0; |
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200 | 201 | |
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201 |
reg_shift_data_s(0) <= shift_data WHEN valid_out_rr(0) = '1' ELSE reg_shift_data |
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202 |
reg_shift_data_s(1) <= shift_data WHEN valid_out_rr(1) = '1' ELSE reg_shift_data |
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203 |
reg_shift_data_s(2) <= shift_data WHEN valid_out_rr(2) = '1' ELSE reg_shift_data |
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204 |
reg_shift_data_s(3) <= shift_data WHEN valid_out_rr(3) = '1' ELSE reg_shift_data |
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202 | reg_shift_data_s(0) <= shift_data WHEN valid_out_rr(0) = '1' ELSE reg_shift_data(0);--_s | |
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203 | reg_shift_data_s(1) <= shift_data WHEN valid_out_rr(1) = '1' ELSE reg_shift_data(1);--_s | |
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204 | reg_shift_data_s(2) <= shift_data WHEN valid_out_rr(2) = '1' ELSE reg_shift_data(2);--_s | |
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205 | reg_shift_data_s(3) <= shift_data WHEN valid_out_rr(3) = '1' ELSE reg_shift_data(3);--_s | |
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205 | 206 | |
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206 | 207 | -- SHIFT_TIME --------------------------------------------------------------- |
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207 | 208 | shift_time_pre <= reg_shift_time(0) WHEN valid_out_rr(0) = '1' ELSE |
@@ -211,10 +212,10 BEGIN | |||
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211 | 212 | |
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212 | 213 | shift_time <= shift_time_pre + 1 WHEN shift_time_pre < 2 ELSE 0; |
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213 | 214 | |
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214 |
reg_shift_time_s(0) <= shift_time WHEN valid_out_rr(0) = '1' ELSE reg_shift_time |
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215 |
reg_shift_time_s(1) <= shift_time WHEN valid_out_rr(1) = '1' ELSE reg_shift_time |
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216 |
reg_shift_time_s(2) <= shift_time WHEN valid_out_rr(2) = '1' ELSE reg_shift_time |
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217 |
reg_shift_time_s(3) <= shift_time WHEN valid_out_rr(3) = '1' ELSE reg_shift_time |
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215 | reg_shift_time_s(0) <= shift_time WHEN valid_out_rr(0) = '1' ELSE reg_shift_time(0);--_s | |
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216 | reg_shift_time_s(1) <= shift_time WHEN valid_out_rr(1) = '1' ELSE reg_shift_time(1);--_s | |
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217 | reg_shift_time_s(2) <= shift_time WHEN valid_out_rr(2) = '1' ELSE reg_shift_time(2);--_s | |
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218 | reg_shift_time_s(3) <= shift_time WHEN valid_out_rr(3) = '1' ELSE reg_shift_time(3);--_s | |
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218 | 219 | |
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219 | 220 | -- COUNT_DATA --------------------------------------------------------------- |
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220 | 221 | count_data_pre <= reg_count_data(0) WHEN valid_out_rr(0) = '1' ELSE |
@@ -224,12 +225,21 BEGIN | |||
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224 | 225 | |
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225 | 226 | count_data <= count_data_pre + 1 WHEN count_data_pre < UNSIGNED(nb_data_by_buffer) ELSE 0; |
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226 | 227 | |
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227 |
reg_count_data_s(0) <= count_data WHEN valid_out_rr(0) = '1' ELSE reg_count_data |
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228 |
reg_count_data_s(1) <= count_data WHEN valid_out_rr(1) = '1' ELSE reg_count_data |
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229 |
reg_count_data_s(2) <= count_data WHEN valid_out_rr(2) = '1' ELSE reg_count_data |
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230 |
reg_count_data_s(3) <= count_data WHEN valid_out_rr(3) = '1' ELSE reg_count_data |
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228 | reg_count_data_s(0) <= count_data WHEN valid_out_rr(0) = '1' ELSE reg_count_data(0);--_s | |
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229 | reg_count_data_s(1) <= count_data WHEN valid_out_rr(1) = '1' ELSE reg_count_data(1);--_s | |
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230 | reg_count_data_s(2) <= count_data WHEN valid_out_rr(2) = '1' ELSE reg_count_data(2);--_s | |
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231 | reg_count_data_s(3) <= count_data WHEN valid_out_rr(3) = '1' ELSE reg_count_data(3);--_s | |
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231 | 232 | ----------------------------------------------------------------------------- |
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232 | 233 | |
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234 | PROCESS (clk, rstn) | |
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235 | BEGIN -- PROCESS | |
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236 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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237 | reg_shift_time_pre <= 0; | |
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238 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
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239 | reg_shift_time_pre <= shift_time_pre; | |
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240 | END IF; | |
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241 | END PROCESS ; | |
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242 | ||
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233 | 243 | END ARCHITECTURE; |
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234 | 244 | |
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235 | 245 |
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