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1 | ------------------------------------------------------------------------------ |
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1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS |
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3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
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4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
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5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
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6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
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7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
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8 | -- (at your option) any later version. | |
9 | -- |
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9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
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10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
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13 | -- GNU General Public License for more details. | |
14 | -- |
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14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
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15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
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16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
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18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Jean-christophe PELLION |
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19 | -- Author : Jean-christophe PELLION | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
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21 | ------------------------------------------------------------------------------ | |
22 | LIBRARY IEEE; |
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22 | LIBRARY IEEE; | |
23 | USE IEEE.std_logic_1164.ALL; |
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23 | USE IEEE.std_logic_1164.ALL; | |
24 | USE IEEE.numeric_std.ALL; |
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24 | USE IEEE.numeric_std.ALL; | |
25 |
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25 | |||
26 | LIBRARY lpp; |
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26 | LIBRARY lpp; | |
27 | USE lpp.lpp_waveform_pkg.ALL; |
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27 | USE lpp.lpp_waveform_pkg.ALL; | |
28 | USE lpp.general_purpose.ALL; |
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28 | USE lpp.general_purpose.ALL; | |
29 |
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29 | |||
30 | ENTITY lpp_waveform_fifo_arbiter IS |
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30 | ENTITY lpp_waveform_fifo_arbiter IS | |
31 | GENERIC( |
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31 | GENERIC( | |
32 | tech : INTEGER := 0; |
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32 | tech : INTEGER := 0; | |
33 | nb_data_by_buffer_size : INTEGER |
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33 | nb_data_by_buffer_size : INTEGER | |
34 | ); |
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34 | ); | |
35 | PORT( |
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35 | PORT( | |
36 | clk : IN STD_LOGIC; |
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36 | clk : IN STD_LOGIC; | |
37 | rstn : IN STD_LOGIC; |
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37 | rstn : IN STD_LOGIC; | |
38 | --------------------------------------------------------------------------- |
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38 | --------------------------------------------------------------------------- | |
39 | run : IN STD_LOGIC; |
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39 | run : IN STD_LOGIC; | |
40 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0); |
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40 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0); | |
41 | --------------------------------------------------------------------------- |
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41 | --------------------------------------------------------------------------- | |
42 | -- SNAPSHOT INTERFACE (INPUT) |
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42 | -- SNAPSHOT INTERFACE (INPUT) | |
43 | --------------------------------------------------------------------------- |
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43 | --------------------------------------------------------------------------- | |
44 | data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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44 | data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
45 | data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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45 | data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
46 | data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); |
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46 | data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); | |
47 | time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); |
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47 | time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); | |
48 |
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48 | |||
49 | --------------------------------------------------------------------------- |
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49 | --------------------------------------------------------------------------- | |
50 | -- FIFO INTERFACE (OUTPUT) |
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50 | -- FIFO INTERFACE (OUTPUT) | |
51 | --------------------------------------------------------------------------- |
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51 | --------------------------------------------------------------------------- | |
52 | data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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52 | data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
53 | data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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53 | data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
54 | full : IN STD_LOGIC_VECTOR(3 DOWNTO 0) |
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54 | full : IN STD_LOGIC_VECTOR(3 DOWNTO 0) | |
55 |
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55 | |||
56 | ); |
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56 | ); | |
57 | END ENTITY; |
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57 | END ENTITY; | |
58 |
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58 | |||
59 |
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59 | |||
60 | ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS |
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60 | ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS | |
61 |
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61 | |||
62 | ----------------------------------------------------------------------------- |
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62 | ----------------------------------------------------------------------------- | |
63 | -- DATA FLOW |
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63 | -- DATA FLOW | |
64 | ----------------------------------------------------------------------------- |
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64 | ----------------------------------------------------------------------------- | |
65 | TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0); |
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65 | TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0); | |
66 | SIGNAL time_temp_0 : WORD_VECTOR(3 DOWNTO 0); |
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66 | SIGNAL time_temp_0 : WORD_VECTOR(3 DOWNTO 0); | |
67 | SIGNAL time_temp_1 : WORD_VECTOR(3 DOWNTO 0); |
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67 | SIGNAL time_temp_1 : WORD_VECTOR(3 DOWNTO 0); | |
68 | SIGNAL data_temp_0 : WORD_VECTOR(3 DOWNTO 0); |
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68 | SIGNAL data_temp_0 : WORD_VECTOR(3 DOWNTO 0); | |
69 | SIGNAL data_temp_1 : WORD_VECTOR(3 DOWNTO 0); |
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69 | SIGNAL data_temp_1 : WORD_VECTOR(3 DOWNTO 0); | |
70 | SIGNAL data_temp_2 : WORD_VECTOR(3 DOWNTO 0); |
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70 | SIGNAL data_temp_2 : WORD_VECTOR(3 DOWNTO 0); | |
71 | SIGNAL data_temp_v : WORD_VECTOR(3 DOWNTO 0); |
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71 | SIGNAL data_temp_v : WORD_VECTOR(3 DOWNTO 0); | |
72 | SIGNAL sel_input : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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72 | SIGNAL sel_input : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
73 | ----------------------------------------------------------------------------- |
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73 | ----------------------------------------------------------------------------- | |
74 | -- CHANNEL SELECTION (RoundRobin) |
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74 | -- CHANNEL SELECTION (RoundRobin) | |
75 | ----------------------------------------------------------------------------- |
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75 | ----------------------------------------------------------------------------- | |
76 | SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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76 | SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
77 | SIGNAL valid_out_rr : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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77 | SIGNAL valid_out_rr : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
78 | ----------------------------------------------------------------------------- |
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78 | ----------------------------------------------------------------------------- | |
79 | -- FSM CONTROL |
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79 | -- FSM CONTROL | |
80 | ----------------------------------------------------------------------------- |
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80 | ----------------------------------------------------------------------------- | |
81 | TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; |
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81 | TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; | |
82 | SIGNAL reg_shift_data : Counter_Vector(3 DOWNTO 0); |
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82 | SIGNAL reg_shift_data : Counter_Vector(3 DOWNTO 0); | |
83 | SIGNAL reg_shift_time : Counter_Vector(3 DOWNTO 0); |
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83 | SIGNAL reg_shift_time : Counter_Vector(3 DOWNTO 0); | |
84 | SIGNAL reg_count_data : Counter_Vector(3 DOWNTO 0); |
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84 | SIGNAL reg_count_data : Counter_Vector(3 DOWNTO 0); | |
85 | -- SHIFT_DATA --------------------------------------------------------------- |
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85 | -- SHIFT_DATA --------------------------------------------------------------- | |
86 | SIGNAL shift_data_pre : INTEGER; |
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86 | SIGNAL shift_data_pre : INTEGER; | |
87 | SIGNAL shift_data : INTEGER; |
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87 | SIGNAL shift_data : INTEGER; | |
88 | SIGNAL reg_shift_data_s : Counter_Vector(3 DOWNTO 0); |
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88 | SIGNAL reg_shift_data_s : Counter_Vector(3 DOWNTO 0); | |
89 | -- SHIFT_TIME --------------------------------------------------------------- |
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89 | -- SHIFT_TIME --------------------------------------------------------------- | |
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90 | SIGNAL reg_shift_time_pre : INTEGER; | |||
90 | SIGNAL shift_time_pre : INTEGER; |
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91 | SIGNAL shift_time_pre : INTEGER; | |
91 | SIGNAL shift_time : INTEGER; |
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92 | SIGNAL shift_time : INTEGER; | |
92 | SIGNAL reg_shift_time_s : Counter_Vector(3 DOWNTO 0); |
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93 | SIGNAL reg_shift_time_s : Counter_Vector(3 DOWNTO 0); | |
93 | -- COUNT_DATA --------------------------------------------------------------- |
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94 | -- COUNT_DATA --------------------------------------------------------------- | |
94 | SIGNAL count_data_pre : INTEGER; |
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95 | SIGNAL count_data_pre : INTEGER; | |
95 | SIGNAL count_data : INTEGER; |
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96 | SIGNAL count_data : INTEGER; | |
96 | SIGNAL reg_count_data_s : Counter_Vector(3 DOWNTO 0); |
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97 | SIGNAL reg_count_data_s : Counter_Vector(3 DOWNTO 0); | |
97 |
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98 | |||
98 | BEGIN |
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99 | BEGIN | |
99 |
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100 | |||
100 | ----------------------------------------------------------------------------- |
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101 | ----------------------------------------------------------------------------- | |
101 | -- DATA FLOW |
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102 | -- DATA FLOW | |
102 | ----------------------------------------------------------------------------- |
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103 | ----------------------------------------------------------------------------- | |
103 |
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104 | |||
104 |
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105 | |||
105 | all_input : FOR I IN 3 DOWNTO 0 GENERATE |
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106 | all_input : FOR I IN 3 DOWNTO 0 GENERATE | |
106 |
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107 | |||
107 | all_bit_of_time: FOR J IN 31 DOWNTO 0 GENERATE |
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108 | all_bit_of_time: FOR J IN 31 DOWNTO 0 GENERATE | |
108 | time_temp_0(I)(J) <= time_in(I,J); |
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109 | time_temp_0(I)(J) <= time_in(I,J); | |
109 | J_47DOWNTO32: IF J+32 < 48 GENERATE |
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110 | J_47DOWNTO32: IF J+32 < 48 GENERATE | |
110 | time_temp_1(I)(J) <= time_in(I,32+J); |
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111 | time_temp_1(I)(J) <= time_in(I,32+J); | |
111 | END GENERATE J_47DOWNTO32; |
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112 | END GENERATE J_47DOWNTO32; | |
112 | J_63DOWNTO48: IF J+32 > 47 GENERATE |
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113 | J_63DOWNTO48: IF J+32 > 47 GENERATE | |
113 | time_temp_1(I)(J) <= '0'; |
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114 | time_temp_1(I)(J) <= '0'; | |
114 | END GENERATE J_63DOWNTO48; |
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115 | END GENERATE J_63DOWNTO48; | |
115 | data_temp_0(I)(J) <= data_in(I,J); |
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116 | data_temp_0(I)(J) <= data_in(I,J); | |
116 | data_temp_1(I)(J) <= data_in(I,J+32); |
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117 | data_temp_1(I)(J) <= data_in(I,J+32); | |
117 | data_temp_2(I)(J) <= data_in(I,J+32*2); |
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118 | data_temp_2(I)(J) <= data_in(I,J+32*2); | |
118 | END GENERATE all_bit_of_time; |
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119 | END GENERATE all_bit_of_time; | |
119 |
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120 | |||
120 |
data_temp_v(I) <= time_temp_0(I) |
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121 | data_temp_v(I) <= time_temp_0(I) WHEN reg_shift_time_pre = 0 ELSE | |
121 |
time_temp_1(I) |
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122 | time_temp_1(I) WHEN reg_shift_time_pre = 1 ELSE | |
122 |
data_temp_0(I) |
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123 | data_temp_0(I) WHEN shift_data = 0 ELSE | |
123 |
data_temp_1(I) |
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124 | data_temp_1(I) WHEN shift_data = 1 ELSE | |
124 | data_temp_2(I); |
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125 | data_temp_2(I); | |
125 | END GENERATE all_input; |
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126 | END GENERATE all_input; | |
126 |
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127 | |||
127 | data_out <= data_temp_v(0) WHEN sel_input = "0001" ELSE |
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128 | data_out <= data_temp_v(0) WHEN sel_input = "0001" ELSE | |
128 | data_temp_v(1) WHEN sel_input = "0010" ELSE |
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129 | data_temp_v(1) WHEN sel_input = "0010" ELSE | |
129 | data_temp_v(2) WHEN sel_input = "0100" ELSE |
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130 | data_temp_v(2) WHEN sel_input = "0100" ELSE | |
130 | data_temp_v(3); |
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131 | data_temp_v(3); | |
131 |
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132 | |||
132 | ----------------------------------------------------------------------------- |
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133 | ----------------------------------------------------------------------------- | |
133 | -- CHANNEL SELECTION (RoundRobin) |
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134 | -- CHANNEL SELECTION (RoundRobin) | |
134 | ----------------------------------------------------------------------------- |
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135 | ----------------------------------------------------------------------------- | |
135 | all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE |
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136 | all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE | |
136 | -- valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I); |
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137 | -- valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I); | |
137 | valid_in_rr(I) <= data_in_valid(I) AND NOT full(I); |
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138 | valid_in_rr(I) <= data_in_valid(I) AND NOT full(I); | |
138 | END GENERATE all_input_rr; |
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139 | END GENERATE all_input_rr; | |
139 |
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140 | |||
140 | RR_Arbiter_4_1 : RR_Arbiter_4 |
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141 | RR_Arbiter_4_1 : RR_Arbiter_4 | |
141 | PORT MAP ( |
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142 | PORT MAP ( | |
142 | clk => clk, |
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143 | clk => clk, | |
143 | rstn => rstn, |
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144 | rstn => rstn, | |
144 | in_valid => valid_in_rr, |
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145 | in_valid => valid_in_rr, | |
145 | out_grant => valid_out_rr); |
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146 | out_grant => valid_out_rr); | |
146 |
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147 | |||
147 | ----------------------------------------------------------------------------- |
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148 | ----------------------------------------------------------------------------- | |
148 | -- FSM CONTROL |
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149 | -- FSM CONTROL | |
149 | ----------------------------------------------------------------------------- |
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150 | ----------------------------------------------------------------------------- | |
150 |
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151 | |||
151 | PROCESS (clk, rstn) |
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152 | PROCESS (clk, rstn) | |
152 | BEGIN -- PROCESS |
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153 | BEGIN -- PROCESS | |
153 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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154 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
154 | reg_shift_data <= (0, 0, 0, 0); |
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155 | reg_shift_data <= (0, 0, 0, 0); | |
155 | reg_shift_time <= (0, 0, 0, 0); |
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156 | reg_shift_time <= (0, 0, 0, 0); | |
156 | reg_count_data <= (0, 0, 0, 0); |
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157 | reg_count_data <= (0, 0, 0, 0); | |
157 | sel_input <= (OTHERS => '0'); |
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158 | sel_input <= (OTHERS => '0'); | |
158 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
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159 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
159 | IF run = '0' THEN |
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160 | IF run = '0' THEN | |
160 | reg_shift_data <= (0, 0, 0, 0); |
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161 | reg_shift_data <= (0, 0, 0, 0); | |
161 | reg_shift_time <= (0, 0, 0, 0); |
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162 | reg_shift_time <= (0, 0, 0, 0); | |
162 | reg_count_data <= (0, 0, 0, 0); |
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163 | reg_count_data <= (0, 0, 0, 0); | |
163 | sel_input <= (OTHERS => '0'); |
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164 | sel_input <= (OTHERS => '0'); | |
164 | ELSE |
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165 | ELSE | |
165 | sel_input <= valid_out_rr; |
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166 | sel_input <= valid_out_rr; | |
166 |
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167 | |||
167 | IF count_data_pre = 0 THEN -- first buffer data |
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168 | IF count_data_pre = 0 THEN -- first buffer data | |
168 | IF shift_time_pre < 2 THEN -- TIME not completly send |
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169 | IF shift_time_pre < 2 THEN -- TIME not completly send | |
169 | reg_shift_time <= reg_shift_time_s; |
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170 | reg_shift_time <= reg_shift_time_s; | |
170 | ELSE |
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171 | ELSE | |
171 | reg_shift_data <= reg_shift_data_s; |
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172 | reg_shift_data <= reg_shift_data_s; | |
172 | IF shift_data_pre = 2 THEN |
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173 | IF shift_data_pre = 2 THEN | |
173 | reg_count_data <= reg_count_data_s; |
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174 | reg_count_data <= reg_count_data_s; | |
174 | END IF; |
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175 | END IF; | |
175 | END IF; |
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176 | END IF; | |
176 | ELSE |
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177 | ELSE | |
177 | reg_shift_data <= reg_shift_data_s; |
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178 | reg_shift_data <= reg_shift_data_s; | |
178 | IF shift_data_pre = 2 THEN |
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179 | IF shift_data_pre = 2 THEN | |
179 | reg_count_data <= reg_count_data_s; |
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180 | reg_count_data <= reg_count_data_s; | |
180 | IF count_data = 0 THEN |
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181 | IF count_data = 0 THEN | |
181 | reg_shift_time <= reg_shift_time_s; |
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182 | reg_shift_time <= reg_shift_time_s; | |
182 | END IF; |
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183 | END IF; | |
183 | END IF; |
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184 | END IF; | |
184 | END IF; |
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185 | END IF; | |
185 | END IF; |
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186 | END IF; | |
186 | END IF; |
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187 | END IF; | |
187 | END PROCESS; |
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188 | END PROCESS; | |
188 |
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189 | |||
189 | ----------------------------------------------------------------------------- |
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190 | ----------------------------------------------------------------------------- | |
190 | data_out_wen <= NOT sel_input; |
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191 | data_out_wen <= NOT sel_input; | |
191 | data_in_ack <= sel_input; |
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192 | data_in_ack <= sel_input; | |
192 |
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193 | |||
193 | -- SHIFT_DATA --------------------------------------------------------------- |
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194 | -- SHIFT_DATA --------------------------------------------------------------- | |
194 | shift_data_pre <= reg_shift_data(0) WHEN valid_out_rr(0) = '1' ELSE |
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195 | shift_data_pre <= reg_shift_data(0) WHEN valid_out_rr(0) = '1' ELSE | |
195 | reg_shift_data(1) WHEN valid_out_rr(1) = '1' ELSE |
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196 | reg_shift_data(1) WHEN valid_out_rr(1) = '1' ELSE | |
196 | reg_shift_data(2) WHEN valid_out_rr(2) = '1' ELSE |
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197 | reg_shift_data(2) WHEN valid_out_rr(2) = '1' ELSE | |
197 | reg_shift_data(3); |
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198 | reg_shift_data(3); | |
198 |
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199 | |||
199 | shift_data <= shift_data_pre + 1 WHEN shift_data_pre < 2 ELSE 0; |
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200 | shift_data <= shift_data_pre + 1 WHEN shift_data_pre < 2 ELSE 0; | |
200 |
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201 | |||
201 |
reg_shift_data_s(0) <= shift_data WHEN valid_out_rr(0) = '1' ELSE reg_shift_data |
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202 | reg_shift_data_s(0) <= shift_data WHEN valid_out_rr(0) = '1' ELSE reg_shift_data(0);--_s | |
202 |
reg_shift_data_s(1) <= shift_data WHEN valid_out_rr(1) = '1' ELSE reg_shift_data |
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203 | reg_shift_data_s(1) <= shift_data WHEN valid_out_rr(1) = '1' ELSE reg_shift_data(1);--_s | |
203 |
reg_shift_data_s(2) <= shift_data WHEN valid_out_rr(2) = '1' ELSE reg_shift_data |
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204 | reg_shift_data_s(2) <= shift_data WHEN valid_out_rr(2) = '1' ELSE reg_shift_data(2);--_s | |
204 |
reg_shift_data_s(3) <= shift_data WHEN valid_out_rr(3) = '1' ELSE reg_shift_data |
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205 | reg_shift_data_s(3) <= shift_data WHEN valid_out_rr(3) = '1' ELSE reg_shift_data(3);--_s | |
205 |
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206 | |||
206 | -- SHIFT_TIME --------------------------------------------------------------- |
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207 | -- SHIFT_TIME --------------------------------------------------------------- | |
207 | shift_time_pre <= reg_shift_time(0) WHEN valid_out_rr(0) = '1' ELSE |
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208 | shift_time_pre <= reg_shift_time(0) WHEN valid_out_rr(0) = '1' ELSE | |
208 | reg_shift_time(1) WHEN valid_out_rr(1) = '1' ELSE |
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209 | reg_shift_time(1) WHEN valid_out_rr(1) = '1' ELSE | |
209 | reg_shift_time(2) WHEN valid_out_rr(2) = '1' ELSE |
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210 | reg_shift_time(2) WHEN valid_out_rr(2) = '1' ELSE | |
210 | reg_shift_time(3); |
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211 | reg_shift_time(3); | |
211 |
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212 | |||
212 | shift_time <= shift_time_pre + 1 WHEN shift_time_pre < 2 ELSE 0; |
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213 | shift_time <= shift_time_pre + 1 WHEN shift_time_pre < 2 ELSE 0; | |
213 |
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214 | |||
214 |
reg_shift_time_s(0) <= shift_time WHEN valid_out_rr(0) = '1' ELSE reg_shift_time |
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215 | reg_shift_time_s(0) <= shift_time WHEN valid_out_rr(0) = '1' ELSE reg_shift_time(0);--_s | |
215 |
reg_shift_time_s(1) <= shift_time WHEN valid_out_rr(1) = '1' ELSE reg_shift_time |
|
216 | reg_shift_time_s(1) <= shift_time WHEN valid_out_rr(1) = '1' ELSE reg_shift_time(1);--_s | |
216 |
reg_shift_time_s(2) <= shift_time WHEN valid_out_rr(2) = '1' ELSE reg_shift_time |
|
217 | reg_shift_time_s(2) <= shift_time WHEN valid_out_rr(2) = '1' ELSE reg_shift_time(2);--_s | |
217 |
reg_shift_time_s(3) <= shift_time WHEN valid_out_rr(3) = '1' ELSE reg_shift_time |
|
218 | reg_shift_time_s(3) <= shift_time WHEN valid_out_rr(3) = '1' ELSE reg_shift_time(3);--_s | |
218 |
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219 | |||
219 | -- COUNT_DATA --------------------------------------------------------------- |
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220 | -- COUNT_DATA --------------------------------------------------------------- | |
220 | count_data_pre <= reg_count_data(0) WHEN valid_out_rr(0) = '1' ELSE |
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221 | count_data_pre <= reg_count_data(0) WHEN valid_out_rr(0) = '1' ELSE | |
221 | reg_count_data(1) WHEN valid_out_rr(1) = '1' ELSE |
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222 | reg_count_data(1) WHEN valid_out_rr(1) = '1' ELSE | |
222 | reg_count_data(2) WHEN valid_out_rr(2) = '1' ELSE |
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223 | reg_count_data(2) WHEN valid_out_rr(2) = '1' ELSE | |
223 | reg_count_data(3); |
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224 | reg_count_data(3); | |
224 |
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225 | |||
225 | count_data <= count_data_pre + 1 WHEN count_data_pre < UNSIGNED(nb_data_by_buffer) ELSE 0; |
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226 | count_data <= count_data_pre + 1 WHEN count_data_pre < UNSIGNED(nb_data_by_buffer) ELSE 0; | |
226 |
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227 | |||
227 |
reg_count_data_s(0) <= count_data WHEN valid_out_rr(0) = '1' ELSE reg_count_data |
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228 | reg_count_data_s(0) <= count_data WHEN valid_out_rr(0) = '1' ELSE reg_count_data(0);--_s | |
228 |
reg_count_data_s(1) <= count_data WHEN valid_out_rr(1) = '1' ELSE reg_count_data |
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229 | reg_count_data_s(1) <= count_data WHEN valid_out_rr(1) = '1' ELSE reg_count_data(1);--_s | |
229 |
reg_count_data_s(2) <= count_data WHEN valid_out_rr(2) = '1' ELSE reg_count_data |
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230 | reg_count_data_s(2) <= count_data WHEN valid_out_rr(2) = '1' ELSE reg_count_data(2);--_s | |
230 |
reg_count_data_s(3) <= count_data WHEN valid_out_rr(3) = '1' ELSE reg_count_data |
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231 | reg_count_data_s(3) <= count_data WHEN valid_out_rr(3) = '1' ELSE reg_count_data(3);--_s | |
231 | ----------------------------------------------------------------------------- |
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232 | ----------------------------------------------------------------------------- | |
232 |
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233 | |||
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234 | PROCESS (clk, rstn) | |||
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235 | BEGIN -- PROCESS | |||
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236 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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237 | reg_shift_time_pre <= 0; | |||
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238 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
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239 | reg_shift_time_pre <= shift_time_pre; | |||
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240 | END IF; | |||
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241 | END PROCESS ; | |||
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242 | ||||
233 | END ARCHITECTURE; |
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243 | END ARCHITECTURE; | |
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