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APB_MATRIX, second version /!\ not stable /!\
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 entity GetResult is
27 generic(
28 Result_SZ : integer := 32);
29 port(
30 clk : in std_logic;
31 raz : in std_logic;
32 Valid : in std_logic;
33 Conjugate : in std_logic;
34 Res : in std_logic_vector(Result_SZ-1 downto 0);
35 Received : out std_logic;
36 Result : out std_logic_vector(Result_SZ-1 downto 0)
37 );
38 end GetResult;
39
40
41 architecture ar_GetResult of GetResult is
42
43 signal Valid_reg : std_logic;
44
45 type state is (st0,st1);
46 signal ect : state;
47
48 begin
49 process(clk,raz)
50 begin
51
52 if(raz='0')then
53 Received <= '0';
54 Valid_reg <= '0';
55 ect <= st0;
56 Result <= (others => '0');
57
58 elsif(clk'event and clk='1')then
59 Valid_reg <= Valid;
60
61 case ect is
62 when st0 =>
63 Received <= '0';
64 if(Valid_reg='0' and Valid='1')then
65 Result <= Res;
66 if(Conjugate='1')then
67 Received <= '1';
68 ect <= st0;
69 else
70 ect <= st1;
71 end if;
72 end if;
73
74 when st1 =>
75 Received <= '1';
76 if(Valid_reg='0' and Valid='1')then
77 Result <= Res;
78 ect <= st0;
79 end if;
80
81 end case;
82 end if;
83 end process;
84
85 end ar_GetResult;
86
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 entity SelectInputs is
27 generic(
28 Input_SZ : integer := 16);
29 port(
30 clk : in std_logic;
31 raz : in std_logic;
32 Read : in std_logic;
33 B1 : in std_logic_vector(Input_SZ-1 downto 0);
34 B2 : in std_logic_vector(Input_SZ-1 downto 0);
35 B3 : in std_logic_vector(Input_SZ-1 downto 0);
36 E1 : in std_logic_vector(Input_SZ-1 downto 0);
37 E2 : in std_logic_vector(Input_SZ-1 downto 0);
38 Conjugate : out std_logic;
39 Take : out std_logic;
40 ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
41 OP1 : out std_logic_vector(Input_SZ-1 downto 0);
42 OP2 : out std_logic_vector(Input_SZ-1 downto 0)
43 );
44 end SelectInputs;
45
46
47 architecture ar_SelectInputs of SelectInputs is
48
49 signal Read_reg : std_logic;
50 signal i : integer range 1 to 15;
51
52 type state is (stX,st1a,st1b);
53 signal ect : state;
54
55 begin
56 process(clk,raz)
57 begin
58
59 if(raz='0')then
60 Take <= '0';
61 i <= 0;
62 Read_reg <= '0';
63 ect <= stX;
64
65 elsif(clk'event and clk='1')then
66 Read_reg <= Read;
67
68 case ect is
69 when stX =>
70 i <= 1;
71 if(Read_reg='0' and Read='1')then
72 ect <= st1a;
73 end if;
74 -------------------------------------------------------------------------------
75 when st1a =>
76 Take <= '1';
77 if(Read_reg='0' and Read='1')then
78 ect <= st1b;
79 end if;
80
81 when st1b =>
82 Take <= '0';
83 if(i=15)then
84 ect <= stX;
85 elsif(Read_reg='0' and Read='1')then
86 i <= i+1;
87 ect <= st1a;
88 end if;
89 -------------------------------------------------------------------------------
90 -- when st2a =>
91 -- Take <= '1';
92 -- if(Read_reg='0' and Read='1')then
93 -- ect <= st2b;
94 -- end if;
95 --
96 -- when st2b =>
97 -- Take <= '0';
98 -- if(Read_reg='0' and Read='1')then
99 -- ect <= st3a;
100 -- end if;
101 ---------------------------------------------------------------------------------
102 -- when st3a =>
103 -- Take <= '1';
104 -- if(Read_reg='0' and Read='1')then
105 -- ect <= st3b;
106 -- end if;
107 --
108 -- when st3b =>
109 -- Take <= '0';
110 -- if(Read_reg='0' and Read='1')then
111 -- ect <= st4a;
112 -- end if;
113 ---------------------------------------------------------------------------------
114 -- when st4a =>
115 -- Take <= '1';
116 -- if(Read_reg='0' and Read='1')then
117 -- ect <= st4b;
118 -- end if;
119 --
120 -- when st4b =>
121 -- Take <= '0';
122 -- if(Read_reg='0' and Read='1')then
123 -- ect <= st5a;
124 -- end if;
125 ---------------------------------------------------------------------------------
126 --
127 -- when st5a =>
128 -- Take <= '1';
129 -- if(Read_reg='0' and Read='1')then
130 -- ect <= st5b;
131 -- end if;
132 --
133 -- when st5b =>
134 -- Take <= '0';
135 -- if(Read_reg='0' and Read='1')then
136 -- ect <= st6a;
137 -- end if;
138 ---------------------------------------------------------------------------------
139 -- when st6a =>
140 -- Take <= '1';
141 -- if(Read_reg='0' and Read='1')then
142 -- ect <= st6b;
143 -- end if;
144 --
145 -- when st6b =>
146 -- Take <= '0';
147 -- if(Read_reg='0' and Read='1')then
148 -- ect <= st7a;
149 -- end if;
150 ---------------------------------------------------------------------------------
151 -- when st7a =>
152 -- Take <= '1';
153 -- if(Read_reg='0' and Read='1')then
154 -- ect <= st7b;
155 -- end if;
156 --
157 -- when st7b =>
158 -- Take <= '0';
159 -- if(Read_reg='0' and Read='1')then
160 -- ect <= st8a;
161 -- end if;
162 ---------------------------------------------------------------------------------
163 -- when st8a =>
164 -- Take <= '1';
165 -- if(Read_reg='0' and Read='1')then
166 -- ect <= st8b;
167 -- end if;
168 --
169 -- when st8b =>
170 -- Take <= '0';
171 -- if(Read_reg='0' and Read='1')then
172 -- ect <= st9a;
173 -- end if;
174 ---------------------------------------------------------------------------------
175 -- when st9a =>
176 -- Take <= '1';
177 -- if(Read_reg='0' and Read='1')then
178 -- ect <= st9b;
179 -- end if;
180 --
181 -- when st9b =>
182 -- Take <= '0';
183 -- if(Read_reg='0' and Read='1')then
184 -- ect <= st10a;
185 -- end if;
186 ---------------------------------------------------------------------------------
187 -- when st10a =>
188 -- Take <= '1';
189 -- if(Read_reg='0' and Read='1')then
190 -- ect <= st10b;
191 -- end if;
192 --
193 -- when st10b =>
194 -- Take <= '0';
195 -- if(Read_reg='0' and Read='1')then
196 -- ect <= st11a;
197 -- end if;
198 ---------------------------------------------------------------------------------
199 -- when st11a =>
200 -- Take <= '1';
201 -- if(Read_reg='0' and Read='1')then
202 -- ect <= st11b;
203 -- end if;
204 --
205 -- when st11b =>
206 -- Take <= '0';
207 -- if(Read_reg='0' and Read='1')then
208 -- ect <= st12a;
209 -- end if;
210 ---------------------------------------------------------------------------------
211 -- when st12a =>
212 -- Take <= '1';
213 -- if(Read_reg='0' and Read='1')then
214 -- ect <= st12b;
215 -- end if;
216 --
217 -- when st12b =>
218 -- Take <= '0';
219 -- if(Read_reg='0' and Read='1')then
220 -- ect <= st13a;
221 -- end if;
222 ---------------------------------------------------------------------------------
223 -- when st13a =>
224 -- Take <= '1';
225 -- if(Read_reg='0' and Read='1')then
226 -- ect <= st13b;
227 -- end if;
228 --
229 -- when st13b =>
230 -- Take <= '0';
231 -- if(Read_reg='0' and Read='1')then
232 -- ect <= st14a;
233 -- end if;
234 ---------------------------------------------------------------------------------
235 -- when st14a =>
236 -- Take <= '1';
237 -- if(Read_reg='0' and Read='1')then
238 -- ect <= st14b;
239 -- end if;
240 --
241 -- when st14b =>
242 -- Take <= '0';
243 -- if(Read_reg='0' and Read='1')then
244 -- ect <= st15a;
245 -- end if;
246 ---------------------------------------------------------------------------------
247 -- when st15a =>
248 -- Take <= '1';
249 -- if(Read_reg='0' and Read='1')then
250 -- ect <= st7_b;
251 -- end if;
252 --
253 -- when st15b =>
254 -- Take <= '0';
255 -- if(Read_reg='0' and Read='1')then
256 -- ect <= stX;
257 -- end if;
258 -------------------------------------------------------------------------------
259 end case;
260 end if;
261 end process;
262
263 with i select
264 ReadFIFO <= "10000" when 1,
265 "11000" when 2,
266 "01000" when 3,
267 "10100" when 4,
268 "01100" when 5,
269 "00100" when 6,
270 "10010" when 7,
271 "01010" when 8,
272 "00110" when 9,
273 "00010" when 10,
274 "10001" when 11,
275 "01001" when 12,
276 "00101" when 13,
277 "00011" when 14,
278 "00001" when 15,
279 "00000" when others;
280
281 --with ect select
282 -- ReadB2 <= Read when st1,
283 -- Read when st2,
284 -- Read when st4,
285 -- Read when st7,
286 -- Read when st11,
287 -- '0' when others;
288 --
289 --with ect select
290 -- ReadB3 <= Read when st3,
291 -- Read when st4,
292 -- Read when st5,
293 -- Read when st8,
294 -- Read when st12,
295 -- '0' when others;
296 --
297 --with ect select
298 -- ReadE1 <= Read when st6,
299 -- Read when st7,
300 -- Read when st8,
301 -- Read when st9,
302 -- Read when st13,
303 -- '0' when others;
304 --
305 --with ect select
306 -- ReadE2 <= Read when st10,
307 -- Read when st11,
308 -- Read when st12,
309 -- Read when st13,
310 -- Read when st14,
311 -- '0' when others;
312
313 with i select
314 OP1 <= B1 when 1,
315 B1 when 2,
316 B1 when 4,
317 B1 when 7,
318 B1 when 11,
319 B2 when 3,
320 B2 when 5,
321 B2 when 8,
322 B2 when 12,
323 B3 when 6,
324 B3 when 9,
325 B3 when 13,
326 E1 when 10,
327 E1 when 14,
328 E2 when 15,
329 X"FFFF" when others;
330
331 with i select
332 OP2 <= B1 when 1,
333 B2 when 2,
334 B2 when 3,
335 B3 when 4,
336 B3 when 5,
337 B3 when 6,
338 E1 when 7,
339 E1 when 8,
340 E1 when 9,
341 E1 when 10,
342 E2 when 11,
343 E2 when 12,
344 E2 when 13,
345 E2 when 14,
346 E2 when 15,
347 X"FFFF" when others;
348
349 with i select
350 Conjugate <= '1' when 1,
351 '1' when 3,
352 '1' when 6,
353 '1' when 10,
354 '1' when 15,
355 '0' when others;
356
357
358 --RE_FIFO <= ReadE2 & ReadE1 & ReadB3 & ReadB2 & ReadB1;
359 end ar_SelectInputs; No newline at end of file
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@@ -0,0 +1,74
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 use lpp.lpp_matrix.all;
26
27 entity SpectralMatrix is
28 generic(
29 Input_SZ : integer := 16;
30 Result_SZ : integer := 32);
31 port(
32 clk : in std_logic;
33 reset : in std_logic;
34 B1 : in std_logic_vector(Input_SZ-1 downto 0);
35 B2 : in std_logic_vector(Input_SZ-1 downto 0);
36 B3 : in std_logic_vector(Input_SZ-1 downto 0);
37 E1 : in std_logic_vector(Input_SZ-1 downto 0);
38 E2 : in std_logic_vector(Input_SZ-1 downto 0);
39 ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
40 Result : out std_logic_vector(Result_SZ-1 downto 0)
41 );
42 end SpectralMatrix;
43
44
45 architecture ar_SpectralMatrix of SpectralMatrix is
46
47 signal Read : std_logic;
48 signal Take : std_logic;
49 signal Received : std_logic;
50 signal Valid : std_logic;
51 signal Conjugate : std_logic;
52 signal OP1 : std_logic_vector(Input_SZ-1 downto 0);
53 signal OP2 : std_logic_vector(Input_SZ-1 downto 0);
54 signal Resultat : std_logic_vector(Result_SZ-1 downto 0);
55
56 begin
57
58
59 IN0 : SelectInputs
60 generic map(Input_SZ)
61 port map(clk,reset,Read,B1,B2,B3,E1,E2,Conjugate,Take,ReadFIFO,OP1,OP2);
62
63
64 CALC0 : Matrix
65 generic map(Input_SZ)
66 port map(clk,reset,OP1,OP2,Take,Received,Conjugate,Valid,Read,Resultat);
67
68
69 RES0 : GetResult
70 generic map(Result_SZ)
71 port map(clk,reset,Valid,Conjugate,Resultat,Received,Result);
72
73
74 end ar_SpectralMatrix; No newline at end of file
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@@ -30,17 +30,18 entity ALU_Driver is
30 30 Input_SZ_1 : integer := 16;
31 31 Input_SZ_2 : integer := 16);
32 32 port(
33 clk : in std_logic; --! Horloge du composant
34 reset : in std_logic; --! Reset general du composant
35 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Donn�e d'entr�e
36 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Donn�e d'entr�e
37 Take : in std_logic; --! Flag, op�rande r�cup�r�
38 Received : in std_logic; --! Flag, R�sultat bien ressu
39 Valid : out std_logic; --! Flag, R�sultat disponible
40 Read : out std_logic; --! Flag, op�rande disponible
41 CTRL : out std_logic_vector(4 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e
42 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande
43 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second Op�rande
33 clk : in std_logic; --! Horloge du composant
34 reset : in std_logic; --! Reset general du composant
35 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Donn�e d'entr�e
36 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Donn�e d'entr�e
37 Take : in std_logic; --! Flag, op�rande r�cup�r�
38 Received : in std_logic; --! Flag, R�sultat bien ressu
39 Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu�
40 Valid : out std_logic; --! Flag, R�sultat disponible
41 Read : out std_logic; --! Flag, op�rande disponible
42 CTRL : out std_logic_vector(4 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e
43 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande
44 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second Op�rande
44 45 );
45 46 end ALU_Driver;
46 47
@@ -66,13 +67,13 begin
66 67 begin
67 68
68 69 if(reset='0')then
69 ect <= eX;
70 st <= e0;
71 go_st <= '0';
72 CTRL <= "10000";
73 Read <= '0';
74 Valid <= '0';
75 Take_reg <= '0';
70 ect <= eX;
71 st <= e0;
72 go_st <= '0';
73 CTRL <= "10000";
74 Read <= '0';
75 Valid <= '0';
76 Take_reg <= '0';
76 77 Received_reg <= '0';
77 78
78 79 elsif(clk'event and clk='1')then
@@ -120,7 +121,11 begin
120 121 CTRL <= "00000";
121 122 go_st <= '1';
122 123 if(Received_reg='0' and Received='1')then
123 ect <= e3;
124 if(Conjugate='1')then
125 ect <= eX;
126 else
127 ect <= e3;
128 end if;
124 129 end if;
125 130
126 131 when e3 =>
@@ -147,7 +152,7 begin
147 152 ect <= eX;
148 153 end if;
149 154 end case;
150
155 ---------------------------------------------------------------------------------
151 156 case st is
152 157 when e0 =>
153 158 if(go_st='1')then
@@ -160,8 +165,12 begin
160 165
161 166 when e2 =>
162 167 if(Received_reg='0' and Received='1')then
163 Valid <= '0';
164 st <= idle;
168 Valid <= '0';
169 if(Conjugate='1')then
170 st <= idle2;
171 else
172 st <= idle;
173 end if;
165 174 end if;
166 175
167 176 when idle =>
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@@ -22,6 +22,7
22 22 library IEEE;
23 23 use IEEE.numeric_std.all;
24 24 use IEEE.std_logic_1164.all;
25 use lpp.lpp_matrix.all;
25 26
26 27 --! Une ALU : Arithmetic and logical unit, permettant de r�aliser une ou plusieurs op�ration
27 28
@@ -58,7 +59,7 begin
58 59 clr_MAC <= '1' when ctrl = "10000" else '0';
59 60
60 61 arith : if Arith_en = 1 generate
61 MACinst : entity work.MAC_v2
62 MACinst : MAC_v2
62 63 generic map(Input_SZ_1,Input_SZ_2)
63 64 port map(clk,reset,clr_MAC,ctrl(3 downto 0),OP1,OP2,RES);
64 65 end generate;
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@@ -22,6 +22,8
22 22 library IEEE;
23 23 use IEEE.numeric_std.all;
24 24 use IEEE.std_logic_1164.all;
25 use lpp.lpp_matrix.all;
26 use lpp.general_purpose.all;
25 27
26 28 --! Un MAC : Multiplier Accumulator Chip
27 29
@@ -79,7 +81,7 begin
79 81 --==============================================================
80 82 --=============M A C C O N T R O L E R=========================
81 83 --==============================================================
82 MAC_CONTROLER1 : entity work.MAC_CONTROLER
84 MAC_CONTROLER1 : MAC_CONTROLER
83 85 port map(
84 86 ctrl => MAC_MUL_ADD_2C_D(1 downto 0),
85 87 MULT => mult,
@@ -96,7 +98,7 port map(
96 98 --==============================================================
97 99 --=============M U L T I P L I E R==============================
98 100 --==============================================================
99 Multiplieri_nst : entity work.Multiplier
101 Multiplieri_nst : Multiplier
100 102 generic map(
101 103 Input_SZ_A => Input_SZ_A,
102 104 Input_SZ_B => Input_SZ_B
@@ -118,7 +120,7 port map(
118 120 --==============================================================
119 121 --======================A D D E R ==============================
120 122 --==============================================================
121 adder_inst : entity work.Adder
123 adder_inst : Adder
122 124 generic map(
123 125 Input_SZ_A => Input_SZ_A+Input_SZ_B,
124 126 Input_SZ_B => Input_SZ_A+Input_SZ_B
@@ -141,7 +143,7 port map(
141 143 --==============================================================
142 144 --===================TWO COMPLEMENTERS==========================
143 145 --==============================================================
144 TWO_COMPLEMENTER1 : entity work.TwoComplementer
146 TWO_COMPLEMENTER1 : TwoComplementer
145 147 generic map(
146 148 Input_SZ => Input_SZ_A
147 149 )
@@ -155,7 +157,7 port map(
155 157 );
156 158
157 159
158 TWO_COMPLEMENTER2 : entity work.TwoComplementer
160 TWO_COMPLEMENTER2 : TwoComplementer
159 161 generic map(
160 162 Input_SZ => Input_SZ_B
161 163 )
@@ -169,7 +171,7 port map(
169 171 );
170 172 --==============================================================
171 173
172 CTRL : entity work.MAC_REG
174 CTRL : MAC_REG
173 175 generic map(size => 2)
174 176 port map(
175 177 reset => reset,
@@ -178,7 +180,7 port map(
178 180 Q => MAC_MUL_ADD_2C_D(1 downto 0)
179 181 );
180 182
181 clr_MACREG1 : entity work.MAC_REG
183 clr_MACREG1 : MAC_REG
182 184 generic map(size => 1)
183 185 port map(
184 186 reset => reset,
@@ -187,7 +189,7 port map(
187 189 Q(0) => clr_MAC_D
188 190 );
189 191
190 clr_MACREG2 : entity work.MAC_REG
192 clr_MACREG2 : MAC_REG
191 193 generic map(size => 1)
192 194 port map(
193 195 reset => reset,
@@ -196,7 +198,7 port map(
196 198 Q(0) => clr_MAC_D_D
197 199 );
198 200
199 addREG : entity work.MAC_REG
201 addREG : MAC_REG
200 202 generic map(size => 1)
201 203 port map(
202 204 reset => reset,
@@ -206,7 +208,7 port map(
206 208 );
207 209
208 210
209 OP1REG : entity work.MAC_REG
211 OP1REG : MAC_REG
210 212 generic map(size => Input_SZ_A)
211 213 port map(
212 214 reset => reset,
@@ -216,7 +218,7 port map(
216 218 );
217 219
218 220
219 OP2REG : entity work.MAC_REG
221 OP2REG : MAC_REG
220 222 generic map(size => Input_SZ_B)
221 223 port map(
222 224 reset => reset,
@@ -226,7 +228,7 port map(
226 228 );
227 229
228 230
229 MULToutREG : entity work.MAC_REG
231 MULToutREG : MAC_REG
230 232 generic map(size => Input_SZ_A+Input_SZ_B)
231 233 port map(
232 234 reset => reset,
@@ -236,7 +238,7 port map(
236 238 );
237 239
238 240
239 MACMUXselREG : entity work.MAC_REG
241 MACMUXselREG : MAC_REG
240 242 generic map(size => 1)
241 243 port map(
242 244 reset => reset,
@@ -247,7 +249,7 port map(
247 249
248 250
249 251
250 MACMUX2selREG : entity work.MAC_REG
252 MACMUX2selREG : MAC_REG
251 253 generic map(size => 1)
252 254 port map(
253 255 reset => reset,
@@ -257,7 +259,7 port map(
257 259 );
258 260
259 261
260 MACMUX2selREG2 : entity work.MAC_REG
262 MACMUX2selREG2 : MAC_REG
261 263 generic map(size => 1)
262 264 port map(
263 265 reset => reset,
@@ -270,7 +272,7 port map(
270 272 --==============================================================
271 273 --======================M A C M U X ===========================
272 274 --==============================================================
273 MACMUX_inst : entity work.MAC_MUX
275 MACMUX_inst : MAC_MUX
274 276 generic map(
275 277 Input_SZ_A => Input_SZ_A+Input_SZ_B,
276 278 Input_SZ_B => Input_SZ_A+Input_SZ_B
@@ -293,7 +295,7 OP2_Resz <= std_logic_vector(resize(si
293 295 --==============================================================
294 296 --======================M A C M U X2 ==========================
295 297 --==============================================================
296 MAC_MUX2_inst : entity work.MAC_MUX2
298 MAC_MUX2_inst : MAC_MUX2
297 299 generic map(Input_SZ => Input_SZ_A+Input_SZ_B)
298 300 port map(
299 301 sel => MACMUX2sel_D_D,
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@@ -29,15 +29,16 entity Matrix is
29 29 generic(
30 30 Input_SZ : integer := 16);
31 31 port(
32 clk : in std_logic; --! Horloge du composant
33 raz : in std_logic; --! Reset general du composant
34 IN1 : in std_logic_vector(Input_SZ-1 downto 0); --! Donn�e d'entr�e
35 IN2 : in std_logic_vector(Input_SZ-1 downto 0); --! Donn�e d'entr�e
36 Take : in std_logic; --! Flag, op�rande r�cup�r�
37 Received : in std_logic; --! Flag, R�sultat bien ressu
38 Valid : out std_logic; --! Flag, R�sultat disponible
39 Read : out std_logic; --! Flag, op�rande disponible
40 Result : out std_logic_vector(2*Input_SZ-1 downto 0) --! R�sultat du calcul
32 clk : in std_logic; --! Horloge du composant
33 raz : in std_logic; --! Reset general du composant
34 IN1 : in std_logic_vector(Input_SZ-1 downto 0); --! Donn�e d'entr�e
35 IN2 : in std_logic_vector(Input_SZ-1 downto 0); --! Donn�e d'entr�e
36 Take : in std_logic; --! Flag, op�rande r�cup�r�
37 Received : in std_logic; --! Flag, R�sultat bien ressu
38 Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu�
39 Valid : out std_logic; --! Flag, R�sultat disponible
40 Read : out std_logic; --! Flag, op�rande disponible
41 Result : out std_logic_vector(2*Input_SZ-1 downto 0) --! R�sultat du calcul
41 42 );
42 43 end Matrix;
43 44
@@ -52,7 +53,7 begin
52 53
53 54 DRIVE : entity work.ALU_Driver
54 55 generic map(Input_SZ,Input_SZ)
55 port map(clk,raz,IN1,IN2,Take,Received,Valid,Read,CTRL,OP1,OP2);
56 port map(clk,raz,IN1,IN2,Take,Received,Conjugate,Valid,Read,CTRL,OP1,OP2);
56 57
57 58
58 59 ALU : entity work.ALU_v2
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@@ -47,19 +47,38 component APB_Matrix is
47 47 end component;
48 48
49 49
50 component SpectralMatrix is
51 generic(
52 Input_SZ : integer := 16;
53 Result_SZ : integer := 32);
54 port(
55 clk : in std_logic;
56 reset : in std_logic;
57 B1 : in std_logic_vector(Input_SZ-1 downto 0);
58 B2 : in std_logic_vector(Input_SZ-1 downto 0);
59 B3 : in std_logic_vector(Input_SZ-1 downto 0);
60 E1 : in std_logic_vector(Input_SZ-1 downto 0);
61 E2 : in std_logic_vector(Input_SZ-1 downto 0);
62 ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
63 Result : out std_logic_vector(Result_SZ-1 downto 0)
64 );
65 end component;
66
67
50 68 component Matrix is
51 69 generic(
52 70 Input_SZ : integer := 16);
53 71 port(
54 clk : in std_logic;
55 raz : in std_logic;
56 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
57 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
58 Take : in std_logic;
59 Received : in std_logic;
60 Valid : out std_logic;
61 Read : out std_logic;
62 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
72 clk : in std_logic;
73 raz : in std_logic;
74 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
75 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
76 Take : in std_logic;
77 Received : in std_logic;
78 Conjugate : in std_logic;
79 Valid : out std_logic;
80 Read : out std_logic;
81 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
63 82 );
64 83 end component;
65 84
@@ -69,17 +88,18 component ALU_Driver is
69 88 Input_SZ_1 : integer := 16;
70 89 Input_SZ_2 : integer := 16);
71 90 port(
72 clk : in std_logic;
73 reset : in std_logic;
74 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
75 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
76 Take : in std_logic;
77 Received : in std_logic;
78 Valid : out std_logic;
79 Read : out std_logic;
80 CTRL : out std_logic_vector(4 downto 0);
81 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
82 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
91 clk : in std_logic;
92 reset : in std_logic;
93 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
94 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
95 Take : in std_logic;
96 Received : in std_logic;
97 Conjugate : in std_logic;
98 Valid : out std_logic;
99 Read : out std_logic;
100 CTRL : out std_logic_vector(4 downto 0);
101 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
102 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
83 103 );
84 104 end component;
85 105
@@ -130,4 +150,40 port(
130 150 );
131 151 end component;
132 152
153
154 component GetResult is
155 generic(
156 Result_SZ : integer := 32);
157 port(
158 clk : in std_logic;
159 raz : in std_logic;
160 Valid : in std_logic;
161 Conjugate : in std_logic;
162 Res : in std_logic_vector(Result_SZ-1 downto 0);
163 Received : out std_logic;
164 Result : out std_logic_vector(Result_SZ-1 downto 0)
165 );
166 end component;
167
168
169 component SelectInputs is
170 generic(
171 Input_SZ : integer := 16);
172 port(
173 clk : in std_logic;
174 raz : in std_logic;
175 Read : in std_logic;
176 B1 : in std_logic_vector(Input_SZ-1 downto 0);
177 B2 : in std_logic_vector(Input_SZ-1 downto 0);
178 B3 : in std_logic_vector(Input_SZ-1 downto 0);
179 E1 : in std_logic_vector(Input_SZ-1 downto 0);
180 E2 : in std_logic_vector(Input_SZ-1 downto 0);
181 Conjugate : out std_logic;
182 Take : out std_logic;
183 ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
184 OP1 : out std_logic_vector(Input_SZ-1 downto 0);
185 OP2 : out std_logic_vector(Input_SZ-1 downto 0)
186 );
187 end component;
188
133 189 end; No newline at end of file
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@@ -28,7 +28,7 use grlib.devices.all;
28 28 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 use lpp.lpp_fifo.all;
31 use lpp.lpp_memory.all;
32 32
33 33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34 34
@@ -43,38 +43,41 entity APB_FifoRead is
43 43 Addr_sz : integer := 8;
44 44 addr_max_int : integer := 256);
45 45 port (
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
49 Flag_WR : in std_logic; --! Demande l'�criture dans la m�moire, g�r� hors de l'IP
50 Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'�criture dans la m�moire
51 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
49 WriteEnable : in std_logic; --! Demande de lecture de la m�moire, g�r� hors de l'IP
50 DATA : out std_logic_vector(Data_sz-1 downto 0); --! Donn�es en sortie de la m�moire
51 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
52 52 );
53 53 end APB_FifoRead;
54 54
55 --! @details Gestion de la FIFO uniquement en �criture
55 --! @details Gestion de la FIFO, �criture interne au FPGA, lecture via le bus APB
56 56
57 57 architecture ar_APB_FifoRead of APB_FifoRead is
58 58
59 signal Low : std_logic:='0';
59 60 signal ReadEnable : std_logic;
60 --signal WriteEnable : std_logic;
61 61 signal FlagEmpty : std_logic;
62 --signal FlagFull : std_logic;
62 signal FlagFull : std_logic;
63 signal ReUse : std_logic;
64 signal Lock : std_logic;
63 65 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
64 66 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
65 --signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
67 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
66 68 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
67 69
68 70 begin
69 71
70 72 APB : ApbDriver
71 73 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
72 port map(clk,rst,ReadEnable,open,FlagEmpty,open,DataIn,DataOut,open,AddrOut,apbi,apbo);
74 port map(clk,rst,ReadEnable,Low,FlagEmpty,FlagFull,ReUse,Lock,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
73 75
74 76
75 MEMORY_READ : Top_FifoRead
77 FIFO : Top_FIFO
76 78 generic map(Data_sz,Addr_sz,addr_max_int)
77 port map(clk,rst,ReadEnable,flag_WR,DataIn,Waddr,FlagEmpty,AddrOut,DataOut);
79 port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
78 80
81 DATA <= DataOut;
79 82
80 end ar_APB_FifoReade; No newline at end of file
83 end ar_APB_FifoRead; No newline at end of file
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@@ -28,7 +28,7 use grlib.devices.all;
28 28 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 use lpp.lpp_fifo.all;
31 use lpp.lpp_memory.all;
32 32
33 33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34 34
@@ -43,38 +43,41 entity APB_FifoWrite is
43 43 Addr_sz : integer := 8;
44 44 addr_max_int : integer := 256);
45 45 port (
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
49 Flag_RE : in std_logic; --! Demande de lecture de la m�moire, g�r� hors de l'IP
50 Raddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture dans la m�moire
51 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
49 ReadEnable : in std_logic; --! Demande de lecture de la m�moire, g�r� hors de l'IP
50 DATA : out std_logic_vector(Data_sz-1 downto 0); --! Donn�es en sortie de la m�moire
51 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
52 52 );
53 53 end APB_FifoWrite;
54 54
55 --! @details Gestion de la FIFO uniquement en lecture
55 --! @details Gestion de la FIFO, �criture via le bus APB, lecture interne au FPGA
56 56
57 57 architecture ar_APB_FifoWrite of APB_FifoWrite is
58 58
59 --signal ReadEnable : std_logic;
59 signal Low : std_logic:='0';
60 60 signal WriteEnable : std_logic;
61 --signal FlagEmpty : std_logic;
61 signal FlagEmpty : std_logic;
62 62 signal FlagFull : std_logic;
63 signal ReUse : std_logic;
64 signal Lock : std_logic;
63 65 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
64 66 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
65 67 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
66 --signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
68 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
67 69
68 70 begin
69 71
70 72 APB : ApbDriver
71 73 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
72 port map(clk,rst,open,WriteEnable,open,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
74 port map(clk,rst,Low,WriteEnable,FlagEmpty,FlagFull,ReUse,Lock,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
73 75
74 76
75 MEMORY_WRITE : Top_FifoWrite
77 FIFO : Top_FIFO
76 78 generic map(Data_sz,Addr_sz,addr_max_int)
77 port map(clk,rst,flag_RE,WriteEnable,DataIn,Raddr,FlagFull,AddrIn,DataOut);
79 port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
78 80
81 DATA <= DataOut;
79 82
80 83 end ar_APB_FifoWrite; No newline at end of file
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@@ -49,7 +49,8 entity ApbDriver is
49 49 WriteEnable : out std_logic; --! Instruction d'�criture en m�moire
50 50 FlagEmpty : in std_logic; --! Flag, M�moire vide
51 51 FlagFull : in std_logic; --! Flag, M�moire pleine
52 ReUse : out std_logic; --! Flag, Permet de relire la m�moire du d�but
52 ReUse : out std_logic; --! Flag, Permet de relire la m�moire du d�but
53 Lock : out std_logic; --! Flag, Permet de bloquer l'�criture dans la m�moire
53 54 DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en entr�e
54 55 DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en sortie
55 56 AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (�criture)
@@ -70,7 +71,7 constant pconfig : apb_config_type := (
70 71 1 => apb_iobar(paddr, pmask));
71 72
72 73 type DEVICE_ctrlr_Reg is record
73 DEVICE_Cfg : std_logic_vector(4 downto 0);
74 DEVICE_Cfg : std_logic_vector(5 downto 0);
74 75 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
75 76 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
76 77 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
@@ -90,6 +91,7 Rec.DEVICE_Cfg(1) <= FlagWR;
90 91 Rec.DEVICE_Cfg(2) <= FlagEmpty;
91 92 Rec.DEVICE_Cfg(3) <= FlagFull;
92 93 ReUse <= Rec.DEVICE_Cfg(4);
94 Lock <= Rec.DEVICE_Cfg(5);
93 95
94 96 DataIn <= Rec.DEVICE_DataW;
95 97 Rec.DEVICE_DataR <= DataOut;
@@ -105,6 +107,7 Rec.DEVICE_AddrR <= AddrOut;
105 107 FlagWR <= '0';
106 108 FlagRE <= '0';
107 109 Rec.DEVICE_Cfg(4) <= '0';
110 Rec.DEVICE_Cfg(5) <= '0';
108 111
109 112 elsif(clk'event and clk='1')then
110 113
@@ -116,6 +119,7 Rec.DEVICE_AddrR <= AddrOut;
116 119 Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
117 120 when "000010" =>
118 121 Rec.DEVICE_Cfg(4) <= apbi.pwdata(16);
122 Rec.DEVICE_Cfg(5) <= apbi.pwdata(20);
119 123 when others =>
120 124 null;
121 125 end case;
@@ -140,8 +144,9 Rec.DEVICE_AddrR <= AddrOut;
140 144 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
141 145 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
142 146 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
143 Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4);
144 Rdata(31 downto 20) <= X"CCC";
147 Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4);
148 Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5);
149 Rdata(31 downto 24) <= X"CC";
145 150 when others =>
146 151 Rdata <= (others => '0');
147 152 end case;
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@@ -72,7 +72,8 component ApbDriver is
72 72 WriteEnable : in std_logic;
73 73 FlagEmpty : in std_logic;
74 74 FlagFull : in std_logic;
75 ReUse : in std_logic;
75 ReUse : out std_logic;
76 Lock : out std_logic;
76 77 DataIn : out std_logic_vector(Data_sz-1 downto 0);
77 78 DataOut : in std_logic_vector(Data_sz-1 downto 0);
78 79 AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
@@ -94,6 +95,7 component Top_FIFO is
94 95 flag_RE : in std_logic;
95 96 flag_WR : in std_logic;
96 97 ReUse : in std_logic;
98 Lock : in std_logic;
97 99 Data_in : in std_logic_vector(Data_sz-1 downto 0);
98 100 Addr_RE : out std_logic_vector(addr_sz-1 downto 0);
99 101 Addr_WR : out std_logic_vector(addr_sz-1 downto 0);
@@ -167,29 +169,31 component APB_FifoWrite is
167 169 clk : in std_logic;
168 170 rst : in std_logic;
169 171 apbi : in apb_slv_in_type;
172 ReadEnable : in std_logic;
173 DATA : out std_logic_vector(Data_sz-1 downto 0);
170 174 apbo : out apb_slv_out_type
171 175 );
172 176 end component;
173 177
174 178
175 component Top_FifoWrite is
176 generic(
177 Data_sz : integer := 16;
178 Addr_sz : integer := 8;
179 addr_max_int : integer := 256);
180 port(
181 clk : in std_logic;
182 raz : in std_logic;
183 flag_RE : in std_logic;
184 flag_WR : in std_logic;
185 Data_in : in std_logic_vector(Data_sz-1 downto 0);
186 Raddr : in std_logic_vector(addr_sz-1 downto 0);
187 full : out std_logic;
188 empty : out std_logic;
189 Waddr : out std_logic_vector(addr_sz-1 downto 0);
190 Data_out : out std_logic_vector(Data_sz-1 downto 0)
191 );
192 end component;
179 --component Top_FifoWrite is
180 -- generic(
181 -- Data_sz : integer := 16;
182 -- Addr_sz : integer := 8;
183 -- addr_max_int : integer := 256);
184 -- port(
185 -- clk : in std_logic;
186 -- raz : in std_logic;
187 -- flag_RE : in std_logic;
188 -- flag_WR : in std_logic;
189 -- Data_in : in std_logic_vector(Data_sz-1 downto 0);
190 -- Raddr : in std_logic_vector(addr_sz-1 downto 0);
191 -- full : out std_logic;
192 -- empty : out std_logic;
193 -- Waddr : out std_logic_vector(addr_sz-1 downto 0);
194 -- Data_out : out std_logic_vector(Data_sz-1 downto 0)
195 -- );
196 --end component;
193 197
194 198 --===========================================================|
195 199 --================== Demi FIFO Lecture ======================|
@@ -209,28 +213,30 component APB_FifoRead is
209 213 clk : in std_logic;
210 214 rst : in std_logic;
211 215 apbi : in apb_slv_in_type;
216 WriteEnable : in std_logic;
217 DATA : out std_logic_vector(Data_sz-1 downto 0);
212 218 apbo : out apb_slv_out_type
213 219 );
214 220 end component;
215 221
216 222
217 component Top_FifoRead is
218 generic(
219 Data_sz : integer := 16;
220 Addr_sz : integer := 8;
221 addr_max_int : integer := 256);
222 port(
223 clk : in std_logic;
224 raz : in std_logic;
225 flag_RE : in std_logic;
226 flag_WR : in std_logic;
227 Data_in : in std_logic_vector(Data_sz-1 downto 0);
228 Waddr : in std_logic_vector(addr_sz-1 downto 0);
229 full : out std_logic;
230 empty : out std_logic;
231 Raddr : out std_logic_vector(addr_sz-1 downto 0);
232 Data_out : out std_logic_vector(Data_sz-1 downto 0)
233 );
234 end component;
223 --component Top_FifoRead is
224 -- generic(
225 -- Data_sz : integer := 16;
226 -- Addr_sz : integer := 8;
227 -- addr_max_int : integer := 256);
228 -- port(
229 -- clk : in std_logic;
230 -- raz : in std_logic;
231 -- flag_RE : in std_logic;
232 -- flag_WR : in std_logic;
233 -- Data_in : in std_logic_vector(Data_sz-1 downto 0);
234 -- Waddr : in std_logic_vector(addr_sz-1 downto 0);
235 -- full : out std_logic;
236 -- empty : out std_logic;
237 -- Raddr : out std_logic_vector(addr_sz-1 downto 0);
238 -- Data_out : out std_logic_vector(Data_sz-1 downto 0)
239 -- );
240 --end component;
235 241
236 242 end;
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