@@ -0,0 +1,86 | |||||
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1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Martin Morlot | |||
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
|
22 | library IEEE; | |||
|
23 | use IEEE.numeric_std.all; | |||
|
24 | use IEEE.std_logic_1164.all; | |||
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25 | ||||
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26 | entity GetResult is | |||
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27 | generic( | |||
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28 | Result_SZ : integer := 32); | |||
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29 | port( | |||
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30 | clk : in std_logic; | |||
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31 | raz : in std_logic; | |||
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32 | Valid : in std_logic; | |||
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33 | Conjugate : in std_logic; | |||
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34 | Res : in std_logic_vector(Result_SZ-1 downto 0); | |||
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35 | Received : out std_logic; | |||
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36 | Result : out std_logic_vector(Result_SZ-1 downto 0) | |||
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37 | ); | |||
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38 | end GetResult; | |||
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39 | ||||
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40 | ||||
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41 | architecture ar_GetResult of GetResult is | |||
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42 | ||||
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43 | signal Valid_reg : std_logic; | |||
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44 | ||||
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45 | type state is (st0,st1); | |||
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46 | signal ect : state; | |||
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47 | ||||
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48 | begin | |||
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49 | process(clk,raz) | |||
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50 | begin | |||
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51 | ||||
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52 | if(raz='0')then | |||
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53 | Received <= '0'; | |||
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54 | Valid_reg <= '0'; | |||
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55 | ect <= st0; | |||
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56 | Result <= (others => '0'); | |||
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57 | ||||
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58 | elsif(clk'event and clk='1')then | |||
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59 | Valid_reg <= Valid; | |||
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60 | ||||
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61 | case ect is | |||
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62 | when st0 => | |||
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63 | Received <= '0'; | |||
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64 | if(Valid_reg='0' and Valid='1')then | |||
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65 | Result <= Res; | |||
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66 | if(Conjugate='1')then | |||
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67 | Received <= '1'; | |||
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68 | ect <= st0; | |||
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69 | else | |||
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70 | ect <= st1; | |||
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71 | end if; | |||
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72 | end if; | |||
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73 | ||||
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74 | when st1 => | |||
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75 | Received <= '1'; | |||
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76 | if(Valid_reg='0' and Valid='1')then | |||
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77 | Result <= Res; | |||
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78 | ect <= st0; | |||
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79 | end if; | |||
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80 | ||||
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81 | end case; | |||
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82 | end if; | |||
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83 | end process; | |||
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84 | ||||
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85 | end ar_GetResult; | |||
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86 |
@@ -0,0 +1,359 | |||||
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1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Martin Morlot | |||
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
|
22 | library IEEE; | |||
|
23 | use IEEE.numeric_std.all; | |||
|
24 | use IEEE.std_logic_1164.all; | |||
|
25 | ||||
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26 | entity SelectInputs is | |||
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27 | generic( | |||
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28 | Input_SZ : integer := 16); | |||
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29 | port( | |||
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30 | clk : in std_logic; | |||
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31 | raz : in std_logic; | |||
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32 | Read : in std_logic; | |||
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33 | B1 : in std_logic_vector(Input_SZ-1 downto 0); | |||
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34 | B2 : in std_logic_vector(Input_SZ-1 downto 0); | |||
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35 | B3 : in std_logic_vector(Input_SZ-1 downto 0); | |||
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36 | E1 : in std_logic_vector(Input_SZ-1 downto 0); | |||
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37 | E2 : in std_logic_vector(Input_SZ-1 downto 0); | |||
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38 | Conjugate : out std_logic; | |||
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39 | Take : out std_logic; | |||
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40 | ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 | |||
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41 | OP1 : out std_logic_vector(Input_SZ-1 downto 0); | |||
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42 | OP2 : out std_logic_vector(Input_SZ-1 downto 0) | |||
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43 | ); | |||
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44 | end SelectInputs; | |||
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45 | ||||
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46 | ||||
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47 | architecture ar_SelectInputs of SelectInputs is | |||
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48 | ||||
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49 | signal Read_reg : std_logic; | |||
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50 | signal i : integer range 1 to 15; | |||
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51 | ||||
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52 | type state is (stX,st1a,st1b); | |||
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53 | signal ect : state; | |||
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54 | ||||
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55 | begin | |||
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56 | process(clk,raz) | |||
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57 | begin | |||
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58 | ||||
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59 | if(raz='0')then | |||
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60 | Take <= '0'; | |||
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61 | i <= 0; | |||
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62 | Read_reg <= '0'; | |||
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63 | ect <= stX; | |||
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64 | ||||
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65 | elsif(clk'event and clk='1')then | |||
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66 | Read_reg <= Read; | |||
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67 | ||||
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68 | case ect is | |||
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69 | when stX => | |||
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70 | i <= 1; | |||
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71 | if(Read_reg='0' and Read='1')then | |||
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72 | ect <= st1a; | |||
|
73 | end if; | |||
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74 | ------------------------------------------------------------------------------- | |||
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75 | when st1a => | |||
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76 | Take <= '1'; | |||
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77 | if(Read_reg='0' and Read='1')then | |||
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78 | ect <= st1b; | |||
|
79 | end if; | |||
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80 | ||||
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81 | when st1b => | |||
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82 | Take <= '0'; | |||
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83 | if(i=15)then | |||
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84 | ect <= stX; | |||
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85 | elsif(Read_reg='0' and Read='1')then | |||
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86 | i <= i+1; | |||
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87 | ect <= st1a; | |||
|
88 | end if; | |||
|
89 | ------------------------------------------------------------------------------- | |||
|
90 | -- when st2a => | |||
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91 | -- Take <= '1'; | |||
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92 | -- if(Read_reg='0' and Read='1')then | |||
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93 | -- ect <= st2b; | |||
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94 | -- end if; | |||
|
95 | -- | |||
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96 | -- when st2b => | |||
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97 | -- Take <= '0'; | |||
|
98 | -- if(Read_reg='0' and Read='1')then | |||
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99 | -- ect <= st3a; | |||
|
100 | -- end if; | |||
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101 | --------------------------------------------------------------------------------- | |||
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102 | -- when st3a => | |||
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103 | -- Take <= '1'; | |||
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104 | -- if(Read_reg='0' and Read='1')then | |||
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105 | -- ect <= st3b; | |||
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106 | -- end if; | |||
|
107 | -- | |||
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108 | -- when st3b => | |||
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109 | -- Take <= '0'; | |||
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110 | -- if(Read_reg='0' and Read='1')then | |||
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111 | -- ect <= st4a; | |||
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112 | -- end if; | |||
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113 | --------------------------------------------------------------------------------- | |||
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114 | -- when st4a => | |||
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115 | -- Take <= '1'; | |||
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116 | -- if(Read_reg='0' and Read='1')then | |||
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117 | -- ect <= st4b; | |||
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118 | -- end if; | |||
|
119 | -- | |||
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120 | -- when st4b => | |||
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121 | -- Take <= '0'; | |||
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122 | -- if(Read_reg='0' and Read='1')then | |||
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123 | -- ect <= st5a; | |||
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124 | -- end if; | |||
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125 | --------------------------------------------------------------------------------- | |||
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126 | -- | |||
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127 | -- when st5a => | |||
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128 | -- Take <= '1'; | |||
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129 | -- if(Read_reg='0' and Read='1')then | |||
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130 | -- ect <= st5b; | |||
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131 | -- end if; | |||
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132 | -- | |||
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133 | -- when st5b => | |||
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134 | -- Take <= '0'; | |||
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135 | -- if(Read_reg='0' and Read='1')then | |||
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136 | -- ect <= st6a; | |||
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137 | -- end if; | |||
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138 | --------------------------------------------------------------------------------- | |||
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139 | -- when st6a => | |||
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140 | -- Take <= '1'; | |||
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141 | -- if(Read_reg='0' and Read='1')then | |||
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142 | -- ect <= st6b; | |||
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143 | -- end if; | |||
|
144 | -- | |||
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145 | -- when st6b => | |||
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146 | -- Take <= '0'; | |||
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147 | -- if(Read_reg='0' and Read='1')then | |||
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148 | -- ect <= st7a; | |||
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149 | -- end if; | |||
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150 | --------------------------------------------------------------------------------- | |||
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151 | -- when st7a => | |||
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152 | -- Take <= '1'; | |||
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153 | -- if(Read_reg='0' and Read='1')then | |||
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154 | -- ect <= st7b; | |||
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155 | -- end if; | |||
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156 | -- | |||
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157 | -- when st7b => | |||
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158 | -- Take <= '0'; | |||
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159 | -- if(Read_reg='0' and Read='1')then | |||
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160 | -- ect <= st8a; | |||
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161 | -- end if; | |||
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162 | --------------------------------------------------------------------------------- | |||
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163 | -- when st8a => | |||
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164 | -- Take <= '1'; | |||
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165 | -- if(Read_reg='0' and Read='1')then | |||
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166 | -- ect <= st8b; | |||
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167 | -- end if; | |||
|
168 | -- | |||
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169 | -- when st8b => | |||
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170 | -- Take <= '0'; | |||
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171 | -- if(Read_reg='0' and Read='1')then | |||
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172 | -- ect <= st9a; | |||
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173 | -- end if; | |||
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174 | --------------------------------------------------------------------------------- | |||
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175 | -- when st9a => | |||
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176 | -- Take <= '1'; | |||
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177 | -- if(Read_reg='0' and Read='1')then | |||
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178 | -- ect <= st9b; | |||
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179 | -- end if; | |||
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180 | -- | |||
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181 | -- when st9b => | |||
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182 | -- Take <= '0'; | |||
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183 | -- if(Read_reg='0' and Read='1')then | |||
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184 | -- ect <= st10a; | |||
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185 | -- end if; | |||
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186 | --------------------------------------------------------------------------------- | |||
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187 | -- when st10a => | |||
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188 | -- Take <= '1'; | |||
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189 | -- if(Read_reg='0' and Read='1')then | |||
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190 | -- ect <= st10b; | |||
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191 | -- end if; | |||
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192 | -- | |||
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193 | -- when st10b => | |||
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194 | -- Take <= '0'; | |||
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195 | -- if(Read_reg='0' and Read='1')then | |||
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196 | -- ect <= st11a; | |||
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197 | -- end if; | |||
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198 | --------------------------------------------------------------------------------- | |||
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199 | -- when st11a => | |||
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200 | -- Take <= '1'; | |||
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201 | -- if(Read_reg='0' and Read='1')then | |||
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202 | -- ect <= st11b; | |||
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203 | -- end if; | |||
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204 | -- | |||
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205 | -- when st11b => | |||
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206 | -- Take <= '0'; | |||
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207 | -- if(Read_reg='0' and Read='1')then | |||
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208 | -- ect <= st12a; | |||
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209 | -- end if; | |||
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210 | --------------------------------------------------------------------------------- | |||
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211 | -- when st12a => | |||
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212 | -- Take <= '1'; | |||
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213 | -- if(Read_reg='0' and Read='1')then | |||
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214 | -- ect <= st12b; | |||
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215 | -- end if; | |||
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216 | -- | |||
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217 | -- when st12b => | |||
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218 | -- Take <= '0'; | |||
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219 | -- if(Read_reg='0' and Read='1')then | |||
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220 | -- ect <= st13a; | |||
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221 | -- end if; | |||
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222 | --------------------------------------------------------------------------------- | |||
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223 | -- when st13a => | |||
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224 | -- Take <= '1'; | |||
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225 | -- if(Read_reg='0' and Read='1')then | |||
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226 | -- ect <= st13b; | |||
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227 | -- end if; | |||
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228 | -- | |||
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229 | -- when st13b => | |||
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230 | -- Take <= '0'; | |||
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231 | -- if(Read_reg='0' and Read='1')then | |||
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232 | -- ect <= st14a; | |||
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233 | -- end if; | |||
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234 | --------------------------------------------------------------------------------- | |||
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235 | -- when st14a => | |||
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236 | -- Take <= '1'; | |||
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237 | -- if(Read_reg='0' and Read='1')then | |||
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238 | -- ect <= st14b; | |||
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239 | -- end if; | |||
|
240 | -- | |||
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241 | -- when st14b => | |||
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242 | -- Take <= '0'; | |||
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243 | -- if(Read_reg='0' and Read='1')then | |||
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244 | -- ect <= st15a; | |||
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245 | -- end if; | |||
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246 | --------------------------------------------------------------------------------- | |||
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247 | -- when st15a => | |||
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248 | -- Take <= '1'; | |||
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249 | -- if(Read_reg='0' and Read='1')then | |||
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250 | -- ect <= st7_b; | |||
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251 | -- end if; | |||
|
252 | -- | |||
|
253 | -- when st15b => | |||
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254 | -- Take <= '0'; | |||
|
255 | -- if(Read_reg='0' and Read='1')then | |||
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256 | -- ect <= stX; | |||
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257 | -- end if; | |||
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258 | ------------------------------------------------------------------------------- | |||
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259 | end case; | |||
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260 | end if; | |||
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261 | end process; | |||
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262 | ||||
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263 | with i select | |||
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264 | ReadFIFO <= "10000" when 1, | |||
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265 | "11000" when 2, | |||
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266 | "01000" when 3, | |||
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267 | "10100" when 4, | |||
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268 | "01100" when 5, | |||
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269 | "00100" when 6, | |||
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270 | "10010" when 7, | |||
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271 | "01010" when 8, | |||
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272 | "00110" when 9, | |||
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273 | "00010" when 10, | |||
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274 | "10001" when 11, | |||
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275 | "01001" when 12, | |||
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276 | "00101" when 13, | |||
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277 | "00011" when 14, | |||
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278 | "00001" when 15, | |||
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279 | "00000" when others; | |||
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280 | ||||
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281 | --with ect select | |||
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282 | -- ReadB2 <= Read when st1, | |||
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283 | -- Read when st2, | |||
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284 | -- Read when st4, | |||
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285 | -- Read when st7, | |||
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286 | -- Read when st11, | |||
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287 | -- '0' when others; | |||
|
288 | -- | |||
|
289 | --with ect select | |||
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290 | -- ReadB3 <= Read when st3, | |||
|
291 | -- Read when st4, | |||
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292 | -- Read when st5, | |||
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293 | -- Read when st8, | |||
|
294 | -- Read when st12, | |||
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295 | -- '0' when others; | |||
|
296 | -- | |||
|
297 | --with ect select | |||
|
298 | -- ReadE1 <= Read when st6, | |||
|
299 | -- Read when st7, | |||
|
300 | -- Read when st8, | |||
|
301 | -- Read when st9, | |||
|
302 | -- Read when st13, | |||
|
303 | -- '0' when others; | |||
|
304 | -- | |||
|
305 | --with ect select | |||
|
306 | -- ReadE2 <= Read when st10, | |||
|
307 | -- Read when st11, | |||
|
308 | -- Read when st12, | |||
|
309 | -- Read when st13, | |||
|
310 | -- Read when st14, | |||
|
311 | -- '0' when others; | |||
|
312 | ||||
|
313 | with i select | |||
|
314 | OP1 <= B1 when 1, | |||
|
315 | B1 when 2, | |||
|
316 | B1 when 4, | |||
|
317 | B1 when 7, | |||
|
318 | B1 when 11, | |||
|
319 | B2 when 3, | |||
|
320 | B2 when 5, | |||
|
321 | B2 when 8, | |||
|
322 | B2 when 12, | |||
|
323 | B3 when 6, | |||
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324 | B3 when 9, | |||
|
325 | B3 when 13, | |||
|
326 | E1 when 10, | |||
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327 | E1 when 14, | |||
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328 | E2 when 15, | |||
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329 | X"FFFF" when others; | |||
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330 | ||||
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331 | with i select | |||
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332 | OP2 <= B1 when 1, | |||
|
333 | B2 when 2, | |||
|
334 | B2 when 3, | |||
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335 | B3 when 4, | |||
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336 | B3 when 5, | |||
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337 | B3 when 6, | |||
|
338 | E1 when 7, | |||
|
339 | E1 when 8, | |||
|
340 | E1 when 9, | |||
|
341 | E1 when 10, | |||
|
342 | E2 when 11, | |||
|
343 | E2 when 12, | |||
|
344 | E2 when 13, | |||
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345 | E2 when 14, | |||
|
346 | E2 when 15, | |||
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347 | X"FFFF" when others; | |||
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348 | ||||
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349 | with i select | |||
|
350 | Conjugate <= '1' when 1, | |||
|
351 | '1' when 3, | |||
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352 | '1' when 6, | |||
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353 | '1' when 10, | |||
|
354 | '1' when 15, | |||
|
355 | '0' when others; | |||
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356 | ||||
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357 | ||||
|
358 | --RE_FIFO <= ReadE2 & ReadE1 & ReadB3 & ReadB2 & ReadB1; | |||
|
359 | end ar_SelectInputs; No newline at end of file |
@@ -0,0 +1,74 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Martin Morlot | |||
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
|
22 | library IEEE; | |||
|
23 | use IEEE.numeric_std.all; | |||
|
24 | use IEEE.std_logic_1164.all; | |||
|
25 | use lpp.lpp_matrix.all; | |||
|
26 | ||||
|
27 | entity SpectralMatrix is | |||
|
28 | generic( | |||
|
29 | Input_SZ : integer := 16; | |||
|
30 | Result_SZ : integer := 32); | |||
|
31 | port( | |||
|
32 | clk : in std_logic; | |||
|
33 | reset : in std_logic; | |||
|
34 | B1 : in std_logic_vector(Input_SZ-1 downto 0); | |||
|
35 | B2 : in std_logic_vector(Input_SZ-1 downto 0); | |||
|
36 | B3 : in std_logic_vector(Input_SZ-1 downto 0); | |||
|
37 | E1 : in std_logic_vector(Input_SZ-1 downto 0); | |||
|
38 | E2 : in std_logic_vector(Input_SZ-1 downto 0); | |||
|
39 | ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 | |||
|
40 | Result : out std_logic_vector(Result_SZ-1 downto 0) | |||
|
41 | ); | |||
|
42 | end SpectralMatrix; | |||
|
43 | ||||
|
44 | ||||
|
45 | architecture ar_SpectralMatrix of SpectralMatrix is | |||
|
46 | ||||
|
47 | signal Read : std_logic; | |||
|
48 | signal Take : std_logic; | |||
|
49 | signal Received : std_logic; | |||
|
50 | signal Valid : std_logic; | |||
|
51 | signal Conjugate : std_logic; | |||
|
52 | signal OP1 : std_logic_vector(Input_SZ-1 downto 0); | |||
|
53 | signal OP2 : std_logic_vector(Input_SZ-1 downto 0); | |||
|
54 | signal Resultat : std_logic_vector(Result_SZ-1 downto 0); | |||
|
55 | ||||
|
56 | begin | |||
|
57 | ||||
|
58 | ||||
|
59 | IN0 : SelectInputs | |||
|
60 | generic map(Input_SZ) | |||
|
61 | port map(clk,reset,Read,B1,B2,B3,E1,E2,Conjugate,Take,ReadFIFO,OP1,OP2); | |||
|
62 | ||||
|
63 | ||||
|
64 | CALC0 : Matrix | |||
|
65 | generic map(Input_SZ) | |||
|
66 | port map(clk,reset,OP1,OP2,Take,Received,Conjugate,Valid,Read,Resultat); | |||
|
67 | ||||
|
68 | ||||
|
69 | RES0 : GetResult | |||
|
70 | generic map(Result_SZ) | |||
|
71 | port map(clk,reset,Valid,Conjugate,Resultat,Received,Result); | |||
|
72 | ||||
|
73 | ||||
|
74 | end ar_SpectralMatrix; No newline at end of file |
@@ -30,17 +30,18 entity ALU_Driver is | |||||
30 | Input_SZ_1 : integer := 16; |
|
30 | Input_SZ_1 : integer := 16; | |
31 | Input_SZ_2 : integer := 16); |
|
31 | Input_SZ_2 : integer := 16); | |
32 | port( |
|
32 | port( | |
33 | clk : in std_logic; --! Horloge du composant |
|
33 | clk : in std_logic; --! Horloge du composant | |
34 | reset : in std_logic; --! Reset general du composant |
|
34 | reset : in std_logic; --! Reset general du composant | |
35 | IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Donn�e d'entr�e |
|
35 | IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Donn�e d'entr�e | |
36 | IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Donn�e d'entr�e |
|
36 | IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Donn�e d'entr�e | |
37 | Take : in std_logic; --! Flag, op�rande r�cup�r� |
|
37 | Take : in std_logic; --! Flag, op�rande r�cup�r� | |
38 | Received : in std_logic; --! Flag, R�sultat bien ressu |
|
38 | Received : in std_logic; --! Flag, R�sultat bien ressu | |
39 |
|
|
39 | Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu� | |
40 |
|
|
40 | Valid : out std_logic; --! Flag, R�sultat disponible | |
41 | CTRL : out std_logic_vector(4 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e |
|
41 | Read : out std_logic; --! Flag, op�rande disponible | |
42 |
|
|
42 | CTRL : out std_logic_vector(4 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e | |
43 |
OP |
|
43 | OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande | |
|
44 | OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second Op�rande | |||
44 | ); |
|
45 | ); | |
45 | end ALU_Driver; |
|
46 | end ALU_Driver; | |
46 |
|
47 | |||
@@ -66,13 +67,13 begin | |||||
66 | begin |
|
67 | begin | |
67 |
|
68 | |||
68 | if(reset='0')then |
|
69 | if(reset='0')then | |
69 | ect <= eX; |
|
70 | ect <= eX; | |
70 | st <= e0; |
|
71 | st <= e0; | |
71 | go_st <= '0'; |
|
72 | go_st <= '0'; | |
72 | CTRL <= "10000"; |
|
73 | CTRL <= "10000"; | |
73 | Read <= '0'; |
|
74 | Read <= '0'; | |
74 | Valid <= '0'; |
|
75 | Valid <= '0'; | |
75 | Take_reg <= '0'; |
|
76 | Take_reg <= '0'; | |
76 | Received_reg <= '0'; |
|
77 | Received_reg <= '0'; | |
77 |
|
78 | |||
78 | elsif(clk'event and clk='1')then |
|
79 | elsif(clk'event and clk='1')then | |
@@ -120,7 +121,11 begin | |||||
120 | CTRL <= "00000"; |
|
121 | CTRL <= "00000"; | |
121 | go_st <= '1'; |
|
122 | go_st <= '1'; | |
122 | if(Received_reg='0' and Received='1')then |
|
123 | if(Received_reg='0' and Received='1')then | |
123 |
e |
|
124 | if(Conjugate='1')then | |
|
125 | ect <= eX; | |||
|
126 | else | |||
|
127 | ect <= e3; | |||
|
128 | end if; | |||
124 | end if; |
|
129 | end if; | |
125 |
|
130 | |||
126 | when e3 => |
|
131 | when e3 => | |
@@ -147,7 +152,7 begin | |||||
147 | ect <= eX; |
|
152 | ect <= eX; | |
148 | end if; |
|
153 | end if; | |
149 | end case; |
|
154 | end case; | |
150 |
|
155 | --------------------------------------------------------------------------------- | ||
151 | case st is |
|
156 | case st is | |
152 | when e0 => |
|
157 | when e0 => | |
153 | if(go_st='1')then |
|
158 | if(go_st='1')then | |
@@ -160,8 +165,12 begin | |||||
160 |
|
165 | |||
161 | when e2 => |
|
166 | when e2 => | |
162 | if(Received_reg='0' and Received='1')then |
|
167 | if(Received_reg='0' and Received='1')then | |
163 |
Valid <= '0'; |
|
168 | Valid <= '0'; | |
164 |
|
|
169 | if(Conjugate='1')then | |
|
170 | st <= idle2; | |||
|
171 | else | |||
|
172 | st <= idle; | |||
|
173 | end if; | |||
165 | end if; |
|
174 | end if; | |
166 |
|
175 | |||
167 | when idle => |
|
176 | when idle => |
@@ -22,6 +22,7 | |||||
22 | library IEEE; |
|
22 | library IEEE; | |
23 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
24 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
|
25 | use lpp.lpp_matrix.all; | |||
25 |
|
26 | |||
26 | --! Une ALU : Arithmetic and logical unit, permettant de r�aliser une ou plusieurs op�ration |
|
27 | --! Une ALU : Arithmetic and logical unit, permettant de r�aliser une ou plusieurs op�ration | |
27 |
|
28 | |||
@@ -58,7 +59,7 begin | |||||
58 | clr_MAC <= '1' when ctrl = "10000" else '0'; |
|
59 | clr_MAC <= '1' when ctrl = "10000" else '0'; | |
59 |
|
60 | |||
60 | arith : if Arith_en = 1 generate |
|
61 | arith : if Arith_en = 1 generate | |
61 |
MACinst : |
|
62 | MACinst : MAC_v2 | |
62 | generic map(Input_SZ_1,Input_SZ_2) |
|
63 | generic map(Input_SZ_1,Input_SZ_2) | |
63 | port map(clk,reset,clr_MAC,ctrl(3 downto 0),OP1,OP2,RES); |
|
64 | port map(clk,reset,clr_MAC,ctrl(3 downto 0),OP1,OP2,RES); | |
64 | end generate; |
|
65 | end generate; |
@@ -22,6 +22,8 | |||||
22 | library IEEE; |
|
22 | library IEEE; | |
23 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
24 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
|
25 | use lpp.lpp_matrix.all; | |||
|
26 | use lpp.general_purpose.all; | |||
25 |
|
27 | |||
26 | --! Un MAC : Multiplier Accumulator Chip |
|
28 | --! Un MAC : Multiplier Accumulator Chip | |
27 |
|
29 | |||
@@ -79,7 +81,7 begin | |||||
79 | --============================================================== |
|
81 | --============================================================== | |
80 | --=============M A C C O N T R O L E R========================= |
|
82 | --=============M A C C O N T R O L E R========================= | |
81 | --============================================================== |
|
83 | --============================================================== | |
82 |
MAC_CONTROLER1 : |
|
84 | MAC_CONTROLER1 : MAC_CONTROLER | |
83 | port map( |
|
85 | port map( | |
84 | ctrl => MAC_MUL_ADD_2C_D(1 downto 0), |
|
86 | ctrl => MAC_MUL_ADD_2C_D(1 downto 0), | |
85 | MULT => mult, |
|
87 | MULT => mult, | |
@@ -96,7 +98,7 port map( | |||||
96 | --============================================================== |
|
98 | --============================================================== | |
97 | --=============M U L T I P L I E R============================== |
|
99 | --=============M U L T I P L I E R============================== | |
98 | --============================================================== |
|
100 | --============================================================== | |
99 |
Multiplieri_nst : |
|
101 | Multiplieri_nst : Multiplier | |
100 | generic map( |
|
102 | generic map( | |
101 | Input_SZ_A => Input_SZ_A, |
|
103 | Input_SZ_A => Input_SZ_A, | |
102 | Input_SZ_B => Input_SZ_B |
|
104 | Input_SZ_B => Input_SZ_B | |
@@ -118,7 +120,7 port map( | |||||
118 | --============================================================== |
|
120 | --============================================================== | |
119 | --======================A D D E R ============================== |
|
121 | --======================A D D E R ============================== | |
120 | --============================================================== |
|
122 | --============================================================== | |
121 |
adder_inst : |
|
123 | adder_inst : Adder | |
122 | generic map( |
|
124 | generic map( | |
123 | Input_SZ_A => Input_SZ_A+Input_SZ_B, |
|
125 | Input_SZ_A => Input_SZ_A+Input_SZ_B, | |
124 | Input_SZ_B => Input_SZ_A+Input_SZ_B |
|
126 | Input_SZ_B => Input_SZ_A+Input_SZ_B | |
@@ -141,7 +143,7 port map( | |||||
141 | --============================================================== |
|
143 | --============================================================== | |
142 | --===================TWO COMPLEMENTERS========================== |
|
144 | --===================TWO COMPLEMENTERS========================== | |
143 | --============================================================== |
|
145 | --============================================================== | |
144 |
TWO_COMPLEMENTER1 : |
|
146 | TWO_COMPLEMENTER1 : TwoComplementer | |
145 | generic map( |
|
147 | generic map( | |
146 | Input_SZ => Input_SZ_A |
|
148 | Input_SZ => Input_SZ_A | |
147 | ) |
|
149 | ) | |
@@ -155,7 +157,7 port map( | |||||
155 | ); |
|
157 | ); | |
156 |
|
158 | |||
157 |
|
159 | |||
158 |
TWO_COMPLEMENTER2 : |
|
160 | TWO_COMPLEMENTER2 : TwoComplementer | |
159 | generic map( |
|
161 | generic map( | |
160 | Input_SZ => Input_SZ_B |
|
162 | Input_SZ => Input_SZ_B | |
161 | ) |
|
163 | ) | |
@@ -169,7 +171,7 port map( | |||||
169 | ); |
|
171 | ); | |
170 | --============================================================== |
|
172 | --============================================================== | |
171 |
|
173 | |||
172 |
CTRL : |
|
174 | CTRL : MAC_REG | |
173 | generic map(size => 2) |
|
175 | generic map(size => 2) | |
174 | port map( |
|
176 | port map( | |
175 | reset => reset, |
|
177 | reset => reset, | |
@@ -178,7 +180,7 port map( | |||||
178 | Q => MAC_MUL_ADD_2C_D(1 downto 0) |
|
180 | Q => MAC_MUL_ADD_2C_D(1 downto 0) | |
179 | ); |
|
181 | ); | |
180 |
|
182 | |||
181 |
clr_MACREG1 : |
|
183 | clr_MACREG1 : MAC_REG | |
182 | generic map(size => 1) |
|
184 | generic map(size => 1) | |
183 | port map( |
|
185 | port map( | |
184 | reset => reset, |
|
186 | reset => reset, | |
@@ -187,7 +189,7 port map( | |||||
187 | Q(0) => clr_MAC_D |
|
189 | Q(0) => clr_MAC_D | |
188 | ); |
|
190 | ); | |
189 |
|
191 | |||
190 |
clr_MACREG2 : |
|
192 | clr_MACREG2 : MAC_REG | |
191 | generic map(size => 1) |
|
193 | generic map(size => 1) | |
192 | port map( |
|
194 | port map( | |
193 | reset => reset, |
|
195 | reset => reset, | |
@@ -196,7 +198,7 port map( | |||||
196 | Q(0) => clr_MAC_D_D |
|
198 | Q(0) => clr_MAC_D_D | |
197 | ); |
|
199 | ); | |
198 |
|
200 | |||
199 |
addREG : |
|
201 | addREG : MAC_REG | |
200 | generic map(size => 1) |
|
202 | generic map(size => 1) | |
201 | port map( |
|
203 | port map( | |
202 | reset => reset, |
|
204 | reset => reset, | |
@@ -206,7 +208,7 port map( | |||||
206 | ); |
|
208 | ); | |
207 |
|
209 | |||
208 |
|
210 | |||
209 |
OP1REG : |
|
211 | OP1REG : MAC_REG | |
210 | generic map(size => Input_SZ_A) |
|
212 | generic map(size => Input_SZ_A) | |
211 | port map( |
|
213 | port map( | |
212 | reset => reset, |
|
214 | reset => reset, | |
@@ -216,7 +218,7 port map( | |||||
216 | ); |
|
218 | ); | |
217 |
|
219 | |||
218 |
|
220 | |||
219 |
OP2REG : |
|
221 | OP2REG : MAC_REG | |
220 | generic map(size => Input_SZ_B) |
|
222 | generic map(size => Input_SZ_B) | |
221 | port map( |
|
223 | port map( | |
222 | reset => reset, |
|
224 | reset => reset, | |
@@ -226,7 +228,7 port map( | |||||
226 | ); |
|
228 | ); | |
227 |
|
229 | |||
228 |
|
230 | |||
229 |
MULToutREG : |
|
231 | MULToutREG : MAC_REG | |
230 | generic map(size => Input_SZ_A+Input_SZ_B) |
|
232 | generic map(size => Input_SZ_A+Input_SZ_B) | |
231 | port map( |
|
233 | port map( | |
232 | reset => reset, |
|
234 | reset => reset, | |
@@ -236,7 +238,7 port map( | |||||
236 | ); |
|
238 | ); | |
237 |
|
239 | |||
238 |
|
240 | |||
239 |
MACMUXselREG : |
|
241 | MACMUXselREG : MAC_REG | |
240 | generic map(size => 1) |
|
242 | generic map(size => 1) | |
241 | port map( |
|
243 | port map( | |
242 | reset => reset, |
|
244 | reset => reset, | |
@@ -247,7 +249,7 port map( | |||||
247 |
|
249 | |||
248 |
|
250 | |||
249 |
|
251 | |||
250 |
MACMUX2selREG : |
|
252 | MACMUX2selREG : MAC_REG | |
251 | generic map(size => 1) |
|
253 | generic map(size => 1) | |
252 | port map( |
|
254 | port map( | |
253 | reset => reset, |
|
255 | reset => reset, | |
@@ -257,7 +259,7 port map( | |||||
257 | ); |
|
259 | ); | |
258 |
|
260 | |||
259 |
|
261 | |||
260 |
MACMUX2selREG2 : |
|
262 | MACMUX2selREG2 : MAC_REG | |
261 | generic map(size => 1) |
|
263 | generic map(size => 1) | |
262 | port map( |
|
264 | port map( | |
263 | reset => reset, |
|
265 | reset => reset, | |
@@ -270,7 +272,7 port map( | |||||
270 | --============================================================== |
|
272 | --============================================================== | |
271 | --======================M A C M U X =========================== |
|
273 | --======================M A C M U X =========================== | |
272 | --============================================================== |
|
274 | --============================================================== | |
273 |
MACMUX_inst : |
|
275 | MACMUX_inst : MAC_MUX | |
274 | generic map( |
|
276 | generic map( | |
275 | Input_SZ_A => Input_SZ_A+Input_SZ_B, |
|
277 | Input_SZ_A => Input_SZ_A+Input_SZ_B, | |
276 | Input_SZ_B => Input_SZ_A+Input_SZ_B |
|
278 | Input_SZ_B => Input_SZ_A+Input_SZ_B | |
@@ -293,7 +295,7 OP2_Resz <= std_logic_vector(resize(si | |||||
293 | --============================================================== |
|
295 | --============================================================== | |
294 | --======================M A C M U X2 ========================== |
|
296 | --======================M A C M U X2 ========================== | |
295 | --============================================================== |
|
297 | --============================================================== | |
296 |
MAC_MUX2_inst : |
|
298 | MAC_MUX2_inst : MAC_MUX2 | |
297 | generic map(Input_SZ => Input_SZ_A+Input_SZ_B) |
|
299 | generic map(Input_SZ => Input_SZ_A+Input_SZ_B) | |
298 | port map( |
|
300 | port map( | |
299 | sel => MACMUX2sel_D_D, |
|
301 | sel => MACMUX2sel_D_D, |
@@ -29,15 +29,16 entity Matrix is | |||||
29 | generic( |
|
29 | generic( | |
30 | Input_SZ : integer := 16); |
|
30 | Input_SZ : integer := 16); | |
31 | port( |
|
31 | port( | |
32 | clk : in std_logic; --! Horloge du composant |
|
32 | clk : in std_logic; --! Horloge du composant | |
33 | raz : in std_logic; --! Reset general du composant |
|
33 | raz : in std_logic; --! Reset general du composant | |
34 | IN1 : in std_logic_vector(Input_SZ-1 downto 0); --! Donn�e d'entr�e |
|
34 | IN1 : in std_logic_vector(Input_SZ-1 downto 0); --! Donn�e d'entr�e | |
35 | IN2 : in std_logic_vector(Input_SZ-1 downto 0); --! Donn�e d'entr�e |
|
35 | IN2 : in std_logic_vector(Input_SZ-1 downto 0); --! Donn�e d'entr�e | |
36 | Take : in std_logic; --! Flag, op�rande r�cup�r� |
|
36 | Take : in std_logic; --! Flag, op�rande r�cup�r� | |
37 | Received : in std_logic; --! Flag, R�sultat bien ressu |
|
37 | Received : in std_logic; --! Flag, R�sultat bien ressu | |
38 |
|
|
38 | Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu� | |
39 |
|
|
39 | Valid : out std_logic; --! Flag, R�sultat disponible | |
40 | Result : out std_logic_vector(2*Input_SZ-1 downto 0) --! R�sultat du calcul |
|
40 | Read : out std_logic; --! Flag, op�rande disponible | |
|
41 | Result : out std_logic_vector(2*Input_SZ-1 downto 0) --! R�sultat du calcul | |||
41 | ); |
|
42 | ); | |
42 | end Matrix; |
|
43 | end Matrix; | |
43 |
|
44 | |||
@@ -52,7 +53,7 begin | |||||
52 |
|
53 | |||
53 | DRIVE : entity work.ALU_Driver |
|
54 | DRIVE : entity work.ALU_Driver | |
54 | generic map(Input_SZ,Input_SZ) |
|
55 | generic map(Input_SZ,Input_SZ) | |
55 | port map(clk,raz,IN1,IN2,Take,Received,Valid,Read,CTRL,OP1,OP2); |
|
56 | port map(clk,raz,IN1,IN2,Take,Received,Conjugate,Valid,Read,CTRL,OP1,OP2); | |
56 |
|
57 | |||
57 |
|
58 | |||
58 | ALU : entity work.ALU_v2 |
|
59 | ALU : entity work.ALU_v2 |
@@ -47,19 +47,38 component APB_Matrix is | |||||
47 | end component; |
|
47 | end component; | |
48 |
|
48 | |||
49 |
|
49 | |||
|
50 | component SpectralMatrix is | |||
|
51 | generic( | |||
|
52 | Input_SZ : integer := 16; | |||
|
53 | Result_SZ : integer := 32); | |||
|
54 | port( | |||
|
55 | clk : in std_logic; | |||
|
56 | reset : in std_logic; | |||
|
57 | B1 : in std_logic_vector(Input_SZ-1 downto 0); | |||
|
58 | B2 : in std_logic_vector(Input_SZ-1 downto 0); | |||
|
59 | B3 : in std_logic_vector(Input_SZ-1 downto 0); | |||
|
60 | E1 : in std_logic_vector(Input_SZ-1 downto 0); | |||
|
61 | E2 : in std_logic_vector(Input_SZ-1 downto 0); | |||
|
62 | ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 | |||
|
63 | Result : out std_logic_vector(Result_SZ-1 downto 0) | |||
|
64 | ); | |||
|
65 | end component; | |||
|
66 | ||||
|
67 | ||||
50 | component Matrix is |
|
68 | component Matrix is | |
51 | generic( |
|
69 | generic( | |
52 | Input_SZ : integer := 16); |
|
70 | Input_SZ : integer := 16); | |
53 | port( |
|
71 | port( | |
54 | clk : in std_logic; |
|
72 | clk : in std_logic; | |
55 | raz : in std_logic; |
|
73 | raz : in std_logic; | |
56 | IN1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
74 | IN1 : in std_logic_vector(Input_SZ-1 downto 0); | |
57 | IN2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
75 | IN2 : in std_logic_vector(Input_SZ-1 downto 0); | |
58 | Take : in std_logic; |
|
76 | Take : in std_logic; | |
59 | Received : in std_logic; |
|
77 | Received : in std_logic; | |
60 |
|
|
78 | Conjugate : in std_logic; | |
61 |
|
|
79 | Valid : out std_logic; | |
62 | Result : out std_logic_vector(2*Input_SZ-1 downto 0) |
|
80 | Read : out std_logic; | |
|
81 | Result : out std_logic_vector(2*Input_SZ-1 downto 0) | |||
63 | ); |
|
82 | ); | |
64 | end component; |
|
83 | end component; | |
65 |
|
84 | |||
@@ -69,17 +88,18 component ALU_Driver is | |||||
69 | Input_SZ_1 : integer := 16; |
|
88 | Input_SZ_1 : integer := 16; | |
70 | Input_SZ_2 : integer := 16); |
|
89 | Input_SZ_2 : integer := 16); | |
71 | port( |
|
90 | port( | |
72 | clk : in std_logic; |
|
91 | clk : in std_logic; | |
73 | reset : in std_logic; |
|
92 | reset : in std_logic; | |
74 | IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); |
|
93 | IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); | |
75 | IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); |
|
94 | IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); | |
76 | Take : in std_logic; |
|
95 | Take : in std_logic; | |
77 | Received : in std_logic; |
|
96 | Received : in std_logic; | |
78 |
|
|
97 | Conjugate : in std_logic; | |
79 |
|
|
98 | Valid : out std_logic; | |
80 |
|
|
99 | Read : out std_logic; | |
81 |
|
|
100 | CTRL : out std_logic_vector(4 downto 0); | |
82 |
OP |
|
101 | OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); | |
|
102 | OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) | |||
83 | ); |
|
103 | ); | |
84 | end component; |
|
104 | end component; | |
85 |
|
105 | |||
@@ -130,4 +150,40 port( | |||||
130 | ); |
|
150 | ); | |
131 | end component; |
|
151 | end component; | |
132 |
|
152 | |||
|
153 | ||||
|
154 | component GetResult is | |||
|
155 | generic( | |||
|
156 | Result_SZ : integer := 32); | |||
|
157 | port( | |||
|
158 | clk : in std_logic; | |||
|
159 | raz : in std_logic; | |||
|
160 | Valid : in std_logic; | |||
|
161 | Conjugate : in std_logic; | |||
|
162 | Res : in std_logic_vector(Result_SZ-1 downto 0); | |||
|
163 | Received : out std_logic; | |||
|
164 | Result : out std_logic_vector(Result_SZ-1 downto 0) | |||
|
165 | ); | |||
|
166 | end component; | |||
|
167 | ||||
|
168 | ||||
|
169 | component SelectInputs is | |||
|
170 | generic( | |||
|
171 | Input_SZ : integer := 16); | |||
|
172 | port( | |||
|
173 | clk : in std_logic; | |||
|
174 | raz : in std_logic; | |||
|
175 | Read : in std_logic; | |||
|
176 | B1 : in std_logic_vector(Input_SZ-1 downto 0); | |||
|
177 | B2 : in std_logic_vector(Input_SZ-1 downto 0); | |||
|
178 | B3 : in std_logic_vector(Input_SZ-1 downto 0); | |||
|
179 | E1 : in std_logic_vector(Input_SZ-1 downto 0); | |||
|
180 | E2 : in std_logic_vector(Input_SZ-1 downto 0); | |||
|
181 | Conjugate : out std_logic; | |||
|
182 | Take : out std_logic; | |||
|
183 | ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 | |||
|
184 | OP1 : out std_logic_vector(Input_SZ-1 downto 0); | |||
|
185 | OP2 : out std_logic_vector(Input_SZ-1 downto 0) | |||
|
186 | ); | |||
|
187 | end component; | |||
|
188 | ||||
133 | end; No newline at end of file |
|
189 | end; |
@@ -28,7 +28,7 use grlib.devices.all; | |||||
28 | library lpp; |
|
28 | library lpp; | |
29 | use lpp.lpp_amba.all; |
|
29 | use lpp.lpp_amba.all; | |
30 | use lpp.apb_devices_list.all; |
|
30 | use lpp.apb_devices_list.all; | |
31 |
use lpp.lpp_ |
|
31 | use lpp.lpp_memory.all; | |
32 |
|
32 | |||
33 | --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba |
|
33 | --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba | |
34 |
|
34 | |||
@@ -43,38 +43,41 entity APB_FifoRead is | |||||
43 | Addr_sz : integer := 8; |
|
43 | Addr_sz : integer := 8; | |
44 | addr_max_int : integer := 256); |
|
44 | addr_max_int : integer := 256); | |
45 | port ( |
|
45 | port ( | |
46 | clk : in std_logic; --! Horloge du composant |
|
46 | clk : in std_logic; --! Horloge du composant | |
47 | rst : in std_logic; --! Reset general du composant |
|
47 | rst : in std_logic; --! Reset general du composant | |
48 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus |
|
48 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus | |
49 |
|
|
49 | WriteEnable : in std_logic; --! Demande de lecture de la m�moire, g�r� hors de l'IP | |
50 |
|
|
50 | DATA : out std_logic_vector(Data_sz-1 downto 0); --! Donn�es en sortie de la m�moire | |
51 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus |
|
51 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus | |
52 | ); |
|
52 | ); | |
53 | end APB_FifoRead; |
|
53 | end APB_FifoRead; | |
54 |
|
54 | |||
55 | --! @details Gestion de la FIFO uniquement en �criture |
|
55 | --! @details Gestion de la FIFO, �criture interne au FPGA, lecture via le bus APB | |
56 |
|
56 | |||
57 | architecture ar_APB_FifoRead of APB_FifoRead is |
|
57 | architecture ar_APB_FifoRead of APB_FifoRead is | |
58 |
|
58 | |||
|
59 | signal Low : std_logic:='0'; | |||
59 | signal ReadEnable : std_logic; |
|
60 | signal ReadEnable : std_logic; | |
60 | --signal WriteEnable : std_logic; |
|
|||
61 | signal FlagEmpty : std_logic; |
|
61 | signal FlagEmpty : std_logic; | |
62 |
|
|
62 | signal FlagFull : std_logic; | |
|
63 | signal ReUse : std_logic; | |||
|
64 | signal Lock : std_logic; | |||
63 | signal DataIn : std_logic_vector(Data_sz-1 downto 0); |
|
65 | signal DataIn : std_logic_vector(Data_sz-1 downto 0); | |
64 | signal DataOut : std_logic_vector(Data_sz-1 downto 0); |
|
66 | signal DataOut : std_logic_vector(Data_sz-1 downto 0); | |
65 |
|
|
67 | signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); | |
66 | signal AddrOut : std_logic_vector(Addr_sz-1 downto 0); |
|
68 | signal AddrOut : std_logic_vector(Addr_sz-1 downto 0); | |
67 |
|
69 | |||
68 | begin |
|
70 | begin | |
69 |
|
71 | |||
70 | APB : ApbDriver |
|
72 | APB : ApbDriver | |
71 | generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) |
|
73 | generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) | |
72 |
port map(clk,rst,ReadEnable, |
|
74 | port map(clk,rst,ReadEnable,Low,FlagEmpty,FlagFull,ReUse,Lock,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); | |
73 |
|
75 | |||
74 |
|
76 | |||
75 | MEMORY_READ : Top_FifoRead |
|
77 | FIFO : Top_FIFO | |
76 | generic map(Data_sz,Addr_sz,addr_max_int) |
|
78 | generic map(Data_sz,Addr_sz,addr_max_int) | |
77 |
port map(clk,rst,ReadEnable, |
|
79 | port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); | |
78 |
|
80 | |||
|
81 | DATA <= DataOut; | |||
79 |
|
82 | |||
80 |
end ar_APB_FifoRead |
|
83 | end ar_APB_FifoRead; No newline at end of file |
@@ -28,7 +28,7 use grlib.devices.all; | |||||
28 | library lpp; |
|
28 | library lpp; | |
29 | use lpp.lpp_amba.all; |
|
29 | use lpp.lpp_amba.all; | |
30 | use lpp.apb_devices_list.all; |
|
30 | use lpp.apb_devices_list.all; | |
31 |
use lpp.lpp_ |
|
31 | use lpp.lpp_memory.all; | |
32 |
|
32 | |||
33 | --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba |
|
33 | --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba | |
34 |
|
34 | |||
@@ -43,38 +43,41 entity APB_FifoWrite is | |||||
43 | Addr_sz : integer := 8; |
|
43 | Addr_sz : integer := 8; | |
44 | addr_max_int : integer := 256); |
|
44 | addr_max_int : integer := 256); | |
45 | port ( |
|
45 | port ( | |
46 | clk : in std_logic; --! Horloge du composant |
|
46 | clk : in std_logic; --! Horloge du composant | |
47 | rst : in std_logic; --! Reset general du composant |
|
47 | rst : in std_logic; --! Reset general du composant | |
48 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus |
|
48 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus | |
49 |
|
|
49 | ReadEnable : in std_logic; --! Demande de lecture de la m�moire, g�r� hors de l'IP | |
50 |
|
|
50 | DATA : out std_logic_vector(Data_sz-1 downto 0); --! Donn�es en sortie de la m�moire | |
51 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus |
|
51 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus | |
52 | ); |
|
52 | ); | |
53 | end APB_FifoWrite; |
|
53 | end APB_FifoWrite; | |
54 |
|
54 | |||
55 |
--! @details Gestion de la FIFO |
|
55 | --! @details Gestion de la FIFO, �criture via le bus APB, lecture interne au FPGA | |
56 |
|
56 | |||
57 | architecture ar_APB_FifoWrite of APB_FifoWrite is |
|
57 | architecture ar_APB_FifoWrite of APB_FifoWrite is | |
58 |
|
58 | |||
59 | --signal ReadEnable : std_logic; |
|
59 | signal Low : std_logic:='0'; | |
60 | signal WriteEnable : std_logic; |
|
60 | signal WriteEnable : std_logic; | |
61 |
|
|
61 | signal FlagEmpty : std_logic; | |
62 | signal FlagFull : std_logic; |
|
62 | signal FlagFull : std_logic; | |
|
63 | signal ReUse : std_logic; | |||
|
64 | signal Lock : std_logic; | |||
63 | signal DataIn : std_logic_vector(Data_sz-1 downto 0); |
|
65 | signal DataIn : std_logic_vector(Data_sz-1 downto 0); | |
64 | signal DataOut : std_logic_vector(Data_sz-1 downto 0); |
|
66 | signal DataOut : std_logic_vector(Data_sz-1 downto 0); | |
65 | signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); |
|
67 | signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); | |
66 |
|
|
68 | signal AddrOut : std_logic_vector(Addr_sz-1 downto 0); | |
67 |
|
69 | |||
68 | begin |
|
70 | begin | |
69 |
|
71 | |||
70 | APB : ApbDriver |
|
72 | APB : ApbDriver | |
71 | generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) |
|
73 | generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) | |
72 |
port map(clk,rst, |
|
74 | port map(clk,rst,Low,WriteEnable,FlagEmpty,FlagFull,ReUse,Lock,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); | |
73 |
|
75 | |||
74 |
|
76 | |||
75 | MEMORY_WRITE : Top_FifoWrite |
|
77 | FIFO : Top_FIFO | |
76 | generic map(Data_sz,Addr_sz,addr_max_int) |
|
78 | generic map(Data_sz,Addr_sz,addr_max_int) | |
77 |
port map(clk,rst, |
|
79 | port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); | |
78 |
|
80 | |||
|
81 | DATA <= DataOut; | |||
79 |
|
82 | |||
80 | end ar_APB_FifoWrite; No newline at end of file |
|
83 | end ar_APB_FifoWrite; |
@@ -49,7 +49,8 entity ApbDriver is | |||||
49 | WriteEnable : out std_logic; --! Instruction d'�criture en m�moire |
|
49 | WriteEnable : out std_logic; --! Instruction d'�criture en m�moire | |
50 | FlagEmpty : in std_logic; --! Flag, M�moire vide |
|
50 | FlagEmpty : in std_logic; --! Flag, M�moire vide | |
51 | FlagFull : in std_logic; --! Flag, M�moire pleine |
|
51 | FlagFull : in std_logic; --! Flag, M�moire pleine | |
52 |
ReUse : out std_logic; |
|
52 | ReUse : out std_logic; --! Flag, Permet de relire la m�moire du d�but | |
|
53 | Lock : out std_logic; --! Flag, Permet de bloquer l'�criture dans la m�moire | |||
53 | DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en entr�e |
|
54 | DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en entr�e | |
54 | DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en sortie |
|
55 | DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en sortie | |
55 | AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (�criture) |
|
56 | AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (�criture) | |
@@ -70,7 +71,7 constant pconfig : apb_config_type := ( | |||||
70 | 1 => apb_iobar(paddr, pmask)); |
|
71 | 1 => apb_iobar(paddr, pmask)); | |
71 |
|
72 | |||
72 | type DEVICE_ctrlr_Reg is record |
|
73 | type DEVICE_ctrlr_Reg is record | |
73 |
DEVICE_Cfg : std_logic_vector( |
|
74 | DEVICE_Cfg : std_logic_vector(5 downto 0); | |
74 | DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0); |
|
75 | DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0); | |
75 | DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0); |
|
76 | DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0); | |
76 | DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0); |
|
77 | DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0); | |
@@ -90,6 +91,7 Rec.DEVICE_Cfg(1) <= FlagWR; | |||||
90 | Rec.DEVICE_Cfg(2) <= FlagEmpty; |
|
91 | Rec.DEVICE_Cfg(2) <= FlagEmpty; | |
91 | Rec.DEVICE_Cfg(3) <= FlagFull; |
|
92 | Rec.DEVICE_Cfg(3) <= FlagFull; | |
92 | ReUse <= Rec.DEVICE_Cfg(4); |
|
93 | ReUse <= Rec.DEVICE_Cfg(4); | |
|
94 | Lock <= Rec.DEVICE_Cfg(5); | |||
93 |
|
95 | |||
94 | DataIn <= Rec.DEVICE_DataW; |
|
96 | DataIn <= Rec.DEVICE_DataW; | |
95 | Rec.DEVICE_DataR <= DataOut; |
|
97 | Rec.DEVICE_DataR <= DataOut; | |
@@ -105,6 +107,7 Rec.DEVICE_AddrR <= AddrOut; | |||||
105 | FlagWR <= '0'; |
|
107 | FlagWR <= '0'; | |
106 | FlagRE <= '0'; |
|
108 | FlagRE <= '0'; | |
107 | Rec.DEVICE_Cfg(4) <= '0'; |
|
109 | Rec.DEVICE_Cfg(4) <= '0'; | |
|
110 | Rec.DEVICE_Cfg(5) <= '0'; | |||
108 |
|
111 | |||
109 | elsif(clk'event and clk='1')then |
|
112 | elsif(clk'event and clk='1')then | |
110 |
|
113 | |||
@@ -116,6 +119,7 Rec.DEVICE_AddrR <= AddrOut; | |||||
116 | Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0); |
|
119 | Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0); | |
117 | when "000010" => |
|
120 | when "000010" => | |
118 | Rec.DEVICE_Cfg(4) <= apbi.pwdata(16); |
|
121 | Rec.DEVICE_Cfg(4) <= apbi.pwdata(16); | |
|
122 | Rec.DEVICE_Cfg(5) <= apbi.pwdata(20); | |||
119 | when others => |
|
123 | when others => | |
120 | null; |
|
124 | null; | |
121 | end case; |
|
125 | end case; | |
@@ -140,8 +144,9 Rec.DEVICE_AddrR <= AddrOut; | |||||
140 | Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1); |
|
144 | Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1); | |
141 | Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2); |
|
145 | Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2); | |
142 | Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3); |
|
146 | Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3); | |
143 |
Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4); |
|
147 | Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4); | |
144 |
Rdata(3 |
|
148 | Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5); | |
|
149 | Rdata(31 downto 24) <= X"CC"; | |||
145 | when others => |
|
150 | when others => | |
146 | Rdata <= (others => '0'); |
|
151 | Rdata <= (others => '0'); | |
147 | end case; |
|
152 | end case; |
@@ -72,7 +72,8 component ApbDriver is | |||||
72 | WriteEnable : in std_logic; |
|
72 | WriteEnable : in std_logic; | |
73 | FlagEmpty : in std_logic; |
|
73 | FlagEmpty : in std_logic; | |
74 | FlagFull : in std_logic; |
|
74 | FlagFull : in std_logic; | |
75 |
ReUse : |
|
75 | ReUse : out std_logic; | |
|
76 | Lock : out std_logic; | |||
76 | DataIn : out std_logic_vector(Data_sz-1 downto 0); |
|
77 | DataIn : out std_logic_vector(Data_sz-1 downto 0); | |
77 | DataOut : in std_logic_vector(Data_sz-1 downto 0); |
|
78 | DataOut : in std_logic_vector(Data_sz-1 downto 0); | |
78 | AddrIn : in std_logic_vector(Addr_sz-1 downto 0); |
|
79 | AddrIn : in std_logic_vector(Addr_sz-1 downto 0); | |
@@ -94,6 +95,7 component Top_FIFO is | |||||
94 | flag_RE : in std_logic; |
|
95 | flag_RE : in std_logic; | |
95 | flag_WR : in std_logic; |
|
96 | flag_WR : in std_logic; | |
96 | ReUse : in std_logic; |
|
97 | ReUse : in std_logic; | |
|
98 | Lock : in std_logic; | |||
97 | Data_in : in std_logic_vector(Data_sz-1 downto 0); |
|
99 | Data_in : in std_logic_vector(Data_sz-1 downto 0); | |
98 | Addr_RE : out std_logic_vector(addr_sz-1 downto 0); |
|
100 | Addr_RE : out std_logic_vector(addr_sz-1 downto 0); | |
99 | Addr_WR : out std_logic_vector(addr_sz-1 downto 0); |
|
101 | Addr_WR : out std_logic_vector(addr_sz-1 downto 0); | |
@@ -167,29 +169,31 component APB_FifoWrite is | |||||
167 | clk : in std_logic; |
|
169 | clk : in std_logic; | |
168 | rst : in std_logic; |
|
170 | rst : in std_logic; | |
169 | apbi : in apb_slv_in_type; |
|
171 | apbi : in apb_slv_in_type; | |
|
172 | ReadEnable : in std_logic; | |||
|
173 | DATA : out std_logic_vector(Data_sz-1 downto 0); | |||
170 | apbo : out apb_slv_out_type |
|
174 | apbo : out apb_slv_out_type | |
171 | ); |
|
175 | ); | |
172 | end component; |
|
176 | end component; | |
173 |
|
177 | |||
174 |
|
178 | |||
175 | component Top_FifoWrite is |
|
179 | --component Top_FifoWrite is | |
176 | generic( |
|
180 | -- generic( | |
177 | Data_sz : integer := 16; |
|
181 | -- Data_sz : integer := 16; | |
178 | Addr_sz : integer := 8; |
|
182 | -- Addr_sz : integer := 8; | |
179 | addr_max_int : integer := 256); |
|
183 | -- addr_max_int : integer := 256); | |
180 | port( |
|
184 | -- port( | |
181 | clk : in std_logic; |
|
185 | -- clk : in std_logic; | |
182 | raz : in std_logic; |
|
186 | -- raz : in std_logic; | |
183 | flag_RE : in std_logic; |
|
187 | -- flag_RE : in std_logic; | |
184 | flag_WR : in std_logic; |
|
188 | -- flag_WR : in std_logic; | |
185 | Data_in : in std_logic_vector(Data_sz-1 downto 0); |
|
189 | -- Data_in : in std_logic_vector(Data_sz-1 downto 0); | |
186 | Raddr : in std_logic_vector(addr_sz-1 downto 0); |
|
190 | -- Raddr : in std_logic_vector(addr_sz-1 downto 0); | |
187 | full : out std_logic; |
|
191 | -- full : out std_logic; | |
188 | empty : out std_logic; |
|
192 | -- empty : out std_logic; | |
189 | Waddr : out std_logic_vector(addr_sz-1 downto 0); |
|
193 | -- Waddr : out std_logic_vector(addr_sz-1 downto 0); | |
190 | Data_out : out std_logic_vector(Data_sz-1 downto 0) |
|
194 | -- Data_out : out std_logic_vector(Data_sz-1 downto 0) | |
191 | ); |
|
195 | -- ); | |
192 | end component; |
|
196 | --end component; | |
193 |
|
197 | |||
194 | --===========================================================| |
|
198 | --===========================================================| | |
195 | --================== Demi FIFO Lecture ======================| |
|
199 | --================== Demi FIFO Lecture ======================| | |
@@ -209,28 +213,30 component APB_FifoRead is | |||||
209 | clk : in std_logic; |
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213 | clk : in std_logic; | |
210 | rst : in std_logic; |
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214 | rst : in std_logic; | |
211 | apbi : in apb_slv_in_type; |
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215 | apbi : in apb_slv_in_type; | |
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216 | WriteEnable : in std_logic; | |||
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217 | DATA : out std_logic_vector(Data_sz-1 downto 0); | |||
212 | apbo : out apb_slv_out_type |
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218 | apbo : out apb_slv_out_type | |
213 | ); |
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219 | ); | |
214 | end component; |
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220 | end component; | |
215 |
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221 | |||
216 |
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222 | |||
217 | component Top_FifoRead is |
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223 | --component Top_FifoRead is | |
218 | generic( |
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224 | -- generic( | |
219 | Data_sz : integer := 16; |
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225 | -- Data_sz : integer := 16; | |
220 | Addr_sz : integer := 8; |
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226 | -- Addr_sz : integer := 8; | |
221 | addr_max_int : integer := 256); |
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227 | -- addr_max_int : integer := 256); | |
222 | port( |
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228 | -- port( | |
223 | clk : in std_logic; |
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229 | -- clk : in std_logic; | |
224 | raz : in std_logic; |
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230 | -- raz : in std_logic; | |
225 | flag_RE : in std_logic; |
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231 | -- flag_RE : in std_logic; | |
226 | flag_WR : in std_logic; |
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232 | -- flag_WR : in std_logic; | |
227 | Data_in : in std_logic_vector(Data_sz-1 downto 0); |
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233 | -- Data_in : in std_logic_vector(Data_sz-1 downto 0); | |
228 | Waddr : in std_logic_vector(addr_sz-1 downto 0); |
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234 | -- Waddr : in std_logic_vector(addr_sz-1 downto 0); | |
229 | full : out std_logic; |
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235 | -- full : out std_logic; | |
230 | empty : out std_logic; |
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236 | -- empty : out std_logic; | |
231 | Raddr : out std_logic_vector(addr_sz-1 downto 0); |
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237 | -- Raddr : out std_logic_vector(addr_sz-1 downto 0); | |
232 | Data_out : out std_logic_vector(Data_sz-1 downto 0) |
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238 | -- Data_out : out std_logic_vector(Data_sz-1 downto 0) | |
233 | ); |
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239 | -- ); | |
234 | end component; |
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240 | --end component; | |
235 |
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241 | |||
236 | end; |
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242 | end; |
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