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1 | ------------------------------------------------------------------------------ |
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1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
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4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
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5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
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6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
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7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
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8 | -- (at your option) any later version. | |
9 | -- |
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9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
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10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
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13 | -- GNU General Public License for more details. | |
14 | -- |
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14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
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15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
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16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
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18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
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19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------- |
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21 | ------------------------------------------------------------------------------- | |
22 | LIBRARY IEEE; |
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22 | LIBRARY IEEE; | |
23 | USE IEEE.numeric_std.ALL; |
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23 | USE IEEE.numeric_std.ALL; | |
24 | USE IEEE.std_logic_1164.ALL; |
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24 | USE IEEE.std_logic_1164.ALL; | |
25 | LIBRARY grlib; |
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25 | LIBRARY grlib; | |
26 | USE grlib.amba.ALL; |
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26 | USE grlib.amba.ALL; | |
27 | USE grlib.stdlib.ALL; |
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27 | USE grlib.stdlib.ALL; | |
28 | LIBRARY techmap; |
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28 | LIBRARY techmap; | |
29 | USE techmap.gencomp.ALL; |
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29 | USE techmap.gencomp.ALL; | |
30 | LIBRARY gaisler; |
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30 | LIBRARY gaisler; | |
31 | USE gaisler.memctrl.ALL; |
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31 | USE gaisler.memctrl.ALL; | |
32 | USE gaisler.leon3.ALL; |
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32 | USE gaisler.leon3.ALL; | |
33 | USE gaisler.uart.ALL; |
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33 | USE gaisler.uart.ALL; | |
34 | USE gaisler.misc.ALL; |
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34 | USE gaisler.misc.ALL; | |
35 | USE gaisler.spacewire.ALL; |
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35 | USE gaisler.spacewire.ALL; | |
36 | LIBRARY esa; |
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36 | LIBRARY esa; | |
37 | USE esa.memoryctrl.ALL; |
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37 | USE esa.memoryctrl.ALL; | |
38 | LIBRARY lpp; |
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38 | LIBRARY lpp; | |
39 | USE lpp.lpp_memory.ALL; |
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39 | USE lpp.lpp_memory.ALL; | |
40 | USE lpp.lpp_ad_conv.ALL; |
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40 | USE lpp.lpp_ad_conv.ALL; | |
41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
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41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib | |
42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
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42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker | |
43 | USE lpp.iir_filter.ALL; |
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43 | USE lpp.iir_filter.ALL; | |
44 | USE lpp.general_purpose.ALL; |
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44 | USE lpp.general_purpose.ALL; | |
45 | USE lpp.lpp_lfr_time_management.ALL; |
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45 | USE lpp.lpp_lfr_time_management.ALL; | |
46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
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46 | USE lpp.lpp_leon3_soc_pkg.ALL; | |
47 |
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47 | |||
48 | ENTITY MINI_LFR_top IS |
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48 | ENTITY MINI_LFR_top IS | |
49 |
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49 | |||
50 | PORT ( |
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50 | PORT ( | |
51 | clk_50 : IN STD_LOGIC; |
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51 | clk_50 : IN STD_LOGIC; | |
52 | clk_49 : IN STD_LOGIC; |
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52 | clk_49 : IN STD_LOGIC; | |
53 | reset : IN STD_LOGIC; |
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53 | reset : IN STD_LOGIC; | |
54 | --BPs |
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54 | --BPs | |
55 | BP0 : IN STD_LOGIC; |
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55 | BP0 : IN STD_LOGIC; | |
56 | BP1 : IN STD_LOGIC; |
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56 | BP1 : IN STD_LOGIC; | |
57 | --LEDs |
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57 | --LEDs | |
58 | LED0 : OUT STD_LOGIC; |
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58 | LED0 : OUT STD_LOGIC; | |
59 | LED1 : OUT STD_LOGIC; |
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59 | LED1 : OUT STD_LOGIC; | |
60 | LED2 : OUT STD_LOGIC; |
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60 | LED2 : OUT STD_LOGIC; | |
61 | --UARTs |
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61 | --UARTs | |
62 | TXD1 : IN STD_LOGIC; |
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62 | TXD1 : IN STD_LOGIC; | |
63 | RXD1 : OUT STD_LOGIC; |
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63 | RXD1 : OUT STD_LOGIC; | |
64 | nCTS1 : OUT STD_LOGIC; |
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64 | nCTS1 : OUT STD_LOGIC; | |
65 | nRTS1 : IN STD_LOGIC; |
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65 | nRTS1 : IN STD_LOGIC; | |
66 |
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66 | |||
67 | TXD2 : IN STD_LOGIC; |
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67 | TXD2 : IN STD_LOGIC; | |
68 | RXD2 : OUT STD_LOGIC; |
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68 | RXD2 : OUT STD_LOGIC; | |
69 | nCTS2 : OUT STD_LOGIC; |
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69 | nCTS2 : OUT STD_LOGIC; | |
70 | nDTR2 : IN STD_LOGIC; |
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70 | nDTR2 : IN STD_LOGIC; | |
71 | nRTS2 : IN STD_LOGIC; |
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71 | nRTS2 : IN STD_LOGIC; | |
72 | nDCD2 : OUT STD_LOGIC; |
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72 | nDCD2 : OUT STD_LOGIC; | |
73 |
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73 | |||
74 | --EXT CONNECTOR |
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74 | --EXT CONNECTOR | |
75 | IO0 : INOUT STD_LOGIC; |
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75 | IO0 : INOUT STD_LOGIC; | |
76 | IO1 : INOUT STD_LOGIC; |
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76 | IO1 : INOUT STD_LOGIC; | |
77 | IO2 : INOUT STD_LOGIC; |
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77 | IO2 : INOUT STD_LOGIC; | |
78 | IO3 : INOUT STD_LOGIC; |
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78 | IO3 : INOUT STD_LOGIC; | |
79 | IO4 : INOUT STD_LOGIC; |
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79 | IO4 : INOUT STD_LOGIC; | |
80 | IO5 : INOUT STD_LOGIC; |
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80 | IO5 : INOUT STD_LOGIC; | |
81 | IO6 : INOUT STD_LOGIC; |
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81 | IO6 : INOUT STD_LOGIC; | |
82 | IO7 : INOUT STD_LOGIC; |
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82 | IO7 : INOUT STD_LOGIC; | |
83 | IO8 : INOUT STD_LOGIC; |
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83 | IO8 : INOUT STD_LOGIC; | |
84 | IO9 : INOUT STD_LOGIC; |
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84 | IO9 : INOUT STD_LOGIC; | |
85 | IO10 : INOUT STD_LOGIC; |
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85 | IO10 : INOUT STD_LOGIC; | |
86 | IO11 : INOUT STD_LOGIC; |
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86 | IO11 : INOUT STD_LOGIC; | |
87 |
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87 | |||
88 | --SPACE WIRE |
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88 | --SPACE WIRE | |
89 | SPW_EN : OUT STD_LOGIC; -- 0 => off |
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89 | SPW_EN : OUT STD_LOGIC; -- 0 => off | |
90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK |
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90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK | |
91 | SPW_NOM_SIN : IN STD_LOGIC; |
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91 | SPW_NOM_SIN : IN STD_LOGIC; | |
92 | SPW_NOM_DOUT : OUT STD_LOGIC; |
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92 | SPW_NOM_DOUT : OUT STD_LOGIC; | |
93 | SPW_NOM_SOUT : OUT STD_LOGIC; |
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93 | SPW_NOM_SOUT : OUT STD_LOGIC; | |
94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK |
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94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK | |
95 | SPW_RED_SIN : IN STD_LOGIC; |
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95 | SPW_RED_SIN : IN STD_LOGIC; | |
96 | SPW_RED_DOUT : OUT STD_LOGIC; |
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96 | SPW_RED_DOUT : OUT STD_LOGIC; | |
97 | SPW_RED_SOUT : OUT STD_LOGIC; |
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97 | SPW_RED_SOUT : OUT STD_LOGIC; | |
98 | -- MINI LFR ADC INPUTS |
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98 | -- MINI LFR ADC INPUTS | |
99 | ADC_nCS : OUT STD_LOGIC; |
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99 | ADC_nCS : OUT STD_LOGIC; | |
100 | ADC_CLK : OUT STD_LOGIC; |
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100 | ADC_CLK : OUT STD_LOGIC; | |
101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
102 |
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102 | |||
103 | -- SRAM |
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103 | -- SRAM | |
104 | SRAM_nWE : OUT STD_LOGIC; |
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104 | SRAM_nWE : OUT STD_LOGIC; | |
105 | SRAM_CE : OUT STD_LOGIC; |
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105 | SRAM_CE : OUT STD_LOGIC; | |
106 | SRAM_nOE : OUT STD_LOGIC; |
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106 | SRAM_nOE : OUT STD_LOGIC; | |
107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
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108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |
109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
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109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
110 | ); |
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110 | ); | |
111 |
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111 | |||
112 | END MINI_LFR_top; |
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112 | END MINI_LFR_top; | |
113 |
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113 | |||
114 |
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114 | |||
115 | ARCHITECTURE beh OF MINI_LFR_top IS |
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115 | ARCHITECTURE beh OF MINI_LFR_top IS | |
116 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
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116 | SIGNAL clk_50_s : STD_LOGIC := '0'; | |
117 | SIGNAL clk_25 : STD_LOGIC := '0'; |
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117 | SIGNAL clk_25 : STD_LOGIC := '0'; | |
118 | SIGNAL clk_24 : STD_LOGIC := '0'; |
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118 | SIGNAL clk_24 : STD_LOGIC := '0'; | |
119 | ----------------------------------------------------------------------------- |
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119 | ----------------------------------------------------------------------------- | |
120 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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120 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
121 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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121 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
122 | -- |
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122 | -- | |
123 | SIGNAL errorn : STD_LOGIC; |
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123 | SIGNAL errorn : STD_LOGIC; | |
124 | -- UART AHB --------------------------------------------------------------- |
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124 | -- UART AHB --------------------------------------------------------------- | |
125 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data |
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125 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data | |
126 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data |
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126 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data | |
127 |
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127 | |||
128 | -- UART APB --------------------------------------------------------------- |
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128 | -- UART APB --------------------------------------------------------------- | |
129 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data |
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129 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data | |
130 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data |
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130 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data | |
131 | -- |
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131 | -- | |
132 | SIGNAL I00_s : STD_LOGIC; |
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132 | SIGNAL I00_s : STD_LOGIC; | |
133 |
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133 | |||
134 | -- CONSTANTS |
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134 | -- CONSTANTS | |
135 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
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135 | CONSTANT CFG_PADTECH : INTEGER := inferred; | |
136 | -- |
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136 | -- | |
137 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
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137 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f | |
138 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
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138 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; | |
139 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
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139 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker | |
140 |
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140 | |||
141 | SIGNAL apbi_ext : apb_slv_in_type; |
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141 | SIGNAL apbi_ext : apb_slv_in_type; | |
142 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
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142 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); | |
143 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
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143 | SIGNAL ahbi_s_ext : ahb_slv_in_type; | |
144 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); |
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144 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); | |
145 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
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145 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |
146 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); |
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146 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); | |
147 |
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147 | |||
148 | -- Spacewire signals |
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148 | -- Spacewire signals | |
149 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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149 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
150 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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150 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
151 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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151 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
152 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
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152 | SIGNAL spw_rxtxclk : STD_ULOGIC; | |
153 | SIGNAL spw_rxclkn : STD_ULOGIC; |
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153 | SIGNAL spw_rxclkn : STD_ULOGIC; | |
154 | SIGNAL spw_clk : STD_LOGIC; |
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154 | SIGNAL spw_clk : STD_LOGIC; | |
155 | SIGNAL swni : grspw_in_type; |
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155 | SIGNAL swni : grspw_in_type; | |
156 | SIGNAL swno : grspw_out_type; |
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156 | SIGNAL swno : grspw_out_type; | |
157 | -- SIGNAL clkmn : STD_ULOGIC; |
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157 | -- SIGNAL clkmn : STD_ULOGIC; | |
158 | -- SIGNAL txclk : STD_ULOGIC; |
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158 | -- SIGNAL txclk : STD_ULOGIC; | |
159 |
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159 | |||
160 | --GPIO |
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160 | --GPIO | |
161 | SIGNAL gpioi : gpio_in_type; |
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161 | SIGNAL gpioi : gpio_in_type; | |
162 | SIGNAL gpioo : gpio_out_type; |
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162 | SIGNAL gpioo : gpio_out_type; | |
163 |
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163 | |||
164 | -- AD Converter ADS7886 |
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164 | -- AD Converter ADS7886 | |
165 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
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165 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
166 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
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166 | SIGNAL sample_s : Samples(7 DOWNTO 0); | |
167 | SIGNAL sample_val : STD_LOGIC; |
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167 | SIGNAL sample_val : STD_LOGIC; | |
168 | SIGNAL ADC_nCS_sig : STD_LOGIC; |
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168 | SIGNAL ADC_nCS_sig : STD_LOGIC; | |
169 | SIGNAL ADC_CLK_sig : STD_LOGIC; |
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169 | SIGNAL ADC_CLK_sig : STD_LOGIC; | |
170 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); |
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170 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
171 |
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171 | |||
172 | SIGNAL bias_fail_sw_sig : STD_LOGIC; |
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172 | SIGNAL bias_fail_sw_sig : STD_LOGIC; | |
173 |
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173 | |||
174 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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174 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
175 | SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0); |
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175 | SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0); | |
176 | SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0); |
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176 | SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0); | |
177 | ----------------------------------------------------------------------------- |
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177 | ----------------------------------------------------------------------------- | |
178 |
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178 | |||
179 | BEGIN -- beh |
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179 | BEGIN -- beh | |
180 |
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180 | |||
181 | ----------------------------------------------------------------------------- |
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181 | ----------------------------------------------------------------------------- | |
182 | -- CLK |
|
182 | -- CLK | |
183 | ----------------------------------------------------------------------------- |
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183 | ----------------------------------------------------------------------------- | |
184 |
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184 | |||
185 | PROCESS(clk_50) |
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185 | PROCESS(clk_50) | |
186 | BEGIN |
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186 | BEGIN | |
187 | IF clk_50'EVENT AND clk_50 = '1' THEN |
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187 | IF clk_50'EVENT AND clk_50 = '1' THEN | |
188 | clk_50_s <= NOT clk_50_s; |
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188 | clk_50_s <= NOT clk_50_s; | |
189 | END IF; |
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189 | END IF; | |
190 | END PROCESS; |
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190 | END PROCESS; | |
191 |
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191 | |||
192 | PROCESS(clk_50_s) |
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192 | PROCESS(clk_50_s) | |
193 | BEGIN |
|
193 | BEGIN | |
194 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
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194 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN | |
195 | clk_25 <= NOT clk_25; |
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195 | clk_25 <= NOT clk_25; | |
196 | END IF; |
|
196 | END IF; | |
197 | END PROCESS; |
|
197 | END PROCESS; | |
198 |
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198 | |||
199 | PROCESS(clk_49) |
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199 | PROCESS(clk_49) | |
200 | BEGIN |
|
200 | BEGIN | |
201 | IF clk_49'EVENT AND clk_49 = '1' THEN |
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201 | IF clk_49'EVENT AND clk_49 = '1' THEN | |
202 | clk_24 <= NOT clk_24; |
|
202 | clk_24 <= NOT clk_24; | |
203 | END IF; |
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203 | END IF; | |
204 | END PROCESS; |
|
204 | END PROCESS; | |
205 |
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205 | |||
206 | ----------------------------------------------------------------------------- |
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206 | ----------------------------------------------------------------------------- | |
207 |
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207 | |||
208 | PROCESS (clk_25, reset) |
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208 | PROCESS (clk_25, reset) | |
209 | BEGIN -- PROCESS |
|
209 | BEGIN -- PROCESS | |
210 | IF reset = '0' THEN -- asynchronous reset (active low) |
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210 | IF reset = '0' THEN -- asynchronous reset (active low) | |
211 | LED0 <= '0'; |
|
211 | LED0 <= '0'; | |
212 | LED1 <= '0'; |
|
212 | LED1 <= '0'; | |
213 | LED2 <= '0'; |
|
213 | LED2 <= '0'; | |
214 | --IO1 <= '0'; |
|
214 | --IO1 <= '0'; | |
215 | --IO2 <= '1'; |
|
215 | --IO2 <= '1'; | |
216 | --IO3 <= '0'; |
|
216 | --IO3 <= '0'; | |
217 | --IO4 <= '0'; |
|
217 | --IO4 <= '0'; | |
218 | --IO5 <= '0'; |
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218 | --IO5 <= '0'; | |
219 | --IO6 <= '0'; |
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219 | --IO6 <= '0'; | |
220 | --IO7 <= '0'; |
|
220 | --IO7 <= '0'; | |
221 | --IO8 <= '0'; |
|
221 | --IO8 <= '0'; | |
222 | --IO9 <= '0'; |
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222 | --IO9 <= '0'; | |
223 | --IO10 <= '0'; |
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223 | --IO10 <= '0'; | |
224 | --IO11 <= '0'; |
|
224 | --IO11 <= '0'; | |
225 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
|
225 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |
226 | LED0 <= '0'; |
|
226 | LED0 <= '0'; | |
227 | LED1 <= '1'; |
|
227 | LED1 <= '1'; | |
228 | LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
|
228 | LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |
229 | --IO1 <= '1'; |
|
229 | --IO1 <= '1'; | |
230 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; |
|
230 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; | |
231 | --IO3 <= ADC_SDO(0); |
|
231 | --IO3 <= ADC_SDO(0); | |
232 | --IO4 <= ADC_SDO(1); |
|
232 | --IO4 <= ADC_SDO(1); | |
233 | --IO5 <= ADC_SDO(2); |
|
233 | --IO5 <= ADC_SDO(2); | |
234 | --IO6 <= ADC_SDO(3); |
|
234 | --IO6 <= ADC_SDO(3); | |
235 | --IO7 <= ADC_SDO(4); |
|
235 | --IO7 <= ADC_SDO(4); | |
236 | --IO8 <= ADC_SDO(5); |
|
236 | --IO8 <= ADC_SDO(5); | |
237 | --IO9 <= ADC_SDO(6); |
|
237 | --IO9 <= ADC_SDO(6); | |
238 | --IO10 <= ADC_SDO(7); |
|
238 | --IO10 <= ADC_SDO(7); | |
239 | --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
|
239 | --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |
240 | END IF; |
|
240 | END IF; | |
241 | END PROCESS; |
|
241 | END PROCESS; | |
242 |
|
242 | |||
243 | PROCESS (clk_24, reset) |
|
243 | PROCESS (clk_24, reset) | |
244 | BEGIN -- PROCESS |
|
244 | BEGIN -- PROCESS | |
245 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
245 | IF reset = '0' THEN -- asynchronous reset (active low) | |
246 | I00_s <= '0'; |
|
246 | I00_s <= '0'; | |
247 | ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge |
|
247 | ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge | |
248 | I00_s <= NOT I00_s ; |
|
248 | I00_s <= NOT I00_s ; | |
249 | END IF; |
|
249 | END IF; | |
250 | END PROCESS; |
|
250 | END PROCESS; | |
251 | -- IO0 <= I00_s; |
|
251 | -- IO0 <= I00_s; | |
252 |
|
252 | |||
253 | --UARTs |
|
253 | --UARTs | |
254 | nCTS1 <= '1'; |
|
254 | nCTS1 <= '1'; | |
255 | nCTS2 <= '1'; |
|
255 | nCTS2 <= '1'; | |
256 | nDCD2 <= '1'; |
|
256 | nDCD2 <= '1'; | |
257 |
|
257 | |||
258 | --EXT CONNECTOR |
|
258 | --EXT CONNECTOR | |
259 |
|
259 | |||
260 | --SPACE WIRE |
|
260 | --SPACE WIRE | |
261 |
|
261 | |||
262 | leon3_soc_1 : leon3_soc |
|
262 | leon3_soc_1 : leon3_soc | |
263 | GENERIC MAP ( |
|
263 | GENERIC MAP ( | |
264 | fabtech => apa3e, |
|
264 | fabtech => apa3e, | |
265 | memtech => apa3e, |
|
265 | memtech => apa3e, | |
266 | padtech => inferred, |
|
266 | padtech => inferred, | |
267 | clktech => inferred, |
|
267 | clktech => inferred, | |
268 | disas => 0, |
|
268 | disas => 0, | |
269 | dbguart => 0, |
|
269 | dbguart => 0, | |
270 | pclow => 2, |
|
270 | pclow => 2, | |
271 | clk_freq => 25000, |
|
271 | clk_freq => 25000, | |
272 | NB_CPU => 1, |
|
272 | NB_CPU => 1, | |
273 | ENABLE_FPU => 1, |
|
273 | ENABLE_FPU => 1, | |
274 | FPU_NETLIST => 0, |
|
274 | FPU_NETLIST => 0, | |
275 | ENABLE_DSU => 1, |
|
275 | ENABLE_DSU => 1, | |
276 | ENABLE_AHB_UART => 1, |
|
276 | ENABLE_AHB_UART => 1, | |
277 | ENABLE_APB_UART => 1, |
|
277 | ENABLE_APB_UART => 1, | |
278 | ENABLE_IRQMP => 1, |
|
278 | ENABLE_IRQMP => 1, | |
279 | ENABLE_GPT => 1, |
|
279 | ENABLE_GPT => 1, | |
280 | NB_AHB_MASTER => NB_AHB_MASTER, |
|
280 | NB_AHB_MASTER => NB_AHB_MASTER, | |
281 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
|
281 | NB_AHB_SLAVE => NB_AHB_SLAVE, | |
282 | NB_APB_SLAVE => NB_APB_SLAVE) |
|
282 | NB_APB_SLAVE => NB_APB_SLAVE) | |
283 | PORT MAP ( |
|
283 | PORT MAP ( | |
284 | clk => clk_25, |
|
284 | clk => clk_25, | |
285 | reset => reset, |
|
285 | reset => reset, | |
286 | errorn => errorn, |
|
286 | errorn => errorn, | |
287 | ahbrxd => TXD1, |
|
287 | ahbrxd => TXD1, | |
288 | ahbtxd => RXD1, |
|
288 | ahbtxd => RXD1, | |
289 | urxd1 => TXD2, |
|
289 | urxd1 => TXD2, | |
290 | utxd1 => RXD2, |
|
290 | utxd1 => RXD2, | |
291 | address => SRAM_A, |
|
291 | address => SRAM_A, | |
292 | data => SRAM_DQ, |
|
292 | data => SRAM_DQ, | |
293 | nSRAM_BE0 => SRAM_nBE(0), |
|
293 | nSRAM_BE0 => SRAM_nBE(0), | |
294 | nSRAM_BE1 => SRAM_nBE(1), |
|
294 | nSRAM_BE1 => SRAM_nBE(1), | |
295 | nSRAM_BE2 => SRAM_nBE(2), |
|
295 | nSRAM_BE2 => SRAM_nBE(2), | |
296 | nSRAM_BE3 => SRAM_nBE(3), |
|
296 | nSRAM_BE3 => SRAM_nBE(3), | |
297 | nSRAM_WE => SRAM_nWE, |
|
297 | nSRAM_WE => SRAM_nWE, | |
298 | nSRAM_CE => SRAM_CE, |
|
298 | nSRAM_CE => SRAM_CE, | |
299 | nSRAM_OE => SRAM_nOE, |
|
299 | nSRAM_OE => SRAM_nOE, | |
300 |
|
300 | |||
301 | apbi_ext => apbi_ext, |
|
301 | apbi_ext => apbi_ext, | |
302 | apbo_ext => apbo_ext, |
|
302 | apbo_ext => apbo_ext, | |
303 | ahbi_s_ext => ahbi_s_ext, |
|
303 | ahbi_s_ext => ahbi_s_ext, | |
304 | ahbo_s_ext => ahbo_s_ext, |
|
304 | ahbo_s_ext => ahbo_s_ext, | |
305 | ahbi_m_ext => ahbi_m_ext, |
|
305 | ahbi_m_ext => ahbi_m_ext, | |
306 | ahbo_m_ext => ahbo_m_ext); |
|
306 | ahbo_m_ext => ahbo_m_ext); | |
307 |
|
307 | |||
308 | ------------------------------------------------------------------------------- |
|
308 | ------------------------------------------------------------------------------- | |
309 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
|
309 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- | |
310 | ------------------------------------------------------------------------------- |
|
310 | ------------------------------------------------------------------------------- | |
311 | apb_lfr_time_management_1 : apb_lfr_time_management |
|
311 | apb_lfr_time_management_1 : apb_lfr_time_management | |
312 | GENERIC MAP ( |
|
312 | GENERIC MAP ( | |
313 | pindex => 6, |
|
313 | pindex => 6, | |
314 | paddr => 6, |
|
314 | paddr => 6, | |
315 | pmask => 16#fff#, |
|
315 | pmask => 16#fff#, | |
316 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 |
|
316 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 | |
317 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
|
317 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set | |
318 | PORT MAP ( |
|
318 | PORT MAP ( | |
319 | clk25MHz => clk_25, |
|
319 | clk25MHz => clk_25, | |
320 | clk24_576MHz => clk_24, -- 49.152MHz/2 |
|
320 | clk24_576MHz => clk_24, -- 49.152MHz/2 | |
321 | resetn => reset, |
|
321 | resetn => reset, | |
322 | grspw_tick => swno.tickout, |
|
322 | grspw_tick => swno.tickout, | |
323 | apbi => apbi_ext, |
|
323 | apbi => apbi_ext, | |
324 | apbo => apbo_ext(6), |
|
324 | apbo => apbo_ext(6), | |
325 | coarse_time => coarse_time, |
|
325 | coarse_time => coarse_time, | |
326 | fine_time => fine_time); |
|
326 | fine_time => fine_time); | |
327 |
|
327 | |||
328 | ----------------------------------------------------------------------- |
|
328 | ----------------------------------------------------------------------- | |
329 | --- SpaceWire -------------------------------------------------------- |
|
329 | --- SpaceWire -------------------------------------------------------- | |
330 | ----------------------------------------------------------------------- |
|
330 | ----------------------------------------------------------------------- | |
331 |
|
331 | |||
332 | SPW_EN <= '1'; |
|
332 | SPW_EN <= '1'; | |
333 |
|
333 | |||
334 | spw_clk <= clk_50_s; |
|
334 | spw_clk <= clk_50_s; | |
335 | spw_rxtxclk <= spw_clk; |
|
335 | spw_rxtxclk <= spw_clk; | |
336 | spw_rxclkn <= NOT spw_rxtxclk; |
|
336 | spw_rxclkn <= NOT spw_rxtxclk; | |
337 |
|
337 | |||
338 | -- PADS for SPW1 |
|
338 | -- PADS for SPW1 | |
339 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
|
339 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) | |
340 | PORT MAP (SPW_NOM_DIN, dtmp(0)); |
|
340 | PORT MAP (SPW_NOM_DIN, dtmp(0)); | |
341 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
|
341 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) | |
342 | PORT MAP (SPW_NOM_SIN, stmp(0)); |
|
342 | PORT MAP (SPW_NOM_SIN, stmp(0)); | |
343 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
343 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) | |
344 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); |
|
344 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); | |
345 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
345 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) | |
346 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); |
|
346 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); | |
347 | -- PADS FOR SPW2 |
|
347 | -- PADS FOR SPW2 | |
348 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
348 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
349 | PORT MAP (SPW_RED_SIN, dtmp(1)); |
|
349 | PORT MAP (SPW_RED_SIN, dtmp(1)); | |
350 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
350 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
351 | PORT MAP (SPW_RED_DIN, stmp(1)); |
|
351 | PORT MAP (SPW_RED_DIN, stmp(1)); | |
352 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
352 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) | |
353 | PORT MAP (SPW_RED_DOUT, swno.d(1)); |
|
353 | PORT MAP (SPW_RED_DOUT, swno.d(1)); | |
354 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
354 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) | |
355 | PORT MAP (SPW_RED_SOUT, swno.s(1)); |
|
355 | PORT MAP (SPW_RED_SOUT, swno.s(1)); | |
356 |
|
356 | |||
357 | -- GRSPW PHY |
|
357 | -- GRSPW PHY | |
358 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
|
358 | --spw1_input: if CFG_SPW_GRSPW = 1 generate | |
359 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
|
359 | spw_inputloop : FOR j IN 0 TO 1 GENERATE | |
360 | spw_phy0 : grspw_phy |
|
360 | spw_phy0 : grspw_phy | |
361 | GENERIC MAP( |
|
361 | GENERIC MAP( | |
362 | tech => apa3e, |
|
362 | tech => apa3e, | |
363 | rxclkbuftype => 1, |
|
363 | rxclkbuftype => 1, | |
364 | scantest => 0) |
|
364 | scantest => 0) | |
365 | PORT MAP( |
|
365 | PORT MAP( | |
366 | rxrst => swno.rxrst, |
|
366 | rxrst => swno.rxrst, | |
367 | di => dtmp(j), |
|
367 | di => dtmp(j), | |
368 | si => stmp(j), |
|
368 | si => stmp(j), | |
369 | rxclko => spw_rxclk(j), |
|
369 | rxclko => spw_rxclk(j), | |
370 | do => swni.d(j), |
|
370 | do => swni.d(j), | |
371 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
|
371 | ndo => swni.nd(j*5+4 DOWNTO j*5), | |
372 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
372 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); | |
373 | END GENERATE spw_inputloop; |
|
373 | END GENERATE spw_inputloop; | |
374 |
|
374 | |||
375 | -- SPW core |
|
375 | -- SPW core | |
376 | sw0 : grspwm GENERIC MAP( |
|
376 | sw0 : grspwm GENERIC MAP( | |
377 | tech => apa3e, |
|
377 | tech => apa3e, | |
378 | hindex => 1, |
|
378 | hindex => 1, | |
379 | pindex => 5, |
|
379 | pindex => 5, | |
380 | paddr => 5, |
|
380 | paddr => 5, | |
381 | pirq => 11, |
|
381 | pirq => 11, | |
382 | sysfreq => 25000, -- CPU_FREQ |
|
382 | sysfreq => 25000, -- CPU_FREQ | |
383 | rmap => 1, |
|
383 | rmap => 1, | |
384 | rmapcrc => 1, |
|
384 | rmapcrc => 1, | |
385 | fifosize1 => 16, |
|
385 | fifosize1 => 16, | |
386 | fifosize2 => 16, |
|
386 | fifosize2 => 16, | |
387 | rxclkbuftype => 1, |
|
387 | rxclkbuftype => 1, | |
388 | rxunaligned => 0, |
|
388 | rxunaligned => 0, | |
389 | rmapbufs => 4, |
|
389 | rmapbufs => 4, | |
390 | ft => 0, |
|
390 | ft => 0, | |
391 | netlist => 0, |
|
391 | netlist => 0, | |
392 | ports => 2, |
|
392 | ports => 2, | |
393 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
|
393 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 | |
394 | memtech => apa3e, |
|
394 | memtech => apa3e, | |
395 | destkey => 2, |
|
395 | destkey => 2, | |
396 | spwcore => 1 |
|
396 | spwcore => 1 | |
397 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
|
397 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 | |
398 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
|
398 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 | |
399 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
|
399 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 | |
400 | ) |
|
400 | ) | |
401 | PORT MAP(reset, clk_25, spw_rxclk(0), |
|
401 | PORT MAP(reset, clk_25, spw_rxclk(0), | |
402 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
|
402 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, | |
403 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
|
403 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), | |
404 | swni, swno); |
|
404 | swni, swno); | |
405 |
|
405 | |||
406 | swni.tickin <= '0'; |
|
406 | swni.tickin <= '0'; | |
407 | swni.rmapen <= '1'; |
|
407 | swni.rmapen <= '1'; | |
408 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz |
|
408 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz | |
409 | swni.tickinraw <= '0'; |
|
409 | swni.tickinraw <= '0'; | |
410 | swni.timein <= (OTHERS => '0'); |
|
410 | swni.timein <= (OTHERS => '0'); | |
411 | swni.dcrstval <= (OTHERS => '0'); |
|
411 | swni.dcrstval <= (OTHERS => '0'); | |
412 | swni.timerrstval <= (OTHERS => '0'); |
|
412 | swni.timerrstval <= (OTHERS => '0'); | |
413 |
|
413 | |||
414 | ------------------------------------------------------------------------------- |
|
414 | ------------------------------------------------------------------------------- | |
415 | -- LFR ------------------------------------------------------------------------ |
|
415 | -- LFR ------------------------------------------------------------------------ | |
416 | ------------------------------------------------------------------------------- |
|
416 | ------------------------------------------------------------------------------- | |
417 | lpp_lfr_1 : lpp_lfr |
|
417 | lpp_lfr_1 : lpp_lfr | |
418 | GENERIC MAP ( |
|
418 | GENERIC MAP ( | |
419 | Mem_use => use_RAM, |
|
419 | Mem_use => use_RAM, | |
420 | nb_data_by_buffer_size => 32, |
|
420 | nb_data_by_buffer_size => 32, | |
421 | nb_word_by_buffer_size => 30, |
|
421 | -- nb_word_by_buffer_size => 30, | |
422 | nb_snapshot_param_size => 32, |
|
422 | nb_snapshot_param_size => 32, | |
423 | delta_vector_size => 32, |
|
423 | delta_vector_size => 32, | |
424 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
424 | delta_vector_size_f0_2 => 7, -- log2(96) | |
425 | pindex => 15, |
|
425 | pindex => 15, | |
426 | paddr => 15, |
|
426 | paddr => 15, | |
427 | pmask => 16#fff#, |
|
427 | pmask => 16#fff#, | |
428 | pirq_ms => 6, |
|
428 | pirq_ms => 6, | |
429 | pirq_wfp => 14, |
|
429 | pirq_wfp => 14, | |
430 | hindex => 2, |
|
430 | hindex => 2, | |
431 | top_lfr_version => X"00011C") -- aa.bb.cc version |
|
431 | top_lfr_version => X"00011C") -- aa.bb.cc version | |
432 | PORT MAP ( |
|
432 | PORT MAP ( | |
433 | clk => clk_25, |
|
433 | clk => clk_25, | |
434 | rstn => reset, |
|
434 | rstn => reset, | |
435 | sample_B => sample_s(2 DOWNTO 0), |
|
435 | sample_B => sample_s(2 DOWNTO 0), | |
436 | sample_E => sample_s(7 DOWNTO 3), |
|
436 | sample_E => sample_s(7 DOWNTO 3), | |
437 | sample_val => sample_val, |
|
437 | sample_val => sample_val, | |
438 | apbi => apbi_ext, |
|
438 | apbi => apbi_ext, | |
439 | apbo => apbo_ext(15), |
|
439 | apbo => apbo_ext(15), | |
440 | ahbi => ahbi_m_ext, |
|
440 | ahbi => ahbi_m_ext, | |
441 | ahbo => ahbo_m_ext(2), |
|
441 | ahbo => ahbo_m_ext(2), | |
442 | coarse_time => coarse_time, |
|
442 | coarse_time => coarse_time, | |
443 | fine_time => fine_time, |
|
443 | fine_time => fine_time, | |
444 |
data_shaping_BW => bias_fail_sw_sig |
|
444 | data_shaping_BW => bias_fail_sw_sig); | |
445 | observation_vector_0=> observation_vector_0, |
|
|||
446 | observation_vector_1 => observation_vector_1, |
|
|||
447 | observation_reg => observation_reg); |
|
|||
448 |
|
445 | |||
449 | all_sample: FOR I IN 7 DOWNTO 0 GENERATE |
|
446 | all_sample: FOR I IN 7 DOWNTO 0 GENERATE | |
450 | sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; |
|
447 | sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; | |
451 | END GENERATE all_sample; |
|
448 | END GENERATE all_sample; | |
452 |
|
449 | |||
453 |
|
450 | |||
454 |
|
451 | |||
455 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 |
|
452 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 | |
456 | GENERIC MAP( |
|
453 | GENERIC MAP( | |
457 | ChannelCount => 8, |
|
454 | ChannelCount => 8, | |
458 | SampleNbBits => 14, |
|
455 | SampleNbBits => 14, | |
459 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 |
|
456 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 | |
460 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 |
|
457 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 | |
461 | PORT MAP ( |
|
458 | PORT MAP ( | |
462 | -- CONV |
|
459 | -- CONV | |
463 | cnv_clk => clk_24, |
|
460 | cnv_clk => clk_24, | |
464 | cnv_rstn => reset, |
|
461 | cnv_rstn => reset, | |
465 | cnv => ADC_nCS_sig, |
|
462 | cnv => ADC_nCS_sig, | |
466 | -- DATA |
|
463 | -- DATA | |
467 | clk => clk_25, |
|
464 | clk => clk_25, | |
468 | rstn => reset, |
|
465 | rstn => reset, | |
469 | sck => ADC_CLK_sig, |
|
466 | sck => ADC_CLK_sig, | |
470 | sdo => ADC_SDO_sig, |
|
467 | sdo => ADC_SDO_sig, | |
471 | -- SAMPLE |
|
468 | -- SAMPLE | |
472 | sample => sample, |
|
469 | sample => sample, | |
473 | sample_val => sample_val); |
|
470 | sample_val => sample_val); | |
474 |
|
471 | |||
475 | --IO10 <= ADC_SDO_sig(5); |
|
472 | --IO10 <= ADC_SDO_sig(5); | |
476 | --IO9 <= ADC_SDO_sig(4); |
|
473 | --IO9 <= ADC_SDO_sig(4); | |
477 | --IO8 <= ADC_SDO_sig(3); |
|
474 | --IO8 <= ADC_SDO_sig(3); | |
478 |
|
475 | |||
479 | ADC_nCS <= ADC_nCS_sig; |
|
476 | ADC_nCS <= ADC_nCS_sig; | |
480 | ADC_CLK <= ADC_CLK_sig; |
|
477 | ADC_CLK <= ADC_CLK_sig; | |
481 | ADC_SDO_sig <= ADC_SDO; |
|
478 | ADC_SDO_sig <= ADC_SDO; | |
482 |
|
479 | |||
483 | ---------------------------------------------------------------------- |
|
480 | ---------------------------------------------------------------------- | |
484 | --- GPIO ----------------------------------------------------------- |
|
481 | --- GPIO ----------------------------------------------------------- | |
485 | ---------------------------------------------------------------------- |
|
482 | ---------------------------------------------------------------------- | |
486 |
|
483 | |||
487 | grgpio0 : grgpio |
|
484 | grgpio0 : grgpio | |
488 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) |
|
485 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) | |
489 | PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); |
|
486 | PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); | |
490 |
|
487 | |||
491 | --pio_pad_0 : iopad |
|
488 | --pio_pad_0 : iopad | |
492 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
489 | -- GENERIC MAP (tech => CFG_PADTECH) | |
493 | -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); |
|
490 | -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); | |
494 | --pio_pad_1 : iopad |
|
491 | --pio_pad_1 : iopad | |
495 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
492 | -- GENERIC MAP (tech => CFG_PADTECH) | |
496 | -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); |
|
493 | -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); | |
497 | --pio_pad_2 : iopad |
|
494 | --pio_pad_2 : iopad | |
498 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
495 | -- GENERIC MAP (tech => CFG_PADTECH) | |
499 | -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); |
|
496 | -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); | |
500 | --pio_pad_3 : iopad |
|
497 | --pio_pad_3 : iopad | |
501 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
498 | -- GENERIC MAP (tech => CFG_PADTECH) | |
502 | -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); |
|
499 | -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); | |
503 | --pio_pad_4 : iopad |
|
500 | --pio_pad_4 : iopad | |
504 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
501 | -- GENERIC MAP (tech => CFG_PADTECH) | |
505 | -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); |
|
502 | -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); | |
506 | --pio_pad_5 : iopad |
|
503 | --pio_pad_5 : iopad | |
507 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
504 | -- GENERIC MAP (tech => CFG_PADTECH) | |
508 | -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); |
|
505 | -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); | |
509 | --pio_pad_6 : iopad |
|
506 | --pio_pad_6 : iopad | |
510 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
507 | -- GENERIC MAP (tech => CFG_PADTECH) | |
511 | -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); |
|
508 | -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); | |
512 | --pio_pad_7 : iopad |
|
509 | --pio_pad_7 : iopad | |
513 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
510 | -- GENERIC MAP (tech => CFG_PADTECH) | |
514 | -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); |
|
511 | -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); | |
515 |
|
512 | |||
516 | PROCESS (clk_25, reset) |
|
513 | PROCESS (clk_25, reset) | |
517 | BEGIN -- PROCESS |
|
514 | BEGIN -- PROCESS | |
518 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
515 | IF reset = '0' THEN -- asynchronous reset (active low) | |
519 | IO0 <= '0'; |
|
516 | IO0 <= '0'; | |
520 | IO1 <= '0'; |
|
517 | IO1 <= '0'; | |
521 | IO2 <= '0'; |
|
518 | IO2 <= '0'; | |
522 | IO3 <= '0'; |
|
519 | IO3 <= '0'; | |
523 | IO4 <= '0'; |
|
520 | IO4 <= '0'; | |
524 | IO5 <= '0'; |
|
521 | IO5 <= '0'; | |
525 | IO6 <= '0'; |
|
522 | IO6 <= '0'; | |
526 | IO7 <= '0'; |
|
523 | IO7 <= '0'; | |
527 | IO8 <= '0'; |
|
524 | IO8 <= '0'; | |
528 | IO9 <= '0'; |
|
525 | IO9 <= '0'; | |
529 | IO10 <= '0'; |
|
526 | IO10 <= '0'; | |
530 | IO11 <= '0'; |
|
527 | IO11 <= '0'; | |
531 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge |
|
528 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge | |
532 | CASE gpioo.dout(2 DOWNTO 0) IS |
|
529 | CASE gpioo.dout(2 DOWNTO 0) IS | |
533 | WHEN "011" => |
|
530 | WHEN "011" => | |
534 | IO0 <= observation_reg(0 ); |
|
531 | IO0 <= observation_reg(0 ); | |
535 | IO1 <= observation_reg(1 ); |
|
532 | IO1 <= observation_reg(1 ); | |
536 | IO2 <= observation_reg(2 ); |
|
533 | IO2 <= observation_reg(2 ); | |
537 | IO3 <= observation_reg(3 ); |
|
534 | IO3 <= observation_reg(3 ); | |
538 | IO4 <= observation_reg(4 ); |
|
535 | IO4 <= observation_reg(4 ); | |
539 | IO5 <= observation_reg(5 ); |
|
536 | IO5 <= observation_reg(5 ); | |
540 | IO6 <= observation_reg(6 ); |
|
537 | IO6 <= observation_reg(6 ); | |
541 | IO7 <= observation_reg(7 ); |
|
538 | IO7 <= observation_reg(7 ); | |
542 | IO8 <= observation_reg(8 ); |
|
539 | IO8 <= observation_reg(8 ); | |
543 | IO9 <= observation_reg(9 ); |
|
540 | IO9 <= observation_reg(9 ); | |
544 | IO10 <= observation_reg(10); |
|
541 | IO10 <= observation_reg(10); | |
545 | IO11 <= observation_reg(11); |
|
542 | IO11 <= observation_reg(11); | |
546 | WHEN "001" => |
|
543 | WHEN "001" => | |
547 | IO0 <= observation_reg(0 + 12); |
|
544 | IO0 <= observation_reg(0 + 12); | |
548 | IO1 <= observation_reg(1 + 12); |
|
545 | IO1 <= observation_reg(1 + 12); | |
549 | IO2 <= observation_reg(2 + 12); |
|
546 | IO2 <= observation_reg(2 + 12); | |
550 | IO3 <= observation_reg(3 + 12); |
|
547 | IO3 <= observation_reg(3 + 12); | |
551 | IO4 <= observation_reg(4 + 12); |
|
548 | IO4 <= observation_reg(4 + 12); | |
552 | IO5 <= observation_reg(5 + 12); |
|
549 | IO5 <= observation_reg(5 + 12); | |
553 | IO6 <= observation_reg(6 + 12); |
|
550 | IO6 <= observation_reg(6 + 12); | |
554 | IO7 <= observation_reg(7 + 12); |
|
551 | IO7 <= observation_reg(7 + 12); | |
555 | IO8 <= observation_reg(8 + 12); |
|
552 | IO8 <= observation_reg(8 + 12); | |
556 | IO9 <= observation_reg(9 + 12); |
|
553 | IO9 <= observation_reg(9 + 12); | |
557 | IO10 <= observation_reg(10 + 12); |
|
554 | IO10 <= observation_reg(10 + 12); | |
558 | IO11 <= observation_reg(11 + 12); |
|
555 | IO11 <= observation_reg(11 + 12); | |
559 | WHEN "010" => |
|
556 | WHEN "010" => | |
560 | IO0 <= observation_reg(0 + 12 + 12); |
|
557 | IO0 <= observation_reg(0 + 12 + 12); | |
561 | IO1 <= observation_reg(1 + 12 + 12); |
|
558 | IO1 <= observation_reg(1 + 12 + 12); | |
562 | IO2 <= observation_reg(2 + 12 + 12); |
|
559 | IO2 <= observation_reg(2 + 12 + 12); | |
563 | IO3 <= observation_reg(3 + 12 + 12); |
|
560 | IO3 <= observation_reg(3 + 12 + 12); | |
564 | IO4 <= observation_reg(4 + 12 + 12); |
|
561 | IO4 <= observation_reg(4 + 12 + 12); | |
565 | IO5 <= observation_reg(5 + 12 + 12); |
|
562 | IO5 <= observation_reg(5 + 12 + 12); | |
566 | IO6 <= observation_reg(6 + 12 + 12); |
|
563 | IO6 <= observation_reg(6 + 12 + 12); | |
567 | IO7 <= observation_reg(7 + 12 + 12); |
|
564 | IO7 <= observation_reg(7 + 12 + 12); | |
568 | IO8 <= '0'; |
|
565 | IO8 <= '0'; | |
569 | IO9 <= '0'; |
|
566 | IO9 <= '0'; | |
570 | IO10 <= '0'; |
|
567 | IO10 <= '0'; | |
571 | IO11 <= '0'; |
|
568 | IO11 <= '0'; | |
572 | WHEN "000" => |
|
569 | WHEN "000" => | |
573 | IO0 <= observation_vector_0(0 ); |
|
570 | IO0 <= observation_vector_0(0 ); | |
574 | IO1 <= observation_vector_0(1 ); |
|
571 | IO1 <= observation_vector_0(1 ); | |
575 | IO2 <= observation_vector_0(2 ); |
|
572 | IO2 <= observation_vector_0(2 ); | |
576 | IO3 <= observation_vector_0(3 ); |
|
573 | IO3 <= observation_vector_0(3 ); | |
577 | IO4 <= observation_vector_0(4 ); |
|
574 | IO4 <= observation_vector_0(4 ); | |
578 | IO5 <= observation_vector_0(5 ); |
|
575 | IO5 <= observation_vector_0(5 ); | |
579 | IO6 <= observation_vector_0(6 ); |
|
576 | IO6 <= observation_vector_0(6 ); | |
580 | IO7 <= observation_vector_0(7 ); |
|
577 | IO7 <= observation_vector_0(7 ); | |
581 | IO8 <= observation_vector_0(8 ); |
|
578 | IO8 <= observation_vector_0(8 ); | |
582 | IO9 <= observation_vector_0(9 ); |
|
579 | IO9 <= observation_vector_0(9 ); | |
583 | IO10 <= observation_vector_0(10); |
|
580 | IO10 <= observation_vector_0(10); | |
584 | IO11 <= observation_vector_0(11); |
|
581 | IO11 <= observation_vector_0(11); | |
585 | WHEN "100" => |
|
582 | WHEN "100" => | |
586 | IO0 <= observation_vector_1(0 ); |
|
583 | IO0 <= observation_vector_1(0 ); | |
587 | IO1 <= observation_vector_1(1 ); |
|
584 | IO1 <= observation_vector_1(1 ); | |
588 | IO2 <= observation_vector_1(2 ); |
|
585 | IO2 <= observation_vector_1(2 ); | |
589 | IO3 <= observation_vector_1(3 ); |
|
586 | IO3 <= observation_vector_1(3 ); | |
590 | IO4 <= observation_vector_1(4 ); |
|
587 | IO4 <= observation_vector_1(4 ); | |
591 | IO5 <= observation_vector_1(5 ); |
|
588 | IO5 <= observation_vector_1(5 ); | |
592 | IO6 <= observation_vector_1(6 ); |
|
589 | IO6 <= observation_vector_1(6 ); | |
593 | IO7 <= observation_vector_1(7 ); |
|
590 | IO7 <= observation_vector_1(7 ); | |
594 | IO8 <= observation_vector_1(8 ); |
|
591 | IO8 <= observation_vector_1(8 ); | |
595 | IO9 <= observation_vector_1(9 ); |
|
592 | IO9 <= observation_vector_1(9 ); | |
596 | IO10 <= observation_vector_1(10); |
|
593 | IO10 <= observation_vector_1(10); | |
597 | IO11 <= observation_vector_1(11); |
|
594 | IO11 <= observation_vector_1(11); | |
598 | WHEN OTHERS => NULL; |
|
595 | WHEN OTHERS => NULL; | |
599 | END CASE; |
|
596 | END CASE; | |
600 |
|
597 | |||
601 | END IF; |
|
598 | END IF; | |
602 | END PROCESS; |
|
599 | END PROCESS; | |
603 |
|
600 | |||
604 | END beh; |
|
601 | END beh; |
@@ -1,564 +1,571 | |||||
1 | VHDLIB=../.. |
|
1 | VHDLIB=../.. | |
2 | SCRIPTSDIR=$(VHDLIB)/scripts/ |
|
2 | SCRIPTSDIR=$(VHDLIB)/scripts/ | |
3 |
|
3 | |||
4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) |
|
4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) | |
5 | TOP=TB |
|
5 | TOP=TB | |
6 |
|
6 | |||
7 | CMD_VLIB=vlib |
|
7 | CMD_VLIB=vlib | |
8 | CMD_VMAP=vmap |
|
8 | CMD_VMAP=vmap | |
9 | CMD_VCOM=@vcom -quiet -93 -work |
|
9 | CMD_VCOM=@vcom -quiet -93 -work | |
10 |
|
10 | |||
11 | ################## project specific targets ########################## |
|
11 | ################## project specific targets ########################## | |
12 |
|
12 | |||
13 | all: |
|
13 | all: | |
14 | @echo "make vsim" |
|
14 | @echo "make vsim" | |
15 | @echo "make libs" |
|
15 | @echo "make libs" | |
16 | @echo "make clean" |
|
16 | @echo "make clean" | |
17 | @echo "make vcom_grlib vcom_lpp vcom_tb" |
|
17 | @echo "make vcom_grlib vcom_lpp vcom_tb" | |
18 |
|
18 | |||
19 | run: |
|
19 | run: | |
20 | @vsim work.TB -do run.do |
|
20 | @vsim work.TB -do run.do | |
21 | # @vsim work.TB |
|
21 | # @vsim work.TB | |
22 | # @vsim lpp.lpp_lfr_ms |
|
22 | # @vsim lpp.lpp_lfr_ms | |
23 |
|
23 | |||
24 | vsim: libs vcom run |
|
24 | vsim: libs vcom run | |
25 |
|
25 | |||
26 | libs: |
|
26 | libs: | |
27 | @$(CMD_VLIB) modelsim |
|
27 | @$(CMD_VLIB) modelsim | |
28 | @$(CMD_VMAP) modelsim modelsim |
|
28 | @$(CMD_VMAP) modelsim modelsim | |
29 | @$(CMD_VLIB) modelsim/techmap |
|
29 | @$(CMD_VLIB) modelsim/techmap | |
30 | @$(CMD_VMAP) techmap modelsim/techmap |
|
30 | @$(CMD_VMAP) techmap modelsim/techmap | |
31 | @$(CMD_VLIB) modelsim/grlib |
|
31 | @$(CMD_VLIB) modelsim/grlib | |
32 | @$(CMD_VMAP) grlib modelsim/grlib |
|
32 | @$(CMD_VMAP) grlib modelsim/grlib | |
33 | @$(CMD_VLIB) modelsim/gaisler |
|
33 | @$(CMD_VLIB) modelsim/gaisler | |
34 | @$(CMD_VMAP) gaisler modelsim/gaisler |
|
34 | @$(CMD_VMAP) gaisler modelsim/gaisler | |
35 | @$(CMD_VLIB) modelsim/work |
|
35 | @$(CMD_VLIB) modelsim/work | |
36 | @$(CMD_VMAP) work modelsim/work |
|
36 | @$(CMD_VMAP) work modelsim/work | |
37 | @$(CMD_VLIB) modelsim/lpp |
|
37 | @$(CMD_VLIB) modelsim/lpp | |
38 | @$(CMD_VMAP) lpp modelsim/lpp |
|
38 | @$(CMD_VMAP) lpp modelsim/lpp | |
39 | @$(CMD_VLIB) modelsim/esa |
|
39 | @$(CMD_VLIB) modelsim/esa | |
40 | @$(CMD_VMAP) esa modelsim/esa |
|
40 | @$(CMD_VMAP) esa modelsim/esa | |
41 | @echo "libs done" |
|
41 | @echo "libs done" | |
42 |
|
42 | |||
43 |
|
43 | |||
44 | clean: |
|
44 | clean: | |
45 | @rm -Rf modelsim |
|
45 | @rm -Rf modelsim | |
46 | @rm -Rf modelsim.ini |
|
46 | @rm -Rf modelsim.ini | |
47 | @rm -Rf *~ |
|
47 | @rm -Rf *~ | |
48 | @rm -Rf transcript |
|
48 | @rm -Rf transcript | |
49 | @rm -Rf wlft* |
|
49 | @rm -Rf wlft* | |
50 | @rm -Rf *.wlf |
|
50 | @rm -Rf *.wlf | |
51 | @rm -Rf vish_stacktrace.vstf |
|
51 | @rm -Rf vish_stacktrace.vstf | |
52 | @rm -Rf libs.do |
|
52 | @rm -Rf libs.do | |
53 |
|
53 | |||
54 | vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_esa vcom_tb |
|
54 | vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_esa vcom_tb | |
55 |
|
55 | |||
56 |
|
56 | |||
57 | vcom_tb: |
|
57 | vcom_tb: | |
58 | ## $(CMD_VCOM) lpp lpp_memory.vhd |
|
58 | ## $(CMD_VCOM) lpp lpp_memory.vhd | |
59 | ## $(CMD_VCOM) lpp lppFIFOxN.vhd |
|
59 | ## $(CMD_VCOM) lpp lppFIFOxN.vhd | |
60 | ## $(CMD_VCOM) lpp lpp_FIFO.vhd |
|
60 | ## $(CMD_VCOM) lpp lpp_FIFO.vhd | |
61 | ## $(CMD_VCOM) lpp lpp_lfr_ms.vhd |
|
61 | ## $(CMD_VCOM) lpp lpp_lfr_ms.vhd | |
62 | $(CMD_VCOM) lpp testbench_package.vhd |
|
62 | $(CMD_VCOM) lpp testbench_package.vhd | |
63 | $(CMD_VCOM) work TB.vhd |
|
63 | $(CMD_VCOM) work TB.vhd | |
64 | @echo "vcom done" |
|
64 | @echo "vcom done" | |
65 |
|
65 | |||
66 | vcom_esa: |
|
66 | vcom_esa: | |
67 | $(CMD_VCOM) esa $(GRLIB)/lib/esa/memoryctrl/memoryctrl.vhd |
|
67 | $(CMD_VCOM) esa $(GRLIB)/lib/esa/memoryctrl/memoryctrl.vhd | |
68 | $(CMD_VCOM) esa $(GRLIB)/lib/esa/memoryctrl/mctrl.vhd |
|
68 | $(CMD_VCOM) esa $(GRLIB)/lib/esa/memoryctrl/mctrl.vhd | |
69 | @echo "lib esa done" |
|
69 | @echo "lib esa done" | |
70 |
|
70 | |||
71 | vcom_grlib: |
|
71 | vcom_grlib: | |
72 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd |
|
72 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd | |
73 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd |
|
73 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd | |
74 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd |
|
74 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd | |
75 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd |
|
75 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd | |
76 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd |
|
76 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd | |
77 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd |
|
77 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd | |
78 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd |
|
78 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd | |
79 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd |
|
79 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd | |
80 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd |
|
80 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd | |
81 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd |
|
81 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd | |
82 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd |
|
82 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd | |
83 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd |
|
83 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd | |
84 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd |
|
84 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd | |
85 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd |
|
85 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd | |
86 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd |
|
86 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd | |
87 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd |
|
87 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd | |
88 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd |
|
88 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd | |
89 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd |
|
89 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd | |
90 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd |
|
90 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd | |
91 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd |
|
91 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd | |
92 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd |
|
92 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd | |
93 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd |
|
93 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd | |
94 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd |
|
94 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd | |
95 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd |
|
95 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd | |
96 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd |
|
96 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd | |
97 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd |
|
97 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd | |
98 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd |
|
98 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd | |
99 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd |
|
99 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd | |
100 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd |
|
100 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd | |
101 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd |
|
101 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd | |
102 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd |
|
102 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd | |
103 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd |
|
103 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd | |
104 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd |
|
104 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd | |
105 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd |
|
105 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd | |
106 | @echo "vcom grlib done" |
|
106 | @echo "vcom grlib done" | |
107 |
|
107 | |||
108 | vcom_gaisler: |
|
108 | vcom_gaisler: | |
109 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd |
|
109 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd | |
110 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd |
|
110 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd | |
111 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd |
|
111 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd | |
112 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd |
|
112 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd | |
113 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd |
|
113 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd | |
114 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd |
|
114 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd | |
115 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd |
|
115 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd | |
116 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd |
|
116 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd | |
117 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd |
|
117 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd | |
118 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd |
|
118 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd | |
119 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd |
|
119 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd | |
120 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd |
|
120 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd | |
121 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd |
|
121 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd | |
122 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd |
|
122 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd | |
123 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd |
|
123 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd | |
124 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd |
|
124 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd | |
125 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd |
|
125 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd | |
126 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd |
|
126 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd | |
127 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd |
|
127 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd | |
128 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd |
|
128 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd | |
129 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd |
|
129 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd | |
130 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd |
|
130 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd | |
131 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd |
|
131 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd | |
132 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd |
|
132 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd | |
133 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd |
|
133 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd | |
134 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd |
|
134 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd | |
135 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd |
|
135 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd | |
136 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd |
|
136 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd | |
137 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd |
|
137 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd | |
138 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd |
|
138 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd | |
139 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd |
|
139 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd | |
140 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd |
|
140 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd | |
141 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd |
|
141 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd | |
142 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd |
|
142 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd | |
143 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd |
|
143 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd | |
144 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd |
|
144 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd | |
145 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd |
|
145 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd | |
146 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd |
|
146 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd | |
147 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd |
|
147 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd | |
148 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd |
|
148 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd | |
149 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd |
|
149 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd | |
150 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd |
|
150 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd | |
151 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd |
|
151 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd | |
152 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd |
|
152 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd | |
153 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd |
|
153 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd | |
154 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd |
|
154 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd | |
155 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd |
|
155 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd | |
156 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd |
|
156 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd | |
157 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd |
|
157 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd | |
158 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd |
|
158 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd | |
159 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd |
|
159 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd | |
160 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd |
|
160 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd | |
161 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd |
|
161 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd | |
162 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd |
|
162 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd | |
163 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd |
|
163 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd | |
164 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd |
|
164 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd | |
165 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd |
|
165 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd | |
166 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd |
|
166 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd | |
167 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd |
|
167 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd | |
168 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd |
|
168 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd | |
169 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd |
|
169 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd | |
170 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd |
|
170 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd | |
171 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd |
|
171 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd | |
172 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd |
|
172 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd | |
173 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd |
|
173 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd | |
174 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd |
|
174 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd | |
175 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd |
|
175 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd | |
176 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd |
|
176 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd | |
177 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd |
|
177 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd | |
178 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd |
|
178 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd | |
179 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd |
|
179 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd | |
180 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd |
|
180 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd | |
181 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd |
|
181 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd | |
182 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd |
|
182 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd | |
183 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd |
|
183 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd | |
184 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd |
|
184 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd | |
185 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd |
|
185 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd | |
186 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd |
|
186 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd | |
187 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd |
|
187 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd | |
188 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd |
|
188 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd | |
189 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd |
|
189 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd | |
190 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd |
|
190 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd | |
191 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd |
|
191 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd | |
192 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd |
|
192 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd | |
193 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd |
|
193 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd | |
194 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd |
|
194 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd | |
195 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd |
|
195 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd | |
196 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd |
|
196 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd | |
197 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd |
|
197 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd | |
198 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd |
|
198 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd | |
199 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd |
|
199 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd | |
200 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd |
|
200 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd | |
201 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd |
|
201 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd | |
202 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd |
|
202 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd | |
203 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd |
|
203 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd | |
204 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd |
|
204 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd | |
205 | ## $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd |
|
205 | ## $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd | |
206 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd |
|
206 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd | |
207 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd |
|
207 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd | |
208 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd |
|
208 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd | |
209 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd |
|
209 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd | |
210 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd |
|
210 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd | |
211 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd |
|
211 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd | |
212 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd |
|
212 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd | |
213 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd |
|
213 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd | |
214 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd |
|
214 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd | |
215 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd |
|
215 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd | |
216 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd |
|
216 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd | |
217 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd |
|
217 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd | |
218 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd |
|
218 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd | |
219 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd |
|
219 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd | |
220 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd |
|
220 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd | |
221 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd |
|
221 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd | |
222 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd |
|
222 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd | |
223 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd |
|
223 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd | |
224 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd |
|
224 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd | |
225 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd |
|
225 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd | |
226 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd |
|
226 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd | |
227 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd |
|
227 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd | |
228 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd |
|
228 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd | |
229 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd |
|
229 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd | |
230 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd |
|
230 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd | |
231 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd |
|
231 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd | |
232 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd |
|
232 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd | |
233 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd |
|
233 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd | |
234 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd |
|
234 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd | |
235 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd |
|
235 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd | |
236 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd |
|
236 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd | |
237 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd |
|
237 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd | |
238 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd |
|
238 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd | |
239 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd |
|
239 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd | |
240 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd |
|
240 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd | |
241 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd |
|
241 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd | |
242 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd |
|
242 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd | |
243 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd |
|
243 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd | |
244 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd |
|
244 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd | |
245 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd |
|
245 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd | |
246 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd |
|
246 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd | |
247 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd |
|
247 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd | |
248 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd |
|
248 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd | |
249 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd |
|
249 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd | |
250 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd |
|
250 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd | |
251 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd |
|
251 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd | |
252 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd |
|
252 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd | |
253 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd |
|
253 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd | |
254 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd |
|
254 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd | |
255 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd |
|
255 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd | |
256 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd |
|
256 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd | |
257 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd |
|
257 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd | |
258 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd |
|
258 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd | |
259 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd |
|
259 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd | |
260 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd |
|
260 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd | |
261 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd |
|
261 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd | |
262 | @echo "vcom gaisler done" |
|
262 | @echo "vcom gaisler done" | |
263 |
|
263 | |||
264 | vcom_techmap: |
|
264 | vcom_techmap: | |
265 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd |
|
265 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd | |
266 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd |
|
266 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd | |
267 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd |
|
267 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd | |
268 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd |
|
268 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd | |
269 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd |
|
269 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd | |
270 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd |
|
270 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd | |
271 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd |
|
271 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd | |
272 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd |
|
272 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd | |
273 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd |
|
273 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd | |
274 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd |
|
274 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd | |
275 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd |
|
275 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd | |
276 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd |
|
276 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd | |
277 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd |
|
277 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd | |
278 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd |
|
278 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd | |
279 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd |
|
279 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd | |
280 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd |
|
280 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd | |
281 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd |
|
281 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd | |
282 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd |
|
282 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd | |
283 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd |
|
283 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd | |
284 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd |
|
284 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd | |
285 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd |
|
285 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd | |
286 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd |
|
286 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd | |
287 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd |
|
287 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd | |
288 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd |
|
288 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd | |
289 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd |
|
289 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd | |
290 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd |
|
290 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd | |
291 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd |
|
291 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd | |
292 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd |
|
292 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd | |
293 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd |
|
293 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd | |
294 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd |
|
294 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd | |
295 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd |
|
295 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd | |
296 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd |
|
296 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd | |
297 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd |
|
297 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd | |
298 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd |
|
298 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd | |
299 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd |
|
299 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd | |
300 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd |
|
300 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd | |
301 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd |
|
301 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd | |
302 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd |
|
302 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd | |
303 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd |
|
303 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd | |
304 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd |
|
304 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd | |
305 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd |
|
305 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd | |
306 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd |
|
306 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd | |
307 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd |
|
307 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd | |
308 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd |
|
308 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd | |
309 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd |
|
309 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd | |
310 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd |
|
310 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd | |
311 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd |
|
311 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd | |
312 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd |
|
312 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd | |
313 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd |
|
313 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd | |
314 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd |
|
314 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd | |
315 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd |
|
315 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd | |
316 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd |
|
316 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd | |
317 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd |
|
317 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd | |
318 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd |
|
318 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd | |
319 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd |
|
319 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd | |
320 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd |
|
320 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd | |
321 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd |
|
321 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd | |
322 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd |
|
322 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd | |
323 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd |
|
323 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd | |
324 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd |
|
324 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd | |
325 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd |
|
325 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd | |
326 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd |
|
326 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd | |
327 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd |
|
327 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd | |
328 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd |
|
328 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd | |
329 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd |
|
329 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd | |
330 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd |
|
330 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd | |
331 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd |
|
331 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd | |
332 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd |
|
332 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd | |
333 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd |
|
333 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd | |
334 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd |
|
334 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd | |
335 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd |
|
335 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd | |
336 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd |
|
336 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd | |
337 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd |
|
337 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd | |
338 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd |
|
338 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd | |
339 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd |
|
339 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd | |
340 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd |
|
340 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd | |
341 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd |
|
341 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd | |
342 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd |
|
342 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd | |
343 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd |
|
343 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd | |
344 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd |
|
344 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd | |
345 | @echo "vcom techmap done" |
|
345 | @echo "vcom techmap done" | |
346 |
|
346 | |||
347 | vcom_lpp: |
|
347 | vcom_lpp: | |
348 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/apb_devices_list.vhd |
|
348 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/apb_devices_list.vhd | |
349 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd |
|
349 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd | |
350 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd |
|
350 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd | |
351 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd |
|
351 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd | |
352 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd |
|
352 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd | |
353 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd |
|
353 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd | |
354 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd |
|
354 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd | |
355 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd |
|
355 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd | |
356 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd |
|
356 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd | |
357 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd |
|
357 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd | |
358 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd |
|
358 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd | |
359 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd |
|
359 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd | |
360 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd |
|
360 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd | |
361 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd |
|
361 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd | |
362 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd |
|
362 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd | |
363 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd |
|
363 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd | |
364 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd |
|
364 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd | |
365 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd |
|
365 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd | |
366 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd |
|
366 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd | |
367 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd |
|
367 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd | |
368 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd |
|
368 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd | |
369 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd |
|
369 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd | |
370 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd |
|
370 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd | |
371 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd |
|
371 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd | |
372 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd |
|
372 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd | |
373 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd |
|
373 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd | |
374 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd |
|
374 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd | |
375 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd |
|
375 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd | |
376 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd |
|
376 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd | |
377 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd |
|
377 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd | |
378 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd |
|
378 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd | |
379 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd |
|
379 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd | |
380 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd |
|
380 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd | |
381 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd |
|
381 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd | |
382 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd |
|
382 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd | |
383 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd |
|
383 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd | |
384 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd |
|
384 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd | |
385 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd |
|
385 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd | |
386 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd |
|
386 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd | |
387 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd |
|
387 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd | |
388 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd |
|
388 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd | |
389 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd |
|
389 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd | |
390 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd |
|
390 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd | |
391 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd |
|
391 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd | |
392 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd |
|
392 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd | |
393 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd |
|
393 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd | |
394 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd |
|
394 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd | |
395 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd |
|
395 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd | |
396 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd |
|
396 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd | |
397 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_memory.vhd |
|
397 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_memory.vhd | |
398 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lppFIFOxN.vhd |
|
398 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lppFIFOxN.vhd | |
399 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO.vhd |
|
399 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO.vhd | |
400 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO_4_Shared.vhd |
|
400 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO_4_Shared.vhd | |
401 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO_control.vhd |
|
401 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO_control.vhd | |
402 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO_4_Shared_headreg_latency_0.vhd |
|
402 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO_4_Shared_headreg_latency_0.vhd | |
403 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO_4_Shared_headreg_latency_1.vhd |
|
403 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO_4_Shared_headreg_latency_1.vhd | |
404 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd |
|
404 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd | |
405 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_package.vhd |
|
405 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_package.vhd | |
406 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_switch_f0.vhd |
|
406 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_switch_f0.vhd | |
407 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd |
|
407 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd | |
408 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_control.vhd |
|
408 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_control.vhd | |
409 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd |
|
409 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd | |
410 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd |
|
410 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd | |
411 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/general_purpose.vhd |
|
411 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/general_purpose.vhd | |
412 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/ADDRcntr.vhd |
|
412 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/ADDRcntr.vhd | |
413 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/ALU.vhd |
|
413 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/ALU.vhd | |
414 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Adder.vhd |
|
414 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Adder.vhd | |
415 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Clk_Divider2.vhd |
|
415 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Clk_Divider2.vhd | |
416 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Clk_divider.vhd |
|
416 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Clk_divider.vhd | |
417 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MAC.vhd |
|
417 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MAC.vhd | |
418 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MAC_CONTROLER.vhd |
|
418 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MAC_CONTROLER.vhd | |
419 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MAC_MUX.vhd |
|
419 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MAC_MUX.vhd | |
420 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MAC_MUX2.vhd |
|
420 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MAC_MUX2.vhd | |
421 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MAC_REG.vhd |
|
421 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MAC_REG.vhd | |
422 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MUX2.vhd |
|
422 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MUX2.vhd | |
423 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MUXN.vhd |
|
423 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MUXN.vhd | |
424 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Multiplier.vhd |
|
424 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Multiplier.vhd | |
425 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/REG.vhd |
|
425 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/REG.vhd | |
426 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/SYNC_FF.vhd |
|
426 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/SYNC_FF.vhd | |
427 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Shifter.vhd |
|
427 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Shifter.vhd | |
428 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/TwoComplementer.vhd |
|
428 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/TwoComplementer.vhd | |
429 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Clock_Divider.vhd |
|
429 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Clock_Divider.vhd | |
430 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/lpp_front_to_level.vhd |
|
430 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/lpp_front_to_level.vhd | |
431 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/lpp_front_detection.vhd |
|
431 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/lpp_front_detection.vhd | |
432 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/lpp_front_positive_detection.vhd |
|
432 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/lpp_front_positive_detection.vhd | |
433 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/SYNC_VALID_BIT.vhd |
|
433 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/SYNC_VALID_BIT.vhd | |
434 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/RR_Arbiter_4.vhd |
|
434 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/RR_Arbiter_4.vhd | |
435 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/general_counter.vhd |
|
435 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/general_counter.vhd | |
436 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/apb_devices_list.vhd |
|
436 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/apb_devices_list.vhd | |
437 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd |
|
437 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd | |
438 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd |
|
438 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd | |
439 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd |
|
439 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd | |
440 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM.vhd |
|
440 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM.vhd | |
441 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd |
|
441 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd | |
442 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CTRLR_v2.vhd |
|
442 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CTRLR_v2.vhd | |
443 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd |
|
443 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd | |
444 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd |
|
444 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd | |
445 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd |
|
445 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd | |
446 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_downsampling/Downsampling.vhd |
|
446 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_downsampling/Downsampling.vhd | |
447 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd |
|
447 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd | |
448 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lfr_time_management/lpp_lfr_time_management.vhd |
|
448 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lfr_time_management/lpp_lfr_time_management.vhd | |
449 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lfr_time_management/apb_lfr_time_management.vhd |
|
449 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lfr_time_management/apb_lfr_time_management.vhd | |
450 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lfr_time_management/lfr_time_management.vhd |
|
450 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lfr_time_management/lfr_time_management.vhd | |
451 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lfr_time_management/fine_time_counter.vhd |
|
451 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lfr_time_management/fine_time_counter.vhd | |
452 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lfr_time_management/coarse_time_counter.vhd |
|
452 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lfr_time_management/coarse_time_counter.vhd | |
453 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd |
|
453 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd | |
454 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/RHF1401.vhd |
|
454 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/RHF1401.vhd | |
455 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401.vhd |
|
455 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401.vhd | |
456 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/TestModule_RHF1401.vhd |
|
456 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/TestModule_RHF1401.vhd | |
457 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/top_ad_conv_ADS7886_v2.vhd |
|
457 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/top_ad_conv_ADS7886_v2.vhd | |
458 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/ADS7886_drvr_v2.vhd |
|
458 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/ADS7886_drvr_v2.vhd | |
459 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_spectral_matrix/spectral_matrix_package.vhd |
|
459 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_spectral_matrix/spectral_matrix_package.vhd | |
460 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_spectral_matrix/MS_calculation.vhd |
|
460 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_spectral_matrix/MS_calculation.vhd | |
461 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_spectral_matrix/MS_control.vhd |
|
461 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_spectral_matrix/MS_control.vhd | |
462 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_spectral_matrix/spectral_matrix_switch_f0.vhd |
|
462 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_spectral_matrix/spectral_matrix_switch_f0.vhd | |
463 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_spectral_matrix/spectral_matrix_time_managment.vhd |
|
463 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_spectral_matrix/spectral_matrix_time_managment.vhd | |
464 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_demux/DEMUX.vhd |
|
464 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_demux/DEMUX.vhd | |
465 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_demux/lpp_demux.vhd |
|
465 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_demux/lpp_demux.vhd | |
466 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_Header/lpp_Header.vhd |
|
466 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_Header/lpp_Header.vhd | |
467 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_Header/HeaderBuilder.vhd |
|
467 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_Header/HeaderBuilder.vhd | |
468 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/ALU_Driver.vhd |
|
468 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/ALU_Driver.vhd | |
469 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd |
|
469 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd | |
470 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/Dispatch.vhd |
|
470 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/Dispatch.vhd | |
471 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/DriveInputs.vhd |
|
471 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/DriveInputs.vhd | |
472 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/GetResult.vhd |
|
472 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/GetResult.vhd | |
473 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd |
|
473 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd | |
474 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/Matrix.vhd |
|
474 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/Matrix.vhd | |
475 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/SpectralMatrix.vhd |
|
475 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/SpectralMatrix.vhd | |
476 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd |
|
476 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd | |
477 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/lpp_matrix.vhd |
|
477 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/lpp_matrix.vhd | |
478 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_memory/lpp_memory.vhd |
|
478 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_memory/lpp_memory.vhd | |
479 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_memory/lpp_FIFO.vhd |
|
479 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_memory/lpp_FIFO.vhd | |
480 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_memory/lppFIFOxN.vhd |
|
480 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_memory/lppFIFOxN.vhd | |
481 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd |
|
481 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd | |
482 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/fifo_latency_correction.vhd |
|
482 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/fifo_latency_correction.vhd | |
483 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_pkg.vhd |
|
483 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_pkg.vhd | |
|
484 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd | |||
|
485 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd | |||
484 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma.vhd |
|
486 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma.vhd | |
485 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_ip.vhd |
|
487 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_ip.vhd | |
486 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd |
|
488 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd | |
487 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd |
|
489 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd | |
488 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd |
|
490 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd | |
|
491 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/DMA_SubSystem.vhd | |||
|
492 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/DMA_SubSystem_GestionBuffer.vhd | |||
|
493 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/DMA_SubSystem_Arbiter.vhd | |||
|
494 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/DMA_SubSystem_MUX.vhd | |||
489 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform.vhd |
|
495 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform.vhd | |
490 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_burst.vhd |
|
496 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_burst.vhd | |
491 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_withoutLatency.vhd |
|
497 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_withoutLatency.vhd | |
492 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_latencyCorrection.vhd |
|
498 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_latencyCorrection.vhd | |
493 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo.vhd |
|
499 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo.vhd | |
494 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter.vhd |
|
500 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter.vhd | |
495 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_ctrl.vhd |
|
501 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_ctrl.vhd | |
496 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_headreg.vhd |
|
502 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_headreg.vhd | |
497 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd |
|
503 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd | |
498 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_snapshot_controler.vhd |
|
504 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_snapshot_controler.vhd | |
499 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_genaddress.vhd |
|
505 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_genaddress.vhd | |
500 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_dma_genvalid.vhd |
|
506 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_dma_genvalid.vhd | |
501 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd |
|
507 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd | |
|
508 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fsmdma.vhd | |||
502 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd |
|
509 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd | |
503 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd |
|
510 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd | |
504 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd |
|
511 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd | |
505 | ## $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg.vhd |
|
512 | ## $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg.vhd | |
506 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_simu.vhd |
|
513 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_simu.vhd | |
507 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd |
|
514 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd | |
508 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd |
|
515 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd | |
509 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_FFT.vhd |
|
516 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_FFT.vhd | |
510 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_ms.vhd |
|
517 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_ms.vhd | |
511 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd |
|
518 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd | |
512 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_Header/lpp_Header.vhd |
|
519 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_Header/lpp_Header.vhd | |
513 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_Header/HeaderBuilder.vhd |
|
520 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_Header/HeaderBuilder.vhd | |
514 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_leon3_soc/lpp_leon3_soc_pkg.vhd |
|
521 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_leon3_soc/lpp_leon3_soc_pkg.vhd | |
515 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_leon3_soc/leon3_soc.vhd |
|
522 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_leon3_soc/leon3_soc.vhd | |
516 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr_pkg.vhd |
|
523 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr_pkg.vhd | |
517 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_debug_lfr/lpp_debug_dma_singleOrBurst.vhd |
|
524 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_debug_lfr/lpp_debug_dma_singleOrBurst.vhd | |
518 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr.vhd |
|
525 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr.vhd | |
519 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd |
|
526 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd | |
520 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr.vhd |
|
527 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr.vhd | |
521 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd |
|
528 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd | |
522 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd |
|
529 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd | |
523 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_reg_head.vhd |
|
530 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_reg_head.vhd | |
524 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd |
|
531 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd | |
525 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd |
|
532 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd | |
526 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_sim/CY7C1061DV33/package_utility.vhd |
|
533 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_sim/CY7C1061DV33/package_utility.vhd | |
527 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_sim/CY7C1061DV33/package_timing.vhd |
|
534 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_sim/CY7C1061DV33/package_timing.vhd | |
528 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_sim/CY7C1061DV33/CY7C1061DV33_pkg.vhd |
|
535 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_sim/CY7C1061DV33/CY7C1061DV33_pkg.vhd | |
529 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_sim/CY7C1061DV33/CY7C1061DV33.vhd |
|
536 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_sim/CY7C1061DV33/CY7C1061DV33.vhd | |
530 | @echo "vcom lpp done" |
|
537 | @echo "vcom lpp done" | |
531 |
|
538 | |||
532 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd |
|
539 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd | |
533 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd |
|
540 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd | |
534 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd |
|
541 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd | |
535 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd |
|
542 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd | |
536 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd |
|
543 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd | |
537 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd |
|
544 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd | |
538 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd |
|
545 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd | |
539 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd |
|
546 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd | |
540 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd |
|
547 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd | |
541 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd |
|
548 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd | |
542 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd |
|
549 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd | |
543 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd |
|
550 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd | |
544 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd |
|
551 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd | |
545 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd |
|
552 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd | |
546 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd |
|
553 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd | |
547 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd |
|
554 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd | |
548 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd |
|
555 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd | |
549 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd |
|
556 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd | |
550 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd |
|
557 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd | |
551 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd |
|
558 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd | |
552 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd |
|
559 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd | |
553 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd |
|
560 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd | |
554 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd |
|
561 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd | |
555 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd |
|
562 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd | |
556 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd |
|
563 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd | |
557 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd |
|
564 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd | |
558 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd |
|
565 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd | |
559 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd |
|
566 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd | |
560 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd |
|
567 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd | |
561 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd |
|
568 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd | |
562 | # @echo "vcom lpp done" |
|
569 | # @echo "vcom lpp done" | |
563 |
|
570 | |||
564 | #include Makefile_vcom_lpp |
|
571 | #include Makefile_vcom_lpp |
@@ -1,567 +1,615 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------- |
|
21 | ------------------------------------------------------------------------------- | |
22 |
|
22 | |||
23 | LIBRARY IEEE; |
|
23 | LIBRARY IEEE; | |
24 | USE IEEE.STD_LOGIC_1164.ALL; |
|
24 | USE IEEE.STD_LOGIC_1164.ALL; | |
25 | USE IEEE.NUMERIC_STD.ALL; |
|
25 | USE IEEE.NUMERIC_STD.ALL; | |
26 |
|
26 | |||
27 | LIBRARY lpp; |
|
27 | LIBRARY lpp; | |
28 | USE lpp.lpp_ad_conv.ALL; |
|
28 | USE lpp.lpp_ad_conv.ALL; | |
29 | USE lpp.iir_filter.ALL; |
|
29 | USE lpp.iir_filter.ALL; | |
30 | USE lpp.FILTERcfg.ALL; |
|
30 | USE lpp.FILTERcfg.ALL; | |
31 | USE lpp.lpp_memory.ALL; |
|
31 | USE lpp.lpp_memory.ALL; | |
32 | USE lpp.lpp_waveform_pkg.ALL; |
|
32 | USE lpp.lpp_waveform_pkg.ALL; | |
33 | USE lpp.lpp_dma_pkg.ALL; |
|
33 | USE lpp.lpp_dma_pkg.ALL; | |
34 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
34 | USE lpp.lpp_top_lfr_pkg.ALL; | |
35 | USE lpp.lpp_lfr_pkg.ALL; |
|
35 | USE lpp.lpp_lfr_pkg.ALL; | |
36 | USE lpp.general_purpose.ALL; |
|
36 | USE lpp.general_purpose.ALL; | |
37 | USE lpp.lpp_lfr_pkg.ALL; |
|
37 | USE lpp.lpp_lfr_pkg.ALL; | |
38 | USE lpp.lpp_memory.ALL; |
|
38 | USE lpp.lpp_memory.ALL; | |
39 | USE lpp.iir_filter.ALL; |
|
39 | USE lpp.iir_filter.ALL; | |
40 | USE lpp.spectral_matrix_package.ALL; |
|
40 | USE lpp.spectral_matrix_package.ALL; | |
41 | USE lpp.lpp_fft.ALL; |
|
41 | USE lpp.lpp_fft.ALL; | |
42 | USE lpp.fft_components.ALL; |
|
42 | USE lpp.fft_components.ALL; | |
43 | USE lpp.CY7C1061DV33_pkg.ALL; |
|
43 | USE lpp.CY7C1061DV33_pkg.ALL; | |
44 | USE lpp.testbench_package.ALL; |
|
44 | USE lpp.testbench_package.ALL; | |
45 |
|
45 | |||
46 |
|
46 | |||
47 | LIBRARY grlib; |
|
47 | LIBRARY grlib; | |
48 | USE grlib.amba.ALL; |
|
48 | USE grlib.amba.ALL; | |
49 | USE grlib.stdlib.ALL; |
|
49 | USE grlib.stdlib.ALL; | |
50 | USE grlib.devices.ALL; |
|
50 | USE grlib.devices.ALL; | |
51 | USE GRLIB.DMA2AHB_Package.ALL; |
|
51 | USE GRLIB.DMA2AHB_Package.ALL; | |
52 |
|
52 | |||
53 | LIBRARY gaisler; |
|
53 | LIBRARY gaisler; | |
54 | USE gaisler.memctrl.ALL; |
|
54 | USE gaisler.memctrl.ALL; | |
55 | USE gaisler.misc.ALL; |
|
55 | USE gaisler.misc.ALL; | |
56 |
|
56 | |||
57 | LIBRARY techmap; |
|
57 | LIBRARY techmap; | |
58 | USE techmap.gencomp.ALL; |
|
58 | USE techmap.gencomp.ALL; | |
59 |
|
59 | |||
60 | LIBRARY esa; |
|
60 | LIBRARY esa; | |
61 | USE esa.memoryctrl.ALL; |
|
61 | USE esa.memoryctrl.ALL; | |
62 |
|
62 | |||
63 |
|
63 | |||
64 | ENTITY TB IS |
|
64 | ENTITY TB IS | |
65 | END TB; |
|
65 | END TB; | |
66 |
|
66 | |||
67 |
|
67 | |||
68 | ARCHITECTURE beh OF TB IS |
|
68 | ARCHITECTURE beh OF TB IS | |
69 | CONSTANT INDEX_LFR : INTEGER := 15; |
|
69 | CONSTANT INDEX_LFR : INTEGER := 15; | |
70 | CONSTANT ADDR_LFR : INTEGER := 15; |
|
70 | CONSTANT ADDR_LFR : INTEGER := 15; | |
71 | -- REG MS |
|
71 | -- REG MS | |
72 | CONSTANT ADDR_SPECTRAL_MATRIX_CONFIG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F00"; |
|
72 | CONSTANT ADDR_SPECTRAL_MATRIX_CONFIG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F00"; | |
73 | CONSTANT ADDR_SPECTRAL_MATRIX_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F04"; |
|
73 | CONSTANT ADDR_SPECTRAL_MATRIX_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F04"; | |
74 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F08"; |
|
74 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F08"; | |
75 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F0C"; |
|
75 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F0C"; | |
76 |
|
76 | |||
77 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F10"; |
|
77 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F10"; | |
78 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F14"; |
|
78 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F14"; | |
79 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F18"; |
|
79 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F18"; | |
80 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F1C"; |
|
80 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F1C"; | |
81 |
|
81 | |||
82 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20"; |
|
82 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20"; | |
83 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24"; |
|
83 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24"; | |
84 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28"; |
|
84 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28"; | |
85 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C"; |
|
85 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C"; | |
86 |
|
86 | |||
87 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30"; |
|
87 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30"; | |
88 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34"; |
|
88 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34"; | |
89 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38"; |
|
89 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38"; | |
90 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3C"; |
|
90 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3C"; | |
91 |
|
91 | |||
92 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40"; |
|
92 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40"; | |
93 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44"; |
|
93 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44"; | |
94 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48"; |
|
94 | CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48"; | |
95 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C"; |
|
95 | CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C"; | |
96 |
|
96 | |||
|
97 | CONSTANT ADDR_SPECTRAL_MATRIX_LENGTH_MATRIX : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50"; | |||
97 | -- REG WAVEFORM |
|
98 | -- REG WAVEFORM | |
98 |
CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5 |
|
99 | CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54"; | |
99 |
CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5 |
|
100 | CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58"; | |
100 |
CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 |
|
101 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C"; | |
101 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C"; |
|
102 | ||
|
103 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F60"; | |||
|
104 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F64"; | |||
|
105 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F68"; | |||
|
106 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F6C"; | |||
|
107 | ||||
|
108 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F70"; | |||
|
109 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F74"; | |||
|
110 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F78"; | |||
|
111 | CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F7C"; | |||
|
112 | ||||
|
113 | CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F80"; | |||
|
114 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F84"; | |||
|
115 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F88"; | |||
|
116 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F8C"; | |||
102 |
|
117 | |||
103 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
|
118 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F90"; | |
104 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
|
119 | CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F94"; | |
105 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
|
120 | CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F98"; | |
106 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
|
121 | CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F9C"; | |
|
122 | ||||
|
123 | CONSTANT ADDR_WAVEFORM_PICKER_COARSE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FA0"; | |||
|
124 | CONSTANT ADDR_WAVEFORM_PICKER_FINE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FA4"; | |||
|
125 | CONSTANT ADDR_WAVEFORM_PICKER_COARSE_TIME_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FA8"; | |||
|
126 | CONSTANT ADDR_WAVEFORM_PICKER_FINE_TIME_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FAC"; | |||
107 |
|
127 | |||
108 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
|
128 | CONSTANT ADDR_WAVEFORM_PICKER_COARSE_TIME_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FB0"; | |
109 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
|
129 | CONSTANT ADDR_WAVEFORM_PICKER_FINE_TIME_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FB4"; | |
110 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
|
130 | CONSTANT ADDR_WAVEFORM_PICKER_COARSE_TIME_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FB8"; | |
111 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
|
131 | CONSTANT ADDR_WAVEFORM_PICKER_FINE_TIME_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FBC"; | |
112 |
|
132 | |||
113 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
|
133 | CONSTANT ADDR_WAVEFORM_PICKER_COARSE_TIME_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FC0"; | |
114 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
|
134 | CONSTANT ADDR_WAVEFORM_PICKER_FINE_TIME_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FC4"; | |
115 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
|
135 | CONSTANT ADDR_WAVEFORM_PICKER_COARSE_TIME_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FC8"; | |
116 |
CONSTANT ADDR_WAVEFORM_PICKER_ |
|
136 | CONSTANT ADDR_WAVEFORM_PICKER_FINE_TIME_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FCC"; | |
|
137 | ||||
|
138 | CONSTANT ADDR_WAVEFORM_PICKER_COARSE_TIME_F3_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FD0"; | |||
|
139 | CONSTANT ADDR_WAVEFORM_PICKER_FINE_TIME_F3_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FD4"; | |||
|
140 | CONSTANT ADDR_WAVEFORM_PICKER_COARSE_TIME_F3_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FD8"; | |||
|
141 | CONSTANT ADDR_WAVEFORM_PICKER_FINE_TIME_F3_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FDC"; | |||
|
142 | ||||
|
143 | CONSTANT ADDR_WAVEFORM_PICKER_LENGTH_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FE0"; | |||
|
144 | ||||
117 |
|
|
145 | -- RAM ADDRESS | |
118 | CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#000#; |
|
146 | CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#000#; | |
119 | CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#; |
|
147 | CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#; | |
120 | CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#; |
|
148 | CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#; | |
121 | CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#; |
|
149 | CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#; | |
122 |
|
150 | |||
123 |
|
151 | |||
124 | -- Common signal |
|
152 | -- Common signal | |
125 | SIGNAL clk49_152MHz : STD_LOGIC := '0'; |
|
153 | SIGNAL clk49_152MHz : STD_LOGIC := '0'; | |
126 | SIGNAL clk25MHz : STD_LOGIC := '0'; |
|
154 | SIGNAL clk25MHz : STD_LOGIC := '0'; | |
127 | SIGNAL rstn : STD_LOGIC := '0'; |
|
155 | SIGNAL rstn : STD_LOGIC := '0'; | |
128 |
|
156 | |||
129 | -- ADC interface |
|
157 | -- ADC interface | |
130 | SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT |
|
158 | SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT | |
131 | SIGNAL ADC_smpclk : STD_LOGIC; -- OUT |
|
159 | SIGNAL ADC_smpclk : STD_LOGIC; -- OUT | |
132 | SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN |
|
160 | SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN | |
133 |
|
161 | |||
134 | -- AD Converter RHF1401 |
|
162 | -- AD Converter RHF1401 | |
135 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
|
163 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
136 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
|
164 | SIGNAL sample_s : Samples(7 DOWNTO 0); | |
137 | SIGNAL sample_val : STD_LOGIC; |
|
165 | SIGNAL sample_val : STD_LOGIC; | |
138 |
|
166 | |||
139 | -- AHB/APB SIGNAL |
|
167 | -- AHB/APB SIGNAL | |
140 | SIGNAL apbi : apb_slv_in_type; |
|
168 | SIGNAL apbi : apb_slv_in_type; | |
141 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); |
|
169 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); | |
142 | SIGNAL ahbsi : ahb_slv_in_type; |
|
170 | SIGNAL ahbsi : ahb_slv_in_type; | |
143 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); |
|
171 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); | |
144 | SIGNAL ahbmi : ahb_mst_in_type; |
|
172 | SIGNAL ahbmi : ahb_mst_in_type; | |
145 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); |
|
173 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); | |
146 |
|
174 | |||
147 | SIGNAL bias_fail_bw : STD_LOGIC; |
|
175 | SIGNAL bias_fail_bw : STD_LOGIC; | |
148 |
|
176 | |||
149 | ----------------------------------------------------------------------------- |
|
177 | ----------------------------------------------------------------------------- | |
150 | -- LPP_WAVEFORM |
|
178 | -- LPP_WAVEFORM | |
151 | ----------------------------------------------------------------------------- |
|
179 | ----------------------------------------------------------------------------- | |
152 | CONSTANT data_size : INTEGER := 96; |
|
180 | CONSTANT data_size : INTEGER := 96; | |
153 | CONSTANT nb_burst_available_size : INTEGER := 50; |
|
181 | CONSTANT nb_burst_available_size : INTEGER := 50; | |
154 | CONSTANT nb_snapshot_param_size : INTEGER := 2; |
|
182 | CONSTANT nb_snapshot_param_size : INTEGER := 2; | |
155 | CONSTANT delta_vector_size : INTEGER := 2; |
|
183 | CONSTANT delta_vector_size : INTEGER := 2; | |
156 | CONSTANT delta_vector_size_f0_2 : INTEGER := 2; |
|
184 | CONSTANT delta_vector_size_f0_2 : INTEGER := 2; | |
157 |
|
185 | |||
158 | SIGNAL reg_run : STD_LOGIC; |
|
186 | SIGNAL reg_run : STD_LOGIC; | |
159 | SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
187 | SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
160 | SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
188 | SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
161 | SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
189 | SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
162 | SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
190 | SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
163 | SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
191 | SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
164 | SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
192 | SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
165 | SIGNAL enable_f0 : STD_LOGIC; |
|
193 | SIGNAL enable_f0 : STD_LOGIC; | |
166 | SIGNAL enable_f1 : STD_LOGIC; |
|
194 | SIGNAL enable_f1 : STD_LOGIC; | |
167 | SIGNAL enable_f2 : STD_LOGIC; |
|
195 | SIGNAL enable_f2 : STD_LOGIC; | |
168 | SIGNAL enable_f3 : STD_LOGIC; |
|
196 | SIGNAL enable_f3 : STD_LOGIC; | |
169 | SIGNAL burst_f0 : STD_LOGIC; |
|
197 | SIGNAL burst_f0 : STD_LOGIC; | |
170 | SIGNAL burst_f1 : STD_LOGIC; |
|
198 | SIGNAL burst_f1 : STD_LOGIC; | |
171 | SIGNAL burst_f2 : STD_LOGIC; |
|
199 | SIGNAL burst_f2 : STD_LOGIC; | |
172 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); |
|
200 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |
173 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
201 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
174 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
202 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
175 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
203 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
176 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
204 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
177 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
205 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
178 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
206 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
179 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
207 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
180 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
208 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
181 | SIGNAL data_f0_in_valid : STD_LOGIC; |
|
209 | SIGNAL data_f0_in_valid : STD_LOGIC; | |
182 | SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
210 | SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
183 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
211 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
184 | SIGNAL data_f1_in_valid : STD_LOGIC; |
|
212 | SIGNAL data_f1_in_valid : STD_LOGIC; | |
185 | SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
213 | SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
186 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
214 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
187 | SIGNAL data_f2_in_valid : STD_LOGIC; |
|
215 | SIGNAL data_f2_in_valid : STD_LOGIC; | |
188 | SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
216 | SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
189 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
217 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
190 | SIGNAL data_f3_in_valid : STD_LOGIC; |
|
218 | SIGNAL data_f3_in_valid : STD_LOGIC; | |
191 | SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
219 | SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
192 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
220 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
193 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
221 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
194 | SIGNAL data_f0_data_out_valid : STD_LOGIC; |
|
222 | SIGNAL data_f0_data_out_valid : STD_LOGIC; | |
195 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; |
|
223 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; | |
196 | SIGNAL data_f0_data_out_ack : STD_LOGIC; |
|
224 | SIGNAL data_f0_data_out_ack : STD_LOGIC; | |
197 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
225 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
198 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
226 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
199 | SIGNAL data_f1_data_out_valid : STD_LOGIC; |
|
227 | SIGNAL data_f1_data_out_valid : STD_LOGIC; | |
200 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; |
|
228 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; | |
201 | SIGNAL data_f1_data_out_ack : STD_LOGIC; |
|
229 | SIGNAL data_f1_data_out_ack : STD_LOGIC; | |
202 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
230 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
203 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
231 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
204 | SIGNAL data_f2_data_out_valid : STD_LOGIC; |
|
232 | SIGNAL data_f2_data_out_valid : STD_LOGIC; | |
205 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; |
|
233 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; | |
206 | SIGNAL data_f2_data_out_ack : STD_LOGIC; |
|
234 | SIGNAL data_f2_data_out_ack : STD_LOGIC; | |
207 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
235 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
208 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
236 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
209 | SIGNAL data_f3_data_out_valid : STD_LOGIC; |
|
237 | SIGNAL data_f3_data_out_valid : STD_LOGIC; | |
210 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; |
|
238 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; | |
211 | SIGNAL data_f3_data_out_ack : STD_LOGIC; |
|
239 | SIGNAL data_f3_data_out_ack : STD_LOGIC; | |
212 |
|
240 | |||
213 | --MEM CTRLR |
|
241 | --MEM CTRLR | |
214 | SIGNAL memi : memory_in_type; |
|
242 | SIGNAL memi : memory_in_type; | |
215 | SIGNAL memo : memory_out_type; |
|
243 | SIGNAL memo : memory_out_type; | |
216 | SIGNAL wpo : wprot_out_type; |
|
244 | SIGNAL wpo : wprot_out_type; | |
217 | SIGNAL sdo : sdram_out_type; |
|
245 | SIGNAL sdo : sdram_out_type; | |
218 |
|
246 | |||
219 | SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0) := "00000000000000000000"; |
|
247 | SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0) := "00000000000000000000"; | |
220 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
248 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
221 | SIGNAL nSRAM_BE0 : STD_LOGIC; |
|
249 | SIGNAL nSRAM_BE0 : STD_LOGIC; | |
222 | SIGNAL nSRAM_BE1 : STD_LOGIC; |
|
250 | SIGNAL nSRAM_BE1 : STD_LOGIC; | |
223 | SIGNAL nSRAM_BE2 : STD_LOGIC; |
|
251 | SIGNAL nSRAM_BE2 : STD_LOGIC; | |
224 | SIGNAL nSRAM_BE3 : STD_LOGIC; |
|
252 | SIGNAL nSRAM_BE3 : STD_LOGIC; | |
225 | SIGNAL nSRAM_WE : STD_LOGIC; |
|
253 | SIGNAL nSRAM_WE : STD_LOGIC; | |
226 | SIGNAL nSRAM_CE : STD_LOGIC; |
|
254 | SIGNAL nSRAM_CE : STD_LOGIC; | |
227 | SIGNAL nSRAM_OE : STD_LOGIC; |
|
255 | SIGNAL nSRAM_OE : STD_LOGIC; | |
228 |
|
256 | |||
229 | CONSTANT padtech : INTEGER := inferred; |
|
257 | CONSTANT padtech : INTEGER := inferred; | |
230 | SIGNAL not_ramsn_0 : STD_LOGIC; |
|
258 | SIGNAL not_ramsn_0 : STD_LOGIC; | |
231 |
|
259 | |||
232 | ----------------------------------------------------------------------------- |
|
260 | ----------------------------------------------------------------------------- | |
233 | SIGNAL status : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
261 | SIGNAL status : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
234 | SIGNAL read_buffer : STD_LOGIC; |
|
262 | SIGNAL read_buffer : STD_LOGIC; | |
235 | ----------------------------------------------------------------------------- |
|
263 | ----------------------------------------------------------------------------- | |
236 | SIGNAL run_test_waveform_picker : STD_LOGIC := '1'; |
|
264 | SIGNAL run_test_waveform_picker : STD_LOGIC := '1'; | |
237 | SIGNAL state_read_buffer_on_going : STD_LOGIC; |
|
265 | SIGNAL state_read_buffer_on_going : STD_LOGIC; | |
238 | CONSTANT hindex : INTEGER := 1; |
|
266 | CONSTANT hindex : INTEGER := 1; | |
239 | SIGNAL time_mem_f0 : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
267 | SIGNAL time_mem_f0 : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
240 | SIGNAL time_mem_f1 : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
268 | SIGNAL time_mem_f1 : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
241 | SIGNAL time_mem_f2 : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
269 | SIGNAL time_mem_f2 : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
242 | SIGNAL time_mem_f3 : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
270 | SIGNAL time_mem_f3 : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
243 |
|
271 | |||
244 | SIGNAL data_mem_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
272 | SIGNAL data_mem_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
245 | SIGNAL data_mem_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
273 | SIGNAL data_mem_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
246 | SIGNAL data_mem_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
274 | SIGNAL data_mem_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
247 | SIGNAL data_mem_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
275 | SIGNAL data_mem_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
248 |
|
276 | |||
249 | SIGNAL data_0_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
277 | SIGNAL data_0_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
250 | SIGNAL data_0_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
278 | SIGNAL data_0_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
251 | SIGNAL data_0_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
279 | SIGNAL data_0_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
252 |
|
280 | |||
253 | SIGNAL data_1_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
281 | SIGNAL data_1_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
254 | SIGNAL data_1_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
282 | SIGNAL data_1_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
255 | SIGNAL data_1_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
283 | SIGNAL data_1_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
256 |
|
284 | |||
257 | SIGNAL data_2_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
285 | SIGNAL data_2_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
258 | SIGNAL data_2_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
286 | SIGNAL data_2_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
259 | SIGNAL data_2_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
287 | SIGNAL data_2_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
260 |
|
288 | |||
261 | SIGNAL data_3_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
289 | SIGNAL data_3_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
262 | SIGNAL data_3_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
290 | SIGNAL data_3_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
263 | SIGNAL data_3_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
291 | SIGNAL data_3_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
264 |
|
292 | |||
265 | SIGNAL data_4_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
293 | SIGNAL data_4_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
266 | SIGNAL data_4_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
294 | SIGNAL data_4_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
267 | SIGNAL data_4_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
295 | SIGNAL data_4_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
268 |
|
296 | |||
269 | SIGNAL data_5_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
297 | SIGNAL data_5_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
270 | SIGNAL data_5_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
298 | SIGNAL data_5_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
271 | SIGNAL data_5_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
299 | SIGNAL data_5_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
272 | ----------------------------------------------------------------------------- |
|
300 | ----------------------------------------------------------------------------- | |
273 |
|
301 | |||
274 | SIGNAL current_data : INTEGER; |
|
302 | SIGNAL current_data : INTEGER; | |
275 | SIGNAL LIMIT_DATA : INTEGER := 64; |
|
303 | SIGNAL LIMIT_DATA : INTEGER := 64; | |
276 |
|
304 | |||
277 | SIGNAL read_buffer_temp : STD_LOGIC; |
|
305 | SIGNAL read_buffer_temp : STD_LOGIC; | |
278 | SIGNAL read_buffer_temp_2 : STD_LOGIC; |
|
306 | SIGNAL read_buffer_temp_2 : STD_LOGIC; | |
279 |
|
307 | |||
280 |
|
308 | |||
281 | BEGIN |
|
309 | BEGIN | |
282 |
|
310 | |||
283 | ----------------------------------------------------------------------------- |
|
311 | ----------------------------------------------------------------------------- | |
284 |
|
312 | |||
285 | clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz |
|
313 | clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz | |
286 | clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz |
|
314 | clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz | |
287 |
|
315 | |||
288 | ----------------------------------------------------------------------------- |
|
316 | ----------------------------------------------------------------------------- | |
289 |
|
317 | |||
290 | MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE |
|
318 | MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE | |
291 | TestModule_RHF1401_1 : TestModule_RHF1401 |
|
319 | TestModule_RHF1401_1 : TestModule_RHF1401 | |
292 | GENERIC MAP ( |
|
320 | GENERIC MAP ( | |
293 | freq => 24*(I+1), |
|
321 | freq => 24*(I+1), | |
294 | amplitude => 8000/(I+1), |
|
322 | amplitude => 8000/(I+1), | |
295 | impulsion => 0) |
|
323 | impulsion => 0) | |
296 | PORT MAP ( |
|
324 | PORT MAP ( | |
297 | ADC_smpclk => ADC_smpclk, |
|
325 | ADC_smpclk => ADC_smpclk, | |
298 | ADC_OEB_bar => ADC_OEB_bar_CH(I), |
|
326 | ADC_OEB_bar => ADC_OEB_bar_CH(I), | |
299 | ADC_data => ADC_data); |
|
327 | ADC_data => ADC_data); | |
300 | END GENERATE MODULE_RHF1401; |
|
328 | END GENERATE MODULE_RHF1401; | |
301 |
|
329 | |||
302 | ----------------------------------------------------------------------------- |
|
330 | ----------------------------------------------------------------------------- | |
303 |
|
331 | |||
304 | top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 |
|
332 | top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 | |
305 | GENERIC MAP ( |
|
333 | GENERIC MAP ( | |
306 | ChanelCount => 8, |
|
334 | ChanelCount => 8, | |
307 | ncycle_cnv_high => 79, |
|
335 | ncycle_cnv_high => 79, | |
308 | ncycle_cnv => 500) |
|
336 | ncycle_cnv => 500) | |
309 | PORT MAP ( |
|
337 | PORT MAP ( | |
310 | cnv_clk => clk49_152MHz, |
|
338 | cnv_clk => clk49_152MHz, | |
311 | cnv_rstn => rstn, |
|
339 | cnv_rstn => rstn, | |
312 | cnv => ADC_smpclk, |
|
340 | cnv => ADC_smpclk, | |
313 | clk => clk25MHz, |
|
341 | clk => clk25MHz, | |
314 | rstn => rstn, |
|
342 | rstn => rstn, | |
315 | ADC_data => ADC_data, |
|
343 | ADC_data => ADC_data, | |
316 | ADC_nOE => ADC_OEB_bar_CH, |
|
344 | ADC_nOE => ADC_OEB_bar_CH, | |
317 | sample => sample, |
|
345 | sample => sample, | |
318 | sample_val => sample_val); |
|
346 | sample_val => sample_val); | |
319 | ----------------------------------------------------------------------------- |
|
347 | ----------------------------------------------------------------------------- | |
320 |
|
348 | |||
321 |
|
349 | |||
322 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE |
|
350 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE | |
323 | sample_s(I) <= sample(I) & '0' & '0'; |
|
351 | sample_s(I) <= sample(I) & '0' & '0'; | |
324 | END GENERATE all_sample; |
|
352 | END GENERATE all_sample; | |
325 | ----------------------------------------------------------------------------- |
|
353 | ----------------------------------------------------------------------------- | |
326 |
|
354 | |||
327 | lpp_lfr_1 : lpp_lfr |
|
355 | lpp_lfr_1 : lpp_lfr | |
328 | GENERIC MAP ( |
|
356 | GENERIC MAP ( | |
329 | Mem_use => use_CEL, -- use_RAM |
|
357 | Mem_use => use_CEL, -- use_RAM | |
330 | nb_data_by_buffer_size => 32, |
|
358 | nb_data_by_buffer_size => 32, | |
331 | nb_word_by_buffer_size => 30, |
|
359 | -- nb_word_by_buffer_size => 30, | |
332 | nb_snapshot_param_size => 32, |
|
360 | nb_snapshot_param_size => 32, | |
333 | delta_vector_size => 32, |
|
361 | delta_vector_size => 32, | |
334 | delta_vector_size_f0_2 => 32, |
|
362 | delta_vector_size_f0_2 => 32, | |
335 | pindex => INDEX_LFR, |
|
363 | pindex => INDEX_LFR, | |
336 | paddr => ADDR_LFR, |
|
364 | paddr => ADDR_LFR, | |
337 | pmask => 16#fff#, |
|
365 | pmask => 16#fff#, | |
338 | pirq_ms => 6, |
|
366 | pirq_ms => 6, | |
339 | pirq_wfp => 14, |
|
367 | pirq_wfp => 14, | |
340 | hindex => 0, |
|
368 | hindex => 0, | |
341 | top_lfr_version => X"000001") |
|
369 | top_lfr_version => X"000001") | |
342 | PORT MAP ( |
|
370 | PORT MAP ( | |
343 | clk => clk25MHz, |
|
371 | clk => clk25MHz, | |
344 | rstn => rstn, |
|
372 | rstn => rstn, | |
345 | sample_B => sample_s(2 DOWNTO 0), |
|
373 | sample_B => sample_s(2 DOWNTO 0), | |
346 | sample_E => sample_s(7 DOWNTO 3), |
|
374 | sample_E => sample_s(7 DOWNTO 3), | |
347 | sample_val => sample_val, |
|
375 | sample_val => sample_val, | |
348 | apbi => apbi, |
|
376 | apbi => apbi, | |
349 | apbo => apbo(15), |
|
377 | apbo => apbo(15), | |
350 | ahbi => ahbmi, |
|
378 | ahbi => ahbmi, | |
351 | ahbo => ahbmo(0), |
|
379 | ahbo => ahbmo(0), | |
352 | coarse_time => coarse_time, |
|
380 | coarse_time => coarse_time, | |
353 | fine_time => fine_time, |
|
381 | fine_time => fine_time, | |
354 | data_shaping_BW => bias_fail_bw); |
|
382 | data_shaping_BW => bias_fail_bw); | |
355 |
|
383 | |||
356 | ----------------------------------------------------------------------------- |
|
384 | ----------------------------------------------------------------------------- | |
357 | --- AHB CONTROLLER ------------------------------------------------- |
|
385 | --- AHB CONTROLLER ------------------------------------------------- | |
358 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
|
386 | ahb0 : ahbctrl -- AHB arbiter/multiplexer | |
359 | GENERIC MAP (defmast => 0, split => 0, |
|
387 | GENERIC MAP (defmast => 0, split => 0, | |
360 | rrobin => 1, ioaddr => 16#FFF#, |
|
388 | rrobin => 1, ioaddr => 16#FFF#, | |
361 | ioen => 0, nahbm => 2, nahbs => 1) |
|
389 | ioen => 0, nahbm => 2, nahbs => 1) | |
362 | PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso); |
|
390 | PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso); | |
363 |
|
391 | |||
364 |
|
392 | |||
365 |
|
393 | |||
366 | --- AHB RAM ---------------------------------------------------------- |
|
394 | --- AHB RAM ---------------------------------------------------------- | |
367 | --ahbram0 : ahbram |
|
395 | --ahbram0 : ahbram | |
368 | -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0) |
|
396 | -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0) | |
369 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0)); |
|
397 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0)); | |
370 | --ahbram1 : ahbram |
|
398 | --ahbram1 : ahbram | |
371 | -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0) |
|
399 | -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0) | |
372 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1)); |
|
400 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1)); | |
373 | --ahbram2 : ahbram |
|
401 | --ahbram2 : ahbram | |
374 | -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0) |
|
402 | -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0) | |
375 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2)); |
|
403 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2)); | |
376 | --ahbram3 : ahbram |
|
404 | --ahbram3 : ahbram | |
377 | -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0) |
|
405 | -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0) | |
378 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3)); |
|
406 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3)); | |
379 |
|
407 | |||
380 | ----------------------------------------------------------------------------- |
|
408 | ----------------------------------------------------------------------------- | |
381 | ---------------------------------------------------------------------- |
|
409 | ---------------------------------------------------------------------- | |
382 | --- Memory controllers --------------------------------------------- |
|
410 | --- Memory controllers --------------------------------------------- | |
383 | ---------------------------------------------------------------------- |
|
411 | ---------------------------------------------------------------------- | |
384 | memctrlr : mctrl GENERIC MAP ( |
|
412 | memctrlr : mctrl GENERIC MAP ( | |
385 | hindex => 0, |
|
413 | hindex => 0, | |
386 | pindex => 0, |
|
414 | pindex => 0, | |
387 | paddr => 0, |
|
415 | paddr => 0, | |
388 | srbanks => 1 |
|
416 | srbanks => 1 | |
389 | ) |
|
417 | ) | |
390 | PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); |
|
418 | PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); | |
391 |
|
419 | |||
392 | memi.brdyn <= '1'; |
|
420 | memi.brdyn <= '1'; | |
393 | memi.bexcn <= '1'; |
|
421 | memi.bexcn <= '1'; | |
394 | memi.writen <= '1'; |
|
422 | memi.writen <= '1'; | |
395 | memi.wrn <= "1111"; |
|
423 | memi.wrn <= "1111"; | |
396 | memi.bwidth <= "10"; |
|
424 | memi.bwidth <= "10"; | |
397 |
|
425 | |||
398 | bdr : FOR i IN 0 TO 3 GENERATE |
|
426 | bdr : FOR i IN 0 TO 3 GENERATE | |
399 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) |
|
427 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) | |
400 | PORT MAP ( |
|
428 | PORT MAP ( | |
401 | data(31-i*8 DOWNTO 24-i*8), |
|
429 | data(31-i*8 DOWNTO 24-i*8), | |
402 | memo.data(31-i*8 DOWNTO 24-i*8), |
|
430 | memo.data(31-i*8 DOWNTO 24-i*8), | |
403 | memo.bdrive(i), |
|
431 | memo.bdrive(i), | |
404 | memi.data(31-i*8 DOWNTO 24-i*8)); |
|
432 | memi.data(31-i*8 DOWNTO 24-i*8)); | |
405 | END GENERATE; |
|
433 | END GENERATE; | |
406 |
|
434 | |||
407 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) |
|
435 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) | |
408 | PORT MAP (address, memo.address(21 DOWNTO 2)); |
|
436 | PORT MAP (address, memo.address(21 DOWNTO 2)); | |
409 |
|
437 | |||
410 | not_ramsn_0 <= NOT(memo.ramsn(0)); |
|
438 | not_ramsn_0 <= NOT(memo.ramsn(0)); | |
411 |
|
439 | |||
412 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0); |
|
440 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0); | |
413 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); |
|
441 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); | |
414 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); |
|
442 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); | |
415 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); |
|
443 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); | |
416 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); |
|
444 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); | |
417 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); |
|
445 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); | |
418 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); |
|
446 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); | |
419 |
|
447 | |||
420 | async_1Mx16_0 : CY7C1061DV33 |
|
448 | async_1Mx16_0 : CY7C1061DV33 | |
421 | GENERIC MAP ( |
|
449 | GENERIC MAP ( | |
422 | ADDR_BITS => 20, |
|
450 | ADDR_BITS => 20, | |
423 | DATA_BITS => 16, |
|
451 | DATA_BITS => 16, | |
424 | depth => 1048576, |
|
452 | depth => 1048576, | |
425 | MEM_ARRAY_DEBUG => 32, |
|
453 | MEM_ARRAY_DEBUG => 32, | |
426 | TimingInfo => true, |
|
454 | TimingInfo => true, | |
427 | TimingChecks => '1') |
|
455 | TimingChecks => '1') | |
428 | PORT MAP ( |
|
456 | PORT MAP ( | |
429 | CE1_b => '0', |
|
457 | CE1_b => '0', | |
430 | CE2 => nSRAM_CE, |
|
458 | CE2 => nSRAM_CE, | |
431 | WE_b => nSRAM_WE, |
|
459 | WE_b => nSRAM_WE, | |
432 | OE_b => nSRAM_OE, |
|
460 | OE_b => nSRAM_OE, | |
433 | BHE_b => nSRAM_BE1, |
|
461 | BHE_b => nSRAM_BE1, | |
434 | BLE_b => nSRAM_BE0, |
|
462 | BLE_b => nSRAM_BE0, | |
435 | A => address, |
|
463 | A => address, | |
436 | DQ => data(15 DOWNTO 0)); |
|
464 | DQ => data(15 DOWNTO 0)); | |
437 |
|
465 | |||
438 | async_1Mx16_1 : CY7C1061DV33 |
|
466 | async_1Mx16_1 : CY7C1061DV33 | |
439 | GENERIC MAP ( |
|
467 | GENERIC MAP ( | |
440 | ADDR_BITS => 20, |
|
468 | ADDR_BITS => 20, | |
441 | DATA_BITS => 16, |
|
469 | DATA_BITS => 16, | |
442 | depth => 1048576, |
|
470 | depth => 1048576, | |
443 | MEM_ARRAY_DEBUG => 32, |
|
471 | MEM_ARRAY_DEBUG => 32, | |
444 | TimingInfo => true, |
|
472 | TimingInfo => true, | |
445 | TimingChecks => '1') |
|
473 | TimingChecks => '1') | |
446 | PORT MAP ( |
|
474 | PORT MAP ( | |
447 | CE1_b => '0', |
|
475 | CE1_b => '0', | |
448 | CE2 => nSRAM_CE, |
|
476 | CE2 => nSRAM_CE, | |
449 | WE_b => nSRAM_WE, |
|
477 | WE_b => nSRAM_WE, | |
450 | OE_b => nSRAM_OE, |
|
478 | OE_b => nSRAM_OE, | |
451 | BHE_b => nSRAM_BE3, |
|
479 | BHE_b => nSRAM_BE3, | |
452 | BLE_b => nSRAM_BE2, |
|
480 | BLE_b => nSRAM_BE2, | |
453 | A => address, |
|
481 | A => address, | |
454 | DQ => data(31 DOWNTO 16)); |
|
482 | DQ => data(31 DOWNTO 16)); | |
455 |
|
483 | |||
456 |
|
484 | |||
457 | ----------------------------------------------------------------------------- |
|
485 | ----------------------------------------------------------------------------- | |
458 |
|
486 | |||
459 | WaveGen_Proc : PROCESS |
|
487 | WaveGen_Proc : PROCESS | |
460 | BEGIN |
|
488 | BEGIN | |
461 |
|
489 | |||
462 | -- insert signal assignments here |
|
490 | -- insert signal assignments here | |
463 | WAIT UNTIL clk25MHz = '1'; |
|
491 | WAIT UNTIL clk25MHz = '1'; | |
464 | rstn <= '0'; |
|
492 | rstn <= '0'; | |
465 | apbi.psel(15) <= '0'; |
|
493 | apbi.psel(15) <= '0'; | |
466 | apbi.pwrite <= '0'; |
|
494 | apbi.pwrite <= '0'; | |
467 | apbi.penable <= '0'; |
|
495 | apbi.penable <= '0'; | |
468 | apbi.paddr <= (OTHERS => '0'); |
|
496 | apbi.paddr <= (OTHERS => '0'); | |
469 | apbi.pwdata <= (OTHERS => '0'); |
|
497 | apbi.pwdata <= (OTHERS => '0'); | |
470 | fine_time <= (OTHERS => '0'); |
|
498 | fine_time <= (OTHERS => '0'); | |
471 | coarse_time <= (OTHERS => '0'); |
|
499 | coarse_time <= (OTHERS => '0'); | |
472 | WAIT UNTIL clk25MHz = '1'; |
|
500 | WAIT UNTIL clk25MHz = '1'; | |
473 | -- ahbmi.HGRANT(2) <= '1'; |
|
501 | -- ahbmi.HGRANT(2) <= '1'; | |
474 | -- ahbmi.HREADY <= '1'; |
|
502 | -- ahbmi.HREADY <= '1'; | |
475 | -- ahbmi.HRESP <= HRESP_OKAY; |
|
503 | -- ahbmi.HRESP <= HRESP_OKAY; | |
476 |
|
504 | |||
477 | WAIT UNTIL clk25MHz = '1'; |
|
505 | WAIT UNTIL clk25MHz = '1'; | |
478 | WAIT UNTIL clk25MHz = '1'; |
|
506 | WAIT UNTIL clk25MHz = '1'; | |
479 | rstn <= '1'; |
|
507 | rstn <= '1'; | |
480 | WAIT UNTIL clk25MHz = '1'; |
|
508 | WAIT UNTIL clk25MHz = '1'; | |
|
509 | --------------------------------------------------------------------------- | |||
|
510 | -- spectral matrix configuration | |||
|
511 | --------------------------------------------------------------------------- | |||
|
512 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_CONFIG, X"00000000"); | |||
|
513 | ||||
481 |
|
|
514 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 , X"40000000"); | |
482 |
APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 , X"400 |
|
515 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 , X"40001000"); | |
483 |
APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1_0 , X"400 |
|
516 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1_0 , X"40002000"); | |
484 |
APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F |
|
517 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1_1 , X"40003000"); | |
485 |
|
518 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2_0 , X"40004000"); | ||
486 |
APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ |
|
519 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2_1 , X"40005000"); | |
487 |
|
|
520 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_LENGTH_MATRIX, X"000000C8"); | |
488 |
|
521 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_STATUS, X"00000000"); | ||
489 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000"); |
|
522 | ||
490 |
|
|
523 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_CONFIG, X"00000007"); | |
491 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000"); |
|
524 | ||
492 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000"); |
|
525 | --------------------------------------------------------------------------- | |
|
526 | -- waveform picker configuration | |||
|
527 | --------------------------------------------------------------------------- | |||
|
528 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0_0 , X"40020000"); | |||
|
529 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0_1 , X"40020000"); | |||
|
530 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1_0 , X"40030000"); | |||
|
531 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1_1 , X"40030000"); | |||
|
532 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2_0 , X"40040000"); | |||
|
533 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2_1 , X"40040000"); | |||
|
534 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3_0 , X"40060000"); | |||
|
535 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3_1 , X"40060000"); | |||
493 |
|
536 | |||
494 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000020"); --"00000020" |
|
537 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000020"); --"00000020" | |
495 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000019"); --"00000019" |
|
538 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000019"); --"00000019" | |
496 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007"); --"00000007" |
|
539 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007"); --"00000007" | |
497 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000019"); --"00000019" |
|
540 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000019"); --"00000019" | |
498 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001"); --"00000001" |
|
541 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001"); --"00000001" | |
499 |
|
542 | |||
500 |
APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"0000000 |
|
543 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000010"); -- X"00000010" | |
501 | -- |
|
544 | -- | |
502 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010"); |
|
545 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010"); | |
503 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001"); |
|
546 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001"); | |
504 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022"); |
|
547 | ||
|
548 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_LENGTH_BUFFER , X"00000003"); | |||
505 |
|
549 | |||
506 |
|
550 | |||
507 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000080"); |
|
551 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000080"); | |
508 | WAIT UNTIL clk25MHz = '1'; |
|
552 | WAIT UNTIL clk25MHz = '1'; | |
509 | --------------------------------------------------------------------------- |
|
553 | --------------------------------------------------------------------------- | |
510 | -- CONFIGURATION STEP |
|
554 | -- CONFIGURATION STEP | |
511 |
APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"400 |
|
555 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0_0 , X"40020000"); | |
512 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000"); |
|
556 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0_1 , X"40020000"); | |
513 |
APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F |
|
557 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1_0 , X"40030000"); | |
514 |
APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F |
|
558 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1_1 , X"40030000"); | |
|
559 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2_0 , X"40040000"); | |||
|
560 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2_1 , X"40040000"); | |||
|
561 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3_0 , X"40060000"); | |||
|
562 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3_1 , X"40060000"); | |||
515 |
|
563 | |||
516 | WAIT UNTIL clk25MHz = '1'; |
|
564 | WAIT UNTIL clk25MHz = '1'; | |
517 | WAIT UNTIL clk25MHz = '1'; |
|
565 | WAIT UNTIL clk25MHz = '1'; | |
518 |
|
566 | |||
519 |
|
567 | |||
520 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000097"); |
|
568 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000097"); | |
521 | WAIT UNTIL clk25MHz = '1'; |
|
569 | WAIT UNTIL clk25MHz = '1'; | |
522 | WAIT UNTIL clk25MHz = '1'; |
|
570 | WAIT UNTIL clk25MHz = '1'; | |
523 | WAIT UNTIL clk25MHz = '1'; |
|
571 | WAIT UNTIL clk25MHz = '1'; | |
524 | WAIT UNTIL clk25MHz = '1'; |
|
572 | WAIT UNTIL clk25MHz = '1'; | |
525 | WAIT UNTIL clk25MHz = '1'; |
|
573 | WAIT UNTIL clk25MHz = '1'; | |
526 | WAIT UNTIL clk25MHz = '1'; |
|
574 | WAIT UNTIL clk25MHz = '1'; | |
527 | WAIT FOR 1 us; |
|
575 | WAIT FOR 1 us; | |
528 | coarse_time <= X"00000001"; |
|
576 | coarse_time <= X"00000001"; | |
529 | --------------------------------------------------------------------------- |
|
577 | --------------------------------------------------------------------------- | |
530 | -- RUN STEP |
|
578 | -- RUN STEP | |
531 | WAIT FOR 200 ms; |
|
579 | WAIT FOR 200 ms; | |
532 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); |
|
580 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); | |
533 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010"); |
|
581 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010"); | |
534 | WAIT FOR 10 us; |
|
582 | WAIT FOR 10 us; | |
535 | WAIT UNTIL clk25MHz = '1'; |
|
583 | WAIT UNTIL clk25MHz = '1'; | |
536 | WAIT UNTIL clk25MHz = '1'; |
|
584 | WAIT UNTIL clk25MHz = '1'; | |
537 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF"); |
|
585 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF"); | |
538 | WAIT UNTIL clk25MHz = '1'; |
|
586 | WAIT UNTIL clk25MHz = '1'; | |
539 | coarse_time <= X"00000010"; |
|
587 | coarse_time <= X"00000010"; | |
540 | WAIT FOR 100 ms; |
|
588 | WAIT FOR 100 ms; | |
541 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); |
|
589 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); | |
542 | WAIT FOR 10 us; |
|
590 | WAIT FOR 10 us; | |
543 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF"); |
|
591 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF"); | |
544 | WAIT FOR 200 ms; |
|
592 | WAIT FOR 200 ms; | |
545 | REPORT "*** END simulation ***" SEVERITY failure; |
|
593 | REPORT "*** END simulation ***" SEVERITY failure; | |
546 |
|
594 | |||
547 |
|
595 | |||
548 | WAIT; |
|
596 | WAIT; | |
549 |
|
597 | |||
550 | END PROCESS WaveGen_Proc; |
|
598 | END PROCESS WaveGen_Proc; | |
551 | ----------------------------------------------------------------------------- |
|
599 | ----------------------------------------------------------------------------- | |
552 |
|
600 | |||
553 | ----------------------------------------------------------------------------- |
|
601 | ----------------------------------------------------------------------------- | |
554 | -- IRQ |
|
602 | -- IRQ | |
555 | ----------------------------------------------------------------------------- |
|
603 | ----------------------------------------------------------------------------- | |
556 | PROCESS (clk25MHz, rstn) |
|
604 | PROCESS (clk25MHz, rstn) | |
557 | BEGIN -- PROCESS |
|
605 | BEGIN -- PROCESS | |
558 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
606 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
559 |
|
607 | |||
560 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge |
|
608 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge | |
561 |
|
609 | |||
562 | END IF; |
|
610 | END IF; | |
563 | END PROCESS; |
|
611 | END PROCESS; | |
564 | ----------------------------------------------------------------------------- |
|
612 | ----------------------------------------------------------------------------- | |
565 |
|
613 | |||
566 | END beh; |
|
614 | END beh; | |
567 |
|
615 |
@@ -1,69 +1,151 | |||||
1 | onerror {resume} |
|
1 | onerror {resume} | |
2 | quietly WaveActivateNextPane {} 0 |
|
2 | quietly WaveActivateNextPane {} 0 | |
3 | add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata |
|
3 | add wave -noupdate -expand -group FILTER_OUTPUT -radix hexadecimal /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata | |
4 | add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata |
|
4 | add wave -noupdate -expand -group FILTER_OUTPUT -radix hexadecimal /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata | |
5 | add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata |
|
5 | add wave -noupdate -expand -group FILTER_OUTPUT -radix hexadecimal /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata | |
6 | add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata |
|
6 | add wave -noupdate -expand -group FILTER_OUTPUT -radix hexadecimal /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata | |
7 | add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val |
|
7 | add wave -noupdate -expand -group FILTER_OUTPUT -radix hexadecimal /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val | |
8 | add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val |
|
8 | add wave -noupdate -expand -group FILTER_OUTPUT -radix hexadecimal /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val | |
9 | add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val |
|
9 | add wave -noupdate -expand -group FILTER_OUTPUT -radix hexadecimal /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val | |
10 | add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val |
|
10 | add wave -noupdate -expand -group FILTER_OUTPUT -radix hexadecimal /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val | |
11 | add wave -noupdate -expand -group SNAPSHOT_F0 /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/enable |
|
11 | add wave -noupdate /tb/lpp_lfr_1/rstn | |
12 | add wave -noupdate -expand -group SNAPSHOT_F0 /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/burst_enable |
|
12 | add wave -noupdate /tb/lpp_lfr_1/run | |
13 | add wave -noupdate -expand -group SNAPSHOT_F0 /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/start_snapshot |
|
13 | add wave -noupdate /tb/lpp_lfr_1/run_dma | |
14 | add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/state_on |
|
14 | add wave -noupdate /tb/lpp_lfr_1/run_ms | |
15 | add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/wfp_on_s |
|
15 | add wave -noupdate -expand -group MS /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp | |
16 | add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f0_pre |
|
16 | add wave -noupdate -expand -group MS -group MS_MEM_OUT_0 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(0)/mem_out_spectralmatrix_i/reuse | |
17 | add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/first_decount |
|
17 | add wave -noupdate -expand -group MS -group MS_MEM_OUT_0 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(0)/mem_out_spectralmatrix_i/run | |
18 | add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/first_init |
|
18 | add wave -noupdate -expand -group MS -group MS_MEM_OUT_0 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(0)/mem_out_spectralmatrix_i/ren | |
19 | add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot |
|
19 | add wave -noupdate -expand -group MS -group MS_MEM_OUT_0 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(0)/mem_out_spectralmatrix_i/rdata | |
20 | add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_f0 |
|
20 | add wave -noupdate -expand -group MS -group MS_MEM_OUT_0 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(0)/mem_out_spectralmatrix_i/wen | |
21 | add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/send_start_snapshot_f0 |
|
21 | add wave -noupdate -expand -group MS -group MS_MEM_OUT_0 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(0)/mem_out_spectralmatrix_i/wdata | |
22 | add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/data_f0_valid |
|
22 | add wave -noupdate -expand -group MS -group MS_MEM_OUT_0 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(0)/mem_out_spectralmatrix_i/full | |
23 | add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/data_f2_valid |
|
23 | add wave -noupdate -expand -group MS -group MS_MEM_OUT_0 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(0)/mem_out_spectralmatrix_i/full_threshold | |
24 | add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f0 |
|
24 | add wave -noupdate -expand -group MS -group MS_MEM_OUT_0 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(0)/mem_out_spectralmatrix_i/full_almost | |
25 | add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f1 |
|
25 | add wave -noupdate -expand -group MS -group MS_MEM_OUT_0 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(0)/mem_out_spectralmatrix_i/empty | |
26 | add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f2 |
|
26 | add wave -noupdate -expand -group MS -group MS_MEM_OUT_0 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(0)/mem_out_spectralmatrix_i/empty_threshold | |
27 | add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/wfp_on |
|
27 | add wave -noupdate -expand -group MS -group MEM_OUT_1 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(1)/mem_out_spectralmatrix_i/reuse | |
28 | add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in |
|
28 | add wave -noupdate -expand -group MS -group MEM_OUT_1 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(1)/mem_out_spectralmatrix_i/run | |
29 | add wave -noupdate -expand -subitemconfig {/tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.haddr {-height 15 -radix hexadecimal} /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hwdata {-height 15 -radix hexadecimal}} /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out |
|
29 | add wave -noupdate -expand -group MS -group MEM_OUT_1 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(1)/mem_out_spectralmatrix_i/ren | |
30 | add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/send |
|
30 | add wave -noupdate -expand -group MS -group MEM_OUT_1 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(1)/mem_out_spectralmatrix_i/rdata | |
31 | add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/valid_burst |
|
31 | add wave -noupdate -expand -group MS -group MEM_OUT_1 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(1)/mem_out_spectralmatrix_i/wen | |
32 | add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/done |
|
32 | add wave -noupdate -expand -group MS -group MEM_OUT_1 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(1)/mem_out_spectralmatrix_i/wdata | |
33 | add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ren |
|
33 | add wave -noupdate -expand -group MS -group MEM_OUT_1 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(1)/mem_out_spectralmatrix_i/empty | |
34 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_1/lpp_dma_singleorburst_1/address |
|
34 | add wave -noupdate -expand -group MS -group MEM_OUT_1 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(1)/mem_out_spectralmatrix_i/full | |
35 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_1/lpp_dma_singleorburst_1/data |
|
35 | add wave -noupdate -expand -group MS -group MEM_OUT_1 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(1)/mem_out_spectralmatrix_i/full_almost | |
36 | add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/debug_dmaout_okay |
|
36 | add wave -noupdate -expand -group MS -group MEM_OUT_1 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(1)/mem_out_spectralmatrix_i/empty_threshold | |
37 | add wave -noupdate /tb/async_1mx16_0/ce1_b |
|
37 | add wave -noupdate -expand -group MS -group MEM_OUT_1 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(1)/mem_out_spectralmatrix_i/full_threshold | |
38 | add wave -noupdate /tb/async_1mx16_0/ce2 |
|
38 | add wave -noupdate -expand -group MS -group FSM_Dma_FIFO /tb/lpp_lfr_1/lpp_lfr_ms_1/fsm_dma_fifo_ren | |
39 | add wave -noupdate /tb/async_1mx16_0/we_b |
|
39 | add wave -noupdate -expand -group MS -group FSM_Dma_FIFO /tb/lpp_lfr_1/lpp_lfr_ms_1/fsm_dma_fifo_empty | |
40 | add wave -noupdate /tb/async_1mx16_0/oe_b |
|
40 | add wave -noupdate -expand -group MS -group FSM_Dma_FIFO /tb/lpp_lfr_1/lpp_lfr_ms_1/fsm_dma_fifo_empty_threshold | |
41 | add wave -noupdate /tb/async_1mx16_0/bhe_b |
|
41 | add wave -noupdate -expand -group MS -group FSM_Dma_FIFO /tb/lpp_lfr_1/lpp_lfr_ms_1/fsm_dma_fifo_data | |
42 | add wave -noupdate /tb/async_1mx16_0/ble_b |
|
42 | add wave -noupdate -expand -group MS -group FSM_Dma_FIFO /tb/lpp_lfr_1/lpp_lfr_ms_1/fsm_dma_fifo_status | |
43 |
add wave -noupdate /tb/asy |
|
43 | add wave -noupdate /tb/lpp_lfr_1/dma_subsystem_1/fifo_ren | |
44 |
add wave -noupdate /tb/asy |
|
44 | add wave -noupdate /tb/lpp_lfr_1/dma_subsystem_1/dma_ren | |
45 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/async_1mx16_0/mem_array_0(31) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(30) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(29) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(28) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(27) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(26) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(25) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(24) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(23) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(22) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(21) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(20) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(19) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(18) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(17) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(16) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(15) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(14) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(13) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(12) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(11) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(10) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(9) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(8) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(7) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(6) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(5) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(4) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(3) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(2) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(1) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(0) {-height 15 -radix hexadecimal}} /tb/async_1mx16_0/mem_array_0 |
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45 | add wave -noupdate /tb/lpp_lfr_1/dma_subsystem_1/fifo_burst_valid | |
46 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/async_1mx16_0/mem_array_1(31) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(30) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(29) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(28) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(27) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(26) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(25) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(24) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(23) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(22) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(21) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(20) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(19) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(18) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(17) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(16) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(15) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(14) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(13) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(12) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(11) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(10) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(9) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(8) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(7) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(6) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(5) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(4) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(3) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(2) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(1) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(0) {-radix hexadecimal}} /tb/async_1mx16_0/mem_array_1 |
|
46 | add wave -noupdate /tb/lpp_lfr_1/dma_subsystem_1/fifo_data | |
47 | add wave -noupdate -radix hexadecimal /tb/async_1mx16_0/mem_array_2 |
|
47 | add wave -noupdate /tb/lpp_lfr_1/dma_subsystem_1/fifo_ren | |
48 | add wave -noupdate -radix hexadecimal /tb/async_1mx16_0/mem_array_3 |
|
48 | add wave -noupdate -radix hexadecimal -subitemconfig {/tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_new_err {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_bw {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_sp0 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_sp1 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_r0 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_r1 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_r2 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_snapshot {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0_2 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f1 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f2 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_data_by_buffer {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_snapshot_param {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f0 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f1 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f2 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f3 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f0 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f1 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f2 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.run {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f {-radix hexadecimal -expand} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f(7) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f(6) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f(5) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f(4) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f(3) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f(2) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f(1) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f(0) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.addr_buffer_f {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.length_buffer {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.error_buffer_full {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.start_date {-radix hexadecimal}} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp | |
49 | add wave -noupdate -format Analog-Step -height 70 -max 256.0 -radix unsigned -subitemconfig {/tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(7) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(6) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(5) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(4) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(3) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(2) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(1) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(0) {-radix unsigned}} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect |
|
49 | add wave -noupdate -group FIFO_0 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/reuse | |
50 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(0) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(1) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(2) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(3) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(4) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(5) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(6) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(7) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(8) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(9) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(10) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(11) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(12) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(13) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(14) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(15) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(16) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(17) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(18) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(19) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(20) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(21) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(22) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(23) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(24) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(25) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(26) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(27) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(28) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(29) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(30) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(31) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(32) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(33) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(34) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(35) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(36) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(37) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(38) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(39) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(40) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(41) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(42) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(43) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(44) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(45) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(46) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(47) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(48) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(49) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(50) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(51) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(52) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(53) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(54) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(55) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(56) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(57) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(58) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(59) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(60) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(61) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(62) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(63) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(64) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(65) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(66) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(67) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(68) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(69) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(70) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(71) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(72) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(73) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(74) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(75) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(76) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(77) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(78) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(79) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(80) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(81) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(82) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(83) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(84) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(85) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(86) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(87) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(88) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(89) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(90) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(91) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(92) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(93) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(94) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(95) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(96) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(97) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(98) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(99) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(100) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(101) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(102) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(103) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(104) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(105) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(106) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(107) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(108) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(109) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(110) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(111) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(112) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(113) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(114) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(115) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(116) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(117) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(118) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(119) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(120) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(121) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(122) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(123) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(124) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(125) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(126) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(127) {-radix hexadecimal}} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd |
|
50 | add wave -noupdate -group FIFO_0 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/run | |
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51 | add wave -noupdate -group FIFO_0 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/ren | |||
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52 | add wave -noupdate -group FIFO_0 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/rdata | |||
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53 | add wave -noupdate -group FIFO_0 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/wen | |||
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54 | add wave -noupdate -group FIFO_0 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/wdata | |||
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55 | add wave -noupdate -group FIFO_0 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/empty | |||
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56 | add wave -noupdate -group FIFO_0 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/full | |||
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57 | add wave -noupdate -group FIFO_0 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/full_almost | |||
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58 | add wave -noupdate -group FIFO_0 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/empty_threshold | |||
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59 | add wave -noupdate -group FIFO_0 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/full_threshold | |||
|
60 | add wave -noupdate -group FIFO_1 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/reuse | |||
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61 | add wave -noupdate -group FIFO_1 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/run | |||
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62 | add wave -noupdate -group FIFO_1 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/ren | |||
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63 | add wave -noupdate -group FIFO_1 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/rdata | |||
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64 | add wave -noupdate -group FIFO_1 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/wen | |||
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65 | add wave -noupdate -group FIFO_1 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/wdata | |||
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66 | add wave -noupdate -group FIFO_1 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/empty | |||
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67 | add wave -noupdate -group FIFO_1 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/full | |||
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68 | add wave -noupdate -group FIFO_1 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/full_almost | |||
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69 | add wave -noupdate -group FIFO_1 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/empty_threshold | |||
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70 | add wave -noupdate -group FIFO_1 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/full_threshold | |||
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71 | add wave -noupdate -group FIFO_2 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/reuse | |||
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72 | add wave -noupdate -group FIFO_2 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/run | |||
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73 | add wave -noupdate -group FIFO_2 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/ren | |||
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74 | add wave -noupdate -group FIFO_2 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/rdata | |||
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75 | add wave -noupdate -group FIFO_2 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/wen | |||
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76 | add wave -noupdate -group FIFO_2 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/wdata | |||
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77 | add wave -noupdate -group FIFO_2 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/empty | |||
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78 | add wave -noupdate -group FIFO_2 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/full | |||
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79 | add wave -noupdate -group FIFO_2 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/full_almost | |||
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80 | add wave -noupdate -group FIFO_2 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/empty_threshold | |||
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81 | add wave -noupdate -group FIFO_2 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/full_threshold | |||
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82 | add wave -noupdate -group FIFO_3 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/reuse | |||
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83 | add wave -noupdate -group FIFO_3 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/run | |||
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84 | add wave -noupdate -group FIFO_3 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/ren | |||
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85 | add wave -noupdate -group FIFO_3 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/rdata | |||
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86 | add wave -noupdate -group FIFO_3 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/wen | |||
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87 | add wave -noupdate -group FIFO_3 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/wdata | |||
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88 | add wave -noupdate -group FIFO_3 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/empty | |||
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89 | add wave -noupdate -group FIFO_3 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/full | |||
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90 | add wave -noupdate -group FIFO_3 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/full_almost | |||
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91 | add wave -noupdate -group FIFO_3 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/empty_threshold | |||
|
92 | add wave -noupdate -group FIFO_3 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/full_threshold | |||
|
93 | add wave -noupdate -expand -group WFP_FSMDMA_0 -group WFP_FSMDMA_dma -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/dma_fifo_valid_burst | |||
|
94 | add wave -noupdate -expand -group WFP_FSMDMA_0 -group WFP_FSMDMA_dma -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/dma_fifo_data | |||
|
95 | add wave -noupdate -expand -group WFP_FSMDMA_0 -group WFP_FSMDMA_dma -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/dma_fifo_ren | |||
|
96 | add wave -noupdate -expand -group WFP_FSMDMA_0 -group WFP_FSMDMA_dma -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/dma_buffer_new | |||
|
97 | add wave -noupdate -expand -group WFP_FSMDMA_0 -group WFP_FSMDMA_dma -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/dma_buffer_addr | |||
|
98 | add wave -noupdate -expand -group WFP_FSMDMA_0 -group WFP_FSMDMA_dma -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/dma_buffer_length | |||
|
99 | add wave -noupdate -expand -group WFP_FSMDMA_0 -group WFP_FSMDMA_dma -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/dma_buffer_full | |||
|
100 | add wave -noupdate -expand -group WFP_FSMDMA_0 -group WFP_FSMDMA_dma -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/dma_buffer_full_err | |||
|
101 | add wave -noupdate -expand -group WFP_FSMDMA_0 -expand -group WFP_FSMDMA_fifo -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/fifo_buffer_time | |||
|
102 | add wave -noupdate -expand -group WFP_FSMDMA_0 -expand -group WFP_FSMDMA_fifo /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/fifo_data | |||
|
103 | add wave -noupdate -expand -group WFP_FSMDMA_0 -expand -group WFP_FSMDMA_fifo /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/fifo_empty | |||
|
104 | add wave -noupdate -expand -group WFP_FSMDMA_0 -expand -group WFP_FSMDMA_fifo /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/fifo_empty_threshold | |||
|
105 | add wave -noupdate -expand -group WFP_FSMDMA_0 -expand -group WFP_FSMDMA_fifo /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/fifo_ren | |||
|
106 | add wave -noupdate -expand -group WFP_FSMDMA_0 -expand -group WFP_FSMDMA_reg /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/status_buffer_ready | |||
|
107 | add wave -noupdate -expand -group WFP_FSMDMA_0 -expand -group WFP_FSMDMA_reg /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/addr_buffer | |||
|
108 | add wave -noupdate -expand -group WFP_FSMDMA_0 -expand -group WFP_FSMDMA_reg /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/length_buffer | |||
|
109 | add wave -noupdate -expand -group WFP_FSMDMA_0 -expand -group WFP_FSMDMA_reg /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/ready_buffer | |||
|
110 | add wave -noupdate -expand -group WFP_FSMDMA_0 -expand -group WFP_FSMDMA_reg -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/buffer_time | |||
|
111 | add wave -noupdate -expand -group WFP_FSMDMA_0 -expand -group WFP_FSMDMA_reg /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/error_buffer_full | |||
|
112 | add wave -noupdate -expand -group WFP_FSMDMA_0 /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/state | |||
|
113 | add wave -noupdate -expand -group WFP_FSMDMA_0 /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/burst_valid_s | |||
|
114 | add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/wfp_status_buffer_ready | |||
|
115 | add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/reg0_status_ready_matrix | |||
|
116 | add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/reg0_ready_matrix | |||
|
117 | add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/reg0_addr_matrix | |||
|
118 | add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/reg0_matrix_time | |||
|
119 | add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/reg1_status_ready_matrix | |||
|
120 | add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/reg1_ready_matrix | |||
|
121 | add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/reg1_addr_matrix | |||
|
122 | add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/reg1_matrix_time | |||
|
123 | add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/ready_matrix | |||
|
124 | add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/status_ready_matrix | |||
|
125 | add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/addr_matrix | |||
|
126 | add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/matrix_time | |||
|
127 | add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/current_reg | |||
|
128 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/fifo_buffer_time | |||
|
129 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/arbiter_time_out | |||
|
130 | add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/arbiter_time_out_new | |||
|
131 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/time_sel | |||
|
132 | add wave -noupdate -expand -subitemconfig {/tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/time_in(3) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/time_in(2) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/time_in(1) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/time_in(0) {-radix hexadecimal}} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/time_in | |||
51 | TreeUpdate [SetDefaultTree] |
|
133 | TreeUpdate [SetDefaultTree] | |
52 |
WaveRestoreCursors {{Cursor 1} {1 |
|
134 | WaveRestoreCursors {{Cursor 1} {111345088346 ps} 0} {{Cursor 2} {50435974615 ps} 0} {{Cursor 3} {4065545 ps} 0} {{Cursor 4} {83087041514 ps} 0} {{Cursor 5} {16894875474 ps} 0} | |
53 | configure wave -namecolwidth 618 |
|
135 | configure wave -namecolwidth 618 | |
54 |
configure wave -valuecolwidth |
|
136 | configure wave -valuecolwidth 205 | |
55 | configure wave -justifyvalue left |
|
137 | configure wave -justifyvalue left | |
56 | configure wave -signalnamewidth 0 |
|
138 | configure wave -signalnamewidth 0 | |
57 | configure wave -snapdistance 10 |
|
139 | configure wave -snapdistance 10 | |
58 | configure wave -datasetprefix 0 |
|
140 | configure wave -datasetprefix 0 | |
59 | configure wave -rowmargin 4 |
|
141 | configure wave -rowmargin 4 | |
60 | configure wave -childrowmargin 2 |
|
142 | configure wave -childrowmargin 2 | |
61 | configure wave -gridoffset 0 |
|
143 | configure wave -gridoffset 0 | |
62 | configure wave -gridperiod 1 |
|
144 | configure wave -gridperiod 1 | |
63 | configure wave -griddelta 40 |
|
145 | configure wave -griddelta 40 | |
64 | configure wave -timeline 0 |
|
146 | configure wave -timeline 0 | |
65 | configure wave -timelineunits ps |
|
147 | configure wave -timelineunits ps | |
66 | update |
|
148 | update | |
67 |
WaveRestoreZoom {0 ps} { |
|
149 | WaveRestoreZoom {4057109 ps} {4131134 ps} | |
68 | bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0 |
|
150 | bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0 | |
69 | bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0 |
|
151 | bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0 |
@@ -1,76 +1,76 | |||||
1 |
|
1 | |||
2 | LIBRARY ieee; |
|
2 | LIBRARY ieee; | |
3 | USE ieee.std_logic_1164.ALL; |
|
3 | USE ieee.std_logic_1164.ALL; | |
4 | USE ieee.numeric_std.ALL; |
|
4 | USE ieee.numeric_std.ALL; | |
5 |
|
5 | |||
6 | ENTITY DMA_SubSystem_GestionBuffer IS |
|
6 | ENTITY DMA_SubSystem_GestionBuffer IS | |
7 | GENERIC ( |
|
7 | GENERIC ( | |
8 | BUFFER_ADDR_SIZE : INTEGER := 32; |
|
8 | BUFFER_ADDR_SIZE : INTEGER := 32; | |
9 | BUFFER_LENGTH_SIZE : INTEGER := 26); |
|
9 | BUFFER_LENGTH_SIZE : INTEGER := 26); | |
10 | PORT ( |
|
10 | PORT ( | |
11 | clk : IN STD_LOGIC; |
|
11 | clk : IN STD_LOGIC; | |
12 | rstn : IN STD_LOGIC; |
|
12 | rstn : IN STD_LOGIC; | |
13 | run : IN STD_LOGIC; |
|
13 | run : IN STD_LOGIC; | |
14 | -- |
|
14 | -- | |
15 | buffer_new : IN STD_LOGIC; |
|
15 | buffer_new : IN STD_LOGIC; | |
16 | buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0); |
|
16 | buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0); | |
17 | buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0); --in 64B |
|
17 | buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0); --in 64B | |
18 | buffer_full : OUT STD_LOGIC; |
|
18 | buffer_full : OUT STD_LOGIC; | |
19 | buffer_full_err : OUT STD_LOGIC; |
|
19 | buffer_full_err : OUT STD_LOGIC; | |
20 | -- |
|
20 | -- | |
21 | burst_send : IN STD_LOGIC; |
|
21 | burst_send : IN STD_LOGIC; | |
22 | burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0) |
|
22 | burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0) | |
23 | ); |
|
23 | ); | |
24 | END DMA_SubSystem_GestionBuffer; |
|
24 | END DMA_SubSystem_GestionBuffer; | |
25 |
|
25 | |||
26 |
|
26 | |||
27 | ARCHITECTURE beh OF DMA_SubSystem_GestionBuffer IS |
|
27 | ARCHITECTURE beh OF DMA_SubSystem_GestionBuffer IS | |
28 |
|
28 | |||
29 | TYPE state_DMA_GestionBuffer IS (IDLE, ON_GOING); |
|
29 | TYPE state_DMA_GestionBuffer IS (IDLE, ON_GOING); | |
30 | SIGNAL state : state_DMA_GestionBuffer; |
|
30 | SIGNAL state : state_DMA_GestionBuffer; | |
31 |
|
31 | |||
32 | SIGNAL burst_send_counter : STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0); |
|
32 | SIGNAL burst_send_counter : STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0); | |
33 | SIGNAL burst_send_counter_add1 : STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0); |
|
33 | SIGNAL burst_send_counter_add1 : STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0); | |
34 | SIGNAL addr_shift : STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0); |
|
34 | SIGNAL addr_shift : STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0); | |
35 |
|
35 | |||
36 | BEGIN |
|
36 | BEGIN | |
37 | addr_shift <= burst_send_counter & "000000"; |
|
37 | addr_shift <= burst_send_counter & "000000"; | |
38 | burst_addr <= STD_LOGIC_VECTOR(unsigned(buffer_addr) + unsigned(addr_shift)); |
|
38 | burst_addr <= STD_LOGIC_VECTOR(unsigned(buffer_addr) + unsigned(addr_shift)); | |
39 |
|
39 | |||
40 | burst_send_counter_add1 <= STD_LOGIC_VECTOR(unsigned(burst_send_counter) + 1); |
|
40 | burst_send_counter_add1 <= STD_LOGIC_VECTOR(unsigned(burst_send_counter) + 1); | |
41 |
|
41 | |||
42 | PROCESS (clk, rstn) |
|
42 | PROCESS (clk, rstn) | |
43 | BEGIN -- PROCESS |
|
43 | BEGIN -- PROCESS | |
44 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
44 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
45 | burst_send_counter <= (OTHERS => '0'); |
|
45 | burst_send_counter <= (OTHERS => '0'); | |
46 | state <= IDLE; |
|
46 | state <= IDLE; | |
47 | buffer_full <= '0'; |
|
47 | buffer_full <= '0'; | |
48 | buffer_full_err <= '0'; |
|
48 | buffer_full_err <= '0'; | |
49 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
49 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
50 | CASE state IS |
|
50 | CASE state IS | |
51 | WHEN IDLE => |
|
51 | WHEN IDLE => | |
52 | burst_send_counter <= (OTHERS => '0'); |
|
52 | burst_send_counter <= (OTHERS => '0'); | |
53 | buffer_full_err <= burst_send; |
|
53 | buffer_full_err <= burst_send; | |
54 | buffer_full <= '0'; |
|
54 | buffer_full <= '0'; | |
55 | IF buffer_new = '1' THEN |
|
55 | IF buffer_new = '1' THEN | |
56 | state <= ON_GOING; |
|
56 | state <= ON_GOING; | |
57 | END IF; |
|
57 | END IF; | |
58 |
|
58 | |||
59 | WHEN ON_GOING => |
|
59 | WHEN ON_GOING => | |
60 | buffer_full_err <= '0'; |
|
60 | buffer_full_err <= '0'; | |
61 | buffer_full <= '0'; |
|
61 | buffer_full <= '0'; | |
62 | IF burst_send = '1' THEN |
|
62 | IF burst_send = '1' THEN | |
63 | IF burst_send_counter_add1 < buffer_length THEN |
|
63 | IF unsigned(burst_send_counter_add1) < unsigned(buffer_length) THEN | |
64 | burst_send_counter <= burst_send_counter_add1; |
|
64 | burst_send_counter <= burst_send_counter_add1; | |
65 | ELSE |
|
65 | ELSE | |
66 | buffer_full <= '1'; |
|
66 | buffer_full <= '1'; | |
67 | state <= IDLE; |
|
67 | state <= IDLE; | |
68 | END IF; |
|
68 | END IF; | |
69 | END IF; |
|
69 | END IF; | |
70 |
|
70 | |||
71 | WHEN OTHERS => NULL; |
|
71 | WHEN OTHERS => NULL; | |
72 | END CASE; |
|
72 | END CASE; | |
73 | END IF; |
|
73 | END IF; | |
74 | END PROCESS; |
|
74 | END PROCESS; | |
75 |
|
75 | |||
76 | END beh; |
|
76 | END beh; |
@@ -1,560 +1,565 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 | USE ieee.numeric_std.ALL; |
|
3 | USE ieee.numeric_std.ALL; | |
4 |
|
4 | |||
5 | LIBRARY lpp; |
|
5 | LIBRARY lpp; | |
6 | USE lpp.lpp_ad_conv.ALL; |
|
6 | USE lpp.lpp_ad_conv.ALL; | |
7 | USE lpp.iir_filter.ALL; |
|
7 | USE lpp.iir_filter.ALL; | |
8 | USE lpp.FILTERcfg.ALL; |
|
8 | USE lpp.FILTERcfg.ALL; | |
9 | USE lpp.lpp_memory.ALL; |
|
9 | USE lpp.lpp_memory.ALL; | |
10 | USE lpp.lpp_waveform_pkg.ALL; |
|
10 | USE lpp.lpp_waveform_pkg.ALL; | |
11 | USE lpp.lpp_dma_pkg.ALL; |
|
11 | USE lpp.lpp_dma_pkg.ALL; | |
12 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
12 | USE lpp.lpp_top_lfr_pkg.ALL; | |
13 | USE lpp.lpp_lfr_pkg.ALL; |
|
13 | USE lpp.lpp_lfr_pkg.ALL; | |
14 | USE lpp.general_purpose.ALL; |
|
14 | USE lpp.general_purpose.ALL; | |
15 |
|
15 | |||
16 | LIBRARY techmap; |
|
16 | LIBRARY techmap; | |
17 | USE techmap.gencomp.ALL; |
|
17 | USE techmap.gencomp.ALL; | |
18 |
|
18 | |||
19 | LIBRARY grlib; |
|
19 | LIBRARY grlib; | |
20 | USE grlib.amba.ALL; |
|
20 | USE grlib.amba.ALL; | |
21 | USE grlib.stdlib.ALL; |
|
21 | USE grlib.stdlib.ALL; | |
22 | USE grlib.devices.ALL; |
|
22 | USE grlib.devices.ALL; | |
23 | USE GRLIB.DMA2AHB_Package.ALL; |
|
23 | USE GRLIB.DMA2AHB_Package.ALL; | |
24 |
|
24 | |||
25 | ENTITY lpp_lfr IS |
|
25 | ENTITY lpp_lfr IS | |
26 | GENERIC ( |
|
26 | GENERIC ( | |
27 | Mem_use : INTEGER := use_RAM; |
|
27 | Mem_use : INTEGER := use_RAM; | |
28 | nb_data_by_buffer_size : INTEGER := 11; |
|
28 | nb_data_by_buffer_size : INTEGER := 11; | |
29 | -- nb_word_by_buffer_size : INTEGER := 11; -- TODO |
|
29 | -- nb_word_by_buffer_size : INTEGER := 11; -- TODO | |
30 | nb_snapshot_param_size : INTEGER := 11; |
|
30 | nb_snapshot_param_size : INTEGER := 11; | |
31 | delta_vector_size : INTEGER := 20; |
|
31 | delta_vector_size : INTEGER := 20; | |
32 | delta_vector_size_f0_2 : INTEGER := 7; |
|
32 | delta_vector_size_f0_2 : INTEGER := 7; | |
33 |
|
33 | |||
34 | pindex : INTEGER := 4; |
|
34 | pindex : INTEGER := 4; | |
35 | paddr : INTEGER := 4; |
|
35 | paddr : INTEGER := 4; | |
36 | pmask : INTEGER := 16#fff#; |
|
36 | pmask : INTEGER := 16#fff#; | |
37 | pirq_ms : INTEGER := 0; |
|
37 | pirq_ms : INTEGER := 0; | |
38 | pirq_wfp : INTEGER := 1; |
|
38 | pirq_wfp : INTEGER := 1; | |
39 |
|
39 | |||
40 | hindex : INTEGER := 2; |
|
40 | hindex : INTEGER := 2; | |
41 |
|
41 | |||
42 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0') |
|
42 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0') | |
43 |
|
43 | |||
44 | ); |
|
44 | ); | |
45 | PORT ( |
|
45 | PORT ( | |
46 | clk : IN STD_LOGIC; |
|
46 | clk : IN STD_LOGIC; | |
47 | rstn : IN STD_LOGIC; |
|
47 | rstn : IN STD_LOGIC; | |
48 | -- SAMPLE |
|
48 | -- SAMPLE | |
49 | sample_B : IN Samples(2 DOWNTO 0); |
|
49 | sample_B : IN Samples(2 DOWNTO 0); | |
50 | sample_E : IN Samples(4 DOWNTO 0); |
|
50 | sample_E : IN Samples(4 DOWNTO 0); | |
51 | sample_val : IN STD_LOGIC; |
|
51 | sample_val : IN STD_LOGIC; | |
52 | -- APB |
|
52 | -- APB | |
53 | apbi : IN apb_slv_in_type; |
|
53 | apbi : IN apb_slv_in_type; | |
54 | apbo : OUT apb_slv_out_type; |
|
54 | apbo : OUT apb_slv_out_type; | |
55 | -- AHB |
|
55 | -- AHB | |
56 | ahbi : IN AHB_Mst_In_Type; |
|
56 | ahbi : IN AHB_Mst_In_Type; | |
57 | ahbo : OUT AHB_Mst_Out_Type; |
|
57 | ahbo : OUT AHB_Mst_Out_Type; | |
58 | -- TIME |
|
58 | -- TIME | |
59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
61 | -- |
|
61 | -- | |
62 | data_shaping_BW : OUT STD_LOGIC |
|
62 | data_shaping_BW : OUT STD_LOGIC | |
63 | -- |
|
63 | -- | |
64 | -- |
|
64 | -- | |
65 | -- observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
65 | -- observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); | |
66 | -- observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
66 | -- observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); | |
67 |
|
67 | |||
68 | -- observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
68 | -- observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
69 |
|
69 | |||
70 | --debug |
|
70 | --debug | |
71 | --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
71 | --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
72 | --debug_f0_data_valid : OUT STD_LOGIC; |
|
72 | --debug_f0_data_valid : OUT STD_LOGIC; | |
73 | --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
73 | --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
74 | --debug_f1_data_valid : OUT STD_LOGIC; |
|
74 | --debug_f1_data_valid : OUT STD_LOGIC; | |
75 | --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
75 | --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
76 | --debug_f2_data_valid : OUT STD_LOGIC; |
|
76 | --debug_f2_data_valid : OUT STD_LOGIC; | |
77 | --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
77 | --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
78 | --debug_f3_data_valid : OUT STD_LOGIC; |
|
78 | --debug_f3_data_valid : OUT STD_LOGIC; | |
79 |
|
79 | |||
80 | ---- debug FIFO_IN |
|
80 | ---- debug FIFO_IN | |
81 | --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
81 | --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
82 | --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; |
|
82 | --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; | |
83 | --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
83 | --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
84 | --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; |
|
84 | --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; | |
85 | --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
85 | --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
86 | --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; |
|
86 | --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; | |
87 | --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
87 | --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
88 | --debug_f3_data_fifo_in_valid : OUT STD_LOGIC; |
|
88 | --debug_f3_data_fifo_in_valid : OUT STD_LOGIC; | |
89 |
|
89 | |||
90 | ----debug FIFO OUT |
|
90 | ----debug FIFO OUT | |
91 | --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
92 | --debug_f0_data_fifo_out_valid : OUT STD_LOGIC; |
|
92 | --debug_f0_data_fifo_out_valid : OUT STD_LOGIC; | |
93 | --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
93 | --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
94 | --debug_f1_data_fifo_out_valid : OUT STD_LOGIC; |
|
94 | --debug_f1_data_fifo_out_valid : OUT STD_LOGIC; | |
95 | --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
95 | --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
96 | --debug_f2_data_fifo_out_valid : OUT STD_LOGIC; |
|
96 | --debug_f2_data_fifo_out_valid : OUT STD_LOGIC; | |
97 | --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
97 | --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
98 | --debug_f3_data_fifo_out_valid : OUT STD_LOGIC; |
|
98 | --debug_f3_data_fifo_out_valid : OUT STD_LOGIC; | |
99 |
|
99 | |||
100 | ----debug DMA IN |
|
100 | ----debug DMA IN | |
101 | --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
101 | --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
102 | --debug_f0_data_dma_in_valid : OUT STD_LOGIC; |
|
102 | --debug_f0_data_dma_in_valid : OUT STD_LOGIC; | |
103 | --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
103 | --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
104 | --debug_f1_data_dma_in_valid : OUT STD_LOGIC; |
|
104 | --debug_f1_data_dma_in_valid : OUT STD_LOGIC; | |
105 | --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
105 | --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
106 | --debug_f2_data_dma_in_valid : OUT STD_LOGIC; |
|
106 | --debug_f2_data_dma_in_valid : OUT STD_LOGIC; | |
107 | --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
107 | --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
108 | --debug_f3_data_dma_in_valid : OUT STD_LOGIC |
|
108 | --debug_f3_data_dma_in_valid : OUT STD_LOGIC | |
109 | ); |
|
109 | ); | |
110 | END lpp_lfr; |
|
110 | END lpp_lfr; | |
111 |
|
111 | |||
112 | ARCHITECTURE beh OF lpp_lfr IS |
|
112 | ARCHITECTURE beh OF lpp_lfr IS | |
113 | --SIGNAL sample : Samples14v(7 DOWNTO 0); |
|
113 | --SIGNAL sample : Samples14v(7 DOWNTO 0); | |
114 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
|
114 | SIGNAL sample_s : Samples(7 DOWNTO 0); | |
115 | -- |
|
115 | -- | |
116 | SIGNAL data_shaping_SP0 : STD_LOGIC; |
|
116 | SIGNAL data_shaping_SP0 : STD_LOGIC; | |
117 | SIGNAL data_shaping_SP1 : STD_LOGIC; |
|
117 | SIGNAL data_shaping_SP1 : STD_LOGIC; | |
118 | SIGNAL data_shaping_R0 : STD_LOGIC; |
|
118 | SIGNAL data_shaping_R0 : STD_LOGIC; | |
119 | SIGNAL data_shaping_R1 : STD_LOGIC; |
|
119 | SIGNAL data_shaping_R1 : STD_LOGIC; | |
120 | SIGNAL data_shaping_R2 : STD_LOGIC; |
|
120 | SIGNAL data_shaping_R2 : STD_LOGIC; | |
121 | -- |
|
121 | -- | |
122 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
122 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
123 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
123 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
124 | SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
124 | SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
125 | -- |
|
125 | -- | |
126 | SIGNAL sample_f0_val : STD_LOGIC; |
|
126 | SIGNAL sample_f0_val : STD_LOGIC; | |
127 | SIGNAL sample_f1_val : STD_LOGIC; |
|
127 | SIGNAL sample_f1_val : STD_LOGIC; | |
128 | SIGNAL sample_f2_val : STD_LOGIC; |
|
128 | SIGNAL sample_f2_val : STD_LOGIC; | |
129 | SIGNAL sample_f3_val : STD_LOGIC; |
|
129 | SIGNAL sample_f3_val : STD_LOGIC; | |
130 | -- |
|
130 | -- | |
131 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
131 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
132 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
132 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
133 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
133 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
134 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
134 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
135 | -- |
|
135 | -- | |
136 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
136 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
137 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
137 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
138 | SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
138 | SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
139 |
|
139 | |||
140 | -- SM |
|
140 | -- SM | |
141 | SIGNAL ready_matrix_f0 : STD_LOGIC; |
|
141 | SIGNAL ready_matrix_f0 : STD_LOGIC; | |
142 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; |
|
142 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; | |
143 | SIGNAL ready_matrix_f1 : STD_LOGIC; |
|
143 | SIGNAL ready_matrix_f1 : STD_LOGIC; | |
144 | SIGNAL ready_matrix_f2 : STD_LOGIC; |
|
144 | SIGNAL ready_matrix_f2 : STD_LOGIC; | |
145 | -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC; |
|
145 | -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC; | |
146 | -- SIGNAL error_bad_component_error : STD_LOGIC; |
|
146 | -- SIGNAL error_bad_component_error : STD_LOGIC; | |
147 | -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
147 | -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
148 | SIGNAL status_ready_matrix_f0 : STD_LOGIC; |
|
148 | SIGNAL status_ready_matrix_f0 : STD_LOGIC; | |
149 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; |
|
149 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; | |
150 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; |
|
150 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; | |
151 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; |
|
151 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; | |
152 | -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; |
|
152 | -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; | |
153 | -- SIGNAL status_error_bad_component_error : STD_LOGIC; |
|
153 | -- SIGNAL status_error_bad_component_error : STD_LOGIC; | |
154 | --SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; |
|
154 | --SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; | |
155 | -- SIGNAL config_active_interruption_onError : STD_LOGIC; |
|
155 | -- SIGNAL config_active_interruption_onError : STD_LOGIC; | |
156 | SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
156 | SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
157 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
157 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
158 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
158 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
159 | SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
159 | SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0); | |
160 | SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
160 | SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0); | |
161 | SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
161 | SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0); | |
162 |
|
162 | |||
163 | -- WFP |
|
163 | -- WFP | |
164 | --SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
164 | --SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
165 | --SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
165 | --SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
166 | --SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
166 | --SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
167 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
167 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
168 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
168 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
169 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
169 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
170 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
170 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
171 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
171 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
172 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
172 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
173 |
|
173 | |||
174 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
174 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
175 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
175 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
176 | SIGNAL enable_f0 : STD_LOGIC; |
|
176 | SIGNAL enable_f0 : STD_LOGIC; | |
177 | SIGNAL enable_f1 : STD_LOGIC; |
|
177 | SIGNAL enable_f1 : STD_LOGIC; | |
178 | SIGNAL enable_f2 : STD_LOGIC; |
|
178 | SIGNAL enable_f2 : STD_LOGIC; | |
179 | SIGNAL enable_f3 : STD_LOGIC; |
|
179 | SIGNAL enable_f3 : STD_LOGIC; | |
180 | SIGNAL burst_f0 : STD_LOGIC; |
|
180 | SIGNAL burst_f0 : STD_LOGIC; | |
181 | SIGNAL burst_f1 : STD_LOGIC; |
|
181 | SIGNAL burst_f1 : STD_LOGIC; | |
182 | SIGNAL burst_f2 : STD_LOGIC; |
|
182 | SIGNAL burst_f2 : STD_LOGIC; | |
183 |
|
183 | |||
184 | SIGNAL run : STD_LOGIC; |
|
184 | SIGNAL run : STD_LOGIC; | |
185 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
185 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
186 |
|
186 | |||
187 | ----------------------------------------------------------------------------- |
|
187 | ----------------------------------------------------------------------------- | |
188 | -- |
|
188 | -- | |
189 | ----------------------------------------------------------------------------- |
|
189 | ----------------------------------------------------------------------------- | |
190 | SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
190 | SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
191 | SIGNAL data_f0_data_out_valid_s : STD_LOGIC; |
|
191 | SIGNAL data_f0_data_out_valid_s : STD_LOGIC; | |
192 | SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; |
|
192 | SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; | |
193 | --f1 |
|
193 | --f1 | |
194 | SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
194 | SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
195 | SIGNAL data_f1_data_out_valid_s : STD_LOGIC; |
|
195 | SIGNAL data_f1_data_out_valid_s : STD_LOGIC; | |
196 | SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; |
|
196 | SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; | |
197 | --f2 |
|
197 | --f2 | |
198 | SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
198 | SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
199 | SIGNAL data_f2_data_out_valid_s : STD_LOGIC; |
|
199 | SIGNAL data_f2_data_out_valid_s : STD_LOGIC; | |
200 | SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; |
|
200 | SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; | |
201 | --f3 |
|
201 | --f3 | |
202 | SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
202 | SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
203 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; |
|
203 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; | |
204 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; |
|
204 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; | |
205 |
|
205 | |||
206 | SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
206 | SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
207 | SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4 DOWNTO 0); |
|
207 | SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4 DOWNTO 0); | |
208 | SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
208 | SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0); | |
209 | SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
209 | SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
210 | SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
|
210 | SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |
211 | SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
211 | SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
212 | ----------------------------------------------------------------------------- |
|
212 | ----------------------------------------------------------------------------- | |
213 | -- DMA RR |
|
213 | -- DMA RR | |
214 | ----------------------------------------------------------------------------- |
|
214 | ----------------------------------------------------------------------------- | |
215 | SIGNAL dma_sel_valid : STD_LOGIC; |
|
215 | SIGNAL dma_sel_valid : STD_LOGIC; | |
216 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
216 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
217 | SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
217 | SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
218 | SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
218 | SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
219 | SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
219 | SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
220 |
|
220 | |||
221 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
221 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
222 | SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
222 | SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
223 |
|
223 | |||
224 | ----------------------------------------------------------------------------- |
|
224 | ----------------------------------------------------------------------------- | |
225 | -- DMA_REG |
|
225 | -- DMA_REG | |
226 | ----------------------------------------------------------------------------- |
|
226 | ----------------------------------------------------------------------------- | |
227 | SIGNAL ongoing_reg : STD_LOGIC; |
|
227 | SIGNAL ongoing_reg : STD_LOGIC; | |
228 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
228 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
229 | SIGNAL dma_send_reg : STD_LOGIC; |
|
229 | SIGNAL dma_send_reg : STD_LOGIC; | |
230 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
230 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
231 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
231 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
232 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
232 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
233 |
|
233 | |||
234 |
|
234 | |||
235 | ----------------------------------------------------------------------------- |
|
235 | ----------------------------------------------------------------------------- | |
236 | -- DMA |
|
236 | -- DMA | |
237 | ----------------------------------------------------------------------------- |
|
237 | ----------------------------------------------------------------------------- | |
238 | SIGNAL dma_send : STD_LOGIC; |
|
238 | SIGNAL dma_send : STD_LOGIC; | |
239 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
239 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
240 | SIGNAL dma_done : STD_LOGIC; |
|
240 | SIGNAL dma_done : STD_LOGIC; | |
241 | SIGNAL dma_ren : STD_LOGIC; |
|
241 | SIGNAL dma_ren : STD_LOGIC; | |
242 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
242 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
243 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
243 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
244 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
244 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
245 |
|
245 | |||
246 | ----------------------------------------------------------------------------- |
|
246 | ----------------------------------------------------------------------------- | |
247 | -- MS |
|
247 | -- MS | |
248 | ----------------------------------------------------------------------------- |
|
248 | ----------------------------------------------------------------------------- | |
249 |
|
249 | |||
250 | SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
250 | SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
251 | SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
251 | SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
252 | SIGNAL data_ms_valid : STD_LOGIC; |
|
252 | SIGNAL data_ms_valid : STD_LOGIC; | |
253 | SIGNAL data_ms_valid_burst : STD_LOGIC; |
|
253 | SIGNAL data_ms_valid_burst : STD_LOGIC; | |
254 | SIGNAL data_ms_ren : STD_LOGIC; |
|
254 | SIGNAL data_ms_ren : STD_LOGIC; | |
255 | SIGNAL data_ms_done : STD_LOGIC; |
|
255 | SIGNAL data_ms_done : STD_LOGIC; | |
256 | SIGNAL dma_ms_ongoing : STD_LOGIC; |
|
256 | SIGNAL dma_ms_ongoing : STD_LOGIC; | |
257 |
|
257 | |||
258 | SIGNAL run_ms : STD_LOGIC; |
|
258 | SIGNAL run_ms : STD_LOGIC; | |
259 | SIGNAL ms_softandhard_rstn : STD_LOGIC; |
|
259 | SIGNAL ms_softandhard_rstn : STD_LOGIC; | |
260 |
|
260 | |||
261 | SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
261 | SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
262 | -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
262 | -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
263 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
263 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
264 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
264 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
265 |
|
265 | |||
266 |
|
266 | |||
267 | SIGNAL error_buffer_full : STD_LOGIC; |
|
267 | SIGNAL error_buffer_full : STD_LOGIC; | |
268 | SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
268 | SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); | |
269 |
|
269 | |||
270 | -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
270 | -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
271 | SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
271 | SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
272 |
|
272 | |||
273 | ----------------------------------------------------------------------------- |
|
273 | ----------------------------------------------------------------------------- | |
274 | SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
274 | SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
275 | SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); |
|
275 | SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); | |
276 | SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
276 | SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
277 | SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
277 | SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
278 | SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); |
|
278 | SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); | |
279 | SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0); |
|
279 | SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0); | |
280 | SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
280 | SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
281 | SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
281 | SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
282 | SIGNAL dma_grant_error : STD_LOGIC; |
|
282 | SIGNAL dma_grant_error : STD_LOGIC; | |
283 |
|
283 | |||
|
284 | ----------------------------------------------------------------------------- | |||
|
285 | SIGNAL run_dma : STD_LOGIC; | |||
284 | BEGIN |
|
286 | BEGIN | |
285 |
|
287 | |||
286 | sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); |
|
288 | sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); | |
287 | sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); |
|
289 | sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); | |
288 |
|
290 | |||
289 | --all_channel : FOR i IN 7 DOWNTO 0 GENERATE |
|
291 | --all_channel : FOR i IN 7 DOWNTO 0 GENERATE | |
290 | -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); |
|
292 | -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); | |
291 | --END GENERATE all_channel; |
|
293 | --END GENERATE all_channel; | |
292 |
|
294 | |||
293 | ----------------------------------------------------------------------------- |
|
295 | ----------------------------------------------------------------------------- | |
294 | lpp_lfr_filter_1 : lpp_lfr_filter |
|
296 | lpp_lfr_filter_1 : lpp_lfr_filter | |
295 | GENERIC MAP ( |
|
297 | GENERIC MAP ( | |
296 | Mem_use => Mem_use) |
|
298 | Mem_use => Mem_use) | |
297 | PORT MAP ( |
|
299 | PORT MAP ( | |
298 | sample => sample_s, |
|
300 | sample => sample_s, | |
299 | sample_val => sample_val, |
|
301 | sample_val => sample_val, | |
300 | clk => clk, |
|
302 | clk => clk, | |
301 | rstn => rstn, |
|
303 | rstn => rstn, | |
302 | data_shaping_SP0 => data_shaping_SP0, |
|
304 | data_shaping_SP0 => data_shaping_SP0, | |
303 | data_shaping_SP1 => data_shaping_SP1, |
|
305 | data_shaping_SP1 => data_shaping_SP1, | |
304 | data_shaping_R0 => data_shaping_R0, |
|
306 | data_shaping_R0 => data_shaping_R0, | |
305 | data_shaping_R1 => data_shaping_R1, |
|
307 | data_shaping_R1 => data_shaping_R1, | |
306 | data_shaping_R2 => data_shaping_R2, |
|
308 | data_shaping_R2 => data_shaping_R2, | |
307 | sample_f0_val => sample_f0_val, |
|
309 | sample_f0_val => sample_f0_val, | |
308 | sample_f1_val => sample_f1_val, |
|
310 | sample_f1_val => sample_f1_val, | |
309 | sample_f2_val => sample_f2_val, |
|
311 | sample_f2_val => sample_f2_val, | |
310 | sample_f3_val => sample_f3_val, |
|
312 | sample_f3_val => sample_f3_val, | |
311 | sample_f0_wdata => sample_f0_data, |
|
313 | sample_f0_wdata => sample_f0_data, | |
312 | sample_f1_wdata => sample_f1_data, |
|
314 | sample_f1_wdata => sample_f1_data, | |
313 | sample_f2_wdata => sample_f2_data, |
|
315 | sample_f2_wdata => sample_f2_data, | |
314 | sample_f3_wdata => sample_f3_data); |
|
316 | sample_f3_wdata => sample_f3_data); | |
315 |
|
317 | |||
316 | ----------------------------------------------------------------------------- |
|
318 | ----------------------------------------------------------------------------- | |
317 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg |
|
319 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg | |
318 | GENERIC MAP ( |
|
320 | GENERIC MAP ( | |
319 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
321 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |
320 | -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO |
|
322 | -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO | |
321 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
323 | nb_snapshot_param_size => nb_snapshot_param_size, | |
322 | delta_vector_size => delta_vector_size, |
|
324 | delta_vector_size => delta_vector_size, | |
323 | delta_vector_size_f0_2 => delta_vector_size_f0_2, |
|
325 | delta_vector_size_f0_2 => delta_vector_size_f0_2, | |
324 | pindex => pindex, |
|
326 | pindex => pindex, | |
325 | paddr => paddr, |
|
327 | paddr => paddr, | |
326 | pmask => pmask, |
|
328 | pmask => pmask, | |
327 | pirq_ms => pirq_ms, |
|
329 | pirq_ms => pirq_ms, | |
328 | pirq_wfp => pirq_wfp, |
|
330 | pirq_wfp => pirq_wfp, | |
329 | top_lfr_version => top_lfr_version) |
|
331 | top_lfr_version => top_lfr_version) | |
330 | PORT MAP ( |
|
332 | PORT MAP ( | |
331 | HCLK => clk, |
|
333 | HCLK => clk, | |
332 | HRESETn => rstn, |
|
334 | HRESETn => rstn, | |
333 | apbi => apbi, |
|
335 | apbi => apbi, | |
334 | apbo => apbo, |
|
336 | apbo => apbo, | |
335 |
|
337 | |||
336 | run_ms => run_ms, |
|
338 | run_ms => run_ms, | |
337 |
|
339 | |||
338 | ready_matrix_f0 => ready_matrix_f0, |
|
340 | ready_matrix_f0 => ready_matrix_f0, | |
339 | ready_matrix_f1 => ready_matrix_f1, |
|
341 | ready_matrix_f1 => ready_matrix_f1, | |
340 | ready_matrix_f2 => ready_matrix_f2, |
|
342 | ready_matrix_f2 => ready_matrix_f2, | |
341 | error_buffer_full => error_buffer_full, -- TODO |
|
343 | error_buffer_full => error_buffer_full, -- TODO | |
342 | error_input_fifo_write => error_input_fifo_write, -- TODO |
|
344 | error_input_fifo_write => error_input_fifo_write, -- TODO | |
343 | status_ready_matrix_f0 => status_ready_matrix_f0, |
|
345 | status_ready_matrix_f0 => status_ready_matrix_f0, | |
344 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
346 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
345 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
347 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
346 |
|
348 | |||
347 | matrix_time_f0 => matrix_time_f0, |
|
349 | matrix_time_f0 => matrix_time_f0, | |
348 | matrix_time_f1 => matrix_time_f1, |
|
350 | matrix_time_f1 => matrix_time_f1, | |
349 | matrix_time_f2 => matrix_time_f2, |
|
351 | matrix_time_f2 => matrix_time_f2, | |
350 |
|
352 | |||
351 | addr_matrix_f0 => addr_matrix_f0, |
|
353 | addr_matrix_f0 => addr_matrix_f0, | |
352 | addr_matrix_f1 => addr_matrix_f1, |
|
354 | addr_matrix_f1 => addr_matrix_f1, | |
353 | addr_matrix_f2 => addr_matrix_f2, |
|
355 | addr_matrix_f2 => addr_matrix_f2, | |
354 |
|
356 | |||
355 | length_matrix_f0 => length_matrix_f0, |
|
357 | length_matrix_f0 => length_matrix_f0, | |
356 | length_matrix_f1 => length_matrix_f1, |
|
358 | length_matrix_f1 => length_matrix_f1, | |
357 | length_matrix_f2 => length_matrix_f2, |
|
359 | length_matrix_f2 => length_matrix_f2, | |
358 | ------------------------------------------------------------------------- |
|
360 | ------------------------------------------------------------------------- | |
359 | --status_full => status_full, -- TODo |
|
361 | --status_full => status_full, -- TODo | |
360 | --status_full_ack => status_full_ack, -- TODo |
|
362 | --status_full_ack => status_full_ack, -- TODo | |
361 | --status_full_err => status_full_err, -- TODo |
|
363 | --status_full_err => status_full_err, -- TODo | |
362 | status_new_err => status_new_err, |
|
364 | status_new_err => status_new_err, | |
363 | data_shaping_BW => data_shaping_BW, |
|
365 | data_shaping_BW => data_shaping_BW, | |
364 | data_shaping_SP0 => data_shaping_SP0, |
|
366 | data_shaping_SP0 => data_shaping_SP0, | |
365 | data_shaping_SP1 => data_shaping_SP1, |
|
367 | data_shaping_SP1 => data_shaping_SP1, | |
366 | data_shaping_R0 => data_shaping_R0, |
|
368 | data_shaping_R0 => data_shaping_R0, | |
367 | data_shaping_R1 => data_shaping_R1, |
|
369 | data_shaping_R1 => data_shaping_R1, | |
368 | data_shaping_R2 => data_shaping_R2, |
|
370 | data_shaping_R2 => data_shaping_R2, | |
369 | delta_snapshot => delta_snapshot, |
|
371 | delta_snapshot => delta_snapshot, | |
370 | delta_f0 => delta_f0, |
|
372 | delta_f0 => delta_f0, | |
371 | delta_f0_2 => delta_f0_2, |
|
373 | delta_f0_2 => delta_f0_2, | |
372 | delta_f1 => delta_f1, |
|
374 | delta_f1 => delta_f1, | |
373 | delta_f2 => delta_f2, |
|
375 | delta_f2 => delta_f2, | |
374 | nb_data_by_buffer => nb_data_by_buffer, |
|
376 | nb_data_by_buffer => nb_data_by_buffer, | |
375 | -- nb_word_by_buffer => nb_word_by_buffer, -- TODO |
|
377 | -- nb_word_by_buffer => nb_word_by_buffer, -- TODO | |
376 | nb_snapshot_param => nb_snapshot_param, |
|
378 | nb_snapshot_param => nb_snapshot_param, | |
377 | enable_f0 => enable_f0, |
|
379 | enable_f0 => enable_f0, | |
378 | enable_f1 => enable_f1, |
|
380 | enable_f1 => enable_f1, | |
379 | enable_f2 => enable_f2, |
|
381 | enable_f2 => enable_f2, | |
380 | enable_f3 => enable_f3, |
|
382 | enable_f3 => enable_f3, | |
381 | burst_f0 => burst_f0, |
|
383 | burst_f0 => burst_f0, | |
382 | burst_f1 => burst_f1, |
|
384 | burst_f1 => burst_f1, | |
383 | burst_f2 => burst_f2, |
|
385 | burst_f2 => burst_f2, | |
384 | run => run, |
|
386 | run => run, | |
385 | start_date => start_date, |
|
387 | start_date => start_date, | |
386 | -- debug_signal => debug_signal, |
|
388 | -- debug_signal => debug_signal, | |
387 | wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO |
|
389 | wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO | |
388 | wfp_addr_buffer => wfp_addr_buffer,-- TODO |
|
390 | wfp_addr_buffer => wfp_addr_buffer,-- TODO | |
389 | wfp_length_buffer => wfp_length_buffer,-- TODO |
|
391 | wfp_length_buffer => wfp_length_buffer,-- TODO | |
390 |
|
392 | |||
391 | wfp_ready_buffer => wfp_ready_buffer,-- TODO |
|
393 | wfp_ready_buffer => wfp_ready_buffer,-- TODO | |
392 | wfp_buffer_time => wfp_buffer_time,-- TODO |
|
394 | wfp_buffer_time => wfp_buffer_time,-- TODO | |
393 | wfp_error_buffer_full => wfp_error_buffer_full -- TODO |
|
395 | wfp_error_buffer_full => wfp_error_buffer_full -- TODO | |
394 | ); |
|
396 | ); | |
395 |
|
397 | |||
396 | ----------------------------------------------------------------------------- |
|
398 | ----------------------------------------------------------------------------- | |
397 | ----------------------------------------------------------------------------- |
|
399 | ----------------------------------------------------------------------------- | |
398 | lpp_waveform_1 : lpp_waveform |
|
400 | lpp_waveform_1 : lpp_waveform | |
399 | GENERIC MAP ( |
|
401 | GENERIC MAP ( | |
400 | tech => inferred, |
|
402 | tech => inferred, | |
401 | data_size => 6*16, |
|
403 | data_size => 6*16, | |
402 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
404 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |
403 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
405 | nb_snapshot_param_size => nb_snapshot_param_size, | |
404 | delta_vector_size => delta_vector_size, |
|
406 | delta_vector_size => delta_vector_size, | |
405 | delta_vector_size_f0_2 => delta_vector_size_f0_2 |
|
407 | delta_vector_size_f0_2 => delta_vector_size_f0_2 | |
406 | ) |
|
408 | ) | |
407 | PORT MAP ( |
|
409 | PORT MAP ( | |
408 | clk => clk, |
|
410 | clk => clk, | |
409 | rstn => rstn, |
|
411 | rstn => rstn, | |
410 |
|
412 | |||
411 | reg_run => run, |
|
413 | reg_run => run, | |
412 | reg_start_date => start_date, |
|
414 | reg_start_date => start_date, | |
413 | reg_delta_snapshot => delta_snapshot, |
|
415 | reg_delta_snapshot => delta_snapshot, | |
414 | reg_delta_f0 => delta_f0, |
|
416 | reg_delta_f0 => delta_f0, | |
415 | reg_delta_f0_2 => delta_f0_2, |
|
417 | reg_delta_f0_2 => delta_f0_2, | |
416 | reg_delta_f1 => delta_f1, |
|
418 | reg_delta_f1 => delta_f1, | |
417 | reg_delta_f2 => delta_f2, |
|
419 | reg_delta_f2 => delta_f2, | |
418 |
|
420 | |||
419 | enable_f0 => enable_f0, |
|
421 | enable_f0 => enable_f0, | |
420 | enable_f1 => enable_f1, |
|
422 | enable_f1 => enable_f1, | |
421 | enable_f2 => enable_f2, |
|
423 | enable_f2 => enable_f2, | |
422 | enable_f3 => enable_f3, |
|
424 | enable_f3 => enable_f3, | |
423 | burst_f0 => burst_f0, |
|
425 | burst_f0 => burst_f0, | |
424 | burst_f1 => burst_f1, |
|
426 | burst_f1 => burst_f1, | |
425 | burst_f2 => burst_f2, |
|
427 | burst_f2 => burst_f2, | |
426 |
|
428 | |||
427 | nb_data_by_buffer => nb_data_by_buffer, |
|
429 | nb_data_by_buffer => nb_data_by_buffer, | |
428 | nb_snapshot_param => nb_snapshot_param, |
|
430 | nb_snapshot_param => nb_snapshot_param, | |
429 | status_new_err => status_new_err, |
|
431 | status_new_err => status_new_err, | |
430 |
|
432 | |||
431 | status_buffer_ready => wfp_status_buffer_ready, |
|
433 | status_buffer_ready => wfp_status_buffer_ready, | |
432 | addr_buffer => wfp_addr_buffer, |
|
434 | addr_buffer => wfp_addr_buffer, | |
433 | length_buffer => wfp_length_buffer, |
|
435 | length_buffer => wfp_length_buffer, | |
434 | ready_buffer => wfp_ready_buffer, |
|
436 | ready_buffer => wfp_ready_buffer, | |
435 | buffer_time => wfp_buffer_time, |
|
437 | buffer_time => wfp_buffer_time, | |
436 | error_buffer_full => wfp_error_buffer_full, |
|
438 | error_buffer_full => wfp_error_buffer_full, | |
437 |
|
439 | |||
438 | coarse_time => coarse_time, |
|
440 | coarse_time => coarse_time, | |
439 | fine_time => fine_time, |
|
441 | fine_time => fine_time, | |
440 |
|
442 | |||
441 | --f0 |
|
443 | --f0 | |
442 | data_f0_in_valid => sample_f0_val, |
|
444 | data_f0_in_valid => sample_f0_val, | |
443 | data_f0_in => sample_f0_data, |
|
445 | data_f0_in => sample_f0_data, | |
444 | --f1 |
|
446 | --f1 | |
445 | data_f1_in_valid => sample_f1_val, |
|
447 | data_f1_in_valid => sample_f1_val, | |
446 | data_f1_in => sample_f1_data, |
|
448 | data_f1_in => sample_f1_data, | |
447 | --f2 |
|
449 | --f2 | |
448 | data_f2_in_valid => sample_f2_val, |
|
450 | data_f2_in_valid => sample_f2_val, | |
449 | data_f2_in => sample_f2_data, |
|
451 | data_f2_in => sample_f2_data, | |
450 | --f3 |
|
452 | --f3 | |
451 | data_f3_in_valid => sample_f3_val, |
|
453 | data_f3_in_valid => sample_f3_val, | |
452 | data_f3_in => sample_f3_data, |
|
454 | data_f3_in => sample_f3_data, | |
453 | -- OUTPUT -- DMA interface |
|
455 | -- OUTPUT -- DMA interface | |
454 |
|
456 | |||
455 | dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0), |
|
457 | dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0), | |
456 | dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0), |
|
458 | dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0), | |
457 | dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0), |
|
459 | dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0), | |
458 | dma_buffer_new => dma_buffer_new(3 DOWNTO 0), |
|
460 | dma_buffer_new => dma_buffer_new(3 DOWNTO 0), | |
459 | dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0), |
|
461 | dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0), | |
460 | dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0), |
|
462 | dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0), | |
461 | dma_buffer_full => dma_buffer_full(3 DOWNTO 0), |
|
463 | dma_buffer_full => dma_buffer_full(3 DOWNTO 0), | |
462 | dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0) |
|
464 | dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0) | |
463 |
|
465 | |||
464 | ); |
|
466 | ); | |
465 |
|
467 | |||
466 | ----------------------------------------------------------------------------- |
|
468 | ----------------------------------------------------------------------------- | |
467 | -- Matrix Spectral |
|
469 | -- Matrix Spectral | |
468 | ----------------------------------------------------------------------------- |
|
470 | ----------------------------------------------------------------------------- | |
469 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & |
|
471 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & | |
470 | NOT(sample_f0_val) & NOT(sample_f0_val); |
|
472 | NOT(sample_f0_val) & NOT(sample_f0_val); | |
471 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & |
|
473 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & | |
472 | NOT(sample_f1_val) & NOT(sample_f1_val); |
|
474 | NOT(sample_f1_val) & NOT(sample_f1_val); | |
473 | sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & |
|
475 | sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & | |
474 | NOT(sample_f2_val) & NOT(sample_f2_val); |
|
476 | NOT(sample_f2_val) & NOT(sample_f2_val); | |
475 |
|
477 | |||
476 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) |
|
478 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) | |
477 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); |
|
479 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); | |
478 | sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16)); |
|
480 | sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16)); | |
479 |
|
481 | |||
480 | ------------------------------------------------------------------------------- |
|
482 | ------------------------------------------------------------------------------- | |
481 |
|
483 | |||
482 | ms_softandhard_rstn <= rstn AND run_ms AND run; |
|
484 | ms_softandhard_rstn <= rstn AND run_ms AND run; | |
483 |
|
485 | |||
484 | ----------------------------------------------------------------------------- |
|
486 | ----------------------------------------------------------------------------- | |
485 | lpp_lfr_ms_1 : lpp_lfr_ms |
|
487 | lpp_lfr_ms_1 : lpp_lfr_ms | |
486 | GENERIC MAP ( |
|
488 | GENERIC MAP ( | |
487 | Mem_use => Mem_use) |
|
489 | Mem_use => Mem_use) | |
488 | PORT MAP ( |
|
490 | PORT MAP ( | |
489 | clk => clk, |
|
491 | clk => clk, | |
490 | rstn => ms_softandhard_rstn, --rstn, |
|
492 | --rstn => ms_softandhard_rstn, --rstn, | |
|
493 | rstn => rstn, | |||
|
494 | ||||
491 |
|
|
495 | run => run_ms, | |
492 |
|
496 | |||
493 | coarse_time => coarse_time, |
|
497 | coarse_time => coarse_time, | |
494 | fine_time => fine_time, |
|
498 | fine_time => fine_time, | |
495 |
|
499 | |||
496 | sample_f0_wen => sample_f0_wen, |
|
500 | sample_f0_wen => sample_f0_wen, | |
497 | sample_f0_wdata => sample_f0_wdata, |
|
501 | sample_f0_wdata => sample_f0_wdata, | |
498 | sample_f1_wen => sample_f1_wen, |
|
502 | sample_f1_wen => sample_f1_wen, | |
499 | sample_f1_wdata => sample_f1_wdata, |
|
503 | sample_f1_wdata => sample_f1_wdata, | |
500 | sample_f2_wen => sample_f2_wen, |
|
504 | sample_f2_wen => sample_f2_wen, | |
501 | sample_f2_wdata => sample_f2_wdata, |
|
505 | sample_f2_wdata => sample_f2_wdata, | |
502 |
|
506 | |||
503 | --DMA |
|
507 | --DMA | |
504 | dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT |
|
508 | dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT | |
505 | dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT |
|
509 | dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT | |
506 | dma_fifo_ren => dma_fifo_ren(4), -- IN |
|
510 | dma_fifo_ren => dma_fifo_ren(4), -- IN | |
507 | dma_buffer_new => dma_buffer_new(4), -- OUT |
|
511 | dma_buffer_new => dma_buffer_new(4), -- OUT | |
508 | dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT |
|
512 | dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT | |
509 | dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT |
|
513 | dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT | |
510 | dma_buffer_full => dma_buffer_full(4), -- IN |
|
514 | dma_buffer_full => dma_buffer_full(4), -- IN | |
511 | dma_buffer_full_err => dma_buffer_full_err(4), -- IN |
|
515 | dma_buffer_full_err => dma_buffer_full_err(4), -- IN | |
512 |
|
516 | |||
513 |
|
517 | |||
514 |
|
518 | |||
515 | --REG |
|
519 | --REG | |
516 | ready_matrix_f0 => ready_matrix_f0, |
|
520 | ready_matrix_f0 => ready_matrix_f0, | |
517 | ready_matrix_f1 => ready_matrix_f1, |
|
521 | ready_matrix_f1 => ready_matrix_f1, | |
518 | ready_matrix_f2 => ready_matrix_f2, |
|
522 | ready_matrix_f2 => ready_matrix_f2, | |
519 | error_buffer_full => error_buffer_full, |
|
523 | error_buffer_full => error_buffer_full, | |
520 | error_input_fifo_write => error_input_fifo_write, |
|
524 | error_input_fifo_write => error_input_fifo_write, | |
521 |
|
525 | |||
522 | status_ready_matrix_f0 => status_ready_matrix_f0, |
|
526 | status_ready_matrix_f0 => status_ready_matrix_f0, | |
523 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
527 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
524 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
528 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
525 | addr_matrix_f0 => addr_matrix_f0, |
|
529 | addr_matrix_f0 => addr_matrix_f0, | |
526 | addr_matrix_f1 => addr_matrix_f1, |
|
530 | addr_matrix_f1 => addr_matrix_f1, | |
527 | addr_matrix_f2 => addr_matrix_f2, |
|
531 | addr_matrix_f2 => addr_matrix_f2, | |
528 |
|
532 | |||
529 | length_matrix_f0 => length_matrix_f0, |
|
533 | length_matrix_f0 => length_matrix_f0, | |
530 | length_matrix_f1 => length_matrix_f1, |
|
534 | length_matrix_f1 => length_matrix_f1, | |
531 | length_matrix_f2 => length_matrix_f2, |
|
535 | length_matrix_f2 => length_matrix_f2, | |
532 |
|
536 | |||
533 | matrix_time_f0 => matrix_time_f0, |
|
537 | matrix_time_f0 => matrix_time_f0, | |
534 | matrix_time_f1 => matrix_time_f1, |
|
538 | matrix_time_f1 => matrix_time_f1, | |
535 | matrix_time_f2 => matrix_time_f2); |
|
539 | matrix_time_f2 => matrix_time_f2); | |
536 |
|
540 | |||
537 | ----------------------------------------------------------------------------- |
|
541 | ----------------------------------------------------------------------------- | |
538 |
|
542 | run_dma <= run_ms OR run; | ||
|
543 | ||||
539 |
|
|
544 | DMA_SubSystem_1 : DMA_SubSystem | |
540 | GENERIC MAP ( |
|
545 | GENERIC MAP ( | |
541 | hindex => hindex) |
|
546 | hindex => hindex) | |
542 | PORT MAP ( |
|
547 | PORT MAP ( | |
543 | clk => clk, |
|
548 | clk => clk, | |
544 | rstn => rstn, |
|
549 | rstn => rstn, | |
545 |
run => run_ |
|
550 | run => run_dma, | |
546 | ahbi => ahbi, |
|
551 | ahbi => ahbi, | |
547 | ahbo => ahbo, |
|
552 | ahbo => ahbo, | |
548 |
|
553 | |||
549 | fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid, |
|
554 | fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid, | |
550 | fifo_data => dma_fifo_data, --fifo_data, |
|
555 | fifo_data => dma_fifo_data, --fifo_data, | |
551 | fifo_ren => dma_fifo_ren, --fifo_ren, |
|
556 | fifo_ren => dma_fifo_ren, --fifo_ren, | |
552 |
|
557 | |||
553 | buffer_new => dma_buffer_new, --buffer_new, |
|
558 | buffer_new => dma_buffer_new, --buffer_new, | |
554 | buffer_addr => dma_buffer_addr, --buffer_addr, |
|
559 | buffer_addr => dma_buffer_addr, --buffer_addr, | |
555 | buffer_length => dma_buffer_length, --buffer_length, |
|
560 | buffer_length => dma_buffer_length, --buffer_length, | |
556 | buffer_full => dma_buffer_full, --buffer_full, |
|
561 | buffer_full => dma_buffer_full, --buffer_full, | |
557 | buffer_full_err => dma_buffer_full_err, --buffer_full_err, |
|
562 | buffer_full_err => dma_buffer_full_err, --buffer_full_err, | |
558 | grant_error => dma_grant_error); --grant_error); |
|
563 | grant_error => dma_grant_error); --grant_error); | |
559 |
|
564 | |||
560 | END beh; |
|
565 | END beh; |
@@ -1,770 +1,776 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | -- jean-christophe.pellion@easii-ic.com |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
22 | ---------------------------------------------------------------------------- |
|
22 | ---------------------------------------------------------------------------- | |
23 | LIBRARY ieee; |
|
23 | LIBRARY ieee; | |
24 | USE ieee.std_logic_1164.ALL; |
|
24 | USE ieee.std_logic_1164.ALL; | |
25 | USE ieee.numeric_std.ALL; |
|
25 | USE ieee.numeric_std.ALL; | |
26 | LIBRARY grlib; |
|
26 | LIBRARY grlib; | |
27 | USE grlib.amba.ALL; |
|
27 | USE grlib.amba.ALL; | |
28 | USE grlib.stdlib.ALL; |
|
28 | USE grlib.stdlib.ALL; | |
29 | USE grlib.devices.ALL; |
|
29 | USE grlib.devices.ALL; | |
30 | LIBRARY lpp; |
|
30 | LIBRARY lpp; | |
31 | USE lpp.lpp_lfr_pkg.ALL; |
|
31 | USE lpp.lpp_lfr_pkg.ALL; | |
32 | --USE lpp.lpp_amba.ALL; |
|
32 | --USE lpp.lpp_amba.ALL; | |
33 | USE lpp.apb_devices_list.ALL; |
|
33 | USE lpp.apb_devices_list.ALL; | |
34 | USE lpp.lpp_memory.ALL; |
|
34 | USE lpp.lpp_memory.ALL; | |
35 | LIBRARY techmap; |
|
35 | LIBRARY techmap; | |
36 | USE techmap.gencomp.ALL; |
|
36 | USE techmap.gencomp.ALL; | |
37 |
|
37 | |||
38 | ENTITY lpp_lfr_apbreg IS |
|
38 | ENTITY lpp_lfr_apbreg IS | |
39 | GENERIC ( |
|
39 | GENERIC ( | |
40 | nb_data_by_buffer_size : INTEGER := 11; |
|
40 | nb_data_by_buffer_size : INTEGER := 11; | |
41 | -- nb_word_by_buffer_size : INTEGER := 11; |
|
41 | -- nb_word_by_buffer_size : INTEGER := 11; | |
42 | nb_snapshot_param_size : INTEGER := 11; |
|
42 | nb_snapshot_param_size : INTEGER := 11; | |
43 | delta_vector_size : INTEGER := 20; |
|
43 | delta_vector_size : INTEGER := 20; | |
44 | delta_vector_size_f0_2 : INTEGER := 3; |
|
44 | delta_vector_size_f0_2 : INTEGER := 3; | |
45 |
|
45 | |||
46 | pindex : INTEGER := 4; |
|
46 | pindex : INTEGER := 4; | |
47 | paddr : INTEGER := 4; |
|
47 | paddr : INTEGER := 4; | |
48 | pmask : INTEGER := 16#fff#; |
|
48 | pmask : INTEGER := 16#fff#; | |
49 | pirq_ms : INTEGER := 0; |
|
49 | pirq_ms : INTEGER := 0; | |
50 | pirq_wfp : INTEGER := 1; |
|
50 | pirq_wfp : INTEGER := 1; | |
51 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000"); |
|
51 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000"); | |
52 | PORT ( |
|
52 | PORT ( | |
53 | -- AMBA AHB system signals |
|
53 | -- AMBA AHB system signals | |
54 | HCLK : IN STD_ULOGIC; |
|
54 | HCLK : IN STD_ULOGIC; | |
55 | HRESETn : IN STD_ULOGIC; |
|
55 | HRESETn : IN STD_ULOGIC; | |
56 |
|
56 | |||
57 | -- AMBA APB Slave Interface |
|
57 | -- AMBA APB Slave Interface | |
58 | apbi : IN apb_slv_in_type; |
|
58 | apbi : IN apb_slv_in_type; | |
59 | apbo : OUT apb_slv_out_type; |
|
59 | apbo : OUT apb_slv_out_type; | |
60 |
|
60 | |||
61 | --------------------------------------------------------------------------- |
|
61 | --------------------------------------------------------------------------- | |
62 | -- Spectral Matrix Reg |
|
62 | -- Spectral Matrix Reg | |
63 | run_ms : OUT STD_LOGIC; |
|
63 | run_ms : OUT STD_LOGIC; | |
64 | -- IN |
|
64 | -- IN | |
65 | ready_matrix_f0 : IN STD_LOGIC; |
|
65 | ready_matrix_f0 : IN STD_LOGIC; | |
66 | ready_matrix_f1 : IN STD_LOGIC; |
|
66 | ready_matrix_f1 : IN STD_LOGIC; | |
67 | ready_matrix_f2 : IN STD_LOGIC; |
|
67 | ready_matrix_f2 : IN STD_LOGIC; | |
68 |
|
68 | |||
69 | -- error_bad_component_error : IN STD_LOGIC; |
|
69 | -- error_bad_component_error : IN STD_LOGIC; | |
70 | error_buffer_full : IN STD_LOGIC; -- TODO |
|
70 | error_buffer_full : IN STD_LOGIC; -- TODO | |
71 | error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO |
|
71 | error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO | |
72 |
|
72 | |||
73 | -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
73 | -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
74 |
|
74 | |||
75 | -- OUT |
|
75 | -- OUT | |
76 | status_ready_matrix_f0 : OUT STD_LOGIC; |
|
76 | status_ready_matrix_f0 : OUT STD_LOGIC; | |
77 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
77 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
78 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
78 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
79 |
|
79 | |||
80 | --config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
80 | --config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
81 | --config_active_interruption_onError : OUT STD_LOGIC; |
|
81 | --config_active_interruption_onError : OUT STD_LOGIC; | |
82 |
|
82 | |||
83 | addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
83 | addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
84 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
84 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
85 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
85 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
86 |
|
86 | |||
87 | length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
87 | length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
88 | length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
88 | length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
89 | length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
89 | length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
90 |
|
90 | |||
91 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
91 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
92 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
92 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
93 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
93 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
94 |
|
94 | |||
95 | --------------------------------------------------------------------------- |
|
95 | --------------------------------------------------------------------------- | |
96 | --------------------------------------------------------------------------- |
|
96 | --------------------------------------------------------------------------- | |
97 | -- WaveForm picker Reg |
|
97 | -- WaveForm picker Reg | |
98 | --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
98 | --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
99 | --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
99 | --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
100 | --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
100 | --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
101 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
101 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
102 |
|
102 | |||
103 | -- OUT |
|
103 | -- OUT | |
104 | data_shaping_BW : OUT STD_LOGIC; |
|
104 | data_shaping_BW : OUT STD_LOGIC; | |
105 | data_shaping_SP0 : OUT STD_LOGIC; |
|
105 | data_shaping_SP0 : OUT STD_LOGIC; | |
106 | data_shaping_SP1 : OUT STD_LOGIC; |
|
106 | data_shaping_SP1 : OUT STD_LOGIC; | |
107 | data_shaping_R0 : OUT STD_LOGIC; |
|
107 | data_shaping_R0 : OUT STD_LOGIC; | |
108 | data_shaping_R1 : OUT STD_LOGIC; |
|
108 | data_shaping_R1 : OUT STD_LOGIC; | |
109 | data_shaping_R2 : OUT STD_LOGIC; |
|
109 | data_shaping_R2 : OUT STD_LOGIC; | |
110 |
|
110 | |||
111 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
111 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
112 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
112 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
113 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
113 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
114 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
114 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
115 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
115 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
116 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
116 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
117 | --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
117 | --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
118 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
118 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
119 |
|
119 | |||
120 | enable_f0 : OUT STD_LOGIC; |
|
120 | enable_f0 : OUT STD_LOGIC; | |
121 | enable_f1 : OUT STD_LOGIC; |
|
121 | enable_f1 : OUT STD_LOGIC; | |
122 | enable_f2 : OUT STD_LOGIC; |
|
122 | enable_f2 : OUT STD_LOGIC; | |
123 | enable_f3 : OUT STD_LOGIC; |
|
123 | enable_f3 : OUT STD_LOGIC; | |
124 |
|
124 | |||
125 | burst_f0 : OUT STD_LOGIC; |
|
125 | burst_f0 : OUT STD_LOGIC; | |
126 | burst_f1 : OUT STD_LOGIC; |
|
126 | burst_f1 : OUT STD_LOGIC; | |
127 | burst_f2 : OUT STD_LOGIC; |
|
127 | burst_f2 : OUT STD_LOGIC; | |
128 |
|
128 | |||
129 | run : OUT STD_LOGIC; |
|
129 | run : OUT STD_LOGIC; | |
130 |
|
130 | |||
131 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
131 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); | |
132 |
|
132 | |||
133 | wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
133 | wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
134 | wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0); |
|
134 | wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0); | |
135 | wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
135 | wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
136 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
136 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
137 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
|
137 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |
138 | wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0) |
|
138 | wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0) | |
139 |
|
139 | |||
140 | ); |
|
140 | ); | |
141 |
|
141 | |||
142 | END lpp_lfr_apbreg; |
|
142 | END lpp_lfr_apbreg; | |
143 |
|
143 | |||
144 | ARCHITECTURE beh OF lpp_lfr_apbreg IS |
|
144 | ARCHITECTURE beh OF lpp_lfr_apbreg IS | |
145 |
|
145 | |||
146 | CONSTANT REVISION : INTEGER := 1; |
|
146 | CONSTANT REVISION : INTEGER := 1; | |
147 |
|
147 | |||
148 | CONSTANT pconfig : apb_config_type := ( |
|
148 | CONSTANT pconfig : apb_config_type := ( | |
149 | 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp), |
|
149 | 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp), | |
150 | 1 => apb_iobar(paddr, pmask)); |
|
150 | 1 => apb_iobar(paddr, pmask)); | |
151 |
|
151 | |||
152 | TYPE lpp_SpectralMatrix_regs IS RECORD |
|
152 | TYPE lpp_SpectralMatrix_regs IS RECORD | |
153 | config_active_interruption_onNewMatrix : STD_LOGIC; |
|
153 | config_active_interruption_onNewMatrix : STD_LOGIC; | |
154 | config_active_interruption_onError : STD_LOGIC; |
|
154 | config_active_interruption_onError : STD_LOGIC; | |
155 | config_ms_run : STD_LOGIC; |
|
155 | config_ms_run : STD_LOGIC; | |
156 | status_ready_matrix_f0_0 : STD_LOGIC; |
|
156 | status_ready_matrix_f0_0 : STD_LOGIC; | |
157 | status_ready_matrix_f1_0 : STD_LOGIC; |
|
157 | status_ready_matrix_f1_0 : STD_LOGIC; | |
158 | status_ready_matrix_f2_0 : STD_LOGIC; |
|
158 | status_ready_matrix_f2_0 : STD_LOGIC; | |
159 | status_ready_matrix_f0_1 : STD_LOGIC; |
|
159 | status_ready_matrix_f0_1 : STD_LOGIC; | |
160 | status_ready_matrix_f1_1 : STD_LOGIC; |
|
160 | status_ready_matrix_f1_1 : STD_LOGIC; | |
161 | status_ready_matrix_f2_1 : STD_LOGIC; |
|
161 | status_ready_matrix_f2_1 : STD_LOGIC; | |
162 | -- status_error_bad_component_error : STD_LOGIC; |
|
162 | -- status_error_bad_component_error : STD_LOGIC; | |
163 | status_error_buffer_full : STD_LOGIC; |
|
163 | status_error_buffer_full : STD_LOGIC; | |
164 | status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
164 | status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); | |
165 |
|
165 | |||
166 | addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
166 | addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
167 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
167 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
168 | addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
168 | addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
169 | addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
169 | addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
170 | addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
170 | addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
171 | addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
171 | addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
172 |
|
172 | |||
173 | length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
173 | length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0); | |
174 |
|
174 | |||
175 | time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
175 | time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
176 | time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
176 | time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
177 | time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
177 | time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
178 | time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
178 | time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
179 | time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
179 | time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
180 | time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
180 | time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
181 | END RECORD; |
|
181 | END RECORD; | |
182 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; |
|
182 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; | |
183 |
|
183 | |||
184 | TYPE lpp_WaveformPicker_regs IS RECORD |
|
184 | TYPE lpp_WaveformPicker_regs IS RECORD | |
185 | -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
185 | -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
186 | -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
186 | -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
187 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
187 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
188 | data_shaping_BW : STD_LOGIC; |
|
188 | data_shaping_BW : STD_LOGIC; | |
189 | data_shaping_SP0 : STD_LOGIC; |
|
189 | data_shaping_SP0 : STD_LOGIC; | |
190 | data_shaping_SP1 : STD_LOGIC; |
|
190 | data_shaping_SP1 : STD_LOGIC; | |
191 | data_shaping_R0 : STD_LOGIC; |
|
191 | data_shaping_R0 : STD_LOGIC; | |
192 | data_shaping_R1 : STD_LOGIC; |
|
192 | data_shaping_R1 : STD_LOGIC; | |
193 | data_shaping_R2 : STD_LOGIC; |
|
193 | data_shaping_R2 : STD_LOGIC; | |
194 | delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
194 | delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
195 | delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
195 | delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
196 | delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
196 | delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
197 | delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
197 | delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
198 | delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
198 | delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
199 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
199 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
200 | -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
200 | -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
201 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
201 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
202 | enable_f0 : STD_LOGIC; |
|
202 | enable_f0 : STD_LOGIC; | |
203 | enable_f1 : STD_LOGIC; |
|
203 | enable_f1 : STD_LOGIC; | |
204 | enable_f2 : STD_LOGIC; |
|
204 | enable_f2 : STD_LOGIC; | |
205 | enable_f3 : STD_LOGIC; |
|
205 | enable_f3 : STD_LOGIC; | |
206 | burst_f0 : STD_LOGIC; |
|
206 | burst_f0 : STD_LOGIC; | |
207 | burst_f1 : STD_LOGIC; |
|
207 | burst_f1 : STD_LOGIC; | |
208 | burst_f2 : STD_LOGIC; |
|
208 | burst_f2 : STD_LOGIC; | |
209 | run : STD_LOGIC; |
|
209 | run : STD_LOGIC; | |
210 | status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0); |
|
210 | status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0); | |
211 | addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0); |
|
211 | addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0); | |
212 | time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0); |
|
212 | time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0); | |
213 | length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
213 | length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0); | |
214 | error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
214 | error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
215 | start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
215 | start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
216 | END RECORD; |
|
216 | END RECORD; | |
217 | SIGNAL reg_wp : lpp_WaveformPicker_regs; |
|
217 | SIGNAL reg_wp : lpp_WaveformPicker_regs; | |
218 |
|
218 | |||
219 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
219 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
220 |
|
220 | |||
221 | ----------------------------------------------------------------------------- |
|
221 | ----------------------------------------------------------------------------- | |
222 | -- IRQ |
|
222 | -- IRQ | |
223 | ----------------------------------------------------------------------------- |
|
223 | ----------------------------------------------------------------------------- | |
224 | CONSTANT IRQ_WFP_SIZE : INTEGER := 12; |
|
224 | CONSTANT IRQ_WFP_SIZE : INTEGER := 12; | |
225 | SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
225 | SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
226 | SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
226 | SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
227 | SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
227 | SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
228 | SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
228 | SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
229 | SIGNAL ored_irq_wfp : STD_LOGIC; |
|
229 | SIGNAL ored_irq_wfp : STD_LOGIC; | |
230 |
|
230 | |||
231 | ----------------------------------------------------------------------------- |
|
231 | ----------------------------------------------------------------------------- | |
232 | -- |
|
232 | -- | |
233 | ----------------------------------------------------------------------------- |
|
233 | ----------------------------------------------------------------------------- | |
234 | SIGNAL reg0_ready_matrix_f0 : STD_LOGIC; |
|
234 | SIGNAL reg0_ready_matrix_f0 : STD_LOGIC; | |
235 | SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
235 | SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
236 | SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
236 | SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
237 |
|
237 | |||
238 | SIGNAL reg1_ready_matrix_f0 : STD_LOGIC; |
|
238 | SIGNAL reg1_ready_matrix_f0 : STD_LOGIC; | |
239 | SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
239 | SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
240 | SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
240 | SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
241 |
|
241 | |||
242 | SIGNAL reg0_ready_matrix_f1 : STD_LOGIC; |
|
242 | SIGNAL reg0_ready_matrix_f1 : STD_LOGIC; | |
243 | SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
243 | SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
244 | SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
244 | SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
245 |
|
245 | |||
246 | SIGNAL reg1_ready_matrix_f1 : STD_LOGIC; |
|
246 | SIGNAL reg1_ready_matrix_f1 : STD_LOGIC; | |
247 | SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
247 | SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
248 | SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
248 | SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
249 |
|
249 | |||
250 | SIGNAL reg0_ready_matrix_f2 : STD_LOGIC; |
|
250 | SIGNAL reg0_ready_matrix_f2 : STD_LOGIC; | |
251 | SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
251 | SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
252 | SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
252 | SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
253 |
|
253 | |||
254 | SIGNAL reg1_ready_matrix_f2 : STD_LOGIC; |
|
254 | SIGNAL reg1_ready_matrix_f2 : STD_LOGIC; | |
255 | SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
255 | SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
256 | SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
256 | SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
257 | SIGNAL apbo_irq_ms : STD_LOGIC; |
|
257 | SIGNAL apbo_irq_ms : STD_LOGIC; | |
258 | SIGNAL apbo_irq_wfp : STD_LOGIC; |
|
258 | SIGNAL apbo_irq_wfp : STD_LOGIC; | |
259 | ----------------------------------------------------------------------------- |
|
259 | ----------------------------------------------------------------------------- | |
260 | SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0); |
|
260 | SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0); | |
261 |
|
261 | |||
262 | BEGIN -- beh |
|
262 | BEGIN -- beh | |
263 |
|
263 | |||
264 | -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0; |
|
264 | -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0; | |
265 | -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; |
|
265 | -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; | |
266 | -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; |
|
266 | -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; | |
267 |
|
267 | |||
268 | -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; |
|
268 | -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; | |
269 | -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError; |
|
269 | -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError; | |
270 |
|
270 | |||
271 |
|
271 | |||
272 | -- addr_matrix_f0 <= reg_sp.addr_matrix_f0; |
|
272 | -- addr_matrix_f0 <= reg_sp.addr_matrix_f0; | |
273 | -- addr_matrix_f1 <= reg_sp.addr_matrix_f1; |
|
273 | -- addr_matrix_f1 <= reg_sp.addr_matrix_f1; | |
274 | -- addr_matrix_f2 <= reg_sp.addr_matrix_f2; |
|
274 | -- addr_matrix_f2 <= reg_sp.addr_matrix_f2; | |
275 |
|
275 | |||
276 |
|
276 | |||
277 | data_shaping_BW <= NOT reg_wp.data_shaping_BW; |
|
277 | data_shaping_BW <= NOT reg_wp.data_shaping_BW; | |
278 | data_shaping_SP0 <= reg_wp.data_shaping_SP0; |
|
278 | data_shaping_SP0 <= reg_wp.data_shaping_SP0; | |
279 | data_shaping_SP1 <= reg_wp.data_shaping_SP1; |
|
279 | data_shaping_SP1 <= reg_wp.data_shaping_SP1; | |
280 | data_shaping_R0 <= reg_wp.data_shaping_R0; |
|
280 | data_shaping_R0 <= reg_wp.data_shaping_R0; | |
281 | data_shaping_R1 <= reg_wp.data_shaping_R1; |
|
281 | data_shaping_R1 <= reg_wp.data_shaping_R1; | |
282 | data_shaping_R2 <= reg_wp.data_shaping_R2; |
|
282 | data_shaping_R2 <= reg_wp.data_shaping_R2; | |
283 |
|
283 | |||
284 | delta_snapshot <= reg_wp.delta_snapshot; |
|
284 | delta_snapshot <= reg_wp.delta_snapshot; | |
285 | delta_f0 <= reg_wp.delta_f0; |
|
285 | delta_f0 <= reg_wp.delta_f0; | |
286 | delta_f0_2 <= reg_wp.delta_f0_2; |
|
286 | delta_f0_2 <= reg_wp.delta_f0_2; | |
287 | delta_f1 <= reg_wp.delta_f1; |
|
287 | delta_f1 <= reg_wp.delta_f1; | |
288 | delta_f2 <= reg_wp.delta_f2; |
|
288 | delta_f2 <= reg_wp.delta_f2; | |
289 | nb_data_by_buffer <= reg_wp.nb_data_by_buffer; |
|
289 | nb_data_by_buffer <= reg_wp.nb_data_by_buffer; | |
290 | nb_snapshot_param <= reg_wp.nb_snapshot_param; |
|
290 | nb_snapshot_param <= reg_wp.nb_snapshot_param; | |
291 |
|
291 | |||
292 | enable_f0 <= reg_wp.enable_f0; |
|
292 | enable_f0 <= reg_wp.enable_f0; | |
293 | enable_f1 <= reg_wp.enable_f1; |
|
293 | enable_f1 <= reg_wp.enable_f1; | |
294 | enable_f2 <= reg_wp.enable_f2; |
|
294 | enable_f2 <= reg_wp.enable_f2; | |
295 | enable_f3 <= reg_wp.enable_f3; |
|
295 | enable_f3 <= reg_wp.enable_f3; | |
296 |
|
296 | |||
297 | burst_f0 <= reg_wp.burst_f0; |
|
297 | burst_f0 <= reg_wp.burst_f0; | |
298 | burst_f1 <= reg_wp.burst_f1; |
|
298 | burst_f1 <= reg_wp.burst_f1; | |
299 | burst_f2 <= reg_wp.burst_f2; |
|
299 | burst_f2 <= reg_wp.burst_f2; | |
300 |
|
300 | |||
301 | run <= reg_wp.run; |
|
301 | run <= reg_wp.run; | |
302 |
|
302 | |||
303 | --addr_data_f0 <= reg_wp.addr_data_f0; |
|
303 | --addr_data_f0 <= reg_wp.addr_data_f0; | |
304 | --addr_data_f1 <= reg_wp.addr_data_f1; |
|
304 | --addr_data_f1 <= reg_wp.addr_data_f1; | |
305 | --addr_data_f2 <= reg_wp.addr_data_f2; |
|
305 | --addr_data_f2 <= reg_wp.addr_data_f2; | |
306 | --addr_data_f3 <= reg_wp.addr_data_f3; |
|
306 | --addr_data_f3 <= reg_wp.addr_data_f3; | |
307 |
|
307 | |||
308 | start_date <= reg_wp.start_date; |
|
308 | start_date <= reg_wp.start_date; | |
309 |
|
309 | |||
310 |
|
|
310 | length_matrix_f0 <= reg_sp.length_matrix; | |
311 |
|
|
311 | length_matrix_f1 <= reg_sp.length_matrix; | |
312 |
|
|
312 | length_matrix_f2 <= reg_sp.length_matrix; | |
|
313 | wfp_length_buffer <= reg_wp.length_buffer; | |||
313 |
|
314 | |||
314 |
|
315 | |||
315 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) |
|
316 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) | |
316 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); |
|
317 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); | |
317 | BEGIN -- PROCESS lpp_dma_top |
|
318 | BEGIN -- PROCESS lpp_dma_top | |
318 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
319 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
319 | reg_sp.config_active_interruption_onNewMatrix <= '0'; |
|
320 | reg_sp.config_active_interruption_onNewMatrix <= '0'; | |
320 | reg_sp.config_active_interruption_onError <= '0'; |
|
321 | reg_sp.config_active_interruption_onError <= '0'; | |
321 |
reg_sp.config_ms_run <= ' |
|
322 | reg_sp.config_ms_run <= '0'; | |
322 | reg_sp.status_ready_matrix_f0_0 <= '0'; |
|
323 | reg_sp.status_ready_matrix_f0_0 <= '0'; | |
323 | reg_sp.status_ready_matrix_f1_0 <= '0'; |
|
324 | reg_sp.status_ready_matrix_f1_0 <= '0'; | |
324 | reg_sp.status_ready_matrix_f2_0 <= '0'; |
|
325 | reg_sp.status_ready_matrix_f2_0 <= '0'; | |
325 | reg_sp.status_ready_matrix_f0_1 <= '0'; |
|
326 | reg_sp.status_ready_matrix_f0_1 <= '0'; | |
326 | reg_sp.status_ready_matrix_f1_1 <= '0'; |
|
327 | reg_sp.status_ready_matrix_f1_1 <= '0'; | |
327 | reg_sp.status_ready_matrix_f2_1 <= '0'; |
|
328 | reg_sp.status_ready_matrix_f2_1 <= '0'; | |
328 | reg_sp.status_error_buffer_full <= '0'; |
|
329 | reg_sp.status_error_buffer_full <= '0'; | |
329 | reg_sp.status_error_input_fifo_write <= (OTHERS => '0'); |
|
330 | reg_sp.status_error_input_fifo_write <= (OTHERS => '0'); | |
330 |
|
331 | |||
331 | reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); |
|
332 | reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); | |
332 | reg_sp.addr_matrix_f1_0 <= (OTHERS => '0'); |
|
333 | reg_sp.addr_matrix_f1_0 <= (OTHERS => '0'); | |
333 | reg_sp.addr_matrix_f2_0 <= (OTHERS => '0'); |
|
334 | reg_sp.addr_matrix_f2_0 <= (OTHERS => '0'); | |
334 |
|
335 | |||
335 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); |
|
336 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); | |
336 | reg_sp.addr_matrix_f1_1 <= (OTHERS => '0'); |
|
337 | reg_sp.addr_matrix_f1_1 <= (OTHERS => '0'); | |
337 | reg_sp.addr_matrix_f2_1 <= (OTHERS => '0'); |
|
338 | reg_sp.addr_matrix_f2_1 <= (OTHERS => '0'); | |
338 |
|
339 | |||
339 | reg_sp.length_matrix <= (OTHERS => '0'); |
|
340 | reg_sp.length_matrix <= (OTHERS => '0'); | |
340 |
|
341 | |||
341 | -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok |
|
342 | -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok | |
342 | -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok |
|
343 | -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok | |
343 | -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok |
|
344 | -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok | |
344 |
|
345 | |||
345 | -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok |
|
346 | -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok | |
346 | --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok |
|
347 | --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok | |
347 | -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok |
|
348 | -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok | |
348 |
|
349 | |||
349 | prdata <= (OTHERS => '0'); |
|
350 | prdata <= (OTHERS => '0'); | |
350 |
|
351 | |||
351 |
|
352 | |||
352 | apbo_irq_ms <= '0'; |
|
353 | apbo_irq_ms <= '0'; | |
353 | apbo_irq_wfp <= '0'; |
|
354 | apbo_irq_wfp <= '0'; | |
354 |
|
355 | |||
355 |
|
356 | |||
356 | -- status_full_ack <= (OTHERS => '0'); |
|
357 | -- status_full_ack <= (OTHERS => '0'); | |
357 |
|
358 | |||
358 | reg_wp.data_shaping_BW <= '0'; |
|
359 | reg_wp.data_shaping_BW <= '0'; | |
359 | reg_wp.data_shaping_SP0 <= '0'; |
|
360 | reg_wp.data_shaping_SP0 <= '0'; | |
360 | reg_wp.data_shaping_SP1 <= '0'; |
|
361 | reg_wp.data_shaping_SP1 <= '0'; | |
361 | reg_wp.data_shaping_R0 <= '0'; |
|
362 | reg_wp.data_shaping_R0 <= '0'; | |
362 | reg_wp.data_shaping_R1 <= '0'; |
|
363 | reg_wp.data_shaping_R1 <= '0'; | |
363 | reg_wp.data_shaping_R2 <= '0'; |
|
364 | reg_wp.data_shaping_R2 <= '0'; | |
364 | reg_wp.enable_f0 <= '0'; |
|
365 | reg_wp.enable_f0 <= '0'; | |
365 | reg_wp.enable_f1 <= '0'; |
|
366 | reg_wp.enable_f1 <= '0'; | |
366 | reg_wp.enable_f2 <= '0'; |
|
367 | reg_wp.enable_f2 <= '0'; | |
367 | reg_wp.enable_f3 <= '0'; |
|
368 | reg_wp.enable_f3 <= '0'; | |
368 | reg_wp.burst_f0 <= '0'; |
|
369 | reg_wp.burst_f0 <= '0'; | |
369 | reg_wp.burst_f1 <= '0'; |
|
370 | reg_wp.burst_f1 <= '0'; | |
370 | reg_wp.burst_f2 <= '0'; |
|
371 | reg_wp.burst_f2 <= '0'; | |
371 | reg_wp.run <= '0'; |
|
372 | reg_wp.run <= '0'; | |
372 | -- reg_wp.status_full <= (OTHERS => '0'); |
|
373 | -- reg_wp.status_full <= (OTHERS => '0'); | |
373 | -- reg_wp.status_full_err <= (OTHERS => '0'); |
|
374 | -- reg_wp.status_full_err <= (OTHERS => '0'); | |
374 | reg_wp.status_new_err <= (OTHERS => '0'); |
|
375 | reg_wp.status_new_err <= (OTHERS => '0'); | |
375 | reg_wp.error_buffer_full <= (OTHERS => '0'); |
|
376 | reg_wp.error_buffer_full <= (OTHERS => '0'); | |
376 | reg_wp.delta_snapshot <= (OTHERS => '0'); |
|
377 | reg_wp.delta_snapshot <= (OTHERS => '0'); | |
377 | reg_wp.delta_f0 <= (OTHERS => '0'); |
|
378 | reg_wp.delta_f0 <= (OTHERS => '0'); | |
378 | reg_wp.delta_f0_2 <= (OTHERS => '0'); |
|
379 | reg_wp.delta_f0_2 <= (OTHERS => '0'); | |
379 | reg_wp.delta_f1 <= (OTHERS => '0'); |
|
380 | reg_wp.delta_f1 <= (OTHERS => '0'); | |
380 | reg_wp.delta_f2 <= (OTHERS => '0'); |
|
381 | reg_wp.delta_f2 <= (OTHERS => '0'); | |
381 | reg_wp.nb_data_by_buffer <= (OTHERS => '0'); |
|
382 | reg_wp.nb_data_by_buffer <= (OTHERS => '0'); | |
382 | reg_wp.nb_snapshot_param <= (OTHERS => '0'); |
|
383 | reg_wp.nb_snapshot_param <= (OTHERS => '0'); | |
383 | reg_wp.start_date <= (OTHERS => '0'); |
|
384 | reg_wp.start_date <= (OTHERS => '0'); | |
384 |
|
385 | |||
|
386 | reg_wp.status_ready_buffer_f <= (OTHERS => '0'); | |||
|
387 | reg_wp.length_buffer <= (OTHERS => '0'); | |||
385 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
388 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
386 |
|
389 | |||
387 | -- status_full_ack <= (OTHERS => '0'); |
|
390 | -- status_full_ack <= (OTHERS => '0'); | |
388 |
|
391 | |||
389 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0; |
|
392 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0; | |
390 | reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1; |
|
393 | reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1; | |
391 | reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2; |
|
394 | reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2; | |
392 |
|
395 | |||
393 | reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0; |
|
396 | reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0; | |
394 | reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1; |
|
397 | reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1; | |
395 | reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2; |
|
398 | reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2; | |
396 |
|
399 | |||
397 | all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP |
|
400 | all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP | |
398 | reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I); |
|
401 | reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I); | |
399 | END LOOP all_status_ready_buffer_bit; |
|
402 | END LOOP all_status_ready_buffer_bit; | |
400 |
|
403 | |||
401 |
|
404 | |||
402 | reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full; |
|
405 | reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full; | |
403 | reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0); |
|
406 | reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0); | |
404 | reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1); |
|
407 | reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1); | |
405 | reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2); |
|
408 | reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2); | |
406 |
|
409 | |||
407 |
|
410 | |||
408 |
|
411 | |||
409 | all_status : FOR I IN 3 DOWNTO 0 LOOP |
|
412 | all_status : FOR I IN 3 DOWNTO 0 LOOP | |
410 | reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I); |
|
413 | reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I); | |
411 | reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I); |
|
414 | reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I); | |
412 | END LOOP all_status; |
|
415 | END LOOP all_status; | |
413 |
|
416 | |||
414 | paddr := "000000"; |
|
417 | paddr := "000000"; | |
415 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); |
|
418 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); | |
416 | prdata <= (OTHERS => '0'); |
|
419 | prdata <= (OTHERS => '0'); | |
417 | IF apbi.psel(pindex) = '1' THEN |
|
420 | IF apbi.psel(pindex) = '1' THEN | |
418 | -- APB DMA READ -- |
|
421 | -- APB DMA READ -- | |
419 | CASE paddr(7 DOWNTO 2) IS |
|
422 | CASE paddr(7 DOWNTO 2) IS | |
420 | --0 |
|
423 | --0 | |
421 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; |
|
424 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; | |
422 | prdata(1) <= reg_sp.config_active_interruption_onError; |
|
425 | prdata(1) <= reg_sp.config_active_interruption_onError; | |
423 | prdata(2) <= reg_sp.config_ms_run; |
|
426 | prdata(2) <= reg_sp.config_ms_run; | |
424 | --1 |
|
427 | --1 | |
425 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; |
|
428 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; | |
426 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; |
|
429 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; | |
427 | prdata(2) <= reg_sp.status_ready_matrix_f1_0; |
|
430 | prdata(2) <= reg_sp.status_ready_matrix_f1_0; | |
428 | prdata(3) <= reg_sp.status_ready_matrix_f1_1; |
|
431 | prdata(3) <= reg_sp.status_ready_matrix_f1_1; | |
429 | prdata(4) <= reg_sp.status_ready_matrix_f2_0; |
|
432 | prdata(4) <= reg_sp.status_ready_matrix_f2_0; | |
430 | prdata(5) <= reg_sp.status_ready_matrix_f2_1; |
|
433 | prdata(5) <= reg_sp.status_ready_matrix_f2_1; | |
431 | -- prdata(6) <= reg_sp.status_error_bad_component_error; |
|
434 | -- prdata(6) <= reg_sp.status_error_bad_component_error; | |
432 | prdata(7) <= reg_sp.status_error_buffer_full; |
|
435 | prdata(7) <= reg_sp.status_error_buffer_full; | |
433 | prdata(8) <= reg_sp.status_error_input_fifo_write(0); |
|
436 | prdata(8) <= reg_sp.status_error_input_fifo_write(0); | |
434 | prdata(9) <= reg_sp.status_error_input_fifo_write(1); |
|
437 | prdata(9) <= reg_sp.status_error_input_fifo_write(1); | |
435 | prdata(10) <= reg_sp.status_error_input_fifo_write(2); |
|
438 | prdata(10) <= reg_sp.status_error_input_fifo_write(2); | |
436 | --2 |
|
439 | --2 | |
437 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; |
|
440 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; | |
438 | --3 |
|
441 | --3 | |
439 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; |
|
442 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; | |
440 | --4 |
|
443 | --4 | |
441 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0; |
|
444 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0; | |
442 | --5 |
|
445 | --5 | |
443 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1; |
|
446 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1; | |
444 | --6 |
|
447 | --6 | |
445 | WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0; |
|
448 | WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0; | |
446 | --7 |
|
449 | --7 | |
447 | WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1; |
|
450 | WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1; | |
448 | --8 |
|
451 | --8 | |
449 | WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16); |
|
452 | WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16); | |
450 | --9 |
|
453 | --9 | |
451 | WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0); |
|
454 | WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0); | |
452 | --10 |
|
455 | --10 | |
453 | WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16); |
|
456 | WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16); | |
454 | --11 |
|
457 | --11 | |
455 | WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0); |
|
458 | WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0); | |
456 | --12 |
|
459 | --12 | |
457 | WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16); |
|
460 | WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16); | |
458 | --13 |
|
461 | --13 | |
459 | WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0); |
|
462 | WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0); | |
460 | --14 |
|
463 | --14 | |
461 | WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16); |
|
464 | WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16); | |
462 | --15 |
|
465 | --15 | |
463 | WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0); |
|
466 | WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0); | |
464 | --16 |
|
467 | --16 | |
465 | WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16); |
|
468 | WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16); | |
466 | --17 |
|
469 | --17 | |
467 | WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0); |
|
470 | WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0); | |
468 | --18 |
|
471 | --18 | |
469 | WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16); |
|
472 | WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16); | |
470 | --19 |
|
473 | --19 | |
471 | WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0); |
|
474 | WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0); | |
472 | --20 |
|
475 | --20 | |
473 | WHEN "010100" => prdata(25 DOWNTO 0) <= reg_sp.length_matrix; |
|
476 | WHEN "010100" => prdata(25 DOWNTO 0) <= reg_sp.length_matrix; | |
474 | --------------------------------------------------------------------- |
|
477 | --------------------------------------------------------------------- | |
475 | --20 |
|
478 | --20 | |
476 | WHEN "010101" => prdata(0) <= reg_wp.data_shaping_BW; |
|
479 | WHEN "010101" => prdata(0) <= reg_wp.data_shaping_BW; | |
477 | prdata(1) <= reg_wp.data_shaping_SP0; |
|
480 | prdata(1) <= reg_wp.data_shaping_SP0; | |
478 | prdata(2) <= reg_wp.data_shaping_SP1; |
|
481 | prdata(2) <= reg_wp.data_shaping_SP1; | |
479 | prdata(3) <= reg_wp.data_shaping_R0; |
|
482 | prdata(3) <= reg_wp.data_shaping_R0; | |
480 | prdata(4) <= reg_wp.data_shaping_R1; |
|
483 | prdata(4) <= reg_wp.data_shaping_R1; | |
481 | prdata(5) <= reg_wp.data_shaping_R2; |
|
484 | prdata(5) <= reg_wp.data_shaping_R2; | |
482 | --21 |
|
485 | --21 | |
483 | WHEN "010110" => prdata(0) <= reg_wp.enable_f0; |
|
486 | WHEN "010110" => prdata(0) <= reg_wp.enable_f0; | |
484 | prdata(1) <= reg_wp.enable_f1; |
|
487 | prdata(1) <= reg_wp.enable_f1; | |
485 | prdata(2) <= reg_wp.enable_f2; |
|
488 | prdata(2) <= reg_wp.enable_f2; | |
486 | prdata(3) <= reg_wp.enable_f3; |
|
489 | prdata(3) <= reg_wp.enable_f3; | |
487 | prdata(4) <= reg_wp.burst_f0; |
|
490 | prdata(4) <= reg_wp.burst_f0; | |
488 | prdata(5) <= reg_wp.burst_f1; |
|
491 | prdata(5) <= reg_wp.burst_f1; | |
489 | prdata(6) <= reg_wp.burst_f2; |
|
492 | prdata(6) <= reg_wp.burst_f2; | |
490 | prdata(7) <= reg_wp.run; |
|
493 | prdata(7) <= reg_wp.run; | |
491 | --22 |
|
494 | --22 | |
492 | --ON GOING \/ |
|
495 | --ON GOING \/ | |
493 | WHEN "010111" => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0); |
|
496 | WHEN "010111" => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0);--0 | |
494 | WHEN "011000" => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1); |
|
497 | WHEN "011000" => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1); | |
495 | WHEN "011001" => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2); |
|
498 | WHEN "011001" => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2);--1 | |
496 | WHEN "011010" => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3); |
|
499 | WHEN "011010" => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3); | |
497 | WHEN "011011" => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4); |
|
500 | WHEN "011011" => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4);--2 | |
498 | WHEN "011100" => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5); |
|
501 | WHEN "011100" => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5); | |
499 | WHEN "011101" => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6); |
|
502 | WHEN "011101" => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6);--3 | |
500 | WHEN "011110" => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7); |
|
503 | WHEN "011110" => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7); | |
501 | --ON GOING /\ |
|
504 | --ON GOING /\ | |
502 | WHEN "011111" => prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f; |
|
505 | WHEN "011111" => prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f; | |
503 | prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full; |
|
506 | prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full; | |
504 | prdata(15 DOWNTO 12) <= reg_wp.status_new_err; |
|
507 | prdata(15 DOWNTO 12) <= reg_wp.status_new_err; | |
505 | --prdata(3 DOWNTO 0) <= reg_wp.status_full; |
|
508 | --prdata(3 DOWNTO 0) <= reg_wp.status_full; | |
506 | -- prdata(7 DOWNTO 4) <= reg_wp.status_full_err; |
|
509 | -- prdata(7 DOWNTO 4) <= reg_wp.status_full_err; | |
507 | --27 |
|
510 | --27 | |
508 | WHEN "100000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; |
|
511 | WHEN "100000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; | |
509 | --28 |
|
512 | --28 | |
510 | WHEN "100001" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; |
|
513 | WHEN "100001" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; | |
511 | --29 |
|
514 | --29 | |
512 | WHEN "100010" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; |
|
515 | WHEN "100010" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; | |
513 | --30 |
|
516 | --30 | |
514 | WHEN "100011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; |
|
517 | WHEN "100011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; | |
515 | --31 |
|
518 | --31 | |
516 | WHEN "100100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; |
|
519 | WHEN "100100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; | |
517 | --32 |
|
520 | --32 | |
518 | WHEN "100101" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; |
|
521 | WHEN "100101" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; | |
519 | --33 |
|
522 | --33 | |
520 | WHEN "100110" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; |
|
523 | WHEN "100110" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; | |
521 | --34 |
|
524 | --34 | |
522 | WHEN "100111" => prdata(30 DOWNTO 0) <= reg_wp.start_date; |
|
525 | WHEN "100111" => prdata(30 DOWNTO 0) <= reg_wp.start_date; | |
523 | --35 |
|
526 | --35 | |
524 | WHEN "101000" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0+15 DOWNTO 48*0); |
|
527 | WHEN "101000" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0+15 DOWNTO 48*0); | |
525 | WHEN "101001" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0+47 DOWNTO 48*0+16); |
|
528 | WHEN "101001" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0+47 DOWNTO 48*0+16); | |
526 | WHEN "101010" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1+15 DOWNTO 48*1); |
|
529 | WHEN "101010" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1+15 DOWNTO 48*1); | |
527 | WHEN "101011" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1+47 DOWNTO 48*1+16); |
|
530 | WHEN "101011" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1+47 DOWNTO 48*1+16); | |
|
531 | ||||
528 |
|
|
532 | WHEN "101100" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2+15 DOWNTO 48*2); | |
529 |
WHEN "1011 |
|
533 | WHEN "101101" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2+47 DOWNTO 48*2+16); | |
530 |
WHEN "10111 |
|
534 | WHEN "101110" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3+15 DOWNTO 48*3); | |
531 |
WHEN "1 |
|
535 | WHEN "101111" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3+47 DOWNTO 48*3+16); | |
532 |
|
536 | |||
533 |
WHEN "11000 |
|
537 | WHEN "110000" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4+15 DOWNTO 48*4); | |
534 |
WHEN "11 |
|
538 | WHEN "110001" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4+47 DOWNTO 48*4+16); | |
535 |
WHEN "11001 |
|
539 | WHEN "110010" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5+15 DOWNTO 48*5); | |
536 |
WHEN "110 |
|
540 | WHEN "110011" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5+47 DOWNTO 48*5+16); | |
537 | WHEN "110101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6+15 DOWNTO 48*6); |
|
541 | ||
538 |
|
|
542 | WHEN "110100" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6+15 DOWNTO 48*6); | |
539 |
WHEN "1101 |
|
543 | WHEN "110101" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6+47 DOWNTO 48*6+16); | |
540 |
WHEN "11 |
|
544 | WHEN "110110" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7+15 DOWNTO 48*7); | |
541 |
WHEN "11 |
|
545 | WHEN "110111" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7+47 DOWNTO 48*7+16); | |
|
546 | ||||
|
547 | WHEN "111000" => prdata(25 DOWNTO 0) <= reg_wp.length_buffer; | |||
542 |
|
548 | |||
543 | -- WHEN "100100" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; |
|
549 | -- WHEN "100100" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; | |
544 | ---------------------------------------------------- |
|
550 | ---------------------------------------------------- | |
545 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); |
|
551 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); | |
546 | WHEN OTHERS => NULL; |
|
552 | WHEN OTHERS => NULL; | |
547 |
|
553 | |||
548 | END CASE; |
|
554 | END CASE; | |
549 | IF (apbi.pwrite AND apbi.penable) = '1' THEN |
|
555 | IF (apbi.pwrite AND apbi.penable) = '1' THEN | |
550 | -- APB DMA WRITE -- |
|
556 | -- APB DMA WRITE -- | |
551 | CASE paddr(7 DOWNTO 2) IS |
|
557 | CASE paddr(7 DOWNTO 2) IS | |
552 | -- |
|
558 | -- | |
553 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); |
|
559 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); | |
554 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); |
|
560 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); | |
555 | reg_sp.config_ms_run <= apbi.pwdata(2); |
|
561 | reg_sp.config_ms_run <= apbi.pwdata(2); | |
556 |
|
562 | |||
557 | WHEN "000001" => |
|
563 | WHEN "000001" => | |
558 | reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0; |
|
564 | reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0; | |
559 | reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0; |
|
565 | reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0; | |
560 | reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1; |
|
566 | reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1; | |
561 | reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1; |
|
567 | reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1; | |
562 | reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2; |
|
568 | reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2; | |
563 | reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2; |
|
569 | reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2; | |
564 | reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full; |
|
570 | reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full; | |
565 | reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0); |
|
571 | reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0); | |
566 | reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1); |
|
572 | reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1); | |
567 | reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2); |
|
573 | reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2); | |
568 | --2 |
|
574 | --2 | |
569 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; |
|
575 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; | |
570 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; |
|
576 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |
571 | WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata; |
|
577 | WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata; | |
572 | WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata; |
|
578 | WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata; | |
573 | WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata; |
|
579 | WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata; | |
574 | WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata; |
|
580 | WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata; | |
575 | --8 to 19 |
|
581 | --8 to 19 | |
576 | --20 |
|
582 | --20 | |
577 | WHEN "010100" => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0); |
|
583 | WHEN "010100" => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0); | |
578 | --20 |
|
584 | --20 | |
579 | WHEN "010101" => reg_wp.data_shaping_BW <= apbi.pwdata(0); |
|
585 | WHEN "010101" => reg_wp.data_shaping_BW <= apbi.pwdata(0); | |
580 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); |
|
586 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); | |
581 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); |
|
587 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); | |
582 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); |
|
588 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); | |
583 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); |
|
589 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); | |
584 | reg_wp.data_shaping_R2 <= apbi.pwdata(5); |
|
590 | reg_wp.data_shaping_R2 <= apbi.pwdata(5); | |
585 | WHEN "010110" => reg_wp.enable_f0 <= apbi.pwdata(0); |
|
591 | WHEN "010110" => reg_wp.enable_f0 <= apbi.pwdata(0); | |
586 | reg_wp.enable_f1 <= apbi.pwdata(1); |
|
592 | reg_wp.enable_f1 <= apbi.pwdata(1); | |
587 | reg_wp.enable_f2 <= apbi.pwdata(2); |
|
593 | reg_wp.enable_f2 <= apbi.pwdata(2); | |
588 | reg_wp.enable_f3 <= apbi.pwdata(3); |
|
594 | reg_wp.enable_f3 <= apbi.pwdata(3); | |
589 | reg_wp.burst_f0 <= apbi.pwdata(4); |
|
595 | reg_wp.burst_f0 <= apbi.pwdata(4); | |
590 | reg_wp.burst_f1 <= apbi.pwdata(5); |
|
596 | reg_wp.burst_f1 <= apbi.pwdata(5); | |
591 | reg_wp.burst_f2 <= apbi.pwdata(6); |
|
597 | reg_wp.burst_f2 <= apbi.pwdata(6); | |
592 | reg_wp.run <= apbi.pwdata(7); |
|
598 | reg_wp.run <= apbi.pwdata(7); | |
593 | --22 |
|
599 | --22 | |
594 | WHEN "010111" => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata; |
|
600 | WHEN "010111" => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata; | |
595 | WHEN "011000" => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata; |
|
601 | WHEN "011000" => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata; | |
596 | WHEN "011001" => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata; |
|
602 | WHEN "011001" => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata; | |
597 | WHEN "011010" => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata; |
|
603 | WHEN "011010" => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata; | |
598 | WHEN "011011" => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata; |
|
604 | WHEN "011011" => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata; | |
599 | WHEN "011100" => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata; |
|
605 | WHEN "011100" => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata; | |
600 | WHEN "011101" => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata; |
|
606 | WHEN "011101" => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata; | |
601 | WHEN "011110" => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata; |
|
607 | WHEN "011110" => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata; | |
602 | --26 |
|
608 | --26 | |
603 | WHEN "011111" => |
|
609 | WHEN "011111" => | |
604 | all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP |
|
610 | all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP | |
605 | reg_wp.status_ready_buffer_f(I) <= ((NOT apbi.pwdata(I) ) AND reg_wp.status_ready_buffer_f(I) ) OR reg_ready_buffer_f(I); |
|
611 | reg_wp.status_ready_buffer_f(I) <= ((NOT apbi.pwdata(I) ) AND reg_wp.status_ready_buffer_f(I) ) OR reg_ready_buffer_f(I); | |
606 | reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1); |
|
612 | reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1); | |
607 | reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I); |
|
613 | reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I); | |
608 | reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I); |
|
614 | reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I); | |
609 | END LOOP all_reg_wp_status_bit; |
|
615 | END LOOP all_reg_wp_status_bit; | |
610 |
|
616 | |||
611 | WHEN "100000" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); |
|
617 | WHEN "100000" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
612 | WHEN "100001" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); |
|
618 | WHEN "100001" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
613 | WHEN "100010" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); |
|
619 | WHEN "100010" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); | |
614 | WHEN "100011" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); |
|
620 | WHEN "100011" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
615 | WHEN "100100" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); |
|
621 | WHEN "100100" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
616 | WHEN "100101" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); |
|
622 | WHEN "100101" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); | |
617 | WHEN "100110" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); |
|
623 | WHEN "100110" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); | |
618 | WHEN "100111" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); |
|
624 | WHEN "100111" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); | |
619 |
|
625 | |||
620 |
WHEN "11100 |
|
626 | WHEN "111000" => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0); | |
621 |
|
627 | |||
622 |
|
628 | |||
623 |
|
629 | |||
624 |
|
630 | |||
625 |
|
631 | |||
626 | -- WHEN "100100" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); |
|
632 | -- WHEN "100100" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); | |
627 | -- |
|
633 | -- | |
628 | WHEN OTHERS => NULL; |
|
634 | WHEN OTHERS => NULL; | |
629 | END CASE; |
|
635 | END CASE; | |
630 | END IF; |
|
636 | END IF; | |
631 | END IF; |
|
637 | END IF; | |
632 | --apbo.pirq(pirq_ms) <= |
|
638 | --apbo.pirq(pirq_ms) <= | |
633 | apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR |
|
639 | apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR | |
634 | ready_matrix_f1 OR |
|
640 | ready_matrix_f1 OR | |
635 | ready_matrix_f2) |
|
641 | ready_matrix_f2) | |
636 | ) |
|
642 | ) | |
637 | OR |
|
643 | OR | |
638 | (reg_sp.config_active_interruption_onError AND ( |
|
644 | (reg_sp.config_active_interruption_onError AND ( | |
639 | -- error_bad_component_error OR |
|
645 | -- error_bad_component_error OR | |
640 | error_buffer_full |
|
646 | error_buffer_full | |
641 | OR error_input_fifo_write(0) |
|
647 | OR error_input_fifo_write(0) | |
642 | OR error_input_fifo_write(1) |
|
648 | OR error_input_fifo_write(1) | |
643 | OR error_input_fifo_write(2)) |
|
649 | OR error_input_fifo_write(2)) | |
644 | )); |
|
650 | )); | |
645 | -- apbo.pirq(pirq_wfp) |
|
651 | -- apbo.pirq(pirq_wfp) | |
646 | apbo_irq_wfp<= ored_irq_wfp; |
|
652 | apbo_irq_wfp<= ored_irq_wfp; | |
647 |
|
653 | |||
648 | END IF; |
|
654 | END IF; | |
649 | END PROCESS lpp_lfr_apbreg; |
|
655 | END PROCESS lpp_lfr_apbreg; | |
650 |
|
656 | |||
651 | apbo.pirq(pirq_ms) <= apbo_irq_ms; |
|
657 | apbo.pirq(pirq_ms) <= apbo_irq_ms; | |
652 | apbo.pirq(pirq_wfp) <= apbo_irq_wfp; |
|
658 | apbo.pirq(pirq_wfp) <= apbo_irq_wfp; | |
653 |
|
659 | |||
654 | apbo.pindex <= pindex; |
|
660 | apbo.pindex <= pindex; | |
655 | apbo.pconfig <= pconfig; |
|
661 | apbo.pconfig <= pconfig; | |
656 | apbo.prdata <= prdata; |
|
662 | apbo.prdata <= prdata; | |
657 |
|
663 | |||
658 | ----------------------------------------------------------------------------- |
|
664 | ----------------------------------------------------------------------------- | |
659 | -- IRQ |
|
665 | -- IRQ | |
660 | ----------------------------------------------------------------------------- |
|
666 | ----------------------------------------------------------------------------- | |
661 |
irq_wfp_reg_s <= wfp_ |
|
667 | irq_wfp_reg_s <= wfp_ready_buffer & wfp_error_buffer_full & status_new_err; | |
662 |
|
668 | |||
663 | PROCESS (HCLK, HRESETn) |
|
669 | PROCESS (HCLK, HRESETn) | |
664 | BEGIN -- PROCESS |
|
670 | BEGIN -- PROCESS | |
665 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
671 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
666 | irq_wfp_reg <= (OTHERS => '0'); |
|
672 | irq_wfp_reg <= (OTHERS => '0'); | |
667 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
673 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
668 | irq_wfp_reg <= irq_wfp_reg_s; |
|
674 | irq_wfp_reg <= irq_wfp_reg_s; | |
669 | END IF; |
|
675 | END IF; | |
670 | END PROCESS; |
|
676 | END PROCESS; | |
671 |
|
677 | |||
672 | all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE |
|
678 | all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE | |
673 | irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I); |
|
679 | irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I); | |
674 | END GENERATE all_irq_wfp; |
|
680 | END GENERATE all_irq_wfp; | |
675 |
|
681 | |||
676 | irq_wfp_ZERO <= (OTHERS => '0'); |
|
682 | irq_wfp_ZERO <= (OTHERS => '0'); | |
677 | ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; |
|
683 | ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; | |
678 |
|
684 | |||
679 | run_ms <= reg_sp.config_ms_run; |
|
685 | run_ms <= reg_sp.config_ms_run; | |
680 |
|
686 | |||
681 | ----------------------------------------------------------------------------- |
|
687 | ----------------------------------------------------------------------------- | |
682 | -- |
|
688 | -- | |
683 | ----------------------------------------------------------------------------- |
|
689 | ----------------------------------------------------------------------------- | |
684 | lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer |
|
690 | lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer | |
685 | PORT MAP ( |
|
691 | PORT MAP ( | |
686 | clk => HCLK, |
|
692 | clk => HCLK, | |
687 | rstn => HRESETn, |
|
693 | rstn => HRESETn, | |
688 |
|
694 | |||
689 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0, |
|
695 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0, | |
690 | reg0_ready_matrix => reg0_ready_matrix_f0, |
|
696 | reg0_ready_matrix => reg0_ready_matrix_f0, | |
691 | reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0, |
|
697 | reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0, | |
692 | reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0, |
|
698 | reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0, | |
693 |
|
699 | |||
694 | reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1, |
|
700 | reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1, | |
695 | reg1_ready_matrix => reg1_ready_matrix_f0, |
|
701 | reg1_ready_matrix => reg1_ready_matrix_f0, | |
696 | reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0, |
|
702 | reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0, | |
697 | reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0, |
|
703 | reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0, | |
698 |
|
704 | |||
699 | ready_matrix => ready_matrix_f0, |
|
705 | ready_matrix => ready_matrix_f0, | |
700 | status_ready_matrix => status_ready_matrix_f0, |
|
706 | status_ready_matrix => status_ready_matrix_f0, | |
701 | addr_matrix => addr_matrix_f0, |
|
707 | addr_matrix => addr_matrix_f0, | |
702 | matrix_time => matrix_time_f0); |
|
708 | matrix_time => matrix_time_f0); | |
703 |
|
709 | |||
704 | lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer |
|
710 | lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer | |
705 | PORT MAP ( |
|
711 | PORT MAP ( | |
706 | clk => HCLK, |
|
712 | clk => HCLK, | |
707 | rstn => HRESETn, |
|
713 | rstn => HRESETn, | |
708 |
|
714 | |||
709 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0, |
|
715 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0, | |
710 | reg0_ready_matrix => reg0_ready_matrix_f1, |
|
716 | reg0_ready_matrix => reg0_ready_matrix_f1, | |
711 | reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1, |
|
717 | reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1, | |
712 | reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1, |
|
718 | reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1, | |
713 |
|
719 | |||
714 | reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1, |
|
720 | reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1, | |
715 | reg1_ready_matrix => reg1_ready_matrix_f1, |
|
721 | reg1_ready_matrix => reg1_ready_matrix_f1, | |
716 | reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1, |
|
722 | reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1, | |
717 | reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1, |
|
723 | reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1, | |
718 |
|
724 | |||
719 | ready_matrix => ready_matrix_f1, |
|
725 | ready_matrix => ready_matrix_f1, | |
720 | status_ready_matrix => status_ready_matrix_f1, |
|
726 | status_ready_matrix => status_ready_matrix_f1, | |
721 | addr_matrix => addr_matrix_f1, |
|
727 | addr_matrix => addr_matrix_f1, | |
722 | matrix_time => matrix_time_f1); |
|
728 | matrix_time => matrix_time_f1); | |
723 |
|
729 | |||
724 | lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer |
|
730 | lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer | |
725 | PORT MAP ( |
|
731 | PORT MAP ( | |
726 | clk => HCLK, |
|
732 | clk => HCLK, | |
727 | rstn => HRESETn, |
|
733 | rstn => HRESETn, | |
728 |
|
734 | |||
729 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0, |
|
735 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0, | |
730 | reg0_ready_matrix => reg0_ready_matrix_f2, |
|
736 | reg0_ready_matrix => reg0_ready_matrix_f2, | |
731 | reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2, |
|
737 | reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2, | |
732 | reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2, |
|
738 | reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2, | |
733 |
|
739 | |||
734 | reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1, |
|
740 | reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1, | |
735 | reg1_ready_matrix => reg1_ready_matrix_f2, |
|
741 | reg1_ready_matrix => reg1_ready_matrix_f2, | |
736 | reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2, |
|
742 | reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2, | |
737 | reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2, |
|
743 | reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2, | |
738 |
|
744 | |||
739 | ready_matrix => ready_matrix_f2, |
|
745 | ready_matrix => ready_matrix_f2, | |
740 | status_ready_matrix => status_ready_matrix_f2, |
|
746 | status_ready_matrix => status_ready_matrix_f2, | |
741 | addr_matrix => addr_matrix_f2, |
|
747 | addr_matrix => addr_matrix_f2, | |
742 | matrix_time => matrix_time_f2); |
|
748 | matrix_time => matrix_time_f2); | |
743 |
|
749 | |||
744 | ----------------------------------------------------------------------------- |
|
750 | ----------------------------------------------------------------------------- | |
745 | all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE |
|
751 | all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE | |
746 | lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer |
|
752 | lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer | |
747 | PORT MAP ( |
|
753 | PORT MAP ( | |
748 | clk => HCLK, |
|
754 | clk => HCLK, | |
749 | rstn => HRESETn, |
|
755 | rstn => HRESETn, | |
750 |
|
756 | |||
751 | reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I), |
|
757 | reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I), | |
752 | reg0_ready_matrix => reg_ready_buffer_f(2*I), |
|
758 | reg0_ready_matrix => reg_ready_buffer_f(2*I), | |
753 | reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32), |
|
759 | reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32), | |
754 | reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48), |
|
760 | reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48), | |
755 |
|
761 | |||
756 | reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1), |
|
762 | reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1), | |
757 | reg1_ready_matrix => reg_ready_buffer_f(2*I+1), |
|
763 | reg1_ready_matrix => reg_ready_buffer_f(2*I+1), | |
758 | reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32), |
|
764 | reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32), | |
759 | reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48), |
|
765 | reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48), | |
760 |
|
766 | |||
761 | ready_matrix => wfp_ready_buffer(I), |
|
767 | ready_matrix => wfp_ready_buffer(I), | |
762 | status_ready_matrix => wfp_status_buffer_ready(I), |
|
768 | status_ready_matrix => wfp_status_buffer_ready(I), | |
763 | addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32), |
|
769 | addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32), | |
764 | matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48) |
|
770 | matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48) | |
765 | ); |
|
771 | ); | |
766 |
|
772 | |||
767 | END GENERATE all_wfp_pointer; |
|
773 | END GENERATE all_wfp_pointer; | |
768 | ----------------------------------------------------------------------------- |
|
774 | ----------------------------------------------------------------------------- | |
769 |
|
775 | |||
770 | END beh; No newline at end of file |
|
776 | END beh; |
@@ -1,1144 +1,1144 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 |
|
3 | |||
4 |
|
4 | |||
5 | LIBRARY lpp; |
|
5 | LIBRARY lpp; | |
6 | USE lpp.lpp_memory.ALL; |
|
6 | USE lpp.lpp_memory.ALL; | |
7 | USE lpp.iir_filter.ALL; |
|
7 | USE lpp.iir_filter.ALL; | |
8 | USE lpp.spectral_matrix_package.ALL; |
|
8 | USE lpp.spectral_matrix_package.ALL; | |
9 | USE lpp.lpp_dma_pkg.ALL; |
|
9 | USE lpp.lpp_dma_pkg.ALL; | |
10 | USE lpp.lpp_Header.ALL; |
|
10 | USE lpp.lpp_Header.ALL; | |
11 | USE lpp.lpp_matrix.ALL; |
|
11 | USE lpp.lpp_matrix.ALL; | |
12 | USE lpp.lpp_matrix.ALL; |
|
12 | USE lpp.lpp_matrix.ALL; | |
13 | USE lpp.lpp_lfr_pkg.ALL; |
|
13 | USE lpp.lpp_lfr_pkg.ALL; | |
14 | USE lpp.lpp_fft.ALL; |
|
14 | USE lpp.lpp_fft.ALL; | |
15 | USE lpp.fft_components.ALL; |
|
15 | USE lpp.fft_components.ALL; | |
16 |
|
16 | |||
17 | ENTITY lpp_lfr_ms IS |
|
17 | ENTITY lpp_lfr_ms IS | |
18 | GENERIC ( |
|
18 | GENERIC ( | |
19 | Mem_use : INTEGER := use_RAM |
|
19 | Mem_use : INTEGER := use_RAM | |
20 | ); |
|
20 | ); | |
21 | PORT ( |
|
21 | PORT ( | |
22 | clk : IN STD_LOGIC; |
|
22 | clk : IN STD_LOGIC; | |
23 | rstn : IN STD_LOGIC; |
|
23 | rstn : IN STD_LOGIC; | |
24 | run : IN STD_LOGIC; |
|
24 | run : IN STD_LOGIC; | |
25 |
|
25 | |||
26 | --------------------------------------------------------------------------- |
|
26 | --------------------------------------------------------------------------- | |
27 | -- DATA INPUT |
|
27 | -- DATA INPUT | |
28 | --------------------------------------------------------------------------- |
|
28 | --------------------------------------------------------------------------- | |
29 | -- TIME |
|
29 | -- TIME | |
30 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
30 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
31 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
31 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
32 | -- |
|
32 | -- | |
33 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
33 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
34 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
34 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
35 | -- |
|
35 | -- | |
36 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
36 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
37 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
37 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
38 | -- |
|
38 | -- | |
39 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
39 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
40 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
40 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
41 |
|
41 | |||
42 | --------------------------------------------------------------------------- |
|
42 | --------------------------------------------------------------------------- | |
43 | -- DMA |
|
43 | -- DMA | |
44 | --------------------------------------------------------------------------- |
|
44 | --------------------------------------------------------------------------- | |
45 | dma_fifo_burst_valid: OUT STD_LOGIC; --TODO |
|
45 | dma_fifo_burst_valid: OUT STD_LOGIC; --TODO | |
46 | dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO |
|
46 | dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO | |
47 | dma_fifo_ren : IN STD_LOGIC; --TODO |
|
47 | dma_fifo_ren : IN STD_LOGIC; --TODO | |
48 | dma_buffer_new : OUT STD_LOGIC; --TODO |
|
48 | dma_buffer_new : OUT STD_LOGIC; --TODOx | |
49 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO |
|
49 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO | |
50 | dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO |
|
50 | dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO | |
51 | dma_buffer_full : IN STD_LOGIC; --TODO |
|
51 | dma_buffer_full : IN STD_LOGIC; --TODO | |
52 | dma_buffer_full_err : IN STD_LOGIC; --TODO |
|
52 | dma_buffer_full_err : IN STD_LOGIC; --TODO | |
53 |
|
53 | |||
54 | -- Reg out |
|
54 | -- Reg out | |
55 | ready_matrix_f0 : OUT STD_LOGIC; -- TODO |
|
55 | ready_matrix_f0 : OUT STD_LOGIC; -- TODO | |
56 | ready_matrix_f1 : OUT STD_LOGIC; -- TODO |
|
56 | ready_matrix_f1 : OUT STD_LOGIC; -- TODO | |
57 | ready_matrix_f2 : OUT STD_LOGIC; -- TODO |
|
57 | ready_matrix_f2 : OUT STD_LOGIC; -- TODO | |
58 | -- error_bad_component_error : OUT STD_LOGIC; -- TODO |
|
58 | -- error_bad_component_error : OUT STD_LOGIC; -- TODO | |
59 | error_buffer_full : OUT STD_LOGIC; -- TODO |
|
59 | error_buffer_full : OUT STD_LOGIC; -- TODO | |
60 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
60 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
61 |
|
61 | |||
62 | -- Reg In |
|
62 | -- Reg In | |
63 | status_ready_matrix_f0 : IN STD_LOGIC; -- TODO |
|
63 | status_ready_matrix_f0 : IN STD_LOGIC; -- TODO | |
64 | status_ready_matrix_f1 : IN STD_LOGIC; -- TODO |
|
64 | status_ready_matrix_f1 : IN STD_LOGIC; -- TODO | |
65 | status_ready_matrix_f2 : IN STD_LOGIC; -- TODO |
|
65 | status_ready_matrix_f2 : IN STD_LOGIC; -- TODO | |
66 |
|
66 | |||
67 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO |
|
67 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO | |
68 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO |
|
68 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO | |
69 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO |
|
69 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO | |
70 |
|
70 | |||
71 | length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO |
|
71 | length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO | |
72 | length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO |
|
72 | length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO | |
73 | length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO |
|
73 | length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO | |
74 |
|
74 | |||
75 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO |
|
75 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO | |
76 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO |
|
76 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO | |
77 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO |
|
77 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO | |
78 |
|
78 | |||
79 | ); |
|
79 | ); | |
80 | END; |
|
80 | END; | |
81 |
|
81 | |||
82 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS |
|
82 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |
83 |
|
83 | |||
84 | SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
84 | SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
85 | SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
85 | SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
86 | SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
86 | SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
87 | SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
87 | SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
88 | SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
88 | SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
89 |
|
89 | |||
90 | SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
90 | SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
91 | SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
91 | SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
92 | SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
92 | SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
93 | SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
93 | SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
94 | SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
94 | SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
95 |
|
95 | |||
96 | SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
96 | SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
97 | SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
97 | SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
98 | SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
98 | SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
99 | SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
99 | SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
100 |
|
100 | |||
101 | SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
101 | SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
102 |
|
102 | |||
103 | SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
103 | SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
104 | SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
104 | SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
105 | SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
105 | SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
106 | SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
106 | SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
107 |
|
107 | |||
108 | SIGNAL error_wen_f0 : STD_LOGIC; |
|
108 | SIGNAL error_wen_f0 : STD_LOGIC; | |
109 | SIGNAL error_wen_f1 : STD_LOGIC; |
|
109 | SIGNAL error_wen_f1 : STD_LOGIC; | |
110 | SIGNAL error_wen_f2 : STD_LOGIC; |
|
110 | SIGNAL error_wen_f2 : STD_LOGIC; | |
111 |
|
111 | |||
112 | SIGNAL one_sample_f1_full : STD_LOGIC; |
|
112 | SIGNAL one_sample_f1_full : STD_LOGIC; | |
113 | SIGNAL one_sample_f1_wen : STD_LOGIC; |
|
113 | SIGNAL one_sample_f1_wen : STD_LOGIC; | |
114 | SIGNAL one_sample_f2_full : STD_LOGIC; |
|
114 | SIGNAL one_sample_f2_full : STD_LOGIC; | |
115 | SIGNAL one_sample_f2_wen : STD_LOGIC; |
|
115 | SIGNAL one_sample_f2_wen : STD_LOGIC; | |
116 |
|
116 | |||
117 | ----------------------------------------------------------------------------- |
|
117 | ----------------------------------------------------------------------------- | |
118 | -- FSM / SWITCH SELECT CHANNEL |
|
118 | -- FSM / SWITCH SELECT CHANNEL | |
119 | ----------------------------------------------------------------------------- |
|
119 | ----------------------------------------------------------------------------- | |
120 | TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2); |
|
120 | TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2); | |
121 | SIGNAL state_fsm_select_channel : fsm_select_channel; |
|
121 | SIGNAL state_fsm_select_channel : fsm_select_channel; | |
122 | SIGNAL pre_state_fsm_select_channel : fsm_select_channel; |
|
122 | SIGNAL pre_state_fsm_select_channel : fsm_select_channel; | |
123 |
|
123 | |||
124 | SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
124 | SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
125 | SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
125 | SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
126 | SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
126 | SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
127 | SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
127 | SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
128 |
|
128 | |||
129 | ----------------------------------------------------------------------------- |
|
129 | ----------------------------------------------------------------------------- | |
130 | -- FSM LOAD FFT |
|
130 | -- FSM LOAD FFT | |
131 | ----------------------------------------------------------------------------- |
|
131 | ----------------------------------------------------------------------------- | |
132 | TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5); |
|
132 | TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5); | |
133 | SIGNAL state_fsm_load_FFT : fsm_load_FFT; |
|
133 | SIGNAL state_fsm_load_FFT : fsm_load_FFT; | |
134 | SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; |
|
134 | SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; | |
135 |
|
135 | |||
136 | SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
136 | SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
137 | SIGNAL sample_load : STD_LOGIC; |
|
137 | SIGNAL sample_load : STD_LOGIC; | |
138 | SIGNAL sample_valid : STD_LOGIC; |
|
138 | SIGNAL sample_valid : STD_LOGIC; | |
139 | SIGNAL sample_valid_r : STD_LOGIC; |
|
139 | SIGNAL sample_valid_r : STD_LOGIC; | |
140 | SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
140 | SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
141 |
|
141 | |||
142 |
|
142 | |||
143 | ----------------------------------------------------------------------------- |
|
143 | ----------------------------------------------------------------------------- | |
144 | -- FFT |
|
144 | -- FFT | |
145 | ----------------------------------------------------------------------------- |
|
145 | ----------------------------------------------------------------------------- | |
146 | SIGNAL fft_read : STD_LOGIC; |
|
146 | SIGNAL fft_read : STD_LOGIC; | |
147 | SIGNAL fft_pong : STD_LOGIC; |
|
147 | SIGNAL fft_pong : STD_LOGIC; | |
148 | SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
148 | SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
149 | SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
149 | SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
150 | SIGNAL fft_data_valid : STD_LOGIC; |
|
150 | SIGNAL fft_data_valid : STD_LOGIC; | |
151 | SIGNAL fft_ready : STD_LOGIC; |
|
151 | SIGNAL fft_ready : STD_LOGIC; | |
152 | ----------------------------------------------------------------------------- |
|
152 | ----------------------------------------------------------------------------- | |
153 | -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
153 | -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
154 | ----------------------------------------------------------------------------- |
|
154 | ----------------------------------------------------------------------------- | |
155 | TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT); |
|
155 | TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT); | |
156 | SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory; |
|
156 | SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory; | |
157 | SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
157 | SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
158 | SIGNAL current_fifo_empty : STD_LOGIC; |
|
158 | SIGNAL current_fifo_empty : STD_LOGIC; | |
159 | SIGNAL current_fifo_locked : STD_LOGIC; |
|
159 | SIGNAL current_fifo_locked : STD_LOGIC; | |
160 | SIGNAL current_fifo_full : STD_LOGIC; |
|
160 | SIGNAL current_fifo_full : STD_LOGIC; | |
161 | SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
161 | SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
162 |
|
162 | |||
163 | ----------------------------------------------------------------------------- |
|
163 | ----------------------------------------------------------------------------- | |
164 | SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
164 | SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
165 | SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
165 | SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
166 | SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
166 | SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
167 | SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
167 | SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
168 | SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); |
|
168 | SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); | |
169 | SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); |
|
169 | SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); | |
170 | SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
170 | SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
171 | SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
171 | SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
172 | ----------------------------------------------------------------------------- |
|
172 | ----------------------------------------------------------------------------- | |
173 | SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); |
|
173 | SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); | |
174 | SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
174 | SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
175 | SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
175 | SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
176 |
|
176 | |||
177 | SIGNAL SM_correlation_start : STD_LOGIC; |
|
177 | SIGNAL SM_correlation_start : STD_LOGIC; | |
178 | SIGNAL SM_correlation_auto : STD_LOGIC; |
|
178 | SIGNAL SM_correlation_auto : STD_LOGIC; | |
179 | SIGNAL SM_correlation_done : STD_LOGIC; |
|
179 | SIGNAL SM_correlation_done : STD_LOGIC; | |
180 | SIGNAL SM_correlation_done_reg1 : STD_LOGIC; |
|
180 | SIGNAL SM_correlation_done_reg1 : STD_LOGIC; | |
181 | SIGNAL SM_correlation_done_reg2 : STD_LOGIC; |
|
181 | SIGNAL SM_correlation_done_reg2 : STD_LOGIC; | |
182 | SIGNAL SM_correlation_done_reg3 : STD_LOGIC; |
|
182 | SIGNAL SM_correlation_done_reg3 : STD_LOGIC; | |
183 | SIGNAL SM_correlation_begin : STD_LOGIC; |
|
183 | SIGNAL SM_correlation_begin : STD_LOGIC; | |
184 |
|
184 | |||
185 | SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC; |
|
185 | SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC; | |
186 | SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
186 | SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
187 | SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC; |
|
187 | SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC; | |
188 |
|
188 | |||
189 | SIGNAL current_matrix_write : STD_LOGIC; |
|
189 | SIGNAL current_matrix_write : STD_LOGIC; | |
190 | SIGNAL current_matrix_wait_empty : STD_LOGIC; |
|
190 | SIGNAL current_matrix_wait_empty : STD_LOGIC; | |
191 | ----------------------------------------------------------------------------- |
|
191 | ----------------------------------------------------------------------------- | |
192 | SIGNAL fifo_0_ready : STD_LOGIC; |
|
192 | SIGNAL fifo_0_ready : STD_LOGIC; | |
193 | SIGNAL fifo_1_ready : STD_LOGIC; |
|
193 | SIGNAL fifo_1_ready : STD_LOGIC; | |
194 | SIGNAL fifo_ongoing : STD_LOGIC; |
|
194 | SIGNAL fifo_ongoing : STD_LOGIC; | |
195 |
|
195 | |||
196 | SIGNAL FSM_DMA_fifo_ren : STD_LOGIC; |
|
196 | SIGNAL FSM_DMA_fifo_ren : STD_LOGIC; | |
197 | SIGNAL FSM_DMA_fifo_empty : STD_LOGIC; |
|
197 | SIGNAL FSM_DMA_fifo_empty : STD_LOGIC; | |
198 | SIGNAL FSM_DMA_fifo_empty_threshold : STD_LOGIC; |
|
198 | SIGNAL FSM_DMA_fifo_empty_threshold : STD_LOGIC; | |
199 | SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
199 | SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
200 | SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
200 | SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
201 | ----------------------------------------------------------------------------- |
|
201 | ----------------------------------------------------------------------------- | |
202 | SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
202 | SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
203 | SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
203 | SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
204 | SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
204 | SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
205 | SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
205 | SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
206 | SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
206 | SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
207 | SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
207 | SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
208 | SIGNAL MEM_OUT_SM_Empty_Threshold : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
208 | SIGNAL MEM_OUT_SM_Empty_Threshold : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
209 |
|
209 | |||
210 | ----------------------------------------------------------------------------- |
|
210 | ----------------------------------------------------------------------------- | |
211 | -- TIME REG & INFOs |
|
211 | -- TIME REG & INFOs | |
212 | ----------------------------------------------------------------------------- |
|
212 | ----------------------------------------------------------------------------- | |
213 | SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
213 | SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
214 |
|
214 | |||
215 | SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
215 | SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
216 | SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
216 | SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
217 | SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
217 | SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
218 | SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
|
218 | SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |
219 |
|
219 | |||
220 | SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
220 | SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
221 | SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
221 | SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
222 | SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
222 | SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
223 | SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
223 | SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
224 |
|
224 | |||
225 | --SIGNAL time_update_f0_A : STD_LOGIC; |
|
225 | --SIGNAL time_update_f0_A : STD_LOGIC; | |
226 | --SIGNAL time_update_f0_B : STD_LOGIC; |
|
226 | --SIGNAL time_update_f0_B : STD_LOGIC; | |
227 | --SIGNAL time_update_f1 : STD_LOGIC; |
|
227 | --SIGNAL time_update_f1 : STD_LOGIC; | |
228 | --SIGNAL time_update_f2 : STD_LOGIC; |
|
228 | --SIGNAL time_update_f2 : STD_LOGIC; | |
229 | -- |
|
229 | -- | |
230 | SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
230 | SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0); | |
231 | SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
231 | SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0); | |
232 | SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
232 | SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
233 |
|
233 | |||
234 | SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
234 | SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
235 | SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
235 | SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
236 | SIGNAL status_component_fifo_0_end : STD_LOGIC; |
|
236 | SIGNAL status_component_fifo_0_end : STD_LOGIC; | |
237 | SIGNAL status_component_fifo_1_end : STD_LOGIC; |
|
237 | SIGNAL status_component_fifo_1_end : STD_LOGIC; | |
238 | ----------------------------------------------------------------------------- |
|
238 | ----------------------------------------------------------------------------- | |
239 | SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0); |
|
239 | SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0); | |
240 |
|
240 | |||
241 | SIGNAL fft_ready_reg : STD_LOGIC; |
|
241 | SIGNAL fft_ready_reg : STD_LOGIC; | |
242 | SIGNAL fft_ready_rising_down : STD_LOGIC; |
|
242 | SIGNAL fft_ready_rising_down : STD_LOGIC; | |
243 |
|
243 | |||
244 | SIGNAL sample_load_reg : STD_LOGIC; |
|
244 | SIGNAL sample_load_reg : STD_LOGIC; | |
245 | SIGNAL sample_load_rising_down : STD_LOGIC; |
|
245 | SIGNAL sample_load_rising_down : STD_LOGIC; | |
246 |
|
246 | |||
247 | ----------------------------------------------------------------------------- |
|
247 | ----------------------------------------------------------------------------- | |
248 | SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
248 | SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
249 | SIGNAL sample_f1_wen_head_in : STD_LOGIC; |
|
249 | SIGNAL sample_f1_wen_head_in : STD_LOGIC; | |
250 | SIGNAL sample_f1_wen_head_out : STD_LOGIC; |
|
250 | SIGNAL sample_f1_wen_head_out : STD_LOGIC; | |
251 | SIGNAL sample_f1_full_head_in : STD_LOGIC; |
|
251 | SIGNAL sample_f1_full_head_in : STD_LOGIC; | |
252 | SIGNAL sample_f1_full_head_out : STD_LOGIC; |
|
252 | SIGNAL sample_f1_full_head_out : STD_LOGIC; | |
253 | SIGNAL sample_f1_empty_head_in : STD_LOGIC; |
|
253 | SIGNAL sample_f1_empty_head_in : STD_LOGIC; | |
254 |
|
254 | |||
255 | SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
255 | SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
256 |
|
256 | |||
257 | BEGIN |
|
257 | BEGIN | |
258 |
|
258 | |||
259 |
|
259 | |||
260 | error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0; |
|
260 | error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0; | |
261 |
|
261 | |||
262 |
|
262 | |||
263 | switch_f0_inst : spectral_matrix_switch_f0 |
|
263 | switch_f0_inst : spectral_matrix_switch_f0 | |
264 | PORT MAP ( |
|
264 | PORT MAP ( | |
265 | clk => clk, |
|
265 | clk => clk, | |
266 | rstn => rstn, |
|
266 | rstn => rstn, | |
267 |
|
267 | |||
268 | sample_wen => sample_f0_wen, |
|
268 | sample_wen => sample_f0_wen, | |
269 |
|
269 | |||
270 | fifo_A_empty => sample_f0_A_empty, |
|
270 | fifo_A_empty => sample_f0_A_empty, | |
271 | fifo_A_full => sample_f0_A_full, |
|
271 | fifo_A_full => sample_f0_A_full, | |
272 | fifo_A_wen => sample_f0_A_wen, |
|
272 | fifo_A_wen => sample_f0_A_wen, | |
273 |
|
273 | |||
274 | fifo_B_empty => sample_f0_B_empty, |
|
274 | fifo_B_empty => sample_f0_B_empty, | |
275 | fifo_B_full => sample_f0_B_full, |
|
275 | fifo_B_full => sample_f0_B_full, | |
276 | fifo_B_wen => sample_f0_B_wen, |
|
276 | fifo_B_wen => sample_f0_B_wen, | |
277 |
|
277 | |||
278 | error_wen => error_wen_f0); -- TODO |
|
278 | error_wen => error_wen_f0); -- TODO | |
279 |
|
279 | |||
280 | ----------------------------------------------------------------------------- |
|
280 | ----------------------------------------------------------------------------- | |
281 | -- FIFO IN |
|
281 | -- FIFO IN | |
282 | ----------------------------------------------------------------------------- |
|
282 | ----------------------------------------------------------------------------- | |
283 | lppFIFOxN_f0_a : lppFIFOxN |
|
283 | lppFIFOxN_f0_a : lppFIFOxN | |
284 | GENERIC MAP ( |
|
284 | GENERIC MAP ( | |
285 | tech => 0, |
|
285 | tech => 0, | |
286 | Mem_use => Mem_use, |
|
286 | Mem_use => Mem_use, | |
287 | Data_sz => 16, |
|
287 | Data_sz => 16, | |
288 | Addr_sz => 8, |
|
288 | Addr_sz => 8, | |
289 | FifoCnt => 5) |
|
289 | FifoCnt => 5) | |
290 | PORT MAP ( |
|
290 | PORT MAP ( | |
291 | clk => clk, |
|
291 | clk => clk, | |
292 | rstn => rstn, |
|
292 | rstn => rstn, | |
293 |
|
293 | |||
294 | ReUse => (OTHERS => '0'), |
|
294 | ReUse => (OTHERS => '0'), | |
295 |
|
295 | |||
296 | run => (OTHERS => '1'), |
|
296 | run => (OTHERS => '1'), | |
297 |
|
297 | |||
298 | wen => sample_f0_A_wen, |
|
298 | wen => sample_f0_A_wen, | |
299 | wdata => sample_f0_wdata, |
|
299 | wdata => sample_f0_wdata, | |
300 |
|
300 | |||
301 | ren => sample_f0_A_ren, |
|
301 | ren => sample_f0_A_ren, | |
302 | rdata => sample_f0_A_rdata, |
|
302 | rdata => sample_f0_A_rdata, | |
303 |
|
303 | |||
304 | empty => sample_f0_A_empty, |
|
304 | empty => sample_f0_A_empty, | |
305 | full => sample_f0_A_full, |
|
305 | full => sample_f0_A_full, | |
306 | almost_full => OPEN); |
|
306 | almost_full => OPEN); | |
307 |
|
307 | |||
308 | lppFIFOxN_f0_b : lppFIFOxN |
|
308 | lppFIFOxN_f0_b : lppFIFOxN | |
309 | GENERIC MAP ( |
|
309 | GENERIC MAP ( | |
310 | tech => 0, |
|
310 | tech => 0, | |
311 | Mem_use => Mem_use, |
|
311 | Mem_use => Mem_use, | |
312 | Data_sz => 16, |
|
312 | Data_sz => 16, | |
313 | Addr_sz => 8, |
|
313 | Addr_sz => 8, | |
314 | FifoCnt => 5) |
|
314 | FifoCnt => 5) | |
315 | PORT MAP ( |
|
315 | PORT MAP ( | |
316 | clk => clk, |
|
316 | clk => clk, | |
317 | rstn => rstn, |
|
317 | rstn => rstn, | |
318 |
|
318 | |||
319 | ReUse => (OTHERS => '0'), |
|
319 | ReUse => (OTHERS => '0'), | |
320 | run => (OTHERS => '1'), |
|
320 | run => (OTHERS => '1'), | |
321 |
|
321 | |||
322 | wen => sample_f0_B_wen, |
|
322 | wen => sample_f0_B_wen, | |
323 | wdata => sample_f0_wdata, |
|
323 | wdata => sample_f0_wdata, | |
324 | ren => sample_f0_B_ren, |
|
324 | ren => sample_f0_B_ren, | |
325 | rdata => sample_f0_B_rdata, |
|
325 | rdata => sample_f0_B_rdata, | |
326 | empty => sample_f0_B_empty, |
|
326 | empty => sample_f0_B_empty, | |
327 | full => sample_f0_B_full, |
|
327 | full => sample_f0_B_full, | |
328 | almost_full => OPEN); |
|
328 | almost_full => OPEN); | |
329 |
|
329 | |||
330 | ----------------------------------------------------------------------------- |
|
330 | ----------------------------------------------------------------------------- | |
331 | -- sample_f1_wen in |
|
331 | -- sample_f1_wen in | |
332 | -- sample_f1_wdata in |
|
332 | -- sample_f1_wdata in | |
333 | -- sample_f1_full OUT |
|
333 | -- sample_f1_full OUT | |
334 |
|
334 | |||
335 | sample_f1_wen_head_in <= '0' WHEN sample_f1_wen = "00000" ELSE '1'; |
|
335 | sample_f1_wen_head_in <= '0' WHEN sample_f1_wen = "00000" ELSE '1'; | |
336 | sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1'; |
|
336 | sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1'; | |
337 | sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; |
|
337 | sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; | |
338 |
|
338 | |||
339 | lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head |
|
339 | lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head | |
340 | PORT MAP ( |
|
340 | PORT MAP ( | |
341 | clk => clk, |
|
341 | clk => clk, | |
342 | rstn => rstn, |
|
342 | rstn => rstn, | |
343 | in_wen => sample_f1_wen_head_in, |
|
343 | in_wen => sample_f1_wen_head_in, | |
344 | in_data => sample_f1_wdata, |
|
344 | in_data => sample_f1_wdata, | |
345 | in_full => sample_f1_full_head_in, |
|
345 | in_full => sample_f1_full_head_in, | |
346 | in_empty => sample_f1_empty_head_in, |
|
346 | in_empty => sample_f1_empty_head_in, | |
347 | out_wen => sample_f1_wen_head_out, |
|
347 | out_wen => sample_f1_wen_head_out, | |
348 | out_data => sample_f1_wdata_head, |
|
348 | out_data => sample_f1_wdata_head, | |
349 | out_full => sample_f1_full_head_out); |
|
349 | out_full => sample_f1_full_head_out); | |
350 |
|
350 | |||
351 | sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out; |
|
351 | sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out; | |
352 |
|
352 | |||
353 |
|
353 | |||
354 | lppFIFOxN_f1 : lppFIFOxN |
|
354 | lppFIFOxN_f1 : lppFIFOxN | |
355 | GENERIC MAP ( |
|
355 | GENERIC MAP ( | |
356 | tech => 0, |
|
356 | tech => 0, | |
357 | Mem_use => Mem_use, |
|
357 | Mem_use => Mem_use, | |
358 | Data_sz => 16, |
|
358 | Data_sz => 16, | |
359 | Addr_sz => 8, |
|
359 | Addr_sz => 8, | |
360 | FifoCnt => 5) |
|
360 | FifoCnt => 5) | |
361 | PORT MAP ( |
|
361 | PORT MAP ( | |
362 | clk => clk, |
|
362 | clk => clk, | |
363 | rstn => rstn, |
|
363 | rstn => rstn, | |
364 |
|
364 | |||
365 | ReUse => (OTHERS => '0'), |
|
365 | ReUse => (OTHERS => '0'), | |
366 | run => (OTHERS => '1'), |
|
366 | run => (OTHERS => '1'), | |
367 |
|
367 | |||
368 | wen => sample_f1_wen_head, |
|
368 | wen => sample_f1_wen_head, | |
369 | wdata => sample_f1_wdata_head, |
|
369 | wdata => sample_f1_wdata_head, | |
370 | ren => sample_f1_ren, |
|
370 | ren => sample_f1_ren, | |
371 | rdata => sample_f1_rdata, |
|
371 | rdata => sample_f1_rdata, | |
372 | empty => sample_f1_empty, |
|
372 | empty => sample_f1_empty, | |
373 | full => sample_f1_full, |
|
373 | full => sample_f1_full, | |
374 | almost_full => sample_f1_almost_full); |
|
374 | almost_full => sample_f1_almost_full); | |
375 |
|
375 | |||
376 |
|
376 | |||
377 | one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1'; |
|
377 | one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1'; | |
378 |
|
378 | |||
379 | PROCESS (clk, rstn) |
|
379 | PROCESS (clk, rstn) | |
380 | BEGIN -- PROCESS |
|
380 | BEGIN -- PROCESS | |
381 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
381 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
382 | one_sample_f1_full <= '0'; |
|
382 | one_sample_f1_full <= '0'; | |
383 | error_wen_f1 <= '0'; |
|
383 | error_wen_f1 <= '0'; | |
384 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
384 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
385 | IF sample_f1_full_head_out = '0' THEN |
|
385 | IF sample_f1_full_head_out = '0' THEN | |
386 | one_sample_f1_full <= '0'; |
|
386 | one_sample_f1_full <= '0'; | |
387 | ELSE |
|
387 | ELSE | |
388 | one_sample_f1_full <= '1'; |
|
388 | one_sample_f1_full <= '1'; | |
389 | END IF; |
|
389 | END IF; | |
390 | error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full; |
|
390 | error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full; | |
391 | END IF; |
|
391 | END IF; | |
392 | END PROCESS; |
|
392 | END PROCESS; | |
393 |
|
393 | |||
394 | ----------------------------------------------------------------------------- |
|
394 | ----------------------------------------------------------------------------- | |
395 |
|
395 | |||
396 |
|
396 | |||
397 | lppFIFOxN_f2 : lppFIFOxN |
|
397 | lppFIFOxN_f2 : lppFIFOxN | |
398 | GENERIC MAP ( |
|
398 | GENERIC MAP ( | |
399 | tech => 0, |
|
399 | tech => 0, | |
400 | Mem_use => Mem_use, |
|
400 | Mem_use => Mem_use, | |
401 | Data_sz => 16, |
|
401 | Data_sz => 16, | |
402 | Addr_sz => 8, |
|
402 | Addr_sz => 8, | |
403 | FifoCnt => 5) |
|
403 | FifoCnt => 5) | |
404 | PORT MAP ( |
|
404 | PORT MAP ( | |
405 | clk => clk, |
|
405 | clk => clk, | |
406 | rstn => rstn, |
|
406 | rstn => rstn, | |
407 |
|
407 | |||
408 | ReUse => (OTHERS => '0'), |
|
408 | ReUse => (OTHERS => '0'), | |
409 | run => (OTHERS => '1'), |
|
409 | run => (OTHERS => '1'), | |
410 |
|
410 | |||
411 | wen => sample_f2_wen, |
|
411 | wen => sample_f2_wen, | |
412 | wdata => sample_f2_wdata, |
|
412 | wdata => sample_f2_wdata, | |
413 | ren => sample_f2_ren, |
|
413 | ren => sample_f2_ren, | |
414 | rdata => sample_f2_rdata, |
|
414 | rdata => sample_f2_rdata, | |
415 | empty => sample_f2_empty, |
|
415 | empty => sample_f2_empty, | |
416 | full => sample_f2_full, |
|
416 | full => sample_f2_full, | |
417 | almost_full => OPEN); |
|
417 | almost_full => OPEN); | |
418 |
|
418 | |||
419 |
|
419 | |||
420 | one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1'; |
|
420 | one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1'; | |
421 |
|
421 | |||
422 | PROCESS (clk, rstn) |
|
422 | PROCESS (clk, rstn) | |
423 | BEGIN -- PROCESS |
|
423 | BEGIN -- PROCESS | |
424 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
424 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
425 | one_sample_f2_full <= '0'; |
|
425 | one_sample_f2_full <= '0'; | |
426 | error_wen_f2 <= '0'; |
|
426 | error_wen_f2 <= '0'; | |
427 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
427 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
428 | IF sample_f2_full = "00000" THEN |
|
428 | IF sample_f2_full = "00000" THEN | |
429 | one_sample_f2_full <= '0'; |
|
429 | one_sample_f2_full <= '0'; | |
430 | ELSE |
|
430 | ELSE | |
431 | one_sample_f2_full <= '1'; |
|
431 | one_sample_f2_full <= '1'; | |
432 | END IF; |
|
432 | END IF; | |
433 | error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full; |
|
433 | error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full; | |
434 | END IF; |
|
434 | END IF; | |
435 | END PROCESS; |
|
435 | END PROCESS; | |
436 |
|
436 | |||
437 | ----------------------------------------------------------------------------- |
|
437 | ----------------------------------------------------------------------------- | |
438 | -- FSM SELECT CHANNEL |
|
438 | -- FSM SELECT CHANNEL | |
439 | ----------------------------------------------------------------------------- |
|
439 | ----------------------------------------------------------------------------- | |
440 | PROCESS (clk, rstn) |
|
440 | PROCESS (clk, rstn) | |
441 | BEGIN |
|
441 | BEGIN | |
442 | IF rstn = '0' THEN |
|
442 | IF rstn = '0' THEN | |
443 | state_fsm_select_channel <= IDLE; |
|
443 | state_fsm_select_channel <= IDLE; | |
444 | ELSIF clk'EVENT AND clk = '1' THEN |
|
444 | ELSIF clk'EVENT AND clk = '1' THEN | |
445 | CASE state_fsm_select_channel IS |
|
445 | CASE state_fsm_select_channel IS | |
446 | WHEN IDLE => |
|
446 | WHEN IDLE => | |
447 | IF sample_f1_full = "11111" THEN |
|
447 | IF sample_f1_full = "11111" THEN | |
448 | state_fsm_select_channel <= SWITCH_F1; |
|
448 | state_fsm_select_channel <= SWITCH_F1; | |
449 | ELSIF sample_f1_almost_full = "00000" THEN |
|
449 | ELSIF sample_f1_almost_full = "00000" THEN | |
450 | IF sample_f0_A_full = "11111" THEN |
|
450 | IF sample_f0_A_full = "11111" THEN | |
451 | state_fsm_select_channel <= SWITCH_F0_A; |
|
451 | state_fsm_select_channel <= SWITCH_F0_A; | |
452 | ELSIF sample_f0_B_full = "11111" THEN |
|
452 | ELSIF sample_f0_B_full = "11111" THEN | |
453 | state_fsm_select_channel <= SWITCH_F0_B; |
|
453 | state_fsm_select_channel <= SWITCH_F0_B; | |
454 | ELSIF sample_f2_full = "11111" THEN |
|
454 | ELSIF sample_f2_full = "11111" THEN | |
455 | state_fsm_select_channel <= SWITCH_F2; |
|
455 | state_fsm_select_channel <= SWITCH_F2; | |
456 | END IF; |
|
456 | END IF; | |
457 | END IF; |
|
457 | END IF; | |
458 |
|
458 | |||
459 | WHEN SWITCH_F0_A => |
|
459 | WHEN SWITCH_F0_A => | |
460 | IF sample_f0_A_empty = "11111" THEN |
|
460 | IF sample_f0_A_empty = "11111" THEN | |
461 | state_fsm_select_channel <= IDLE; |
|
461 | state_fsm_select_channel <= IDLE; | |
462 | END IF; |
|
462 | END IF; | |
463 | WHEN SWITCH_F0_B => |
|
463 | WHEN SWITCH_F0_B => | |
464 | IF sample_f0_B_empty = "11111" THEN |
|
464 | IF sample_f0_B_empty = "11111" THEN | |
465 | state_fsm_select_channel <= IDLE; |
|
465 | state_fsm_select_channel <= IDLE; | |
466 | END IF; |
|
466 | END IF; | |
467 | WHEN SWITCH_F1 => |
|
467 | WHEN SWITCH_F1 => | |
468 | IF sample_f1_empty = "11111" THEN |
|
468 | IF sample_f1_empty = "11111" THEN | |
469 | state_fsm_select_channel <= IDLE; |
|
469 | state_fsm_select_channel <= IDLE; | |
470 | END IF; |
|
470 | END IF; | |
471 | WHEN SWITCH_F2 => |
|
471 | WHEN SWITCH_F2 => | |
472 | IF sample_f2_empty = "11111" THEN |
|
472 | IF sample_f2_empty = "11111" THEN | |
473 | state_fsm_select_channel <= IDLE; |
|
473 | state_fsm_select_channel <= IDLE; | |
474 | END IF; |
|
474 | END IF; | |
475 | WHEN OTHERS => NULL; |
|
475 | WHEN OTHERS => NULL; | |
476 | END CASE; |
|
476 | END CASE; | |
477 |
|
477 | |||
478 | END IF; |
|
478 | END IF; | |
479 | END PROCESS; |
|
479 | END PROCESS; | |
480 |
|
480 | |||
481 | PROCESS (clk, rstn) |
|
481 | PROCESS (clk, rstn) | |
482 | BEGIN |
|
482 | BEGIN | |
483 | IF rstn = '0' THEN |
|
483 | IF rstn = '0' THEN | |
484 | pre_state_fsm_select_channel <= IDLE; |
|
484 | pre_state_fsm_select_channel <= IDLE; | |
485 | ELSIF clk'EVENT AND clk = '1' THEN |
|
485 | ELSIF clk'EVENT AND clk = '1' THEN | |
486 | pre_state_fsm_select_channel <= state_fsm_select_channel; |
|
486 | pre_state_fsm_select_channel <= state_fsm_select_channel; | |
487 | END IF; |
|
487 | END IF; | |
488 | END PROCESS; |
|
488 | END PROCESS; | |
489 |
|
489 | |||
490 |
|
490 | |||
491 | ----------------------------------------------------------------------------- |
|
491 | ----------------------------------------------------------------------------- | |
492 | -- SWITCH SELECT CHANNEL |
|
492 | -- SWITCH SELECT CHANNEL | |
493 | ----------------------------------------------------------------------------- |
|
493 | ----------------------------------------------------------------------------- | |
494 | sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
494 | sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE | |
495 | sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
495 | sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE | |
496 | sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
496 | sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE | |
497 | sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
497 | sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE | |
498 | (OTHERS => '1'); |
|
498 | (OTHERS => '1'); | |
499 |
|
499 | |||
500 | sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
500 | sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE | |
501 | sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
501 | sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE | |
502 | sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
502 | sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE | |
503 | sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
503 | sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE | |
504 | (OTHERS => '0'); |
|
504 | (OTHERS => '0'); | |
505 |
|
505 | |||
506 | sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE |
|
506 | sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE | |
507 | sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE |
|
507 | sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE | |
508 | sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE |
|
508 | sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE | |
509 | sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
509 | sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE | |
510 |
|
510 | |||
511 |
|
511 | |||
512 | sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1'); |
|
512 | sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1'); | |
513 | sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1'); |
|
513 | sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1'); | |
514 | sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1'); |
|
514 | sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1'); | |
515 | sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1'); |
|
515 | sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1'); | |
516 |
|
516 | |||
517 |
|
517 | |||
518 | status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
518 | status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE | |
519 | time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
519 | time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE | |
520 | time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
520 | time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE | |
521 | time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2 |
|
521 | time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2 | |
522 |
|
522 | |||
523 | ----------------------------------------------------------------------------- |
|
523 | ----------------------------------------------------------------------------- | |
524 | -- FSM LOAD FFT |
|
524 | -- FSM LOAD FFT | |
525 | ----------------------------------------------------------------------------- |
|
525 | ----------------------------------------------------------------------------- | |
526 |
|
526 | |||
527 | sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE |
|
527 | sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE | |
528 | sample_ren_s WHEN sample_load = '1' ELSE |
|
528 | sample_ren_s WHEN sample_load = '1' ELSE | |
529 | (OTHERS => '1'); |
|
529 | (OTHERS => '1'); | |
530 |
|
530 | |||
531 | PROCESS (clk, rstn) |
|
531 | PROCESS (clk, rstn) | |
532 | BEGIN |
|
532 | BEGIN | |
533 | IF rstn = '0' THEN |
|
533 | IF rstn = '0' THEN | |
534 | sample_ren_s <= (OTHERS => '1'); |
|
534 | sample_ren_s <= (OTHERS => '1'); | |
535 | state_fsm_load_FFT <= IDLE; |
|
535 | state_fsm_load_FFT <= IDLE; | |
536 | status_MS_input <= (OTHERS => '0'); |
|
536 | status_MS_input <= (OTHERS => '0'); | |
537 | --next_state_fsm_load_FFT <= IDLE; |
|
537 | --next_state_fsm_load_FFT <= IDLE; | |
538 | --sample_valid <= '0'; |
|
538 | --sample_valid <= '0'; | |
539 | ELSIF clk'EVENT AND clk = '1' THEN |
|
539 | ELSIF clk'EVENT AND clk = '1' THEN | |
540 | CASE state_fsm_load_FFT IS |
|
540 | CASE state_fsm_load_FFT IS | |
541 | WHEN IDLE => |
|
541 | WHEN IDLE => | |
542 | --sample_valid <= '0'; |
|
542 | --sample_valid <= '0'; | |
543 | sample_ren_s <= (OTHERS => '1'); |
|
543 | sample_ren_s <= (OTHERS => '1'); | |
544 | IF sample_full = "11111" AND sample_load = '1' THEN |
|
544 | IF sample_full = "11111" AND sample_load = '1' THEN | |
545 | state_fsm_load_FFT <= FIFO_1; |
|
545 | state_fsm_load_FFT <= FIFO_1; | |
546 | status_MS_input <= status_channel; |
|
546 | status_MS_input <= status_channel; | |
547 | END IF; |
|
547 | END IF; | |
548 |
|
548 | |||
549 | WHEN FIFO_1 => |
|
549 | WHEN FIFO_1 => | |
550 | sample_ren_s <= "1111" & NOT(sample_load); |
|
550 | sample_ren_s <= "1111" & NOT(sample_load); | |
551 | IF sample_empty(0) = '1' THEN |
|
551 | IF sample_empty(0) = '1' THEN | |
552 | sample_ren_s <= (OTHERS => '1'); |
|
552 | sample_ren_s <= (OTHERS => '1'); | |
553 | state_fsm_load_FFT <= FIFO_2; |
|
553 | state_fsm_load_FFT <= FIFO_2; | |
554 | END IF; |
|
554 | END IF; | |
555 |
|
555 | |||
556 | WHEN FIFO_2 => |
|
556 | WHEN FIFO_2 => | |
557 | sample_ren_s <= "111" & NOT(sample_load) & '1'; |
|
557 | sample_ren_s <= "111" & NOT(sample_load) & '1'; | |
558 | IF sample_empty(1) = '1' THEN |
|
558 | IF sample_empty(1) = '1' THEN | |
559 | sample_ren_s <= (OTHERS => '1'); |
|
559 | sample_ren_s <= (OTHERS => '1'); | |
560 | state_fsm_load_FFT <= FIFO_3; |
|
560 | state_fsm_load_FFT <= FIFO_3; | |
561 | END IF; |
|
561 | END IF; | |
562 |
|
562 | |||
563 | WHEN FIFO_3 => |
|
563 | WHEN FIFO_3 => | |
564 | sample_ren_s <= "11" & NOT(sample_load) & "11"; |
|
564 | sample_ren_s <= "11" & NOT(sample_load) & "11"; | |
565 | IF sample_empty(2) = '1' THEN |
|
565 | IF sample_empty(2) = '1' THEN | |
566 | sample_ren_s <= (OTHERS => '1'); |
|
566 | sample_ren_s <= (OTHERS => '1'); | |
567 | state_fsm_load_FFT <= FIFO_4; |
|
567 | state_fsm_load_FFT <= FIFO_4; | |
568 | END IF; |
|
568 | END IF; | |
569 |
|
569 | |||
570 | WHEN FIFO_4 => |
|
570 | WHEN FIFO_4 => | |
571 | sample_ren_s <= '1' & NOT(sample_load) & "111"; |
|
571 | sample_ren_s <= '1' & NOT(sample_load) & "111"; | |
572 | IF sample_empty(3) = '1' THEN |
|
572 | IF sample_empty(3) = '1' THEN | |
573 | sample_ren_s <= (OTHERS => '1'); |
|
573 | sample_ren_s <= (OTHERS => '1'); | |
574 | state_fsm_load_FFT <= FIFO_5; |
|
574 | state_fsm_load_FFT <= FIFO_5; | |
575 | END IF; |
|
575 | END IF; | |
576 |
|
576 | |||
577 | WHEN FIFO_5 => |
|
577 | WHEN FIFO_5 => | |
578 | sample_ren_s <= NOT(sample_load) & "1111"; |
|
578 | sample_ren_s <= NOT(sample_load) & "1111"; | |
579 | IF sample_empty(4) = '1' THEN |
|
579 | IF sample_empty(4) = '1' THEN | |
580 | sample_ren_s <= (OTHERS => '1'); |
|
580 | sample_ren_s <= (OTHERS => '1'); | |
581 | state_fsm_load_FFT <= IDLE; |
|
581 | state_fsm_load_FFT <= IDLE; | |
582 | END IF; |
|
582 | END IF; | |
583 | WHEN OTHERS => NULL; |
|
583 | WHEN OTHERS => NULL; | |
584 | END CASE; |
|
584 | END CASE; | |
585 | END IF; |
|
585 | END IF; | |
586 | END PROCESS; |
|
586 | END PROCESS; | |
587 |
|
587 | |||
588 | PROCESS (clk, rstn) |
|
588 | PROCESS (clk, rstn) | |
589 | BEGIN |
|
589 | BEGIN | |
590 | IF rstn = '0' THEN |
|
590 | IF rstn = '0' THEN | |
591 | sample_valid_r <= '0'; |
|
591 | sample_valid_r <= '0'; | |
592 | next_state_fsm_load_FFT <= IDLE; |
|
592 | next_state_fsm_load_FFT <= IDLE; | |
593 | ELSIF clk'EVENT AND clk = '1' THEN |
|
593 | ELSIF clk'EVENT AND clk = '1' THEN | |
594 | next_state_fsm_load_FFT <= state_fsm_load_FFT; |
|
594 | next_state_fsm_load_FFT <= state_fsm_load_FFT; | |
595 | IF sample_ren_s = "11111" THEN |
|
595 | IF sample_ren_s = "11111" THEN | |
596 | sample_valid_r <= '0'; |
|
596 | sample_valid_r <= '0'; | |
597 | ELSE |
|
597 | ELSE | |
598 | sample_valid_r <= '1'; |
|
598 | sample_valid_r <= '1'; | |
599 | END IF; |
|
599 | END IF; | |
600 | END IF; |
|
600 | END IF; | |
601 | END PROCESS; |
|
601 | END PROCESS; | |
602 |
|
602 | |||
603 | sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load; |
|
603 | sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load; | |
604 |
|
604 | |||
605 | sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE |
|
605 | sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE | |
606 | sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE |
|
606 | sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE | |
607 | sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE |
|
607 | sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE | |
608 | sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE |
|
608 | sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE | |
609 | sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE |
|
609 | sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE | |
610 |
|
610 | |||
611 | ----------------------------------------------------------------------------- |
|
611 | ----------------------------------------------------------------------------- | |
612 | -- FFT |
|
612 | -- FFT | |
613 | ----------------------------------------------------------------------------- |
|
613 | ----------------------------------------------------------------------------- | |
614 | lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT |
|
614 | lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT | |
615 | PORT MAP ( |
|
615 | PORT MAP ( | |
616 | clk => clk, |
|
616 | clk => clk, | |
617 | rstn => rstn, |
|
617 | rstn => rstn, | |
618 | sample_valid => sample_valid, |
|
618 | sample_valid => sample_valid, | |
619 | fft_read => fft_read, |
|
619 | fft_read => fft_read, | |
620 | sample_data => sample_data, |
|
620 | sample_data => sample_data, | |
621 | sample_load => sample_load, |
|
621 | sample_load => sample_load, | |
622 | fft_pong => fft_pong, |
|
622 | fft_pong => fft_pong, | |
623 | fft_data_im => fft_data_im, |
|
623 | fft_data_im => fft_data_im, | |
624 | fft_data_re => fft_data_re, |
|
624 | fft_data_re => fft_data_re, | |
625 | fft_data_valid => fft_data_valid, |
|
625 | fft_data_valid => fft_data_valid, | |
626 | fft_ready => fft_ready); |
|
626 | fft_ready => fft_ready); | |
627 |
|
627 | |||
628 | ----------------------------------------------------------------------------- |
|
628 | ----------------------------------------------------------------------------- | |
629 | fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready; |
|
629 | fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready; | |
630 | sample_load_rising_down <= sample_load_reg AND NOT sample_load; |
|
630 | sample_load_rising_down <= sample_load_reg AND NOT sample_load; | |
631 |
|
631 | |||
632 | PROCESS (clk, rstn) |
|
632 | PROCESS (clk, rstn) | |
633 | BEGIN |
|
633 | BEGIN | |
634 | IF rstn = '0' THEN |
|
634 | IF rstn = '0' THEN | |
635 | fft_ready_reg <= '0'; |
|
635 | fft_ready_reg <= '0'; | |
636 | sample_load_reg <= '0'; |
|
636 | sample_load_reg <= '0'; | |
637 |
|
637 | |||
638 | fft_ongoing_counter <= '0'; |
|
638 | fft_ongoing_counter <= '0'; | |
639 | ELSIF clk'event AND clk = '1' THEN |
|
639 | ELSIF clk'event AND clk = '1' THEN | |
640 | fft_ready_reg <= fft_ready; |
|
640 | fft_ready_reg <= fft_ready; | |
641 | sample_load_reg <= sample_load; |
|
641 | sample_load_reg <= sample_load; | |
642 |
|
642 | |||
643 | IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN |
|
643 | IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN | |
644 | fft_ongoing_counter <= '0'; |
|
644 | fft_ongoing_counter <= '0'; | |
645 |
|
645 | |||
646 | -- CASE fft_ongoing_counter IS |
|
646 | -- CASE fft_ongoing_counter IS | |
647 | -- WHEN "01" => fft_ongoing_counter <= "00"; |
|
647 | -- WHEN "01" => fft_ongoing_counter <= "00"; | |
648 | ---- WHEN "10" => fft_ongoing_counter <= "01"; |
|
648 | ---- WHEN "10" => fft_ongoing_counter <= "01"; | |
649 | -- WHEN OTHERS => NULL; |
|
649 | -- WHEN OTHERS => NULL; | |
650 | -- END CASE; |
|
650 | -- END CASE; | |
651 | ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN |
|
651 | ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN | |
652 | fft_ongoing_counter <= '1'; |
|
652 | fft_ongoing_counter <= '1'; | |
653 | -- CASE fft_ongoing_counter IS |
|
653 | -- CASE fft_ongoing_counter IS | |
654 | -- WHEN "00" => fft_ongoing_counter <= "01"; |
|
654 | -- WHEN "00" => fft_ongoing_counter <= "01"; | |
655 | ---- WHEN "01" => fft_ongoing_counter <= "10"; |
|
655 | ---- WHEN "01" => fft_ongoing_counter <= "10"; | |
656 | -- WHEN OTHERS => NULL; |
|
656 | -- WHEN OTHERS => NULL; | |
657 | -- END CASE; |
|
657 | -- END CASE; | |
658 | END IF; |
|
658 | END IF; | |
659 |
|
659 | |||
660 | END IF; |
|
660 | END IF; | |
661 | END PROCESS; |
|
661 | END PROCESS; | |
662 |
|
662 | |||
663 | ----------------------------------------------------------------------------- |
|
663 | ----------------------------------------------------------------------------- | |
664 | PROCESS (clk, rstn) |
|
664 | PROCESS (clk, rstn) | |
665 | BEGIN |
|
665 | BEGIN | |
666 | IF rstn = '0' THEN |
|
666 | IF rstn = '0' THEN | |
667 | state_fsm_load_MS_memory <= IDLE; |
|
667 | state_fsm_load_MS_memory <= IDLE; | |
668 | current_fifo_load <= "00001"; |
|
668 | current_fifo_load <= "00001"; | |
669 | ELSIF clk'EVENT AND clk = '1' THEN |
|
669 | ELSIF clk'EVENT AND clk = '1' THEN | |
670 | CASE state_fsm_load_MS_memory IS |
|
670 | CASE state_fsm_load_MS_memory IS | |
671 | WHEN IDLE => |
|
671 | WHEN IDLE => | |
672 | IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN |
|
672 | IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN | |
673 | state_fsm_load_MS_memory <= LOAD_FIFO; |
|
673 | state_fsm_load_MS_memory <= LOAD_FIFO; | |
674 | END IF; |
|
674 | END IF; | |
675 | WHEN LOAD_FIFO => |
|
675 | WHEN LOAD_FIFO => | |
676 | IF current_fifo_full = '1' THEN |
|
676 | IF current_fifo_full = '1' THEN | |
677 | state_fsm_load_MS_memory <= TRASH_FFT; |
|
677 | state_fsm_load_MS_memory <= TRASH_FFT; | |
678 | END IF; |
|
678 | END IF; | |
679 | WHEN TRASH_FFT => |
|
679 | WHEN TRASH_FFT => | |
680 | IF fft_ready = '0' THEN |
|
680 | IF fft_ready = '0' THEN | |
681 | state_fsm_load_MS_memory <= IDLE; |
|
681 | state_fsm_load_MS_memory <= IDLE; | |
682 | current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4); |
|
682 | current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4); | |
683 | END IF; |
|
683 | END IF; | |
684 | WHEN OTHERS => NULL; |
|
684 | WHEN OTHERS => NULL; | |
685 | END CASE; |
|
685 | END CASE; | |
686 |
|
686 | |||
687 | END IF; |
|
687 | END IF; | |
688 | END PROCESS; |
|
688 | END PROCESS; | |
689 |
|
689 | |||
690 | current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE |
|
690 | current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE | |
691 | MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE |
|
691 | MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE | |
692 | MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE |
|
692 | MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE | |
693 | MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE |
|
693 | MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE | |
694 | MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE |
|
694 | MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE | |
695 |
|
695 | |||
696 | current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE |
|
696 | current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE | |
697 | MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE |
|
697 | MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE | |
698 | MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE |
|
698 | MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE | |
699 | MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE |
|
699 | MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE | |
700 | MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE |
|
700 | MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE | |
701 |
|
701 | |||
702 | current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE |
|
702 | current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE | |
703 | MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE |
|
703 | MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE | |
704 | MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE |
|
704 | MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE | |
705 | MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE |
|
705 | MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE | |
706 | MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE |
|
706 | MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE | |
707 |
|
707 | |||
708 | fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1'; |
|
708 | fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1'; | |
709 |
|
709 | |||
710 | all_fifo : FOR I IN 4 DOWNTO 0 GENERATE |
|
710 | all_fifo : FOR I IN 4 DOWNTO 0 GENERATE | |
711 | MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1' |
|
711 | MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1' | |
712 | AND state_fsm_load_MS_memory = LOAD_FIFO |
|
712 | AND state_fsm_load_MS_memory = LOAD_FIFO | |
713 | AND current_fifo_load(I) = '1' |
|
713 | AND current_fifo_load(I) = '1' | |
714 | ELSE '1'; |
|
714 | ELSE '1'; | |
715 | END GENERATE all_fifo; |
|
715 | END GENERATE all_fifo; | |
716 |
|
716 | |||
717 | PROCESS (clk, rstn) |
|
717 | PROCESS (clk, rstn) | |
718 | BEGIN |
|
718 | BEGIN | |
719 | IF rstn = '0' THEN |
|
719 | IF rstn = '0' THEN | |
720 | MEM_IN_SM_wen <= (OTHERS => '1'); |
|
720 | MEM_IN_SM_wen <= (OTHERS => '1'); | |
721 | ELSIF clk'EVENT AND clk = '1' THEN |
|
721 | ELSIF clk'EVENT AND clk = '1' THEN | |
722 | MEM_IN_SM_wen <= MEM_IN_SM_wen_s; |
|
722 | MEM_IN_SM_wen <= MEM_IN_SM_wen_s; | |
723 | END IF; |
|
723 | END IF; | |
724 | END PROCESS; |
|
724 | END PROCESS; | |
725 |
|
725 | |||
726 | MEM_IN_SM_wData <= (fft_data_im & fft_data_re) & |
|
726 | MEM_IN_SM_wData <= (fft_data_im & fft_data_re) & | |
727 | (fft_data_im & fft_data_re) & |
|
727 | (fft_data_im & fft_data_re) & | |
728 | (fft_data_im & fft_data_re) & |
|
728 | (fft_data_im & fft_data_re) & | |
729 | (fft_data_im & fft_data_re) & |
|
729 | (fft_data_im & fft_data_re) & | |
730 | (fft_data_im & fft_data_re); |
|
730 | (fft_data_im & fft_data_re); | |
731 | ----------------------------------------------------------------------------- |
|
731 | ----------------------------------------------------------------------------- | |
732 |
|
732 | |||
733 |
|
733 | |||
734 | ----------------------------------------------------------------------------- |
|
734 | ----------------------------------------------------------------------------- | |
735 | Mem_In_SpectralMatrix : lppFIFOxN |
|
735 | Mem_In_SpectralMatrix : lppFIFOxN | |
736 | GENERIC MAP ( |
|
736 | GENERIC MAP ( | |
737 | tech => 0, |
|
737 | tech => 0, | |
738 | Mem_use => Mem_use, |
|
738 | Mem_use => Mem_use, | |
739 | Data_sz => 32, --16, |
|
739 | Data_sz => 32, --16, | |
740 | Addr_sz => 7, --8 |
|
740 | Addr_sz => 7, --8 | |
741 | FifoCnt => 5) |
|
741 | FifoCnt => 5) | |
742 | PORT MAP ( |
|
742 | PORT MAP ( | |
743 | clk => clk, |
|
743 | clk => clk, | |
744 | rstn => rstn, |
|
744 | rstn => rstn, | |
745 |
|
745 | |||
746 | ReUse => MEM_IN_SM_ReUse, |
|
746 | ReUse => MEM_IN_SM_ReUse, | |
747 | run => (OTHERS => '1'), |
|
747 | run => (OTHERS => '1'), | |
748 |
|
748 | |||
749 | wen => MEM_IN_SM_wen, |
|
749 | wen => MEM_IN_SM_wen, | |
750 | wdata => MEM_IN_SM_wData, |
|
750 | wdata => MEM_IN_SM_wData, | |
751 |
|
751 | |||
752 | ren => MEM_IN_SM_ren, |
|
752 | ren => MEM_IN_SM_ren, | |
753 | rdata => MEM_IN_SM_rData, |
|
753 | rdata => MEM_IN_SM_rData, | |
754 | full => MEM_IN_SM_Full, |
|
754 | full => MEM_IN_SM_Full, | |
755 | empty => MEM_IN_SM_Empty, |
|
755 | empty => MEM_IN_SM_Empty, | |
756 | almost_full => OPEN); |
|
756 | almost_full => OPEN); | |
757 |
|
757 | |||
758 |
|
758 | |||
759 | ----------------------------------------------------------------------------- |
|
759 | ----------------------------------------------------------------------------- | |
760 | MS_control_1 : MS_control |
|
760 | MS_control_1 : MS_control | |
761 | PORT MAP ( |
|
761 | PORT MAP ( | |
762 | clk => clk, |
|
762 | clk => clk, | |
763 | rstn => rstn, |
|
763 | rstn => rstn, | |
764 |
|
764 | |||
765 | current_status_ms => status_MS_input, |
|
765 | current_status_ms => status_MS_input, | |
766 |
|
766 | |||
767 | fifo_in_lock => MEM_IN_SM_locked, |
|
767 | fifo_in_lock => MEM_IN_SM_locked, | |
768 | fifo_in_data => MEM_IN_SM_rdata, |
|
768 | fifo_in_data => MEM_IN_SM_rdata, | |
769 | fifo_in_full => MEM_IN_SM_Full, |
|
769 | fifo_in_full => MEM_IN_SM_Full, | |
770 | fifo_in_empty => MEM_IN_SM_Empty, |
|
770 | fifo_in_empty => MEM_IN_SM_Empty, | |
771 | fifo_in_ren => MEM_IN_SM_ren, |
|
771 | fifo_in_ren => MEM_IN_SM_ren, | |
772 | fifo_in_reuse => MEM_IN_SM_ReUse, |
|
772 | fifo_in_reuse => MEM_IN_SM_ReUse, | |
773 |
|
773 | |||
774 | fifo_out_data => SM_in_data, |
|
774 | fifo_out_data => SM_in_data, | |
775 | fifo_out_ren => SM_in_ren, |
|
775 | fifo_out_ren => SM_in_ren, | |
776 | fifo_out_empty => SM_in_empty, |
|
776 | fifo_out_empty => SM_in_empty, | |
777 |
|
777 | |||
778 | current_status_component => status_component, |
|
778 | current_status_component => status_component, | |
779 |
|
779 | |||
780 | correlation_start => SM_correlation_start, |
|
780 | correlation_start => SM_correlation_start, | |
781 | correlation_auto => SM_correlation_auto, |
|
781 | correlation_auto => SM_correlation_auto, | |
782 | correlation_done => SM_correlation_done); |
|
782 | correlation_done => SM_correlation_done); | |
783 |
|
783 | |||
784 |
|
784 | |||
785 | MS_calculation_1 : MS_calculation |
|
785 | MS_calculation_1 : MS_calculation | |
786 | PORT MAP ( |
|
786 | PORT MAP ( | |
787 | clk => clk, |
|
787 | clk => clk, | |
788 | rstn => rstn, |
|
788 | rstn => rstn, | |
789 |
|
789 | |||
790 | fifo_in_data => SM_in_data, |
|
790 | fifo_in_data => SM_in_data, | |
791 | fifo_in_ren => SM_in_ren, |
|
791 | fifo_in_ren => SM_in_ren, | |
792 | fifo_in_empty => SM_in_empty, |
|
792 | fifo_in_empty => SM_in_empty, | |
793 |
|
793 | |||
794 | fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO |
|
794 | fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO | |
795 | fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO |
|
795 | fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO | |
796 | fifo_out_full => MEM_OUT_SM_Full_s, -- TODO |
|
796 | fifo_out_full => MEM_OUT_SM_Full_s, -- TODO | |
797 |
|
797 | |||
798 | correlation_start => SM_correlation_start, |
|
798 | correlation_start => SM_correlation_start, | |
799 | correlation_auto => SM_correlation_auto, |
|
799 | correlation_auto => SM_correlation_auto, | |
800 | correlation_begin => SM_correlation_begin, |
|
800 | correlation_begin => SM_correlation_begin, | |
801 | correlation_done => SM_correlation_done); |
|
801 | correlation_done => SM_correlation_done); | |
802 |
|
802 | |||
803 | ----------------------------------------------------------------------------- |
|
803 | ----------------------------------------------------------------------------- | |
804 | PROCESS (clk, rstn) |
|
804 | PROCESS (clk, rstn) | |
805 | BEGIN -- PROCESS |
|
805 | BEGIN -- PROCESS | |
806 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
806 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
807 | current_matrix_write <= '0'; |
|
807 | current_matrix_write <= '0'; | |
808 | current_matrix_wait_empty <= '1'; |
|
808 | current_matrix_wait_empty <= '1'; | |
809 | status_component_fifo_0 <= (OTHERS => '0'); |
|
809 | status_component_fifo_0 <= (OTHERS => '0'); | |
810 | status_component_fifo_1 <= (OTHERS => '0'); |
|
810 | status_component_fifo_1 <= (OTHERS => '0'); | |
811 | status_component_fifo_0_end <= '0'; |
|
811 | status_component_fifo_0_end <= '0'; | |
812 | status_component_fifo_1_end <= '0'; |
|
812 | status_component_fifo_1_end <= '0'; | |
813 | SM_correlation_done_reg1 <= '0'; |
|
813 | SM_correlation_done_reg1 <= '0'; | |
814 | SM_correlation_done_reg2 <= '0'; |
|
814 | SM_correlation_done_reg2 <= '0'; | |
815 | SM_correlation_done_reg3 <= '0'; |
|
815 | SM_correlation_done_reg3 <= '0'; | |
816 |
|
816 | |||
817 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
817 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
818 | SM_correlation_done_reg1 <= SM_correlation_done; |
|
818 | SM_correlation_done_reg1 <= SM_correlation_done; | |
819 | SM_correlation_done_reg2 <= SM_correlation_done_reg1; |
|
819 | SM_correlation_done_reg2 <= SM_correlation_done_reg1; | |
820 | SM_correlation_done_reg3 <= SM_correlation_done_reg2; |
|
820 | SM_correlation_done_reg3 <= SM_correlation_done_reg2; | |
821 | status_component_fifo_0_end <= '0'; |
|
821 | status_component_fifo_0_end <= '0'; | |
822 | status_component_fifo_1_end <= '0'; |
|
822 | status_component_fifo_1_end <= '0'; | |
823 | IF SM_correlation_begin = '1' THEN |
|
823 | IF SM_correlation_begin = '1' THEN | |
824 | IF current_matrix_write = '0' THEN |
|
824 | IF current_matrix_write = '0' THEN | |
825 | status_component_fifo_0 <= status_component; |
|
825 | status_component_fifo_0 <= status_component; | |
826 | ELSE |
|
826 | ELSE | |
827 | status_component_fifo_1 <= status_component; |
|
827 | status_component_fifo_1 <= status_component; | |
828 | END IF; |
|
828 | END IF; | |
829 | END IF; |
|
829 | END IF; | |
830 |
|
830 | |||
831 | IF SM_correlation_done_reg3 = '1' THEN |
|
831 | IF SM_correlation_done_reg3 = '1' THEN | |
832 | IF current_matrix_write = '0' THEN |
|
832 | IF current_matrix_write = '0' THEN | |
833 | status_component_fifo_0_end <= '1'; |
|
833 | status_component_fifo_0_end <= '1'; | |
834 | ELSE |
|
834 | ELSE | |
835 | status_component_fifo_1_end <= '1'; |
|
835 | status_component_fifo_1_end <= '1'; | |
836 | END IF; |
|
836 | END IF; | |
837 | current_matrix_wait_empty <= '1'; |
|
837 | current_matrix_wait_empty <= '1'; | |
838 | current_matrix_write <= NOT current_matrix_write; |
|
838 | current_matrix_write <= NOT current_matrix_write; | |
839 | END IF; |
|
839 | END IF; | |
840 |
|
840 | |||
841 | IF current_matrix_wait_empty <= '1' THEN |
|
841 | IF current_matrix_wait_empty <= '1' THEN | |
842 | IF current_matrix_write = '0' THEN |
|
842 | IF current_matrix_write = '0' THEN | |
843 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0); |
|
843 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0); | |
844 | ELSE |
|
844 | ELSE | |
845 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1); |
|
845 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1); | |
846 | END IF; |
|
846 | END IF; | |
847 | END IF; |
|
847 | END IF; | |
848 |
|
848 | |||
849 | END IF; |
|
849 | END IF; | |
850 | END PROCESS; |
|
850 | END PROCESS; | |
851 |
|
851 | |||
852 | MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE |
|
852 | MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE | |
853 | '1' WHEN SM_correlation_done_reg1 = '1' ELSE |
|
853 | '1' WHEN SM_correlation_done_reg1 = '1' ELSE | |
854 | '1' WHEN SM_correlation_done_reg2 = '1' ELSE |
|
854 | '1' WHEN SM_correlation_done_reg2 = '1' ELSE | |
855 | '1' WHEN SM_correlation_done_reg3 = '1' ELSE |
|
855 | '1' WHEN SM_correlation_done_reg3 = '1' ELSE | |
856 | '1' WHEN current_matrix_wait_empty = '1' ELSE |
|
856 | '1' WHEN current_matrix_wait_empty = '1' ELSE | |
857 | MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE |
|
857 | MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE | |
858 | MEM_OUT_SM_Full(1); |
|
858 | MEM_OUT_SM_Full(1); | |
859 |
|
859 | |||
860 | MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1'; |
|
860 | MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1'; | |
861 | MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1'; |
|
861 | MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1'; | |
862 |
|
862 | |||
863 | MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s; |
|
863 | MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s; | |
864 | ----------------------------------------------------------------------------- |
|
864 | ----------------------------------------------------------------------------- | |
865 |
|
865 | |||
866 | --Mem_Out_SpectralMatrix : lppFIFOxN |
|
866 | --Mem_Out_SpectralMatrix : lppFIFOxN | |
867 | -- GENERIC MAP ( |
|
867 | -- GENERIC MAP ( | |
868 | -- tech => 0, |
|
868 | -- tech => 0, | |
869 | -- Mem_use => Mem_use, |
|
869 | -- Mem_use => Mem_use, | |
870 | -- Data_sz => 32, |
|
870 | -- Data_sz => 32, | |
871 | -- Addr_sz => 8, |
|
871 | -- Addr_sz => 8, | |
872 | -- FifoCnt => 2) |
|
872 | -- FifoCnt => 2) | |
873 | -- PORT MAP ( |
|
873 | -- PORT MAP ( | |
874 | -- clk => clk, |
|
874 | -- clk => clk, | |
875 | -- rstn => rstn, |
|
875 | -- rstn => rstn, | |
876 |
|
876 | |||
877 | -- ReUse => (OTHERS => '0'), |
|
877 | -- ReUse => (OTHERS => '0'), | |
878 | -- run => (OTHERS => '1'), |
|
878 | -- run => (OTHERS => '1'), | |
879 |
|
879 | |||
880 | -- wen => MEM_OUT_SM_Write, |
|
880 | -- wen => MEM_OUT_SM_Write, | |
881 | -- wdata => MEM_OUT_SM_Data_in, |
|
881 | -- wdata => MEM_OUT_SM_Data_in, | |
882 |
|
882 | |||
883 | -- ren => MEM_OUT_SM_Read, |
|
883 | -- ren => MEM_OUT_SM_Read, | |
884 | -- rdata => MEM_OUT_SM_Data_out, |
|
884 | -- rdata => MEM_OUT_SM_Data_out, | |
885 |
|
885 | |||
886 | -- full => MEM_OUT_SM_Full, |
|
886 | -- full => MEM_OUT_SM_Full, | |
887 | -- empty => MEM_OUT_SM_Empty, |
|
887 | -- empty => MEM_OUT_SM_Empty, | |
888 | -- almost_full => OPEN); |
|
888 | -- almost_full => OPEN); | |
889 |
|
889 | |||
890 |
|
890 | |||
891 | all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE |
|
891 | all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE | |
892 | Mem_Out_SpectralMatrix_I: lpp_fifo |
|
892 | Mem_Out_SpectralMatrix_I: lpp_fifo | |
893 | GENERIC MAP ( |
|
893 | GENERIC MAP ( | |
894 | tech => 0, |
|
894 | tech => 0, | |
895 | Mem_use => Mem_use, |
|
895 | Mem_use => Mem_use, | |
896 | EMPTY_THRESHOLD_LIMIT => 15, |
|
896 | EMPTY_THRESHOLD_LIMIT => 15, | |
897 | FULL_THRESHOLD_LIMIT => 1, |
|
897 | FULL_THRESHOLD_LIMIT => 1, | |
898 | DataSz => 32, |
|
898 | DataSz => 32, | |
899 | AddrSz => 8) |
|
899 | AddrSz => 8) | |
900 | PORT MAP ( |
|
900 | PORT MAP ( | |
901 | clk => clk, |
|
901 | clk => clk, | |
902 | rstn => rstn, |
|
902 | rstn => rstn, | |
903 | reUse => '0', |
|
903 | reUse => '0', | |
904 | run => run, |
|
904 | run => run, | |
905 |
|
905 | |||
906 | ren => MEM_OUT_SM_Read(I), |
|
906 | ren => MEM_OUT_SM_Read(I), | |
907 | rdata => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i), |
|
907 | rdata => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i), | |
908 |
|
908 | |||
909 | wen => MEM_OUT_SM_Write(I), |
|
909 | wen => MEM_OUT_SM_Write(I), | |
910 | wdata => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i), |
|
910 | wdata => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i), | |
911 |
|
911 | |||
912 | empty => MEM_OUT_SM_Empty(I), |
|
912 | empty => MEM_OUT_SM_Empty(I), | |
913 | full => MEM_OUT_SM_Full(I), |
|
913 | full => MEM_OUT_SM_Full(I), | |
914 | full_almost => OPEN, |
|
914 | full_almost => OPEN, | |
915 | empty_threshold => MEM_OUT_SM_Empty_Threshold(I), |
|
915 | empty_threshold => MEM_OUT_SM_Empty_Threshold(I), | |
916 |
|
916 | |||
917 | full_threshold => OPEN); |
|
917 | full_threshold => OPEN); | |
918 |
|
918 | |||
919 | END GENERATE all_Mem_Out_SpectralMatrix; |
|
919 | END GENERATE all_Mem_Out_SpectralMatrix; | |
920 |
|
920 | |||
921 | ----------------------------------------------------------------------------- |
|
921 | ----------------------------------------------------------------------------- | |
922 | -- MEM_OUT_SM_Read <= "00"; |
|
922 | -- MEM_OUT_SM_Read <= "00"; | |
923 | PROCESS (clk, rstn) |
|
923 | PROCESS (clk, rstn) | |
924 | BEGIN |
|
924 | BEGIN | |
925 | IF rstn = '0' THEN |
|
925 | IF rstn = '0' THEN | |
926 | fifo_0_ready <= '0'; |
|
926 | fifo_0_ready <= '0'; | |
927 | fifo_1_ready <= '0'; |
|
927 | fifo_1_ready <= '0'; | |
928 | fifo_ongoing <= '0'; |
|
928 | fifo_ongoing <= '0'; | |
929 | ELSIF clk'EVENT AND clk = '1' THEN |
|
929 | ELSIF clk'EVENT AND clk = '1' THEN | |
930 | IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN |
|
930 | IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN | |
931 | fifo_ongoing <= '1'; |
|
931 | fifo_ongoing <= '1'; | |
932 | fifo_0_ready <= '0'; |
|
932 | fifo_0_ready <= '0'; | |
933 | ELSIF status_component_fifo_0_end = '1' THEN |
|
933 | ELSIF status_component_fifo_0_end = '1' THEN | |
934 | fifo_0_ready <= '1'; |
|
934 | fifo_0_ready <= '1'; | |
935 | END IF; |
|
935 | END IF; | |
936 |
|
936 | |||
937 | IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN |
|
937 | IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN | |
938 | fifo_ongoing <= '0'; |
|
938 | fifo_ongoing <= '0'; | |
939 | fifo_1_ready <= '0'; |
|
939 | fifo_1_ready <= '0'; | |
940 | ELSIF status_component_fifo_1_end = '1' THEN |
|
940 | ELSIF status_component_fifo_1_end = '1' THEN | |
941 | fifo_1_ready <= '1'; |
|
941 | fifo_1_ready <= '1'; | |
942 | END IF; |
|
942 | END IF; | |
943 |
|
943 | |||
944 | END IF; |
|
944 | END IF; | |
945 | END PROCESS; |
|
945 | END PROCESS; | |
946 |
|
946 | |||
947 | MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE |
|
947 | MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE | |
948 | '1' WHEN fifo_0_ready = '0' ELSE |
|
948 | '1' WHEN fifo_0_ready = '0' ELSE | |
949 | FSM_DMA_fifo_ren; |
|
949 | FSM_DMA_fifo_ren; | |
950 |
|
950 | |||
951 | MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE |
|
951 | MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE | |
952 | '1' WHEN fifo_1_ready = '0' ELSE |
|
952 | '1' WHEN fifo_1_ready = '0' ELSE | |
953 | FSM_DMA_fifo_ren; |
|
953 | FSM_DMA_fifo_ren; | |
954 |
|
954 | |||
955 | FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE |
|
955 | FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE | |
956 | MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE |
|
956 | MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE | |
957 | '1'; |
|
957 | '1'; | |
958 |
|
958 | |||
959 | FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE |
|
959 | FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE | |
960 | status_component_fifo_1; |
|
960 | status_component_fifo_1; | |
961 |
|
961 | |||
962 | FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE |
|
962 | FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE | |
963 | MEM_OUT_SM_Data_out(63 DOWNTO 32); |
|
963 | MEM_OUT_SM_Data_out(63 DOWNTO 32); | |
964 |
|
964 | |||
965 |
|
965 | |||
966 | FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE |
|
966 | FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE | |
967 | MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE |
|
967 | MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE | |
968 |
|
|
968 | '1'; | |
969 |
|
969 | |||
970 | ----------------------------------------------------------------------------- |
|
970 | ----------------------------------------------------------------------------- | |
971 | -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --IN |
|
971 | -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --IN | |
972 | -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), --IN |
|
972 | -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), --IN | |
973 | -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), --IN |
|
973 | -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), --IN | |
974 | -- fifo_data => FSM_DMA_fifo_data, --IN |
|
974 | -- fifo_data => FSM_DMA_fifo_data, --IN | |
975 | -- fifo_empty => FSM_DMA_fifo_empty, --IN |
|
975 | -- fifo_empty => FSM_DMA_fifo_empty, --IN | |
976 | -- fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, --IN |
|
976 | -- fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, --IN | |
977 | -- fifo_ren => FSM_DMA_fifo_ren, --OUT |
|
977 | -- fifo_ren => FSM_DMA_fifo_ren, --OUT | |
978 |
|
978 | |||
979 |
|
979 | |||
980 | lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma |
|
980 | lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma | |
981 | PORT MAP ( |
|
981 | PORT MAP ( | |
982 | clk => clk, |
|
982 | clk => clk, | |
983 | rstn => rstn, |
|
983 | rstn => rstn, | |
984 | run => run, |
|
984 | run => run, | |
985 |
|
985 | |||
986 | fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), |
|
986 | fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), | |
987 | fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), |
|
987 | fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), | |
988 | fifo_data => FSM_DMA_fifo_data, |
|
988 | fifo_data => FSM_DMA_fifo_data, | |
989 | fifo_empty => FSM_DMA_fifo_empty, |
|
989 | fifo_empty => FSM_DMA_fifo_empty, | |
990 | fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, |
|
990 | fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, | |
991 | fifo_ren => FSM_DMA_fifo_ren, |
|
991 | fifo_ren => FSM_DMA_fifo_ren, | |
992 |
|
992 | |||
993 | dma_fifo_valid_burst => dma_fifo_burst_valid, |
|
993 | dma_fifo_valid_burst => dma_fifo_burst_valid, | |
994 | dma_fifo_data => dma_fifo_data, |
|
994 | dma_fifo_data => dma_fifo_data, | |
995 | dma_fifo_ren => dma_fifo_ren, |
|
995 | dma_fifo_ren => dma_fifo_ren, | |
996 | dma_buffer_new => dma_buffer_new, |
|
996 | dma_buffer_new => dma_buffer_new, | |
997 | dma_buffer_addr => dma_buffer_addr, |
|
997 | dma_buffer_addr => dma_buffer_addr, | |
998 | dma_buffer_length => dma_buffer_length, |
|
998 | dma_buffer_length => dma_buffer_length, | |
999 | dma_buffer_full => dma_buffer_full, |
|
999 | dma_buffer_full => dma_buffer_full, | |
1000 | dma_buffer_full_err => dma_buffer_full_err, |
|
1000 | dma_buffer_full_err => dma_buffer_full_err, | |
1001 |
|
1001 | |||
1002 | status_ready_matrix_f0 => status_ready_matrix_f0, |
|
1002 | status_ready_matrix_f0 => status_ready_matrix_f0, | |
1003 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
1003 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
1004 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
1004 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
1005 | addr_matrix_f0 => addr_matrix_f0, |
|
1005 | addr_matrix_f0 => addr_matrix_f0, | |
1006 | addr_matrix_f1 => addr_matrix_f1, |
|
1006 | addr_matrix_f1 => addr_matrix_f1, | |
1007 | addr_matrix_f2 => addr_matrix_f2, |
|
1007 | addr_matrix_f2 => addr_matrix_f2, | |
1008 | length_matrix_f0 => length_matrix_f0, |
|
1008 | length_matrix_f0 => length_matrix_f0, | |
1009 | length_matrix_f1 => length_matrix_f1, |
|
1009 | length_matrix_f1 => length_matrix_f1, | |
1010 | length_matrix_f2 => length_matrix_f2, |
|
1010 | length_matrix_f2 => length_matrix_f2, | |
1011 | ready_matrix_f0 => ready_matrix_f0, |
|
1011 | ready_matrix_f0 => ready_matrix_f0, | |
1012 | ready_matrix_f1 => ready_matrix_f1, |
|
1012 | ready_matrix_f1 => ready_matrix_f1, | |
1013 | ready_matrix_f2 => ready_matrix_f2, |
|
1013 | ready_matrix_f2 => ready_matrix_f2, | |
1014 | matrix_time_f0 => matrix_time_f0, |
|
1014 | matrix_time_f0 => matrix_time_f0, | |
1015 | matrix_time_f1 => matrix_time_f1, |
|
1015 | matrix_time_f1 => matrix_time_f1, | |
1016 | matrix_time_f2 => matrix_time_f2, |
|
1016 | matrix_time_f2 => matrix_time_f2, | |
1017 | error_buffer_full => error_buffer_full); |
|
1017 | error_buffer_full => error_buffer_full); | |
1018 |
|
1018 | |||
1019 |
|
1019 | |||
1020 |
|
1020 | |||
1021 |
|
1021 | |||
1022 |
|
1022 | |||
1023 | --dma_fifo_burst_valid: OUT STD_LOGIC; --TODO |
|
1023 | --dma_fifo_burst_valid: OUT STD_LOGIC; --TODO | |
1024 | --dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO |
|
1024 | --dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO | |
1025 | --dma_fifo_ren : IN STD_LOGIC; --TODO |
|
1025 | --dma_fifo_ren : IN STD_LOGIC; --TODO | |
1026 | --dma_buffer_new : OUT STD_LOGIC; --TODO |
|
1026 | --dma_buffer_new : OUT STD_LOGIC; --TODO | |
1027 | --dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO |
|
1027 | --dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO | |
1028 | --dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO |
|
1028 | --dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO | |
1029 | --dma_buffer_full : IN STD_LOGIC; --TODO |
|
1029 | --dma_buffer_full : IN STD_LOGIC; --TODO | |
1030 | --dma_buffer_full_err : IN STD_LOGIC; --TODO |
|
1030 | --dma_buffer_full_err : IN STD_LOGIC; --TODO | |
1031 |
|
1031 | |||
1032 | ---- Reg out |
|
1032 | ---- Reg out | |
1033 | --ready_matrix_f0 : OUT STD_LOGIC; -- TODO |
|
1033 | --ready_matrix_f0 : OUT STD_LOGIC; -- TODO | |
1034 | --ready_matrix_f1 : OUT STD_LOGIC; -- TODO |
|
1034 | --ready_matrix_f1 : OUT STD_LOGIC; -- TODO | |
1035 | --ready_matrix_f2 : OUT STD_LOGIC; -- TODO |
|
1035 | --ready_matrix_f2 : OUT STD_LOGIC; -- TODO | |
1036 | --error_bad_component_error : OUT STD_LOGIC; -- TODO |
|
1036 | --error_bad_component_error : OUT STD_LOGIC; -- TODO | |
1037 | --error_buffer_full : OUT STD_LOGIC; -- TODO |
|
1037 | --error_buffer_full : OUT STD_LOGIC; -- TODO | |
1038 |
|
1038 | |||
1039 | ---- Reg In |
|
1039 | ---- Reg In | |
1040 | --status_ready_matrix_f0 : IN STD_LOGIC; -- TODO |
|
1040 | --status_ready_matrix_f0 : IN STD_LOGIC; -- TODO | |
1041 | --status_ready_matrix_f1 : IN STD_LOGIC; -- TODO |
|
1041 | --status_ready_matrix_f1 : IN STD_LOGIC; -- TODO | |
1042 | --status_ready_matrix_f2 : IN STD_LOGIC; -- TODO |
|
1042 | --status_ready_matrix_f2 : IN STD_LOGIC; -- TODO | |
1043 |
|
1043 | |||
1044 | --addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO |
|
1044 | --addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO | |
1045 | --addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO |
|
1045 | --addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO | |
1046 | --addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO |
|
1046 | --addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO | |
1047 |
|
1047 | |||
1048 | --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO |
|
1048 | --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO | |
1049 | --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO |
|
1049 | --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO | |
1050 | --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO |
|
1050 | --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO | |
1051 | ----------------------------------------------------------------------------- |
|
1051 | ----------------------------------------------------------------------------- | |
1052 |
|
1052 | |||
1053 | ----------------------------------------------------------------------------- |
|
1053 | ----------------------------------------------------------------------------- | |
1054 | --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma |
|
1054 | --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma | |
1055 | -- PORT MAP ( |
|
1055 | -- PORT MAP ( | |
1056 | -- HCLK => clk, |
|
1056 | -- HCLK => clk, | |
1057 | -- HRESETn => rstn, |
|
1057 | -- HRESETn => rstn, | |
1058 |
|
1058 | |||
1059 | -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), |
|
1059 | -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), | |
1060 | -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), |
|
1060 | -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), | |
1061 | -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), |
|
1061 | -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), | |
1062 | -- fifo_data => FSM_DMA_fifo_data, |
|
1062 | -- fifo_data => FSM_DMA_fifo_data, | |
1063 | -- fifo_empty => FSM_DMA_fifo_empty, |
|
1063 | -- fifo_empty => FSM_DMA_fifo_empty, | |
1064 | -- fifo_ren => FSM_DMA_fifo_ren, |
|
1064 | -- fifo_ren => FSM_DMA_fifo_ren, | |
1065 |
|
1065 | |||
1066 | -- dma_addr => dma_addr, |
|
1066 | -- dma_addr => dma_addr, | |
1067 | -- dma_data => dma_data, |
|
1067 | -- dma_data => dma_data, | |
1068 | -- dma_valid => dma_valid, |
|
1068 | -- dma_valid => dma_valid, | |
1069 | -- dma_valid_burst => dma_valid_burst, |
|
1069 | -- dma_valid_burst => dma_valid_burst, | |
1070 | -- dma_ren => dma_ren, |
|
1070 | -- dma_ren => dma_ren, | |
1071 | -- dma_done => dma_done, |
|
1071 | -- dma_done => dma_done, | |
1072 |
|
1072 | |||
1073 | -- ready_matrix_f0 => ready_matrix_f0, |
|
1073 | -- ready_matrix_f0 => ready_matrix_f0, | |
1074 | -- ready_matrix_f1 => ready_matrix_f1, |
|
1074 | -- ready_matrix_f1 => ready_matrix_f1, | |
1075 | -- ready_matrix_f2 => ready_matrix_f2, |
|
1075 | -- ready_matrix_f2 => ready_matrix_f2, | |
1076 |
|
1076 | |||
1077 | -- error_bad_component_error => error_bad_component_error, |
|
1077 | -- error_bad_component_error => error_bad_component_error, | |
1078 | -- error_buffer_full => error_buffer_full, |
|
1078 | -- error_buffer_full => error_buffer_full, | |
1079 |
|
1079 | |||
1080 | -- debug_reg => debug_reg, |
|
1080 | -- debug_reg => debug_reg, | |
1081 | -- status_ready_matrix_f0 => status_ready_matrix_f0, |
|
1081 | -- status_ready_matrix_f0 => status_ready_matrix_f0, | |
1082 | -- status_ready_matrix_f1 => status_ready_matrix_f1, |
|
1082 | -- status_ready_matrix_f1 => status_ready_matrix_f1, | |
1083 | -- status_ready_matrix_f2 => status_ready_matrix_f2, |
|
1083 | -- status_ready_matrix_f2 => status_ready_matrix_f2, | |
1084 |
|
1084 | |||
1085 | -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
1085 | -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
1086 | -- config_active_interruption_onError => config_active_interruption_onError, |
|
1086 | -- config_active_interruption_onError => config_active_interruption_onError, | |
1087 |
|
1087 | |||
1088 | -- addr_matrix_f0 => addr_matrix_f0, |
|
1088 | -- addr_matrix_f0 => addr_matrix_f0, | |
1089 | -- addr_matrix_f1 => addr_matrix_f1, |
|
1089 | -- addr_matrix_f1 => addr_matrix_f1, | |
1090 | -- addr_matrix_f2 => addr_matrix_f2, |
|
1090 | -- addr_matrix_f2 => addr_matrix_f2, | |
1091 |
|
1091 | |||
1092 | -- matrix_time_f0 => matrix_time_f0, |
|
1092 | -- matrix_time_f0 => matrix_time_f0, | |
1093 | -- matrix_time_f1 => matrix_time_f1, |
|
1093 | -- matrix_time_f1 => matrix_time_f1, | |
1094 | -- matrix_time_f2 => matrix_time_f2 |
|
1094 | -- matrix_time_f2 => matrix_time_f2 | |
1095 | -- ); |
|
1095 | -- ); | |
1096 | ----------------------------------------------------------------------------- |
|
1096 | ----------------------------------------------------------------------------- | |
1097 |
|
1097 | |||
1098 |
|
1098 | |||
1099 |
|
1099 | |||
1100 |
|
1100 | |||
1101 |
|
1101 | |||
1102 |
|
1102 | |||
1103 | ----------------------------------------------------------------------------- |
|
1103 | ----------------------------------------------------------------------------- | |
1104 | -- TIME MANAGMENT |
|
1104 | -- TIME MANAGMENT | |
1105 | ----------------------------------------------------------------------------- |
|
1105 | ----------------------------------------------------------------------------- | |
1106 | all_time <= coarse_time & fine_time; |
|
1106 | all_time <= coarse_time & fine_time; | |
1107 | -- |
|
1107 | -- | |
1108 | f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0'; |
|
1108 | f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0'; | |
1109 | f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0'; |
|
1109 | f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0'; | |
1110 | f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; |
|
1110 | f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; | |
1111 | f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0'; |
|
1111 | f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0'; | |
1112 |
|
1112 | |||
1113 | all_time_reg: FOR I IN 0 TO 3 GENERATE |
|
1113 | all_time_reg: FOR I IN 0 TO 3 GENERATE | |
1114 |
|
1114 | |||
1115 | PROCESS (clk, rstn) |
|
1115 | PROCESS (clk, rstn) | |
1116 | BEGIN |
|
1116 | BEGIN | |
1117 | IF rstn = '0' THEN |
|
1117 | IF rstn = '0' THEN | |
1118 | f_empty_reg(I) <= '1'; |
|
1118 | f_empty_reg(I) <= '1'; | |
1119 | ELSIF clk'event AND clk = '1' THEN |
|
1119 | ELSIF clk'event AND clk = '1' THEN | |
1120 | f_empty_reg(I) <= f_empty(I); |
|
1120 | f_empty_reg(I) <= f_empty(I); | |
1121 | END IF; |
|
1121 | END IF; | |
1122 | END PROCESS; |
|
1122 | END PROCESS; | |
1123 |
|
1123 | |||
1124 | time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0'; |
|
1124 | time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0'; | |
1125 |
|
1125 | |||
1126 | s_m_t_m_f0_A : spectral_matrix_time_managment |
|
1126 | s_m_t_m_f0_A : spectral_matrix_time_managment | |
1127 | PORT MAP ( |
|
1127 | PORT MAP ( | |
1128 | clk => clk, |
|
1128 | clk => clk, | |
1129 | rstn => rstn, |
|
1129 | rstn => rstn, | |
1130 | time_in => all_time, |
|
1130 | time_in => all_time, | |
1131 | update_1 => time_update_f(I), |
|
1131 | update_1 => time_update_f(I), | |
1132 | time_out => time_reg_f((I+1)*48-1 DOWNTO I*48) |
|
1132 | time_out => time_reg_f((I+1)*48-1 DOWNTO I*48) | |
1133 | ); |
|
1133 | ); | |
1134 |
|
1134 | |||
1135 | END GENERATE all_time_reg; |
|
1135 | END GENERATE all_time_reg; | |
1136 |
|
1136 | |||
1137 | time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48); |
|
1137 | time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48); | |
1138 | time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48); |
|
1138 | time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48); | |
1139 | time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48); |
|
1139 | time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48); | |
1140 | time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48); |
|
1140 | time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48); | |
1141 |
|
1141 | |||
1142 | ----------------------------------------------------------------------------- |
|
1142 | ----------------------------------------------------------------------------- | |
1143 |
|
1143 | |||
1144 | END Behavioral; No newline at end of file |
|
1144 | END Behavioral; |
@@ -1,187 +1,188 | |||||
1 |
|
1 | |||
2 | ------------------------------------------------------------------------------ |
|
2 | ------------------------------------------------------------------------------ | |
3 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | -- This file is a part of the LPP VHDL IP LIBRARY | |
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
5 | -- |
|
5 | -- | |
6 | -- This program is free software; you can redistribute it and/or modify |
|
6 | -- This program is free software; you can redistribute it and/or modify | |
7 | -- it under the terms of the GNU General Public License as published by |
|
7 | -- it under the terms of the GNU General Public License as published by | |
8 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | -- the Free Software Foundation; either version 3 of the License, or | |
9 | -- (at your option) any later version. |
|
9 | -- (at your option) any later version. | |
10 | -- |
|
10 | -- | |
11 | -- This program is distributed in the hope that it will be useful, |
|
11 | -- This program is distributed in the hope that it will be useful, | |
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | -- GNU General Public License for more details. |
|
14 | -- GNU General Public License for more details. | |
15 | -- |
|
15 | -- | |
16 | -- You should have received a copy of the GNU General Public License |
|
16 | -- You should have received a copy of the GNU General Public License | |
17 | -- along with this program; if not, write to the Free Software |
|
17 | -- along with this program; if not, write to the Free Software | |
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | ------------------------------------------------------------------------------- |
|
19 | ------------------------------------------------------------------------------- | |
20 | -- Author : Jean-christophe Pellion |
|
20 | -- Author : Jean-christophe Pellion | |
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
22 | -- jean-christophe.pellion@easii-ic.com |
|
22 | -- jean-christophe.pellion@easii-ic.com | |
23 | ------------------------------------------------------------------------------- |
|
23 | ------------------------------------------------------------------------------- | |
24 | LIBRARY ieee; |
|
24 | LIBRARY ieee; | |
25 | USE ieee.std_logic_1164.ALL; |
|
25 | USE ieee.std_logic_1164.ALL; | |
26 | USE ieee.numeric_std.ALL; |
|
26 | USE ieee.numeric_std.ALL; | |
27 | LIBRARY grlib; |
|
27 | LIBRARY grlib; | |
28 | USE grlib.amba.ALL; |
|
28 | USE grlib.amba.ALL; | |
29 | USE grlib.stdlib.ALL; |
|
29 | USE grlib.stdlib.ALL; | |
30 | USE grlib.devices.ALL; |
|
30 | USE grlib.devices.ALL; | |
31 | USE GRLIB.DMA2AHB_Package.ALL; |
|
31 | USE GRLIB.DMA2AHB_Package.ALL; | |
32 | LIBRARY lpp; |
|
32 | LIBRARY lpp; | |
33 | USE lpp.lpp_amba.ALL; |
|
33 | USE lpp.lpp_amba.ALL; | |
34 | USE lpp.apb_devices_list.ALL; |
|
34 | USE lpp.apb_devices_list.ALL; | |
35 | USE lpp.lpp_memory.ALL; |
|
35 | USE lpp.lpp_memory.ALL; | |
36 | USE lpp.lpp_dma_pkg.ALL; |
|
36 | USE lpp.lpp_dma_pkg.ALL; | |
37 | LIBRARY techmap; |
|
37 | LIBRARY techmap; | |
38 | USE techmap.gencomp.ALL; |
|
38 | USE techmap.gencomp.ALL; | |
39 |
|
39 | |||
40 |
|
40 | |||
41 | ENTITY lpp_lfr_ms_fsmdma IS |
|
41 | ENTITY lpp_lfr_ms_fsmdma IS | |
42 | PORT ( |
|
42 | PORT ( | |
43 | -- AMBA AHB system signals |
|
43 | -- AMBA AHB system signals | |
44 | clk : IN STD_ULOGIC; |
|
44 | clk : IN STD_ULOGIC; | |
45 | rstn : IN STD_ULOGIC; |
|
45 | rstn : IN STD_ULOGIC; | |
46 | run : IN STD_LOGIC; |
|
46 | run : IN STD_LOGIC; | |
47 |
|
47 | |||
48 | --------------------------------------------------------------------------- |
|
48 | --------------------------------------------------------------------------- | |
49 | -- FIFO - IN |
|
49 | -- FIFO - IN | |
50 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
50 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
51 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
51 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
52 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
52 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
53 | fifo_empty : IN STD_LOGIC; |
|
53 | fifo_empty : IN STD_LOGIC; | |
54 | fifo_empty_threshold : IN STD_LOGIC; |
|
54 | fifo_empty_threshold : IN STD_LOGIC; | |
55 | fifo_ren : OUT STD_LOGIC; |
|
55 | fifo_ren : OUT STD_LOGIC; | |
56 |
|
56 | |||
57 | --------------------------------------------------------------------------- |
|
57 | --------------------------------------------------------------------------- | |
58 | -- DMA - OUT |
|
58 | -- DMA - OUT | |
59 | dma_fifo_valid_burst : OUT STD_LOGIC; |
|
59 | dma_fifo_valid_burst : OUT STD_LOGIC; | |
60 | dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
60 | dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
61 | dma_fifo_ren : IN STD_LOGIC; |
|
61 | dma_fifo_ren : IN STD_LOGIC; | |
62 |
|
62 | |||
63 | dma_buffer_new : OUT STD_LOGIC; |
|
63 | dma_buffer_new : OUT STD_LOGIC; | |
64 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
64 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
65 | dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
65 | dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
66 | dma_buffer_full : IN STD_LOGIC; |
|
66 | dma_buffer_full : IN STD_LOGIC; | |
67 | dma_buffer_full_err : IN STD_LOGIC; |
|
67 | dma_buffer_full_err : IN STD_LOGIC; | |
68 |
|
68 | |||
69 | --------------------------------------------------------------------------- |
|
69 | --------------------------------------------------------------------------- | |
70 | -- Reg In |
|
70 | -- Reg In | |
71 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
71 | status_ready_matrix_f0 : IN STD_LOGIC; | |
72 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
72 | status_ready_matrix_f1 : IN STD_LOGIC; | |
73 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
73 | status_ready_matrix_f2 : IN STD_LOGIC; | |
74 |
|
74 | |||
75 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
75 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
76 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
76 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
77 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
77 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
78 |
|
78 | |||
79 | length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
79 | length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); | |
80 | length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
80 | length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); | |
81 | length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
81 | length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); | |
82 |
|
82 | |||
83 | -- Reg Out |
|
83 | -- Reg Out | |
84 | ready_matrix_f0 : OUT STD_LOGIC; |
|
84 | ready_matrix_f0 : OUT STD_LOGIC; | |
85 | ready_matrix_f1 : OUT STD_LOGIC; |
|
85 | ready_matrix_f1 : OUT STD_LOGIC; | |
86 | ready_matrix_f2 : OUT STD_LOGIC; |
|
86 | ready_matrix_f2 : OUT STD_LOGIC; | |
87 |
|
87 | |||
88 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
88 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
89 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
89 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
90 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
90 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
91 | error_buffer_full : OUT STD_LOGIC |
|
91 | error_buffer_full : OUT STD_LOGIC | |
92 | ); |
|
92 | ); | |
93 | END; |
|
93 | END; | |
94 |
|
94 | |||
95 | ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS |
|
95 | ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS | |
96 |
|
96 | |||
97 | TYPE FSM_DMA_STATE IS (IDLE, ONGOING); |
|
97 | TYPE FSM_DMA_STATE IS (IDLE, ONGOING); | |
98 | SIGNAL state : FSM_DMA_STATE; |
|
98 | SIGNAL state : FSM_DMA_STATE; | |
99 | SIGNAL burst_valid_s : STD_LOGIC; |
|
99 | SIGNAL burst_valid_s : STD_LOGIC; | |
100 |
|
100 | |||
101 | SIGNAL current_matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
101 | SIGNAL current_matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
102 |
|
102 | |||
103 | BEGIN |
|
103 | BEGIN | |
104 | burst_valid_s <= NOT fifo_empty_threshold; |
|
104 | burst_valid_s <= NOT fifo_empty_threshold; | |
105 |
|
105 | |||
106 | error_buffer_full <= dma_buffer_full_err; |
|
106 | error_buffer_full <= dma_buffer_full_err; | |
107 |
|
107 | |||
108 | fifo_ren <= dma_fifo_ren WHEN state = ONGOING ELSE '1'; |
|
108 | fifo_ren <= dma_fifo_ren WHEN state = ONGOING ELSE '1'; | |
109 | dma_fifo_data <= fifo_data; |
|
109 | dma_fifo_data <= fifo_data; | |
110 |
dma_fifo_valid_burst <= burst_valid_s WHEN state = ONGOING ELSE ' |
|
110 | dma_fifo_valid_burst <= burst_valid_s WHEN state = ONGOING ELSE '0'; | |
111 |
|
111 | |||
112 | PROCESS (clk, rstn) |
|
112 | PROCESS (clk, rstn) | |
113 | BEGIN -- PROCESS |
|
113 | BEGIN -- PROCESS | |
114 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
114 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
115 | state <= IDLE; |
|
115 | state <= IDLE; | |
116 | current_matrix_type <= "00"; |
|
116 | current_matrix_type <= "00"; | |
117 | matrix_time_f0 <= (OTHERS => '0'); |
|
117 | matrix_time_f0 <= (OTHERS => '0'); | |
118 | matrix_time_f1 <= (OTHERS => '0'); |
|
118 | matrix_time_f1 <= (OTHERS => '0'); | |
119 | matrix_time_f2 <= (OTHERS => '0'); |
|
119 | matrix_time_f2 <= (OTHERS => '0'); | |
120 | dma_buffer_addr <= (OTHERS => '0'); |
|
120 | dma_buffer_addr <= (OTHERS => '0'); | |
121 | dma_buffer_length <= (OTHERS => '0'); |
|
121 | dma_buffer_length <= (OTHERS => '0'); | |
122 | dma_buffer_new <= '0'; |
|
122 | dma_buffer_new <= '0'; | |
123 | ready_matrix_f0 <= '0'; |
|
123 | ready_matrix_f0 <= '0'; | |
124 | ready_matrix_f1 <= '0'; |
|
124 | ready_matrix_f1 <= '0'; | |
125 | ready_matrix_f2 <= '0'; |
|
125 | ready_matrix_f2 <= '0'; | |
126 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
126 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
127 | ready_matrix_f0 <= '0'; |
|
127 | ready_matrix_f0 <= '0'; | |
128 | ready_matrix_f1 <= '0'; |
|
128 | ready_matrix_f1 <= '0'; | |
129 | ready_matrix_f2 <= '0'; |
|
129 | ready_matrix_f2 <= '0'; | |
130 | IF run = '1' THEN |
|
130 | IF run = '1' THEN | |
|
131 | dma_buffer_new <= '0'; | |||
131 | CASE state IS |
|
132 | CASE state IS | |
132 | WHEN IDLE => |
|
133 | WHEN IDLE => | |
133 | IF fifo_empty = '0' THEN |
|
134 | IF fifo_empty = '0' THEN | |
134 | current_matrix_type <= fifo_matrix_type; |
|
135 | current_matrix_type <= fifo_matrix_type; | |
135 | CASE fifo_matrix_type IS |
|
136 | CASE fifo_matrix_type IS | |
136 | WHEN "00" => |
|
137 | WHEN "00" => | |
137 | IF status_ready_matrix_f0 = '0' THEN |
|
138 | IF status_ready_matrix_f0 = '0' THEN | |
138 | state <= ONGOING; |
|
139 | state <= ONGOING; | |
139 | matrix_time_f0 <= fifo_matrix_time; |
|
140 | matrix_time_f0 <= fifo_matrix_time; | |
140 | dma_buffer_addr <= addr_matrix_f0; |
|
141 | dma_buffer_addr <= addr_matrix_f0; | |
141 | dma_buffer_length <= length_matrix_f0; |
|
142 | dma_buffer_length <= length_matrix_f0; | |
142 | dma_buffer_new <= '1'; |
|
143 | dma_buffer_new <= '1'; | |
143 | END IF; |
|
144 | END IF; | |
144 | WHEN "01" => |
|
145 | WHEN "01" => | |
145 | IF status_ready_matrix_f1 = '0' THEN |
|
146 | IF status_ready_matrix_f1 = '0' THEN | |
146 | state <= ONGOING; |
|
147 | state <= ONGOING; | |
147 | matrix_time_f1 <= fifo_matrix_time; |
|
148 | matrix_time_f1 <= fifo_matrix_time; | |
148 | dma_buffer_addr <= addr_matrix_f1; |
|
149 | dma_buffer_addr <= addr_matrix_f1; | |
149 | dma_buffer_length <= length_matrix_f1; |
|
150 | dma_buffer_length <= length_matrix_f1; | |
150 | dma_buffer_new <= '1'; |
|
151 | dma_buffer_new <= '1'; | |
151 | END IF; |
|
152 | END IF; | |
152 | WHEN "10" => |
|
153 | WHEN "10" => | |
153 | IF status_ready_matrix_f2 = '0' THEN |
|
154 | IF status_ready_matrix_f2 = '0' THEN | |
154 | state <= ONGOING; |
|
155 | state <= ONGOING; | |
155 | matrix_time_f2 <= fifo_matrix_time; |
|
156 | matrix_time_f2 <= fifo_matrix_time; | |
156 | dma_buffer_addr <= addr_matrix_f2; |
|
157 | dma_buffer_addr <= addr_matrix_f2; | |
157 | dma_buffer_length <= length_matrix_f2; |
|
158 | dma_buffer_length <= length_matrix_f2; | |
158 | dma_buffer_new <= '1'; |
|
159 | dma_buffer_new <= '1'; | |
159 | END IF; |
|
160 | END IF; | |
160 | WHEN OTHERS => NULL; |
|
161 | WHEN OTHERS => NULL; | |
161 | END CASE; |
|
162 | END CASE; | |
162 | END IF; |
|
163 | END IF; | |
163 | WHEN ONGOING => |
|
164 | WHEN ONGOING => | |
164 | IF dma_buffer_full = '1' THEN |
|
165 | IF dma_buffer_full = '1' THEN | |
165 | CASE current_matrix_type IS |
|
166 | CASE current_matrix_type IS | |
166 | WHEN "00" => ready_matrix_f0 <= '1'; state <= IDLE; |
|
167 | WHEN "00" => ready_matrix_f0 <= '1'; state <= IDLE; | |
167 | WHEN "01" => ready_matrix_f1 <= '1'; state <= IDLE; |
|
168 | WHEN "01" => ready_matrix_f1 <= '1'; state <= IDLE; | |
168 | WHEN "10" => ready_matrix_f2 <= '1'; state <= IDLE; |
|
169 | WHEN "10" => ready_matrix_f2 <= '1'; state <= IDLE; | |
169 | WHEN OTHERS => NULL; |
|
170 | WHEN OTHERS => NULL; | |
170 | END CASE; |
|
171 | END CASE; | |
171 | END IF; |
|
172 | END IF; | |
172 | WHEN OTHERS => NULL; |
|
173 | WHEN OTHERS => NULL; | |
173 | END CASE; |
|
174 | END CASE; | |
174 | ELSE |
|
175 | ELSE | |
175 | state <= IDLE; |
|
176 | state <= IDLE; | |
176 | current_matrix_type <= "00"; |
|
177 | current_matrix_type <= "00"; | |
177 | matrix_time_f0 <= (OTHERS => '0'); |
|
178 | matrix_time_f0 <= (OTHERS => '0'); | |
178 | matrix_time_f1 <= (OTHERS => '0'); |
|
179 | matrix_time_f1 <= (OTHERS => '0'); | |
179 | matrix_time_f2 <= (OTHERS => '0'); |
|
180 | matrix_time_f2 <= (OTHERS => '0'); | |
180 | dma_buffer_addr <= (OTHERS => '0'); |
|
181 | dma_buffer_addr <= (OTHERS => '0'); | |
181 | dma_buffer_length <= (OTHERS => '0'); |
|
182 | dma_buffer_length <= (OTHERS => '0'); | |
182 | dma_buffer_new <= '0'; |
|
183 | dma_buffer_new <= '0'; | |
183 | END IF; |
|
184 | END IF; | |
184 | END IF; |
|
185 | END IF; | |
185 | END PROCESS; |
|
186 | END PROCESS; | |
186 |
|
187 | |||
187 | END Behavioral; |
|
188 | END Behavioral; |
@@ -1,389 +1,385 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
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2 | USE ieee.std_logic_1164.ALL; | |
3 |
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3 | |||
4 | LIBRARY grlib; |
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4 | LIBRARY grlib; | |
5 | USE grlib.amba.ALL; |
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5 | USE grlib.amba.ALL; | |
6 |
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6 | |||
7 | LIBRARY lpp; |
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7 | LIBRARY lpp; | |
8 | USE lpp.lpp_ad_conv.ALL; |
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8 | USE lpp.lpp_ad_conv.ALL; | |
9 | USE lpp.iir_filter.ALL; |
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9 | USE lpp.iir_filter.ALL; | |
10 | USE lpp.FILTERcfg.ALL; |
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10 | USE lpp.FILTERcfg.ALL; | |
11 | USE lpp.lpp_memory.ALL; |
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11 | USE lpp.lpp_memory.ALL; | |
12 | LIBRARY techmap; |
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12 | LIBRARY techmap; | |
13 | USE techmap.gencomp.ALL; |
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13 | USE techmap.gencomp.ALL; | |
14 |
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14 | |||
15 | PACKAGE lpp_lfr_pkg IS |
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15 | PACKAGE lpp_lfr_pkg IS | |
16 | ----------------------------------------------------------------------------- |
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16 | ----------------------------------------------------------------------------- | |
17 | -- TEMP |
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17 | -- TEMP | |
18 | ----------------------------------------------------------------------------- |
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18 | ----------------------------------------------------------------------------- | |
19 | COMPONENT lpp_lfr_ms_test |
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19 | COMPONENT lpp_lfr_ms_test | |
20 | GENERIC ( |
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20 | GENERIC ( | |
21 | Mem_use : INTEGER); |
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21 | Mem_use : INTEGER); | |
22 | PORT ( |
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22 | PORT ( | |
23 | clk : IN STD_LOGIC; |
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23 | clk : IN STD_LOGIC; | |
24 | rstn : IN STD_LOGIC; |
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24 | rstn : IN STD_LOGIC; | |
25 |
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25 | |||
26 | -- TIME |
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26 | -- TIME | |
27 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
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27 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
28 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
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28 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
29 | -- |
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29 | -- | |
30 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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30 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
31 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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31 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
32 | -- |
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32 | -- | |
33 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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33 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
34 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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34 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
35 | -- |
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35 | -- | |
36 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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36 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
37 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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37 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
38 |
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38 | |||
39 |
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39 | |||
40 |
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40 | |||
41 | --------------------------------------------------------------------------- |
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41 | --------------------------------------------------------------------------- | |
42 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
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42 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
43 |
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43 | |||
44 | -- |
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44 | -- | |
45 | --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
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45 | --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
46 | --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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46 | --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
47 | --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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47 | --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
48 | --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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48 | --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
49 |
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49 | |||
50 | --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0); |
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50 | --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0); | |
51 |
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51 | |||
52 | -- IN |
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52 | -- IN | |
53 | MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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53 | MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
54 |
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54 | |||
55 | ----------------------------------------------------------------------------- |
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55 | ----------------------------------------------------------------------------- | |
56 |
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56 | |||
57 | status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); |
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57 | status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); | |
58 | SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); |
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58 | SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); | |
59 | SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
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59 | SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
60 | SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
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60 | SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
61 |
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61 | |||
62 | SM_correlation_start : OUT STD_LOGIC; |
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62 | SM_correlation_start : OUT STD_LOGIC; | |
63 | SM_correlation_auto : OUT STD_LOGIC; |
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63 | SM_correlation_auto : OUT STD_LOGIC; | |
64 | SM_correlation_done : IN STD_LOGIC |
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64 | SM_correlation_done : IN STD_LOGIC | |
65 | ); |
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65 | ); | |
66 | END COMPONENT; |
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66 | END COMPONENT; | |
67 |
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67 | |||
68 |
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68 | |||
69 | ----------------------------------------------------------------------------- |
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69 | ----------------------------------------------------------------------------- | |
70 | COMPONENT lpp_lfr_ms |
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70 | COMPONENT lpp_lfr_ms | |
71 | GENERIC ( |
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71 | GENERIC ( | |
72 | Mem_use : INTEGER); |
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72 | Mem_use : INTEGER); | |
73 | PORT ( |
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73 | PORT ( | |
74 | clk : IN STD_LOGIC; |
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74 | clk : IN STD_LOGIC; | |
75 | rstn : IN STD_LOGIC; |
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75 | rstn : IN STD_LOGIC; | |
76 | run : IN STD_LOGIC; |
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76 | run : IN STD_LOGIC; | |
77 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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77 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
78 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
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78 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
79 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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79 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
80 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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80 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
81 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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81 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
82 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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82 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
83 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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83 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
84 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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84 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
85 | dma_fifo_burst_valid : OUT STD_LOGIC; |
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85 | dma_fifo_burst_valid : OUT STD_LOGIC; | |
86 | dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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86 | dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
87 | dma_fifo_ren : IN STD_LOGIC; |
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87 | dma_fifo_ren : IN STD_LOGIC; | |
88 | dma_buffer_new : OUT STD_LOGIC; |
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88 | dma_buffer_new : OUT STD_LOGIC; | |
89 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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89 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
90 | dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
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90 | dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
91 | dma_buffer_full : IN STD_LOGIC; |
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91 | dma_buffer_full : IN STD_LOGIC; | |
92 | dma_buffer_full_err : IN STD_LOGIC; |
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92 | dma_buffer_full_err : IN STD_LOGIC; | |
93 | ready_matrix_f0 : OUT STD_LOGIC; |
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93 | ready_matrix_f0 : OUT STD_LOGIC; | |
94 | ready_matrix_f1 : OUT STD_LOGIC; |
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94 | ready_matrix_f1 : OUT STD_LOGIC; | |
95 | ready_matrix_f2 : OUT STD_LOGIC; |
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95 | ready_matrix_f2 : OUT STD_LOGIC; | |
96 | error_buffer_full : OUT STD_LOGIC; |
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96 | error_buffer_full : OUT STD_LOGIC; | |
97 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
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97 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
98 | status_ready_matrix_f0 : IN STD_LOGIC; |
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98 | status_ready_matrix_f0 : IN STD_LOGIC; | |
99 | status_ready_matrix_f1 : IN STD_LOGIC; |
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99 | status_ready_matrix_f1 : IN STD_LOGIC; | |
100 | status_ready_matrix_f2 : IN STD_LOGIC; |
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100 | status_ready_matrix_f2 : IN STD_LOGIC; | |
101 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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101 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
102 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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102 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
103 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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103 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
104 | length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
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104 | length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); | |
105 | length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
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105 | length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); | |
106 | length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
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106 | length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); | |
107 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
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107 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
108 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
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108 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
109 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); |
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109 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); | |
110 | END COMPONENT; |
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110 | END COMPONENT; | |
111 |
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111 | |||
112 | COMPONENT lpp_lfr_ms_fsmdma |
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112 | COMPONENT lpp_lfr_ms_fsmdma | |
113 | PORT ( |
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113 | PORT ( | |
114 | clk : IN STD_ULOGIC; |
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114 | clk : IN STD_ULOGIC; | |
115 | rstn : IN STD_ULOGIC; |
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115 | rstn : IN STD_ULOGIC; | |
116 | run : IN STD_LOGIC; |
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116 | run : IN STD_LOGIC; | |
117 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
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117 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
118 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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118 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
119 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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119 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
120 | fifo_empty : IN STD_LOGIC; |
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120 | fifo_empty : IN STD_LOGIC; | |
121 | fifo_empty_threshold : IN STD_LOGIC; |
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121 | fifo_empty_threshold : IN STD_LOGIC; | |
122 | fifo_ren : OUT STD_LOGIC; |
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122 | fifo_ren : OUT STD_LOGIC; | |
123 | dma_fifo_valid_burst : OUT STD_LOGIC; |
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123 | dma_fifo_valid_burst : OUT STD_LOGIC; | |
124 | dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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124 | dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
125 | dma_fifo_ren : IN STD_LOGIC; |
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125 | dma_fifo_ren : IN STD_LOGIC; | |
126 | dma_buffer_new : OUT STD_LOGIC; |
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126 | dma_buffer_new : OUT STD_LOGIC; | |
127 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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127 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
128 | dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
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128 | dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
129 | dma_buffer_full : IN STD_LOGIC; |
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129 | dma_buffer_full : IN STD_LOGIC; | |
130 | dma_buffer_full_err : IN STD_LOGIC; |
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130 | dma_buffer_full_err : IN STD_LOGIC; | |
131 | status_ready_matrix_f0 : IN STD_LOGIC; |
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131 | status_ready_matrix_f0 : IN STD_LOGIC; | |
132 | status_ready_matrix_f1 : IN STD_LOGIC; |
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132 | status_ready_matrix_f1 : IN STD_LOGIC; | |
133 | status_ready_matrix_f2 : IN STD_LOGIC; |
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133 | status_ready_matrix_f2 : IN STD_LOGIC; | |
134 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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134 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
135 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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135 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
136 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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136 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
137 | length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
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137 | length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); | |
138 | length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
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138 | length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); | |
139 | length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
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139 | length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); | |
140 | ready_matrix_f0 : OUT STD_LOGIC; |
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140 | ready_matrix_f0 : OUT STD_LOGIC; | |
141 | ready_matrix_f1 : OUT STD_LOGIC; |
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141 | ready_matrix_f1 : OUT STD_LOGIC; | |
142 | ready_matrix_f2 : OUT STD_LOGIC; |
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142 | ready_matrix_f2 : OUT STD_LOGIC; | |
143 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
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143 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
144 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
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144 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
145 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
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145 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
146 | error_buffer_full : OUT STD_LOGIC); |
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146 | error_buffer_full : OUT STD_LOGIC); | |
147 | END COMPONENT; |
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147 | END COMPONENT; | |
148 |
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148 | |||
149 | COMPONENT lpp_lfr_ms_FFT |
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149 | COMPONENT lpp_lfr_ms_FFT | |
150 | PORT ( |
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150 | PORT ( | |
151 | clk : IN STD_LOGIC; |
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151 | clk : IN STD_LOGIC; | |
152 | rstn : IN STD_LOGIC; |
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152 | rstn : IN STD_LOGIC; | |
153 | sample_valid : IN STD_LOGIC; |
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153 | sample_valid : IN STD_LOGIC; | |
154 | fft_read : IN STD_LOGIC; |
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154 | fft_read : IN STD_LOGIC; | |
155 | sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
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155 | sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
156 | sample_load : OUT STD_LOGIC; |
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156 | sample_load : OUT STD_LOGIC; | |
157 | fft_pong : OUT STD_LOGIC; |
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157 | fft_pong : OUT STD_LOGIC; | |
158 | fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
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158 | fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |
159 | fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
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159 | fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |
160 | fft_data_valid : OUT STD_LOGIC; |
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160 | fft_data_valid : OUT STD_LOGIC; | |
161 | fft_ready : OUT STD_LOGIC); |
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161 | fft_ready : OUT STD_LOGIC); | |
162 | END COMPONENT; |
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162 | END COMPONENT; | |
163 |
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163 | |||
164 | COMPONENT lpp_lfr_filter |
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164 | COMPONENT lpp_lfr_filter | |
165 | GENERIC ( |
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165 | GENERIC ( | |
166 | Mem_use : INTEGER); |
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166 | Mem_use : INTEGER); | |
167 | PORT ( |
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167 | PORT ( | |
168 | sample : IN Samples(7 DOWNTO 0); |
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168 | sample : IN Samples(7 DOWNTO 0); | |
169 | sample_val : IN STD_LOGIC; |
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169 | sample_val : IN STD_LOGIC; | |
170 | clk : IN STD_LOGIC; |
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170 | clk : IN STD_LOGIC; | |
171 | rstn : IN STD_LOGIC; |
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171 | rstn : IN STD_LOGIC; | |
172 | data_shaping_SP0 : IN STD_LOGIC; |
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172 | data_shaping_SP0 : IN STD_LOGIC; | |
173 | data_shaping_SP1 : IN STD_LOGIC; |
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173 | data_shaping_SP1 : IN STD_LOGIC; | |
174 | data_shaping_R0 : IN STD_LOGIC; |
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174 | data_shaping_R0 : IN STD_LOGIC; | |
175 | data_shaping_R1 : IN STD_LOGIC; |
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175 | data_shaping_R1 : IN STD_LOGIC; | |
176 | data_shaping_R2 : IN STD_LOGIC; |
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176 | data_shaping_R2 : IN STD_LOGIC; | |
177 | sample_f0_val : OUT STD_LOGIC; |
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177 | sample_f0_val : OUT STD_LOGIC; | |
178 | sample_f1_val : OUT STD_LOGIC; |
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178 | sample_f1_val : OUT STD_LOGIC; | |
179 | sample_f2_val : OUT STD_LOGIC; |
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179 | sample_f2_val : OUT STD_LOGIC; | |
180 | sample_f3_val : OUT STD_LOGIC; |
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180 | sample_f3_val : OUT STD_LOGIC; | |
181 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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181 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
182 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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182 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
183 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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183 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
184 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)); |
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184 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)); | |
185 | END COMPONENT; |
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185 | END COMPONENT; | |
186 |
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186 | |||
187 | COMPONENT lpp_lfr |
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187 | COMPONENT lpp_lfr | |
188 | GENERIC ( |
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188 | GENERIC ( | |
189 | Mem_use : INTEGER; |
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189 | Mem_use : INTEGER; | |
190 | nb_data_by_buffer_size : INTEGER; |
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190 | nb_data_by_buffer_size : INTEGER; | |
191 | nb_word_by_buffer_size : INTEGER; |
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191 | -- nb_word_by_buffer_size : INTEGER; | |
192 | nb_snapshot_param_size : INTEGER; |
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192 | nb_snapshot_param_size : INTEGER; | |
193 | delta_vector_size : INTEGER; |
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193 | delta_vector_size : INTEGER; | |
194 | delta_vector_size_f0_2 : INTEGER; |
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194 | delta_vector_size_f0_2 : INTEGER; | |
195 | pindex : INTEGER; |
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195 | pindex : INTEGER; | |
196 | paddr : INTEGER; |
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196 | paddr : INTEGER; | |
197 | pmask : INTEGER; |
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197 | pmask : INTEGER; | |
198 | pirq_ms : INTEGER; |
|
198 | pirq_ms : INTEGER; | |
199 | pirq_wfp : INTEGER; |
|
199 | pirq_wfp : INTEGER; | |
200 | hindex : INTEGER; |
|
200 | hindex : INTEGER; | |
201 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) |
|
201 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) | |
202 | ); |
|
202 | ); | |
203 | PORT ( |
|
203 | PORT ( | |
204 | clk : IN STD_LOGIC; |
|
204 | clk : IN STD_LOGIC; | |
205 | rstn : IN STD_LOGIC; |
|
205 | rstn : IN STD_LOGIC; | |
206 | sample_B : IN Samples(2 DOWNTO 0); |
|
206 | sample_B : IN Samples(2 DOWNTO 0); | |
207 | sample_E : IN Samples(4 DOWNTO 0); |
|
207 | sample_E : IN Samples(4 DOWNTO 0); | |
208 | sample_val : IN STD_LOGIC; |
|
208 | sample_val : IN STD_LOGIC; | |
209 | apbi : IN apb_slv_in_type; |
|
209 | apbi : IN apb_slv_in_type; | |
210 | apbo : OUT apb_slv_out_type; |
|
210 | apbo : OUT apb_slv_out_type; | |
211 | ahbi : IN AHB_Mst_In_Type; |
|
211 | ahbi : IN AHB_Mst_In_Type; | |
212 | ahbo : OUT AHB_Mst_Out_Type; |
|
212 | ahbo : OUT AHB_Mst_Out_Type; | |
213 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
213 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
214 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
214 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
215 |
data_shaping_BW : OUT STD_LOGIC |
|
215 | data_shaping_BW : OUT STD_LOGIC | |
216 | -- |
|
|||
217 | observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
|||
218 | observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
|||
219 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
|||
220 | ); |
|
216 | ); | |
221 | END COMPONENT; |
|
217 | END COMPONENT; | |
222 |
|
218 | |||
223 | ----------------------------------------------------------------------------- |
|
219 | ----------------------------------------------------------------------------- | |
224 | -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System) |
|
220 | -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System) | |
225 | ----------------------------------------------------------------------------- |
|
221 | ----------------------------------------------------------------------------- | |
226 | COMPONENT lpp_lfr_WFP_nMS |
|
222 | COMPONENT lpp_lfr_WFP_nMS | |
227 | GENERIC ( |
|
223 | GENERIC ( | |
228 | Mem_use : INTEGER; |
|
224 | Mem_use : INTEGER; | |
229 | nb_data_by_buffer_size : INTEGER; |
|
225 | nb_data_by_buffer_size : INTEGER; | |
230 | nb_word_by_buffer_size : INTEGER; |
|
226 | nb_word_by_buffer_size : INTEGER; | |
231 | nb_snapshot_param_size : INTEGER; |
|
227 | nb_snapshot_param_size : INTEGER; | |
232 | delta_vector_size : INTEGER; |
|
228 | delta_vector_size : INTEGER; | |
233 | delta_vector_size_f0_2 : INTEGER; |
|
229 | delta_vector_size_f0_2 : INTEGER; | |
234 | pindex : INTEGER; |
|
230 | pindex : INTEGER; | |
235 | paddr : INTEGER; |
|
231 | paddr : INTEGER; | |
236 | pmask : INTEGER; |
|
232 | pmask : INTEGER; | |
237 | pirq_ms : INTEGER; |
|
233 | pirq_ms : INTEGER; | |
238 | pirq_wfp : INTEGER; |
|
234 | pirq_wfp : INTEGER; | |
239 | hindex : INTEGER; |
|
235 | hindex : INTEGER; | |
240 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
236 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
241 | PORT ( |
|
237 | PORT ( | |
242 | clk : IN STD_LOGIC; |
|
238 | clk : IN STD_LOGIC; | |
243 | rstn : IN STD_LOGIC; |
|
239 | rstn : IN STD_LOGIC; | |
244 | sample_B : IN Samples(2 DOWNTO 0); |
|
240 | sample_B : IN Samples(2 DOWNTO 0); | |
245 | sample_E : IN Samples(4 DOWNTO 0); |
|
241 | sample_E : IN Samples(4 DOWNTO 0); | |
246 | sample_val : IN STD_LOGIC; |
|
242 | sample_val : IN STD_LOGIC; | |
247 | apbi : IN apb_slv_in_type; |
|
243 | apbi : IN apb_slv_in_type; | |
248 | apbo : OUT apb_slv_out_type; |
|
244 | apbo : OUT apb_slv_out_type; | |
249 | ahbi : IN AHB_Mst_In_Type; |
|
245 | ahbi : IN AHB_Mst_In_Type; | |
250 | ahbo : OUT AHB_Mst_Out_Type; |
|
246 | ahbo : OUT AHB_Mst_Out_Type; | |
251 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
247 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
252 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
248 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
253 | data_shaping_BW : OUT STD_LOGIC; |
|
249 | data_shaping_BW : OUT STD_LOGIC; | |
254 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
250 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
255 | END COMPONENT; |
|
251 | END COMPONENT; | |
256 | ----------------------------------------------------------------------------- |
|
252 | ----------------------------------------------------------------------------- | |
257 |
|
253 | |||
258 | COMPONENT lpp_lfr_apbreg |
|
254 | COMPONENT lpp_lfr_apbreg | |
259 | GENERIC ( |
|
255 | GENERIC ( | |
260 | nb_data_by_buffer_size : INTEGER; |
|
256 | nb_data_by_buffer_size : INTEGER; | |
261 | nb_snapshot_param_size : INTEGER; |
|
257 | nb_snapshot_param_size : INTEGER; | |
262 | delta_vector_size : INTEGER; |
|
258 | delta_vector_size : INTEGER; | |
263 | delta_vector_size_f0_2 : INTEGER; |
|
259 | delta_vector_size_f0_2 : INTEGER; | |
264 | pindex : INTEGER; |
|
260 | pindex : INTEGER; | |
265 | paddr : INTEGER; |
|
261 | paddr : INTEGER; | |
266 | pmask : INTEGER; |
|
262 | pmask : INTEGER; | |
267 | pirq_ms : INTEGER; |
|
263 | pirq_ms : INTEGER; | |
268 | pirq_wfp : INTEGER; |
|
264 | pirq_wfp : INTEGER; | |
269 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
265 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
270 | PORT ( |
|
266 | PORT ( | |
271 | HCLK : IN STD_ULOGIC; |
|
267 | HCLK : IN STD_ULOGIC; | |
272 | HRESETn : IN STD_ULOGIC; |
|
268 | HRESETn : IN STD_ULOGIC; | |
273 | apbi : IN apb_slv_in_type; |
|
269 | apbi : IN apb_slv_in_type; | |
274 | apbo : OUT apb_slv_out_type; |
|
270 | apbo : OUT apb_slv_out_type; | |
275 | run_ms : OUT STD_LOGIC; |
|
271 | run_ms : OUT STD_LOGIC; | |
276 | ready_matrix_f0 : IN STD_LOGIC; |
|
272 | ready_matrix_f0 : IN STD_LOGIC; | |
277 | ready_matrix_f1 : IN STD_LOGIC; |
|
273 | ready_matrix_f1 : IN STD_LOGIC; | |
278 | ready_matrix_f2 : IN STD_LOGIC; |
|
274 | ready_matrix_f2 : IN STD_LOGIC; | |
279 | error_buffer_full : IN STD_LOGIC; |
|
275 | error_buffer_full : IN STD_LOGIC; | |
280 | error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
276 | error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); | |
281 | status_ready_matrix_f0 : OUT STD_LOGIC; |
|
277 | status_ready_matrix_f0 : OUT STD_LOGIC; | |
282 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
278 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
283 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
279 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
284 | addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
280 | addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
285 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
281 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
286 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
282 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
287 | length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
283 | length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
288 | length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
284 | length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
289 | length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
285 | length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
290 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
286 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
291 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
287 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
292 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
288 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
293 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
289 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
294 | data_shaping_BW : OUT STD_LOGIC; |
|
290 | data_shaping_BW : OUT STD_LOGIC; | |
295 | data_shaping_SP0 : OUT STD_LOGIC; |
|
291 | data_shaping_SP0 : OUT STD_LOGIC; | |
296 | data_shaping_SP1 : OUT STD_LOGIC; |
|
292 | data_shaping_SP1 : OUT STD_LOGIC; | |
297 | data_shaping_R0 : OUT STD_LOGIC; |
|
293 | data_shaping_R0 : OUT STD_LOGIC; | |
298 | data_shaping_R1 : OUT STD_LOGIC; |
|
294 | data_shaping_R1 : OUT STD_LOGIC; | |
299 | data_shaping_R2 : OUT STD_LOGIC; |
|
295 | data_shaping_R2 : OUT STD_LOGIC; | |
300 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
296 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
301 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
297 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
302 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
298 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
303 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
299 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
304 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
300 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
305 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
301 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
306 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
302 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
307 | enable_f0 : OUT STD_LOGIC; |
|
303 | enable_f0 : OUT STD_LOGIC; | |
308 | enable_f1 : OUT STD_LOGIC; |
|
304 | enable_f1 : OUT STD_LOGIC; | |
309 | enable_f2 : OUT STD_LOGIC; |
|
305 | enable_f2 : OUT STD_LOGIC; | |
310 | enable_f3 : OUT STD_LOGIC; |
|
306 | enable_f3 : OUT STD_LOGIC; | |
311 | burst_f0 : OUT STD_LOGIC; |
|
307 | burst_f0 : OUT STD_LOGIC; | |
312 | burst_f1 : OUT STD_LOGIC; |
|
308 | burst_f1 : OUT STD_LOGIC; | |
313 | burst_f2 : OUT STD_LOGIC; |
|
309 | burst_f2 : OUT STD_LOGIC; | |
314 | run : OUT STD_LOGIC; |
|
310 | run : OUT STD_LOGIC; | |
315 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
311 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); | |
316 | wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
312 | wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
317 | wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0); |
|
313 | wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0); | |
318 | wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
314 | wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
319 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
315 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
320 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
|
316 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |
321 | wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)); |
|
317 | wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)); | |
322 | END COMPONENT; |
|
318 | END COMPONENT; | |
323 |
|
319 | |||
324 | COMPONENT lpp_top_ms |
|
320 | COMPONENT lpp_top_ms | |
325 | GENERIC ( |
|
321 | GENERIC ( | |
326 | Mem_use : INTEGER; |
|
322 | Mem_use : INTEGER; | |
327 | nb_burst_available_size : INTEGER; |
|
323 | nb_burst_available_size : INTEGER; | |
328 | nb_snapshot_param_size : INTEGER; |
|
324 | nb_snapshot_param_size : INTEGER; | |
329 | delta_snapshot_size : INTEGER; |
|
325 | delta_snapshot_size : INTEGER; | |
330 | delta_f2_f0_size : INTEGER; |
|
326 | delta_f2_f0_size : INTEGER; | |
331 | delta_f2_f1_size : INTEGER; |
|
327 | delta_f2_f1_size : INTEGER; | |
332 | pindex : INTEGER; |
|
328 | pindex : INTEGER; | |
333 | paddr : INTEGER; |
|
329 | paddr : INTEGER; | |
334 | pmask : INTEGER; |
|
330 | pmask : INTEGER; | |
335 | pirq_ms : INTEGER; |
|
331 | pirq_ms : INTEGER; | |
336 | pirq_wfp : INTEGER; |
|
332 | pirq_wfp : INTEGER; | |
337 | hindex_wfp : INTEGER; |
|
333 | hindex_wfp : INTEGER; | |
338 | hindex_ms : INTEGER); |
|
334 | hindex_ms : INTEGER); | |
339 | PORT ( |
|
335 | PORT ( | |
340 | clk : IN STD_LOGIC; |
|
336 | clk : IN STD_LOGIC; | |
341 | rstn : IN STD_LOGIC; |
|
337 | rstn : IN STD_LOGIC; | |
342 | sample_B : IN Samples14v(2 DOWNTO 0); |
|
338 | sample_B : IN Samples14v(2 DOWNTO 0); | |
343 | sample_E : IN Samples14v(4 DOWNTO 0); |
|
339 | sample_E : IN Samples14v(4 DOWNTO 0); | |
344 | sample_val : IN STD_LOGIC; |
|
340 | sample_val : IN STD_LOGIC; | |
345 | apbi : IN apb_slv_in_type; |
|
341 | apbi : IN apb_slv_in_type; | |
346 | apbo : OUT apb_slv_out_type; |
|
342 | apbo : OUT apb_slv_out_type; | |
347 | ahbi_ms : IN AHB_Mst_In_Type; |
|
343 | ahbi_ms : IN AHB_Mst_In_Type; | |
348 | ahbo_ms : OUT AHB_Mst_Out_Type; |
|
344 | ahbo_ms : OUT AHB_Mst_Out_Type; | |
349 | data_shaping_BW : OUT STD_LOGIC; |
|
345 | data_shaping_BW : OUT STD_LOGIC; | |
350 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
346 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
351 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
347 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
352 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
348 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
353 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
349 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) | |
354 |
|
350 | |||
355 | ); |
|
351 | ); | |
356 | END COMPONENT; |
|
352 | END COMPONENT; | |
357 |
|
353 | |||
358 | COMPONENT lpp_apbreg_ms_pointer |
|
354 | COMPONENT lpp_apbreg_ms_pointer | |
359 | PORT ( |
|
355 | PORT ( | |
360 | clk : IN STD_LOGIC; |
|
356 | clk : IN STD_LOGIC; | |
361 | rstn : IN STD_LOGIC; |
|
357 | rstn : IN STD_LOGIC; | |
362 | reg0_status_ready_matrix : IN STD_LOGIC; |
|
358 | reg0_status_ready_matrix : IN STD_LOGIC; | |
363 | reg0_ready_matrix : OUT STD_LOGIC; |
|
359 | reg0_ready_matrix : OUT STD_LOGIC; | |
364 | reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
360 | reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
365 | reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
361 | reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
366 | reg1_status_ready_matrix : IN STD_LOGIC; |
|
362 | reg1_status_ready_matrix : IN STD_LOGIC; | |
367 | reg1_ready_matrix : OUT STD_LOGIC; |
|
363 | reg1_ready_matrix : OUT STD_LOGIC; | |
368 | reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
364 | reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
369 | reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
365 | reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
370 | ready_matrix : IN STD_LOGIC; |
|
366 | ready_matrix : IN STD_LOGIC; | |
371 | status_ready_matrix : OUT STD_LOGIC; |
|
367 | status_ready_matrix : OUT STD_LOGIC; | |
372 | addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
368 | addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
373 | matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0)); |
|
369 | matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0)); | |
374 | END COMPONENT; |
|
370 | END COMPONENT; | |
375 |
|
371 | |||
376 | COMPONENT lpp_lfr_ms_reg_head |
|
372 | COMPONENT lpp_lfr_ms_reg_head | |
377 | PORT ( |
|
373 | PORT ( | |
378 | clk : IN STD_LOGIC; |
|
374 | clk : IN STD_LOGIC; | |
379 | rstn : IN STD_LOGIC; |
|
375 | rstn : IN STD_LOGIC; | |
380 | in_wen : IN STD_LOGIC; |
|
376 | in_wen : IN STD_LOGIC; | |
381 | in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); |
|
377 | in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); | |
382 | in_full : IN STD_LOGIC; |
|
378 | in_full : IN STD_LOGIC; | |
383 | in_empty : IN STD_LOGIC; |
|
379 | in_empty : IN STD_LOGIC; | |
384 | out_wen : OUT STD_LOGIC; |
|
380 | out_wen : OUT STD_LOGIC; | |
385 | out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); |
|
381 | out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); | |
386 | out_full : OUT STD_LOGIC); |
|
382 | out_full : OUT STD_LOGIC); | |
387 | END COMPONENT; |
|
383 | END COMPONENT; | |
388 |
|
384 | |||
389 | END lpp_lfr_pkg; |
|
385 | END lpp_lfr_pkg; |
@@ -1,264 +1,265 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Jean-christophe PELLION |
|
19 | -- Author : Jean-christophe PELLION | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | LIBRARY IEEE; |
|
22 | LIBRARY IEEE; | |
23 | USE IEEE.std_logic_1164.ALL; |
|
23 | USE IEEE.std_logic_1164.ALL; | |
24 | USE IEEE.numeric_std.ALL; |
|
24 | USE IEEE.numeric_std.ALL; | |
25 |
|
25 | |||
26 | LIBRARY lpp; |
|
26 | LIBRARY lpp; | |
27 | USE lpp.lpp_waveform_pkg.ALL; |
|
27 | USE lpp.lpp_waveform_pkg.ALL; | |
28 | USE lpp.general_purpose.ALL; |
|
28 | USE lpp.general_purpose.ALL; | |
29 |
|
29 | |||
30 | ENTITY lpp_waveform_fifo_arbiter IS |
|
30 | ENTITY lpp_waveform_fifo_arbiter IS | |
31 | GENERIC( |
|
31 | GENERIC( | |
32 | tech : INTEGER := 0; |
|
32 | tech : INTEGER := 0; | |
33 | nb_data_by_buffer_size : INTEGER := 11 |
|
33 | nb_data_by_buffer_size : INTEGER := 11 | |
34 | ); |
|
34 | ); | |
35 | PORT( |
|
35 | PORT( | |
36 | clk : IN STD_LOGIC; |
|
36 | clk : IN STD_LOGIC; | |
37 | rstn : IN STD_LOGIC; |
|
37 | rstn : IN STD_LOGIC; | |
38 | --------------------------------------------------------------------------- |
|
38 | --------------------------------------------------------------------------- | |
39 | run : IN STD_LOGIC; |
|
39 | run : IN STD_LOGIC; | |
40 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0); |
|
40 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0); | |
41 | --------------------------------------------------------------------------- |
|
41 | --------------------------------------------------------------------------- | |
42 | -- SNAPSHOT INTERFACE (INPUT) |
|
42 | -- SNAPSHOT INTERFACE (INPUT) | |
43 | --------------------------------------------------------------------------- |
|
43 | --------------------------------------------------------------------------- | |
44 | data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
44 | data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
45 | data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
45 | data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
46 | data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); |
|
46 | data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); | |
47 |
|
47 | |||
48 | time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); |
|
48 | time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); | |
49 |
|
49 | |||
50 | --------------------------------------------------------------------------- |
|
50 | --------------------------------------------------------------------------- | |
51 | -- FIFO INTERFACE (OUTPUT) |
|
51 | -- FIFO INTERFACE (OUTPUT) | |
52 | --------------------------------------------------------------------------- |
|
52 | --------------------------------------------------------------------------- | |
53 | data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
53 | data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
54 | data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
54 | data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
55 | full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
55 | full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
56 | full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
56 | full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
57 |
|
57 | |||
58 | --------------------------------------------------------------------------- |
|
58 | --------------------------------------------------------------------------- | |
59 | -- TIME INTERFACE (OUTPUT) |
|
59 | -- TIME INTERFACE (OUTPUT) | |
60 | --------------------------------------------------------------------------- |
|
60 | --------------------------------------------------------------------------- | |
61 | time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
61 | time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
62 | time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) |
|
62 | time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) | |
63 |
|
63 | |||
64 | ); |
|
64 | ); | |
65 | END ENTITY; |
|
65 | END ENTITY; | |
66 |
|
66 | |||
67 |
|
67 | |||
68 | ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS |
|
68 | ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS | |
69 | TYPE state_type_fifo_arbiter IS (IDLE,DATA1,DATA2,DATA3,LAST); |
|
69 | TYPE state_type_fifo_arbiter IS (IDLE,DATA1,DATA2,DATA3,LAST); | |
70 | SIGNAL state : state_type_fifo_arbiter; |
|
70 | SIGNAL state : state_type_fifo_arbiter; | |
71 |
|
71 | |||
72 | ----------------------------------------------------------------------------- |
|
72 | ----------------------------------------------------------------------------- | |
73 | -- DATA MUX |
|
73 | -- DATA MUX | |
74 | ----------------------------------------------------------------------------- |
|
74 | ----------------------------------------------------------------------------- | |
75 | TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
75 | TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0); | |
76 | SIGNAL data_0 : WORD_VECTOR(3 DOWNTO 0); |
|
76 | SIGNAL data_0 : WORD_VECTOR(3 DOWNTO 0); | |
77 | SIGNAL data_1 : WORD_VECTOR(3 DOWNTO 0); |
|
77 | SIGNAL data_1 : WORD_VECTOR(3 DOWNTO 0); | |
78 | SIGNAL data_2 : WORD_VECTOR(3 DOWNTO 0); |
|
78 | SIGNAL data_2 : WORD_VECTOR(3 DOWNTO 0); | |
79 | SIGNAL data_3 : WORD_VECTOR(3 DOWNTO 0); |
|
79 | SIGNAL data_3 : WORD_VECTOR(3 DOWNTO 0); | |
80 | SIGNAL data_sel : WORD_VECTOR(3 DOWNTO 0); |
|
80 | SIGNAL data_sel : WORD_VECTOR(3 DOWNTO 0); | |
81 |
|
81 | |||
82 | ----------------------------------------------------------------------------- |
|
82 | ----------------------------------------------------------------------------- | |
83 | -- RR and SELECTION |
|
83 | -- RR and SELECTION | |
84 | ----------------------------------------------------------------------------- |
|
84 | ----------------------------------------------------------------------------- | |
85 | SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
85 | SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
86 | SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
86 | SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
87 | SIGNAL sel_s : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
87 | SIGNAL sel_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
88 | SIGNAL sel_reg : STD_LOGIC; |
|
88 | SIGNAL sel_reg : STD_LOGIC; | |
89 | SIGNAL sel_ack : STD_LOGIC; |
|
89 | SIGNAL sel_ack : STD_LOGIC; | |
90 | SIGNAL no_sel : STD_LOGIC; |
|
90 | SIGNAL no_sel : STD_LOGIC; | |
91 |
|
91 | |||
92 | ----------------------------------------------------------------------------- |
|
92 | ----------------------------------------------------------------------------- | |
93 | -- REG |
|
93 | -- REG | |
94 | ----------------------------------------------------------------------------- |
|
94 | ----------------------------------------------------------------------------- | |
95 | SIGNAL count_enable : STD_LOGIC; |
|
95 | SIGNAL count_enable : STD_LOGIC; | |
96 | SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
96 | SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
97 | SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
97 | SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
98 |
|
98 | |||
99 | SIGNAL time_sel : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
99 | SIGNAL time_sel : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
100 |
|
100 | |||
101 | BEGIN |
|
101 | BEGIN | |
102 |
|
102 | |||
103 | ----------------------------------------------------------------------------- |
|
103 | ----------------------------------------------------------------------------- | |
104 | -- CONTROL |
|
104 | -- CONTROL | |
105 | ----------------------------------------------------------------------------- |
|
105 | ----------------------------------------------------------------------------- | |
106 | PROCESS (clk, rstn) |
|
106 | PROCESS (clk, rstn) | |
107 | BEGIN -- PROCESS |
|
107 | BEGIN -- PROCESS | |
108 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
108 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
109 | count_enable <= '0'; |
|
109 | count_enable <= '0'; | |
110 | data_in_ack <= (OTHERS => '0'); |
|
110 | data_in_ack <= (OTHERS => '0'); | |
111 | data_out_wen <= (OTHERS => '1'); |
|
111 | data_out_wen <= (OTHERS => '1'); | |
112 | sel_ack <= '0'; |
|
112 | sel_ack <= '0'; | |
113 | state <= IDLE; |
|
113 | state <= IDLE; | |
114 | time_out <= (OTHERS => '0'); |
|
114 | time_out <= (OTHERS => '0'); | |
115 | time_out_new <= (OTHERS => '0'); |
|
115 | time_out_new <= (OTHERS => '0'); | |
116 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
116 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
117 | count_enable <= '0'; |
|
117 | count_enable <= '0'; | |
118 | data_in_ack <= (OTHERS => '0'); |
|
118 | data_in_ack <= (OTHERS => '0'); | |
119 | data_out_wen <= (OTHERS => '1'); |
|
119 | data_out_wen <= (OTHERS => '1'); | |
120 | sel_ack <= '0'; |
|
120 | sel_ack <= '0'; | |
121 | time_out_new <= (OTHERS => '0'); |
|
121 | time_out_new <= (OTHERS => '0'); | |
122 | IF run = '0' THEN |
|
122 | IF run = '0' THEN | |
123 | state <= IDLE; |
|
123 | state <= IDLE; | |
124 | time_out <= (OTHERS => '0'); |
|
124 | time_out <= (OTHERS => '0'); | |
125 | ELSE |
|
125 | ELSE | |
126 | CASE state IS |
|
126 | CASE state IS | |
127 | WHEN IDLE => |
|
127 | WHEN IDLE => | |
128 | IF no_sel = '0' THEN |
|
128 | IF no_sel = '0' THEN | |
129 | state <= DATA1; |
|
129 | state <= DATA1; | |
130 | END IF; |
|
130 | END IF; | |
131 | WHEN DATA1 => |
|
131 | WHEN DATA1 => | |
132 | count_enable <= '1'; |
|
132 | count_enable <= '1'; | |
133 | IF UNSIGNED(count) = 0 THEN |
|
133 | IF UNSIGNED(count) = 0 THEN | |
134 | time_out <= time_sel; |
|
134 | time_out <= time_sel; | |
135 | time_out_new <= sel; |
|
135 | time_out_new <= sel; | |
136 | END IF; |
|
136 | END IF; | |
137 | data_out_wen <= NOT sel; |
|
137 | data_out_wen <= NOT sel; | |
138 | data_out <= data_sel(0); |
|
138 | data_out <= data_sel(0); | |
139 | state <= DATA2; |
|
139 | state <= DATA2; | |
140 | WHEN DATA2 => |
|
140 | WHEN DATA2 => | |
141 | data_out_wen <= NOT sel; |
|
141 | data_out_wen <= NOT sel; | |
142 | data_out <= data_sel(1); |
|
142 | data_out <= data_sel(1); | |
143 | state <= DATA3; |
|
143 | state <= DATA3; | |
144 | WHEN DATA3 => |
|
144 | WHEN DATA3 => | |
145 | data_out_wen <= NOT sel; |
|
145 | data_out_wen <= NOT sel; | |
146 | data_out <= data_sel(2); |
|
146 | data_out <= data_sel(2); | |
147 | state <= LAST; |
|
147 | state <= LAST; | |
148 | data_in_ack <= sel; |
|
148 | data_in_ack <= sel; | |
149 | WHEN LAST => |
|
149 | WHEN LAST => | |
150 | state <= IDLE; |
|
150 | state <= IDLE; | |
151 | sel_ack <= '1'; |
|
151 | sel_ack <= '1'; | |
152 |
|
152 | |||
153 | WHEN OTHERS => NULL; |
|
153 | WHEN OTHERS => NULL; | |
154 | END CASE; |
|
154 | END CASE; | |
155 | END IF; |
|
155 | END IF; | |
156 | END IF; |
|
156 | END IF; | |
157 | END PROCESS; |
|
157 | END PROCESS; | |
158 | ----------------------------------------------------------------------------- |
|
158 | ----------------------------------------------------------------------------- | |
159 |
|
159 | |||
160 | ----------------------------------------------------------------------------- |
|
160 | ----------------------------------------------------------------------------- | |
161 | -- DATA MUX |
|
161 | -- DATA MUX | |
162 | ----------------------------------------------------------------------------- |
|
162 | ----------------------------------------------------------------------------- | |
163 |
|
163 | |||
164 | all_word: FOR J IN 2 DOWNTO 0 GENERATE |
|
164 | all_word: FOR J IN 2 DOWNTO 0 GENERATE | |
165 | all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE |
|
165 | all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE | |
166 | data_0(J)(I) <= data_in(0,I+32*J); |
|
166 | data_0(J)(I) <= data_in(0,I+32*J); | |
167 | data_1(J)(I) <= data_in(1,I+32*J); |
|
167 | data_1(J)(I) <= data_in(1,I+32*J); | |
168 | data_2(J)(I) <= data_in(2,I+32*J); |
|
168 | data_2(J)(I) <= data_in(2,I+32*J); | |
169 | data_3(J)(I) <= data_in(3,I+32*J); |
|
169 | data_3(J)(I) <= data_in(3,I+32*J); | |
170 | END GENERATE all_data_bit; |
|
170 | END GENERATE all_data_bit; | |
171 | END GENERATE all_word; |
|
171 | END GENERATE all_word; | |
172 |
|
172 | |||
173 | data_sel <= data_0 WHEN sel(0) = '1' ELSE |
|
173 | data_sel <= data_0 WHEN sel(0) = '1' ELSE | |
174 | data_1 WHEN sel(1) = '1' ELSE |
|
174 | data_1 WHEN sel(1) = '1' ELSE | |
175 | data_2 WHEN sel(2) = '1' ELSE |
|
175 | data_2 WHEN sel(2) = '1' ELSE | |
176 | data_3; |
|
176 | data_3; | |
177 |
|
177 | |||
178 |
all_time_bit: FOR I IN |
|
178 | all_time_bit: FOR I IN 47 DOWNTO 0 GENERATE | |
|
179 | ||||
179 |
|
|
180 | time_sel(I) <= time_in(0,I) WHEN sel(0) = '1' ELSE | |
180 | time_in(1,I) WHEN sel(1) = '1' ELSE |
|
181 | time_in(1,I) WHEN sel(1) = '1' ELSE | |
181 | time_in(2,I) WHEN sel(2) = '1' ELSE |
|
182 | time_in(2,I) WHEN sel(2) = '1' ELSE | |
182 | time_in(3,I); |
|
183 | time_in(3,I); | |
183 | END GENERATE all_time_bit; |
|
184 | END GENERATE all_time_bit; | |
184 |
|
185 | |||
185 |
|
186 | |||
186 | ----------------------------------------------------------------------------- |
|
187 | ----------------------------------------------------------------------------- | |
187 | -- RR and SELECTION |
|
188 | -- RR and SELECTION | |
188 | ----------------------------------------------------------------------------- |
|
189 | ----------------------------------------------------------------------------- | |
189 | all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE |
|
190 | all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE | |
190 | valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I); |
|
191 | valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I); | |
191 | END GENERATE all_input_rr; |
|
192 | END GENERATE all_input_rr; | |
192 |
|
193 | |||
193 | RR_Arbiter_4_1 : RR_Arbiter_4 |
|
194 | RR_Arbiter_4_1 : RR_Arbiter_4 | |
194 | PORT MAP ( |
|
195 | PORT MAP ( | |
195 | clk => clk, |
|
196 | clk => clk, | |
196 | rstn => rstn, |
|
197 | rstn => rstn, | |
197 | in_valid => valid_in_rr, |
|
198 | in_valid => valid_in_rr, | |
198 | out_grant => sel_s); |
|
199 | out_grant => sel_s); | |
199 |
|
200 | |||
200 | PROCESS (clk, rstn) |
|
201 | PROCESS (clk, rstn) | |
201 | BEGIN -- PROCESS |
|
202 | BEGIN -- PROCESS | |
202 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
203 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
203 | sel <= "0000"; |
|
204 | sel <= "0000"; | |
204 | sel_reg <= '0'; |
|
205 | sel_reg <= '0'; | |
205 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
206 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
206 | IF sel_reg = '0' OR sel_ack = '1' THEN |
|
207 | IF sel_reg = '0' OR sel_ack = '1' THEN | |
207 | sel <= sel_s; |
|
208 | sel <= sel_s; | |
208 | IF sel_s = "0000" THEN |
|
209 | IF sel_s = "0000" THEN | |
209 | sel_reg <= '0'; |
|
210 | sel_reg <= '0'; | |
210 | ELSE |
|
211 | ELSE | |
211 | sel_reg <= '1'; |
|
212 | sel_reg <= '1'; | |
212 | END IF; |
|
213 | END IF; | |
213 | END IF; |
|
214 | END IF; | |
214 | END IF; |
|
215 | END IF; | |
215 | END PROCESS; |
|
216 | END PROCESS; | |
216 |
|
217 | |||
217 | no_sel <= '1' WHEN sel = "0000" ELSE '0'; |
|
218 | no_sel <= '1' WHEN sel = "0000" ELSE '0'; | |
218 |
|
219 | |||
219 | ----------------------------------------------------------------------------- |
|
220 | ----------------------------------------------------------------------------- | |
220 | -- REG |
|
221 | -- REG | |
221 | ----------------------------------------------------------------------------- |
|
222 | ----------------------------------------------------------------------------- | |
222 | reg_count_i: lpp_waveform_fifo_arbiter_reg |
|
223 | reg_count_i: lpp_waveform_fifo_arbiter_reg | |
223 | GENERIC MAP ( |
|
224 | GENERIC MAP ( | |
224 | data_size => nb_data_by_buffer_size, |
|
225 | data_size => nb_data_by_buffer_size, | |
225 | data_nb => 4) |
|
226 | data_nb => 4) | |
226 | PORT MAP ( |
|
227 | PORT MAP ( | |
227 | clk => clk, |
|
228 | clk => clk, | |
228 | rstn => rstn, |
|
229 | rstn => rstn, | |
229 | run => run, |
|
230 | run => run, | |
230 | max_count => nb_data_by_buffer, |
|
231 | max_count => nb_data_by_buffer, | |
231 | enable => count_enable, |
|
232 | enable => count_enable, | |
232 | sel => sel, |
|
233 | sel => sel, | |
233 | data => count, |
|
234 | data => count, | |
234 | data_s => count_s); |
|
235 | data_s => count_s); | |
235 |
|
236 | |||
236 |
|
237 | |||
237 |
|
238 | |||
238 |
|
239 | |||
239 | END ARCHITECTURE; |
|
240 | END ARCHITECTURE; | |
240 |
|
241 | |||
241 |
|
242 | |||
242 |
|
243 | |||
243 |
|
244 | |||
244 |
|
245 | |||
245 |
|
246 | |||
246 |
|
247 | |||
247 |
|
248 | |||
248 |
|
249 | |||
249 |
|
250 | |||
250 |
|
251 | |||
251 |
|
252 | |||
252 |
|
253 | |||
253 |
|
254 | |||
254 |
|
255 | |||
255 |
|
256 | |||
256 |
|
257 | |||
257 |
|
258 | |||
258 |
|
259 | |||
259 |
|
260 | |||
260 |
|
261 | |||
261 |
|
262 | |||
262 |
|
263 | |||
263 |
|
264 | |||
264 |
|
265 |
@@ -1,117 +1,116 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Jean-christophe PELLION |
|
19 | -- Author : Jean-christophe PELLION | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | LIBRARY IEEE; |
|
22 | LIBRARY IEEE; | |
23 | USE IEEE.std_logic_1164.ALL; |
|
23 | USE IEEE.std_logic_1164.ALL; | |
24 | USE IEEE.numeric_std.ALL; |
|
24 | USE IEEE.numeric_std.ALL; | |
25 |
|
25 | |||
26 | LIBRARY lpp; |
|
26 | LIBRARY lpp; | |
27 | USE lpp.lpp_waveform_pkg.ALL; |
|
27 | USE lpp.lpp_waveform_pkg.ALL; | |
28 | USE lpp.general_purpose.ALL; |
|
28 | USE lpp.general_purpose.ALL; | |
29 |
|
29 | |||
30 | ENTITY lpp_waveform_fifo_arbiter_reg IS |
|
30 | ENTITY lpp_waveform_fifo_arbiter_reg IS | |
31 | GENERIC( |
|
31 | GENERIC( | |
32 | data_size : INTEGER; |
|
32 | data_size : INTEGER; | |
33 | data_nb : INTEGER |
|
33 | data_nb : INTEGER); | |
34 | ); |
|
|||
35 | PORT( |
|
34 | PORT( | |
36 |
clk |
|
35 | clk : IN STD_LOGIC; | |
37 |
rstn |
|
36 | rstn : IN STD_LOGIC; | |
38 | --------------------------------------------------------------------------- |
|
37 | --------------------------------------------------------------------------- | |
39 |
run |
|
38 | run : IN STD_LOGIC; | |
40 |
|
39 | |||
41 | max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0); |
|
40 | max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0); | |
42 |
|
41 | |||
43 | enable : IN STD_LOGIC; |
|
42 | enable : IN STD_LOGIC; | |
44 | sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0); |
|
43 | sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0); | |
45 |
|
44 | |||
46 | data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
45 | data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
47 | data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0) |
|
46 | data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0) | |
48 | ); |
|
47 | ); | |
49 | END ENTITY; |
|
48 | END ENTITY; | |
50 |
|
49 | |||
51 |
|
50 | |||
52 | ARCHITECTURE ar_lpp_waveform_fifo_arbiter_reg OF lpp_waveform_fifo_arbiter_reg IS |
|
51 | ARCHITECTURE ar_lpp_waveform_fifo_arbiter_reg OF lpp_waveform_fifo_arbiter_reg IS | |
53 |
|
52 | |||
54 | TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; |
|
53 | TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; | |
55 | SIGNAL reg : Counter_Vector(data_nb-1 DOWNTO 0); |
|
54 | SIGNAL reg : Counter_Vector(data_nb-1 DOWNTO 0); | |
56 |
|
55 | |||
57 | SIGNAL reg_sel : INTEGER := 0; |
|
56 | SIGNAL reg_sel : INTEGER := 0; | |
58 | SIGNAL reg_sel_s : INTEGER := 0; |
|
57 | SIGNAL reg_sel_s : INTEGER := 0; | |
59 |
|
58 | |||
60 | BEGIN |
|
59 | BEGIN | |
61 |
|
60 | |||
62 | all_reg: FOR I IN data_nb-1 DOWNTO 0 GENERATE |
|
61 | all_reg : FOR I IN data_nb-1 DOWNTO 0 GENERATE | |
63 | PROCESS (clk, rstn) |
|
62 | PROCESS (clk, rstn) | |
64 | BEGIN -- PROCESS |
|
63 | BEGIN -- PROCESS | |
65 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
64 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
66 | reg(I) <= 0; |
|
65 | reg(I) <= 0; | |
67 |
ELSIF clk' |
|
66 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
68 | IF run = '0' THEN |
|
67 | IF run = '0' THEN | |
69 | reg(I) <= 0; |
|
68 | reg(I) <= 0; | |
70 | ELSE |
|
69 | ELSE | |
71 | IF sel(I) = '1' THEN |
|
70 | IF sel(I) = '1' THEN | |
72 | reg(I) <= reg_sel_s; |
|
71 | reg(I) <= reg_sel_s; | |
73 | END IF; |
|
72 | END IF; | |
74 |
END IF; |
|
73 | END IF; | |
75 | END IF; |
|
74 | END IF; | |
76 | END PROCESS; |
|
75 | END PROCESS; | |
77 | END GENERATE all_reg; |
|
76 | END GENERATE all_reg; | |
78 |
|
77 | |||
79 | reg_sel <= reg(0) WHEN sel(0) = '1' ELSE |
|
78 | reg_sel <= reg(0) WHEN sel(0) = '1' ELSE | |
80 | reg(1) WHEN sel(1) = '1' ELSE |
|
79 | reg(1) WHEN sel(1) = '1' ELSE | |
81 | reg(2) WHEN sel(2) = '1' ELSE |
|
80 | reg(2) WHEN sel(2) = '1' ELSE | |
82 | reg(3); |
|
81 | reg(3); | |
83 |
|
82 | |||
84 |
reg_sel_s <= reg_sel |
|
83 | reg_sel_s <= reg_sel WHEN enable = '0' ELSE | |
85 | reg_sel + 1 WHEN reg_sel < UNSIGNED(max_count) ELSE |
|
84 | reg_sel + 1 WHEN reg_sel < UNSIGNED(max_count) ELSE | |
86 | 0; |
|
85 | 0; | |
87 |
|
86 | |||
88 |
data <= STD_LOGIC_VECTOR(to_unsigned(reg_sel |
|
87 | data <= STD_LOGIC_VECTOR(to_unsigned(reg_sel , data_size)); | |
89 | data_s <= STD_LOGIC_VECTOR(to_unsigned(reg_sel_s,data_size)); |
|
88 | data_s <= STD_LOGIC_VECTOR(to_unsigned(reg_sel_s, data_size)); | |
90 |
|
89 | |||
91 | END ARCHITECTURE; |
|
90 | END ARCHITECTURE; | |
92 |
|
91 | |||
93 |
|
92 | |||
94 |
|
93 | |||
95 |
|
94 | |||
96 |
|
95 | |||
97 |
|
96 | |||
98 |
|
97 | |||
99 |
|
98 | |||
100 |
|
99 | |||
101 |
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100 | |||
102 |
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101 | |||
103 |
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102 | |||
104 |
|
103 | |||
105 |
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104 | |||
106 |
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105 | |||
107 |
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106 | |||
108 |
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107 | |||
109 |
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108 | |||
110 |
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109 | |||
111 |
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110 | |||
112 |
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111 | |||
113 |
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112 | |||
114 |
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113 | |||
115 |
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114 | |||
116 |
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115 | |||
117 |
|
116 |
@@ -1,392 +1,370 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | -- jean-christophe.pellion@easii-ic.com |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
22 | ------------------------------------------------------------------------------- |
|
22 | ------------------------------------------------------------------------------- | |
23 | LIBRARY IEEE; |
|
23 | LIBRARY IEEE; | |
24 | USE IEEE.STD_LOGIC_1164.ALL; |
|
24 | USE IEEE.STD_LOGIC_1164.ALL; | |
25 |
|
25 | |||
26 | LIBRARY grlib; |
|
26 | LIBRARY grlib; | |
27 | USE grlib.amba.ALL; |
|
27 | USE grlib.amba.ALL; | |
28 | USE grlib.stdlib.ALL; |
|
28 | USE grlib.stdlib.ALL; | |
29 | USE grlib.devices.ALL; |
|
29 | USE grlib.devices.ALL; | |
30 | USE GRLIB.DMA2AHB_Package.ALL; |
|
30 | USE GRLIB.DMA2AHB_Package.ALL; | |
31 |
|
31 | |||
32 | LIBRARY techmap; |
|
32 | LIBRARY techmap; | |
33 | USE techmap.gencomp.ALL; |
|
33 | USE techmap.gencomp.ALL; | |
34 |
|
34 | |||
35 | PACKAGE lpp_waveform_pkg IS |
|
35 | PACKAGE lpp_waveform_pkg IS | |
36 |
|
36 | |||
37 | TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0); |
|
37 | TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0); | |
38 |
|
38 | |||
39 | TYPE Data_Vector IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; |
|
39 | TYPE Data_Vector IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; | |
40 |
|
40 | |||
41 | ----------------------------------------------------------------------------- |
|
41 | ----------------------------------------------------------------------------- | |
42 | -- SNAPSHOT |
|
42 | -- SNAPSHOT | |
43 | ----------------------------------------------------------------------------- |
|
43 | ----------------------------------------------------------------------------- | |
44 |
|
44 | |||
45 | COMPONENT lpp_waveform_snapshot |
|
45 | COMPONENT lpp_waveform_snapshot | |
46 | GENERIC ( |
|
46 | GENERIC ( | |
47 | data_size : INTEGER; |
|
47 | data_size : INTEGER; | |
48 | nb_snapshot_param_size : INTEGER); |
|
48 | nb_snapshot_param_size : INTEGER); | |
49 | PORT ( |
|
49 | PORT ( | |
50 | clk : IN STD_LOGIC; |
|
50 | clk : IN STD_LOGIC; | |
51 | rstn : IN STD_LOGIC; |
|
51 | rstn : IN STD_LOGIC; | |
52 | run : IN STD_LOGIC; |
|
52 | run : IN STD_LOGIC; | |
53 | enable : IN STD_LOGIC; |
|
53 | enable : IN STD_LOGIC; | |
54 | burst_enable : IN STD_LOGIC; |
|
54 | burst_enable : IN STD_LOGIC; | |
55 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
55 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
56 | start_snapshot : IN STD_LOGIC; |
|
56 | start_snapshot : IN STD_LOGIC; | |
57 | data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
57 | data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
58 | data_in_valid : IN STD_LOGIC; |
|
58 | data_in_valid : IN STD_LOGIC; | |
59 | data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
59 | data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
60 | data_out_valid : OUT STD_LOGIC); |
|
60 | data_out_valid : OUT STD_LOGIC); | |
61 | END COMPONENT; |
|
61 | END COMPONENT; | |
62 |
|
62 | |||
63 | COMPONENT lpp_waveform_burst |
|
63 | COMPONENT lpp_waveform_burst | |
64 | GENERIC ( |
|
64 | GENERIC ( | |
65 | data_size : INTEGER); |
|
65 | data_size : INTEGER); | |
66 | PORT ( |
|
66 | PORT ( | |
67 | clk : IN STD_LOGIC; |
|
67 | clk : IN STD_LOGIC; | |
68 | rstn : IN STD_LOGIC; |
|
68 | rstn : IN STD_LOGIC; | |
69 | run : IN STD_LOGIC; |
|
69 | run : IN STD_LOGIC; | |
70 | enable : IN STD_LOGIC; |
|
70 | enable : IN STD_LOGIC; | |
71 | data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
71 | data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
72 | data_in_valid : IN STD_LOGIC; |
|
72 | data_in_valid : IN STD_LOGIC; | |
73 | data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
73 | data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
74 | data_out_valid : OUT STD_LOGIC); |
|
74 | data_out_valid : OUT STD_LOGIC); | |
75 | END COMPONENT; |
|
75 | END COMPONENT; | |
76 |
|
76 | |||
77 | COMPONENT lpp_waveform_snapshot_controler |
|
77 | COMPONENT lpp_waveform_snapshot_controler | |
78 | GENERIC ( |
|
78 | GENERIC ( | |
79 | delta_vector_size : INTEGER; |
|
79 | delta_vector_size : INTEGER; | |
80 | delta_vector_size_f0_2 : INTEGER); |
|
80 | delta_vector_size_f0_2 : INTEGER); | |
81 | PORT ( |
|
81 | PORT ( | |
82 | clk : IN STD_LOGIC; |
|
82 | clk : IN STD_LOGIC; | |
83 | rstn : IN STD_LOGIC; |
|
83 | rstn : IN STD_LOGIC; | |
84 | reg_run : IN STD_LOGIC; |
|
84 | reg_run : IN STD_LOGIC; | |
85 | reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
85 | reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); | |
86 | reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
86 | reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
87 | reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
87 | reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
88 | reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
88 | reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
89 | reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
89 | reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
90 | reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
90 | reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
91 | coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
91 | coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0); | |
92 | data_f0_valid : IN STD_LOGIC; |
|
92 | data_f0_valid : IN STD_LOGIC; | |
93 | data_f2_valid : IN STD_LOGIC; |
|
93 | data_f2_valid : IN STD_LOGIC; | |
94 | start_snapshot_f0 : OUT STD_LOGIC; |
|
94 | start_snapshot_f0 : OUT STD_LOGIC; | |
95 | start_snapshot_f1 : OUT STD_LOGIC; |
|
95 | start_snapshot_f1 : OUT STD_LOGIC; | |
96 | start_snapshot_f2 : OUT STD_LOGIC; |
|
96 | start_snapshot_f2 : OUT STD_LOGIC; | |
97 | wfp_on : OUT STD_LOGIC); |
|
97 | wfp_on : OUT STD_LOGIC); | |
98 | END COMPONENT; |
|
98 | END COMPONENT; | |
99 |
|
99 | |||
100 | ----------------------------------------------------------------------------- |
|
100 | ----------------------------------------------------------------------------- | |
101 | -- |
|
101 | -- | |
102 | ----------------------------------------------------------------------------- |
|
102 | ----------------------------------------------------------------------------- | |
103 | COMPONENT lpp_waveform |
|
103 | COMPONENT lpp_waveform | |
104 | GENERIC ( |
|
104 | GENERIC ( | |
105 | tech : INTEGER; |
|
105 | tech : INTEGER; | |
106 | data_size : INTEGER; |
|
106 | data_size : INTEGER; | |
107 | nb_data_by_buffer_size : INTEGER; |
|
107 | nb_data_by_buffer_size : INTEGER; | |
108 | nb_snapshot_param_size : INTEGER; |
|
108 | nb_snapshot_param_size : INTEGER; | |
109 | delta_vector_size : INTEGER; |
|
109 | delta_vector_size : INTEGER; | |
110 | delta_vector_size_f0_2 : INTEGER); |
|
110 | delta_vector_size_f0_2 : INTEGER); | |
111 | PORT ( |
|
111 | PORT ( | |
112 | clk : IN STD_LOGIC; |
|
112 | clk : IN STD_LOGIC; | |
113 | rstn : IN STD_LOGIC; |
|
113 | rstn : IN STD_LOGIC; | |
114 | reg_run : IN STD_LOGIC; |
|
114 | reg_run : IN STD_LOGIC; | |
115 | reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
115 | reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); | |
116 | reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
116 | reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
117 | reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
117 | reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
118 | reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
118 | reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
119 | reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
119 | reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
120 | reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
120 | reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
121 | enable_f0 : IN STD_LOGIC; |
|
121 | enable_f0 : IN STD_LOGIC; | |
122 | enable_f1 : IN STD_LOGIC; |
|
122 | enable_f1 : IN STD_LOGIC; | |
123 | enable_f2 : IN STD_LOGIC; |
|
123 | enable_f2 : IN STD_LOGIC; | |
124 | enable_f3 : IN STD_LOGIC; |
|
124 | enable_f3 : IN STD_LOGIC; | |
125 | burst_f0 : IN STD_LOGIC; |
|
125 | burst_f0 : IN STD_LOGIC; | |
126 | burst_f1 : IN STD_LOGIC; |
|
126 | burst_f1 : IN STD_LOGIC; | |
127 | burst_f2 : IN STD_LOGIC; |
|
127 | burst_f2 : IN STD_LOGIC; | |
128 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
128 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
129 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
129 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
130 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
130 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
131 | status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
131 | status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
132 | addr_buffer : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0); |
|
132 | addr_buffer : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0); | |
133 | length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
133 | length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0); | |
134 | ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
134 | ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
135 | buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
|
135 | buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |
136 | error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
136 | error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
137 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
137 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
138 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
138 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
139 | data_f0_in_valid : IN STD_LOGIC; |
|
139 | data_f0_in_valid : IN STD_LOGIC; | |
140 | data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
140 | data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
141 | data_f1_in_valid : IN STD_LOGIC; |
|
141 | data_f1_in_valid : IN STD_LOGIC; | |
142 | data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
142 | data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
143 | data_f2_in_valid : IN STD_LOGIC; |
|
143 | data_f2_in_valid : IN STD_LOGIC; | |
144 | data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
144 | data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
145 | data_f3_in_valid : IN STD_LOGIC; |
|
145 | data_f3_in_valid : IN STD_LOGIC; | |
146 | data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
146 | data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
147 | data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
148 | data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
149 | data_f0_data_out_valid : OUT STD_LOGIC; |
|
|||
150 | data_f0_data_out_valid_burst : OUT STD_LOGIC; |
|
|||
151 | data_f0_data_out_ren : IN STD_LOGIC; |
|
|||
152 | data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
153 | data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
154 | data_f1_data_out_valid : OUT STD_LOGIC; |
|
|||
155 | data_f1_data_out_valid_burst : OUT STD_LOGIC; |
|
|||
156 | data_f1_data_out_ren : IN STD_LOGIC; |
|
|||
157 | data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
158 | data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
159 | data_f2_data_out_valid : OUT STD_LOGIC; |
|
|||
160 | data_f2_data_out_valid_burst : OUT STD_LOGIC; |
|
|||
161 | data_f2_data_out_ren : IN STD_LOGIC; |
|
|||
162 | data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
163 | data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
164 | data_f3_data_out_valid : OUT STD_LOGIC; |
|
|||
165 | data_f3_data_out_valid_burst : OUT STD_LOGIC; |
|
|||
166 | data_f3_data_out_ren : IN STD_LOGIC; |
|
|||
167 |
|
147 | |||
168 | dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
148 | dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
169 | dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
|
149 | dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |
170 | dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
150 | dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
171 | dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
151 | dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
172 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
|
152 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |
173 | dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0); |
|
153 | dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0); | |
174 | dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
154 | dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
175 | dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0) |
|
155 | dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0) | |
176 | ); |
|
156 | ); | |
177 | END COMPONENT; |
|
157 | END COMPONENT; | |
178 |
|
158 | |||
179 | COMPONENT lpp_waveform_dma_genvalid |
|
159 | COMPONENT lpp_waveform_dma_genvalid | |
180 | PORT ( |
|
160 | PORT ( | |
181 | HCLK : IN STD_LOGIC; |
|
161 | HCLK : IN STD_LOGIC; | |
182 | HRESETn : IN STD_LOGIC; |
|
162 | HRESETn : IN STD_LOGIC; | |
183 | run : IN STD_LOGIC; |
|
163 | run : IN STD_LOGIC; | |
184 | valid_in : IN STD_LOGIC; |
|
164 | valid_in : IN STD_LOGIC; | |
185 | ack_in : IN STD_LOGIC; |
|
165 | ack_in : IN STD_LOGIC; | |
186 | time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
166 | time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
187 | valid_out : OUT STD_LOGIC; |
|
167 | valid_out : OUT STD_LOGIC; | |
188 | time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
168 | time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
189 | error : OUT STD_LOGIC); |
|
169 | error : OUT STD_LOGIC); | |
190 | END COMPONENT; |
|
170 | END COMPONENT; | |
191 |
|
171 | |||
192 | ----------------------------------------------------------------------------- |
|
172 | ----------------------------------------------------------------------------- | |
193 | -- FIFO |
|
173 | -- FIFO | |
194 | ----------------------------------------------------------------------------- |
|
174 | ----------------------------------------------------------------------------- | |
195 | COMPONENT lpp_waveform_fifo_ctrl |
|
175 | COMPONENT lpp_waveform_fifo_ctrl | |
196 | GENERIC ( |
|
176 | GENERIC ( | |
197 | offset : INTEGER; |
|
177 | offset : INTEGER; | |
198 | length : INTEGER); |
|
178 | length : INTEGER); | |
199 | PORT ( |
|
179 | PORT ( | |
200 | clk : IN STD_LOGIC; |
|
180 | clk : IN STD_LOGIC; | |
201 | rstn : IN STD_LOGIC; |
|
181 | rstn : IN STD_LOGIC; | |
202 | run : IN STD_LOGIC; |
|
182 | run : IN STD_LOGIC; | |
203 | ren : IN STD_LOGIC; |
|
183 | ren : IN STD_LOGIC; | |
204 | wen : IN STD_LOGIC; |
|
184 | wen : IN STD_LOGIC; | |
205 | mem_re : OUT STD_LOGIC; |
|
185 | mem_re : OUT STD_LOGIC; | |
206 | mem_we : OUT STD_LOGIC; |
|
186 | mem_we : OUT STD_LOGIC; | |
207 | mem_addr_ren : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); |
|
187 | mem_addr_ren : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); | |
208 | mem_addr_wen : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); |
|
188 | mem_addr_wen : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); | |
209 | empty_almost : OUT STD_LOGIC; |
|
189 | empty_almost : OUT STD_LOGIC; | |
210 | empty : OUT STD_LOGIC; |
|
190 | empty : OUT STD_LOGIC; | |
211 | full_almost : OUT STD_LOGIC; |
|
191 | full_almost : OUT STD_LOGIC; | |
212 | full : OUT STD_LOGIC); |
|
192 | full : OUT STD_LOGIC); | |
213 | END COMPONENT; |
|
193 | END COMPONENT; | |
214 |
|
194 | |||
215 | COMPONENT lpp_waveform_fifo_arbiter |
|
195 | COMPONENT lpp_waveform_fifo_arbiter | |
216 | GENERIC ( |
|
196 | GENERIC ( | |
217 | tech : INTEGER; |
|
197 | tech : INTEGER; | |
218 | nb_data_by_buffer_size : INTEGER); |
|
198 | nb_data_by_buffer_size : INTEGER); | |
219 | PORT ( |
|
199 | PORT ( | |
220 | clk : IN STD_LOGIC; |
|
200 | clk : IN STD_LOGIC; | |
221 | rstn : IN STD_LOGIC; |
|
201 | rstn : IN STD_LOGIC; | |
222 | run : IN STD_LOGIC; |
|
202 | run : IN STD_LOGIC; | |
223 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0); |
|
203 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0); | |
224 | data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
204 | data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
225 | data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
205 | data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
226 | data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); |
|
206 | data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); | |
227 | time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); |
|
207 | time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); | |
228 | data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
208 | data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
229 | data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
209 | data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
230 | full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
210 | full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
231 | full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
211 | full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
232 | time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
212 | time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
233 | time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) |
|
213 | time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) | |
234 | ); |
|
214 | ); | |
235 | END COMPONENT; |
|
215 | END COMPONENT; | |
236 |
|
216 | |||
237 | COMPONENT lpp_waveform_fifo |
|
217 | COMPONENT lpp_waveform_fifo | |
238 | GENERIC ( |
|
218 | GENERIC ( | |
239 | tech : INTEGER); |
|
219 | tech : INTEGER); | |
240 | PORT ( |
|
220 | PORT ( | |
241 | clk : IN STD_LOGIC; |
|
221 | clk : IN STD_LOGIC; | |
242 | rstn : IN STD_LOGIC; |
|
222 | rstn : IN STD_LOGIC; | |
243 | run : IN STD_LOGIC; |
|
223 | run : IN STD_LOGIC; | |
244 | empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
224 | empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
245 | empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
225 | empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
246 | data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
226 | data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
247 | rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
227 | rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
248 | full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
228 | full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
249 | full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
229 | full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
250 | data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
230 | data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
251 | wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
231 | wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
252 | END COMPONENT; |
|
232 | END COMPONENT; | |
253 |
|
233 | |||
254 | COMPONENT lpp_waveform_fifo_headreg |
|
234 | COMPONENT lpp_waveform_fifo_headreg | |
255 | GENERIC ( |
|
235 | GENERIC ( | |
256 | tech : INTEGER); |
|
236 | tech : INTEGER); | |
257 | PORT ( |
|
237 | PORT ( | |
258 | clk : IN STD_LOGIC; |
|
238 | clk : IN STD_LOGIC; | |
259 | rstn : IN STD_LOGIC; |
|
239 | rstn : IN STD_LOGIC; | |
260 | run : IN STD_LOGIC; |
|
240 | run : IN STD_LOGIC; | |
261 | o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
241 | o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
262 | o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
242 | o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
263 | o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
243 | o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
264 | o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
244 | o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
265 | o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
245 | o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
266 | o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
246 | o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
267 | o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
247 | o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
268 | i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
248 | i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
269 | i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
249 | i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
270 | i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
250 | i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
271 | i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
251 | i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
272 | END COMPONENT; |
|
252 | END COMPONENT; | |
273 |
|
253 | |||
274 | COMPONENT lpp_waveform_fifo_latencyCorrection |
|
254 | COMPONENT lpp_waveform_fifo_latencyCorrection | |
275 | GENERIC ( |
|
255 | GENERIC ( | |
276 | tech : INTEGER); |
|
256 | tech : INTEGER); | |
277 | PORT ( |
|
257 | PORT ( | |
278 | clk : IN STD_LOGIC; |
|
258 | clk : IN STD_LOGIC; | |
279 | rstn : IN STD_LOGIC; |
|
259 | rstn : IN STD_LOGIC; | |
280 | run : IN STD_LOGIC; |
|
260 | run : IN STD_LOGIC; | |
281 | empty_almost : OUT STD_LOGIC; |
|
261 | empty_almost : OUT STD_LOGIC; | |
282 | empty : OUT STD_LOGIC; |
|
262 | empty : OUT STD_LOGIC; | |
283 | data_ren : IN STD_LOGIC; |
|
263 | data_ren : IN STD_LOGIC; | |
284 | rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
264 | rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
285 | empty_almost_fifo : IN STD_LOGIC; |
|
265 | empty_almost_fifo : IN STD_LOGIC; | |
286 | empty_fifo : IN STD_LOGIC; |
|
266 | empty_fifo : IN STD_LOGIC; | |
287 | data_ren_fifo : OUT STD_LOGIC; |
|
267 | data_ren_fifo : OUT STD_LOGIC; | |
288 | rdata_fifo : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
268 | rdata_fifo : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
289 | END COMPONENT; |
|
269 | END COMPONENT; | |
290 |
|
270 | |||
291 | COMPONENT lpp_waveform_fifo_withoutLatency |
|
271 | COMPONENT lpp_waveform_fifo_withoutLatency | |
292 | GENERIC ( |
|
272 | GENERIC ( | |
293 | tech : INTEGER); |
|
273 | tech : INTEGER); | |
294 | PORT ( |
|
274 | PORT ( | |
295 | clk : IN STD_LOGIC; |
|
275 | clk : IN STD_LOGIC; | |
296 | rstn : IN STD_LOGIC; |
|
276 | rstn : IN STD_LOGIC; | |
297 | run : IN STD_LOGIC; |
|
277 | run : IN STD_LOGIC; | |
298 | empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
278 | empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
299 | empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
279 | empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
300 | data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
280 | data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
301 | rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
281 | rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
302 | rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
282 | rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
303 | rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
283 | rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
304 | rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
284 | rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
305 | full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
285 | full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
306 | full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
286 | full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
307 | data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
287 | data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
308 | wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
288 | wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
309 | END COMPONENT; |
|
289 | END COMPONENT; | |
310 |
|
290 | |||
311 | ----------------------------------------------------------------------------- |
|
291 | ----------------------------------------------------------------------------- | |
312 | -- GEN ADDRESS |
|
292 | -- GEN ADDRESS | |
313 | ----------------------------------------------------------------------------- |
|
293 | ----------------------------------------------------------------------------- | |
314 | COMPONENT lpp_waveform_genaddress |
|
294 | COMPONENT lpp_waveform_genaddress | |
315 | GENERIC ( |
|
295 | GENERIC ( | |
316 | nb_data_by_buffer_size : INTEGER); |
|
296 | nb_data_by_buffer_size : INTEGER); | |
317 | PORT ( |
|
297 | PORT ( | |
318 | clk : IN STD_LOGIC; |
|
298 | clk : IN STD_LOGIC; | |
319 | rstn : IN STD_LOGIC; |
|
299 | rstn : IN STD_LOGIC; | |
320 | run : IN STD_LOGIC; |
|
300 | run : IN STD_LOGIC; | |
321 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
301 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
322 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
302 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
323 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
303 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
324 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
304 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
325 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
305 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
326 | empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
306 | empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
327 | empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
307 | empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
328 | data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
308 | data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
329 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
309 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
330 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
310 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
331 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
311 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
332 | data_f0_data_out_valid_burst : OUT STD_LOGIC; |
|
312 | data_f0_data_out_valid_burst : OUT STD_LOGIC; | |
333 | data_f1_data_out_valid_burst : OUT STD_LOGIC; |
|
313 | data_f1_data_out_valid_burst : OUT STD_LOGIC; | |
334 | data_f2_data_out_valid_burst : OUT STD_LOGIC; |
|
314 | data_f2_data_out_valid_burst : OUT STD_LOGIC; | |
335 | data_f3_data_out_valid_burst : OUT STD_LOGIC; |
|
315 | data_f3_data_out_valid_burst : OUT STD_LOGIC; | |
336 | data_f0_data_out_valid : OUT STD_LOGIC; |
|
316 | data_f0_data_out_valid : OUT STD_LOGIC; | |
337 | data_f1_data_out_valid : OUT STD_LOGIC; |
|
317 | data_f1_data_out_valid : OUT STD_LOGIC; | |
338 | data_f2_data_out_valid : OUT STD_LOGIC; |
|
318 | data_f2_data_out_valid : OUT STD_LOGIC; | |
339 | data_f3_data_out_valid : OUT STD_LOGIC; |
|
319 | data_f3_data_out_valid : OUT STD_LOGIC; | |
340 | data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
320 | data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
341 | data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
321 | data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
342 | data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
322 | data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
343 | data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
323 | data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
344 | END COMPONENT; |
|
324 | END COMPONENT; | |
345 |
|
325 | |||
346 | ----------------------------------------------------------------------------- |
|
326 | ----------------------------------------------------------------------------- | |
347 | -- lpp_waveform_fifo_arbiter_reg |
|
327 | -- lpp_waveform_fifo_arbiter_reg | |
348 | ----------------------------------------------------------------------------- |
|
328 | ----------------------------------------------------------------------------- | |
349 | COMPONENT lpp_waveform_fifo_arbiter_reg |
|
329 | COMPONENT lpp_waveform_fifo_arbiter_reg | |
350 | GENERIC ( |
|
330 | GENERIC ( | |
351 | data_size : INTEGER; |
|
331 | data_size : INTEGER; | |
352 | data_nb : INTEGER); |
|
332 | data_nb : INTEGER); | |
353 | PORT ( |
|
333 | PORT ( | |
354 | clk : IN STD_LOGIC; |
|
334 | clk : IN STD_LOGIC; | |
355 | rstn : IN STD_LOGIC; |
|
335 | rstn : IN STD_LOGIC; | |
356 | run : IN STD_LOGIC; |
|
336 | run : IN STD_LOGIC; | |
357 | max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0); |
|
337 | max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0); | |
358 | enable : IN STD_LOGIC; |
|
338 | enable : IN STD_LOGIC; | |
359 | sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0); |
|
339 | sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0); | |
360 | data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
340 | data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
361 | data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
341 | data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0)); | |
362 | time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|||
363 | time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); |
|
|||
364 | END COMPONENT; |
|
342 | END COMPONENT; | |
365 |
|
343 | |||
366 | COMPONENT lpp_waveform_fsmdma |
|
344 | COMPONENT lpp_waveform_fsmdma | |
367 | PORT ( |
|
345 | PORT ( | |
368 | clk : IN STD_ULOGIC; |
|
346 | clk : IN STD_ULOGIC; | |
369 | rstn : IN STD_ULOGIC; |
|
347 | rstn : IN STD_ULOGIC; | |
370 | run : IN STD_LOGIC; |
|
348 | run : IN STD_LOGIC; | |
371 | fifo_buffer_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
349 | fifo_buffer_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
372 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
350 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
373 | fifo_empty : IN STD_LOGIC; |
|
351 | fifo_empty : IN STD_LOGIC; | |
374 | fifo_empty_threshold : IN STD_LOGIC; |
|
352 | fifo_empty_threshold : IN STD_LOGIC; | |
375 | fifo_ren : OUT STD_LOGIC; |
|
353 | fifo_ren : OUT STD_LOGIC; | |
376 | dma_fifo_valid_burst : OUT STD_LOGIC; |
|
354 | dma_fifo_valid_burst : OUT STD_LOGIC; | |
377 | dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
355 | dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
378 | dma_fifo_ren : IN STD_LOGIC; |
|
356 | dma_fifo_ren : IN STD_LOGIC; | |
379 | dma_buffer_new : OUT STD_LOGIC; |
|
357 | dma_buffer_new : OUT STD_LOGIC; | |
380 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
358 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
381 | dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
359 | dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
382 | dma_buffer_full : IN STD_LOGIC; |
|
360 | dma_buffer_full : IN STD_LOGIC; | |
383 | dma_buffer_full_err : IN STD_LOGIC; |
|
361 | dma_buffer_full_err : IN STD_LOGIC; | |
384 | status_buffer_ready : IN STD_LOGIC; |
|
362 | status_buffer_ready : IN STD_LOGIC; | |
385 | addr_buffer : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
363 | addr_buffer : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
386 | length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
364 | length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0); | |
387 | ready_buffer : OUT STD_LOGIC; |
|
365 | ready_buffer : OUT STD_LOGIC; | |
388 | buffer_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
366 | buffer_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
389 | error_buffer_full : OUT STD_LOGIC); |
|
367 | error_buffer_full : OUT STD_LOGIC); | |
390 | END COMPONENT; |
|
368 | END COMPONENT; | |
391 |
|
369 | |||
392 | END lpp_waveform_pkg; |
|
370 | END lpp_waveform_pkg; |
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