# HG changeset patch # User pellion # Date 2014-10-24 07:04:53 # Node ID f9d16aadc780ab2aaf92a47d869644c04d2e2dec # Parent 0e3034ceda82ac83fb50e939c35b1b2fe9c2b101 new bitstream to test diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -418,7 +418,7 @@ BEGIN -- beh GENERIC MAP ( Mem_use => use_RAM, nb_data_by_buffer_size => 32, - nb_word_by_buffer_size => 30, +-- nb_word_by_buffer_size => 30, nb_snapshot_param_size => 32, delta_vector_size => 32, delta_vector_size_f0_2 => 7, -- log2(96) @@ -441,10 +441,7 @@ BEGIN -- beh ahbo => ahbo_m_ext(2), coarse_time => coarse_time, fine_time => fine_time, - data_shaping_BW => bias_fail_sw_sig, - observation_vector_0=> observation_vector_0, - observation_vector_1 => observation_vector_1, - observation_reg => observation_reg); + data_shaping_BW => bias_fail_sw_sig); all_sample: FOR I IN 7 DOWNTO 0 GENERATE sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; diff --git a/designs/Validation_LFR/Makefile b/designs/Validation_LFR/Makefile --- a/designs/Validation_LFR/Makefile +++ b/designs/Validation_LFR/Makefile @@ -481,11 +481,17 @@ vcom_lpp: $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/fifo_latency_correction.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_pkg.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_ip.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/DMA_SubSystem.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/DMA_SubSystem_GestionBuffer.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/DMA_SubSystem_Arbiter.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/DMA_SubSystem_MUX.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_burst.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_withoutLatency.vhd @@ -499,6 +505,7 @@ vcom_lpp: $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_genaddress.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_dma_genvalid.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fsmdma.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd diff --git a/designs/Validation_LFR/TB.vhd b/designs/Validation_LFR/TB.vhd --- a/designs/Validation_LFR/TB.vhd +++ b/designs/Validation_LFR/TB.vhd @@ -93,27 +93,55 @@ ARCHITECTURE beh OF TB IS CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44"; CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48"; CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C"; - + + CONSTANT ADDR_SPECTRAL_MATRIX_LENGTH_MATRIX : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50"; -- REG WAVEFORM - CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50"; - CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54"; - CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58"; - CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C"; + CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54"; + CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58"; + CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C"; + + CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F60"; + CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F64"; + CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F68"; + CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F6C"; + + CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F70"; + CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F74"; + CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F78"; + CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F7C"; + + CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F80"; + CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F84"; + CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F88"; + CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F8C"; - CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F60"; - CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F64"; - CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F68"; - CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F6C"; + CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F90"; + CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F94"; + CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F98"; + CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F9C"; + + CONSTANT ADDR_WAVEFORM_PICKER_COARSE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FA0"; + CONSTANT ADDR_WAVEFORM_PICKER_FINE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FA4"; + CONSTANT ADDR_WAVEFORM_PICKER_COARSE_TIME_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FA8"; + CONSTANT ADDR_WAVEFORM_PICKER_FINE_TIME_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FAC"; - CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F70"; - CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F74"; - CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F78"; - CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F7C"; + CONSTANT ADDR_WAVEFORM_PICKER_COARSE_TIME_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FB0"; + CONSTANT ADDR_WAVEFORM_PICKER_FINE_TIME_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FB4"; + CONSTANT ADDR_WAVEFORM_PICKER_COARSE_TIME_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FB8"; + CONSTANT ADDR_WAVEFORM_PICKER_FINE_TIME_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FBC"; - CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F80"; - CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F84"; - CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F88"; - CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F8C"; + CONSTANT ADDR_WAVEFORM_PICKER_COARSE_TIME_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FC0"; + CONSTANT ADDR_WAVEFORM_PICKER_FINE_TIME_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FC4"; + CONSTANT ADDR_WAVEFORM_PICKER_COARSE_TIME_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FC8"; + CONSTANT ADDR_WAVEFORM_PICKER_FINE_TIME_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FCC"; + + CONSTANT ADDR_WAVEFORM_PICKER_COARSE_TIME_F3_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FD0"; + CONSTANT ADDR_WAVEFORM_PICKER_FINE_TIME_F3_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FD4"; + CONSTANT ADDR_WAVEFORM_PICKER_COARSE_TIME_F3_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FD8"; + CONSTANT ADDR_WAVEFORM_PICKER_FINE_TIME_F3_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FDC"; + + CONSTANT ADDR_WAVEFORM_PICKER_LENGTH_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000FE0"; + -- RAM ADDRESS CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#000#; CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#; @@ -328,7 +356,7 @@ BEGIN GENERIC MAP ( Mem_use => use_CEL, -- use_RAM nb_data_by_buffer_size => 32, - nb_word_by_buffer_size => 30, +-- nb_word_by_buffer_size => 30, nb_snapshot_param_size => 32, delta_vector_size => 32, delta_vector_size_f0_2 => 32, @@ -478,18 +506,33 @@ BEGIN WAIT UNTIL clk25MHz = '1'; rstn <= '1'; WAIT UNTIL clk25MHz = '1'; + --------------------------------------------------------------------------- + -- spectral matrix configuration + --------------------------------------------------------------------------- + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_CONFIG, X"00000000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 , X"40000000"); - APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 , X"40020000"); - APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1_0 , X"40040000"); - APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2_0 , X"40060000"); - - APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_CONFIG, X"00000007"); - APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_STATUS, X"00000000"); - - APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000"); - APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000"); - APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000"); - APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 , X"40001000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1_0 , X"40002000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1_1 , X"40003000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2_0 , X"40004000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2_1 , X"40005000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_LENGTH_MATRIX, X"000000C8"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_STATUS, X"00000000"); + + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_CONFIG, X"00000007"); + + --------------------------------------------------------------------------- + -- waveform picker configuration + --------------------------------------------------------------------------- + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0_0 , X"40020000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0_1 , X"40020000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1_0 , X"40030000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1_1 , X"40030000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2_0 , X"40040000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2_1 , X"40040000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3_0 , X"40060000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3_1 , X"40060000"); APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000020"); --"00000020" APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000019"); --"00000019" @@ -497,21 +540,26 @@ BEGIN APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000019"); --"00000019" APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001"); --"00000001" - APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010" + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000010"); -- X"00000010" -- APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010"); APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001"); - APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022"); + + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_LENGTH_BUFFER , X"00000003"); APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000080"); WAIT UNTIL clk25MHz = '1'; --------------------------------------------------------------------------- -- CONFIGURATION STEP - APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000"); - APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000"); - APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000"); - APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0_0 , X"40020000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0_1 , X"40020000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1_0 , X"40030000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1_1 , X"40030000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2_0 , X"40040000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2_1 , X"40040000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3_0 , X"40060000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3_1 , X"40060000"); WAIT UNTIL clk25MHz = '1'; WAIT UNTIL clk25MHz = '1'; diff --git a/designs/Validation_LFR/wave.do b/designs/Validation_LFR/wave.do --- a/designs/Validation_LFR/wave.do +++ b/designs/Validation_LFR/wave.do @@ -1,57 +1,139 @@ onerror {resume} quietly WaveActivateNextPane {} 0 -add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata -add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata -add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata -add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata -add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val -add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val -add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val -add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val -add wave -noupdate -expand -group SNAPSHOT_F0 /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/enable -add wave -noupdate -expand -group SNAPSHOT_F0 /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/burst_enable -add wave -noupdate -expand -group SNAPSHOT_F0 /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/start_snapshot -add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/state_on -add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/wfp_on_s -add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f0_pre -add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/first_decount -add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/first_init -add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot -add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_f0 -add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/send_start_snapshot_f0 -add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/data_f0_valid -add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/data_f2_valid -add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f0 -add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f1 -add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f2 -add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/wfp_on -add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in -add wave -noupdate -expand -subitemconfig {/tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.haddr {-height 15 -radix hexadecimal} /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hwdata {-height 15 -radix hexadecimal}} /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out -add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/send -add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/valid_burst -add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/done -add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ren -add wave -noupdate -radix hexadecimal /tb/lpp_lfr_1/lpp_dma_singleorburst_1/address -add wave -noupdate -radix hexadecimal /tb/lpp_lfr_1/lpp_dma_singleorburst_1/data -add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/debug_dmaout_okay -add wave -noupdate /tb/async_1mx16_0/ce1_b -add wave -noupdate /tb/async_1mx16_0/ce2 -add wave -noupdate /tb/async_1mx16_0/we_b -add wave -noupdate /tb/async_1mx16_0/oe_b -add wave -noupdate /tb/async_1mx16_0/bhe_b -add wave -noupdate /tb/async_1mx16_0/ble_b -add wave -noupdate /tb/async_1mx16_0/a -add wave -noupdate /tb/async_1mx16_0/dq -add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/async_1mx16_0/mem_array_0(31) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(30) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(29) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(28) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(27) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(26) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(25) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(24) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(23) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(22) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(21) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(20) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(19) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(18) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(17) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(16) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(15) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(14) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(13) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(12) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(11) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(10) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(9) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(8) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(7) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(6) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(5) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(4) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(3) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(2) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(1) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(0) {-height 15 -radix hexadecimal}} /tb/async_1mx16_0/mem_array_0 -add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/async_1mx16_0/mem_array_1(31) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(30) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(29) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(28) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(27) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(26) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(25) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(24) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(23) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(22) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(21) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(20) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(19) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(18) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(17) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(16) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(15) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(14) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(13) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(12) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(11) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(10) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(9) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(8) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(7) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(6) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(5) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(4) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(3) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(2) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(1) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(0) {-radix hexadecimal}} /tb/async_1mx16_0/mem_array_1 -add wave -noupdate -radix hexadecimal /tb/async_1mx16_0/mem_array_2 -add wave -noupdate -radix hexadecimal /tb/async_1mx16_0/mem_array_3 -add wave -noupdate -format Analog-Step -height 70 -max 256.0 -radix unsigned -subitemconfig {/tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(7) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(6) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(5) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(4) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(3) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(2) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(1) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(0) {-radix unsigned}} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect -add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(0) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(1) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(2) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(3) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(4) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(5) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(6) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(7) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(8) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(9) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(10) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(11) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(12) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(13) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(14) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(15) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(16) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(17) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(18) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(19) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(20) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(21) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(22) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(23) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(24) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(25) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(26) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(27) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(28) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(29) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(30) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(31) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(32) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(33) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(34) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(35) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(36) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(37) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(38) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(39) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(40) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(41) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(42) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(43) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(44) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(45) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(46) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(47) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(48) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(49) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(50) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(51) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(52) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(53) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(54) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(55) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(56) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(57) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(58) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(59) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(60) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(61) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(62) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(63) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(64) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(65) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(66) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(67) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(68) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(69) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(70) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(71) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(72) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(73) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(74) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(75) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(76) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(77) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(78) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(79) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(80) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(81) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(82) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(83) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(84) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(85) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(86) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(87) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(88) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(89) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(90) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(91) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(92) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(93) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(94) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(95) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(96) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(97) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(98) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(99) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(100) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(101) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(102) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(103) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(104) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(105) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(106) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(107) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(108) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(109) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(110) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(111) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(112) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(113) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(114) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(115) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(116) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(117) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(118) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(119) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(120) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(121) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(122) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(123) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(124) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(125) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(126) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(127) {-radix hexadecimal}} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd +add wave -noupdate -expand -group FILTER_OUTPUT -radix hexadecimal /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata +add wave -noupdate -expand -group FILTER_OUTPUT -radix hexadecimal /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata +add wave -noupdate -expand -group FILTER_OUTPUT -radix hexadecimal /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata +add wave -noupdate -expand -group FILTER_OUTPUT -radix hexadecimal /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata +add wave -noupdate -expand -group FILTER_OUTPUT -radix hexadecimal /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val +add wave -noupdate -expand -group FILTER_OUTPUT -radix hexadecimal /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val +add wave -noupdate -expand -group FILTER_OUTPUT -radix hexadecimal /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val +add wave -noupdate -expand -group FILTER_OUTPUT -radix hexadecimal /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val +add wave -noupdate /tb/lpp_lfr_1/rstn +add wave -noupdate /tb/lpp_lfr_1/run +add wave -noupdate /tb/lpp_lfr_1/run_dma +add wave -noupdate /tb/lpp_lfr_1/run_ms +add wave -noupdate -expand -group MS /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp +add wave -noupdate -expand -group MS -group MS_MEM_OUT_0 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(0)/mem_out_spectralmatrix_i/reuse +add wave -noupdate -expand -group MS -group MS_MEM_OUT_0 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(0)/mem_out_spectralmatrix_i/run +add wave -noupdate -expand -group MS -group MS_MEM_OUT_0 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(0)/mem_out_spectralmatrix_i/ren +add wave -noupdate -expand -group MS -group MS_MEM_OUT_0 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(0)/mem_out_spectralmatrix_i/rdata +add wave -noupdate -expand -group MS -group MS_MEM_OUT_0 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(0)/mem_out_spectralmatrix_i/wen +add wave -noupdate -expand -group MS -group MS_MEM_OUT_0 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(0)/mem_out_spectralmatrix_i/wdata +add wave -noupdate -expand -group MS -group MS_MEM_OUT_0 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(0)/mem_out_spectralmatrix_i/full +add wave -noupdate -expand -group MS -group MS_MEM_OUT_0 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(0)/mem_out_spectralmatrix_i/full_threshold +add wave -noupdate -expand -group MS -group MS_MEM_OUT_0 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(0)/mem_out_spectralmatrix_i/full_almost +add wave -noupdate -expand -group MS -group MS_MEM_OUT_0 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(0)/mem_out_spectralmatrix_i/empty +add wave -noupdate -expand -group MS -group MS_MEM_OUT_0 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(0)/mem_out_spectralmatrix_i/empty_threshold +add wave -noupdate -expand -group MS -group MEM_OUT_1 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(1)/mem_out_spectralmatrix_i/reuse +add wave -noupdate -expand -group MS -group MEM_OUT_1 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(1)/mem_out_spectralmatrix_i/run +add wave -noupdate -expand -group MS -group MEM_OUT_1 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(1)/mem_out_spectralmatrix_i/ren +add wave -noupdate -expand -group MS -group MEM_OUT_1 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(1)/mem_out_spectralmatrix_i/rdata +add wave -noupdate -expand -group MS -group MEM_OUT_1 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(1)/mem_out_spectralmatrix_i/wen +add wave -noupdate -expand -group MS -group MEM_OUT_1 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(1)/mem_out_spectralmatrix_i/wdata +add wave -noupdate -expand -group MS -group MEM_OUT_1 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(1)/mem_out_spectralmatrix_i/empty +add wave -noupdate -expand -group MS -group MEM_OUT_1 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(1)/mem_out_spectralmatrix_i/full +add wave -noupdate -expand -group MS -group MEM_OUT_1 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(1)/mem_out_spectralmatrix_i/full_almost +add wave -noupdate -expand -group MS -group MEM_OUT_1 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(1)/mem_out_spectralmatrix_i/empty_threshold +add wave -noupdate -expand -group MS -group MEM_OUT_1 /tb/lpp_lfr_1/lpp_lfr_ms_1/all_mem_out_spectralmatrix(1)/mem_out_spectralmatrix_i/full_threshold +add wave -noupdate -expand -group MS -group FSM_Dma_FIFO /tb/lpp_lfr_1/lpp_lfr_ms_1/fsm_dma_fifo_ren +add wave -noupdate -expand -group MS -group FSM_Dma_FIFO /tb/lpp_lfr_1/lpp_lfr_ms_1/fsm_dma_fifo_empty +add wave -noupdate -expand -group MS -group FSM_Dma_FIFO /tb/lpp_lfr_1/lpp_lfr_ms_1/fsm_dma_fifo_empty_threshold +add wave -noupdate -expand -group MS -group FSM_Dma_FIFO /tb/lpp_lfr_1/lpp_lfr_ms_1/fsm_dma_fifo_data +add wave -noupdate -expand -group MS -group FSM_Dma_FIFO /tb/lpp_lfr_1/lpp_lfr_ms_1/fsm_dma_fifo_status +add wave -noupdate /tb/lpp_lfr_1/dma_subsystem_1/fifo_ren +add wave -noupdate /tb/lpp_lfr_1/dma_subsystem_1/dma_ren +add wave -noupdate /tb/lpp_lfr_1/dma_subsystem_1/fifo_burst_valid +add wave -noupdate /tb/lpp_lfr_1/dma_subsystem_1/fifo_data +add wave -noupdate /tb/lpp_lfr_1/dma_subsystem_1/fifo_ren +add wave -noupdate -radix hexadecimal -subitemconfig {/tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_new_err {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_bw {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_sp0 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_sp1 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_r0 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_r1 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_r2 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_snapshot {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0_2 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f1 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f2 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_data_by_buffer {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_snapshot_param {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f0 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f1 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f2 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f3 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f0 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f1 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f2 {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.run {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f {-radix hexadecimal -expand} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f(7) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f(6) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f(5) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f(4) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f(3) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f(2) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f(1) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f(0) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.addr_buffer_f {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.length_buffer {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.error_buffer_full {-radix hexadecimal} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.start_date {-radix hexadecimal}} /tb/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp +add wave -noupdate -group FIFO_0 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/reuse +add wave -noupdate -group FIFO_0 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/run +add wave -noupdate -group FIFO_0 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/ren +add wave -noupdate -group FIFO_0 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/rdata +add wave -noupdate -group FIFO_0 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/wen +add wave -noupdate -group FIFO_0 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/wdata +add wave -noupdate -group FIFO_0 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/empty +add wave -noupdate -group FIFO_0 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/full +add wave -noupdate -group FIFO_0 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/full_almost +add wave -noupdate -group FIFO_0 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/empty_threshold +add wave -noupdate -group FIFO_0 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/full_threshold +add wave -noupdate -group FIFO_1 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/reuse +add wave -noupdate -group FIFO_1 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/run +add wave -noupdate -group FIFO_1 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/ren +add wave -noupdate -group FIFO_1 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/rdata +add wave -noupdate -group FIFO_1 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/wen +add wave -noupdate -group FIFO_1 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/wdata +add wave -noupdate -group FIFO_1 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/empty +add wave -noupdate -group FIFO_1 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/full +add wave -noupdate -group FIFO_1 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/full_almost +add wave -noupdate -group FIFO_1 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/empty_threshold +add wave -noupdate -group FIFO_1 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/full_threshold +add wave -noupdate -group FIFO_2 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/reuse +add wave -noupdate -group FIFO_2 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/run +add wave -noupdate -group FIFO_2 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/ren +add wave -noupdate -group FIFO_2 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/rdata +add wave -noupdate -group FIFO_2 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/wen +add wave -noupdate -group FIFO_2 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/wdata +add wave -noupdate -group FIFO_2 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/empty +add wave -noupdate -group FIFO_2 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/full +add wave -noupdate -group FIFO_2 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/full_almost +add wave -noupdate -group FIFO_2 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/empty_threshold +add wave -noupdate -group FIFO_2 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/full_threshold +add wave -noupdate -group FIFO_3 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/reuse +add wave -noupdate -group FIFO_3 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/run +add wave -noupdate -group FIFO_3 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/ren +add wave -noupdate -group FIFO_3 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/rdata +add wave -noupdate -group FIFO_3 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/wen +add wave -noupdate -group FIFO_3 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/wdata +add wave -noupdate -group FIFO_3 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/empty +add wave -noupdate -group FIFO_3 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/full +add wave -noupdate -group FIFO_3 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/full_almost +add wave -noupdate -group FIFO_3 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/empty_threshold +add wave -noupdate -group FIFO_3 /tb/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/full_threshold +add wave -noupdate -expand -group WFP_FSMDMA_0 -group WFP_FSMDMA_dma -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/dma_fifo_valid_burst +add wave -noupdate -expand -group WFP_FSMDMA_0 -group WFP_FSMDMA_dma -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/dma_fifo_data +add wave -noupdate -expand -group WFP_FSMDMA_0 -group WFP_FSMDMA_dma -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/dma_fifo_ren +add wave -noupdate -expand -group WFP_FSMDMA_0 -group WFP_FSMDMA_dma -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/dma_buffer_new +add wave -noupdate -expand -group WFP_FSMDMA_0 -group WFP_FSMDMA_dma -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/dma_buffer_addr +add wave -noupdate -expand -group WFP_FSMDMA_0 -group WFP_FSMDMA_dma -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/dma_buffer_length +add wave -noupdate -expand -group WFP_FSMDMA_0 -group WFP_FSMDMA_dma -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/dma_buffer_full +add wave -noupdate -expand -group WFP_FSMDMA_0 -group WFP_FSMDMA_dma -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/dma_buffer_full_err +add wave -noupdate -expand -group WFP_FSMDMA_0 -expand -group WFP_FSMDMA_fifo -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/fifo_buffer_time +add wave -noupdate -expand -group WFP_FSMDMA_0 -expand -group WFP_FSMDMA_fifo /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/fifo_data +add wave -noupdate -expand -group WFP_FSMDMA_0 -expand -group WFP_FSMDMA_fifo /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/fifo_empty +add wave -noupdate -expand -group WFP_FSMDMA_0 -expand -group WFP_FSMDMA_fifo /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/fifo_empty_threshold +add wave -noupdate -expand -group WFP_FSMDMA_0 -expand -group WFP_FSMDMA_fifo /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/fifo_ren +add wave -noupdate -expand -group WFP_FSMDMA_0 -expand -group WFP_FSMDMA_reg /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/status_buffer_ready +add wave -noupdate -expand -group WFP_FSMDMA_0 -expand -group WFP_FSMDMA_reg /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/addr_buffer +add wave -noupdate -expand -group WFP_FSMDMA_0 -expand -group WFP_FSMDMA_reg /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/length_buffer +add wave -noupdate -expand -group WFP_FSMDMA_0 -expand -group WFP_FSMDMA_reg /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/ready_buffer +add wave -noupdate -expand -group WFP_FSMDMA_0 -expand -group WFP_FSMDMA_reg -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/buffer_time +add wave -noupdate -expand -group WFP_FSMDMA_0 -expand -group WFP_FSMDMA_reg /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/error_buffer_full +add wave -noupdate -expand -group WFP_FSMDMA_0 /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/state +add wave -noupdate -expand -group WFP_FSMDMA_0 /tb/lpp_lfr_1/lpp_waveform_1/all_channel(0)/lpp_waveform_fsmdma_i/burst_valid_s +add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/wfp_status_buffer_ready +add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/reg0_status_ready_matrix +add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/reg0_ready_matrix +add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/reg0_addr_matrix +add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/reg0_matrix_time +add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/reg1_status_ready_matrix +add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/reg1_ready_matrix +add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/reg1_addr_matrix +add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/reg1_matrix_time +add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/ready_matrix +add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/status_ready_matrix +add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/addr_matrix +add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/matrix_time +add wave -noupdate /tb/lpp_lfr_1/lpp_lfr_apbreg_1/all_wfp_pointer(0)/lpp_apbreg_wfp_pointer_fi/current_reg +add wave -noupdate -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/fifo_buffer_time +add wave -noupdate -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/arbiter_time_out +add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/arbiter_time_out_new +add wave -noupdate -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/time_sel +add wave -noupdate -expand -subitemconfig {/tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/time_in(3) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/time_in(2) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/time_in(1) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/time_in(0) {-radix hexadecimal}} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/time_in TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {44999193701 ps} 0} {{Cursor 3} {209437155 ps} 0} {{Cursor 4} {69917366400 ps} 0} {{Cursor 5} {27526990683 ps} 0} +WaveRestoreCursors {{Cursor 1} {111345088346 ps} 0} {{Cursor 2} {50435974615 ps} 0} {{Cursor 3} {4065545 ps} 0} {{Cursor 4} {83087041514 ps} 0} {{Cursor 5} {16894875474 ps} 0} configure wave -namecolwidth 618 -configure wave -valuecolwidth 472 +configure wave -valuecolwidth 205 configure wave -justifyvalue left configure wave -signalnamewidth 0 configure wave -snapdistance 10 @@ -64,6 +146,6 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ps update -WaveRestoreZoom {0 ps} {91678875750 ps} +WaveRestoreZoom {4057109 ps} {4131134 ps} bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0 diff --git a/lib/lpp/lpp_dma/DMA_SubSystem_GestionBuffer.vhd b/lib/lpp/lpp_dma/DMA_SubSystem_GestionBuffer.vhd --- a/lib/lpp/lpp_dma/DMA_SubSystem_GestionBuffer.vhd +++ b/lib/lpp/lpp_dma/DMA_SubSystem_GestionBuffer.vhd @@ -60,7 +60,7 @@ BEGIN buffer_full_err <= '0'; buffer_full <= '0'; IF burst_send = '1' THEN - IF burst_send_counter_add1 < buffer_length THEN + IF unsigned(burst_send_counter_add1) < unsigned(buffer_length) THEN burst_send_counter <= burst_send_counter_add1; ELSE buffer_full <= '1'; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -280,7 +280,9 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL dma_grant_error : STD_LOGIC; - + + ----------------------------------------------------------------------------- + SIGNAL run_dma : STD_LOGIC; BEGIN sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); @@ -487,7 +489,9 @@ BEGIN Mem_use => Mem_use) PORT MAP ( clk => clk, - rstn => ms_softandhard_rstn, --rstn, + --rstn => ms_softandhard_rstn, --rstn, + rstn => rstn, + run => run_ms, coarse_time => coarse_time, @@ -535,14 +539,15 @@ BEGIN matrix_time_f2 => matrix_time_f2); ----------------------------------------------------------------------------- - + run_dma <= run_ms OR run; + DMA_SubSystem_1 : DMA_SubSystem GENERIC MAP ( hindex => hindex) PORT MAP ( clk => clk, rstn => rstn, - run => run_ms, + run => run_dma, ahbi => ahbi, ahbo => ahbo, diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd @@ -307,9 +307,10 @@ BEGIN -- beh start_date <= reg_wp.start_date; - --length_matrix_f0 <= reg_sp.length_matrix; - --length_matrix_f1 <= reg_sp.length_matrix; - --length_matrix_f2 <= reg_sp.length_matrix; + length_matrix_f0 <= reg_sp.length_matrix; + length_matrix_f1 <= reg_sp.length_matrix; + length_matrix_f2 <= reg_sp.length_matrix; + wfp_length_buffer <= reg_wp.length_buffer; lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) @@ -318,7 +319,7 @@ BEGIN -- beh IF HRESETn = '0' THEN -- asynchronous reset (active low) reg_sp.config_active_interruption_onNewMatrix <= '0'; reg_sp.config_active_interruption_onError <= '0'; - reg_sp.config_ms_run <= '1'; + reg_sp.config_ms_run <= '0'; reg_sp.status_ready_matrix_f0_0 <= '0'; reg_sp.status_ready_matrix_f1_0 <= '0'; reg_sp.status_ready_matrix_f2_0 <= '0'; @@ -382,6 +383,8 @@ BEGIN -- beh reg_wp.nb_snapshot_param <= (OTHERS => '0'); reg_wp.start_date <= (OTHERS => '0'); + reg_wp.status_ready_buffer_f <= (OTHERS => '0'); + reg_wp.length_buffer <= (OTHERS => '0'); ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge -- status_full_ack <= (OTHERS => '0'); @@ -490,13 +493,13 @@ BEGIN -- beh prdata(7) <= reg_wp.run; --22 --ON GOING \/ - WHEN "010111" => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0); + WHEN "010111" => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0);--0 WHEN "011000" => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1); - WHEN "011001" => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2); + WHEN "011001" => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2);--1 WHEN "011010" => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3); - WHEN "011011" => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4); + WHEN "011011" => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4);--2 WHEN "011100" => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5); - WHEN "011101" => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6); + WHEN "011101" => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6);--3 WHEN "011110" => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7); --ON GOING /\ WHEN "011111" => prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f; @@ -525,20 +528,23 @@ BEGIN -- beh WHEN "101001" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0+47 DOWNTO 48*0+16); WHEN "101010" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1+15 DOWNTO 48*1); WHEN "101011" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1+47 DOWNTO 48*1+16); + WHEN "101100" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2+15 DOWNTO 48*2); - WHEN "101110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2+47 DOWNTO 48*2+16); - WHEN "101111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3+15 DOWNTO 48*3); - WHEN "110000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3+47 DOWNTO 48*3+16); + WHEN "101101" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2+47 DOWNTO 48*2+16); + WHEN "101110" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3+15 DOWNTO 48*3); + WHEN "101111" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3+47 DOWNTO 48*3+16); - WHEN "110001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4+15 DOWNTO 48*4); - WHEN "111010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4+47 DOWNTO 48*4+16); - WHEN "110011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5+15 DOWNTO 48*5); - WHEN "110100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5+47 DOWNTO 48*5+16); - WHEN "110101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6+15 DOWNTO 48*6); - WHEN "110110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6+47 DOWNTO 48*6+16); - WHEN "110111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7+15 DOWNTO 48*7); - WHEN "111000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7+47 DOWNTO 48*7+16); - WHEN "111001" => prdata(25 DOWNTO 0) <= reg_wp.length_buffer; + WHEN "110000" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4+15 DOWNTO 48*4); + WHEN "110001" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4+47 DOWNTO 48*4+16); + WHEN "110010" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5+15 DOWNTO 48*5); + WHEN "110011" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5+47 DOWNTO 48*5+16); + + WHEN "110100" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6+15 DOWNTO 48*6); + WHEN "110101" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6+47 DOWNTO 48*6+16); + WHEN "110110" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7+15 DOWNTO 48*7); + WHEN "110111" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7+47 DOWNTO 48*7+16); + + WHEN "111000" => prdata(25 DOWNTO 0) <= reg_wp.length_buffer; -- WHEN "100100" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; ---------------------------------------------------- @@ -617,7 +623,7 @@ BEGIN -- beh WHEN "100110" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); WHEN "100111" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); - WHEN "111001" => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0); + WHEN "111000" => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0); @@ -658,7 +664,7 @@ BEGIN -- beh ----------------------------------------------------------------------------- -- IRQ ----------------------------------------------------------------------------- - irq_wfp_reg_s <= wfp_status_buffer_ready & wfp_error_buffer_full & status_new_err; + irq_wfp_reg_s <= wfp_ready_buffer & wfp_error_buffer_full & status_new_err; PROCESS (HCLK, HRESETn) BEGIN -- PROCESS @@ -767,4 +773,4 @@ BEGIN -- beh END GENERATE all_wfp_pointer; ----------------------------------------------------------------------------- -END beh; \ No newline at end of file +END beh; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd @@ -45,7 +45,7 @@ ENTITY lpp_lfr_ms IS dma_fifo_burst_valid: OUT STD_LOGIC; --TODO dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO dma_fifo_ren : IN STD_LOGIC; --TODO - dma_buffer_new : OUT STD_LOGIC; --TODO + dma_buffer_new : OUT STD_LOGIC; --TODOx dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO dma_buffer_full : IN STD_LOGIC; --TODO @@ -965,7 +965,7 @@ BEGIN FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE - '0'; + '1'; ----------------------------------------------------------------------------- -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --IN @@ -1141,4 +1141,4 @@ BEGIN ----------------------------------------------------------------------------- -END Behavioral; \ No newline at end of file +END Behavioral; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd @@ -107,7 +107,7 @@ BEGIN fifo_ren <= dma_fifo_ren WHEN state = ONGOING ELSE '1'; dma_fifo_data <= fifo_data; - dma_fifo_valid_burst <= burst_valid_s WHEN state = ONGOING ELSE '1'; + dma_fifo_valid_burst <= burst_valid_s WHEN state = ONGOING ELSE '0'; PROCESS (clk, rstn) BEGIN -- PROCESS @@ -128,6 +128,7 @@ BEGIN ready_matrix_f1 <= '0'; ready_matrix_f2 <= '0'; IF run = '1' THEN + dma_buffer_new <= '0'; CASE state IS WHEN IDLE => IF fifo_empty = '0' THEN diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd @@ -188,7 +188,7 @@ PACKAGE lpp_lfr_pkg IS GENERIC ( Mem_use : INTEGER; nb_data_by_buffer_size : INTEGER; - nb_word_by_buffer_size : INTEGER; +-- nb_word_by_buffer_size : INTEGER; nb_snapshot_param_size : INTEGER; delta_vector_size : INTEGER; delta_vector_size_f0_2 : INTEGER; @@ -212,11 +212,7 @@ PACKAGE lpp_lfr_pkg IS ahbo : OUT AHB_Mst_Out_Type; coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - data_shaping_BW : OUT STD_LOGIC; - -- - observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + data_shaping_BW : OUT STD_LOGIC ); END COMPONENT; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd @@ -175,7 +175,8 @@ BEGIN data_2 WHEN sel(2) = '1' ELSE data_3; - all_time_bit: FOR I IN 3 DOWNTO 0 GENERATE + all_time_bit: FOR I IN 47 DOWNTO 0 GENERATE + time_sel(I) <= time_in(0,I) WHEN sel(0) = '1' ELSE time_in(1,I) WHEN sel(1) = '1' ELSE time_in(2,I) WHEN sel(2) = '1' ELSE diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd @@ -30,19 +30,18 @@ USE lpp.general_purpose.ALL; ENTITY lpp_waveform_fifo_arbiter_reg IS GENERIC( data_size : INTEGER; - data_nb : INTEGER - ); + data_nb : INTEGER); PORT( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; --------------------------------------------------------------------------- - run : IN STD_LOGIC; + run : IN STD_LOGIC; max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0); enable : IN STD_LOGIC; sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0); - + data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0) ); @@ -59,19 +58,19 @@ ARCHITECTURE ar_lpp_waveform_fifo_arbite BEGIN - all_reg: FOR I IN data_nb-1 DOWNTO 0 GENERATE + all_reg : FOR I IN data_nb-1 DOWNTO 0 GENERATE PROCESS (clk, rstn) BEGIN -- PROCESS IF rstn = '0' THEN -- asynchronous reset (active low) reg(I) <= 0; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge IF run = '0' THEN reg(I) <= 0; ELSE IF sel(I) = '1' THEN reg(I) <= reg_sel_s; END IF; - END IF; + END IF; END IF; END PROCESS; END GENERATE all_reg; @@ -81,12 +80,12 @@ BEGIN reg(2) WHEN sel(2) = '1' ELSE reg(3); - reg_sel_s <= reg_sel WHEN enable = '0' ELSE + reg_sel_s <= reg_sel WHEN enable = '0' ELSE reg_sel + 1 WHEN reg_sel < UNSIGNED(max_count) ELSE 0; - data <= STD_LOGIC_VECTOR(to_unsigned(reg_sel ,data_size)); - data_s <= STD_LOGIC_VECTOR(to_unsigned(reg_sel_s,data_size)); + data <= STD_LOGIC_VECTOR(to_unsigned(reg_sel , data_size)); + data_s <= STD_LOGIC_VECTOR(to_unsigned(reg_sel_s, data_size)); END ARCHITECTURE; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd @@ -144,26 +144,6 @@ PACKAGE lpp_waveform_pkg IS data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); data_f3_in_valid : IN STD_LOGIC; data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f0_data_out_valid : OUT STD_LOGIC; - data_f0_data_out_valid_burst : OUT STD_LOGIC; - data_f0_data_out_ren : IN STD_LOGIC; - data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f1_data_out_valid : OUT STD_LOGIC; - data_f1_data_out_valid_burst : OUT STD_LOGIC; - data_f1_data_out_ren : IN STD_LOGIC; - data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f2_data_out_valid : OUT STD_LOGIC; - data_f2_data_out_valid_burst : OUT STD_LOGIC; - data_f2_data_out_ren : IN STD_LOGIC; - data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f3_data_out_valid : OUT STD_LOGIC; - data_f3_data_out_valid_burst : OUT STD_LOGIC; - data_f3_data_out_ren : IN STD_LOGIC; dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); @@ -358,9 +338,7 @@ PACKAGE lpp_waveform_pkg IS enable : IN STD_LOGIC; sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0); data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); - time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); + data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0)); END COMPONENT; COMPONENT lpp_waveform_fsmdma