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add comments for clk_50 frequency in the code (ALTRAN request)
pellion -
r610:f9824a3b6ae2 simu_with_Leon3
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 -----------------------------------------------------------------------------
52 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
53 -- clk_50 frequency is 100 Mhz !
51 clk_50 : IN STD_LOGIC;
54 clk_50 : IN STD_LOGIC;
55 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
56 -----------------------------------------------------------------------------
52 clk_49 : IN STD_LOGIC;
57 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
58 reset : IN STD_LOGIC;
54 --BPs
59 --BPs
55 BP0 : IN STD_LOGIC;
60 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
61 BP1 : IN STD_LOGIC;
57 --LEDs
62 --LEDs
58 LED0 : OUT STD_LOGIC;
63 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
64 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
65 LED2 : OUT STD_LOGIC;
61 --UARTs
66 --UARTs
62 TXD1 : IN STD_LOGIC;
67 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
68 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
69 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
70 nRTS1 : IN STD_LOGIC;
66
71
67 TXD2 : IN STD_LOGIC;
72 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
73 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
74 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
75 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
76 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
77 nDCD2 : OUT STD_LOGIC;
73
78
74 --EXT CONNECTOR
79 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
80 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
81 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
82 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
83 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
84 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
85 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
86 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
87 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
88 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
89 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
90 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
91 IO11 : INOUT STD_LOGIC;
87
92
88 --SPACE WIRE
93 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
94 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
95 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
96 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
97 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
98 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
99 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
100 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
101 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
102 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
103 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
104 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
105 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
106 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
107
103 -- SRAM
108 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
109 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
110 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
111 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
112 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
113 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
114 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
115 );
111
116
112 END MINI_LFR_top;
117 END MINI_LFR_top;
113
118
114
119
115 ARCHITECTURE beh OF MINI_LFR_top IS
120 ARCHITECTURE beh OF MINI_LFR_top IS
116
121
117 --==========================================================================
122 --==========================================================================
118 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
123 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
119 -- when enabled, chip enable polarity should be reversed and bank size also
124 -- when enabled, chip enable polarity should be reversed and bank size also
120 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
125 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
121 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
126 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
122 --==========================================================================
127 --==========================================================================
123 CONSTANT USE_IAP_MEMCTRL : integer := 1;
128 CONSTANT USE_IAP_MEMCTRL : integer := 1;
124 --==========================================================================
129 --==========================================================================
125
130
126 SIGNAL clk_50_s : STD_LOGIC := '0';
131 SIGNAL clk_50_s : STD_LOGIC := '0';
127 SIGNAL clk_25 : STD_LOGIC := '0';
132 SIGNAL clk_25 : STD_LOGIC := '0';
128 SIGNAL clk_24 : STD_LOGIC := '0';
133 SIGNAL clk_24 : STD_LOGIC := '0';
129 -----------------------------------------------------------------------------
134 -----------------------------------------------------------------------------
130 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
135 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
136 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
132 --
137 --
133 SIGNAL errorn : STD_LOGIC;
138 SIGNAL errorn : STD_LOGIC;
134 -- UART AHB ---------------------------------------------------------------
139 -- UART AHB ---------------------------------------------------------------
135 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
140 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
136 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
141 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
137
142
138 -- UART APB ---------------------------------------------------------------
143 -- UART APB ---------------------------------------------------------------
139 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
144 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
140 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
145 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
141 --
146 --
142 SIGNAL I00_s : STD_LOGIC;
147 SIGNAL I00_s : STD_LOGIC;
143
148
144 -- CONSTANTS
149 -- CONSTANTS
145 CONSTANT CFG_PADTECH : INTEGER := inferred;
150 CONSTANT CFG_PADTECH : INTEGER := inferred;
146 --
151 --
147 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
152 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
148 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
153 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
149 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
154 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
150
155
151 SIGNAL apbi_ext : apb_slv_in_type;
156 SIGNAL apbi_ext : apb_slv_in_type;
152 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
157 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
153 SIGNAL ahbi_s_ext : ahb_slv_in_type;
158 SIGNAL ahbi_s_ext : ahb_slv_in_type;
154 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
159 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
155 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
160 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
156 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
161 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
157
162
158 -- Spacewire signals
163 -- Spacewire signals
159 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
164 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
160 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
165 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
161 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
166 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
162 SIGNAL spw_rxtxclk : STD_ULOGIC;
167 SIGNAL spw_rxtxclk : STD_ULOGIC;
163 SIGNAL spw_rxclkn : STD_ULOGIC;
168 SIGNAL spw_rxclkn : STD_ULOGIC;
164 SIGNAL spw_clk : STD_LOGIC;
169 SIGNAL spw_clk : STD_LOGIC;
165 SIGNAL swni : grspw_in_type;
170 SIGNAL swni : grspw_in_type;
166 SIGNAL swno : grspw_out_type;
171 SIGNAL swno : grspw_out_type;
167 -- SIGNAL clkmn : STD_ULOGIC;
172 -- SIGNAL clkmn : STD_ULOGIC;
168 -- SIGNAL txclk : STD_ULOGIC;
173 -- SIGNAL txclk : STD_ULOGIC;
169
174
170 --GPIO
175 --GPIO
171 SIGNAL gpioi : gpio_in_type;
176 SIGNAL gpioi : gpio_in_type;
172 SIGNAL gpioo : gpio_out_type;
177 SIGNAL gpioo : gpio_out_type;
173
178
174 -- AD Converter ADS7886
179 -- AD Converter ADS7886
175 SIGNAL sample : Samples14v(7 DOWNTO 0);
180 SIGNAL sample : Samples14v(7 DOWNTO 0);
176 SIGNAL sample_s : Samples(7 DOWNTO 0);
181 SIGNAL sample_s : Samples(7 DOWNTO 0);
177 SIGNAL sample_val : STD_LOGIC;
182 SIGNAL sample_val : STD_LOGIC;
178 SIGNAL ADC_nCS_sig : STD_LOGIC;
183 SIGNAL ADC_nCS_sig : STD_LOGIC;
179 SIGNAL ADC_CLK_sig : STD_LOGIC;
184 SIGNAL ADC_CLK_sig : STD_LOGIC;
180 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
185 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
181
186
182 SIGNAL bias_fail_sw_sig : STD_LOGIC;
187 SIGNAL bias_fail_sw_sig : STD_LOGIC;
183
188
184 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
190 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
186 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
191 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
187 -----------------------------------------------------------------------------
192 -----------------------------------------------------------------------------
188
193
189 SIGNAL LFR_soft_rstn : STD_LOGIC;
194 SIGNAL LFR_soft_rstn : STD_LOGIC;
190 SIGNAL LFR_rstn : STD_LOGIC;
195 SIGNAL LFR_rstn : STD_LOGIC;
191
196
192
197
193 SIGNAL rstn_25 : STD_LOGIC;
198 SIGNAL rstn_25 : STD_LOGIC;
194 SIGNAL rstn_25_d1 : STD_LOGIC;
199 SIGNAL rstn_25_d1 : STD_LOGIC;
195 SIGNAL rstn_25_d2 : STD_LOGIC;
200 SIGNAL rstn_25_d2 : STD_LOGIC;
196 SIGNAL rstn_25_d3 : STD_LOGIC;
201 SIGNAL rstn_25_d3 : STD_LOGIC;
197
202
198 SIGNAL rstn_24 : STD_LOGIC;
203 SIGNAL rstn_24 : STD_LOGIC;
199 SIGNAL rstn_24_d1 : STD_LOGIC;
204 SIGNAL rstn_24_d1 : STD_LOGIC;
200 SIGNAL rstn_24_d2 : STD_LOGIC;
205 SIGNAL rstn_24_d2 : STD_LOGIC;
201 SIGNAL rstn_24_d3 : STD_LOGIC;
206 SIGNAL rstn_24_d3 : STD_LOGIC;
202
207
203 SIGNAL rstn_50 : STD_LOGIC;
208 SIGNAL rstn_50 : STD_LOGIC;
204 SIGNAL rstn_50_d1 : STD_LOGIC;
209 SIGNAL rstn_50_d1 : STD_LOGIC;
205 SIGNAL rstn_50_d2 : STD_LOGIC;
210 SIGNAL rstn_50_d2 : STD_LOGIC;
206 SIGNAL rstn_50_d3 : STD_LOGIC;
211 SIGNAL rstn_50_d3 : STD_LOGIC;
207
212
208 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
213 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
209 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
214 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
210
215
211 --
216 --
212 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
217 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
213
218
214 --
219 --
215 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
220 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
216 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
221 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
217
222
218 SIGNAL nSRAM_READY : STD_LOGIC;
223 SIGNAL nSRAM_READY : STD_LOGIC;
219
224
220 BEGIN -- beh
225 BEGIN -- beh
221
226
222 -----------------------------------------------------------------------------
223 -- CLK
224 -----------------------------------------------------------------------------
227 -----------------------------------------------------------------------------
225
228 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
226 --PROCESS(clk_50)
229 -- clk_50 frequency is 100 Mhz !
227 --BEGIN
228 -- IF clk_50'EVENT AND clk_50 = '1' THEN
229 -- clk_50_s <= NOT clk_50_s;
230 -- END IF;
231 --END PROCESS;
232
233 --PROCESS(clk_50_s)
234 --BEGIN
235 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
236 -- clk_25 <= NOT clk_25;
237 -- END IF;
238 --END PROCESS;
239
240 --PROCESS(clk_49)
241 --BEGIN
242 -- IF clk_49'EVENT AND clk_49 = '1' THEN
243 -- clk_24 <= NOT clk_24;
244 -- END IF;
245 --END PROCESS;
246
247 --PROCESS(clk_25)
248 --BEGIN
249 -- IF clk_25'EVENT AND clk_25 = '1' THEN
250 -- rstn_25 <= reset;
251 -- END IF;
252 --END PROCESS;
253
254 PROCESS (clk_50, reset)
230 PROCESS (clk_50, reset)
255 BEGIN -- PROCESS
231 BEGIN -- PROCESS
256 IF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
232 IF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
257 clk_50_s <= NOT clk_50_s;
233 clk_50_s <= NOT clk_50_s;
258 END IF;
234 END IF;
259 END PROCESS;
235 END PROCESS;
236 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
237 -----------------------------------------------------------------------------
260
238
261 PROCESS (clk_50_s, reset)
239 PROCESS (clk_50_s, reset)
262 BEGIN -- PROCESS
240 BEGIN -- PROCESS
263 IF reset = '0' THEN -- asynchronous reset (active low)
241 IF reset = '0' THEN -- asynchronous reset (active low)
264 clk_25 <= '0';
242 clk_25 <= '0';
265 rstn_25 <= '0';
243 rstn_25 <= '0';
266 rstn_25_d1 <= '0';
244 rstn_25_d1 <= '0';
267 rstn_25_d2 <= '0';
245 rstn_25_d2 <= '0';
268 rstn_25_d3 <= '0';
246 rstn_25_d3 <= '0';
269 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
247 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
270 clk_25 <= NOT clk_25;
248 clk_25 <= NOT clk_25;
271 rstn_25_d1 <= '1';
249 rstn_25_d1 <= '1';
272 rstn_25_d2 <= rstn_25_d1;
250 rstn_25_d2 <= rstn_25_d1;
273 rstn_25_d3 <= rstn_25_d2;
251 rstn_25_d3 <= rstn_25_d2;
274 rstn_25 <= rstn_25_d3;
252 rstn_25 <= rstn_25_d3;
275 END IF;
253 END IF;
276 END PROCESS;
254 END PROCESS;
277
255
278 PROCESS (clk_49, reset)
256 PROCESS (clk_49, reset)
279 BEGIN -- PROCESS
257 BEGIN -- PROCESS
280 IF reset = '0' THEN -- asynchronous reset (active low)
258 IF reset = '0' THEN -- asynchronous reset (active low)
281 clk_24 <= '0';
259 clk_24 <= '0';
282 rstn_24_d1 <= '0';
260 rstn_24_d1 <= '0';
283 rstn_24_d2 <= '0';
261 rstn_24_d2 <= '0';
284 rstn_24_d3 <= '0';
262 rstn_24_d3 <= '0';
285 rstn_24 <= '0';
263 rstn_24 <= '0';
286 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
264 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
287 clk_24 <= NOT clk_24;
265 clk_24 <= NOT clk_24;
288 rstn_24_d1 <= '1';
266 rstn_24_d1 <= '1';
289 rstn_24_d2 <= rstn_24_d1;
267 rstn_24_d2 <= rstn_24_d1;
290 rstn_24_d3 <= rstn_24_d2;
268 rstn_24_d3 <= rstn_24_d2;
291 rstn_24 <= rstn_24_d3;
269 rstn_24 <= rstn_24_d3;
292 END IF;
270 END IF;
293 END PROCESS;
271 END PROCESS;
294
272
295 -----------------------------------------------------------------------------
273 -----------------------------------------------------------------------------
296
274
297 PROCESS (clk_25, rstn_25)
275 PROCESS (clk_25, rstn_25)
298 BEGIN -- PROCESS
276 BEGIN -- PROCESS
299 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
277 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
300 LED0 <= '0';
278 LED0 <= '0';
301 LED1 <= '0';
279 LED1 <= '0';
302 LED2 <= '0';
280 LED2 <= '0';
303 --IO1 <= '0';
304 --IO2 <= '1';
305 --IO3 <= '0';
306 --IO4 <= '0';
307 --IO5 <= '0';
308 --IO6 <= '0';
309 --IO7 <= '0';
310 --IO8 <= '0';
311 --IO9 <= '0';
312 --IO10 <= '0';
313 --IO11 <= '0';
314 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
281 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
315 LED0 <= '0';
282 LED0 <= '0';
316 LED1 <= '1';
283 LED1 <= '1';
317 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
284 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
318 --IO1 <= '1';
319 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
320 --IO3 <= ADC_SDO(0);
321 --IO4 <= ADC_SDO(1);
322 --IO5 <= ADC_SDO(2);
323 --IO6 <= ADC_SDO(3);
324 --IO7 <= ADC_SDO(4);
325 --IO8 <= ADC_SDO(5);
326 --IO9 <= ADC_SDO(6);
327 --IO10 <= ADC_SDO(7);
328 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
329 END IF;
285 END IF;
330 END PROCESS;
286 END PROCESS;
331
287
332 PROCESS (clk_24, rstn_24)
288 PROCESS (clk_24, rstn_24)
333 BEGIN -- PROCESS
289 BEGIN -- PROCESS
334 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
290 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
335 I00_s <= '0';
291 I00_s <= '0';
336 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
292 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
337 I00_s <= NOT I00_s;
293 I00_s <= NOT I00_s;
338 END IF;
294 END IF;
339 END PROCESS;
295 END PROCESS;
340 -- IO0 <= I00_s;
341
296
342 --UARTs
297 --UARTs
343 nCTS1 <= '1';
298 nCTS1 <= '1';
344 nCTS2 <= '1';
299 nCTS2 <= '1';
345 nDCD2 <= '1';
300 nDCD2 <= '1';
346
301
347 --
302 --
348
303
349 leon3_soc_1 : leon3_soc
304 leon3_soc_1 : leon3_soc
350 GENERIC MAP (
305 GENERIC MAP (
351 fabtech => apa3e,
306 fabtech => apa3e,
352 memtech => apa3e,
307 memtech => apa3e,
353 padtech => inferred,
308 padtech => inferred,
354 clktech => inferred,
309 clktech => inferred,
355 disas => 0,
310 disas => 0,
356 dbguart => 0,
311 dbguart => 0,
357 pclow => 2,
312 pclow => 2,
358 clk_freq => 25000,
313 clk_freq => 25000,
359 IS_RADHARD => 0,
314 IS_RADHARD => 0,
360 NB_CPU => 1,
315 NB_CPU => 1,
361 ENABLE_FPU => 1,
316 ENABLE_FPU => 1,
362 FPU_NETLIST => 0,
317 FPU_NETLIST => 0,
363 ENABLE_DSU => 1,
318 ENABLE_DSU => 1,
364 ENABLE_AHB_UART => 1,
319 ENABLE_AHB_UART => 1,
365 ENABLE_APB_UART => 1,
320 ENABLE_APB_UART => 1,
366 ENABLE_IRQMP => 1,
321 ENABLE_IRQMP => 1,
367 ENABLE_GPT => 1,
322 ENABLE_GPT => 1,
368 NB_AHB_MASTER => NB_AHB_MASTER,
323 NB_AHB_MASTER => NB_AHB_MASTER,
369 NB_AHB_SLAVE => NB_AHB_SLAVE,
324 NB_AHB_SLAVE => NB_AHB_SLAVE,
370 NB_APB_SLAVE => NB_APB_SLAVE,
325 NB_APB_SLAVE => NB_APB_SLAVE,
371 ADDRESS_SIZE => 20,
326 ADDRESS_SIZE => 20,
372 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
327 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
373 BYPASS_EDAC_MEMCTRLR => '0',
328 BYPASS_EDAC_MEMCTRLR => '0',
374 SRBANKSZ => 9)
329 SRBANKSZ => 9)
375 PORT MAP (
330 PORT MAP (
376 clk => clk_25,
331 clk => clk_25,
377 reset => rstn_25,
332 reset => rstn_25,
378 errorn => errorn,
333 errorn => errorn,
379 ahbrxd => TXD1,
334 ahbrxd => TXD1,
380 ahbtxd => RXD1,
335 ahbtxd => RXD1,
381 urxd1 => TXD2,
336 urxd1 => TXD2,
382 utxd1 => RXD2,
337 utxd1 => RXD2,
383 address => SRAM_A,
338 address => SRAM_A,
384 data => SRAM_DQ,
339 data => SRAM_DQ,
385 nSRAM_BE0 => SRAM_nBE(0),
340 nSRAM_BE0 => SRAM_nBE(0),
386 nSRAM_BE1 => SRAM_nBE(1),
341 nSRAM_BE1 => SRAM_nBE(1),
387 nSRAM_BE2 => SRAM_nBE(2),
342 nSRAM_BE2 => SRAM_nBE(2),
388 nSRAM_BE3 => SRAM_nBE(3),
343 nSRAM_BE3 => SRAM_nBE(3),
389 nSRAM_WE => SRAM_nWE,
344 nSRAM_WE => SRAM_nWE,
390 nSRAM_CE => SRAM_CE_s,
345 nSRAM_CE => SRAM_CE_s,
391 nSRAM_OE => SRAM_nOE,
346 nSRAM_OE => SRAM_nOE,
392 nSRAM_READY => nSRAM_READY,
347 nSRAM_READY => nSRAM_READY,
393 SRAM_MBE => OPEN,
348 SRAM_MBE => OPEN,
394 apbi_ext => apbi_ext,
349 apbi_ext => apbi_ext,
395 apbo_ext => apbo_ext,
350 apbo_ext => apbo_ext,
396 ahbi_s_ext => ahbi_s_ext,
351 ahbi_s_ext => ahbi_s_ext,
397 ahbo_s_ext => ahbo_s_ext,
352 ahbo_s_ext => ahbo_s_ext,
398 ahbi_m_ext => ahbi_m_ext,
353 ahbi_m_ext => ahbi_m_ext,
399 ahbo_m_ext => ahbo_m_ext);
354 ahbo_m_ext => ahbo_m_ext);
400
355
401 PROCESS (clk_25, rstn_25)
356 PROCESS (clk_25, rstn_25)
402 BEGIN -- PROCESS
357 BEGIN -- PROCESS
403 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
358 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
404 nSRAM_READY <= '1';
359 nSRAM_READY <= '1';
405 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
360 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
406 nSRAM_READY <= '1';
361 nSRAM_READY <= '1';
407 IF IO0 = '1' THEN
362 IF IO0 = '1' THEN
408 nSRAM_READY <= '0';
363 nSRAM_READY <= '0';
409 END IF;
364 END IF;
410 END IF;
365 END IF;
411 END PROCESS;
366 END PROCESS;
412
367
413
368
414
369
415 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
370 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
416 SRAM_CE <= not SRAM_CE_s(0);
371 SRAM_CE <= not SRAM_CE_s(0);
417 END GENERATE;
372 END GENERATE;
418
373
419 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
374 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
420 SRAM_CE <= SRAM_CE_s(0);
375 SRAM_CE <= SRAM_CE_s(0);
421 END GENERATE;
376 END GENERATE;
422 -------------------------------------------------------------------------------
377 -------------------------------------------------------------------------------
423 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
378 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
424 -------------------------------------------------------------------------------
379 -------------------------------------------------------------------------------
425 apb_lfr_management_1 : apb_lfr_management
380 apb_lfr_management_1 : apb_lfr_management
426 GENERIC MAP (
381 GENERIC MAP (
427 tech => apa3e,
382 tech => apa3e,
428 pindex => 6,
383 pindex => 6,
429 paddr => 6,
384 paddr => 6,
430 pmask => 16#fff#,
385 pmask => 16#fff#,
431 -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
386 -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
432 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
387 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
433 PORT MAP (
388 PORT MAP (
434 clk25MHz => clk_25,
389 clk25MHz => clk_25,
435 resetn_25MHz => rstn_25, -- TODO
390 resetn_25MHz => rstn_25, -- TODO
436 -- clk24_576MHz => clk_24, -- 49.152MHz/2
391 -- clk24_576MHz => clk_24, -- 49.152MHz/2
437 -- resetn_24_576MHz => rstn_24, -- TODO
392 -- resetn_24_576MHz => rstn_24, -- TODO
438 grspw_tick => swno.tickout,
393 grspw_tick => swno.tickout,
439 apbi => apbi_ext,
394 apbi => apbi_ext,
440 apbo => apbo_ext(6),
395 apbo => apbo_ext(6),
441 HK_sample => sample_hk,
396 HK_sample => sample_hk,
442 HK_val => sample_val,
397 HK_val => sample_val,
443 HK_sel => HK_SEL,
398 HK_sel => HK_SEL,
444 DAC_SDO => OPEN,
399 DAC_SDO => OPEN,
445 DAC_SCK => OPEN,
400 DAC_SCK => OPEN,
446 DAC_SYNC => OPEN,
401 DAC_SYNC => OPEN,
447 DAC_CAL_EN => OPEN,
402 DAC_CAL_EN => OPEN,
448 coarse_time => coarse_time,
403 coarse_time => coarse_time,
449 fine_time => fine_time,
404 fine_time => fine_time,
450 LFR_soft_rstn => LFR_soft_rstn
405 LFR_soft_rstn => LFR_soft_rstn
451 );
406 );
452
407
453 -----------------------------------------------------------------------
408 -----------------------------------------------------------------------
454 --- SpaceWire --------------------------------------------------------
409 --- SpaceWire --------------------------------------------------------
455 -----------------------------------------------------------------------
410 -----------------------------------------------------------------------
456
411
457 SPW_EN <= '1';
412 SPW_EN <= '1';
458
413
459 spw_clk <= clk_50_s;
414 spw_clk <= clk_50_s;
460 spw_rxtxclk <= spw_clk;
415 spw_rxtxclk <= spw_clk;
461 spw_rxclkn <= NOT spw_rxtxclk;
416 spw_rxclkn <= NOT spw_rxtxclk;
462
417
463 -- PADS for SPW1
418 -- PADS for SPW1
464 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
419 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
465 PORT MAP (SPW_NOM_DIN, dtmp(0));
420 PORT MAP (SPW_NOM_DIN, dtmp(0));
466 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
421 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
467 PORT MAP (SPW_NOM_SIN, stmp(0));
422 PORT MAP (SPW_NOM_SIN, stmp(0));
468 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
423 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
469 PORT MAP (SPW_NOM_DOUT, swno.d(0));
424 PORT MAP (SPW_NOM_DOUT, swno.d(0));
470 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
425 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
471 PORT MAP (SPW_NOM_SOUT, swno.s(0));
426 PORT MAP (SPW_NOM_SOUT, swno.s(0));
472 -- PADS FOR SPW2
427 -- PADS FOR SPW2
473 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
428 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
474 PORT MAP (SPW_RED_SIN, dtmp(1));
429 PORT MAP (SPW_RED_SIN, dtmp(1));
475 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
430 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
476 PORT MAP (SPW_RED_DIN, stmp(1));
431 PORT MAP (SPW_RED_DIN, stmp(1));
477 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
432 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
478 PORT MAP (SPW_RED_DOUT, swno.d(1));
433 PORT MAP (SPW_RED_DOUT, swno.d(1));
479 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
434 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
480 PORT MAP (SPW_RED_SOUT, swno.s(1));
435 PORT MAP (SPW_RED_SOUT, swno.s(1));
481
436
482 -- GRSPW PHY
437 -- GRSPW PHY
483 --spw1_input: if CFG_SPW_GRSPW = 1 generate
438 --spw1_input: if CFG_SPW_GRSPW = 1 generate
484 spw_inputloop : FOR j IN 0 TO 1 GENERATE
439 spw_inputloop : FOR j IN 0 TO 1 GENERATE
485 spw_phy0 : grspw_phy
440 spw_phy0 : grspw_phy
486 GENERIC MAP(
441 GENERIC MAP(
487 tech => apa3e,
442 tech => apa3e,
488 rxclkbuftype => 1,
443 rxclkbuftype => 1,
489 scantest => 0)
444 scantest => 0)
490 PORT MAP(
445 PORT MAP(
491 rxrst => swno.rxrst,
446 rxrst => swno.rxrst,
492 di => dtmp(j),
447 di => dtmp(j),
493 si => stmp(j),
448 si => stmp(j),
494 rxclko => spw_rxclk(j),
449 rxclko => spw_rxclk(j),
495 do => swni.d(j),
450 do => swni.d(j),
496 ndo => swni.nd(j*5+4 DOWNTO j*5),
451 ndo => swni.nd(j*5+4 DOWNTO j*5),
497 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
452 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
498 END GENERATE spw_inputloop;
453 END GENERATE spw_inputloop;
499
454
500 swni.rmapnodeaddr <= (OTHERS => '0');
455 swni.rmapnodeaddr <= (OTHERS => '0');
501
456
502 -- SPW core
457 -- SPW core
503 sw0 : grspwm GENERIC MAP(
458 sw0 : grspwm GENERIC MAP(
504 tech => apa3e,
459 tech => apa3e,
505 hindex => 1,
460 hindex => 1,
506 pindex => 5,
461 pindex => 5,
507 paddr => 5,
462 paddr => 5,
508 pirq => 11,
463 pirq => 11,
509 sysfreq => 25000, -- CPU_FREQ
464 sysfreq => 25000, -- CPU_FREQ
510 rmap => 1,
465 rmap => 1,
511 rmapcrc => 1,
466 rmapcrc => 1,
512 fifosize1 => 16,
467 fifosize1 => 16,
513 fifosize2 => 16,
468 fifosize2 => 16,
514 rxclkbuftype => 1,
469 rxclkbuftype => 1,
515 rxunaligned => 0,
470 rxunaligned => 0,
516 rmapbufs => 4,
471 rmapbufs => 4,
517 ft => 0,
472 ft => 0,
518 netlist => 0,
473 netlist => 0,
519 ports => 2,
474 ports => 2,
520 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
475 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
521 memtech => apa3e,
476 memtech => apa3e,
522 destkey => 2,
477 destkey => 2,
523 spwcore => 1
478 spwcore => 1
524 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
479 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
525 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
480 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
526 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
481 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
527 )
482 )
528 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
483 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
529 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
484 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
530 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
485 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
531 swni, swno);
486 swni, swno);
532
487
533 swni.tickin <= '0';
488 swni.tickin <= '0';
534 swni.rmapen <= '1';
489 swni.rmapen <= '1';
535 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
490 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
536 swni.tickinraw <= '0';
491 swni.tickinraw <= '0';
537 swni.timein <= (OTHERS => '0');
492 swni.timein <= (OTHERS => '0');
538 swni.dcrstval <= (OTHERS => '0');
493 swni.dcrstval <= (OTHERS => '0');
539 swni.timerrstval <= (OTHERS => '0');
494 swni.timerrstval <= (OTHERS => '0');
540
495
541 -------------------------------------------------------------------------------
496 -------------------------------------------------------------------------------
542 -- LFR ------------------------------------------------------------------------
497 -- LFR ------------------------------------------------------------------------
543 -------------------------------------------------------------------------------
498 -------------------------------------------------------------------------------
544
499
545
500
546 LFR_rstn <= LFR_soft_rstn AND rstn_25;
501 LFR_rstn <= LFR_soft_rstn AND rstn_25;
547 --LFR_rstn <= rstn_25;
502 --LFR_rstn <= rstn_25;
548
503
549 lpp_lfr_1 : lpp_lfr
504 lpp_lfr_1 : lpp_lfr
550 GENERIC MAP (
505 GENERIC MAP (
551 Mem_use => use_RAM,
506 Mem_use => use_RAM,
552 nb_data_by_buffer_size => 32,
507 nb_data_by_buffer_size => 32,
553 nb_snapshot_param_size => 32,
508 nb_snapshot_param_size => 32,
554 delta_vector_size => 32,
509 delta_vector_size => 32,
555 delta_vector_size_f0_2 => 7, -- log2(96)
510 delta_vector_size_f0_2 => 7, -- log2(96)
556 pindex => 15,
511 pindex => 15,
557 paddr => 15,
512 paddr => 15,
558 pmask => 16#fff#,
513 pmask => 16#fff#,
559 pirq_ms => 6,
514 pirq_ms => 6,
560 pirq_wfp => 14,
515 pirq_wfp => 14,
561 hindex => 2,
516 hindex => 2,
562 top_lfr_version => X"000146") -- aa.bb.cc version
517 top_lfr_version => X"000146") -- aa.bb.cc version
563 PORT MAP (
518 PORT MAP (
564 clk => clk_25,
519 clk => clk_25,
565 rstn => LFR_rstn,
520 rstn => LFR_rstn,
566 sample_B => sample_s(2 DOWNTO 0),
521 sample_B => sample_s(2 DOWNTO 0),
567 sample_E => sample_s(7 DOWNTO 3),
522 sample_E => sample_s(7 DOWNTO 3),
568 sample_val => sample_val,
523 sample_val => sample_val,
569 apbi => apbi_ext,
524 apbi => apbi_ext,
570 apbo => apbo_ext(15),
525 apbo => apbo_ext(15),
571 ahbi => ahbi_m_ext,
526 ahbi => ahbi_m_ext,
572 ahbo => ahbo_m_ext(2),
527 ahbo => ahbo_m_ext(2),
573 coarse_time => coarse_time,
528 coarse_time => coarse_time,
574 fine_time => fine_time,
529 fine_time => fine_time,
575 data_shaping_BW => bias_fail_sw_sig,
530 data_shaping_BW => bias_fail_sw_sig,
576 debug_vector => lfr_debug_vector,
531 debug_vector => lfr_debug_vector,
577 debug_vector_ms => lfr_debug_vector_ms
532 debug_vector_ms => lfr_debug_vector_ms
578 );
533 );
579
534
580 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
535 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
581 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
536 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
582 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
537 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
583 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
538 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
584 -- IO0 <= rstn_25;
539 -- IO0 <= rstn_25;
585 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
540 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
586 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
541 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
587 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
542 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
588 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
543 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
589 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
544 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
590 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
545 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
591 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
546 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
592
547
593 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
548 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
594 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
549 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
595 END GENERATE all_sample;
550 END GENERATE all_sample;
596
551
597 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
552 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
598 GENERIC MAP(
553 GENERIC MAP(
599 ChannelCount => 8,
554 ChannelCount => 8,
600 SampleNbBits => 14,
555 SampleNbBits => 14,
601 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
556 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
602 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
557 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
603 PORT MAP (
558 PORT MAP (
604 -- CONV
559 -- CONV
605 cnv_clk => clk_24,
560 cnv_clk => clk_24,
606 cnv_rstn => rstn_24,
561 cnv_rstn => rstn_24,
607 cnv => ADC_nCS_sig,
562 cnv => ADC_nCS_sig,
608 -- DATA
563 -- DATA
609 clk => clk_25,
564 clk => clk_25,
610 rstn => rstn_25,
565 rstn => rstn_25,
611 sck => ADC_CLK_sig,
566 sck => ADC_CLK_sig,
612 sdo => ADC_SDO_sig,
567 sdo => ADC_SDO_sig,
613 -- SAMPLE
568 -- SAMPLE
614 sample => sample,
569 sample => sample,
615 sample_val => sample_val);
570 sample_val => sample_val);
616
571
617 --IO10 <= ADC_SDO_sig(5);
572 --IO10 <= ADC_SDO_sig(5);
618 --IO9 <= ADC_SDO_sig(4);
573 --IO9 <= ADC_SDO_sig(4);
619 --IO8 <= ADC_SDO_sig(3);
574 --IO8 <= ADC_SDO_sig(3);
620
575
621 ADC_nCS <= ADC_nCS_sig;
576 ADC_nCS <= ADC_nCS_sig;
622 ADC_CLK <= ADC_CLK_sig;
577 ADC_CLK <= ADC_CLK_sig;
623 ADC_SDO_sig <= ADC_SDO;
578 ADC_SDO_sig <= ADC_SDO;
624
579
625 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
580 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
626 "0010001000100010" WHEN HK_SEL = "01" ELSE
581 "0010001000100010" WHEN HK_SEL = "01" ELSE
627 "0100010001000100" WHEN HK_SEL = "10" ELSE
582 "0100010001000100" WHEN HK_SEL = "10" ELSE
628 (OTHERS => '0');
583 (OTHERS => '0');
629
584
630
585
631 ----------------------------------------------------------------------
586 ----------------------------------------------------------------------
632 --- GPIO -----------------------------------------------------------
587 --- GPIO -----------------------------------------------------------
633 ----------------------------------------------------------------------
588 ----------------------------------------------------------------------
634
589
635 grgpio0 : grgpio
590 grgpio0 : grgpio
636 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
591 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
637 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
592 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
638
593
639 gpioi.sig_en <= (OTHERS => '0');
594 gpioi.sig_en <= (OTHERS => '0');
640 gpioi.sig_in <= (OTHERS => '0');
595 gpioi.sig_in <= (OTHERS => '0');
641 gpioi.din <= (OTHERS => '0');
596 gpioi.din <= (OTHERS => '0');
642 --pio_pad_0 : iopad
643 -- GENERIC MAP (tech => CFG_PADTECH)
644 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
645 --pio_pad_1 : iopad
646 -- GENERIC MAP (tech => CFG_PADTECH)
647 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
648 --pio_pad_2 : iopad
649 -- GENERIC MAP (tech => CFG_PADTECH)
650 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
651 --pio_pad_3 : iopad
652 -- GENERIC MAP (tech => CFG_PADTECH)
653 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
654 --pio_pad_4 : iopad
655 -- GENERIC MAP (tech => CFG_PADTECH)
656 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
657 --pio_pad_5 : iopad
658 -- GENERIC MAP (tech => CFG_PADTECH)
659 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
660 --pio_pad_6 : iopad
661 -- GENERIC MAP (tech => CFG_PADTECH)
662 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
663 --pio_pad_7 : iopad
664 -- GENERIC MAP (tech => CFG_PADTECH)
665 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
666
667 PROCESS (clk_25, rstn_25)
597 PROCESS (clk_25, rstn_25)
668 BEGIN -- PROCESS
598 BEGIN -- PROCESS
669 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
599 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
670 -- --IO0 <= '0';
671 -- IO1 <= '0';
672 -- IO2 <= '0';
673 -- IO3 <= '0';
674 -- IO4 <= '0';
675 -- IO5 <= '0';
676 -- IO6 <= '0';
677 -- IO7 <= '0';
678 IO8 <= '0';
600 IO8 <= '0';
679 IO9 <= '0';
601 IO9 <= '0';
680 IO10 <= '0';
602 IO10 <= '0';
681 IO11 <= '0';
603 IO11 <= '0';
682 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
604 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
683 CASE gpioo.dout(2 DOWNTO 0) IS
605 CASE gpioo.dout(2 DOWNTO 0) IS
684 WHEN "011" =>
606 WHEN "011" =>
685 -- --IO0 <= observation_reg(0 );
686 -- IO1 <= observation_reg(1 );
687 -- IO2 <= observation_reg(2 );
688 -- IO3 <= observation_reg(3 );
689 -- IO4 <= observation_reg(4 );
690 -- IO5 <= observation_reg(5 );
691 -- IO6 <= observation_reg(6 );
692 -- IO7 <= observation_reg(7 );
693 IO8 <= observation_reg(8);
607 IO8 <= observation_reg(8);
694 IO9 <= observation_reg(9);
608 IO9 <= observation_reg(9);
695 IO10 <= observation_reg(10);
609 IO10 <= observation_reg(10);
696 IO11 <= observation_reg(11);
610 IO11 <= observation_reg(11);
697 WHEN "001" =>
611 WHEN "001" =>
698 -- --IO0 <= observation_reg(0 + 12);
699 -- IO1 <= observation_reg(1 + 12);
700 -- IO2 <= observation_reg(2 + 12);
701 -- IO3 <= observation_reg(3 + 12);
702 -- IO4 <= observation_reg(4 + 12);
703 -- IO5 <= observation_reg(5 + 12);
704 -- IO6 <= observation_reg(6 + 12);
705 -- IO7 <= observation_reg(7 + 12);
706 IO8 <= observation_reg(8 + 12);
612 IO8 <= observation_reg(8 + 12);
707 IO9 <= observation_reg(9 + 12);
613 IO9 <= observation_reg(9 + 12);
708 IO10 <= observation_reg(10 + 12);
614 IO10 <= observation_reg(10 + 12);
709 IO11 <= observation_reg(11 + 12);
615 IO11 <= observation_reg(11 + 12);
710 WHEN "010" =>
616 WHEN "010" =>
711 -- --IO0 <= observation_reg(0 + 12 + 12);
712 -- IO1 <= observation_reg(1 + 12 + 12);
713 -- IO2 <= observation_reg(2 + 12 + 12);
714 -- IO3 <= observation_reg(3 + 12 + 12);
715 -- IO4 <= observation_reg(4 + 12 + 12);
716 -- IO5 <= observation_reg(5 + 12 + 12);
717 -- IO6 <= observation_reg(6 + 12 + 12);
718 -- IO7 <= observation_reg(7 + 12 + 12);
719 IO8 <= '0';
617 IO8 <= '0';
720 IO9 <= '0';
618 IO9 <= '0';
721 IO10 <= '0';
619 IO10 <= '0';
722 IO11 <= '0';
620 IO11 <= '0';
723 WHEN "000" =>
621 WHEN "000" =>
724 -- --IO0 <= observation_vector_0(0 );
725 -- IO1 <= observation_vector_0(1 );
726 -- IO2 <= observation_vector_0(2 );
727 -- IO3 <= observation_vector_0(3 );
728 -- IO4 <= observation_vector_0(4 );
729 -- IO5 <= observation_vector_0(5 );
730 -- IO6 <= observation_vector_0(6 );
731 -- IO7 <= observation_vector_0(7 );
732 IO8 <= observation_vector_0(8);
622 IO8 <= observation_vector_0(8);
733 IO9 <= observation_vector_0(9);
623 IO9 <= observation_vector_0(9);
734 IO10 <= observation_vector_0(10);
624 IO10 <= observation_vector_0(10);
735 IO11 <= observation_vector_0(11);
625 IO11 <= observation_vector_0(11);
736 WHEN "100" =>
626 WHEN "100" =>
737 -- --IO0 <= observation_vector_1(0 );
738 -- IO1 <= observation_vector_1(1 );
739 -- IO2 <= observation_vector_1(2 );
740 -- IO3 <= observation_vector_1(3 );
741 -- IO4 <= observation_vector_1(4 );
742 -- IO5 <= observation_vector_1(5 );
743 -- IO6 <= observation_vector_1(6 );
744 -- IO7 <= observation_vector_1(7 );
745 IO8 <= observation_vector_1(8);
627 IO8 <= observation_vector_1(8);
746 IO9 <= observation_vector_1(9);
628 IO9 <= observation_vector_1(9);
747 IO10 <= observation_vector_1(10);
629 IO10 <= observation_vector_1(10);
748 IO11 <= observation_vector_1(11);
630 IO11 <= observation_vector_1(11);
749 WHEN OTHERS => NULL;
631 WHEN OTHERS => NULL;
750 END CASE;
632 END CASE;
751
633
752 END IF;
634 END IF;
753 END PROCESS;
635 END PROCESS;
754 -----------------------------------------------------------------------------
636 -----------------------------------------------------------------------------
755 --
637 --
756 -----------------------------------------------------------------------------
638 -----------------------------------------------------------------------------
757 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
639 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
758 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
640 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
759 apbo_ext(I) <= apb_none;
641 apbo_ext(I) <= apb_none;
760 END GENERATE apbo_ext_not_used;
642 END GENERATE apbo_ext_not_used;
761 END GENERATE all_apbo_ext;
643 END GENERATE all_apbo_ext;
762
644
763
645
764 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
646 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
765 ahbo_s_ext(I) <= ahbs_none;
647 ahbo_s_ext(I) <= ahbs_none;
766 END GENERATE all_ahbo_ext;
648 END GENERATE all_ahbo_ext;
767
649
768 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
650 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
769 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
651 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
770 ahbo_m_ext(I) <= ahbm_none;
652 ahbo_m_ext(I) <= ahbm_none;
771 END GENERATE ahbo_m_ext_not_used;
653 END GENERATE ahbo_m_ext_not_used;
772 END GENERATE all_ahbo_m_ext;
654 END GENERATE all_ahbo_m_ext;
773
655
774 END beh;
656 END beh;
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