diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -48,7 +48,12 @@ USE lpp.lpp_leon3_soc_pkg.ALL; ENTITY MINI_LFR_top IS PORT ( + ----------------------------------------------------------------------------- + -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + -- clk_50 frequency is 100 Mhz ! clk_50 : IN STD_LOGIC; + -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + ----------------------------------------------------------------------------- clk_49 : IN STD_LOGIC; reset : IN STD_LOGIC; --BPs @@ -218,45 +223,18 @@ ARCHITECTURE beh OF MINI_LFR_top IS SIGNAL nSRAM_READY : STD_LOGIC; BEGIN -- beh - - ----------------------------------------------------------------------------- - -- CLK + ----------------------------------------------------------------------------- - - --PROCESS(clk_50) - --BEGIN - -- IF clk_50'EVENT AND clk_50 = '1' THEN - -- clk_50_s <= NOT clk_50_s; - -- END IF; - --END PROCESS; - - --PROCESS(clk_50_s) - --BEGIN - -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN - -- clk_25 <= NOT clk_25; - -- END IF; - --END PROCESS; - - --PROCESS(clk_49) - --BEGIN - -- IF clk_49'EVENT AND clk_49 = '1' THEN - -- clk_24 <= NOT clk_24; - -- END IF; - --END PROCESS; - - --PROCESS(clk_25) - --BEGIN - -- IF clk_25'EVENT AND clk_25 = '1' THEN - -- rstn_25 <= reset; - -- END IF; - --END PROCESS; - + -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + -- clk_50 frequency is 100 Mhz ! PROCESS (clk_50, reset) BEGIN -- PROCESS IF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge clk_50_s <= NOT clk_50_s; END IF; END PROCESS; + -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + ----------------------------------------------------------------------------- PROCESS (clk_50_s, reset) BEGIN -- PROCESS @@ -300,32 +278,10 @@ BEGIN -- beh LED0 <= '0'; LED1 <= '0'; LED2 <= '0'; - --IO1 <= '0'; - --IO2 <= '1'; - --IO3 <= '0'; - --IO4 <= '0'; - --IO5 <= '0'; - --IO6 <= '0'; - --IO7 <= '0'; - --IO8 <= '0'; - --IO9 <= '0'; - --IO10 <= '0'; - --IO11 <= '0'; ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge LED0 <= '0'; LED1 <= '1'; LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; - --IO1 <= '1'; - --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; - --IO3 <= ADC_SDO(0); - --IO4 <= ADC_SDO(1); - --IO5 <= ADC_SDO(2); - --IO6 <= ADC_SDO(3); - --IO7 <= ADC_SDO(4); - --IO8 <= ADC_SDO(5); - --IO9 <= ADC_SDO(6); - --IO10 <= ADC_SDO(7); - --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; END IF; END PROCESS; @@ -337,7 +293,6 @@ BEGIN -- beh I00_s <= NOT I00_s; END IF; END PROCESS; --- IO0 <= I00_s; --UARTs nCTS1 <= '1'; @@ -639,42 +594,9 @@ BEGIN -- beh gpioi.sig_en <= (OTHERS => '0'); gpioi.sig_in <= (OTHERS => '0'); gpioi.din <= (OTHERS => '0'); - --pio_pad_0 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); - --pio_pad_1 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); - --pio_pad_2 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); - --pio_pad_3 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); - --pio_pad_4 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); - --pio_pad_5 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); - --pio_pad_6 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); - --pio_pad_7 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); - PROCESS (clk_25, rstn_25) BEGIN -- PROCESS IF rstn_25 = '0' THEN -- asynchronous reset (active low) - -- --IO0 <= '0'; - -- IO1 <= '0'; - -- IO2 <= '0'; - -- IO3 <= '0'; - -- IO4 <= '0'; - -- IO5 <= '0'; - -- IO6 <= '0'; - -- IO7 <= '0'; IO8 <= '0'; IO9 <= '0'; IO10 <= '0'; @@ -682,66 +604,26 @@ BEGIN -- beh ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge CASE gpioo.dout(2 DOWNTO 0) IS WHEN "011" => - -- --IO0 <= observation_reg(0 ); - -- IO1 <= observation_reg(1 ); - -- IO2 <= observation_reg(2 ); - -- IO3 <= observation_reg(3 ); - -- IO4 <= observation_reg(4 ); - -- IO5 <= observation_reg(5 ); - -- IO6 <= observation_reg(6 ); - -- IO7 <= observation_reg(7 ); IO8 <= observation_reg(8); IO9 <= observation_reg(9); IO10 <= observation_reg(10); IO11 <= observation_reg(11); WHEN "001" => - -- --IO0 <= observation_reg(0 + 12); - -- IO1 <= observation_reg(1 + 12); - -- IO2 <= observation_reg(2 + 12); - -- IO3 <= observation_reg(3 + 12); - -- IO4 <= observation_reg(4 + 12); - -- IO5 <= observation_reg(5 + 12); - -- IO6 <= observation_reg(6 + 12); - -- IO7 <= observation_reg(7 + 12); IO8 <= observation_reg(8 + 12); IO9 <= observation_reg(9 + 12); IO10 <= observation_reg(10 + 12); IO11 <= observation_reg(11 + 12); WHEN "010" => - -- --IO0 <= observation_reg(0 + 12 + 12); - -- IO1 <= observation_reg(1 + 12 + 12); - -- IO2 <= observation_reg(2 + 12 + 12); - -- IO3 <= observation_reg(3 + 12 + 12); - -- IO4 <= observation_reg(4 + 12 + 12); - -- IO5 <= observation_reg(5 + 12 + 12); - -- IO6 <= observation_reg(6 + 12 + 12); - -- IO7 <= observation_reg(7 + 12 + 12); IO8 <= '0'; IO9 <= '0'; IO10 <= '0'; IO11 <= '0'; WHEN "000" => - -- --IO0 <= observation_vector_0(0 ); - -- IO1 <= observation_vector_0(1 ); - -- IO2 <= observation_vector_0(2 ); - -- IO3 <= observation_vector_0(3 ); - -- IO4 <= observation_vector_0(4 ); - -- IO5 <= observation_vector_0(5 ); - -- IO6 <= observation_vector_0(6 ); - -- IO7 <= observation_vector_0(7 ); IO8 <= observation_vector_0(8); IO9 <= observation_vector_0(9); IO10 <= observation_vector_0(10); IO11 <= observation_vector_0(11); WHEN "100" => - -- --IO0 <= observation_vector_1(0 ); - -- IO1 <= observation_vector_1(1 ); - -- IO2 <= observation_vector_1(2 ); - -- IO3 <= observation_vector_1(3 ); - -- IO4 <= observation_vector_1(4 ); - -- IO5 <= observation_vector_1(5 ); - -- IO6 <= observation_vector_1(6 ); - -- IO7 <= observation_vector_1(7 ); IO8 <= observation_vector_1(8); IO9 <= observation_vector_1(9); IO10 <= observation_vector_1(10);