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Corrections des vecteurs entrant dans la FFT.
pellion -
r553:f7426aef3b86 (MINI-LFR) WFP_MS-0-1-65 JC
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 167 SIGNAL sample_val : STD_LOGIC;
168 168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171 171
172 172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173 173
174 174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 177 -----------------------------------------------------------------------------
178 178
179 179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 180 SIGNAL LFR_rstn : STD_LOGIC;
181 181
182 182
183 183 SIGNAL rstn_25 : STD_LOGIC;
184 184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 186 SIGNAL rstn_25_d3 : STD_LOGIC;
187 187
188 188 SIGNAL rstn_50 : STD_LOGIC;
189 189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 191 SIGNAL rstn_50_d3 : STD_LOGIC;
192 192
193 193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
195 195
196 196 --
197 197 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
198 198
199 199 --
200 200 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
201 201 SIGNAL HK_SEL : STD_LOGIC_VECTOR( 1 DOWNTO 0);
202 202
203 203 BEGIN -- beh
204 204
205 205 -----------------------------------------------------------------------------
206 206 -- CLK
207 207 -----------------------------------------------------------------------------
208 208
209 209 --PROCESS(clk_50)
210 210 --BEGIN
211 211 -- IF clk_50'EVENT AND clk_50 = '1' THEN
212 212 -- clk_50_s <= NOT clk_50_s;
213 213 -- END IF;
214 214 --END PROCESS;
215 215
216 216 --PROCESS(clk_50_s)
217 217 --BEGIN
218 218 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
219 219 -- clk_25 <= NOT clk_25;
220 220 -- END IF;
221 221 --END PROCESS;
222 222
223 223 --PROCESS(clk_49)
224 224 --BEGIN
225 225 -- IF clk_49'EVENT AND clk_49 = '1' THEN
226 226 -- clk_24 <= NOT clk_24;
227 227 -- END IF;
228 228 --END PROCESS;
229 229
230 230 --PROCESS(clk_25)
231 231 --BEGIN
232 232 -- IF clk_25'EVENT AND clk_25 = '1' THEN
233 233 -- rstn_25 <= reset;
234 234 -- END IF;
235 235 --END PROCESS;
236 236
237 237 PROCESS (clk_50, reset)
238 238 BEGIN -- PROCESS
239 239 IF reset = '0' THEN -- asynchronous reset (active low)
240 240 clk_50_s <= '0';
241 241 rstn_50 <= '0';
242 242 rstn_50_d1 <= '0';
243 243 rstn_50_d2 <= '0';
244 244 rstn_50_d3 <= '0';
245 245
246 246 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
247 247 clk_50_s <= NOT clk_50_s;
248 248 rstn_50_d1 <= '1';
249 249 rstn_50_d2 <= rstn_50_d1;
250 250 rstn_50_d3 <= rstn_50_d2;
251 251 rstn_50 <= rstn_50_d3;
252 252 END IF;
253 253 END PROCESS;
254 254
255 255 PROCESS (clk_50_s, rstn_50)
256 256 BEGIN -- PROCESS
257 257 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
258 258 clk_25 <= '0';
259 259 rstn_25 <= '0';
260 260 rstn_25_d1 <= '0';
261 261 rstn_25_d2 <= '0';
262 262 rstn_25_d3 <= '0';
263 263 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
264 264 clk_25 <= NOT clk_25;
265 265 rstn_25_d1 <= '1';
266 266 rstn_25_d2 <= rstn_25_d1;
267 267 rstn_25_d3 <= rstn_25_d2;
268 268 rstn_25 <= rstn_25_d3;
269 269 END IF;
270 270 END PROCESS;
271 271
272 272 PROCESS (clk_49, reset)
273 273 BEGIN -- PROCESS
274 274 IF reset = '0' THEN -- asynchronous reset (active low)
275 275 clk_24 <= '0';
276 276 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
277 277 clk_24 <= NOT clk_24;
278 278 END IF;
279 279 END PROCESS;
280 280
281 281 -----------------------------------------------------------------------------
282 282
283 283 PROCESS (clk_25, rstn_25)
284 284 BEGIN -- PROCESS
285 285 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
286 286 LED0 <= '0';
287 287 LED1 <= '0';
288 288 LED2 <= '0';
289 289 --IO1 <= '0';
290 290 --IO2 <= '1';
291 291 --IO3 <= '0';
292 292 --IO4 <= '0';
293 293 --IO5 <= '0';
294 294 --IO6 <= '0';
295 295 --IO7 <= '0';
296 296 --IO8 <= '0';
297 297 --IO9 <= '0';
298 298 --IO10 <= '0';
299 299 --IO11 <= '0';
300 300 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
301 301 LED0 <= '0';
302 302 LED1 <= '1';
303 303 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
304 304 --IO1 <= '1';
305 305 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
306 306 --IO3 <= ADC_SDO(0);
307 307 --IO4 <= ADC_SDO(1);
308 308 --IO5 <= ADC_SDO(2);
309 309 --IO6 <= ADC_SDO(3);
310 310 --IO7 <= ADC_SDO(4);
311 311 --IO8 <= ADC_SDO(5);
312 312 --IO9 <= ADC_SDO(6);
313 313 --IO10 <= ADC_SDO(7);
314 314 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
315 315 END IF;
316 316 END PROCESS;
317 317
318 318 PROCESS (clk_24, rstn_25)
319 319 BEGIN -- PROCESS
320 320 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
321 321 I00_s <= '0';
322 322 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
323 323 I00_s <= NOT I00_s;
324 324 END IF;
325 325 END PROCESS;
326 326 -- IO0 <= I00_s;
327 327
328 328 --UARTs
329 329 nCTS1 <= '1';
330 330 nCTS2 <= '1';
331 331 nDCD2 <= '1';
332 332
333 333 --
334 334
335 335 leon3_soc_1 : leon3_soc
336 336 GENERIC MAP (
337 337 fabtech => apa3e,
338 338 memtech => apa3e,
339 339 padtech => inferred,
340 340 clktech => inferred,
341 341 disas => 0,
342 342 dbguart => 0,
343 343 pclow => 2,
344 344 clk_freq => 25000,
345 345 IS_RADHARD => 0,
346 346 NB_CPU => 1,
347 347 ENABLE_FPU => 1,
348 348 FPU_NETLIST => 0,
349 349 ENABLE_DSU => 1,
350 350 ENABLE_AHB_UART => 1,
351 351 ENABLE_APB_UART => 1,
352 352 ENABLE_IRQMP => 1,
353 353 ENABLE_GPT => 1,
354 354 NB_AHB_MASTER => NB_AHB_MASTER,
355 355 NB_AHB_SLAVE => NB_AHB_SLAVE,
356 356 NB_APB_SLAVE => NB_APB_SLAVE,
357 357 ADDRESS_SIZE => 20,
358 358 USES_IAP_MEMCTRLR => 0)
359 359 PORT MAP (
360 360 clk => clk_25,
361 361 reset => rstn_25,
362 362 errorn => errorn,
363 363 ahbrxd => TXD1,
364 364 ahbtxd => RXD1,
365 365 urxd1 => TXD2,
366 366 utxd1 => RXD2,
367 367 address => SRAM_A,
368 368 data => SRAM_DQ,
369 369 nSRAM_BE0 => SRAM_nBE(0),
370 370 nSRAM_BE1 => SRAM_nBE(1),
371 371 nSRAM_BE2 => SRAM_nBE(2),
372 372 nSRAM_BE3 => SRAM_nBE(3),
373 373 nSRAM_WE => SRAM_nWE,
374 374 nSRAM_CE => SRAM_CE_s,
375 375 nSRAM_OE => SRAM_nOE,
376 376 nSRAM_READY => '0',
377 377 SRAM_MBE => OPEN,
378 378 apbi_ext => apbi_ext,
379 379 apbo_ext => apbo_ext,
380 380 ahbi_s_ext => ahbi_s_ext,
381 381 ahbo_s_ext => ahbo_s_ext,
382 382 ahbi_m_ext => ahbi_m_ext,
383 383 ahbo_m_ext => ahbo_m_ext);
384 384
385 385 SRAM_CE <= SRAM_CE_s(0);
386 386 -------------------------------------------------------------------------------
387 387 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
388 388 -------------------------------------------------------------------------------
389 389 apb_lfr_management_1 : apb_lfr_management
390 390 GENERIC MAP (
391 391 tech => apa3e,
392 392 pindex => 6,
393 393 paddr => 6,
394 394 pmask => 16#fff#,
395 395 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
396 396 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
397 397 PORT MAP (
398 398 clk25MHz => clk_25,
399 399 clk24_576MHz => clk_24, -- 49.152MHz/2
400 400 resetn => rstn_25,
401 401 grspw_tick => swno.tickout,
402 402 apbi => apbi_ext,
403 403 apbo => apbo_ext(6),
404 404 HK_sample => sample_hk,
405 405 HK_val => sample_val,
406 406 HK_sel => HK_SEL,
407 407 DAC_SDO => OPEN,
408 408 DAC_SCK => OPEN,
409 409 DAC_SYNC => OPEN,
410 410 DAC_CAL_EN => OPEN,
411 411 coarse_time => coarse_time,
412 412 fine_time => fine_time,
413 413 LFR_soft_rstn => LFR_soft_rstn
414 414 );
415 415
416 416 -----------------------------------------------------------------------
417 417 --- SpaceWire --------------------------------------------------------
418 418 -----------------------------------------------------------------------
419 419
420 420 SPW_EN <= '1';
421 421
422 422 spw_clk <= clk_50_s;
423 423 spw_rxtxclk <= spw_clk;
424 424 spw_rxclkn <= NOT spw_rxtxclk;
425 425
426 426 -- PADS for SPW1
427 427 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
428 428 PORT MAP (SPW_NOM_DIN, dtmp(0));
429 429 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
430 430 PORT MAP (SPW_NOM_SIN, stmp(0));
431 431 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
432 432 PORT MAP (SPW_NOM_DOUT, swno.d(0));
433 433 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
434 434 PORT MAP (SPW_NOM_SOUT, swno.s(0));
435 435 -- PADS FOR SPW2
436 436 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
437 437 PORT MAP (SPW_RED_SIN, dtmp(1));
438 438 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
439 439 PORT MAP (SPW_RED_DIN, stmp(1));
440 440 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
441 441 PORT MAP (SPW_RED_DOUT, swno.d(1));
442 442 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
443 443 PORT MAP (SPW_RED_SOUT, swno.s(1));
444 444
445 445 -- GRSPW PHY
446 446 --spw1_input: if CFG_SPW_GRSPW = 1 generate
447 447 spw_inputloop : FOR j IN 0 TO 1 GENERATE
448 448 spw_phy0 : grspw_phy
449 449 GENERIC MAP(
450 450 tech => apa3e,
451 451 rxclkbuftype => 1,
452 452 scantest => 0)
453 453 PORT MAP(
454 454 rxrst => swno.rxrst,
455 455 di => dtmp(j),
456 456 si => stmp(j),
457 457 rxclko => spw_rxclk(j),
458 458 do => swni.d(j),
459 459 ndo => swni.nd(j*5+4 DOWNTO j*5),
460 460 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
461 461 END GENERATE spw_inputloop;
462 462
463 463 swni.rmapnodeaddr <= (OTHERS => '0');
464 464
465 465 -- SPW core
466 466 sw0 : grspwm GENERIC MAP(
467 467 tech => apa3e,
468 468 hindex => 1,
469 469 pindex => 5,
470 470 paddr => 5,
471 471 pirq => 11,
472 472 sysfreq => 25000, -- CPU_FREQ
473 473 rmap => 1,
474 474 rmapcrc => 1,
475 475 fifosize1 => 16,
476 476 fifosize2 => 16,
477 477 rxclkbuftype => 1,
478 478 rxunaligned => 0,
479 479 rmapbufs => 4,
480 480 ft => 0,
481 481 netlist => 0,
482 482 ports => 2,
483 483 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
484 484 memtech => apa3e,
485 485 destkey => 2,
486 486 spwcore => 1
487 487 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
488 488 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
489 489 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
490 490 )
491 491 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
492 492 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
493 493 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
494 494 swni, swno);
495 495
496 496 swni.tickin <= '0';
497 497 swni.rmapen <= '1';
498 498 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
499 499 swni.tickinraw <= '0';
500 500 swni.timein <= (OTHERS => '0');
501 501 swni.dcrstval <= (OTHERS => '0');
502 502 swni.timerrstval <= (OTHERS => '0');
503 503
504 504 -------------------------------------------------------------------------------
505 505 -- LFR ------------------------------------------------------------------------
506 506 -------------------------------------------------------------------------------
507 507
508 508
509 509 LFR_rstn <= LFR_soft_rstn AND rstn_25;
510 510 --LFR_rstn <= rstn_25;
511 511
512 512 lpp_lfr_1 : lpp_lfr
513 513 GENERIC MAP (
514 514 Mem_use => use_RAM,
515 515 nb_data_by_buffer_size => 32,
516 516 nb_snapshot_param_size => 32,
517 517 delta_vector_size => 32,
518 518 delta_vector_size_f0_2 => 7, -- log2(96)
519 519 pindex => 15,
520 520 paddr => 15,
521 521 pmask => 16#fff#,
522 522 pirq_ms => 6,
523 523 pirq_wfp => 14,
524 524 hindex => 2,
525 top_lfr_version => X"000140") -- aa.bb.cc version
525 top_lfr_version => X"000141") -- aa.bb.cc version
526 526 PORT MAP (
527 527 clk => clk_25,
528 528 rstn => LFR_rstn,
529 529 sample_B => sample_s(2 DOWNTO 0),
530 530 sample_E => sample_s(7 DOWNTO 3),
531 531 sample_val => sample_val,
532 532 apbi => apbi_ext,
533 533 apbo => apbo_ext(15),
534 534 ahbi => ahbi_m_ext,
535 535 ahbo => ahbo_m_ext(2),
536 536 coarse_time => coarse_time,
537 537 fine_time => fine_time,
538 538 data_shaping_BW => bias_fail_sw_sig,
539 539 debug_vector => lfr_debug_vector,
540 540 debug_vector_ms => lfr_debug_vector_ms
541 541 );
542 542
543 543 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
544 544 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
545 545 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
546 546 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
547 547 IO0 <= rstn_25;
548 548 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
549 549 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
550 550 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
551 551 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
552 552 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
553 553 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
554 554 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
555 555
556 556 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
557 557 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
558 558 END GENERATE all_sample;
559 559
560 560 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
561 561 GENERIC MAP(
562 562 ChannelCount => 8,
563 563 SampleNbBits => 14,
564 564 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
565 565 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
566 566 PORT MAP (
567 567 -- CONV
568 568 cnv_clk => clk_24,
569 569 cnv_rstn => rstn_25,
570 570 cnv => ADC_nCS_sig,
571 571 -- DATA
572 572 clk => clk_25,
573 573 rstn => rstn_25,
574 574 sck => ADC_CLK_sig,
575 575 sdo => ADC_SDO_sig,
576 576 -- SAMPLE
577 577 sample => sample,
578 578 sample_val => sample_val);
579 579
580 580 --IO10 <= ADC_SDO_sig(5);
581 581 --IO9 <= ADC_SDO_sig(4);
582 582 --IO8 <= ADC_SDO_sig(3);
583 583
584 584 ADC_nCS <= ADC_nCS_sig;
585 585 ADC_CLK <= ADC_CLK_sig;
586 586 ADC_SDO_sig <= ADC_SDO;
587 587
588 588 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
589 589 "0010001000100010" WHEN HK_SEL = "01" ELSE
590 590 "0100010001000100" WHEN HK_SEL = "10" ELSE
591 591 (OTHERS => '0');
592 592
593 593
594 594 ----------------------------------------------------------------------
595 595 --- GPIO -----------------------------------------------------------
596 596 ----------------------------------------------------------------------
597 597
598 598 grgpio0 : grgpio
599 599 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
600 600 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
601 601
602 602 gpioi.sig_en <= (OTHERS => '0');
603 603 gpioi.sig_in <= (OTHERS => '0');
604 604 gpioi.din <= (OTHERS => '0');
605 605 --pio_pad_0 : iopad
606 606 -- GENERIC MAP (tech => CFG_PADTECH)
607 607 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
608 608 --pio_pad_1 : iopad
609 609 -- GENERIC MAP (tech => CFG_PADTECH)
610 610 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
611 611 --pio_pad_2 : iopad
612 612 -- GENERIC MAP (tech => CFG_PADTECH)
613 613 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
614 614 --pio_pad_3 : iopad
615 615 -- GENERIC MAP (tech => CFG_PADTECH)
616 616 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
617 617 --pio_pad_4 : iopad
618 618 -- GENERIC MAP (tech => CFG_PADTECH)
619 619 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
620 620 --pio_pad_5 : iopad
621 621 -- GENERIC MAP (tech => CFG_PADTECH)
622 622 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
623 623 --pio_pad_6 : iopad
624 624 -- GENERIC MAP (tech => CFG_PADTECH)
625 625 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
626 626 --pio_pad_7 : iopad
627 627 -- GENERIC MAP (tech => CFG_PADTECH)
628 628 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
629 629
630 630 PROCESS (clk_25, rstn_25)
631 631 BEGIN -- PROCESS
632 632 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
633 633 -- --IO0 <= '0';
634 634 -- IO1 <= '0';
635 635 -- IO2 <= '0';
636 636 -- IO3 <= '0';
637 637 -- IO4 <= '0';
638 638 -- IO5 <= '0';
639 639 -- IO6 <= '0';
640 640 -- IO7 <= '0';
641 641 IO8 <= '0';
642 642 IO9 <= '0';
643 643 IO10 <= '0';
644 644 IO11 <= '0';
645 645 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
646 646 CASE gpioo.dout(2 DOWNTO 0) IS
647 647 WHEN "011" =>
648 648 -- --IO0 <= observation_reg(0 );
649 649 -- IO1 <= observation_reg(1 );
650 650 -- IO2 <= observation_reg(2 );
651 651 -- IO3 <= observation_reg(3 );
652 652 -- IO4 <= observation_reg(4 );
653 653 -- IO5 <= observation_reg(5 );
654 654 -- IO6 <= observation_reg(6 );
655 655 -- IO7 <= observation_reg(7 );
656 656 IO8 <= observation_reg(8);
657 657 IO9 <= observation_reg(9);
658 658 IO10 <= observation_reg(10);
659 659 IO11 <= observation_reg(11);
660 660 WHEN "001" =>
661 661 -- --IO0 <= observation_reg(0 + 12);
662 662 -- IO1 <= observation_reg(1 + 12);
663 663 -- IO2 <= observation_reg(2 + 12);
664 664 -- IO3 <= observation_reg(3 + 12);
665 665 -- IO4 <= observation_reg(4 + 12);
666 666 -- IO5 <= observation_reg(5 + 12);
667 667 -- IO6 <= observation_reg(6 + 12);
668 668 -- IO7 <= observation_reg(7 + 12);
669 669 IO8 <= observation_reg(8 + 12);
670 670 IO9 <= observation_reg(9 + 12);
671 671 IO10 <= observation_reg(10 + 12);
672 672 IO11 <= observation_reg(11 + 12);
673 673 WHEN "010" =>
674 674 -- --IO0 <= observation_reg(0 + 12 + 12);
675 675 -- IO1 <= observation_reg(1 + 12 + 12);
676 676 -- IO2 <= observation_reg(2 + 12 + 12);
677 677 -- IO3 <= observation_reg(3 + 12 + 12);
678 678 -- IO4 <= observation_reg(4 + 12 + 12);
679 679 -- IO5 <= observation_reg(5 + 12 + 12);
680 680 -- IO6 <= observation_reg(6 + 12 + 12);
681 681 -- IO7 <= observation_reg(7 + 12 + 12);
682 682 IO8 <= '0';
683 683 IO9 <= '0';
684 684 IO10 <= '0';
685 685 IO11 <= '0';
686 686 WHEN "000" =>
687 687 -- --IO0 <= observation_vector_0(0 );
688 688 -- IO1 <= observation_vector_0(1 );
689 689 -- IO2 <= observation_vector_0(2 );
690 690 -- IO3 <= observation_vector_0(3 );
691 691 -- IO4 <= observation_vector_0(4 );
692 692 -- IO5 <= observation_vector_0(5 );
693 693 -- IO6 <= observation_vector_0(6 );
694 694 -- IO7 <= observation_vector_0(7 );
695 695 IO8 <= observation_vector_0(8);
696 696 IO9 <= observation_vector_0(9);
697 697 IO10 <= observation_vector_0(10);
698 698 IO11 <= observation_vector_0(11);
699 699 WHEN "100" =>
700 700 -- --IO0 <= observation_vector_1(0 );
701 701 -- IO1 <= observation_vector_1(1 );
702 702 -- IO2 <= observation_vector_1(2 );
703 703 -- IO3 <= observation_vector_1(3 );
704 704 -- IO4 <= observation_vector_1(4 );
705 705 -- IO5 <= observation_vector_1(5 );
706 706 -- IO6 <= observation_vector_1(6 );
707 707 -- IO7 <= observation_vector_1(7 );
708 708 IO8 <= observation_vector_1(8);
709 709 IO9 <= observation_vector_1(9);
710 710 IO10 <= observation_vector_1(10);
711 711 IO11 <= observation_vector_1(11);
712 712 WHEN OTHERS => NULL;
713 713 END CASE;
714 714
715 715 END IF;
716 716 END PROCESS;
717 717 -----------------------------------------------------------------------------
718 718 --
719 719 -----------------------------------------------------------------------------
720 720 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
721 721 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
722 722 apbo_ext(I) <= apb_none;
723 723 END GENERATE apbo_ext_not_used;
724 724 END GENERATE all_apbo_ext;
725 725
726 726
727 727 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
728 728 ahbo_s_ext(I) <= ahbs_none;
729 729 END GENERATE all_ahbo_ext;
730 730
731 731 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
732 732 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
733 733 ahbo_m_ext(I) <= ahbm_none;
734 734 END GENERATE ahbo_m_ext_not_used;
735 735 END GENERATE all_ahbo_m_ext;
736 736
737 737 END beh;
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@@ -1,199 +1,214
1 1 onerror {resume}
2 2 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(31 downto 0)} data_0
3 3 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(63 downto 32)} data_1
4 4 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(95 downto 64)} data_2
5 5 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(127 downto 96)} data_3
6 6 quietly virtual signal -install /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix { /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/rdata(159 downto 128)} data_4
7 7 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(15 downto 0)} f0_0
8 8 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(31 downto 16)} f0_1
9 9 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(47 downto 32)} f0_2
10 10 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(63 downto 48)} f0_4
11 11 quietly virtual signal -install /testbench/data_read_with_timer_f0 { /testbench/data_read_with_timer_f0/data_out(79 downto 64)} f0_4001
12 12 quietly WaveActivateNextPane {} 0
13 13 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/data_out_val
14 14 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/end_of_file
15 15 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_0 -radix decimal /testbench/data_read_with_timer_f0/f0_0
16 16 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_1 -radix decimal /testbench/data_read_with_timer_f0/f0_1
17 17 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_2 -radix decimal /testbench/data_read_with_timer_f0/f0_2
18 18 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_3 -radix decimal /testbench/data_read_with_timer_f0/f0_4
19 19 add wave -noupdate -expand -group DATA_GEN_F0 -label f0_4 -radix decimal /testbench/data_read_with_timer_f0/f0_4001
20 20 add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/data_out
21 21 add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/data_out_val
22 22 add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/end_of_file
23 23 add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/data_out
24 24 add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/data_out_val
25 25 add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/end_of_file
26 26 add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/data_out
27 27 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_addr
28 28 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_full
29 29 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_full_err
30 30 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_length
31 31 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_new
32 32 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_burst_valid
33 33 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_data
34 34 add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_ren
35 35 add wave -noupdate /testbench/dma_ren_counter
36 36 add wave -noupdate /testbench/dma_output_counter
37 37 add wave -noupdate -expand -group MEM_IN_MS -radix hexadecimal -childformat {{/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(0) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(1) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(2) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(3) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(4) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(5) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(6) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(7) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(8) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(9) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(10) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(11) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(12) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(13) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(14) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(15) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(16) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(17) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(18) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(19) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(20) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(21) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(22) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(23) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(24) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(25) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(26) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(27) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(28) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(29) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(30) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(31) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(32) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(33) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(34) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(35) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(36) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(37) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(38) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(39) -radix hexadecimal} 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/testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(24) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(25) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(26) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(27) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(28) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(29) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(30) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(31) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(32) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(33) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(34) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(35) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(36) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(37) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(38) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(39) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(40) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(41) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(42) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(43) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(44) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(45) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(46) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(47) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(48) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(49) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(50) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(51) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(52) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(53) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(54) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(55) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(56) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(57) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(58) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(59) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(60) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(61) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(62) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(63) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(64) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(65) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(66) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(67) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(68) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(69) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(70) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(71) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(72) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(73) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(74) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(75) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(76) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(77) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(78) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(79) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(80) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(81) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(82) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(83) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(84) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(85) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(86) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(87) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(88) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(89) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(90) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(91) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(92) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(93) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(94) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(95) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(96) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(97) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(98) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(99) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(100) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(101) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(102) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(103) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(104) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(105) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(106) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(107) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(108) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(109) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(110) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(111) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(112) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(113) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(114) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(115) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(116) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(117) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(118) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(119) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(120) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(121) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(122) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(123) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(124) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(125) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(126) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd(127) {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/fifos(4)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd
42 42 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_0
43 43 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(0)
44 44 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(0)
45 45 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(0)
46 46 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(0)
47 47 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(0)
48 48 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_1
49 49 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(1)
50 50 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(1)
51 51 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(1)
52 52 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(1)
53 53 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group fif0_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(1)
54 54 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_2
55 55 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(2)
56 56 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(2)
57 57 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(2)
58 58 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(2)
59 59 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_2 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(2)
60 60 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_3
61 61 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(3)
62 62 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(3)
63 63 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(3)
64 64 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(3)
65 65 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_3 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(3)
66 66 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/data_4
67 67 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ren(4)
68 68 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/wen(4)
69 69 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/full(4)
70 70 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/empty(4)
71 71 add wave -noupdate -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -expand -group MEM_IN_MS -expand -group MEM_IN_MS_control -group fif0_4 -radix hexadecimal /testbench/lpp_lfr_ms_1/Mem_In_SpectralMatrix/ReUse(4)
72 72 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/full_threshold
73 73 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/full
74 74 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/empty
75 75 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/full_almost
76 76 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/empty_threshold
77 77 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/wen
78 78 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/wdata
79 79 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/ren
80 80 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/rdata
81 81 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/run
82 82 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_0 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(0)/Mem_Out_SpectralMatrix_I/reUse
83 83 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/full_threshold
84 84 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/full
85 85 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/empty
86 86 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/full_almost
87 87 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/empty_threshold
88 88 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/wen
89 89 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/wdata
90 90 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix decimal -childformat {{/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(31) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(30) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(29) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(28) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(27) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(26) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(25) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(24) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(23) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(22) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(21) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(20) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(19) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(18) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(17) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(16) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(15) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(14) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(13) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(12) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(11) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(10) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(9) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(8) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(7) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(6) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(5) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(4) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(3) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(2) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(1) -radix hexadecimal} {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(0) -radix hexadecimal}} -subitemconfig {/testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(31) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(30) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(29) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(28) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(27) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(26) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(25) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(24) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(23) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(22) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(21) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(20) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(19) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(18) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(17) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(16) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(15) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(14) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(13) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(12) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(11) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(10) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(9) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(8) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(7) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(6) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(5) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(4) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(3) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(2) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(1) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata(0) {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/rdata
91 91 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/ren
92 92 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/run
93 93 add wave -noupdate -expand -group MEM_OUT_MS -expand -group fifo_1 -radix hexadecimal /testbench/lpp_lfr_ms_1/all_Mem_Out_SpectralMatrix(1)/Mem_Out_SpectralMatrix_I/reUse
94 94 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_ms_1/dma_fifo_data
95 95 add wave -noupdate -expand -group ALU_MS -radix decimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/RES
96 96 add wave -noupdate -expand -group ALU_MS -radix decimal -childformat {{/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(15) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(14) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(13) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(12) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(11) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(10) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(9) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(8) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(7) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(6) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(5) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(4) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(3) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(2) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(1) -radix decimal} {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(0) -radix decimal}} -subitemconfig {/testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(15) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(14) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(13) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(12) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(11) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(10) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(9) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(8) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(7) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(6) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(5) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(4) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(3) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(2) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(1) {-height 15 -radix decimal} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2(0) {-height 15 -radix decimal}} /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP2
97 97 add wave -noupdate -expand -group ALU_MS -radix decimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/OP1
98 98 add wave -noupdate -expand -group ALU_MS -radix hexadecimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/comp
99 99 add wave -noupdate -expand -group ALU_MS -radix hexadecimal /testbench/lpp_lfr_ms_1/MS_calculation_1/ALU_MS/ctrl
100 100 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_control_1/state
101 101 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/state
102 102 add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_data
103 103 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_ren
104 104 add wave -noupdate /testbench/lpp_lfr_ms_1/MEM_OUT_SM_Full
105 105 add wave -noupdate /testbench/lpp_lfr_ms_1/MEM_OUT_SM_Full_s
106 106 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done
107 107 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done_reg1
108 108 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done_reg2
109 109 add wave -noupdate /testbench/lpp_lfr_ms_1/SM_correlation_done_reg3
110 110 add wave -noupdate /testbench/lpp_lfr_ms_1/current_matrix_wait_empty
111 111 add wave -noupdate /testbench/lpp_lfr_ms_1/current_matrix_write
112 112 add wave -noupdate /testbench/lpp_lfr_ms_1/MEM_OUT_SM_Empty
113 113 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_fifo_ren
114 114 add wave -noupdate /testbench/lpp_lfr_ms_1/addr_matrix_f2
115 115 add wave -noupdate /testbench/lpp_lfr_ms_1/addr_matrix_f1
116 116 add wave -noupdate /testbench/lpp_lfr_ms_1/length_matrix_f2
117 117 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_full
118 118 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_full_err
119 119 add wave -noupdate /testbench/lpp_lfr_ms_1/addr_matrix_f0
120 120 add wave -noupdate /testbench/lpp_lfr_ms_1/status_ready_matrix_f2
121 121 add wave -noupdate /testbench/lpp_lfr_ms_1/status_ready_matrix_f1
122 122 add wave -noupdate /testbench/lpp_lfr_ms_1/status_ready_matrix_f0
123 123 add wave -noupdate /testbench/lpp_lfr_ms_1/current_matrix_write
124 124 add wave -noupdate /testbench/lpp_lfr_ms_1/matrix_time_f2
125 125 add wave -noupdate /testbench/lpp_lfr_ms_1/matrix_time_f1
126 126 add wave -noupdate /testbench/lpp_lfr_ms_1/matrix_time_f0
127 127 add wave -noupdate /testbench/lpp_lfr_ms_1/error_input_fifo_write
128 128 add wave -noupdate /testbench/lpp_lfr_ms_1/error_buffer_full
129 129 add wave -noupdate /testbench/lpp_lfr_ms_1/ready_matrix_f2
130 130 add wave -noupdate /testbench/lpp_lfr_ms_1/ready_matrix_f1
131 131 add wave -noupdate /testbench/lpp_lfr_ms_1/ready_matrix_f0
132 132 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_length
133 133 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_addr
134 134 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_buffer_new
135 135 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_fifo_data
136 136 add wave -noupdate /testbench/lpp_lfr_ms_1/dma_fifo_burst_valid
137 137 add wave -noupdate /testbench/lpp_lfr_ms_1/debug_vector
138 138 add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state
139 139 add wave -noupdate /testbench/lpp_lfr_ms_1/fifo_0_ready
140 140 add wave -noupdate /testbench/lpp_lfr_ms_1/fifo_1_ready
141 141 add wave -noupdate /testbench/lpp_lfr_ms_1/fifo_ongoing
142 142 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_0
143 143 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_1
144 144 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_0_end
145 145 add wave -noupdate /testbench/lpp_lfr_ms_1/status_component_fifo_1_end
146 146 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/state
147 147 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_empty
148 148 add wave -noupdate /testbench/lpp_lfr_ms_1/MS_calculation_1/fifo_in_empty_reg
149 149 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/start_date
150 150 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/coarse_time
151 151 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f0_wen
152 152 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f0_wdata
153 153 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f1_wen
154 154 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f1_wdata
155 155 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f2_wen
156 156 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/sample_f2_wdata
157 157 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/length_matrix_f1
158 158 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/length_matrix_f0
159 159 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_fifo_ren
160 160 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/addr_matrix_f2
161 161 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/addr_matrix_f1
162 162 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/length_matrix_f2
163 163 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_full
164 164 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_full_err
165 165 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/addr_matrix_f0
166 166 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/status_ready_matrix_f2
167 167 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/status_ready_matrix_f1
168 168 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/status_ready_matrix_f0
169 169 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/matrix_time_f2
170 170 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/matrix_time_f1
171 171 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/matrix_time_f0
172 172 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/error_input_fifo_write
173 173 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/error_buffer_full
174 174 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/ready_matrix_f2
175 175 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/ready_matrix_f1
176 176 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/ready_matrix_f0
177 177 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_length
178 178 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_addr
179 179 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_new
180 180 add wave -noupdate -expand -group TOP_IN_OUT -radix decimal /testbench/lpp_lfr_ms_1/dma_fifo_data
181 181 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_fifo_burst_valid
182 add wave -noupdate -expand -group FFT /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_pong
183 add wave -noupdate -expand -group FFT /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_ready
184 add wave -noupdate -expand -group FFT -expand -group IN -format Analog-Step -height 74 -max 4096.0 -min -1800.0 -radix decimal /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/sample_data
185 add wave -noupdate -expand -group FFT -expand -group IN /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/sample_load
186 add wave -noupdate -expand -group FFT -expand -group IN /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_read
187 add wave -noupdate -expand -group FFT -expand -group IN /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/sample_valid
188 add wave -noupdate -expand -group FFT -expand -group OUT -radix decimal /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_data_im
189 add wave -noupdate -expand -group FFT -expand -group OUT -radix decimal /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_data_re
190 add wave -noupdate -expand -group FFT -expand -group OUT /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_data_valid
191 add wave -noupdate /testbench/lpp_lfr_ms_1/sample_valid
192 add wave -noupdate /testbench/lpp_lfr_ms_1/sample_valid_delay
193 add wave -noupdate /testbench/lpp_lfr_ms_1/sample_valid_r
194 add wave -noupdate /testbench/lpp_lfr_ms_1/state_fsm_load_FFT
195 add wave -noupdate -expand /testbench/lpp_lfr_ms_1/sample_f0_A_ren
196 add wave -noupdate /testbench/lpp_lfr_ms_1/sample_f0_B_ren
182 197 TreeUpdate [SetDefaultTree]
183 WaveRestoreCursors {WDATA_1 {10541340000 ps} 1} {WDATA_2 {10541500000 ps} 1} {WDATA_8 {10542460000 ps} 1} {WDATA_16 {10543740000 ps} 1} {{Cursor 9} {10572740000 ps} 0} {{Cursor 10} {6346220000 ps} 0}
184 quietly wave cursor active 6
198 WaveRestoreCursors {WDATA_1 {10541340000 ps} 1} {WDATA_2 {10541500000 ps} 1} {WDATA_8 {10542460000 ps} 1} {WDATA_16 {10543740000 ps} 1} {{Cursor 9} {10490580000 ps} 0} {{Cursor 10} {6346220000 ps} 0}
199 quietly wave cursor active 5
185 200 configure wave -namecolwidth 573
186 201 configure wave -valuecolwidth 108
187 202 configure wave -justifyvalue left
188 203 configure wave -signalnamewidth 0
189 204 configure wave -snapdistance 10
190 205 configure wave -datasetprefix 0
191 206 configure wave -rowmargin 4
192 207 configure wave -childrowmargin 2
193 208 configure wave -gridoffset 0
194 209 configure wave -gridperiod 1
195 210 configure wave -griddelta 40
196 211 configure wave -timeline 0
197 212 configure wave -timelineunits ns
198 213 update
199 WaveRestoreZoom {0 ps} {14085099 ns}
214 WaveRestoreZoom {10489250172 ps} {10491702980 ps}
Show file before | Show file after | Hide comments
@@ -1,1220 +1,1249
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5
6 6 LIBRARY lpp;
7 7 USE lpp.lpp_memory.ALL;
8 8 USE lpp.iir_filter.ALL;
9 9 USE lpp.spectral_matrix_package.ALL;
10 10 USE lpp.lpp_dma_pkg.ALL;
11 11 USE lpp.lpp_Header.ALL;
12 12 USE lpp.lpp_matrix.ALL;
13 13 USE lpp.lpp_matrix.ALL;
14 14 USE lpp.lpp_lfr_pkg.ALL;
15 15 USE lpp.lpp_fft.ALL;
16 16 USE lpp.fft_components.ALL;
17 17
18 18 ENTITY lpp_lfr_ms IS
19 19 GENERIC (
20 20 Mem_use : INTEGER := use_RAM
21 21 );
22 22 PORT (
23 23 clk : IN STD_LOGIC;
24 24 rstn : IN STD_LOGIC;
25 25 run : IN STD_LOGIC;
26 26
27 27 ---------------------------------------------------------------------------
28 28 -- DATA INPUT
29 29 ---------------------------------------------------------------------------
30 30 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
31 31 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
32 32 --fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
33 33 --
34 34 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
35 35 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 36 sample_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
37 37 --
38 38 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 39 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40 40 sample_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
41 41 --
42 42 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
43 43 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
44 44 sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
45 45
46 46 ---------------------------------------------------------------------------
47 47 -- DMA
48 48 ---------------------------------------------------------------------------
49 49 dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
50 50 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
51 51 dma_fifo_ren : IN STD_LOGIC; --TODO
52 52 dma_buffer_new : OUT STD_LOGIC; --TODOx
53 53 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
54 54 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
55 55 dma_buffer_full : IN STD_LOGIC; --TODO
56 56 dma_buffer_full_err : IN STD_LOGIC; --TODO
57 57
58 58 -- Reg out
59 59 ready_matrix_f0 : OUT STD_LOGIC; -- TODO
60 60 ready_matrix_f1 : OUT STD_LOGIC; -- TODO
61 61 ready_matrix_f2 : OUT STD_LOGIC; -- TODO
62 62 -- error_bad_component_error : OUT STD_LOGIC; -- TODO
63 63 error_buffer_full : OUT STD_LOGIC; -- TODO
64 64 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
65 65
66 66 -- Reg In
67 67 status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
68 68 status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
69 69 status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
70 70
71 71 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
72 72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
73 73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
74 74
75 75 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
76 76 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
77 77 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
78 78
79 79 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
80 80 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
81 81 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
82 82 ---------------------------------------------------------------------------
83 83 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
84 84 );
85 85 END;
86 86
87 87 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
88 88
89 89 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
90 90 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 91 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 92 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 93 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 94
95 95 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
96 96 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 97 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 98 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 99 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 100
101 101 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
102 102 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
103 103 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
104 104 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 105
106 106 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 107
108 108 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
109 109 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
110 110 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
111 111 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
112 112
113 113 SIGNAL error_wen_f0 : STD_LOGIC;
114 114 SIGNAL error_wen_f1 : STD_LOGIC;
115 115 SIGNAL error_wen_f2 : STD_LOGIC;
116 116
117 117 SIGNAL one_sample_f1_full : STD_LOGIC;
118 118 SIGNAL one_sample_f1_wen : STD_LOGIC;
119 119 SIGNAL one_sample_f2_full : STD_LOGIC;
120 120 SIGNAL one_sample_f2_wen : STD_LOGIC;
121 121
122 122 -----------------------------------------------------------------------------
123 123 -- FSM / SWITCH SELECT CHANNEL
124 124 -----------------------------------------------------------------------------
125 125 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
126 126 SIGNAL state_fsm_select_channel : fsm_select_channel;
127 127 -- SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
128 128 SIGNAL select_channel : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 129 SIGNAL select_channel_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
130 130
131 131 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 132 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
133 133 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
134 134 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
135 135
136 136 -----------------------------------------------------------------------------
137 137 -- FSM LOAD FFT
138 138 -----------------------------------------------------------------------------
139 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
139 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5, WAIT_STATE, WAIT_STATE_2);
140 140 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
141 -- SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
141 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
142 142 SIGNAL select_fifo : STD_LOGIC_VECTOR(2 DOWNTO 0);
143 143 SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
144 144
145 145 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
146 146 SIGNAL sample_load : STD_LOGIC;
147 147 SIGNAL sample_valid : STD_LOGIC;
148 148 SIGNAL sample_valid_r : STD_LOGIC;
149 SIGNAL sample_valid_delay : STD_LOGIC;
149 150 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
150 151
151 152
152 153 -----------------------------------------------------------------------------
153 154 -- FFT
154 155 -----------------------------------------------------------------------------
155 156 SIGNAL fft_read : STD_LOGIC;
156 157 SIGNAL fft_pong : STD_LOGIC;
157 158 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
158 159 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
159 160 SIGNAL fft_data_valid : STD_LOGIC;
161 SIGNAL fft_data_valid_pre : STD_LOGIC;
160 162 SIGNAL fft_ready : STD_LOGIC;
161 163 -----------------------------------------------------------------------------
162 164 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
163 165 -----------------------------------------------------------------------------
164 166 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
165 167 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
166 168 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 169 SIGNAL current_fifo_empty : STD_LOGIC;
168 170 SIGNAL current_fifo_locked : STD_LOGIC;
169 171 SIGNAL current_fifo_full : STD_LOGIC;
170 172 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 173
172 174 -----------------------------------------------------------------------------
173 175 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
174 176 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
175 177 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
176 178 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
177 179 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
178 180 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
179 181 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
180 182 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
181 183 -----------------------------------------------------------------------------
182 184 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
183 185 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
184 186 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
185 187
186 188 SIGNAL SM_correlation_start : STD_LOGIC;
187 189 SIGNAL SM_correlation_auto : STD_LOGIC;
188 190 SIGNAL SM_correlation_done : STD_LOGIC;
189 191 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
190 192 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
191 193 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
192 194 SIGNAL SM_correlation_begin : STD_LOGIC;
193 195
194 196 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
195 197 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 198 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
197 199
198 200 SIGNAL current_matrix_write : STD_LOGIC;
199 201 SIGNAL current_matrix_wait_empty : STD_LOGIC;
200 202 -----------------------------------------------------------------------------
201 203 SIGNAL fifo_0_ready : STD_LOGIC;
202 204 SIGNAL fifo_1_ready : STD_LOGIC;
203 205 SIGNAL fifo_ongoing : STD_LOGIC;
204 206 SIGNAL fifo_ongoing_reg : STD_LOGIC;
205 207
206 208 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
207 209 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
208 210 SIGNAL FSM_DMA_fifo_empty_threshold : STD_LOGIC;
209 211 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
210 212 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 4);
211 213 -----------------------------------------------------------------------------
212 214 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
213 215 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
214 216 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
215 217 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
216 218 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
217 219 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
218 220 SIGNAL MEM_OUT_SM_Empty_Threshold : STD_LOGIC_VECTOR(1 DOWNTO 0);
219 221
220 222 -----------------------------------------------------------------------------
221 223 -- TIME REG & INFOs
222 224 -----------------------------------------------------------------------------
223 225 SIGNAL all_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
224 226
225 227 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
226 228 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
227 229 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
228 230 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
229 231
230 232 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
231 233 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
232 234 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
233 235 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
234 236
235 237 --SIGNAL time_update_f0_A : STD_LOGIC;
236 238 --SIGNAL time_update_f0_B : STD_LOGIC;
237 239 --SIGNAL time_update_f1 : STD_LOGIC;
238 240 --SIGNAL time_update_f2 : STD_LOGIC;
239 241 --
240 242 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
241 243 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
242 244 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
243 245
244 246 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 4);
245 247 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 4);
246 248 SIGNAL status_component_fifo_0_end : STD_LOGIC;
247 249 SIGNAL status_component_fifo_1_end : STD_LOGIC;
248 250 -----------------------------------------------------------------------------
249 251 SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
250 252
251 253 SIGNAL fft_ready_reg : STD_LOGIC;
252 254 SIGNAL fft_ready_rising_down : STD_LOGIC;
253 255
254 256 SIGNAL sample_load_reg : STD_LOGIC;
255 257 SIGNAL sample_load_rising_down : STD_LOGIC;
256 258
257 259 -----------------------------------------------------------------------------
258 260 SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0);
259 261 SIGNAL sample_f1_wen_head_in : STD_LOGIC;
260 262 SIGNAL sample_f1_wen_head_out : STD_LOGIC;
261 263 SIGNAL sample_f1_full_head_in : STD_LOGIC;
262 264 SIGNAL sample_f1_full_head_out : STD_LOGIC;
263 265 SIGNAL sample_f1_empty_head_in : STD_LOGIC;
264 266
265 267 SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
266 268 -----------------------------------------------------------------------------
267 269 SIGNAL sample_f0_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
268 270 SIGNAL sample_f1_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
269 271 SIGNAL sample_f2_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
270 272 SIGNAL ongoing : STD_LOGIC;
271 273
272 274 BEGIN
273 275
274 276 PROCESS (clk, rstn)
275 277 BEGIN -- PROCESS
276 278 IF rstn = '0' THEN -- asynchronous reset (active low)
277 279 sample_f0_wen_s <= (OTHERS => '1');
278 280 sample_f1_wen_s <= (OTHERS => '1');
279 281 sample_f2_wen_s <= (OTHERS => '1');
280 282 ongoing <= '0';
281 283 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
282 284 IF ongoing = '1' THEN
283 285 sample_f0_wen_s <= sample_f0_wen;
284 286 sample_f1_wen_s <= sample_f1_wen;
285 287 sample_f2_wen_s <= sample_f2_wen;
286 288 ELSE
287 289 IF start_date = coarse_time(30 DOWNTO 0) THEN
288 290 ongoing <= '1';
289 291 END IF;
290 292 sample_f0_wen_s <= (OTHERS => '1');
291 293 sample_f1_wen_s <= (OTHERS => '1');
292 294 sample_f2_wen_s <= (OTHERS => '1');
293 295 END IF;
294 296 END IF;
295 297 END PROCESS;
296 298
297 299
298 300 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
299 301
300 302
301 303 switch_f0_inst : spectral_matrix_switch_f0
302 304 PORT MAP (
303 305 clk => clk,
304 306 rstn => rstn,
305 307
306 308 sample_wen => sample_f0_wen_s,
307 309
308 310 fifo_A_empty => sample_f0_A_empty,
309 311 fifo_A_full => sample_f0_A_full,
310 312 fifo_A_wen => sample_f0_A_wen,
311 313
312 314 fifo_B_empty => sample_f0_B_empty,
313 315 fifo_B_full => sample_f0_B_full,
314 316 fifo_B_wen => sample_f0_B_wen,
315 317
316 318 error_wen => error_wen_f0); -- TODO
317 319
318 320 -----------------------------------------------------------------------------
319 321 -- FIFO IN
320 322 -----------------------------------------------------------------------------
321 323 lppFIFOxN_f0_a : lppFIFOxN
322 324 GENERIC MAP (
323 325 tech => 0,
324 326 Mem_use => Mem_use,
325 327 Data_sz => 16,
326 328 Addr_sz => 8,
327 329 FifoCnt => 5)
328 330 PORT MAP (
329 331 clk => clk,
330 332 rstn => rstn,
331 333
332 334 ReUse => (OTHERS => '0'),
333 335
334 336 run => (OTHERS => '1'),
335 337
336 338 wen => sample_f0_A_wen,
337 339 wdata => sample_f0_wdata,
338 340
339 341 ren => sample_f0_A_ren,
340 342 rdata => sample_f0_A_rdata,
341 343
342 344 empty => sample_f0_A_empty,
343 345 full => sample_f0_A_full,
344 346 almost_full => OPEN);
345 347
346 348 lppFIFOxN_f0_b : lppFIFOxN
347 349 GENERIC MAP (
348 350 tech => 0,
349 351 Mem_use => Mem_use,
350 352 Data_sz => 16,
351 353 Addr_sz => 8,
352 354 FifoCnt => 5)
353 355 PORT MAP (
354 356 clk => clk,
355 357 rstn => rstn,
356 358
357 359 ReUse => (OTHERS => '0'),
358 360 run => (OTHERS => '1'),
359 361
360 362 wen => sample_f0_B_wen,
361 363 wdata => sample_f0_wdata,
362 364 ren => sample_f0_B_ren,
363 365 rdata => sample_f0_B_rdata,
364 366 empty => sample_f0_B_empty,
365 367 full => sample_f0_B_full,
366 368 almost_full => OPEN);
367 369
368 370 -----------------------------------------------------------------------------
369 371 -- sample_f1_wen in
370 372 -- sample_f1_wdata in
371 373 -- sample_f1_full OUT
372 374
373 375 sample_f1_wen_head_in <= '0' WHEN sample_f1_wen_s = "00000" ELSE '1';
374 376 sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1';
375 377 sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
376 378
377 379 lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
378 380 PORT MAP (
379 381 clk => clk,
380 382 rstn => rstn,
381 383 in_wen => sample_f1_wen_head_in,
382 384 in_data => sample_f1_wdata,
383 385 in_full => sample_f1_full_head_in,
384 386 in_empty => sample_f1_empty_head_in,
385 387 out_write_error => error_wen_f1,
386 388 out_wen => sample_f1_wen_head_out,
387 389 out_data => sample_f1_wdata_head,
388 390 out_full => sample_f1_full_head_out);
389 391
390 392 sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
391 393
392 394
393 395 lppFIFOxN_f1 : lppFIFOxN
394 396 GENERIC MAP (
395 397 tech => 0,
396 398 Mem_use => Mem_use,
397 399 Data_sz => 16,
398 400 Addr_sz => 8,
399 401 FifoCnt => 5)
400 402 PORT MAP (
401 403 clk => clk,
402 404 rstn => rstn,
403 405
404 406 ReUse => (OTHERS => '0'),
405 407 run => (OTHERS => '1'),
406 408
407 409 wen => sample_f1_wen_head,
408 410 wdata => sample_f1_wdata_head,
409 411 ren => sample_f1_ren,
410 412 rdata => sample_f1_rdata,
411 413 empty => sample_f1_empty,
412 414 full => sample_f1_full,
413 415 almost_full => sample_f1_almost_full);
414 416
415 417
416 418 one_sample_f1_wen <= '0' WHEN sample_f1_wen_head = "11111" ELSE '1';
417 419
418 420 PROCESS (clk, rstn)
419 421 BEGIN -- PROCESS
420 422 IF rstn = '0' THEN -- asynchronous reset (active low)
421 423 one_sample_f1_full <= '0';
422 424 --error_wen_f1 <= '0';
423 425 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
424 426 IF sample_f1_full_head_out = '0' THEN
425 427 one_sample_f1_full <= '0';
426 428 ELSE
427 429 one_sample_f1_full <= '1';
428 430 END IF;
429 431 --error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
430 432 END IF;
431 433 END PROCESS;
432 434
433 435 -----------------------------------------------------------------------------
434 436
435 437
436 438 lppFIFOxN_f2 : lppFIFOxN
437 439 GENERIC MAP (
438 440 tech => 0,
439 441 Mem_use => Mem_use,
440 442 Data_sz => 16,
441 443 Addr_sz => 8,
442 444 FifoCnt => 5)
443 445 PORT MAP (
444 446 clk => clk,
445 447 rstn => rstn,
446 448
447 449 ReUse => (OTHERS => '0'),
448 450 run => (OTHERS => '1'),
449 451
450 452 wen => sample_f2_wen_s,
451 453 wdata => sample_f2_wdata,
452 454 ren => sample_f2_ren,
453 455 rdata => sample_f2_rdata,
454 456 empty => sample_f2_empty,
455 457 full => sample_f2_full,
456 458 almost_full => OPEN);
457 459
458 460
459 461 one_sample_f2_wen <= '0' WHEN sample_f2_wen_s = "11111" ELSE '1';
460 462
461 463 PROCESS (clk, rstn)
462 464 BEGIN -- PROCESS
463 465 IF rstn = '0' THEN -- asynchronous reset (active low)
464 466 one_sample_f2_full <= '0';
465 467 error_wen_f2 <= '0';
466 468 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
467 469 IF sample_f2_full = "00000" THEN
468 470 one_sample_f2_full <= '0';
469 471 ELSE
470 472 one_sample_f2_full <= '1';
471 473 END IF;
472 474 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
473 475 END IF;
474 476 END PROCESS;
475 477
476 478 -----------------------------------------------------------------------------
477 479 -- FSM SELECT CHANNEL
478 480 -----------------------------------------------------------------------------
479 481 PROCESS (clk, rstn)
480 482 BEGIN
481 483 IF rstn = '0' THEN
482 484 state_fsm_select_channel <= IDLE;
483 485 select_channel <= (OTHERS => '0');
484 486 ELSIF clk'EVENT AND clk = '1' THEN
485 487 CASE state_fsm_select_channel IS
486 488 WHEN IDLE =>
487 489 IF sample_f1_full = "11111" THEN
488 490 state_fsm_select_channel <= SWITCH_F1;
489 491 select_channel <= "10";
490 492 ELSIF sample_f1_almost_full = "00000" THEN
491 493 IF sample_f0_A_full = "11111" THEN
492 494 state_fsm_select_channel <= SWITCH_F0_A;
493 495 select_channel <= "00";
494 496 ELSIF sample_f0_B_full = "11111" THEN
495 497 state_fsm_select_channel <= SWITCH_F0_B;
496 498 select_channel <= "01";
497 499 ELSIF sample_f2_full = "11111" THEN
498 500 state_fsm_select_channel <= SWITCH_F2;
499 501 select_channel <= "11";
500 502 END IF;
501 503 END IF;
502 504
503 505 WHEN SWITCH_F0_A =>
504 506 IF sample_f0_A_empty = "11111" THEN
505 507 state_fsm_select_channel <= IDLE;
506 508 select_channel <= (OTHERS => '0');
507 509 END IF;
508 510 WHEN SWITCH_F0_B =>
509 511 IF sample_f0_B_empty = "11111" THEN
510 512 state_fsm_select_channel <= IDLE;
511 513 select_channel <= (OTHERS => '0');
512 514 END IF;
513 515 WHEN SWITCH_F1 =>
514 516 IF sample_f1_empty = "11111" THEN
515 517 state_fsm_select_channel <= IDLE;
516 518 select_channel <= (OTHERS => '0');
517 519 END IF;
518 520 WHEN SWITCH_F2 =>
519 521 IF sample_f2_empty = "11111" THEN
520 522 state_fsm_select_channel <= IDLE;
521 523 select_channel <= (OTHERS => '0');
522 524 END IF;
523 525 WHEN OTHERS => NULL;
524 526 END CASE;
525 527
526 528 END IF;
527 529 END PROCESS;
528 530
529 531 PROCESS (clk, rstn)
530 532 BEGIN
531 533 IF rstn = '0' THEN
532 534 select_channel_reg <= (OTHERS => '0');
533 535 --pre_state_fsm_select_channel <= IDLE;
534 536 ELSIF clk'EVENT AND clk = '1' THEN
535 537 select_channel_reg <= select_channel;
536 538 --pre_state_fsm_select_channel <= state_fsm_select_channel;
537 539 END IF;
538 540 END PROCESS;
539 541
540 542
541 543 -----------------------------------------------------------------------------
542 544 -- SWITCH SELECT CHANNEL
543 545 -----------------------------------------------------------------------------
544 546 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
545 547 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
546 548 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
547 549 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
548 550 (OTHERS => '1');
549 551
550 552 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
551 553 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
552 554 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
553 555 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
554 556 (OTHERS => '0');
555 557
556 558 --sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
557 559 -- sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
558 560 -- sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
559 561 -- sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
560 562 sample_rdata <= sample_f0_A_rdata WHEN select_channel_reg = "00" ELSE
561 563 sample_f0_B_rdata WHEN select_channel_reg = "01" ELSE
562 564 sample_f1_rdata WHEN select_channel_reg = "10" ELSE
563 565 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
564 566
565 567
566 568 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
567 569 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
568 570 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
569 571 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
570 572
571 573
572 574 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
573 575 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
574 576 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
575 577 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
576 578
577 579 -----------------------------------------------------------------------------
578 580 -- FSM LOAD FFT
579 581 -----------------------------------------------------------------------------
580 582
581 583 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
582 584 sample_ren_s WHEN sample_load = '1' ELSE
583 585 (OTHERS => '1');
584 586
585 587 PROCESS (clk, rstn)
586 588 BEGIN
587 589 IF rstn = '0' THEN
588 590 sample_ren_s <= (OTHERS => '1');
589 591 state_fsm_load_FFT <= IDLE;
590 592 status_MS_input <= (OTHERS => '0');
591 593 select_fifo <= "000";
592 594 --next_state_fsm_load_FFT <= IDLE;
593 595 --sample_valid <= '0';
594 596 ELSIF clk'EVENT AND clk = '1' THEN
595 597 CASE state_fsm_load_FFT IS
596 598 WHEN IDLE =>
597 599 --sample_valid <= '0';
598 600 sample_ren_s <= (OTHERS => '1');
599 601 IF sample_full = "11111" AND sample_load = '1' THEN
602 sample_ren_s <= "11111";
600 603 state_fsm_load_FFT <= FIFO_1;
601 604 status_MS_input <= status_channel;
602 select_fifo <= "000";
605 select_fifo <= "000";
603 606 END IF;
604 607
605 608 WHEN FIFO_1 =>
606 609 sample_ren_s <= "1111" & NOT(sample_load);
607 610 IF sample_empty(0) = '1' THEN
608 sample_ren_s <= (OTHERS => '1');
609 state_fsm_load_FFT <= FIFO_2;
611 sample_ren_s <= "11111";
612 state_fsm_load_FFT <= WAIT_STATE;
613 next_state_fsm_load_FFT <= FIFO_2;
610 614 select_fifo <= "001";
611 615 END IF;
612 616
613 617 WHEN FIFO_2 =>
614 618 sample_ren_s <= "111" & NOT(sample_load) & '1';
615 619 IF sample_empty(1) = '1' THEN
616 sample_ren_s <= (OTHERS => '1');
617 state_fsm_load_FFT <= FIFO_3;
620 sample_ren_s <= "11111";
621 state_fsm_load_FFT <= WAIT_STATE;
622 next_state_fsm_load_FFT <= FIFO_3;
618 623 select_fifo <= "010";
619 624 END IF;
620 625
621 626 WHEN FIFO_3 =>
622 627 sample_ren_s <= "11" & NOT(sample_load) & "11";
623 628 IF sample_empty(2) = '1' THEN
624 sample_ren_s <= (OTHERS => '1');
625 state_fsm_load_FFT <= FIFO_4;
629 sample_ren_s <= "11111";
630 state_fsm_load_FFT <= WAIT_STATE;
631 next_state_fsm_load_FFT <= FIFO_4;
626 632 select_fifo <= "011";
627 633 END IF;
628 634
629 635 WHEN FIFO_4 =>
630 636 sample_ren_s <= '1' & NOT(sample_load) & "111";
631 637 IF sample_empty(3) = '1' THEN
632 sample_ren_s <= (OTHERS => '1');
633 state_fsm_load_FFT <= FIFO_5;
638 sample_ren_s <= "11111";
639 state_fsm_load_FFT <= WAIT_STATE;
640 next_state_fsm_load_FFT <= FIFO_5;
634 641 select_fifo <= "100";
635 642 END IF;
636 643
637 644 WHEN FIFO_5 =>
638 645 sample_ren_s <= NOT(sample_load) & "1111";
639 646 IF sample_empty(4) = '1' THEN
640 647 sample_ren_s <= (OTHERS => '1');
641 648 state_fsm_load_FFT <= IDLE;
642 649 select_fifo <= "000";
643 650 END IF;
651
652 WHEN WAIT_STATE =>
653 sample_ren_s <= (OTHERS => '1');
654 IF sample_load = '1' THEN
655 state_fsm_load_FFT <= WAIT_STATE_2 ;
656 END IF;
657
658 WHEN WAIT_STATE_2 =>
659 sample_ren_s <= (OTHERS => '1');
660 IF fft_data_valid = '0' AND fft_data_valid_pre = '1' THEN
661 state_fsm_load_FFT <= next_state_fsm_load_FFT;
662 END IF;
663
644 664 WHEN OTHERS => NULL;
645 665 END CASE;
646 666 END IF;
647 667 END PROCESS;
648 668
649 669 PROCESS (clk, rstn)
670 BEGIN -- PROCESS
671 IF rstn = '0' THEN -- asynchronous reset (active low)
672 fft_data_valid_pre <= '0';
673 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
674 fft_data_valid_pre <= fft_data_valid;
675 END IF;
676 END PROCESS;
677
678 PROCESS (clk, rstn)
650 679 BEGIN
651 680 IF rstn = '0' THEN
652 681 sample_valid_r <= '0';
653 682 select_fifo_reg <= (OTHERS => '0');
654 683 --next_state_fsm_load_FFT <= IDLE;
655 684 ELSIF clk'EVENT AND clk = '1' THEN
656 685 select_fifo_reg <= select_fifo;
657 686 --next_state_fsm_load_FFT <= state_fsm_load_FFT;
658 687 IF sample_ren_s = "11111" THEN
659 688 sample_valid_r <= '0';
660 689 ELSE
661 690 sample_valid_r <= '1';
662 691 END IF;
663 692 END IF;
664 693 END PROCESS;
665 694
666 695 sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
667 696
668 697 --sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
669 698 -- sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
670 699 -- sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
671 700 -- sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
672 701 -- sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
673 702 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN select_fifo_reg = "000" ELSE
674 703 sample_rdata(16*2-1 DOWNTO 16*1) WHEN select_fifo_reg = "001" ELSE
675 704 sample_rdata(16*3-1 DOWNTO 16*2) WHEN select_fifo_reg = "010" ELSE
676 705 sample_rdata(16*4-1 DOWNTO 16*3) WHEN select_fifo_reg = "011" ELSE
677 706 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
678 707
679 708 -----------------------------------------------------------------------------
680 709 -- FFT
681 710 -----------------------------------------------------------------------------
682 711 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
683 712 PORT MAP (
684 713 clk => clk,
685 714 rstn => rstn,
686 715 sample_valid => sample_valid,
687 716 fft_read => fft_read,
688 717 sample_data => sample_data,
689 718 sample_load => sample_load,
690 719 fft_pong => fft_pong,
691 720 fft_data_im => fft_data_im,
692 721 fft_data_re => fft_data_re,
693 722 fft_data_valid => fft_data_valid,
694 723 fft_ready => fft_ready);
695 724
696 725 debug_vector(0) <= fft_data_valid;
697 726 debug_vector(1) <= fft_ready;
698 727 debug_vector(11 DOWNTO 2) <= (OTHERS => '0');
699 728
700 729
701 730 -----------------------------------------------------------------------------
702 731 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
703 732 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
704 733
705 734 PROCESS (clk, rstn)
706 735 BEGIN
707 736 IF rstn = '0' THEN
708 737 fft_ready_reg <= '0';
709 738 sample_load_reg <= '0';
710 739
711 740 fft_ongoing_counter <= '0';
712 741 ELSIF clk'event AND clk = '1' THEN
713 742 fft_ready_reg <= fft_ready;
714 743 sample_load_reg <= sample_load;
715 744
716 745 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
717 746 fft_ongoing_counter <= '0';
718 747
719 748 -- CASE fft_ongoing_counter IS
720 749 -- WHEN "01" => fft_ongoing_counter <= "00";
721 750 ---- WHEN "10" => fft_ongoing_counter <= "01";
722 751 -- WHEN OTHERS => NULL;
723 752 -- END CASE;
724 753 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
725 754 fft_ongoing_counter <= '1';
726 755 -- CASE fft_ongoing_counter IS
727 756 -- WHEN "00" => fft_ongoing_counter <= "01";
728 757 ---- WHEN "01" => fft_ongoing_counter <= "10";
729 758 -- WHEN OTHERS => NULL;
730 759 -- END CASE;
731 760 END IF;
732 761
733 762 END IF;
734 763 END PROCESS;
735 764
736 765 -----------------------------------------------------------------------------
737 766 PROCESS (clk, rstn)
738 767 BEGIN
739 768 IF rstn = '0' THEN
740 769 state_fsm_load_MS_memory <= IDLE;
741 770 current_fifo_load <= "00001";
742 771 ELSIF clk'EVENT AND clk = '1' THEN
743 772 CASE state_fsm_load_MS_memory IS
744 773 WHEN IDLE =>
745 774 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
746 775 state_fsm_load_MS_memory <= LOAD_FIFO;
747 776 END IF;
748 777 WHEN LOAD_FIFO =>
749 778 IF current_fifo_full = '1' THEN
750 779 state_fsm_load_MS_memory <= TRASH_FFT;
751 780 END IF;
752 781 WHEN TRASH_FFT =>
753 782 IF fft_ready = '0' THEN
754 783 state_fsm_load_MS_memory <= IDLE;
755 784 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
756 785 END IF;
757 786 WHEN OTHERS => NULL;
758 787 END CASE;
759 788
760 789 END IF;
761 790 END PROCESS;
762 791
763 792 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
764 793 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
765 794 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
766 795 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
767 796 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
768 797
769 798 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
770 799 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
771 800 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
772 801 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
773 802 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
774 803
775 804 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
776 805 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
777 806 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
778 807 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
779 808 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
780 809
781 810 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
782 811
783 812 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
784 813 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
785 814 AND state_fsm_load_MS_memory = LOAD_FIFO
786 815 AND current_fifo_load(I) = '1'
787 816 ELSE '1';
788 817 END GENERATE all_fifo;
789 818
790 819 PROCESS (clk, rstn)
791 820 BEGIN
792 821 IF rstn = '0' THEN
793 822 MEM_IN_SM_wen <= (OTHERS => '1');
794 823 ELSIF clk'EVENT AND clk = '1' THEN
795 824 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
796 825 END IF;
797 826 END PROCESS;
798 827
799 828 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
800 829 (fft_data_im & fft_data_re) &
801 830 (fft_data_im & fft_data_re) &
802 831 (fft_data_im & fft_data_re) &
803 832 (fft_data_im & fft_data_re);
804 833 -----------------------------------------------------------------------------
805 834
806 835
807 836 -----------------------------------------------------------------------------
808 837 Mem_In_SpectralMatrix : lppFIFOxN
809 838 GENERIC MAP (
810 839 tech => 0,
811 840 Mem_use => Mem_use,
812 841 Data_sz => 32, --16,
813 842 Addr_sz => 7, --8
814 843 FifoCnt => 5)
815 844 PORT MAP (
816 845 clk => clk,
817 846 rstn => rstn,
818 847
819 848 ReUse => MEM_IN_SM_ReUse,
820 849 run => (OTHERS => '1'),
821 850
822 851 wen => MEM_IN_SM_wen,
823 852 wdata => MEM_IN_SM_wData,
824 853
825 854 ren => MEM_IN_SM_ren,
826 855 rdata => MEM_IN_SM_rData,
827 856 full => MEM_IN_SM_Full,
828 857 empty => MEM_IN_SM_Empty,
829 858 almost_full => OPEN);
830 859
831 860
832 861 -----------------------------------------------------------------------------
833 862 MS_control_1 : MS_control
834 863 PORT MAP (
835 864 clk => clk,
836 865 rstn => rstn,
837 866
838 867 current_status_ms => status_MS_input,
839 868
840 869 fifo_in_lock => MEM_IN_SM_locked,
841 870 fifo_in_data => MEM_IN_SM_rdata,
842 871 fifo_in_full => MEM_IN_SM_Full,
843 872 fifo_in_empty => MEM_IN_SM_Empty,
844 873 fifo_in_ren => MEM_IN_SM_ren,
845 874 fifo_in_reuse => MEM_IN_SM_ReUse,
846 875
847 876 fifo_out_data => SM_in_data,
848 877 fifo_out_ren => SM_in_ren,
849 878 fifo_out_empty => SM_in_empty,
850 879
851 880 current_status_component => status_component,
852 881
853 882 correlation_start => SM_correlation_start,
854 883 correlation_auto => SM_correlation_auto,
855 884 correlation_done => SM_correlation_done);
856 885
857 886
858 887 MS_calculation_1 : MS_calculation
859 888 PORT MAP (
860 889 clk => clk,
861 890 rstn => rstn,
862 891
863 892 fifo_in_data => SM_in_data,
864 893 fifo_in_ren => SM_in_ren,
865 894 fifo_in_empty => SM_in_empty,
866 895
867 896 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
868 897 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
869 898 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
870 899
871 900 correlation_start => SM_correlation_start,
872 901 correlation_auto => SM_correlation_auto,
873 902 correlation_begin => SM_correlation_begin,
874 903 correlation_done => SM_correlation_done);
875 904
876 905 -----------------------------------------------------------------------------
877 906 PROCESS (clk, rstn)
878 907 BEGIN -- PROCESS
879 908 IF rstn = '0' THEN -- asynchronous reset (active low)
880 909 current_matrix_write <= '0';
881 910 current_matrix_wait_empty <= '1';
882 911 status_component_fifo_0 <= (OTHERS => '0');
883 912 status_component_fifo_1 <= (OTHERS => '0');
884 913 status_component_fifo_0_end <= '0';
885 914 status_component_fifo_1_end <= '0';
886 915 SM_correlation_done_reg1 <= '0';
887 916 SM_correlation_done_reg2 <= '0';
888 917 SM_correlation_done_reg3 <= '0';
889 918
890 919 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
891 920 SM_correlation_done_reg1 <= SM_correlation_done;
892 921 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
893 922 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
894 923 status_component_fifo_0_end <= '0';
895 924 status_component_fifo_1_end <= '0';
896 925 IF SM_correlation_begin = '1' THEN
897 926 IF current_matrix_write = '0' THEN
898 927 status_component_fifo_0 <= status_component(53 DOWNTO 4);
899 928 ELSE
900 929 status_component_fifo_1 <= status_component(53 DOWNTO 4);
901 930 END IF;
902 931 END IF;
903 932
904 933 IF SM_correlation_done_reg3 = '1' THEN
905 934 IF current_matrix_write = '0' THEN
906 935 status_component_fifo_0_end <= '1';
907 936 ELSE
908 937 status_component_fifo_1_end <= '1';
909 938 END IF;
910 939 current_matrix_wait_empty <= '1';
911 940 current_matrix_write <= NOT current_matrix_write;
912 941 END IF;
913 942
914 943 IF current_matrix_wait_empty <= '1' THEN
915 944 IF current_matrix_write = '0' THEN
916 945 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
917 946 ELSE
918 947 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
919 948 END IF;
920 949 END IF;
921 950
922 951 END IF;
923 952 END PROCESS;
924 953
925 954 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
926 955 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
927 956 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
928 957 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
929 958 '1' WHEN current_matrix_wait_empty = '1' ELSE
930 959 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
931 960 MEM_OUT_SM_Full(1);
932 961
933 962 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
934 963 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
935 964
936 965 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
937 966 -----------------------------------------------------------------------------
938 967
939 968 --Mem_Out_SpectralMatrix : lppFIFOxN
940 969 -- GENERIC MAP (
941 970 -- tech => 0,
942 971 -- Mem_use => Mem_use,
943 972 -- Data_sz => 32,
944 973 -- Addr_sz => 8,
945 974 -- FifoCnt => 2)
946 975 -- PORT MAP (
947 976 -- clk => clk,
948 977 -- rstn => rstn,
949 978
950 979 -- ReUse => (OTHERS => '0'),
951 980 -- run => (OTHERS => '1'),
952 981
953 982 -- wen => MEM_OUT_SM_Write,
954 983 -- wdata => MEM_OUT_SM_Data_in,
955 984
956 985 -- ren => MEM_OUT_SM_Read,
957 986 -- rdata => MEM_OUT_SM_Data_out,
958 987
959 988 -- full => MEM_OUT_SM_Full,
960 989 -- empty => MEM_OUT_SM_Empty,
961 990 -- almost_full => OPEN);
962 991
963 992
964 993 all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE
965 994 Mem_Out_SpectralMatrix_I: lpp_fifo
966 995 GENERIC MAP (
967 996 tech => 0,
968 997 Mem_use => Mem_use,
969 998 EMPTY_THRESHOLD_LIMIT => 15,
970 999 FULL_THRESHOLD_LIMIT => 1,
971 1000 DataSz => 32,
972 1001 AddrSz => 8)
973 1002 PORT MAP (
974 1003 clk => clk,
975 1004 rstn => rstn,
976 1005 reUse => '0',
977 1006 run => run,
978 1007
979 1008 ren => MEM_OUT_SM_Read(I),
980 1009 rdata => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i),
981 1010
982 1011 wen => MEM_OUT_SM_Write(I),
983 1012 wdata => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i),
984 1013
985 1014 empty => MEM_OUT_SM_Empty(I),
986 1015 full => MEM_OUT_SM_Full(I),
987 1016 full_almost => OPEN,
988 1017 empty_threshold => MEM_OUT_SM_Empty_Threshold(I),
989 1018
990 1019 full_threshold => OPEN);
991 1020
992 1021 END GENERATE all_Mem_Out_SpectralMatrix;
993 1022
994 1023 -----------------------------------------------------------------------------
995 1024 -- MEM_OUT_SM_Read <= "00";
996 1025 PROCESS (clk, rstn)
997 1026 BEGIN
998 1027 IF rstn = '0' THEN
999 1028 fifo_0_ready <= '0';
1000 1029 fifo_1_ready <= '0';
1001 1030 fifo_ongoing <= '0';
1002 1031 fifo_ongoing_reg <= '0';
1003 1032 ELSIF clk'EVENT AND clk = '1' THEN
1004 1033 fifo_ongoing_reg <= fifo_ongoing;
1005 1034 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
1006 1035 fifo_ongoing <= '1';
1007 1036 fifo_0_ready <= '0';
1008 1037 ELSIF status_component_fifo_0_end = '1' THEN
1009 1038 fifo_0_ready <= '1';
1010 1039 END IF;
1011 1040
1012 1041 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
1013 1042 fifo_ongoing <= '0';
1014 1043 fifo_1_ready <= '0';
1015 1044 ELSIF status_component_fifo_1_end = '1' THEN
1016 1045 fifo_1_ready <= '1';
1017 1046 END IF;
1018 1047
1019 1048 END IF;
1020 1049 END PROCESS;
1021 1050
1022 1051 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
1023 1052 '1' WHEN fifo_0_ready = '0' ELSE
1024 1053 FSM_DMA_fifo_ren;
1025 1054
1026 1055 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
1027 1056 '1' WHEN fifo_1_ready = '0' ELSE
1028 1057 FSM_DMA_fifo_ren;
1029 1058
1030 1059 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
1031 1060 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
1032 1061 '1';
1033 1062
1034 1063 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
1035 1064 status_component_fifo_1;
1036 1065
1037 1066 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing_reg = '0' ELSE
1038 1067 MEM_OUT_SM_Data_out(63 DOWNTO 32);
1039 1068
1040 1069
1041 1070 FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
1042 1071 MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
1043 1072 '1';
1044 1073
1045 1074 -----------------------------------------------------------------------------
1046 1075 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --IN
1047 1076 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), --IN
1048 1077 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), --IN
1049 1078 -- fifo_data => FSM_DMA_fifo_data, --IN
1050 1079 -- fifo_empty => FSM_DMA_fifo_empty, --IN
1051 1080 -- fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, --IN
1052 1081 -- fifo_ren => FSM_DMA_fifo_ren, --OUT
1053 1082
1054 1083
1055 1084 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
1056 1085 PORT MAP (
1057 1086 clk => clk,
1058 1087 rstn => rstn,
1059 1088 run => run,
1060 1089
1061 1090 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1062 1091 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1063 1092 fifo_data => FSM_DMA_fifo_data,
1064 1093 fifo_empty => FSM_DMA_fifo_empty,
1065 1094 fifo_empty_threshold => FSM_DMA_fifo_empty_threshold,
1066 1095 fifo_ren => FSM_DMA_fifo_ren,
1067 1096
1068 1097 dma_fifo_valid_burst => dma_fifo_burst_valid,
1069 1098 dma_fifo_data => dma_fifo_data,
1070 1099 dma_fifo_ren => dma_fifo_ren,
1071 1100 dma_buffer_new => dma_buffer_new,
1072 1101 dma_buffer_addr => dma_buffer_addr,
1073 1102 dma_buffer_length => dma_buffer_length,
1074 1103 dma_buffer_full => dma_buffer_full,
1075 1104 dma_buffer_full_err => dma_buffer_full_err,
1076 1105
1077 1106 status_ready_matrix_f0 => status_ready_matrix_f0,
1078 1107 status_ready_matrix_f1 => status_ready_matrix_f1,
1079 1108 status_ready_matrix_f2 => status_ready_matrix_f2,
1080 1109 addr_matrix_f0 => addr_matrix_f0,
1081 1110 addr_matrix_f1 => addr_matrix_f1,
1082 1111 addr_matrix_f2 => addr_matrix_f2,
1083 1112 length_matrix_f0 => length_matrix_f0,
1084 1113 length_matrix_f1 => length_matrix_f1,
1085 1114 length_matrix_f2 => length_matrix_f2,
1086 1115 ready_matrix_f0 => ready_matrix_f0,
1087 1116 ready_matrix_f1 => ready_matrix_f1,
1088 1117 ready_matrix_f2 => ready_matrix_f2,
1089 1118 matrix_time_f0 => matrix_time_f0,
1090 1119 matrix_time_f1 => matrix_time_f1,
1091 1120 matrix_time_f2 => matrix_time_f2,
1092 1121 error_buffer_full => error_buffer_full);
1093 1122
1094 1123
1095 1124
1096 1125
1097 1126
1098 1127 --dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
1099 1128 --dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1100 1129 --dma_fifo_ren : IN STD_LOGIC; --TODO
1101 1130 --dma_buffer_new : OUT STD_LOGIC; --TODO
1102 1131 --dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1103 1132 --dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
1104 1133 --dma_buffer_full : IN STD_LOGIC; --TODO
1105 1134 --dma_buffer_full_err : IN STD_LOGIC; --TODO
1106 1135
1107 1136 ---- Reg out
1108 1137 --ready_matrix_f0 : OUT STD_LOGIC; -- TODO
1109 1138 --ready_matrix_f1 : OUT STD_LOGIC; -- TODO
1110 1139 --ready_matrix_f2 : OUT STD_LOGIC; -- TODO
1111 1140 --error_bad_component_error : OUT STD_LOGIC; -- TODO
1112 1141 --error_buffer_full : OUT STD_LOGIC; -- TODO
1113 1142
1114 1143 ---- Reg In
1115 1144 --status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
1116 1145 --status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
1117 1146 --status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
1118 1147
1119 1148 --addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1120 1149 --addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1121 1150 --addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1122 1151
1123 1152 --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1124 1153 --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1125 1154 --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO
1126 1155 -----------------------------------------------------------------------------
1127 1156
1128 1157 -----------------------------------------------------------------------------
1129 1158 --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
1130 1159 -- PORT MAP (
1131 1160 -- HCLK => clk,
1132 1161 -- HRESETn => rstn,
1133 1162
1134 1163 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1135 1164 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
1136 1165 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1137 1166 -- fifo_data => FSM_DMA_fifo_data,
1138 1167 -- fifo_empty => FSM_DMA_fifo_empty,
1139 1168 -- fifo_ren => FSM_DMA_fifo_ren,
1140 1169
1141 1170 -- dma_addr => dma_addr,
1142 1171 -- dma_data => dma_data,
1143 1172 -- dma_valid => dma_valid,
1144 1173 -- dma_valid_burst => dma_valid_burst,
1145 1174 -- dma_ren => dma_ren,
1146 1175 -- dma_done => dma_done,
1147 1176
1148 1177 -- ready_matrix_f0 => ready_matrix_f0,
1149 1178 -- ready_matrix_f1 => ready_matrix_f1,
1150 1179 -- ready_matrix_f2 => ready_matrix_f2,
1151 1180
1152 1181 -- error_bad_component_error => error_bad_component_error,
1153 1182 -- error_buffer_full => error_buffer_full,
1154 1183
1155 1184 -- debug_reg => debug_reg,
1156 1185 -- status_ready_matrix_f0 => status_ready_matrix_f0,
1157 1186 -- status_ready_matrix_f1 => status_ready_matrix_f1,
1158 1187 -- status_ready_matrix_f2 => status_ready_matrix_f2,
1159 1188
1160 1189 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
1161 1190 -- config_active_interruption_onError => config_active_interruption_onError,
1162 1191
1163 1192 -- addr_matrix_f0 => addr_matrix_f0,
1164 1193 -- addr_matrix_f1 => addr_matrix_f1,
1165 1194 -- addr_matrix_f2 => addr_matrix_f2,
1166 1195
1167 1196 -- matrix_time_f0 => matrix_time_f0,
1168 1197 -- matrix_time_f1 => matrix_time_f1,
1169 1198 -- matrix_time_f2 => matrix_time_f2
1170 1199 -- );
1171 1200 -----------------------------------------------------------------------------
1172 1201
1173 1202
1174 1203
1175 1204
1176 1205
1177 1206
1178 1207 -----------------------------------------------------------------------------
1179 1208 -- TIME MANAGMENT
1180 1209 -----------------------------------------------------------------------------
1181 1210 all_time <= sample_f2_time & sample_f1_time & sample_f0_time & sample_f0_time;
1182 1211 --all_time <= coarse_time & fine_time;
1183 1212 --
1184 1213 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
1185 1214 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
1186 1215 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
1187 1216 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
1188 1217
1189 1218 all_time_reg: FOR I IN 0 TO 3 GENERATE
1190 1219
1191 1220 PROCESS (clk, rstn)
1192 1221 BEGIN
1193 1222 IF rstn = '0' THEN
1194 1223 f_empty_reg(I) <= '1';
1195 1224 ELSIF clk'event AND clk = '1' THEN
1196 1225 f_empty_reg(I) <= f_empty(I);
1197 1226 END IF;
1198 1227 END PROCESS;
1199 1228
1200 1229 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
1201 1230
1202 1231 s_m_t_m_f0_A : spectral_matrix_time_managment
1203 1232 PORT MAP (
1204 1233 clk => clk,
1205 1234 rstn => rstn,
1206 1235 time_in => all_time((I+1)*48-1 DOWNTO I*48),
1207 1236 update_1 => time_update_f(I),
1208 1237 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1209 1238 );
1210 1239
1211 1240 END GENERATE all_time_reg;
1212 1241
1213 1242 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
1214 1243 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
1215 1244 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
1216 1245 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
1217 1246
1218 1247 -----------------------------------------------------------------------------
1219 1248
1220 1249 END Behavioral;
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