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add LFR-EQM's files for RTAX
pellion -
r612:f5ec87dbbcce simu_with_Leon3
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Thu Jun 04 11:49:44 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
28
29
30 ######## Generated Clock Constraints ########
31
32
33
34 ######## Clock Source Latency Constraints #########
35
36
37
38 ######## Input Delay Constraints ########
39
40 set_input_delay -max 35.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
41
42 set_input_delay -max 35.000 -clock { clk_25:Q } [get_ports { ADC_data }]
43
44
45
46 ######## Output Delay Constraints ########
47
48 set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
49 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
50 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
51 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
52
53 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
54 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
55 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
56 address[7] address[8] address[9] }]
57
58 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W nSRAM_G nSRAM_MBE}]
59
60 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH ADC_OEB_bar_HK }]
61
62 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { DAC_SCK DAC_SDO DAC_SYNC }]
63
64
65 ######## Delay Constraints ########
66
67 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
68 [get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}]
69
70 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
71 [get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}]
72
73
74 ######## Delay Constraints ########
75
76
77
78 ######## Multicycle Constraints ########
79
80
81
82 ######## False Path Constraints ########
83
84
85
86 ######## Output load Constraints ########
87
88
89
90 ######## Disable Timing Constraints #########
91
92
93
94 ######## Clock Uncertainty Constraints #########
95
96
97
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Thu Jun 04 11:49:44 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_1_0:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_1_0:Y }
28
29
30 ######## Generated Clock Constraints ########
31
32
33
34 ######## Clock Source Latency Constraints #########
35
36
37
38 ######## Input Delay Constraints ########
39
40 set_input_delay -max 35.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
41
42 set_input_delay -max 35.000 -clock { clk_25:Q } [get_ports { ADC_data }]
43
44
45
46 ######## Output Delay Constraints ########
47
48 set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
49 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
50 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
51 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
52
53 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
54 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
55 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
56 address[7] address[8] address[9] }]
57
58 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W nSRAM_G nSRAM_MBE}]
59
60 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH ADC_OEB_bar_HK }]
61
62 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { DAC_SCK DAC_SDO DAC_SYNC }]
63
64
65 ######## Delay Constraints ########
66
67 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
68 [get_clocks {spw_inputloop.0.spw_phy0/rxclki_1_0:Y}]
69
70 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
71 [get_clocks {spw_inputloop.1.spw_phy0/rxclki_1_0:Y}]
72
73
74 ######## Delay Constraints ########
75
76
77
78 ######## Multicycle Constraints ########
79
80
81
82 ######## False Path Constraints ########
83
84
85
86 ######## Output load Constraints ########
87
88
89
90 ######## Disable Timing Constraints #########
91
92
93
94 ######## Clock Uncertainty Constraints #########
95
96
97
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Thu Jun 04 11:49:44 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
19 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
20 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
21 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_1_0:Y }
22 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_1_0:Y }
23
24
25
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1 # Synopsys, Inc. constraint file
2 # E:\opt\tortoiseHG_vhdlib\boards\LFR-EQM\LFR_EQM_altran_syn.sdc
3 # Written on Fri Jun 12 10:24:30 2015
4 # by Synplify Pro, E-2010.09A-1 Scope Editor
5
6 #
7 # Collections
8 #
9
10 #
11 # Clocks
12 #
13 define_clock {clk50MHz} -freq 50 -clockgroup default_clkgroup_0
14 define_clock {n:clk_25} -freq 25 -clockgroup default_clkgroup_1
15 define_clock {n:clk_24} -freq 24.576 -clockgroup default_clkgroup_2
16 define_clock {n:spw_inputloop\.0\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_3
17 define_clock {n:spw_inputloop\.1\.spw_phy0.rxclki_1} -freq 10 -clockgroup default_clkgroup_4
18 define_clock {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup_5
19
20 #
21 # Clock to Clock
22 #
23
24 #
25 # Inputs/Outputs
26 #
27
28 #
29 # Registers
30 #
31
32 #
33 # Delay Paths
34 #
35
36 #
37 # Attributes
38 #
39
40 #
41 # I/O Standards
42 #
43
44
45 #
46 # Compile Points
47 #
48
49 #
50 # Other
51 # No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.sim.ALL;
32 USE gaisler.memctrl.ALL;
33 USE gaisler.leon3.ALL;
34 USE gaisler.uart.ALL;
35 USE gaisler.misc.ALL;
36 USE gaisler.spacewire.ALL;
37 LIBRARY esa;
38 USE esa.memoryctrl.ALL;
39 LIBRARY lpp;
40 USE lpp.lpp_memory.ALL;
41 USE lpp.lpp_ad_conv.ALL;
42 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
43 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
44 USE lpp.iir_filter.ALL;
45 USE lpp.general_purpose.ALL;
46 USE lpp.lpp_lfr_management.ALL;
47 USE lpp.lpp_leon3_soc_pkg.ALL;
48
49 --library proasic3l;
50 --use proasic3l.all;
51
52 ENTITY LFR_EQM IS
53 GENERIC (
54 Mem_use : INTEGER := use_RAM;
55 USE_BOOTLOADER : INTEGER := 0;
56 USE_ADCDRIVER : INTEGER := 1;
57 tech : INTEGER := inferred;
58 tech_leon : INTEGER := inferred;
59 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
60 USE_DEBUG_VECTOR : INTEGER := 0
61 );
62
63 PORT (
64 clk50MHz : IN STD_ULOGIC;
65 clk49_152MHz : IN STD_ULOGIC;
66 reset : IN STD_ULOGIC;
67
68 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
69
70 -- TAG --------------------------------------------------------------------
71 --TAG1 : IN STD_ULOGIC; -- DSU rx data
72 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
73 -- UART APB ---------------------------------------------------------------
74 --TAG2 : IN STD_ULOGIC; -- UART1 rx data
75 --TAG4 : OUT STD_ULOGIC; -- UART1 tx data
76 -- RAM --------------------------------------------------------------------
77 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
78 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79
80 nSRAM_MBE : INOUT STD_LOGIC; -- new
81 nSRAM_E1 : OUT STD_LOGIC; -- new
82 nSRAM_E2 : OUT STD_LOGIC; -- new
83 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
84 nSRAM_W : OUT STD_LOGIC; -- new
85 nSRAM_G : OUT STD_LOGIC; -- new
86 nSRAM_BUSY : IN STD_LOGIC; -- new
87 -- SPW --------------------------------------------------------------------
88 spw1_en : OUT STD_LOGIC; -- new
89 spw1_din : IN STD_LOGIC;
90 spw1_sin : IN STD_LOGIC;
91 spw1_dout : OUT STD_LOGIC;
92 spw1_sout : OUT STD_LOGIC;
93 spw2_en : OUT STD_LOGIC; -- new
94 spw2_din : IN STD_LOGIC;
95 spw2_sin : IN STD_LOGIC;
96 spw2_dout : OUT STD_LOGIC;
97 spw2_sout : OUT STD_LOGIC;
98 -- ADC --------------------------------------------------------------------
99 bias_fail_sw : OUT STD_LOGIC;
100 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_smpclk : OUT STD_LOGIC;
102 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
103 -- DAC --------------------------------------------------------------------
104 DAC_SDO : OUT STD_LOGIC;
105 DAC_SCK : OUT STD_LOGIC;
106 DAC_SYNC : OUT STD_LOGIC;
107 DAC_CAL_EN : OUT STD_LOGIC;
108 -- HK ---------------------------------------------------------------------
109 HK_smpclk : OUT STD_LOGIC;
110 ADC_OEB_bar_HK : OUT STD_LOGIC;
111 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--;
112 ---------------------------------------------------------------------------
113 -- TAG8 : OUT STD_LOGIC
114 );
115
116 END LFR_EQM;
117
118
119 ARCHITECTURE beh OF LFR_EQM IS
120
121 SIGNAL clk_25 : STD_LOGIC := '0';
122 SIGNAL clk_24 : STD_LOGIC := '0';
123 -----------------------------------------------------------------------------
124 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
125 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
126
127 -- CONSTANTS
128 CONSTANT CFG_PADTECH : INTEGER := inferred;
129 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
130 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
131 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
132
133 SIGNAL apbi_ext : apb_slv_in_type;
134 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
135 SIGNAL ahbi_s_ext : ahb_slv_in_type;
136 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
137 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
138 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
139
140 -- Spacewire signals
141 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
142 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
143 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
144 SIGNAL swni : grspw_in_type;
145 SIGNAL swno : grspw_out_type;
146
147 --GPIO
148 SIGNAL gpioi : gpio_in_type;
149 SIGNAL gpioo : gpio_out_type;
150
151 -- AD Converter ADS7886
152 SIGNAL sample : Samples14v(8 DOWNTO 0);
153 SIGNAL sample_s : Samples(8 DOWNTO 0);
154 SIGNAL sample_val : STD_LOGIC;
155 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
156
157 -----------------------------------------------------------------------------
158 SIGNAL rstn_25 : STD_LOGIC;
159 SIGNAL rstn_24 : STD_LOGIC;
160
161 SIGNAL LFR_soft_rstn : STD_LOGIC;
162 SIGNAL LFR_rstn : STD_LOGIC;
163
164 SIGNAL ADC_smpclk_s : STD_LOGIC;
165
166 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
167
168 SIGNAL clk50MHz_int : STD_LOGIC := '0';
169
170 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
171
172 SIGNAL rstn_50 : STD_LOGIC;
173 SIGNAL clk_lock : STD_LOGIC;
174 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
175 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
176
177 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
178 SIGNAL ahbrxd: STD_LOGIC;
179 SIGNAL ahbtxd: STD_LOGIC;
180 SIGNAL urxd1 : STD_LOGIC;
181 SIGNAL utxd1 : STD_LOGIC;
182 BEGIN -- beh
183
184 -----------------------------------------------------------------------------
185 -- CLK_LOCK
186 -----------------------------------------------------------------------------
187 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
188
189 PROCESS (clk50MHz_int, rstn_50)
190 BEGIN -- PROCESS
191 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
192 clk_lock <= '0';
193 clk_busy_counter <= (OTHERS => '0');
194 nSRAM_BUSY_reg <= '0';
195 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
196 nSRAM_BUSY_reg <= nSRAM_BUSY;
197 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
198 IF clk_busy_counter = "1111" THEN
199 clk_lock <= '1';
200 ELSE
201 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
202 END IF;
203 END IF;
204 END IF;
205 END PROCESS;
206
207 -----------------------------------------------------------------------------
208 -- CLK
209 -----------------------------------------------------------------------------
210 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
211 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
212
213 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
214 clk50MHz_int <= clk50MHz;
215
216 PROCESS(clk50MHz_int)
217 BEGIN
218 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
219 --clk_25_int <= NOT clk_25_int;
220 clk_25 <= NOT clk_25;
221 END IF;
222 END PROCESS;
223 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
224
225 PROCESS(clk49_152MHz)
226 BEGIN
227 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
228 clk_24 <= NOT clk_24;
229 END IF;
230 END PROCESS;
231 -- clk_49 <= clk49_152MHz;
232
233 -----------------------------------------------------------------------------
234 --
235 leon3_soc_1 : leon3_soc
236 GENERIC MAP (
237 fabtech => axcel,--inferred,--axdsp,
238 memtech => axcel,--inferred,--tech_leon,
239 padtech => axcel,--inferred,
240 clktech => axcel,--inferred,
241 disas => 0,
242 dbguart => 0,
243 pclow => 2,
244 clk_freq => 25000,
245 IS_RADHARD => 1,
246 NB_CPU => 1,
247 ENABLE_FPU => 1,
248 FPU_NETLIST => 1,
249 ENABLE_DSU => 1,
250 ENABLE_AHB_UART => 1,
251 ENABLE_APB_UART => 1,
252 ENABLE_IRQMP => 1,
253 ENABLE_GPT => 1,
254 NB_AHB_MASTER => NB_AHB_MASTER,
255 NB_AHB_SLAVE => NB_AHB_SLAVE,
256 NB_APB_SLAVE => NB_APB_SLAVE,
257 ADDRESS_SIZE => 19,
258 USES_IAP_MEMCTRLR => 1,
259 BYPASS_EDAC_MEMCTRLR => '0',
260 SRBANKSZ => 8)
261 PORT MAP (
262 clk => clk_25,
263 reset => rstn_25,
264 errorn => OPEN,
265
266 ahbrxd => ahbrxd, -- INPUT
267 ahbtxd => ahbtxd, -- OUTPUT
268 urxd1 => urxd1, -- INPUT
269 utxd1 => utxd1, -- OUTPUT
270
271 address => address,
272 data => data,
273 nSRAM_BE0 => OPEN,
274 nSRAM_BE1 => OPEN,
275 nSRAM_BE2 => OPEN,
276 nSRAM_BE3 => OPEN,
277 nSRAM_WE => nSRAM_W,
278 nSRAM_CE => nSRAM_CE,
279 nSRAM_OE => nSRAM_G,
280 nSRAM_READY => nSRAM_BUSY,
281 SRAM_MBE => nSRAM_MBE,
282
283 apbi_ext => apbi_ext,
284 apbo_ext => apbo_ext,
285 ahbi_s_ext => ahbi_s_ext,
286 ahbo_s_ext => ahbo_s_ext,
287 ahbi_m_ext => ahbi_m_ext,
288 ahbo_m_ext => ahbo_m_ext);
289
290
291 nSRAM_E1 <= nSRAM_CE(0);
292 nSRAM_E2 <= nSRAM_CE(1);
293
294 -------------------------------------------------------------------------------
295 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
296 -------------------------------------------------------------------------------
297 apb_lfr_management_1 : apb_lfr_management
298 GENERIC MAP (
299 tech => tech,
300 pindex => 6,
301 paddr => 6,
302 pmask => 16#fff#,
303 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
304 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
305 PORT MAP (
306 clk25MHz => clk_25,
307 resetn_25MHz => rstn_25, -- TODO
308 --clk24_576MHz => clk_24, -- 49.152MHz/2
309 --resetn_24_576MHz => rstn_24, -- TODO
310
311 grspw_tick => swno.tickout,
312 apbi => apbi_ext,
313 apbo => apbo_ext(6),
314
315 HK_sample => sample_s(8),
316 HK_val => sample_val,
317 HK_sel => HK_SEL,
318
319 DAC_SDO => DAC_SDO,
320 DAC_SCK => DAC_SCK,
321 DAC_SYNC => DAC_SYNC,
322 DAC_CAL_EN => DAC_CAL_EN,
323
324 coarse_time => coarse_time,
325 fine_time => fine_time,
326 LFR_soft_rstn => LFR_soft_rstn
327 );
328
329 -----------------------------------------------------------------------
330 --- SpaceWire --------------------------------------------------------
331 -----------------------------------------------------------------------
332
333 ------------------------------------------------------------------------------
334 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
335 ------------------------------------------------------------------------------
336 spw1_en <= '1';
337 spw2_en <= '1';
338 ------------------------------------------------------------------------------
339 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
340 ------------------------------------------------------------------------------
341
342 --spw_clk <= clk50MHz;
343 --spw_rxtxclk <= spw_clk;
344 --spw_rxclkn <= NOT spw_rxtxclk;
345
346 -- PADS for SPW1
347 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
348 PORT MAP (spw1_din, dtmp(0));
349 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
350 PORT MAP (spw1_sin, stmp(0));
351 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
352 PORT MAP (spw1_dout, swno.d(0));
353 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
354 PORT MAP (spw1_sout, swno.s(0));
355 -- PADS FOR SPW2
356 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
357 PORT MAP (spw2_din, dtmp(1));
358 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
359 PORT MAP (spw2_sin, stmp(1));
360 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
361 PORT MAP (spw2_dout, swno.d(1));
362 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
363 PORT MAP (spw2_sout, swno.s(1));
364
365 -- GRSPW PHY
366 --spw1_input: if CFG_SPW_GRSPW = 1 generate
367 spw_inputloop : FOR j IN 0 TO 1 GENERATE
368 spw_phy0 : grspw_phy
369 GENERIC MAP(
370 tech => axcel,-- inferred,--axdsp,--tech_leon,
371 rxclkbuftype => 1,
372 scantest => 0)
373 PORT MAP(
374 rxrst => swno.rxrst,
375 di => dtmp(j),
376 si => stmp(j),
377 rxclko => spw_rxclk(j),
378 do => swni.d(j),
379 ndo => swni.nd(j*5+4 DOWNTO j*5),
380 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
381 END GENERATE spw_inputloop;
382
383 -- SPW core
384 sw0 : grspwm GENERIC MAP(
385 tech => axcel,--inferred,--axdsp,--tech_leon,
386 hindex => 1,
387 pindex => 5,
388 paddr => 5,
389 pirq => 11,
390 sysfreq => 25000, -- CPU_FREQ
391 rmap => 1,
392 rmapcrc => 1,
393 fifosize1 => 16,
394 fifosize2 => 16,
395 rxclkbuftype => 1,
396 rxunaligned => 0,
397 rmapbufs => 4,
398 ft => 1,
399 netlist => 0,
400 ports => 2,
401 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
402 memtech => axcel,--inferred,--tech_leon,
403 destkey => 2,
404 spwcore => 1
405 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
406 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
407 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
408 )
409 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
410 spw_rxclk(1),
411 clk50MHz_int,
412 clk50MHz_int,
413 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
414 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
415 swni, swno);
416
417 swni.tickin <= '0';
418 swni.rmapen <= '1';
419 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
420 swni.tickinraw <= '0';
421 swni.timein <= (OTHERS => '0');
422 swni.dcrstval <= (OTHERS => '0');
423 swni.timerrstval <= (OTHERS => '0');
424
425 -------------------------------------------------------------------------------
426 -- LFR ------------------------------------------------------------------------
427 -------------------------------------------------------------------------------
428 --rst_domain25_lfr : rstgen PORT MAP (LFR_soft_rstn, clk_25, clk_lock, LFR_rstn, OPEN);
429 LFR_rstn <= LFR_soft_rstn AND rstn_25;
430
431 lpp_lfr_1 : lpp_lfr
432 GENERIC MAP (
433 Mem_use => Mem_use,
434 tech => inferred,--tech,
435 nb_data_by_buffer_size => 32,
436 --nb_word_by_buffer_size => 30,
437 nb_snapshot_param_size => 32,
438 delta_vector_size => 32,
439 delta_vector_size_f0_2 => 7, -- log2(96)
440 pindex => 15,
441 paddr => 15,
442 pmask => 16#fff#,
443 pirq_ms => 6,
444 pirq_wfp => 14,
445 hindex => 2,
446 top_lfr_version => X"020153", -- aa.bb.cc version
447 -- AA : BOARD NUMBER
448 -- 0 => MINI_LFR
449 -- 1 => EM
450 -- 2 => EQM (with A3PE3000)
451 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA)
452 PORT MAP (
453 clk => clk_25,
454 rstn => LFR_rstn,
455 sample_B => sample_s(2 DOWNTO 0),
456 sample_E => sample_s(7 DOWNTO 3),
457 sample_val => sample_val,
458 apbi => apbi_ext,
459 apbo => apbo_ext(15),
460 ahbi => ahbi_m_ext,
461 ahbo => ahbo_m_ext(2),
462 coarse_time => coarse_time,
463 fine_time => fine_time,
464 data_shaping_BW => bias_fail_sw,
465 debug_vector => debug_vector,
466 debug_vector_ms => OPEN); --,
467 --observation_vector_0 => OPEN,
468 --observation_vector_1 => OPEN,
469 --observation_reg => observation_reg);
470
471
472 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
473 sample_s(I) <= sample(I) & '0' & '0';
474 END GENERATE all_sample;
475 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
476
477 -----------------------------------------------------------------------------
478 --
479 -----------------------------------------------------------------------------
480 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
481 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
482 GENERIC MAP (
483 ChanelCount => 9,
484 ncycle_cnv_high => 12,
485 ncycle_cnv => 25,
486 FILTER_ENABLED => 16#FF#)
487 PORT MAP (
488 cnv_clk => clk_24,
489 cnv_rstn => rstn_24,
490 cnv => ADC_smpclk_s,
491 clk => clk_25,
492 rstn => rstn_25,
493 ADC_data => ADC_data,
494 ADC_nOE => ADC_OEB_bar_CH_s,
495 sample => sample,
496 sample_val => sample_val);
497
498 END GENERATE USE_ADCDRIVER_true;
499
500 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
501 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
502 GENERIC MAP (
503 ChanelCount => 9,
504 ncycle_cnv_high => 25,
505 ncycle_cnv => 50,
506 FILTER_ENABLED => 16#FF#)
507 PORT MAP (
508 cnv_clk => clk_24,
509 cnv_rstn => rstn_24,
510 cnv => ADC_smpclk_s,
511 clk => clk_25,
512 rstn => rstn_25,
513 ADC_data => ADC_data,
514 ADC_nOE => OPEN,
515 sample => OPEN,
516 sample_val => sample_val);
517
518 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
519
520 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
521 ramp_generator_1: ramp_generator
522 GENERIC MAP (
523 DATA_SIZE => 14,
524 VALUE_UNSIGNED_INIT => 2**I,
525 VALUE_UNSIGNED_INCR => 0,
526 VALUE_UNSIGNED_MASK => 16#3FFF#)
527 PORT MAP (
528 clk => clk_25,
529 rstn => rstn_25,
530 new_data => sample_val,
531 output_data => sample(I) );
532 END GENERATE all_sample;
533
534
535 END GENERATE USE_ADCDRIVER_false;
536
537
538
539
540 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
541
542 ADC_smpclk <= ADC_smpclk_s;
543 HK_smpclk <= ADC_smpclk_s;
544
545
546 -----------------------------------------------------------------------------
547 -- HK
548 -----------------------------------------------------------------------------
549 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
550
551 -----------------------------------------------------------------------------
552 --
553 -----------------------------------------------------------------------------
554 --inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
555 -- lpp_bootloader_1: lpp_bootloader
556 -- GENERIC MAP (
557 -- pindex => 13,
558 -- paddr => 13,
559 -- pmask => 16#fff#,
560 -- hindex => 3,
561 -- haddr => 0,
562 -- hmask => 16#fff#)
563 -- PORT MAP (
564 -- HCLK => clk_25,
565 -- HRESETn => rstn_25,
566 -- apbi => apbi_ext,
567 -- apbo => apbo_ext(13),
568 -- ahbsi => ahbi_s_ext,
569 -- ahbso => ahbo_s_ext(3));
570 --END GENERATE inst_bootloader;
571
572 -----------------------------------------------------------------------------
573 --
574 -----------------------------------------------------------------------------
575 USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
576 PROCESS (clk_25, rstn_25)
577 BEGIN -- PROCESS
578 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
579 TAG <= (OTHERS => '0');
580 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
581 TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
582 END IF;
583 END PROCESS;
584
585
586 END GENERATE USE_DEBUG_VECTOR_IF;
587
588 USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
589 ahbrxd <= TAG(1);
590 TAG(3) <= ahbtxd;
591 urxd1 <= TAG(2);
592 TAG(4) <= utxd1;
593 TAG(8) <= nSRAM_BUSY;
594 END GENERATE USE_DEBUG_VECTOR_IF2;
595
596 END beh;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.sim.ALL;
32 USE gaisler.memctrl.ALL;
33 USE gaisler.leon3.ALL;
34 USE gaisler.uart.ALL;
35 USE gaisler.misc.ALL;
36 USE gaisler.spacewire.ALL;
37 LIBRARY esa;
38 USE esa.memoryctrl.ALL;
39 LIBRARY lpp;
40 USE lpp.lpp_memory.ALL;
41 USE lpp.lpp_ad_conv.ALL;
42 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
43 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
44 USE lpp.iir_filter.ALL;
45 USE lpp.general_purpose.ALL;
46 USE lpp.lpp_lfr_management.ALL;
47 USE lpp.lpp_leon3_soc_pkg.ALL;
48
49 --library proasic3l;
50 --use proasic3l.all;
51
52 ENTITY LFR_soc_subsystem IS
53 GENERIC (
54 Mem_use : INTEGER := use_RAM;
55 USE_BOOTLOADER : INTEGER := 0;
56 USE_ADCDRIVER : INTEGER := 1;
57 tech : INTEGER := inferred;
58 tech_leon : INTEGER := inferred;
59 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
60 USE_DEBUG_VECTOR : INTEGER := 0
61 );
62
63 PORT (
64 clk50MHz : IN STD_ULOGIC;
65 clk49_152MHz : IN STD_ULOGIC;
66 reset : IN STD_ULOGIC;
67
68 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
69
70 -- TAG --------------------------------------------------------------------
71 --TAG1 : IN STD_ULOGIC; -- DSU rx data
72 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
73 -- UART APB ---------------------------------------------------------------
74 --TAG2 : IN STD_ULOGIC; -- UART1 rx data
75 --TAG4 : OUT STD_ULOGIC; -- UART1 tx data
76 -- RAM --------------------------------------------------------------------
77 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
78 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79
80 nSRAM_MBE : INOUT STD_LOGIC; -- new
81 nSRAM_E1 : OUT STD_LOGIC; -- new
82 nSRAM_E2 : OUT STD_LOGIC; -- new
83 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
84 nSRAM_W : OUT STD_LOGIC; -- new
85 nSRAM_G : OUT STD_LOGIC; -- new
86 nSRAM_BUSY : IN STD_LOGIC; -- new
87 -- SPW --------------------------------------------------------------------
88 spw1_en : OUT STD_LOGIC; -- new
89 spw1_din : IN STD_LOGIC;
90 spw1_sin : IN STD_LOGIC;
91 spw1_dout : OUT STD_LOGIC;
92 spw1_sout : OUT STD_LOGIC;
93 spw2_en : OUT STD_LOGIC; -- new
94 spw2_din : IN STD_LOGIC;
95 spw2_sin : IN STD_LOGIC;
96 spw2_dout : OUT STD_LOGIC;
97 spw2_sout : OUT STD_LOGIC;
98 -- ADC --------------------------------------------------------------------
99 bias_fail_sw : OUT STD_LOGIC;
100 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_smpclk : OUT STD_LOGIC;
102 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
103 -- DAC --------------------------------------------------------------------
104 DAC_SDO : OUT STD_LOGIC;
105 DAC_SCK : OUT STD_LOGIC;
106 DAC_SYNC : OUT STD_LOGIC;
107 DAC_CAL_EN : OUT STD_LOGIC;
108 -- HK ---------------------------------------------------------------------
109 HK_smpclk : OUT STD_LOGIC;
110 ADC_OEB_bar_HK : OUT STD_LOGIC;
111 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--;
112 ---------------------------------------------------------------------------
113 -- TAG8 : OUT STD_LOGIC
114 );
115
116 END LFR_soc_subsystem;
117
118
119 ARCHITECTURE beh OF LFR_soc_subsystem IS
120
121 SIGNAL clk_25 : STD_LOGIC := '0';
122 SIGNAL clk_24 : STD_LOGIC := '0';
123 -----------------------------------------------------------------------------
124 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
125 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
126
127 -- CONSTANTS
128 CONSTANT CFG_PADTECH : INTEGER := inferred;
129 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
130 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
131 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
132
133 SIGNAL apbi_ext : apb_slv_in_type;
134 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
135 SIGNAL ahbi_s_ext : ahb_slv_in_type;
136 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
137 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
138 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
139
140 -- Spacewire signals
141 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
142 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
143 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
144 SIGNAL swni : grspw_in_type;
145 SIGNAL swno : grspw_out_type;
146
147 --GPIO
148 SIGNAL gpioi : gpio_in_type;
149 SIGNAL gpioo : gpio_out_type;
150
151 -- AD Converter ADS7886
152 SIGNAL sample : Samples14v(8 DOWNTO 0);
153 SIGNAL sample_s : Samples(8 DOWNTO 0);
154 SIGNAL sample_val : STD_LOGIC;
155 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
156
157 -----------------------------------------------------------------------------
158 SIGNAL rstn_25 : STD_LOGIC;
159 SIGNAL rstn_24 : STD_LOGIC;
160
161 SIGNAL LFR_soft_rstn : STD_LOGIC;
162 SIGNAL LFR_rstn : STD_LOGIC;
163
164 SIGNAL ADC_smpclk_s : STD_LOGIC;
165
166 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
167
168 SIGNAL clk50MHz_int : STD_LOGIC := '0';
169
170 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
171
172 SIGNAL rstn_50 : STD_LOGIC;
173 SIGNAL clk_lock : STD_LOGIC;
174 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
175 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
176
177 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
178 SIGNAL ahbrxd: STD_LOGIC;
179 SIGNAL ahbtxd: STD_LOGIC;
180 SIGNAL urxd1 : STD_LOGIC;
181 SIGNAL utxd1 : STD_LOGIC;
182 BEGIN -- beh
183
184 -----------------------------------------------------------------------------
185 -- CLK_LOCK
186 -----------------------------------------------------------------------------
187 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
188
189 PROCESS (clk50MHz_int, rstn_50)
190 BEGIN -- PROCESS
191 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
192 clk_lock <= '0';
193 clk_busy_counter <= (OTHERS => '0');
194 nSRAM_BUSY_reg <= '0';
195 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
196 nSRAM_BUSY_reg <= nSRAM_BUSY;
197 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
198 IF clk_busy_counter = "1111" THEN
199 clk_lock <= '1';
200 ELSE
201 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
202 END IF;
203 END IF;
204 END IF;
205 END PROCESS;
206
207 -----------------------------------------------------------------------------
208 -- CLK
209 -----------------------------------------------------------------------------
210 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
211 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
212
213 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
214 clk50MHz_int <= clk50MHz;
215
216 PROCESS(clk50MHz_int)
217 BEGIN
218 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
219 --clk_25_int <= NOT clk_25_int;
220 clk_25 <= NOT clk_25;
221 END IF;
222 END PROCESS;
223 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
224
225 PROCESS(clk49_152MHz)
226 BEGIN
227 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
228 clk_24 <= NOT clk_24;
229 END IF;
230 END PROCESS;
231 -- clk_49 <= clk49_152MHz;
232
233 -----------------------------------------------------------------------------
234 --
235 leon3_soc_1 : leon3_soc
236 GENERIC MAP (
237 fabtech => axcel,--inferred,--axdsp,
238 memtech => axcel,--inferred,--tech_leon,
239 padtech => axcel,--inferred,
240 clktech => axcel,--inferred,
241 disas => 0,
242 dbguart => 0,
243 pclow => 2,
244 clk_freq => 25000,
245 IS_RADHARD => 1,
246 NB_CPU => 1,
247 ENABLE_FPU => 1,
248 FPU_NETLIST => 1,
249 ENABLE_DSU => 1,
250 ENABLE_AHB_UART => 1,
251 ENABLE_APB_UART => 1,
252 ENABLE_IRQMP => 1,
253 ENABLE_GPT => 1,
254 NB_AHB_MASTER => NB_AHB_MASTER,
255 NB_AHB_SLAVE => NB_AHB_SLAVE,
256 NB_APB_SLAVE => NB_APB_SLAVE,
257 ADDRESS_SIZE => 19,
258 USES_IAP_MEMCTRLR => 1,
259 BYPASS_EDAC_MEMCTRLR => '0',
260 SRBANKSZ => 8)
261 PORT MAP (
262 clk => clk_25,
263 reset => rstn_25,
264 errorn => OPEN,
265
266 ahbrxd => ahbrxd, -- INPUT
267 ahbtxd => ahbtxd, -- OUTPUT
268 urxd1 => urxd1, -- INPUT
269 utxd1 => utxd1, -- OUTPUT
270
271 address => address,
272 data => data,
273 nSRAM_BE0 => OPEN,
274 nSRAM_BE1 => OPEN,
275 nSRAM_BE2 => OPEN,
276 nSRAM_BE3 => OPEN,
277 nSRAM_WE => nSRAM_W,
278 nSRAM_CE => nSRAM_CE,
279 nSRAM_OE => nSRAM_G,
280 nSRAM_READY => nSRAM_BUSY,
281 SRAM_MBE => nSRAM_MBE,
282
283 apbi_ext => apbi_ext,
284 apbo_ext => apbo_ext,
285 ahbi_s_ext => ahbi_s_ext,
286 ahbo_s_ext => ahbo_s_ext,
287 ahbi_m_ext => ahbi_m_ext,
288 ahbo_m_ext => ahbo_m_ext);
289
290
291 nSRAM_E1 <= nSRAM_CE(0);
292 nSRAM_E2 <= nSRAM_CE(1);
293
294 -------------------------------------------------------------------------------
295 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
296 -------------------------------------------------------------------------------
297 apb_lfr_management_1 : apb_lfr_management_nocal
298 GENERIC MAP (
299 tech => tech,
300 pindex => 6,
301 paddr => 6,
302 pmask => 16#fff#,
303 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
304 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
305 PORT MAP (
306 clk25MHz => clk_25,
307 resetn_25MHz => rstn_25, -- TODO
308 --clk24_576MHz => clk_24, -- 49.152MHz/2
309 --resetn_24_576MHz => rstn_24, -- TODO
310
311 grspw_tick => swno.tickout,
312 apbi => apbi_ext,
313 apbo => apbo_ext(6),
314
315 HK_sample => sample_s(8),
316 HK_val => sample_val,
317 HK_sel => HK_SEL,
318
319 DAC_SDO => DAC_SDO,
320 DAC_SCK => DAC_SCK,
321 DAC_SYNC => DAC_SYNC,
322 DAC_CAL_EN => DAC_CAL_EN,
323
324 coarse_time => coarse_time,
325 fine_time => fine_time,
326 LFR_soft_rstn => LFR_soft_rstn
327 );
328
329 -----------------------------------------------------------------------
330 --- SpaceWire --------------------------------------------------------
331 -----------------------------------------------------------------------
332
333 ------------------------------------------------------------------------------
334 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
335 ------------------------------------------------------------------------------
336 spw1_en <= '1';
337 spw2_en <= '1';
338 ------------------------------------------------------------------------------
339 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
340 ------------------------------------------------------------------------------
341
342 --spw_clk <= clk50MHz;
343 --spw_rxtxclk <= spw_clk;
344 --spw_rxclkn <= NOT spw_rxtxclk;
345
346 -- PADS for SPW1
347 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
348 PORT MAP (spw1_din, dtmp(0));
349 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
350 PORT MAP (spw1_sin, stmp(0));
351 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
352 PORT MAP (spw1_dout, swno.d(0));
353 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
354 PORT MAP (spw1_sout, swno.s(0));
355 -- PADS FOR SPW2
356 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
357 PORT MAP (spw2_din, dtmp(1));
358 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
359 PORT MAP (spw2_sin, stmp(1));
360 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
361 PORT MAP (spw2_dout, swno.d(1));
362 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
363 PORT MAP (spw2_sout, swno.s(1));
364
365 -- GRSPW PHY
366 --spw1_input: if CFG_SPW_GRSPW = 1 generate
367 spw_inputloop : FOR j IN 0 TO 1 GENERATE
368 spw_phy0 : grspw_phy
369 GENERIC MAP(
370 tech => axcel,-- inferred,--axdsp,--tech_leon,
371 rxclkbuftype => 1,
372 scantest => 0)
373 PORT MAP(
374 rxrst => swno.rxrst,
375 di => dtmp(j),
376 si => stmp(j),
377 rxclko => spw_rxclk(j),
378 do => swni.d(j),
379 ndo => swni.nd(j*5+4 DOWNTO j*5),
380 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
381 END GENERATE spw_inputloop;
382
383 -- SPW core
384 sw0 : grspwm GENERIC MAP(
385 tech => axcel,--inferred,--axdsp,--tech_leon,
386 hindex => 1,
387 pindex => 5,
388 paddr => 5,
389 pirq => 11,
390 sysfreq => 25000, -- CPU_FREQ
391 rmap => 1,
392 rmapcrc => 1,
393 fifosize1 => 16,
394 fifosize2 => 16,
395 rxclkbuftype => 1,
396 rxunaligned => 0,
397 rmapbufs => 4,
398 ft => 1,
399 netlist => 0,
400 ports => 2,
401 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
402 memtech => axcel,--inferred,--tech_leon,
403 destkey => 2,
404 spwcore => 1
405 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
406 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
407 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
408 )
409 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
410 spw_rxclk(1),
411 clk50MHz_int,
412 clk50MHz_int,
413 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
414 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
415 swni, swno);
416
417 swni.tickin <= '0';
418 swni.rmapen <= '1';
419 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
420 swni.tickinraw <= '0';
421 swni.timein <= (OTHERS => '0');
422 swni.dcrstval <= (OTHERS => '0');
423 swni.timerrstval <= (OTHERS => '0');
424
425 -------------------------------------------------------------------------------
426 -- LFR ------------------------------------------------------------------------
427 -------------------------------------------------------------------------------
428 LFR_rstn <= LFR_soft_rstn AND rstn_25;
429
430 --lpp_lfr_1 : lpp_lfr
431 -- GENERIC MAP (
432 -- Mem_use => Mem_use,
433 -- tech => inferred,--tech,
434 -- nb_data_by_buffer_size => 32,
435 -- --nb_word_by_buffer_size => 30,
436 -- nb_snapshot_param_size => 32,
437 -- delta_vector_size => 32,
438 -- delta_vector_size_f0_2 => 7, -- log2(96)
439 -- pindex => 15,
440 -- paddr => 15,
441 -- pmask => 16#fff#,
442 -- pirq_ms => 6,
443 -- pirq_wfp => 14,
444 -- hindex => 2,
445 -- top_lfr_version => X"020153", -- aa.bb.cc version
446 -- -- AA : BOARD NUMBER
447 -- -- 0 => MINI_LFR
448 -- -- 1 => EM
449 -- -- 2 => EQM (with A3PE3000)
450 -- DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA)
451 -- PORT MAP (
452 -- clk => clk_25,
453 -- rstn => LFR_rstn,
454 -- sample_B => sample_s(2 DOWNTO 0),
455 -- sample_E => sample_s(7 DOWNTO 3),
456 -- sample_val => sample_val,
457 -- apbi => apbi_ext,
458 -- apbo => apbo_ext(15),
459 -- ahbi => ahbi_m_ext,
460 -- ahbo => ahbo_m_ext(2),
461 -- coarse_time => coarse_time,
462 -- fine_time => fine_time,
463 -- data_shaping_BW => bias_fail_sw,
464 -- debug_vector => debug_vector,
465 -- debug_vector_ms => OPEN); --,
466 --observation_vector_0 => OPEN,
467 --observation_vector_1 => OPEN,
468 --observation_reg => observation_reg);
469
470
471 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
472 sample_s(I) <= sample(I) & '0' & '0';
473 END GENERATE all_sample;
474 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
475
476 -----------------------------------------------------------------------------
477 --
478 -----------------------------------------------------------------------------
479 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
480 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
481 GENERIC MAP (
482 ChanelCount => 9,
483 ncycle_cnv_high => 12,
484 ncycle_cnv => 25,
485 FILTER_ENABLED => 16#FF#)
486 PORT MAP (
487 cnv_clk => clk_24,
488 cnv_rstn => rstn_24,
489 cnv => ADC_smpclk_s,
490 clk => clk_25,
491 rstn => rstn_25,
492 ADC_data => ADC_data,
493 ADC_nOE => ADC_OEB_bar_CH_s,
494 sample => sample,
495 sample_val => sample_val);
496
497 END GENERATE USE_ADCDRIVER_true;
498
499 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
500 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
501 GENERIC MAP (
502 ChanelCount => 9,
503 ncycle_cnv_high => 25,
504 ncycle_cnv => 50,
505 FILTER_ENABLED => 16#FF#)
506 PORT MAP (
507 cnv_clk => clk_24,
508 cnv_rstn => rstn_24,
509 cnv => ADC_smpclk_s,
510 clk => clk_25,
511 rstn => rstn_25,
512 ADC_data => ADC_data,
513 ADC_nOE => OPEN,
514 sample => OPEN,
515 sample_val => sample_val);
516
517 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
518
519 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
520 ramp_generator_1: ramp_generator
521 GENERIC MAP (
522 DATA_SIZE => 14,
523 VALUE_UNSIGNED_INIT => 2**I,
524 VALUE_UNSIGNED_INCR => 0,
525 VALUE_UNSIGNED_MASK => 16#3FFF#)
526 PORT MAP (
527 clk => clk_25,
528 rstn => rstn_25,
529 new_data => sample_val,
530 output_data => sample(I) );
531 END GENERATE all_sample;
532
533
534 END GENERATE USE_ADCDRIVER_false;
535
536
537
538
539 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
540
541 ADC_smpclk <= ADC_smpclk_s;
542 HK_smpclk <= ADC_smpclk_s;
543
544
545 -----------------------------------------------------------------------------
546 -- HK
547 -----------------------------------------------------------------------------
548 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
549
550 -----------------------------------------------------------------------------
551 --
552 -----------------------------------------------------------------------------
553 --inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
554 -- lpp_bootloader_1: lpp_bootloader
555 -- GENERIC MAP (
556 -- pindex => 13,
557 -- paddr => 13,
558 -- pmask => 16#fff#,
559 -- hindex => 3,
560 -- haddr => 0,
561 -- hmask => 16#fff#)
562 -- PORT MAP (
563 -- HCLK => clk_25,
564 -- HRESETn => rstn_25,
565 -- apbi => apbi_ext,
566 -- apbo => apbo_ext(13),
567 -- ahbsi => ahbi_s_ext,
568 -- ahbso => ahbo_s_ext(3));
569 --END GENERATE inst_bootloader;
570
571 -----------------------------------------------------------------------------
572 --
573 -----------------------------------------------------------------------------
574 USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
575 PROCESS (clk_25, rstn_25)
576 BEGIN -- PROCESS
577 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
578 TAG <= (OTHERS => '0');
579 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
580 TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
581 END IF;
582 END PROCESS;
583
584
585 END GENERATE USE_DEBUG_VECTOR_IF;
586
587 USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
588 ahbrxd <= TAG(1);
589 TAG(3) <= ahbtxd;
590 urxd1 <= TAG(2);
591 TAG(4) <= utxd1;
592 TAG(8) <= nSRAM_BUSY;
593 END GENERATE USE_DEBUG_VECTOR_IF2;
594
595 END beh;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.sim.ALL;
32 USE gaisler.memctrl.ALL;
33 USE gaisler.leon3.ALL;
34 USE gaisler.uart.ALL;
35 USE gaisler.misc.ALL;
36 USE gaisler.spacewire.ALL;
37 LIBRARY esa;
38 USE esa.memoryctrl.ALL;
39 LIBRARY lpp;
40 USE lpp.lpp_memory.ALL;
41 USE lpp.lpp_ad_conv.ALL;
42 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
43 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
44 USE lpp.iir_filter.ALL;
45 USE lpp.general_purpose.ALL;
46 USE lpp.lpp_lfr_management.ALL;
47 USE lpp.lpp_leon3_soc_pkg.ALL;
48
49 --library proasic3l;
50 --use proasic3l.all;
51
52
53 ENTITY lfr_subsystem IS
54 GENERIC (
55 Mem_use : INTEGER := use_RAM
56 );
57 PORT (
58 clk_25 : IN STD_LOGIC;
59 LFR_soft_rstn : IN STD_LOGIC;
60 rstn_25 : IN STD_LOGIC;
61 -- SAMPLE
62 sample_s : IN Samples(7 DOWNTO 0);
63 sample_val : IN STD_LOGIC;
64 -- APB
65 apbi_ext : IN apb_slv_in_type;
66 apbo_ext : OUT apb_slv_out_type;
67 -- AHB
68 ahbi_m_ext : IN AHB_Mst_In_Type;
69 ahbo_m_ext : OUT AHB_Mst_Out_Type;
70 -- TIME
71 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
72 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
73 --
74 bias_fail_sw : OUT STD_LOGIC;
75 --
76 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
77 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
78 );
79 END lfr_subsystem;
80
81
82 ARCHITECTURE beh OF lfr_subsystem IS
83 SIGNAL LFR_rstn : STD_LOGIC;
84 BEGIN -- beh
85
86 LFR_rstn <= LFR_soft_rstn AND rstn_25;
87
88 lpp_lfr_1 : lpp_lfr
89 GENERIC MAP (
90 Mem_use => Mem_use,
91 tech => inferred,--tech,
92 nb_data_by_buffer_size => 32,
93 --nb_word_by_buffer_size => 30,
94 nb_snapshot_param_size => 32,
95 delta_vector_size => 32,
96 delta_vector_size_f0_2 => 7, -- log2(96)
97 pindex => 15,
98 paddr => 15,
99 pmask => 16#fff#,
100 pirq_ms => 6,
101 pirq_wfp => 14,
102 hindex => 2,
103 top_lfr_version => X"020153", -- aa.bb.cc version
104 -- AA : BOARD NUMBER
105 -- 0 => MINI_LFR
106 -- 1 => EM
107 -- 2 => EQM (with A3PE3000)
108 DEBUG_FORCE_DATA_DMA => 0)
109 PORT MAP (
110 clk => clk_25,
111 rstn => LFR_rstn,
112 sample_B => sample_s(2 DOWNTO 0),
113 sample_E => sample_s(7 DOWNTO 3),
114 sample_val => sample_val,
115 apbi => apbi_ext,
116 apbo => apbo_ext,
117 ahbi => ahbi_m_ext,
118 ahbo => ahbo_m_ext,
119 coarse_time => coarse_time,
120 fine_time => fine_time,
121 data_shaping_BW => bias_fail_sw,
122 debug_vector => debug_vector,
123 debug_vector_ms => OPEN);
124
125 END beh; No newline at end of file
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1 #GRLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=LFR_EQM
6 BOARD=LFR-EQM
7 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
12 XSTOPT=
13 #SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
16 VHDLSYNFILES=LFR-EQM.vhd
17 VHDLSIMFILES=testbench.vhd
18 #SIMTOP=testbench
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc
20 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn.sdc
21 ##SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route_RTAX_ALTRAN.sdc
22 ##SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM.sdc
23
24 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
25 CLEAN=soft-clean
26
27 TECHLIBS = axcelerator
28
29 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
30 tmtc openchip hynix ihp gleichmann micron usbhc
31
32 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
33 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
34 ./amba_lcd_16x2_ctrlr \
35 ./general_purpose/lpp_AMR \
36 ./general_purpose/lpp_balise \
37 ./general_purpose/lpp_delay \
38 ./lpp_bootloader \
39 ./dsp/lpp_fft \
40 ./lpp_uart \
41 ./lpp_usb \
42 ./lpp_sim/CY7C1061DV33 \
43
44 FILESKIP = i2cmst.vhd \
45 APB_MULTI_DIODE.vhd \
46 APB_MULTI_DIODE.vhd \
47 Top_MatrixSpec.vhd \
48 APB_FFT.vhd\
49 CoreFFT_simu.vhd \
50 lpp_lfr_apbreg_simu.vhd
51
52 include $(GRLIB)/bin/Makefile
53 include $(GRLIB)/software/leon3/Makefile
54
55 ################## project specific targets ##########################
56
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4 use IEEE.std_logic_textio.all;
5 LIBRARY STD;
6 use std.textio.all;
7
8 LIBRARY grlib;
9 USE grlib.stdlib.ALL;
10 LIBRARY gaisler;
11 USE gaisler.libdcom.ALL;
12 USE gaisler.sim.ALL;
13 USE gaisler.jtagtst.ALL;
14 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
16
17 LIBRARY lpp;
18 USE lpp.lpp_sim_pkg.ALL;
19 USE lpp.lpp_lfr_sim_pkg.ALL;
20 USE lpp.lpp_lfr_apbreg_pkg.ALL;
21 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
22
23
24 ENTITY testbench IS
25 END;
26
27 ARCHITECTURE behav OF testbench IS
28
29 COMPONENT LFR_em
30 PORT (
31 clk100MHz : IN STD_ULOGIC;
32 clk49_152MHz : IN STD_ULOGIC;
33 reset : IN STD_ULOGIC;
34 TAG1 : IN STD_ULOGIC;
35 TAG3 : OUT STD_ULOGIC;
36 TAG2 : IN STD_ULOGIC;
37 TAG4 : OUT STD_ULOGIC;
38 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
39 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
40 nSRAM_BE0 : OUT STD_LOGIC;
41 nSRAM_BE1 : OUT STD_LOGIC;
42 nSRAM_BE2 : OUT STD_LOGIC;
43 nSRAM_BE3 : OUT STD_LOGIC;
44 nSRAM_WE : OUT STD_LOGIC;
45 nSRAM_CE : OUT STD_LOGIC;
46 nSRAM_OE : OUT STD_LOGIC;
47 spw1_din : IN STD_LOGIC;
48 spw1_sin : IN STD_LOGIC;
49 spw1_dout : OUT STD_LOGIC;
50 spw1_sout : OUT STD_LOGIC;
51 spw2_din : IN STD_LOGIC;
52 spw2_sin : IN STD_LOGIC;
53 spw2_dout : OUT STD_LOGIC;
54 spw2_sout : OUT STD_LOGIC;
55 bias_fail_sw : OUT STD_LOGIC;
56 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
57 ADC_smpclk : OUT STD_LOGIC;
58 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
59 HK_smpclk : OUT STD_LOGIC;
60 ADC_OEB_bar_HK : OUT STD_LOGIC;
61 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
62 TAG8 : OUT STD_LOGIC;
63 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
64 END COMPONENT;
65
66
67 --COMPONENT MINI_LFR_top
68 -- PORT (
69 -- clk_50 : IN STD_LOGIC;
70 -- clk_49 : IN STD_LOGIC;
71 -- reset : IN STD_LOGIC;
72 -- BP0 : IN STD_LOGIC;
73 -- BP1 : IN STD_LOGIC;
74 -- LED0 : OUT STD_LOGIC;
75 -- LED1 : OUT STD_LOGIC;
76 -- LED2 : OUT STD_LOGIC;
77 -- TXD1 : IN STD_LOGIC;
78 -- RXD1 : OUT STD_LOGIC;
79 -- nCTS1 : OUT STD_LOGIC;
80 -- nRTS1 : IN STD_LOGIC;
81 -- TXD2 : IN STD_LOGIC;
82 -- RXD2 : OUT STD_LOGIC;
83 -- nCTS2 : OUT STD_LOGIC;
84 -- nDTR2 : IN STD_LOGIC;
85 -- nRTS2 : IN STD_LOGIC;
86 -- nDCD2 : OUT STD_LOGIC;
87 -- IO0 : INOUT STD_LOGIC;
88 -- IO1 : INOUT STD_LOGIC;
89 -- IO2 : INOUT STD_LOGIC;
90 -- IO3 : INOUT STD_LOGIC;
91 -- IO4 : INOUT STD_LOGIC;
92 -- IO5 : INOUT STD_LOGIC;
93 -- IO6 : INOUT STD_LOGIC;
94 -- IO7 : INOUT STD_LOGIC;
95 -- IO8 : INOUT STD_LOGIC;
96 -- IO9 : INOUT STD_LOGIC;
97 -- IO10 : INOUT STD_LOGIC;
98 -- IO11 : INOUT STD_LOGIC;
99 -- SPW_EN : OUT STD_LOGIC;
100 -- SPW_NOM_DIN : IN STD_LOGIC;
101 -- SPW_NOM_SIN : IN STD_LOGIC;
102 -- SPW_NOM_DOUT : OUT STD_LOGIC;
103 -- SPW_NOM_SOUT : OUT STD_LOGIC;
104 -- SPW_RED_DIN : IN STD_LOGIC;
105 -- SPW_RED_SIN : IN STD_LOGIC;
106 -- SPW_RED_DOUT : OUT STD_LOGIC;
107 -- SPW_RED_SOUT : OUT STD_LOGIC;
108 -- ADC_nCS : OUT STD_LOGIC;
109 -- ADC_CLK : OUT STD_LOGIC;
110 -- ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
111 -- SRAM_nWE : OUT STD_LOGIC;
112 -- SRAM_CE : OUT STD_LOGIC;
113 -- SRAM_nOE : OUT STD_LOGIC;
114 -- SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
115 -- SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
116 -- SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
117 --END COMPONENT;
118
119 -----------------------------------------------------------------------------
120 SIGNAL clk_50 : STD_LOGIC := '0';
121 SIGNAL clk_49 : STD_LOGIC := '0';
122 SIGNAL reset : STD_LOGIC;
123 SIGNAL BP0 : STD_LOGIC;
124 SIGNAL BP1 : STD_LOGIC;
125 SIGNAL LED0 : STD_LOGIC;
126 SIGNAL LED1 : STD_LOGIC;
127 SIGNAL LED2 : STD_LOGIC;
128 SIGNAL TXD1 : STD_LOGIC;
129 SIGNAL RXD1 : STD_LOGIC;
130 SIGNAL nCTS1 : STD_LOGIC;
131 SIGNAL nRTS1 : STD_LOGIC;
132 SIGNAL TXD2 : STD_LOGIC;
133 SIGNAL RXD2 : STD_LOGIC;
134 SIGNAL nCTS2 : STD_LOGIC;
135 SIGNAL nDTR2 : STD_LOGIC;
136 SIGNAL nRTS2 : STD_LOGIC;
137 SIGNAL nDCD2 : STD_LOGIC;
138 SIGNAL IO0 : STD_LOGIC;
139 SIGNAL IO1 : STD_LOGIC;
140 SIGNAL IO2 : STD_LOGIC;
141 SIGNAL IO3 : STD_LOGIC;
142 SIGNAL IO4 : STD_LOGIC;
143 SIGNAL IO5 : STD_LOGIC;
144 SIGNAL IO6 : STD_LOGIC;
145 SIGNAL IO7 : STD_LOGIC;
146 SIGNAL IO8 : STD_LOGIC;
147 SIGNAL IO9 : STD_LOGIC;
148 SIGNAL IO10 : STD_LOGIC;
149 SIGNAL IO11 : STD_LOGIC;
150 SIGNAL SPW_EN : STD_LOGIC;
151 SIGNAL SPW_NOM_DIN : STD_LOGIC;
152 SIGNAL SPW_NOM_SIN : STD_LOGIC;
153 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
154 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
155 SIGNAL SPW_RED_DIN : STD_LOGIC;
156 SIGNAL SPW_RED_SIN : STD_LOGIC;
157 SIGNAL SPW_RED_DOUT : STD_LOGIC;
158 SIGNAL SPW_RED_SOUT : STD_LOGIC;
159 SIGNAL ADC_nCS : STD_LOGIC;
160 SIGNAL ADC_CLK : STD_LOGIC;
161 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
162 SIGNAL SRAM_nWE : STD_LOGIC;
163 SIGNAL SRAM_CE : STD_LOGIC;
164 SIGNAL SRAM_nOE : STD_LOGIC;
165 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
167 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
168
169 -----------------------------------------------------------------------------
170
171 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0);
172 SIGNAL ADC_smpclk : STD_LOGIC;
173 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0);
174 SIGNAL HK_smpclk : STD_LOGIC;
175 SIGNAL ADC_OEB_bar_HK : STD_LOGIC;
176 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
177
178 SIGNAL all_OEB_bar : STD_LOGIC_VECTOR(8 DOWNTO 0);
179 SIGNAL HK_SEL_DATA : STD_LOGIC_VECTOR(13 DOWNTO 0);
180
181 -----------------------------------------------------------------------------
182
183 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
184 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
185 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
186
187
188 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
189 SIGNAL data_message : STRING(1 TO 15) := "---------------";
190 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
191
192 BEGIN
193
194 -----------------------------------------------------------------------------
195 -- TB
196 -----------------------------------------------------------------------------
197 PROCESS
198 CONSTANT txp : TIME := 320 ns;
199 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
200 BEGIN -- PROCESS
201 TXD1 <= '1';
202 reset <= '0';
203 WAIT FOR 500 ns;
204 reset <= '1';
205 WAIT FOR 10000 ns;
206 message_simu <= "0 - UART init ";
207 UART_INIT(TXD1,txp);
208
209 message_simu <= "1 - UART test ";
210 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
211 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
212 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
213 UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v);
214 data_read <= data_read_v;
215 data_message <= "GPIO_data_write";
216
217 -- UNSET the LFR reset
218 message_simu <= "2 - LFR UNRESET";
219 UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT);
220 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
221 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
222 --
223 message_simu <= "3 - LFR CONFIG ";
224 --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
225 LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR,
226 X"40000000",
227 X"40001000",
228 X"40002000",
229 X"40003000",
230 X"40004000",
231 X"40005000");
232
233
234 LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp,
235 LFR_MODE_SBM1,
236 X"7FFFFFFF", -- START DATE
237
238 "00000",--DATA_SHAPING ( 4 DOWNTO 0)
239 X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0)
240 X"0001280A",--DELTA_F0 (31 DOWNTO 0)
241 X"00000007",--DELTA_F0_2 (31 DOWNTO 0)
242 X"0001283F",--DELTA_F1 (31 DOWNTO 0)
243 X"000127FF",--DELTA_F2 (31 DOWNTO 0)
244
245 ADDR_BASE_LFR,
246 X"40006000",
247 X"40007000",
248 X"40008000",
249 X"40009000",
250 X"4000A000",
251 X"4000B000",
252 X"4000C000",
253 X"4000D000");
254
255 UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F");
256 UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
257
258 message_simu <= "4 - GO GO GO !!";
259 UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000");
260
261 READ_STATUS: LOOP
262 WAIT FOR 2 ms;
263 data_message <= "READ_NEW_STATUS";
264 UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
265 data_read <= data_read_v;
266 UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
267
268 UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v);
269 data_read <= data_read_v;
270 UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v);
271 END LOOP READ_STATUS;
272
273 WAIT;
274 END PROCESS;
275
276 -----------------------------------------------------------------------------
277 -- CLOCK
278 -----------------------------------------------------------------------------
279 clk_50 <= NOT clk_50 AFTER 5 ns;
280 clk_49 <= NOT clk_49 AFTER 10172 ps;
281
282 -----------------------------------------------------------------------------
283 -- DON'T CARE
284 -----------------------------------------------------------------------------
285 BP0 <= '0';
286 BP1 <= '0';
287 nRTS1 <= '0' ;
288
289 TXD2 <= '1';
290 nRTS2 <= '1';
291 nDTR2 <= '1';
292
293 SPW_NOM_DIN <= '1';
294 SPW_NOM_SIN <= '1';
295 SPW_RED_DIN <= '1';
296 SPW_RED_SIN <= '1';
297
298 ADC_SDO <= x"AA";
299
300 SRAM_DQ <= (OTHERS => 'Z');
301 --IO0 <= 'Z';
302 --IO1 <= 'Z';
303 --IO2 <= 'Z';
304 --IO3 <= 'Z';
305 --IO4 <= 'Z';
306 --IO5 <= 'Z';
307 --IO6 <= 'Z';
308 --IO7 <= 'Z';
309 --IO8 <= 'Z';
310 --IO9 <= 'Z';
311 --IO10 <= 'Z';
312 --IO11 <= 'Z';
313
314 -----------------------------------------------------------------------------
315 -- DUT
316 -----------------------------------------------------------------------------
317
318 LFR_em_1: LFR_em
319 PORT MAP (
320 clk100MHz => clk_50,
321 clk49_152MHz => clk_49,
322 reset => reset,
323
324 TAG1 => TXD1,
325 TAG3 => RXD1,
326 TAG2 => TXD2,
327 TAG4 => RXD2,
328
329 address => SRAM_A,
330 data => SRAM_DQ,
331 nSRAM_BE0 => SRAM_nBE(0),
332 nSRAM_BE1 => SRAM_nBE(1),
333 nSRAM_BE2 => SRAM_nBE(2),
334 nSRAM_BE3 => SRAM_nBE(3),
335 nSRAM_WE => SRAM_nWE,
336 nSRAM_CE => SRAM_CE,
337 nSRAM_OE => SRAM_nOE,
338
339 spw1_din => SPW_NOM_DIN,
340 spw1_sin => SPW_NOM_SIN,
341 spw1_dout => SPW_NOM_DOUT,
342 spw1_sout => SPW_NOM_SOUT,
343 spw2_din => SPW_RED_DIN,
344 spw2_sin => SPW_RED_SIN,
345 spw2_dout => SPW_RED_DOUT,
346 spw2_sout => SPW_RED_SOUT,
347
348 bias_fail_sw => OPEN,
349
350 ADC_OEB_bar_CH => ADC_OEB_bar_CH,
351 ADC_smpclk => ADC_smpclk,
352 ADC_data => ADC_data,
353 HK_smpclk => HK_smpclk,
354 ADC_OEB_bar_HK => ADC_OEB_bar_HK,
355 HK_SEL => HK_SEL,
356
357 TAG8 => OPEN,
358 led => OPEN);
359
360 all_OEB_bar <= ADC_OEB_bar_HK & ADC_OEB_bar_CH;
361
362 WITH HK_SEL SELECT
363 HK_SEL_DATA <=
364 "00"&X"00F" WHEN "00",
365 "00"&X"01F" WHEN "01",
366 "00"&X"02F" WHEN "10",
367 "XXXXXXXXXXXXXX" WHEN OTHERS;
368
369 WITH all_OEB_bar SELECT
370 ADC_data <=
371 "00"&X"000" WHEN "111111110",
372 "00"&X"001" WHEN "111111101",
373 "00"&X"002" WHEN "111111011",
374 "00"&X"003" WHEN "111110111",
375 "00"&X"004" WHEN "111101111",
376 "00"&X"005" WHEN "111011111",
377 "00"&X"006" WHEN "110111111",
378 "00"&X"007" WHEN "101111111",
379 HK_SEL_DATA WHEN "011111111",
380 "XXXXXXXXXXXXXX" WHEN OTHERS;
381
382 END;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.sim.ALL;
32 USE gaisler.memctrl.ALL;
33 USE gaisler.leon3.ALL;
34 USE gaisler.uart.ALL;
35 USE gaisler.misc.ALL;
36 USE gaisler.spacewire.ALL;
37 LIBRARY esa;
38 USE esa.memoryctrl.ALL;
39 LIBRARY lpp;
40 USE lpp.lpp_memory.ALL;
41 USE lpp.lpp_ad_conv.ALL;
42 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
43 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
44 USE lpp.iir_filter.ALL;
45 USE lpp.general_purpose.ALL;
46 USE lpp.lpp_lfr_management.ALL;
47 USE lpp.lpp_leon3_soc_pkg.ALL;
48
49 --library proasic3l;
50 --use proasic3l.all;
51
52 ENTITY LFR_EQM IS
53 GENERIC (
54 Mem_use : INTEGER := use_RAM;
55 USE_BOOTLOADER : INTEGER := 0;
56 USE_ADCDRIVER : INTEGER := 1;
57 tech : INTEGER := inferred;
58 tech_leon : INTEGER := inferred;
59 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
60 USE_DEBUG_VECTOR : INTEGER := 0
61 );
62
63 PORT (
64 clk50MHz : IN STD_ULOGIC;
65 clk49_152MHz : IN STD_ULOGIC;
66 reset : IN STD_ULOGIC;
67
68 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
69
70 -- TAG --------------------------------------------------------------------
71 --TAG1 : IN STD_ULOGIC; -- DSU rx data
72 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
73 -- UART APB ---------------------------------------------------------------
74 --TAG2 : IN STD_ULOGIC; -- UART1 rx data
75 --TAG4 : OUT STD_ULOGIC; -- UART1 tx data
76 -- RAM --------------------------------------------------------------------
77 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
78 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79
80 nSRAM_MBE : INOUT STD_LOGIC; -- new
81 nSRAM_E1 : OUT STD_LOGIC; -- new
82 nSRAM_E2 : OUT STD_LOGIC; -- new
83 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
84 nSRAM_W : OUT STD_LOGIC; -- new
85 nSRAM_G : OUT STD_LOGIC; -- new
86 nSRAM_BUSY : IN STD_LOGIC; -- new
87 -- SPW --------------------------------------------------------------------
88 spw1_en : OUT STD_LOGIC; -- new
89 spw1_din : IN STD_LOGIC;
90 spw1_sin : IN STD_LOGIC;
91 spw1_dout : OUT STD_LOGIC;
92 spw1_sout : OUT STD_LOGIC;
93 spw2_en : OUT STD_LOGIC; -- new
94 spw2_din : IN STD_LOGIC;
95 spw2_sin : IN STD_LOGIC;
96 spw2_dout : OUT STD_LOGIC;
97 spw2_sout : OUT STD_LOGIC;
98 -- ADC --------------------------------------------------------------------
99 bias_fail_sw : OUT STD_LOGIC;
100 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_smpclk : OUT STD_LOGIC;
102 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
103 -- DAC --------------------------------------------------------------------
104 DAC_SDO : OUT STD_LOGIC;
105 DAC_SCK : OUT STD_LOGIC;
106 DAC_SYNC : OUT STD_LOGIC;
107 DAC_CAL_EN : OUT STD_LOGIC;
108 -- HK ---------------------------------------------------------------------
109 HK_smpclk : OUT STD_LOGIC;
110 ADC_OEB_bar_HK : OUT STD_LOGIC;
111 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--;
112 ---------------------------------------------------------------------------
113 -- TAG8 : OUT STD_LOGIC
114 );
115
116 END LFR_EQM;
117
118
119 ARCHITECTURE beh OF LFR_EQM IS
120
121 SIGNAL clk_25 : STD_LOGIC := '0';
122 SIGNAL clk_24 : STD_LOGIC := '0';
123 -----------------------------------------------------------------------------
124 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
125 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
126
127 -- CONSTANTS
128 CONSTANT CFG_PADTECH : INTEGER := inferred;
129 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
130 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
131 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
132
133 SIGNAL apbi_ext : apb_slv_in_type;
134 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
135 SIGNAL ahbi_s_ext : ahb_slv_in_type;
136 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
137 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
138 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
139
140 -- Spacewire signals
141 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
142 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
143 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
144 SIGNAL swni : grspw_in_type;
145 SIGNAL swno : grspw_out_type;
146
147 --GPIO
148 SIGNAL gpioi : gpio_in_type;
149 SIGNAL gpioo : gpio_out_type;
150
151 -- AD Converter ADS7886
152 SIGNAL sample : Samples14v(8 DOWNTO 0);
153 SIGNAL sample_s : Samples(8 DOWNTO 0);
154 SIGNAL sample_val : STD_LOGIC;
155 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
156
157 -----------------------------------------------------------------------------
158 SIGNAL rstn_25 : STD_LOGIC;
159 SIGNAL rstn_24 : STD_LOGIC;
160
161 SIGNAL LFR_soft_rstn : STD_LOGIC;
162 SIGNAL LFR_rstn : STD_LOGIC;
163
164 SIGNAL ADC_smpclk_s : STD_LOGIC;
165
166 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
167
168 SIGNAL clk50MHz_int : STD_LOGIC := '0';
169
170 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
171
172 SIGNAL rstn_50 : STD_LOGIC;
173 SIGNAL clk_lock : STD_LOGIC;
174 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
175 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
176
177 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
178 SIGNAL ahbrxd: STD_LOGIC;
179 SIGNAL ahbtxd: STD_LOGIC;
180 SIGNAL urxd1 : STD_LOGIC;
181 SIGNAL utxd1 : STD_LOGIC;
182 BEGIN -- beh
183
184 -----------------------------------------------------------------------------
185 -- CLK_LOCK
186 -----------------------------------------------------------------------------
187 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
188
189 PROCESS (clk50MHz_int, rstn_50)
190 BEGIN -- PROCESS
191 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
192 clk_lock <= '0';
193 clk_busy_counter <= (OTHERS => '0');
194 nSRAM_BUSY_reg <= '0';
195 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
196 nSRAM_BUSY_reg <= nSRAM_BUSY;
197 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
198 IF clk_busy_counter = "1111" THEN
199 clk_lock <= '1';
200 ELSE
201 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
202 END IF;
203 END IF;
204 END IF;
205 END PROCESS;
206
207 -----------------------------------------------------------------------------
208 -- CLK
209 -----------------------------------------------------------------------------
210 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
211 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
212
213 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
214 clk50MHz_int <= clk50MHz;
215
216 PROCESS(clk50MHz_int)
217 BEGIN
218 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
219 --clk_25_int <= NOT clk_25_int;
220 clk_25 <= NOT clk_25;
221 END IF;
222 END PROCESS;
223 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
224
225 PROCESS(clk49_152MHz)
226 BEGIN
227 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
228 clk_24 <= NOT clk_24;
229 END IF;
230 END PROCESS;
231 -- clk_49 <= clk49_152MHz;
232
233 -----------------------------------------------------------------------------
234 --
235 leon3_soc_1 : leon3_soc
236 GENERIC MAP (
237 fabtech => axcel,--inferred,--axdsp,
238 memtech => axcel,--inferred,--tech_leon,
239 padtech => axcel,--inferred,
240 clktech => axcel,--inferred,
241 disas => 0,
242 dbguart => 0,
243 pclow => 2,
244 clk_freq => 25000,
245 IS_RADHARD => 1,
246 NB_CPU => 1,
247 ENABLE_FPU => 1,
248 FPU_NETLIST => 1,
249 ENABLE_DSU => 1,
250 ENABLE_AHB_UART => 1,
251 ENABLE_APB_UART => 1,
252 ENABLE_IRQMP => 1,
253 ENABLE_GPT => 1,
254 NB_AHB_MASTER => NB_AHB_MASTER,
255 NB_AHB_SLAVE => NB_AHB_SLAVE,
256 NB_APB_SLAVE => NB_APB_SLAVE,
257 ADDRESS_SIZE => 19,
258 USES_IAP_MEMCTRLR => 1,
259 BYPASS_EDAC_MEMCTRLR => '0',
260 SRBANKSZ => 8)
261 PORT MAP (
262 clk => clk_25,
263 reset => rstn_25,
264 errorn => OPEN,
265
266 ahbrxd => ahbrxd, -- INPUT
267 ahbtxd => ahbtxd, -- OUTPUT
268 urxd1 => urxd1, -- INPUT
269 utxd1 => utxd1, -- OUTPUT
270
271 address => address,
272 data => data,
273 nSRAM_BE0 => OPEN,
274 nSRAM_BE1 => OPEN,
275 nSRAM_BE2 => OPEN,
276 nSRAM_BE3 => OPEN,
277 nSRAM_WE => nSRAM_W,
278 nSRAM_CE => nSRAM_CE,
279 nSRAM_OE => nSRAM_G,
280 nSRAM_READY => nSRAM_BUSY,
281 SRAM_MBE => nSRAM_MBE,
282
283 apbi_ext => apbi_ext,
284 apbo_ext => apbo_ext,
285 ahbi_s_ext => ahbi_s_ext,
286 ahbo_s_ext => ahbo_s_ext,
287 ahbi_m_ext => ahbi_m_ext,
288 ahbo_m_ext => ahbo_m_ext);
289
290
291 nSRAM_E1 <= nSRAM_CE(0);
292 nSRAM_E2 <= nSRAM_CE(1);
293
294 -------------------------------------------------------------------------------
295 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
296 -------------------------------------------------------------------------------
297 apb_lfr_management_1 : apb_lfr_management
298 GENERIC MAP (
299 tech => tech,
300 pindex => 6,
301 paddr => 6,
302 pmask => 16#fff#,
303 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
304 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
305 PORT MAP (
306 clk25MHz => clk_25,
307 resetn_25MHz => rstn_25, -- TODO
308 --clk24_576MHz => clk_24, -- 49.152MHz/2
309 --resetn_24_576MHz => rstn_24, -- TODO
310
311 grspw_tick => swno.tickout,
312 apbi => apbi_ext,
313 apbo => apbo_ext(6),
314
315 HK_sample => sample_s(8),
316 HK_val => sample_val,
317 HK_sel => HK_SEL,
318
319 DAC_SDO => DAC_SDO,
320 DAC_SCK => DAC_SCK,
321 DAC_SYNC => DAC_SYNC,
322 DAC_CAL_EN => DAC_CAL_EN,
323
324 coarse_time => coarse_time,
325 fine_time => fine_time,
326 LFR_soft_rstn => LFR_soft_rstn
327 );
328
329 -----------------------------------------------------------------------
330 --- SpaceWire --------------------------------------------------------
331 -----------------------------------------------------------------------
332
333 ------------------------------------------------------------------------------
334 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
335 ------------------------------------------------------------------------------
336 spw1_en <= '1';
337 spw2_en <= '1';
338 ------------------------------------------------------------------------------
339 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
340 ------------------------------------------------------------------------------
341
342 --spw_clk <= clk50MHz;
343 --spw_rxtxclk <= spw_clk;
344 --spw_rxclkn <= NOT spw_rxtxclk;
345
346 -- PADS for SPW1
347 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
348 PORT MAP (spw1_din, dtmp(0));
349 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
350 PORT MAP (spw1_sin, stmp(0));
351 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
352 PORT MAP (spw1_dout, swno.d(0));
353 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
354 PORT MAP (spw1_sout, swno.s(0));
355 -- PADS FOR SPW2
356 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
357 PORT MAP (spw2_din, dtmp(1));
358 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
359 PORT MAP (spw2_sin, stmp(1));
360 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
361 PORT MAP (spw2_dout, swno.d(1));
362 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
363 PORT MAP (spw2_sout, swno.s(1));
364
365 -- GRSPW PHY
366 --spw1_input: if CFG_SPW_GRSPW = 1 generate
367 spw_inputloop : FOR j IN 0 TO 1 GENERATE
368 spw_phy0 : grspw_phy
369 GENERIC MAP(
370 tech => axcel,-- inferred,--axdsp,--tech_leon,
371 rxclkbuftype => 1,
372 scantest => 0)
373 PORT MAP(
374 rxrst => swno.rxrst,
375 di => dtmp(j),
376 si => stmp(j),
377 rxclko => spw_rxclk(j),
378 do => swni.d(j),
379 ndo => swni.nd(j*5+4 DOWNTO j*5),
380 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
381 END GENERATE spw_inputloop;
382
383 -- SPW core
384 sw0 : grspwm GENERIC MAP(
385 tech => axcel,--inferred,--axdsp,--tech_leon,
386 hindex => 1,
387 pindex => 5,
388 paddr => 5,
389 pirq => 11,
390 sysfreq => 25000, -- CPU_FREQ
391 rmap => 1,
392 rmapcrc => 1,
393 fifosize1 => 16,
394 fifosize2 => 16,
395 rxclkbuftype => 1,
396 rxunaligned => 0,
397 rmapbufs => 4,
398 ft => 1,
399 netlist => 0,
400 ports => 2,
401 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
402 memtech => axcel,--inferred,--tech_leon,
403 destkey => 2,
404 spwcore => 1
405 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
406 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
407 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
408 )
409 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
410 spw_rxclk(1),
411 clk50MHz_int,
412 clk50MHz_int,
413 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
414 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
415 swni, swno);
416
417 swni.tickin <= '0';
418 swni.rmapen <= '1';
419 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
420 swni.tickinraw <= '0';
421 swni.timein <= (OTHERS => '0');
422 swni.dcrstval <= (OTHERS => '0');
423 swni.timerrstval <= (OTHERS => '0');
424
425 -------------------------------------------------------------------------------
426 -- LFR ------------------------------------------------------------------------
427 -------------------------------------------------------------------------------
428 --rst_domain25_lfr : rstgen PORT MAP (LFR_soft_rstn, clk_25, clk_lock, LFR_rstn, OPEN);
429 --LFR_rstn <= LFR_soft_rstn AND rstn_25;
430
431 lpp_lfr_1 : lpp_lfr
432 GENERIC MAP (
433 Mem_use => Mem_use,
434 tech => inferred,--tech,
435 nb_data_by_buffer_size => 32,
436 --nb_word_by_buffer_size => 30,
437 nb_snapshot_param_size => 32,
438 delta_vector_size => 32,
439 delta_vector_size_f0_2 => 7, -- log2(96)
440 pindex => 15,
441 paddr => 15,
442 pmask => 16#fff#,
443 pirq_ms => 6,
444 pirq_wfp => 14,
445 hindex => 2,
446 top_lfr_version => X"020153", -- aa.bb.cc version
447 -- AA : BOARD NUMBER
448 -- 0 => MINI_LFR
449 -- 1 => EM
450 -- 2 => EQM (with A3PE3000)
451 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA)
452 PORT MAP (
453 clk => clk_25,
454 rstn => rstn_25,--LFR_rstn,
455 sample_B => sample_s(2 DOWNTO 0),
456 sample_E => sample_s(7 DOWNTO 3),
457 sample_val => sample_val,
458 apbi => apbi_ext,
459 apbo => apbo_ext(15),
460 ahbi => ahbi_m_ext,
461 ahbo => ahbo_m_ext(2),
462 coarse_time => coarse_time,
463 fine_time => fine_time,
464 data_shaping_BW => bias_fail_sw,
465 debug_vector => debug_vector,
466 debug_vector_ms => OPEN); --,
467 --observation_vector_0 => OPEN,
468 --observation_vector_1 => OPEN,
469 --observation_reg => observation_reg);
470
471
472 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
473 sample_s(I) <= sample(I) & '0' & '0';
474 END GENERATE all_sample;
475 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
476
477 -----------------------------------------------------------------------------
478 --
479 -----------------------------------------------------------------------------
480 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
481 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
482 GENERIC MAP (
483 ChanelCount => 9,
484 ncycle_cnv_high => 12,
485 ncycle_cnv => 25,
486 FILTER_ENABLED => 16#FF#)
487 PORT MAP (
488 cnv_clk => clk_24,
489 cnv_rstn => rstn_24,
490 cnv => ADC_smpclk_s,
491 clk => clk_25,
492 rstn => rstn_25,
493 ADC_data => ADC_data,
494 ADC_nOE => ADC_OEB_bar_CH_s,
495 sample => sample,
496 sample_val => sample_val);
497
498 END GENERATE USE_ADCDRIVER_true;
499
500 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
501 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
502 GENERIC MAP (
503 ChanelCount => 9,
504 ncycle_cnv_high => 25,
505 ncycle_cnv => 50,
506 FILTER_ENABLED => 16#FF#)
507 PORT MAP (
508 cnv_clk => clk_24,
509 cnv_rstn => rstn_24,
510 cnv => ADC_smpclk_s,
511 clk => clk_25,
512 rstn => rstn_25,
513 ADC_data => ADC_data,
514 ADC_nOE => OPEN,
515 sample => OPEN,
516 sample_val => sample_val);
517
518 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
519
520 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
521 ramp_generator_1: ramp_generator
522 GENERIC MAP (
523 DATA_SIZE => 14,
524 VALUE_UNSIGNED_INIT => 2**I,
525 VALUE_UNSIGNED_INCR => 0,
526 VALUE_UNSIGNED_MASK => 16#3FFF#)
527 PORT MAP (
528 clk => clk_25,
529 rstn => rstn_25,
530 new_data => sample_val,
531 output_data => sample(I) );
532 END GENERATE all_sample;
533
534
535 END GENERATE USE_ADCDRIVER_false;
536
537
538
539
540 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
541
542 ADC_smpclk <= ADC_smpclk_s;
543 HK_smpclk <= ADC_smpclk_s;
544
545
546 -----------------------------------------------------------------------------
547 -- HK
548 -----------------------------------------------------------------------------
549 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
550
551 -----------------------------------------------------------------------------
552 --
553 -----------------------------------------------------------------------------
554 --inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
555 -- lpp_bootloader_1: lpp_bootloader
556 -- GENERIC MAP (
557 -- pindex => 13,
558 -- paddr => 13,
559 -- pmask => 16#fff#,
560 -- hindex => 3,
561 -- haddr => 0,
562 -- hmask => 16#fff#)
563 -- PORT MAP (
564 -- HCLK => clk_25,
565 -- HRESETn => rstn_25,
566 -- apbi => apbi_ext,
567 -- apbo => apbo_ext(13),
568 -- ahbsi => ahbi_s_ext,
569 -- ahbso => ahbo_s_ext(3));
570 --END GENERATE inst_bootloader;
571
572 -----------------------------------------------------------------------------
573 --
574 -----------------------------------------------------------------------------
575 USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
576 PROCESS (clk_25, rstn_25)
577 BEGIN -- PROCESS
578 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
579 TAG <= (OTHERS => '0');
580 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
581 TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
582 END IF;
583 END PROCESS;
584
585
586 END GENERATE USE_DEBUG_VECTOR_IF;
587
588 USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
589 ahbrxd <= TAG(1);
590 TAG(3) <= ahbtxd;
591 urxd1 <= TAG(2);
592 TAG(4) <= utxd1;
593 TAG(8) <= nSRAM_BUSY;
594 END GENERATE USE_DEBUG_VECTOR_IF2;
595
596 END beh;
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1 #GRLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=LFR_EQM
6 BOARD=LFR-EQM
7 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
12 XSTOPT=
13 #SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
16 VHDLSYNFILES=LFR-EQM.vhd
17 VHDLSIMFILES=testbench.vhd
18 #SIMTOP=testbench
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc
20 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn.sdc
21 ##SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route_RTAX_ALTRAN.sdc
22 ##SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM.sdc
23
24 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
25 CLEAN=soft-clean
26
27 TECHLIBS = axcelerator
28
29 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
30 tmtc openchip hynix ihp gleichmann micron usbhc
31
32 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
33 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
34 ./amba_lcd_16x2_ctrlr \
35 ./general_purpose/lpp_AMR \
36 ./general_purpose/lpp_balise \
37 ./general_purpose/lpp_delay \
38 ./lpp_bootloader \
39 ./dsp/lpp_fft \
40 ./lpp_uart \
41 ./lpp_usb \
42 ./lpp_sim/CY7C1061DV33 \
43
44 FILESKIP = i2cmst.vhd \
45 APB_MULTI_DIODE.vhd \
46 APB_MULTI_DIODE.vhd \
47 Top_MatrixSpec.vhd \
48 APB_FFT.vhd\
49 CoreFFT_simu.vhd \
50 lpp_lfr_apbreg_simu.vhd
51
52 include $(GRLIB)/bin/Makefile
53 include $(GRLIB)/software/leon3/Makefile
54
55 ################## project specific targets ##########################
56
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1 vcom -quiet -93 -work work LFR-em.vhd
2 vcom -quiet -93 -work work testbench.vhd
3
4 vsim work.testbench
5
6 log -r *
7
8 do wave.do
9
10 run 65 ms
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4 use IEEE.std_logic_textio.all;
5 LIBRARY STD;
6 use std.textio.all;
7
8 LIBRARY grlib;
9 USE grlib.stdlib.ALL;
10 LIBRARY gaisler;
11 USE gaisler.libdcom.ALL;
12 USE gaisler.sim.ALL;
13 USE gaisler.jtagtst.ALL;
14 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
16
17 LIBRARY lpp;
18 USE lpp.lpp_sim_pkg.ALL;
19 USE lpp.lpp_lfr_sim_pkg.ALL;
20 USE lpp.lpp_lfr_apbreg_pkg.ALL;
21 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
22
23
24 ENTITY testbench IS
25 END;
26
27 ARCHITECTURE behav OF testbench IS
28
29 COMPONENT LFR_em
30 PORT (
31 clk100MHz : IN STD_ULOGIC;
32 clk49_152MHz : IN STD_ULOGIC;
33 reset : IN STD_ULOGIC;
34 TAG1 : IN STD_ULOGIC;
35 TAG3 : OUT STD_ULOGIC;
36 TAG2 : IN STD_ULOGIC;
37 TAG4 : OUT STD_ULOGIC;
38 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
39 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
40 nSRAM_BE0 : OUT STD_LOGIC;
41 nSRAM_BE1 : OUT STD_LOGIC;
42 nSRAM_BE2 : OUT STD_LOGIC;
43 nSRAM_BE3 : OUT STD_LOGIC;
44 nSRAM_WE : OUT STD_LOGIC;
45 nSRAM_CE : OUT STD_LOGIC;
46 nSRAM_OE : OUT STD_LOGIC;
47 spw1_din : IN STD_LOGIC;
48 spw1_sin : IN STD_LOGIC;
49 spw1_dout : OUT STD_LOGIC;
50 spw1_sout : OUT STD_LOGIC;
51 spw2_din : IN STD_LOGIC;
52 spw2_sin : IN STD_LOGIC;
53 spw2_dout : OUT STD_LOGIC;
54 spw2_sout : OUT STD_LOGIC;
55 bias_fail_sw : OUT STD_LOGIC;
56 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
57 ADC_smpclk : OUT STD_LOGIC;
58 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
59 HK_smpclk : OUT STD_LOGIC;
60 ADC_OEB_bar_HK : OUT STD_LOGIC;
61 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
62 TAG8 : OUT STD_LOGIC;
63 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
64 END COMPONENT;
65
66
67 --COMPONENT MINI_LFR_top
68 -- PORT (
69 -- clk_50 : IN STD_LOGIC;
70 -- clk_49 : IN STD_LOGIC;
71 -- reset : IN STD_LOGIC;
72 -- BP0 : IN STD_LOGIC;
73 -- BP1 : IN STD_LOGIC;
74 -- LED0 : OUT STD_LOGIC;
75 -- LED1 : OUT STD_LOGIC;
76 -- LED2 : OUT STD_LOGIC;
77 -- TXD1 : IN STD_LOGIC;
78 -- RXD1 : OUT STD_LOGIC;
79 -- nCTS1 : OUT STD_LOGIC;
80 -- nRTS1 : IN STD_LOGIC;
81 -- TXD2 : IN STD_LOGIC;
82 -- RXD2 : OUT STD_LOGIC;
83 -- nCTS2 : OUT STD_LOGIC;
84 -- nDTR2 : IN STD_LOGIC;
85 -- nRTS2 : IN STD_LOGIC;
86 -- nDCD2 : OUT STD_LOGIC;
87 -- IO0 : INOUT STD_LOGIC;
88 -- IO1 : INOUT STD_LOGIC;
89 -- IO2 : INOUT STD_LOGIC;
90 -- IO3 : INOUT STD_LOGIC;
91 -- IO4 : INOUT STD_LOGIC;
92 -- IO5 : INOUT STD_LOGIC;
93 -- IO6 : INOUT STD_LOGIC;
94 -- IO7 : INOUT STD_LOGIC;
95 -- IO8 : INOUT STD_LOGIC;
96 -- IO9 : INOUT STD_LOGIC;
97 -- IO10 : INOUT STD_LOGIC;
98 -- IO11 : INOUT STD_LOGIC;
99 -- SPW_EN : OUT STD_LOGIC;
100 -- SPW_NOM_DIN : IN STD_LOGIC;
101 -- SPW_NOM_SIN : IN STD_LOGIC;
102 -- SPW_NOM_DOUT : OUT STD_LOGIC;
103 -- SPW_NOM_SOUT : OUT STD_LOGIC;
104 -- SPW_RED_DIN : IN STD_LOGIC;
105 -- SPW_RED_SIN : IN STD_LOGIC;
106 -- SPW_RED_DOUT : OUT STD_LOGIC;
107 -- SPW_RED_SOUT : OUT STD_LOGIC;
108 -- ADC_nCS : OUT STD_LOGIC;
109 -- ADC_CLK : OUT STD_LOGIC;
110 -- ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
111 -- SRAM_nWE : OUT STD_LOGIC;
112 -- SRAM_CE : OUT STD_LOGIC;
113 -- SRAM_nOE : OUT STD_LOGIC;
114 -- SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
115 -- SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
116 -- SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
117 --END COMPONENT;
118
119 -----------------------------------------------------------------------------
120 SIGNAL clk_50 : STD_LOGIC := '0';
121 SIGNAL clk_49 : STD_LOGIC := '0';
122 SIGNAL reset : STD_LOGIC;
123 SIGNAL BP0 : STD_LOGIC;
124 SIGNAL BP1 : STD_LOGIC;
125 SIGNAL LED0 : STD_LOGIC;
126 SIGNAL LED1 : STD_LOGIC;
127 SIGNAL LED2 : STD_LOGIC;
128 SIGNAL TXD1 : STD_LOGIC;
129 SIGNAL RXD1 : STD_LOGIC;
130 SIGNAL nCTS1 : STD_LOGIC;
131 SIGNAL nRTS1 : STD_LOGIC;
132 SIGNAL TXD2 : STD_LOGIC;
133 SIGNAL RXD2 : STD_LOGIC;
134 SIGNAL nCTS2 : STD_LOGIC;
135 SIGNAL nDTR2 : STD_LOGIC;
136 SIGNAL nRTS2 : STD_LOGIC;
137 SIGNAL nDCD2 : STD_LOGIC;
138 SIGNAL IO0 : STD_LOGIC;
139 SIGNAL IO1 : STD_LOGIC;
140 SIGNAL IO2 : STD_LOGIC;
141 SIGNAL IO3 : STD_LOGIC;
142 SIGNAL IO4 : STD_LOGIC;
143 SIGNAL IO5 : STD_LOGIC;
144 SIGNAL IO6 : STD_LOGIC;
145 SIGNAL IO7 : STD_LOGIC;
146 SIGNAL IO8 : STD_LOGIC;
147 SIGNAL IO9 : STD_LOGIC;
148 SIGNAL IO10 : STD_LOGIC;
149 SIGNAL IO11 : STD_LOGIC;
150 SIGNAL SPW_EN : STD_LOGIC;
151 SIGNAL SPW_NOM_DIN : STD_LOGIC;
152 SIGNAL SPW_NOM_SIN : STD_LOGIC;
153 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
154 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
155 SIGNAL SPW_RED_DIN : STD_LOGIC;
156 SIGNAL SPW_RED_SIN : STD_LOGIC;
157 SIGNAL SPW_RED_DOUT : STD_LOGIC;
158 SIGNAL SPW_RED_SOUT : STD_LOGIC;
159 SIGNAL ADC_nCS : STD_LOGIC;
160 SIGNAL ADC_CLK : STD_LOGIC;
161 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
162 SIGNAL SRAM_nWE : STD_LOGIC;
163 SIGNAL SRAM_CE : STD_LOGIC;
164 SIGNAL SRAM_nOE : STD_LOGIC;
165 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
167 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
168
169 -----------------------------------------------------------------------------
170
171 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0);
172 SIGNAL ADC_smpclk : STD_LOGIC;
173 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0);
174 SIGNAL HK_smpclk : STD_LOGIC;
175 SIGNAL ADC_OEB_bar_HK : STD_LOGIC;
176 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
177
178 SIGNAL all_OEB_bar : STD_LOGIC_VECTOR(8 DOWNTO 0);
179 SIGNAL HK_SEL_DATA : STD_LOGIC_VECTOR(13 DOWNTO 0);
180
181 -----------------------------------------------------------------------------
182
183 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
184 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
185 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
186
187
188 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
189 SIGNAL data_message : STRING(1 TO 15) := "---------------";
190 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
191
192 BEGIN
193
194 -----------------------------------------------------------------------------
195 -- TB
196 -----------------------------------------------------------------------------
197 PROCESS
198 CONSTANT txp : TIME := 320 ns;
199 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
200 BEGIN -- PROCESS
201 TXD1 <= '1';
202 reset <= '0';
203 WAIT FOR 500 ns;
204 reset <= '1';
205 WAIT FOR 10000 ns;
206 message_simu <= "0 - UART init ";
207 UART_INIT(TXD1,txp);
208
209 message_simu <= "1 - UART test ";
210 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
211 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
212 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
213 UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v);
214 data_read <= data_read_v;
215 data_message <= "GPIO_data_write";
216
217 -- UNSET the LFR reset
218 message_simu <= "2 - LFR UNRESET";
219 UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT);
220 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
221 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
222 --
223 message_simu <= "3 - LFR CONFIG ";
224 --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
225 LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR,
226 X"40000000",
227 X"40001000",
228 X"40002000",
229 X"40003000",
230 X"40004000",
231 X"40005000");
232
233
234 LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp,
235 LFR_MODE_SBM1,
236 X"7FFFFFFF", -- START DATE
237
238 "00000",--DATA_SHAPING ( 4 DOWNTO 0)
239 X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0)
240 X"0001280A",--DELTA_F0 (31 DOWNTO 0)
241 X"00000007",--DELTA_F0_2 (31 DOWNTO 0)
242 X"0001283F",--DELTA_F1 (31 DOWNTO 0)
243 X"000127FF",--DELTA_F2 (31 DOWNTO 0)
244
245 ADDR_BASE_LFR,
246 X"40006000",
247 X"40007000",
248 X"40008000",
249 X"40009000",
250 X"4000A000",
251 X"4000B000",
252 X"4000C000",
253 X"4000D000");
254
255 UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F");
256 UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
257
258 message_simu <= "4 - GO GO GO !!";
259 UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000");
260
261 READ_STATUS: LOOP
262 WAIT FOR 2 ms;
263 data_message <= "READ_NEW_STATUS";
264 UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
265 data_read <= data_read_v;
266 UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
267
268 UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v);
269 data_read <= data_read_v;
270 UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v);
271 END LOOP READ_STATUS;
272
273 WAIT;
274 END PROCESS;
275
276 -----------------------------------------------------------------------------
277 -- CLOCK
278 -----------------------------------------------------------------------------
279 clk_50 <= NOT clk_50 AFTER 5 ns;
280 clk_49 <= NOT clk_49 AFTER 10172 ps;
281
282 -----------------------------------------------------------------------------
283 -- DON'T CARE
284 -----------------------------------------------------------------------------
285 BP0 <= '0';
286 BP1 <= '0';
287 nRTS1 <= '0' ;
288
289 TXD2 <= '1';
290 nRTS2 <= '1';
291 nDTR2 <= '1';
292
293 SPW_NOM_DIN <= '1';
294 SPW_NOM_SIN <= '1';
295 SPW_RED_DIN <= '1';
296 SPW_RED_SIN <= '1';
297
298 ADC_SDO <= x"AA";
299
300 SRAM_DQ <= (OTHERS => 'Z');
301 --IO0 <= 'Z';
302 --IO1 <= 'Z';
303 --IO2 <= 'Z';
304 --IO3 <= 'Z';
305 --IO4 <= 'Z';
306 --IO5 <= 'Z';
307 --IO6 <= 'Z';
308 --IO7 <= 'Z';
309 --IO8 <= 'Z';
310 --IO9 <= 'Z';
311 --IO10 <= 'Z';
312 --IO11 <= 'Z';
313
314 -----------------------------------------------------------------------------
315 -- DUT
316 -----------------------------------------------------------------------------
317
318 LFR_em_1: LFR_em
319 PORT MAP (
320 clk100MHz => clk_50,
321 clk49_152MHz => clk_49,
322 reset => reset,
323
324 TAG1 => TXD1,
325 TAG3 => RXD1,
326 TAG2 => TXD2,
327 TAG4 => RXD2,
328
329 address => SRAM_A,
330 data => SRAM_DQ,
331 nSRAM_BE0 => SRAM_nBE(0),
332 nSRAM_BE1 => SRAM_nBE(1),
333 nSRAM_BE2 => SRAM_nBE(2),
334 nSRAM_BE3 => SRAM_nBE(3),
335 nSRAM_WE => SRAM_nWE,
336 nSRAM_CE => SRAM_CE,
337 nSRAM_OE => SRAM_nOE,
338
339 spw1_din => SPW_NOM_DIN,
340 spw1_sin => SPW_NOM_SIN,
341 spw1_dout => SPW_NOM_DOUT,
342 spw1_sout => SPW_NOM_SOUT,
343 spw2_din => SPW_RED_DIN,
344 spw2_sin => SPW_RED_SIN,
345 spw2_dout => SPW_RED_DOUT,
346 spw2_sout => SPW_RED_SOUT,
347
348 bias_fail_sw => OPEN,
349
350 ADC_OEB_bar_CH => ADC_OEB_bar_CH,
351 ADC_smpclk => ADC_smpclk,
352 ADC_data => ADC_data,
353 HK_smpclk => HK_smpclk,
354 ADC_OEB_bar_HK => ADC_OEB_bar_HK,
355 HK_SEL => HK_SEL,
356
357 TAG8 => OPEN,
358 led => OPEN);
359
360 all_OEB_bar <= ADC_OEB_bar_HK & ADC_OEB_bar_CH;
361
362 WITH HK_SEL SELECT
363 HK_SEL_DATA <=
364 "00"&X"00F" WHEN "00",
365 "00"&X"01F" WHEN "01",
366 "00"&X"02F" WHEN "10",
367 "XXXXXXXXXXXXXX" WHEN OTHERS;
368
369 WITH all_OEB_bar SELECT
370 ADC_data <=
371 "00"&X"000" WHEN "111111110",
372 "00"&X"001" WHEN "111111101",
373 "00"&X"002" WHEN "111111011",
374 "00"&X"003" WHEN "111110111",
375 "00"&X"004" WHEN "111101111",
376 "00"&X"005" WHEN "111011111",
377 "00"&X"006" WHEN "110111111",
378 "00"&X"007" WHEN "101111111",
379 HK_SEL_DATA WHEN "011111111",
380 "XXXXXXXXXXXXXX" WHEN OTHERS;
381
382 END;
Show file before | Show file after | Hide comments
@@ -0,0 +1,28
1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -radix hexadecimal -childformat {{/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0 -radix hexadecimal -childformat {{/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(15) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(14) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(13) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(12) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(11) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(10) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(9) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(8) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(7) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(6) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(5) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(4) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(3) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(2) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(1) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(0) -radix hexadecimal}}} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_1 -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_2 -radix hexadecimal}} -expand -subitemconfig {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0 {-radix hexadecimal -childformat {{/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(15) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(14) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(13) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(12) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(11) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(10) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(9) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(8) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(7) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(6) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(5) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(4) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(3) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(2) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(1) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(0) -radix hexadecimal}}} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(15) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(14) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(13) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(12) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(11) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(10) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(9) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(8) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(7) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(6) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(5) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(4) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(3) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(2) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(1) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(0) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_1 {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_2 {-radix hexadecimal}} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk
4 add wave -noupdate /testbench/LFR_em_1/ADC_data
5 add wave -noupdate /testbench/LFR_em_1/ADC_data
6 add wave -noupdate /testbench/LFR_em_1/HK_SEL
7 add wave -noupdate /testbench/LFR_em_1/ADC_OEB_bar_HK
8 add wave -noupdate /testbench/LFR_em_1/HK_smpclk
9 add wave -noupdate /testbench/LFR_em_1/ADC_smpclk
10 add wave -noupdate /testbench/LFR_em_1/ADC_OEB_bar_CH
11 TreeUpdate [SetDefaultTree]
12 WaveRestoreCursors {{Cursor 1} {0 ps} 0}
13 quietly wave cursor active 0
14 configure wave -namecolwidth 233
15 configure wave -valuecolwidth 100
16 configure wave -justifyvalue left
17 configure wave -signalnamewidth 0
18 configure wave -snapdistance 10
19 configure wave -datasetprefix 0
20 configure wave -rowmargin 4
21 configure wave -childrowmargin 2
22 configure wave -gridoffset 0
23 configure wave -gridperiod 1
24 configure wave -griddelta 40
25 configure wave -timeline 0
26 configure wave -timelineunits ns
27 update
28 WaveRestoreZoom {934646651 ps} {1003439650 ps}
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