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Renamed design LFR-RTAX_keypoint into SOLO_LFR_LFR-FM...
Alexis Jeandet -
r667:f5c31dc5d20d default draft
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Thu Jun 04 11:49:44 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_pad_25/U0:Y }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_1:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_1:Y }
28
29
30 ######## Generated Clock Constraints ########
31
32
33
34 ######## Clock Source Latency Constraints #########
35
36
37
38 ######## Input Delay Constraints ########
39
40 set_input_delay -max 10.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
41
42 set_input_delay -max 10.000 -clock { clk_25:Q } [get_ports { ADC_data }]
43
44
45
46 ######## Output Delay Constraints ########
47
48 set_max_delay 25.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
49 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
50 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
51 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
52
53 set_max_delay 25.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
54 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
55 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
56 address[7] address[8] address[9] }]
57
58 set_max_delay 25.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W nSRAM_G nSRAM_MBE}]
59
60 set_max_delay 25.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH ADC_OEB_bar_HK }]
61
62 set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { DAC_SCK DAC_SDO DAC_SYNC }]
63
64
65 ######## Delay Constraints ########
66
67 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
68 [get_clocks {spw_inputloop.0.spw_phy0/rxclki_1_0:Y}]
69
70 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
71 [get_clocks {spw_inputloop.1.spw_phy0/rxclki_1_0:Y}]
72
73
74 ######## Delay Constraints ########
75
76
77
78 ######## Multicycle Constraints ########
79
80
81
82 ######## False Path Constraints ########
83
84
85
86 ######## Output load Constraints ########
87
88
89
90 ######## Disable Timing Constraints #########
91
92
93
94 ######## Clock Uncertainty Constraints #########
95
96
97
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1 NO CONTENT: file copied from boards/LFR-EQM/LFR_EQM_RTAX.pdc to boards/LFR-FM/LFR_FM_RTAX.pdc
NO CONTENT: file copied from boards/LFR-EQM/LFR_EQM_RTAX.pdc to boards/LFR-FM/LFR_FM_RTAX.pdc
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1 NO CONTENT: file copied from boards/LFR-EQM/LFR_EQM_RTAX_layout.sdc to boards/LFR-FM/LFR_FM_RTAX_layout.sdc
NO CONTENT: file copied from boards/LFR-EQM/LFR_EQM_RTAX_layout.sdc to boards/LFR-FM/LFR_FM_RTAX_layout.sdc
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1 NO CONTENT: file copied from boards/LFR-EQM/Makefile_RTAX.inc to boards/LFR-FM/Makefile_RTAX.inc
NO CONTENT: file copied from boards/LFR-EQM/Makefile_RTAX.inc to boards/LFR-FM/Makefile_RTAX.inc
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@@ -1,606 +1,606
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 USE techmap.axcomp.ALL;
30 USE techmap.axcomp.ALL;
31
31
32 LIBRARY gaisler;
32 LIBRARY gaisler;
33 USE gaisler.sim.ALL;
33 USE gaisler.sim.ALL;
34 USE gaisler.memctrl.ALL;
34 USE gaisler.memctrl.ALL;
35 USE gaisler.leon3.ALL;
35 USE gaisler.leon3.ALL;
36 USE gaisler.uart.ALL;
36 USE gaisler.uart.ALL;
37 USE gaisler.misc.ALL;
37 USE gaisler.misc.ALL;
38 USE gaisler.spacewire.ALL;
38 USE gaisler.spacewire.ALL;
39 LIBRARY esa;
39 LIBRARY esa;
40 USE esa.memoryctrl.ALL;
40 USE esa.memoryctrl.ALL;
41 LIBRARY lpp;
41 LIBRARY lpp;
42 USE lpp.lpp_memory.ALL;
42 USE lpp.lpp_memory.ALL;
43 USE lpp.lpp_ad_conv.ALL;
43 USE lpp.lpp_ad_conv.ALL;
44 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
44 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
45 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
45 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
46 USE lpp.iir_filter.ALL;
46 USE lpp.iir_filter.ALL;
47 USE lpp.general_purpose.ALL;
47 USE lpp.general_purpose.ALL;
48 USE lpp.lpp_lfr_management.ALL;
48 USE lpp.lpp_lfr_management.ALL;
49 USE lpp.lpp_leon3_soc_pkg.ALL;
49 USE lpp.lpp_leon3_soc_pkg.ALL;
50
50
51 --library proasic3l;
51 --library proasic3l;
52 --use proasic3l.all;
52 --use proasic3l.all;
53
53
54 ENTITY LFR_EQM IS
54 ENTITY LFR_FM IS
55 GENERIC (
55 GENERIC (
56 Mem_use : INTEGER := use_RAM;
56 Mem_use : INTEGER := use_RAM;
57 USE_BOOTLOADER : INTEGER := 0;
57 USE_BOOTLOADER : INTEGER := 0;
58 USE_ADCDRIVER : INTEGER := 1;
58 USE_ADCDRIVER : INTEGER := 1;
59 tech : INTEGER := inferred;
59 tech : INTEGER := inferred;
60 tech_leon : INTEGER := inferred;
60 tech_leon : INTEGER := inferred;
61 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
61 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
62 USE_DEBUG_VECTOR : INTEGER := 0
62 USE_DEBUG_VECTOR : INTEGER := 0
63 );
63 );
64
64
65 PORT (
65 PORT (
66 clk50MHz : IN STD_ULOGIC;
66 clk50MHz : IN STD_ULOGIC;
67 clk49_152MHz : IN STD_ULOGIC;
67 clk49_152MHz : IN STD_ULOGIC;
68 reset : IN STD_ULOGIC;
68 reset : IN STD_ULOGIC;
69
69
70 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
70 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
71
71
72 -- TAG --------------------------------------------------------------------
72 -- TAG --------------------------------------------------------------------
73 --TAG1 : IN STD_ULOGIC; -- DSU rx data
73 --TAG1 : IN STD_ULOGIC; -- DSU rx data
74 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
74 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
75 -- UART APB ---------------------------------------------------------------
75 -- UART APB ---------------------------------------------------------------
76 --TAG2 : IN STD_ULOGIC; -- UART1 rx data
76 --TAG2 : IN STD_ULOGIC; -- UART1 rx data
77 --TAG4 : OUT STD_ULOGIC; -- UART1 tx data
77 --TAG4 : OUT STD_ULOGIC; -- UART1 tx data
78 -- RAM --------------------------------------------------------------------
78 -- RAM --------------------------------------------------------------------
79 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
79 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
80 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81
81
82 nSRAM_MBE : INOUT STD_LOGIC; -- new
82 nSRAM_MBE : INOUT STD_LOGIC; -- new
83 nSRAM_E1 : OUT STD_LOGIC; -- new
83 nSRAM_E1 : OUT STD_LOGIC; -- new
84 nSRAM_E2 : OUT STD_LOGIC; -- new
84 nSRAM_E2 : OUT STD_LOGIC; -- new
85 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
85 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
86 nSRAM_W : OUT STD_LOGIC; -- new
86 nSRAM_W : OUT STD_LOGIC; -- new
87 nSRAM_G : OUT STD_LOGIC; -- new
87 nSRAM_G : OUT STD_LOGIC; -- new
88 nSRAM_BUSY : IN STD_LOGIC; -- new
88 nSRAM_BUSY : IN STD_LOGIC; -- new
89 -- SPW --------------------------------------------------------------------
89 -- SPW --------------------------------------------------------------------
90 spw1_en : OUT STD_LOGIC; -- new
90 spw1_en : OUT STD_LOGIC; -- new
91 spw1_din : IN STD_LOGIC;
91 spw1_din : IN STD_LOGIC;
92 spw1_sin : IN STD_LOGIC;
92 spw1_sin : IN STD_LOGIC;
93 spw1_dout : OUT STD_LOGIC;
93 spw1_dout : OUT STD_LOGIC;
94 spw1_sout : OUT STD_LOGIC;
94 spw1_sout : OUT STD_LOGIC;
95 spw2_en : OUT STD_LOGIC; -- new
95 spw2_en : OUT STD_LOGIC; -- new
96 spw2_din : IN STD_LOGIC;
96 spw2_din : IN STD_LOGIC;
97 spw2_sin : IN STD_LOGIC;
97 spw2_sin : IN STD_LOGIC;
98 spw2_dout : OUT STD_LOGIC;
98 spw2_dout : OUT STD_LOGIC;
99 spw2_sout : OUT STD_LOGIC;
99 spw2_sout : OUT STD_LOGIC;
100 -- ADC --------------------------------------------------------------------
100 -- ADC --------------------------------------------------------------------
101 bias_fail_sw : OUT STD_LOGIC;
101 bias_fail_sw : OUT STD_LOGIC;
102 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
102 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
103 ADC_smpclk : OUT STD_LOGIC;
103 ADC_smpclk : OUT STD_LOGIC;
104 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
104 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
105 -- DAC --------------------------------------------------------------------
105 -- DAC --------------------------------------------------------------------
106 DAC_SDO : OUT STD_LOGIC;
106 DAC_SDO : OUT STD_LOGIC;
107 DAC_SCK : OUT STD_LOGIC;
107 DAC_SCK : OUT STD_LOGIC;
108 DAC_SYNC : OUT STD_LOGIC;
108 DAC_SYNC : OUT STD_LOGIC;
109 DAC_CAL_EN : OUT STD_LOGIC;
109 DAC_CAL_EN : OUT STD_LOGIC;
110 -- HK ---------------------------------------------------------------------
110 -- HK ---------------------------------------------------------------------
111 HK_smpclk : OUT STD_LOGIC;
111 HK_smpclk : OUT STD_LOGIC;
112 ADC_OEB_bar_HK : OUT STD_LOGIC;
112 ADC_OEB_bar_HK : OUT STD_LOGIC;
113 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
113 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
114 );
114 );
115
115
116 END LFR_EQM;
116 END LFR_FM;
117
117
118
118
119 ARCHITECTURE beh OF LFR_EQM IS
119 ARCHITECTURE beh OF LFR_FM IS
120
120
121 SIGNAL clk_25_int : STD_LOGIC := '0';
121 SIGNAL clk_25_int : STD_LOGIC := '0';
122 SIGNAL clk_25 : STD_LOGIC := '0';
122 SIGNAL clk_25 : STD_LOGIC := '0';
123 SIGNAL clk_24 : STD_LOGIC := '0';
123 SIGNAL clk_24 : STD_LOGIC := '0';
124 -----------------------------------------------------------------------------
124 -----------------------------------------------------------------------------
125 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
125 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
126 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
127
127
128 -- CONSTANTS
128 -- CONSTANTS
129 CONSTANT CFG_PADTECH : INTEGER := inferred;
129 CONSTANT CFG_PADTECH : INTEGER := inferred;
130 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
130 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
131 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
131 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
132 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
132 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
133
133
134 SIGNAL apbi_ext : apb_slv_in_type;
134 SIGNAL apbi_ext : apb_slv_in_type;
135 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
135 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
136 SIGNAL ahbi_s_ext : ahb_slv_in_type;
136 SIGNAL ahbi_s_ext : ahb_slv_in_type;
137 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
137 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
138 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
138 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
139 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
139 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
140
140
141 -- Spacewire signals
141 -- Spacewire signals
142 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
142 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
143 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
143 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
144 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
144 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
145 SIGNAL swni : grspw_in_type;
145 SIGNAL swni : grspw_in_type;
146 SIGNAL swno : grspw_out_type;
146 SIGNAL swno : grspw_out_type;
147
147
148 --GPIO
148 --GPIO
149 SIGNAL gpioi : gpio_in_type;
149 SIGNAL gpioi : gpio_in_type;
150 SIGNAL gpioo : gpio_out_type;
150 SIGNAL gpioo : gpio_out_type;
151
151
152 -- AD Converter ADS7886
152 -- AD Converter ADS7886
153 SIGNAL sample : Samples14v(8 DOWNTO 0);
153 SIGNAL sample : Samples14v(8 DOWNTO 0);
154 SIGNAL sample_s : Samples(8 DOWNTO 0);
154 SIGNAL sample_s : Samples(8 DOWNTO 0);
155 SIGNAL sample_val : STD_LOGIC;
155 SIGNAL sample_val : STD_LOGIC;
156 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
156 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
157
157
158 -----------------------------------------------------------------------------
158 -----------------------------------------------------------------------------
159 SIGNAL LFR_rstn_int : STD_LOGIC := '0';
159 SIGNAL LFR_rstn_int : STD_LOGIC := '0';
160 SIGNAL rstn_25_int : STD_LOGIC := '0';
160 SIGNAL rstn_25_int : STD_LOGIC := '0';
161 SIGNAL rstn_25 : STD_LOGIC;
161 SIGNAL rstn_25 : STD_LOGIC;
162 SIGNAL rstn_24 : STD_LOGIC;
162 SIGNAL rstn_24 : STD_LOGIC;
163
163
164 SIGNAL LFR_soft_rstn : STD_LOGIC;
164 SIGNAL LFR_soft_rstn : STD_LOGIC;
165 SIGNAL LFR_rstn : STD_LOGIC;
165 SIGNAL LFR_rstn : STD_LOGIC;
166
166
167 SIGNAL ADC_smpclk_s : STD_LOGIC;
167 SIGNAL ADC_smpclk_s : STD_LOGIC;
168
168
169 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
169 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
170
170
171 SIGNAL clk50MHz_int : STD_LOGIC := '0';
171 SIGNAL clk50MHz_int : STD_LOGIC := '0';
172
172
173 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
173 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
174
174
175 SIGNAL rstn_50 : STD_LOGIC;
175 SIGNAL rstn_50 : STD_LOGIC;
176 SIGNAL clk_lock : STD_LOGIC;
176 SIGNAL clk_lock : STD_LOGIC;
177 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
177 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
178 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
178 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
179
179
180 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
180 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
181 SIGNAL ahbrxd: STD_LOGIC;
181 SIGNAL ahbrxd: STD_LOGIC;
182 SIGNAL ahbtxd: STD_LOGIC;
182 SIGNAL ahbtxd: STD_LOGIC;
183 SIGNAL urxd1 : STD_LOGIC;
183 SIGNAL urxd1 : STD_LOGIC;
184 SIGNAL utxd1 : STD_LOGIC;
184 SIGNAL utxd1 : STD_LOGIC;
185 BEGIN -- beh
185 BEGIN -- beh
186
186
187 -----------------------------------------------------------------------------
187 -----------------------------------------------------------------------------
188 -- CLK_LOCK
188 -- CLK_LOCK
189 -----------------------------------------------------------------------------
189 -----------------------------------------------------------------------------
190 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
190 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
191
191
192 PROCESS (clk50MHz_int, rstn_50)
192 PROCESS (clk50MHz_int, rstn_50)
193 BEGIN -- PROCESS
193 BEGIN -- PROCESS
194 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
194 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
195 clk_lock <= '0';
195 clk_lock <= '0';
196 clk_busy_counter <= (OTHERS => '0');
196 clk_busy_counter <= (OTHERS => '0');
197 nSRAM_BUSY_reg <= '0';
197 nSRAM_BUSY_reg <= '0';
198 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
198 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
199 nSRAM_BUSY_reg <= nSRAM_BUSY;
199 nSRAM_BUSY_reg <= nSRAM_BUSY;
200 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
200 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
201 IF clk_busy_counter = "1111" THEN
201 IF clk_busy_counter = "1111" THEN
202 clk_lock <= '1';
202 clk_lock <= '1';
203 ELSE
203 ELSE
204 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
204 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
205 END IF;
205 END IF;
206 END IF;
206 END IF;
207 END IF;
207 END IF;
208 END PROCESS;
208 END PROCESS;
209
209
210 -----------------------------------------------------------------------------
210 -----------------------------------------------------------------------------
211 -- CLK
211 -- CLK
212 -----------------------------------------------------------------------------
212 -----------------------------------------------------------------------------
213 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25_int, OPEN);
213 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25_int, OPEN);
214 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
214 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
215
215
216 rstn_pad_25 : clkint port map (A => rstn_25_int, Y => rstn_25 );
216 rstn_pad_25 : clkint port map (A => rstn_25_int, Y => rstn_25 );
217
217
218 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
218 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
219 clk50MHz_int <= clk50MHz;
219 clk50MHz_int <= clk50MHz;
220
220
221 PROCESS(clk50MHz_int)
221 PROCESS(clk50MHz_int)
222 BEGIN
222 BEGIN
223 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
223 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
224 clk_25_int <= NOT clk_25_int;
224 clk_25_int <= NOT clk_25_int;
225 --clk_25 <= NOT clk_25;
225 --clk_25 <= NOT clk_25;
226 END IF;
226 END IF;
227 END PROCESS;
227 END PROCESS;
228 clk_pad_25 : hclkint port map (A => clk_25_int, Y => clk_25 );
228 clk_pad_25 : hclkint port map (A => clk_25_int, Y => clk_25 );
229
229
230 PROCESS(clk49_152MHz)
230 PROCESS(clk49_152MHz)
231 BEGIN
231 BEGIN
232 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
232 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
233 clk_24 <= NOT clk_24;
233 clk_24 <= NOT clk_24;
234 END IF;
234 END IF;
235 END PROCESS;
235 END PROCESS;
236 -- clk_49 <= clk49_152MHz;
236 -- clk_49 <= clk49_152MHz;
237
237
238 -----------------------------------------------------------------------------
238 -----------------------------------------------------------------------------
239 leon3_soc_1 : leon3_soc
239 leon3_soc_1 : leon3_soc
240 GENERIC MAP (
240 GENERIC MAP (
241 fabtech => axcel,--inferred,--axdsp,
241 fabtech => axcel,--inferred,--axdsp,
242 memtech => axcel,--inferred,--tech_leon,
242 memtech => axcel,--inferred,--tech_leon,
243 padtech => axcel,--inferred,
243 padtech => axcel,--inferred,
244 clktech => axcel,--inferred,
244 clktech => axcel,--inferred,
245 disas => 0,
245 disas => 0,
246 dbguart => 0,
246 dbguart => 0,
247 pclow => 2,
247 pclow => 2,
248 clk_freq => 25000,
248 clk_freq => 25000,
249 IS_RADHARD => 1,
249 IS_RADHARD => 1,
250 NB_CPU => 1,
250 NB_CPU => 1,
251 ENABLE_FPU => 1,
251 ENABLE_FPU => 1,
252 FPU_NETLIST => 0,
252 FPU_NETLIST => 0,
253 ENABLE_DSU => 1,
253 ENABLE_DSU => 1,
254 ENABLE_AHB_UART => 0,
254 ENABLE_AHB_UART => 0,
255 ENABLE_APB_UART => 1,
255 ENABLE_APB_UART => 1,
256 ENABLE_IRQMP => 1,
256 ENABLE_IRQMP => 1,
257 ENABLE_GPT => 1,
257 ENABLE_GPT => 1,
258 NB_AHB_MASTER => NB_AHB_MASTER,
258 NB_AHB_MASTER => NB_AHB_MASTER,
259 NB_AHB_SLAVE => NB_AHB_SLAVE,
259 NB_AHB_SLAVE => NB_AHB_SLAVE,
260 NB_APB_SLAVE => NB_APB_SLAVE,
260 NB_APB_SLAVE => NB_APB_SLAVE,
261 ADDRESS_SIZE => 19,
261 ADDRESS_SIZE => 19,
262 USES_IAP_MEMCTRLR => 1,
262 USES_IAP_MEMCTRLR => 1,
263 USES_MBE_PIN => 1,
263 USES_MBE_PIN => 1,
264 BYPASS_EDAC_MEMCTRLR => '0',
264 BYPASS_EDAC_MEMCTRLR => '0',
265 SRBANKSZ => 8)
265 SRBANKSZ => 8)
266 PORT MAP (
266 PORT MAP (
267 clk => clk_25,
267 clk => clk_25,
268 reset => rstn_25,
268 reset => rstn_25,
269 errorn => OPEN,
269 errorn => OPEN,
270
270
271 ahbrxd => ahbrxd, -- INPUT
271 ahbrxd => ahbrxd, -- INPUT
272 ahbtxd => ahbtxd, -- OUTPUT
272 ahbtxd => ahbtxd, -- OUTPUT
273 urxd1 => urxd1, -- INPUT
273 urxd1 => urxd1, -- INPUT
274 utxd1 => utxd1, -- OUTPUT
274 utxd1 => utxd1, -- OUTPUT
275
275
276 address => address,
276 address => address,
277 data => data,
277 data => data,
278 nSRAM_BE0 => OPEN,
278 nSRAM_BE0 => OPEN,
279 nSRAM_BE1 => OPEN,
279 nSRAM_BE1 => OPEN,
280 nSRAM_BE2 => OPEN,
280 nSRAM_BE2 => OPEN,
281 nSRAM_BE3 => OPEN,
281 nSRAM_BE3 => OPEN,
282 nSRAM_WE => nSRAM_W,
282 nSRAM_WE => nSRAM_W,
283 nSRAM_CE => nSRAM_CE,
283 nSRAM_CE => nSRAM_CE,
284 nSRAM_OE => nSRAM_G,
284 nSRAM_OE => nSRAM_G,
285 nSRAM_READY => nSRAM_BUSY,
285 nSRAM_READY => nSRAM_BUSY,
286 SRAM_MBE => nSRAM_MBE,
286 SRAM_MBE => nSRAM_MBE,
287
287
288 apbi_ext => apbi_ext,
288 apbi_ext => apbi_ext,
289 apbo_ext => apbo_ext,
289 apbo_ext => apbo_ext,
290 ahbi_s_ext => ahbi_s_ext,
290 ahbi_s_ext => ahbi_s_ext,
291 ahbo_s_ext => ahbo_s_ext,
291 ahbo_s_ext => ahbo_s_ext,
292 ahbi_m_ext => ahbi_m_ext,
292 ahbi_m_ext => ahbi_m_ext,
293 ahbo_m_ext => ahbo_m_ext);
293 ahbo_m_ext => ahbo_m_ext);
294
294
295
295
296 nSRAM_E1 <= nSRAM_CE(0);
296 nSRAM_E1 <= nSRAM_CE(0);
297 nSRAM_E2 <= nSRAM_CE(1);
297 nSRAM_E2 <= nSRAM_CE(1);
298
298
299 -------------------------------------------------------------------------------
299 -------------------------------------------------------------------------------
300 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
300 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
301 -------------------------------------------------------------------------------
301 -------------------------------------------------------------------------------
302 apb_lfr_management_1 : apb_lfr_management
302 apb_lfr_management_1 : apb_lfr_management
303 GENERIC MAP (
303 GENERIC MAP (
304 tech => tech,
304 tech => tech,
305 pindex => 6,
305 pindex => 6,
306 paddr => 6,
306 paddr => 6,
307 pmask => 16#fff#,
307 pmask => 16#fff#,
308 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
308 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
309 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
309 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
310 PORT MAP (
310 PORT MAP (
311 clk25MHz => clk_25,
311 clk25MHz => clk_25,
312 resetn_25MHz => rstn_25, -- TODO
312 resetn_25MHz => rstn_25, -- TODO
313 --clk24_576MHz => clk_24, -- 49.152MHz/2
313 --clk24_576MHz => clk_24, -- 49.152MHz/2
314 --resetn_24_576MHz => rstn_24, -- TODO
314 --resetn_24_576MHz => rstn_24, -- TODO
315
315
316 grspw_tick => swno.tickout,
316 grspw_tick => swno.tickout,
317 apbi => apbi_ext,
317 apbi => apbi_ext,
318 apbo => apbo_ext(6),
318 apbo => apbo_ext(6),
319
319
320 HK_sample => sample_s(8),
320 HK_sample => sample_s(8),
321 HK_val => sample_val,
321 HK_val => sample_val,
322 HK_sel => HK_SEL,
322 HK_sel => HK_SEL,
323
323
324 DAC_SDO => DAC_SDO,
324 DAC_SDO => DAC_SDO,
325 DAC_SCK => DAC_SCK,
325 DAC_SCK => DAC_SCK,
326 DAC_SYNC => DAC_SYNC,
326 DAC_SYNC => DAC_SYNC,
327 DAC_CAL_EN => DAC_CAL_EN,
327 DAC_CAL_EN => DAC_CAL_EN,
328
328
329 coarse_time => coarse_time,
329 coarse_time => coarse_time,
330 fine_time => fine_time,
330 fine_time => fine_time,
331 LFR_soft_rstn => LFR_soft_rstn
331 LFR_soft_rstn => LFR_soft_rstn
332 );
332 );
333
333
334 -----------------------------------------------------------------------
334 -----------------------------------------------------------------------
335 --- SpaceWire --------------------------------------------------------
335 --- SpaceWire --------------------------------------------------------
336 -----------------------------------------------------------------------
336 -----------------------------------------------------------------------
337
337
338 ------------------------------------------------------------------------------
338 ------------------------------------------------------------------------------
339 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
339 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
340 ------------------------------------------------------------------------------
340 ------------------------------------------------------------------------------
341 spw1_en <= '1';
341 spw1_en <= '1';
342 spw2_en <= '1';
342 spw2_en <= '1';
343 ------------------------------------------------------------------------------
343 ------------------------------------------------------------------------------
344 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
344 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
345 ------------------------------------------------------------------------------
345 ------------------------------------------------------------------------------
346
346
347 --spw_clk <= clk50MHz;
347 --spw_clk <= clk50MHz;
348 --spw_rxtxclk <= spw_clk;
348 --spw_rxtxclk <= spw_clk;
349 --spw_rxclkn <= NOT spw_rxtxclk;
349 --spw_rxclkn <= NOT spw_rxtxclk;
350
350
351 -- PADS for SPW1
351 -- PADS for SPW1
352 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
352 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
353 PORT MAP (spw1_din, dtmp(0));
353 PORT MAP (spw1_din, dtmp(0));
354 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
354 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
355 PORT MAP (spw1_sin, stmp(0));
355 PORT MAP (spw1_sin, stmp(0));
356 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
356 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
357 PORT MAP (spw1_dout, swno.d(0));
357 PORT MAP (spw1_dout, swno.d(0));
358 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
358 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
359 PORT MAP (spw1_sout, swno.s(0));
359 PORT MAP (spw1_sout, swno.s(0));
360 -- PADS FOR SPW2
360 -- PADS FOR SPW2
361 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
361 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
362 PORT MAP (spw2_din, dtmp(1));
362 PORT MAP (spw2_din, dtmp(1));
363 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
363 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
364 PORT MAP (spw2_sin, stmp(1));
364 PORT MAP (spw2_sin, stmp(1));
365 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
365 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
366 PORT MAP (spw2_dout, swno.d(1));
366 PORT MAP (spw2_dout, swno.d(1));
367 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
367 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
368 PORT MAP (spw2_sout, swno.s(1));
368 PORT MAP (spw2_sout, swno.s(1));
369
369
370 -- GRSPW PHY
370 -- GRSPW PHY
371 --spw1_input: if CFG_SPW_GRSPW = 1 generate
371 --spw1_input: if CFG_SPW_GRSPW = 1 generate
372 spw_inputloop : FOR j IN 0 TO 1 GENERATE
372 spw_inputloop : FOR j IN 0 TO 1 GENERATE
373 spw_phy0 : grspw_phy
373 spw_phy0 : grspw_phy
374 GENERIC MAP(
374 GENERIC MAP(
375 tech => axcel,-- inferred,--axdsp,--tech_leon,
375 tech => axcel,-- inferred,--axdsp,--tech_leon,
376 rxclkbuftype => 1,
376 rxclkbuftype => 1,
377 scantest => 0)
377 scantest => 0)
378 PORT MAP(
378 PORT MAP(
379 rxrst => swno.rxrst,
379 rxrst => swno.rxrst,
380 di => dtmp(j),
380 di => dtmp(j),
381 si => stmp(j),
381 si => stmp(j),
382 rxclko => spw_rxclk(j),
382 rxclko => spw_rxclk(j),
383 do => swni.d(j),
383 do => swni.d(j),
384 ndo => swni.nd(j*5+4 DOWNTO j*5),
384 ndo => swni.nd(j*5+4 DOWNTO j*5),
385 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
385 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
386 END GENERATE spw_inputloop;
386 END GENERATE spw_inputloop;
387
387
388 -- SPW core
388 -- SPW core
389 sw0 : grspwm GENERIC MAP(
389 sw0 : grspwm GENERIC MAP(
390 tech => axcel,--inferred,--axdsp,--tech_leon,
390 tech => axcel,--inferred,--axdsp,--tech_leon,
391 hindex => 1,
391 hindex => 1,
392 pindex => 5,
392 pindex => 5,
393 paddr => 5,
393 paddr => 5,
394 pirq => 11,
394 pirq => 11,
395 sysfreq => 25000, -- CPU_FREQ
395 sysfreq => 25000, -- CPU_FREQ
396 rmap => 1,
396 rmap => 1,
397 rmapcrc => 1,
397 rmapcrc => 1,
398 fifosize1 => 16,
398 fifosize1 => 16,
399 fifosize2 => 16,
399 fifosize2 => 16,
400 rxclkbuftype => 1,
400 rxclkbuftype => 1,
401 rxunaligned => 0,
401 rxunaligned => 0,
402 rmapbufs => 4,
402 rmapbufs => 4,
403 ft => 1,
403 ft => 1,
404 netlist => 0,
404 netlist => 0,
405 ports => 2,
405 ports => 2,
406 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
406 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
407 memtech => axcel,--inferred,--tech_leon,
407 memtech => axcel,--inferred,--tech_leon,
408 destkey => 2,
408 destkey => 2,
409 spwcore => 1
409 spwcore => 1
410 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
410 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
411 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
411 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
412 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
412 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
413 )
413 )
414 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
414 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
415 spw_rxclk(1),
415 spw_rxclk(1),
416 clk50MHz_int,
416 clk50MHz_int,
417 clk50MHz_int,
417 clk50MHz_int,
418 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
418 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
419 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
419 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
420 swni, swno);
420 swni, swno);
421
421
422 swni.tickin <= '0';
422 swni.tickin <= '0';
423 swni.rmapen <= '1';
423 swni.rmapen <= '1';
424 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
424 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
425 swni.tickinraw <= '0';
425 swni.tickinraw <= '0';
426 swni.timein <= (OTHERS => '0');
426 swni.timein <= (OTHERS => '0');
427 swni.dcrstval <= (OTHERS => '0');
427 swni.dcrstval <= (OTHERS => '0');
428 swni.timerrstval <= (OTHERS => '0');
428 swni.timerrstval <= (OTHERS => '0');
429
429
430 -------------------------------------------------------------------------------
430 -------------------------------------------------------------------------------
431 -- LFR ------------------------------------------------------------------------
431 -- LFR ------------------------------------------------------------------------
432 -------------------------------------------------------------------------------
432 -------------------------------------------------------------------------------
433 --rst_domain25_lfr : rstgen PORT MAP (LFR_soft_rstn, clk_25, clk_lock, LFR_rstn, OPEN);
433 --rst_domain25_lfr : rstgen PORT MAP (LFR_soft_rstn, clk_25, clk_lock, LFR_rstn, OPEN);
434 LFR_rstn_int <= LFR_soft_rstn AND rstn_25_int;
434 LFR_rstn_int <= LFR_soft_rstn AND rstn_25_int;
435
435
436 rstn_pad_lfr : clkint port map (A => LFR_rstn_int, Y => LFR_rstn );
436 rstn_pad_lfr : clkint port map (A => LFR_rstn_int, Y => LFR_rstn );
437
437
438 lpp_lfr_1 : lpp_lfr
438 lpp_lfr_1 : lpp_lfr
439 GENERIC MAP (
439 GENERIC MAP (
440 Mem_use => Mem_use,
440 Mem_use => Mem_use,
441 tech => inferred,--tech,
441 tech => inferred,--tech,
442 nb_data_by_buffer_size => 32,
442 nb_data_by_buffer_size => 32,
443 --nb_word_by_buffer_size => 30,
443 --nb_word_by_buffer_size => 30,
444 nb_snapshot_param_size => 32,
444 nb_snapshot_param_size => 32,
445 delta_vector_size => 32,
445 delta_vector_size => 32,
446 delta_vector_size_f0_2 => 7, -- log2(96)
446 delta_vector_size_f0_2 => 7, -- log2(96)
447 pindex => 15,
447 pindex => 15,
448 paddr => 15,
448 paddr => 15,
449 pmask => 16#fff#,
449 pmask => 16#fff#,
450 pirq_ms => 6,
450 pirq_ms => 6,
451 pirq_wfp => 14,
451 pirq_wfp => 14,
452 hindex => 2,
452 hindex => 2,
453 top_lfr_version => X"030159", -- aa.bb.cc version
453 top_lfr_version => X"030159", -- aa.bb.cc version
454 -- AA : BOARD NUMBER
454 -- AA : BOARD NUMBER
455 -- 0 => MINI_LFR
455 -- 0 => MINI_LFR
456 -- 1 => EM
456 -- 1 => EM
457 -- 2 => EQM (with A3PE3000)
457 -- 2 => EQM (with A3PE3000)
458 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA,
458 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA,
459 RTL_DESIGN_LIGHT =>0,
459 RTL_DESIGN_LIGHT =>0,
460 WINDOWS_HAANNING_PARAM_SIZE => 15)
460 WINDOWS_HAANNING_PARAM_SIZE => 15)
461 PORT MAP (
461 PORT MAP (
462 clk => clk_25,
462 clk => clk_25,
463 rstn => LFR_rstn,
463 rstn => LFR_rstn,
464 sample_B => sample_s(2 DOWNTO 0),
464 sample_B => sample_s(2 DOWNTO 0),
465 sample_E => sample_s(7 DOWNTO 3),
465 sample_E => sample_s(7 DOWNTO 3),
466 sample_val => sample_val,
466 sample_val => sample_val,
467 apbi => apbi_ext,
467 apbi => apbi_ext,
468 apbo => apbo_ext(15),
468 apbo => apbo_ext(15),
469 ahbi => ahbi_m_ext,
469 ahbi => ahbi_m_ext,
470 ahbo => ahbo_m_ext(2),
470 ahbo => ahbo_m_ext(2),
471 coarse_time => coarse_time,
471 coarse_time => coarse_time,
472 fine_time => fine_time,
472 fine_time => fine_time,
473 data_shaping_BW => bias_fail_sw,
473 data_shaping_BW => bias_fail_sw,
474 debug_vector => debug_vector,
474 debug_vector => debug_vector,
475 debug_vector_ms => OPEN); --,
475 debug_vector_ms => OPEN); --,
476 --observation_vector_0 => OPEN,
476 --observation_vector_0 => OPEN,
477 --observation_vector_1 => OPEN,
477 --observation_vector_1 => OPEN,
478 --observation_reg => observation_reg);
478 --observation_reg => observation_reg);
479
479
480
480
481 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
481 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
482 sample_s(I) <= sample(I) & '0' & '0';
482 sample_s(I) <= sample(I) & '0' & '0';
483 END GENERATE all_sample;
483 END GENERATE all_sample;
484 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
484 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
485
485
486 -----------------------------------------------------------------------------
486 -----------------------------------------------------------------------------
487 --
487 --
488 -----------------------------------------------------------------------------
488 -----------------------------------------------------------------------------
489 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
489 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
490 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
490 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
491 GENERIC MAP (
491 GENERIC MAP (
492 ChanelCount => 9,
492 ChanelCount => 9,
493 ncycle_cnv_high => 12,
493 ncycle_cnv_high => 12,
494 ncycle_cnv => 25,
494 ncycle_cnv => 25,
495 FILTER_ENABLED => 16#FF#)
495 FILTER_ENABLED => 16#FF#)
496 PORT MAP (
496 PORT MAP (
497 cnv_clk => clk_24,
497 cnv_clk => clk_24,
498 cnv_rstn => rstn_24,
498 cnv_rstn => rstn_24,
499 cnv => ADC_smpclk_s,
499 cnv => ADC_smpclk_s,
500 clk => clk_25,
500 clk => clk_25,
501 rstn => rstn_25,
501 rstn => rstn_25,
502 ADC_data => ADC_data,
502 ADC_data => ADC_data,
503 ADC_nOE => ADC_OEB_bar_CH_s,
503 ADC_nOE => ADC_OEB_bar_CH_s,
504 sample => sample,
504 sample => sample,
505 sample_val => sample_val);
505 sample_val => sample_val);
506
506
507 END GENERATE USE_ADCDRIVER_true;
507 END GENERATE USE_ADCDRIVER_true;
508
508
509 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
509 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
510 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
510 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
511 GENERIC MAP (
511 GENERIC MAP (
512 ChanelCount => 9,
512 ChanelCount => 9,
513 ncycle_cnv_high => 25,
513 ncycle_cnv_high => 25,
514 ncycle_cnv => 50,
514 ncycle_cnv => 50,
515 FILTER_ENABLED => 16#FF#)
515 FILTER_ENABLED => 16#FF#)
516 PORT MAP (
516 PORT MAP (
517 cnv_clk => clk_24,
517 cnv_clk => clk_24,
518 cnv_rstn => rstn_24,
518 cnv_rstn => rstn_24,
519 cnv => ADC_smpclk_s,
519 cnv => ADC_smpclk_s,
520 clk => clk_25,
520 clk => clk_25,
521 rstn => rstn_25,
521 rstn => rstn_25,
522 ADC_data => ADC_data,
522 ADC_data => ADC_data,
523 ADC_nOE => OPEN,
523 ADC_nOE => OPEN,
524 sample => OPEN,
524 sample => OPEN,
525 sample_val => sample_val);
525 sample_val => sample_val);
526
526
527 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
527 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
528
528
529 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
529 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
530 ramp_generator_1: ramp_generator
530 ramp_generator_1: ramp_generator
531 GENERIC MAP (
531 GENERIC MAP (
532 DATA_SIZE => 14,
532 DATA_SIZE => 14,
533 VALUE_UNSIGNED_INIT => 2**I,
533 VALUE_UNSIGNED_INIT => 2**I,
534 VALUE_UNSIGNED_INCR => 0,
534 VALUE_UNSIGNED_INCR => 0,
535 VALUE_UNSIGNED_MASK => 16#3FFF#)
535 VALUE_UNSIGNED_MASK => 16#3FFF#)
536 PORT MAP (
536 PORT MAP (
537 clk => clk_25,
537 clk => clk_25,
538 rstn => rstn_25,
538 rstn => rstn_25,
539 new_data => sample_val,
539 new_data => sample_val,
540 output_data => sample(I) );
540 output_data => sample(I) );
541 END GENERATE all_sample;
541 END GENERATE all_sample;
542
542
543
543
544 END GENERATE USE_ADCDRIVER_false;
544 END GENERATE USE_ADCDRIVER_false;
545
545
546
546
547
547
548
548
549 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
549 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
550
550
551 ADC_smpclk <= ADC_smpclk_s;
551 ADC_smpclk <= ADC_smpclk_s;
552 HK_smpclk <= ADC_smpclk_s;
552 HK_smpclk <= ADC_smpclk_s;
553
553
554
554
555 -----------------------------------------------------------------------------
555 -----------------------------------------------------------------------------
556 -- HK
556 -- HK
557 -----------------------------------------------------------------------------
557 -----------------------------------------------------------------------------
558 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
558 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
559
559
560 -----------------------------------------------------------------------------
560 -----------------------------------------------------------------------------
561 --
561 --
562 -----------------------------------------------------------------------------
562 -----------------------------------------------------------------------------
563 --inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
563 --inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
564 -- lpp_bootloader_1: lpp_bootloader
564 -- lpp_bootloader_1: lpp_bootloader
565 -- GENERIC MAP (
565 -- GENERIC MAP (
566 -- pindex => 13,
566 -- pindex => 13,
567 -- paddr => 13,
567 -- paddr => 13,
568 -- pmask => 16#fff#,
568 -- pmask => 16#fff#,
569 -- hindex => 3,
569 -- hindex => 3,
570 -- haddr => 0,
570 -- haddr => 0,
571 -- hmask => 16#fff#)
571 -- hmask => 16#fff#)
572 -- PORT MAP (
572 -- PORT MAP (
573 -- HCLK => clk_25,
573 -- HCLK => clk_25,
574 -- HRESETn => rstn_25,
574 -- HRESETn => rstn_25,
575 -- apbi => apbi_ext,
575 -- apbi => apbi_ext,
576 -- apbo => apbo_ext(13),
576 -- apbo => apbo_ext(13),
577 -- ahbsi => ahbi_s_ext,
577 -- ahbsi => ahbi_s_ext,
578 -- ahbso => ahbo_s_ext(3));
578 -- ahbso => ahbo_s_ext(3));
579 --END GENERATE inst_bootloader;
579 --END GENERATE inst_bootloader;
580
580
581 -----------------------------------------------------------------------------
581 -----------------------------------------------------------------------------
582 --
582 --
583 -----------------------------------------------------------------------------
583 -----------------------------------------------------------------------------
584 USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
584 USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
585 PROCESS (clk_25, rstn_25)
585 PROCESS (clk_25, rstn_25)
586 BEGIN -- PROCESS
586 BEGIN -- PROCESS
587 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
587 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
588 TAG <= (OTHERS => '0');
588 TAG <= (OTHERS => '0');
589 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
589 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
590 TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
590 TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
591 END IF;
591 END IF;
592 END PROCESS;
592 END PROCESS;
593
593
594
594
595 END GENERATE USE_DEBUG_VECTOR_IF;
595 END GENERATE USE_DEBUG_VECTOR_IF;
596
596
597 USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
597 USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
598 --ahbrxd <= TAG(1); -- AHB UART
598 --ahbrxd <= TAG(1); -- AHB UART
599 --TAG(3) <= ahbtxd;
599 --TAG(3) <= ahbtxd;
600
600
601 urxd1 <= TAG(2); -- APB UART
601 urxd1 <= TAG(2); -- APB UART
602 TAG(4) <= utxd1;
602 TAG(4) <= utxd1;
603 --TAG(8) <= nSRAM_BUSY;
603 --TAG(8) <= nSRAM_BUSY;
604 END GENERATE USE_DEBUG_VECTOR_IF2;
604 END GENERATE USE_DEBUG_VECTOR_IF2;
605
605
606 END beh;
606 END beh;
Show file before | Show file after | Hide comments
@@ -1,55 +1,55
1 VHDLIB=../..
1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4
4
5 TOP=LFR_EQM
5 TOP=LFR_FM
6 BOARD=LFR-EQM
6 BOARD=LFR-FM
7
7
8 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
8 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
9
9
10 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
10 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
11 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
11 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
12 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
12 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
13 EFFORT=high
13 EFFORT=high
14 XSTOPT=
14 XSTOPT=
15
15
16 VHDLSYNFILES=LFR-EQM.vhd
16 VHDLSYNFILES=LFR-FM.vhd
17 VHDLSIMFILES=testbench.vhd
17 VHDLSIMFILES=
18
18
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_FM_RTAX.pdc
20 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc
20 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc
21
21
22 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
22 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
23 CLEAN=soft-clean
23 CLEAN=soft-clean
24
24
25 TECHLIBS = axcelerator
25 TECHLIBS = axcelerator
26
26
27 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
28 tmtc openchip hynix ihp gleichmann micron usbhc ge_1000baseX
28 tmtc openchip hynix ihp gleichmann micron usbhc ge_1000baseX
29
29
30 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
30 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
31 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
31 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
32 ./amba_lcd_16x2_ctrlr \
32 ./amba_lcd_16x2_ctrlr \
33 ./general_purpose/lpp_AMR \
33 ./general_purpose/lpp_AMR \
34 ./general_purpose/lpp_balise \
34 ./general_purpose/lpp_balise \
35 ./general_purpose/lpp_delay \
35 ./general_purpose/lpp_delay \
36 ./lpp_bootloader \
36 ./lpp_bootloader \
37 ./dsp/lpp_fft \
37 ./dsp/lpp_fft \
38 ./lpp_uart \
38 ./lpp_uart \
39 ./lpp_usb \
39 ./lpp_usb \
40 ./lpp_sim/CY7C1061DV33 \
40 ./lpp_sim/CY7C1061DV33 \
41
41
42 FILESKIP = i2cmst.vhd \
42 FILESKIP = i2cmst.vhd \
43 APB_MULTI_DIODE.vhd \
43 APB_MULTI_DIODE.vhd \
44 APB_MULTI_DIODE.vhd \
44 APB_MULTI_DIODE.vhd \
45 Top_MatrixSpec.vhd \
45 Top_MatrixSpec.vhd \
46 APB_FFT.vhd\
46 APB_FFT.vhd\
47 CoreFFT_simu.vhd \
47 CoreFFT_simu.vhd \
48 lpp_lfr_apbreg_simu.vhd \
48 lpp_lfr_apbreg_simu.vhd \
49 sgmii.vhd
49 sgmii.vhd
50
50
51 include $(GRLIB)/bin/Makefile
51 include $(GRLIB)/bin/Makefile
52 include $(GRLIB)/software/leon3/Makefile
52 include $(GRLIB)/software/leon3/Makefile
53
53
54 ################## project specific targets ##########################
54 ################## project specific targets ##########################
55
55
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