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custom dma : update transition's condition between FSM state "ARBITER" and "CTRL"
pellion -
r580:f4e8c3120b82 simu_with_Leon3
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 USE gaisler.sim.ALL;
31 32 USE gaisler.memctrl.ALL;
32 33 USE gaisler.leon3.ALL;
33 34 USE gaisler.uart.ALL;
34 35 USE gaisler.misc.ALL;
35 36 USE gaisler.spacewire.ALL;
36 37 LIBRARY esa;
37 38 USE esa.memoryctrl.ALL;
38 39 LIBRARY lpp;
39 40 USE lpp.lpp_memory.ALL;
40 41 USE lpp.lpp_ad_conv.ALL;
41 42 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 43 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 44 USE lpp.iir_filter.ALL;
44 45 USE lpp.general_purpose.ALL;
45 46 USE lpp.lpp_lfr_management.ALL;
46 47 USE lpp.lpp_leon3_soc_pkg.ALL;
48 USE lpp.lpp_bootloader_pkg.ALL;
47 49
48 50 --library proasic3l;
49 51 --use proasic3l.all;
50 52
51 53 ENTITY LFR_EQM IS
52 --GENERIC (
53 -- Mem_use : INTEGER := use_RAM);
54 GENERIC (
55 Mem_use : INTEGER := use_RAM;
56 USE_BOOTLOADER : INTEGER := 0
57 );
54 58
55 59 PORT (
56 60 clk50MHz : IN STD_ULOGIC;
57 61 clk49_152MHz : IN STD_ULOGIC;
58 62 reset : IN STD_ULOGIC;
59 63
60 64 -- TAG --------------------------------------------------------------------
61 65 TAG1 : IN STD_ULOGIC; -- DSU rx data
62 66 TAG3 : OUT STD_ULOGIC; -- DSU tx data
63 67 -- UART APB ---------------------------------------------------------------
64 68 TAG2 : IN STD_ULOGIC; -- UART1 rx data
65 69 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
66 70 -- RAM --------------------------------------------------------------------
67 71 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
68 72 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
69 73
70 74 nSRAM_MBE : INOUT STD_LOGIC; -- new
71 75 nSRAM_E1 : OUT STD_LOGIC; -- new
72 76 nSRAM_E2 : OUT STD_LOGIC; -- new
73 77 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
74 78 nSRAM_W : OUT STD_LOGIC; -- new
75 79 nSRAM_G : OUT STD_LOGIC; -- new
76 80 nSRAM_BUSY : IN STD_LOGIC; -- new
77 81 -- SPW --------------------------------------------------------------------
78 82 spw1_en : OUT STD_LOGIC; -- new
79 83 spw1_din : IN STD_LOGIC;
80 84 spw1_sin : IN STD_LOGIC;
81 85 spw1_dout : OUT STD_LOGIC;
82 86 spw1_sout : OUT STD_LOGIC;
83 87 spw2_en : OUT STD_LOGIC; -- new
84 88 spw2_din : IN STD_LOGIC;
85 89 spw2_sin : IN STD_LOGIC;
86 90 spw2_dout : OUT STD_LOGIC;
87 91 spw2_sout : OUT STD_LOGIC;
88 92 -- ADC --------------------------------------------------------------------
89 93 bias_fail_sw : OUT STD_LOGIC;
90 94 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
91 95 ADC_smpclk : OUT STD_LOGIC;
92 96 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
93 97 -- DAC --------------------------------------------------------------------
94 98 DAC_SDO : OUT STD_LOGIC;
95 99 DAC_SCK : OUT STD_LOGIC;
96 100 DAC_SYNC : OUT STD_LOGIC;
97 101 DAC_CAL_EN : OUT STD_LOGIC;
98 102 -- HK ---------------------------------------------------------------------
99 103 HK_smpclk : OUT STD_LOGIC;
100 104 ADC_OEB_bar_HK : OUT STD_LOGIC;
101 105 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
102 106 ---------------------------------------------------------------------------
103 107 TAG8 : OUT STD_LOGIC
104 108 );
105 109
106 110 END LFR_EQM;
107 111
108 112
109 113 ARCHITECTURE beh OF LFR_EQM IS
110 114
111 115 SIGNAL clk_25 : STD_LOGIC := '0';
112 116 SIGNAL clk_24 : STD_LOGIC := '0';
113 117 -----------------------------------------------------------------------------
114 118 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
115 119 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
116 120
117 121 -- CONSTANTS
118 122 CONSTANT CFG_PADTECH : INTEGER := inferred;
119 123 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
120 124 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
121 125 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
122 126
123 127 SIGNAL apbi_ext : apb_slv_in_type;
124 128 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
125 129 SIGNAL ahbi_s_ext : ahb_slv_in_type;
126 130 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
127 131 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
128 132 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
129 133
130 134 -- Spacewire signals
131 135 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
132 136 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
133 137 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
134 138 SIGNAL spw_rxtxclk : STD_ULOGIC;
135 139 SIGNAL spw_rxclkn : STD_ULOGIC;
136 140 SIGNAL spw_clk : STD_LOGIC;
137 141 SIGNAL swni : grspw_in_type;
138 142 SIGNAL swno : grspw_out_type;
139 143
140 144 --GPIO
141 145 SIGNAL gpioi : gpio_in_type;
142 146 SIGNAL gpioo : gpio_out_type;
143 147
144 148 -- AD Converter ADS7886
145 149 SIGNAL sample : Samples14v(8 DOWNTO 0);
146 150 SIGNAL sample_s : Samples(8 DOWNTO 0);
147 151 SIGNAL sample_val : STD_LOGIC;
148 152 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
149 153
150 154 -----------------------------------------------------------------------------
151 155 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 156
153 157 -----------------------------------------------------------------------------
154 158 SIGNAL rstn_25 : STD_LOGIC;
155 159 SIGNAL rstn_24 : STD_LOGIC;
156 160
157 161 SIGNAL LFR_soft_rstn : STD_LOGIC;
158 162 SIGNAL LFR_rstn : STD_LOGIC;
159 163
160 164 SIGNAL ADC_smpclk_s : STD_LOGIC;
161 165
162 166 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
163 167
164 168 SIGNAL clk50MHz_int : STD_LOGIC := '0';
165 169 SIGNAL clk_25_int : STD_LOGIC := '0';
166 170
167 171 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
168 172
169 173 BEGIN -- beh
170 174
171 175 -----------------------------------------------------------------------------
172 176 -- CLK
173 177 -----------------------------------------------------------------------------
174 178 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
175 179 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
176 180
177 181 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
178 182 clk50MHz_int <= clk50MHz;
179 183
180 184 PROCESS(clk50MHz_int)
181 185 BEGIN
182 186 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
183 187 --clk_25_int <= NOT clk_25_int;
184 188 clk_25 <= NOT clk_25;
185 189 END IF;
186 190 END PROCESS;
187 191 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
188 192
189 193 PROCESS(clk49_152MHz)
190 194 BEGIN
191 195 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
192 196 clk_24 <= NOT clk_24;
193 197 END IF;
194 198 END PROCESS;
195 199
196 200 -----------------------------------------------------------------------------
197 201 --
198 202 leon3_soc_1 : leon3_soc
199 203 GENERIC MAP (
200 204 fabtech => apa3l,
201 205 memtech => apa3l,
202 206 padtech => inferred,
203 207 clktech => inferred,
204 208 disas => 0,
205 209 dbguart => 0,
206 210 pclow => 2,
207 211 clk_freq => 25000,
208 212 IS_RADHARD => 0,
209 213 NB_CPU => 1,
210 214 ENABLE_FPU => 1,
211 215 FPU_NETLIST => 0,
212 216 ENABLE_DSU => 1,
213 217 ENABLE_AHB_UART => 1,
214 218 ENABLE_APB_UART => 1,
215 219 ENABLE_IRQMP => 1,
216 220 ENABLE_GPT => 1,
217 221 NB_AHB_MASTER => NB_AHB_MASTER,
218 222 NB_AHB_SLAVE => NB_AHB_SLAVE,
219 223 NB_APB_SLAVE => NB_APB_SLAVE,
220 224 ADDRESS_SIZE => 19,
221 225 USES_IAP_MEMCTRLR => 1,
222 226 BYPASS_EDAC_MEMCTRLR => '0',
223 227 SRBANKSZ => 8)
224 228 PORT MAP (
225 229 clk => clk_25,
226 230 reset => rstn_25,
227 231 errorn => OPEN,
228 232
229 233 ahbrxd => TAG1,
230 234 ahbtxd => TAG3,
231 235 urxd1 => TAG2,
232 236 utxd1 => TAG4,
233 237
234 238 address => address,
235 239 data => data,
236 240 nSRAM_BE0 => OPEN,
237 241 nSRAM_BE1 => OPEN,
238 242 nSRAM_BE2 => OPEN,
239 243 nSRAM_BE3 => OPEN,
240 244 nSRAM_WE => nSRAM_W,
241 245 nSRAM_CE => nSRAM_CE,
242 246 nSRAM_OE => nSRAM_G,
243 247 nSRAM_READY => nSRAM_BUSY,
244 248 SRAM_MBE => nSRAM_MBE,
245 249
246 250 apbi_ext => apbi_ext,
247 251 apbo_ext => apbo_ext,
248 252 ahbi_s_ext => ahbi_s_ext,
249 253 ahbo_s_ext => ahbo_s_ext,
250 254 ahbi_m_ext => ahbi_m_ext,
251 255 ahbo_m_ext => ahbo_m_ext);
252 256
253 257
254 258 nSRAM_E1 <= nSRAM_CE(0);
255 259 nSRAM_E2 <= nSRAM_CE(1);
256 260
257 261 -------------------------------------------------------------------------------
258 262 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
259 263 -------------------------------------------------------------------------------
260 264 apb_lfr_management_1 : apb_lfr_management
261 265 GENERIC MAP (
262 266 tech => apa3l,
263 267 pindex => 6,
264 268 paddr => 6,
265 269 pmask => 16#fff#,
266 270 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
267 271 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
268 272 PORT MAP (
269 273 clk25MHz => clk_25,
270 274 resetn_25MHz => rstn_25, -- TODO
271 275 --clk24_576MHz => clk_24, -- 49.152MHz/2
272 276 --resetn_24_576MHz => rstn_24, -- TODO
273 277
274 278 grspw_tick => swno.tickout,
275 279 apbi => apbi_ext,
276 280 apbo => apbo_ext(6),
277 281
278 282 HK_sample => sample_s(8),
279 283 HK_val => sample_val,
280 284 HK_sel => HK_SEL,
281 285
282 286 DAC_SDO => DAC_SDO,
283 287 DAC_SCK => DAC_SCK,
284 288 DAC_SYNC => DAC_SYNC,
285 289 DAC_CAL_EN => DAC_CAL_EN,
286 290
287 291 coarse_time => coarse_time,
288 292 fine_time => fine_time,
289 293 LFR_soft_rstn => LFR_soft_rstn
290 294 );
291 295
292 296 -----------------------------------------------------------------------
293 297 --- SpaceWire --------------------------------------------------------
294 298 -----------------------------------------------------------------------
295 299
296 300 ------------------------------------------------------------------------------
297 301 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
298 302 ------------------------------------------------------------------------------
299 303 spw1_en <= '1';
300 304 spw2_en <= '1';
301 305 ------------------------------------------------------------------------------
302 306 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
303 307 ------------------------------------------------------------------------------
304 308
305 309 --spw_clk <= clk50MHz;
306 310 --spw_rxtxclk <= spw_clk;
307 311 --spw_rxclkn <= NOT spw_rxtxclk;
308 312
309 313 -- PADS for SPW1
310 314 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
311 315 PORT MAP (spw1_din, dtmp(0));
312 316 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
313 317 PORT MAP (spw1_sin, stmp(0));
314 318 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
315 319 PORT MAP (spw1_dout, swno.d(0));
316 320 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
317 321 PORT MAP (spw1_sout, swno.s(0));
318 322 -- PADS FOR SPW2
319 323 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
320 324 PORT MAP (spw2_din, dtmp(1));
321 325 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
322 326 PORT MAP (spw2_sin, stmp(1));
323 327 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
324 328 PORT MAP (spw2_dout, swno.d(1));
325 329 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
326 330 PORT MAP (spw2_sout, swno.s(1));
327 331
328 332 -- GRSPW PHY
329 333 --spw1_input: if CFG_SPW_GRSPW = 1 generate
330 334 spw_inputloop : FOR j IN 0 TO 1 GENERATE
331 335 spw_phy0 : grspw_phy
332 336 GENERIC MAP(
333 337 tech => apa3l,
334 338 rxclkbuftype => 1,
335 339 scantest => 0)
336 340 PORT MAP(
337 341 rxrst => swno.rxrst,
338 342 di => dtmp(j),
339 343 si => stmp(j),
340 344 rxclko => spw_rxclk(j),
341 345 do => swni.d(j),
342 346 ndo => swni.nd(j*5+4 DOWNTO j*5),
343 347 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
344 348 END GENERATE spw_inputloop;
345 349
346 350 -- SPW core
347 351 sw0 : grspwm GENERIC MAP(
348 352 tech => apa3l,
349 353 hindex => 1,
350 354 pindex => 5,
351 355 paddr => 5,
352 356 pirq => 11,
353 357 sysfreq => 25000, -- CPU_FREQ
354 358 rmap => 1,
355 359 rmapcrc => 1,
356 360 fifosize1 => 16,
357 361 fifosize2 => 16,
358 362 rxclkbuftype => 1,
359 363 rxunaligned => 0,
360 364 rmapbufs => 4,
361 365 ft => 0,
362 366 netlist => 0,
363 367 ports => 2,
364 368 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
365 369 memtech => apa3l,
366 370 destkey => 2,
367 371 spwcore => 1
368 372 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
369 373 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
370 374 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
371 375 )
372 376 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
373 377 spw_rxclk(1),
374 378 clk50MHz_int,
375 379 clk50MHz_int,
376 380 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
377 381 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
378 382 swni, swno);
379 383
380 384 swni.tickin <= '0';
381 385 swni.rmapen <= '1';
382 386 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
383 387 swni.tickinraw <= '0';
384 388 swni.timein <= (OTHERS => '0');
385 389 swni.dcrstval <= (OTHERS => '0');
386 390 swni.timerrstval <= (OTHERS => '0');
387 391
388 392 -------------------------------------------------------------------------------
389 393 -- LFR ------------------------------------------------------------------------
390 394 -------------------------------------------------------------------------------
391 395 LFR_rstn <= LFR_soft_rstn AND rstn_25;
392 396
393 397 lpp_lfr_1 : lpp_lfr
394 398 GENERIC MAP (
395 Mem_use => use_RAM,
399 Mem_use => Mem_use,
396 400 nb_data_by_buffer_size => 32,
397 401 --nb_word_by_buffer_size => 30,
398 402 nb_snapshot_param_size => 32,
399 403 delta_vector_size => 32,
400 404 delta_vector_size_f0_2 => 7, -- log2(96)
401 405 pindex => 15,
402 406 paddr => 15,
403 407 pmask => 16#fff#,
404 408 pirq_ms => 6,
405 409 pirq_wfp => 14,
406 410 hindex => 2,
407 411 top_lfr_version => X"020146") -- aa.bb.cc version
408 412 -- AA : BOARD NUMBER
409 413 -- 0 => MINI_LFR
410 414 -- 1 => EM
411 415 -- 2 => EQM (with A3PE3000)
412 416 PORT MAP (
413 417 clk => clk_25,
414 418 rstn => LFR_rstn,
415 419 sample_B => sample_s(2 DOWNTO 0),
416 420 sample_E => sample_s(7 DOWNTO 3),
417 421 sample_val => sample_val,
418 422 apbi => apbi_ext,
419 423 apbo => apbo_ext(15),
420 424 ahbi => ahbi_m_ext,
421 425 ahbo => ahbo_m_ext(2),
422 426 coarse_time => coarse_time,
423 427 fine_time => fine_time,
424 428 data_shaping_BW => bias_fail_sw,
425 429 debug_vector => OPEN,
426 430 debug_vector_ms => OPEN); --,
427 431 --observation_vector_0 => OPEN,
428 432 --observation_vector_1 => OPEN,
429 433 --observation_reg => observation_reg);
430 434
431 435
432 436 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
433 437 sample_s(I) <= sample(I) & '0' & '0';
434 438 END GENERATE all_sample;
435 439 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
436 440
437 441 -----------------------------------------------------------------------------
438 442 --
439 443 -----------------------------------------------------------------------------
440 444 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
441 445 GENERIC MAP (
442 446 ChanelCount => 9,
443 447 ncycle_cnv_high => 13,
444 448 ncycle_cnv => 25,
445 449 FILTER_ENABLED => 16#FF#)
446 450 PORT MAP (
447 451 cnv_clk => clk_24,
448 452 cnv_rstn => rstn_24,
449 453 cnv => ADC_smpclk_s,
450 454 clk => clk_25,
451 455 rstn => rstn_25,
452 456 ADC_data => ADC_data,
453 457 ADC_nOE => ADC_OEB_bar_CH_s,
454 458 sample => sample,
455 459 sample_val => sample_val);
456 460
457 461 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
458 462
459 463 ADC_smpclk <= ADC_smpclk_s;
460 464 HK_smpclk <= ADC_smpclk_s;
461 465
462 466 TAG8 <= nSRAM_BUSY;
463 467
464 468 -----------------------------------------------------------------------------
465 469 -- HK
466 470 -----------------------------------------------------------------------------
467 471 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
468 472
473 -----------------------------------------------------------------------------
474 --
475 -----------------------------------------------------------------------------
476 inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
477 lpp_bootloader_1: lpp_bootloader
478 GENERIC MAP (
479 pindex => 13,
480 paddr => 13,
481 pmask => 16#fff#,
482 hindex => 3,
483 haddr => 0,
484 hmask => 16#fff#)
485 PORT MAP (
486 HCLK => clk_25,
487 HRESETn => rstn_25,
488 apbi => apbi_ext,
489 apbo => apbo_ext(13),
490 ahbsi => ahbi_s_ext,
491 ahbso => ahbo_s_ext(3));
492 END GENERATE inst_bootloader;
469 493 END beh;
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@@ -1,55 +1,54
1 1 #GRLIB=../..
2 2 VHDLIB=../..
3 3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 5 TOP=LFR_EQM
6 6 BOARD=LFR-EQM
7 7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
8 8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 11 EFFORT=high
12 12 XSTOPT=
13 13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 15 #VHDLSYNFILES=config.vhd leon3mp.vhd
16 16 VHDLSYNFILES=LFR-EQM.vhd
17 17 VHDLSIMFILES=testbench.vhd
18 18 #SIMTOP=testbench
19 19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc
20 20 SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc
21 21 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc
22 22
23 23 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
24 24 CLEAN=soft-clean
25 25
26 26 TECHLIBS = proasic3l
27 27
28 28 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
29 29 tmtc openchip hynix ihp gleichmann micron usbhc
30 30
31 31 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
32 32 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
33 33 ./amba_lcd_16x2_ctrlr \
34 34 ./general_purpose/lpp_AMR \
35 35 ./general_purpose/lpp_balise \
36 36 ./general_purpose/lpp_delay \
37 ./lpp_bootloader \
38 37 ./dsp/lpp_fft_rtax \
39 38 ./lpp_uart \
40 39 ./lpp_usb \
41 40 ./lpp_sim/CY7C1061DV33 \
42 41
43 42 FILESKIP = i2cmst.vhd \
44 43 APB_MULTI_DIODE.vhd \
45 44 APB_MULTI_DIODE.vhd \
46 45 Top_MatrixSpec.vhd \
47 46 APB_FFT.vhd\
48 47 CoreFFT_simu.vhd \
49 48 lpp_lfr_apbreg_simu.vhd
50 49
51 50 include $(GRLIB)/bin/Makefile
52 51 include $(GRLIB)/software/leon3/Makefile
53 52
54 53 ################## project specific targets ##########################
55 54
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@@ -1,22 +1,22
1 GRLIB=../../..
1 #GRLIB=../../..
2 2 CC=gcc
3 3 XCC=sparc-elf-gcc -I$(GRLIB)/software/leon3 $(BOPT)
4 4 XAS=sparc-elf-gcc -c -I. -I$(GRLIB)/software/leon3 $(BOPT)
5 5
6 6 bootrom.o: bootrom.S bootrom.h
7 7 $(XAS) $<
8 8 bootrom.exe: bootrom.o
9 9 $(XCC) -nostdlib -Tlinkprom -N -L./ -Ttext=0 -nostartfiles -o bootrom.exe $<
10 10
11 11
12 12 make_bootrom : $(GRLIB)/bin/ahbrom.c
13 13 @if test -r "/mingw/bin/gcc.exe"; then \
14 14 $(CC) $(GRLIB)/bin/ahbrom.c -o make_bootrom -lwsock32; \
15 15 else \
16 16 $(CC) $(GRLIB)/bin/ahbrom.c -o make_bootrom; \
17 17 fi;
18 18
19 19 bootrom.vhd: bootrom.exe
20 20 make make_bootrom
21 21 sparc-elf-objcopy -O binary bootrom.exe bootrom.bin
22 ./make_bootrom bootrom.bin bootrom.vhd No newline at end of file
22 ./make_bootrom bootrom.bin bootrom.vhd
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@@ -1,204 +1,214
1 1
2 2 /* Template boot-code for LEON3 test benches */
3 3
4 4 #include "bootrom.h"
5 5
6 6 #ifndef STACKSIZE
7 7 #define STACKSIZE 0x00020000
8 8 #endif
9 9
10 10
11 11 .seg "text"
12 12 .proc 0
13 13 .align 4
14 14 .global start
15 15 start:
16 16
17 17 flush
18 18 set 0x10e0, %g1 ! init IU
19 19 mov %g1, %psr
20 20 mov %g0, %wim
21 21 mov %g0, %tbr
22 22 mov %g0, %y
23 23 mov %g0, %asr16
24 24 nop
25 25 set 0x81000f, %g1
26 26 sta %g1, [%g0] 2
27 27 mov %g0, %g2
28 28 nop
29 29 nop
30 30 nop
31 31 nop
32 32 nop
33 33 or %g2, %g2, %g0
34 34 nop
35 35 nop
36 36 nop
37 37 nop
38 38 nop
39 39 #ifdef DSUADDR
40 40 set DSUADDR, %g2
41 41 st %g0, [%g2]
42 42 st %g0, [%g2+0x08]
43 43 st %g0, [%g2+0x20]
44 44 st %g0, [%g2+0x24]
45 45 st %g0, [%g2+0x40]
46 46 st %g0, [%g2+0x44]
47 47 st %g0, [%g2+0x50]
48 48 st %g0, [%g2+0x54]
49 49 st %g0, [%g2+0x58]
50 50 st %g0, [%g2+0x5C]
51 51 st %g0, [%g2+0x54]
52 52 #endif
53 53
54 54 2:
55 55 mov %asr17, %g3
56 56 and %g3, 0x1f, %g3
57 57 mov %g0, %g4
58 58 mov %g0, %g5
59 59 mov %g0, %g6
60 60 mov %g0, %g7
61 61 1:
62 62 mov %g0, %l0
63 63 mov %g0, %l1
64 64 mov %g0, %l2
65 65 mov %g0, %l3
66 66 mov %g0, %l4
67 67 mov %g0, %l5
68 68 mov %g0, %l6
69 69 mov %g0, %l7
70 70 mov %g0, %o0
71 71 mov %g0, %o1
72 72 mov %g0, %o2
73 73 mov %g0, %o3
74 74 mov %g0, %o4
75 75 mov %g0, %o5
76 76 mov %g0, %o6
77 77 mov %g0, %o7
78 78 subcc %g3, 1, %g3
79 79 bge 1b
80 80 save
81 81
82 82 mov 2, %g1
83 83 mov %g1, %wim
84 84 set 0x10e0, %g1 ! enable traps
85 85 mov %g1, %psr
86 86 nop; nop; nop;
87 87
88 88 mov %psr, %g1
89 89 srl %g1, 12, %g1
90 90 andcc %g1, 1, %g0
91 91 be 1f
92 92 nop
93 93
94 94 set _fsrxx, %g3
95 95 ld [%g3], %fsr
96 96 ldd [%g3], %f0
97 97 ldd [%g3], %f2
98 98 ldd [%g3], %f4
99 99 ldd [%g3], %f6
100 100 ldd [%g3], %f8
101 101 ldd [%g3], %f10
102 102 ldd [%g3], %f12
103 103 ldd [%g3], %f14
104 104 ldd [%g3], %f16
105 105 ldd [%g3], %f18
106 106 ldd [%g3], %f20
107 107 ldd [%g3], %f22
108 108 ldd [%g3], %f24
109 109 ldd [%g3], %f26
110 110 ldd [%g3], %f28
111 111 ldd [%g3], %f30
112 112 nop
113 113 nop
114 114 nop
115 115 nop
116 116 nop
117 117 faddd %f0, %f2, %f4
118 118 nop
119 119 nop
120 120 nop
121 121 nop
122 122 ba 1f
123 123 nop
124 124
125 125
126 126 .align 8
127 127 _fsrxx:
128 128 .word 0
129 129 .word 0
130 130
131 131 1:
132 132 mov %asr17, %g3
133 133 srl %g3, 28, %g3
134 134 andcc %g3, 0x0f, %g3
135 135 bne 1f
136 136
137 set L2MCTRLIO, %g1
137 /* set L2MCTRLIO, %g1
138 138 set MCFG1, %g2
139 139 st %g2, [%g1]
140 140 set MCFG2, %g2
141 141 st %g2, [%g1+4]
142 142 set MCFG3, %g2
143 143 st %g2, [%g1+8]
144 */
144 145 ! set IRQCTRL, %g1
145 146 ! set 0x0ffff, %g2
146 147 ! st %g2, [%g1+0x10]
147 148
148 149 #ifdef DDR2CTRLIO
149 150 set DDR2CTRLIO, %g1
150 151 set DDR2CFG4, %g2
151 152 st %g2, [%g1+12]
152 153 #endif
153 154
154 155 #ifdef ASDCFG
155 156 #ifndef SDCTRLPNP
156 157 #define SDCTRLPNP 0xFFFFF860
157 158 #endif
158 159 set SDCTRLPNP, %g1
159 160 ld [%g1], %g2
160 161 srl %g2, 12, %g2
161 162 set 0x01009, %g1
162 163 subcc %g1, %g2, %g0
163 164 bne 1f
164 165
165 166 set ASDCFG, %g1
166 167 set DSDCFG, %g2
167 168 st %g2, [%g1]
168 169 #endif
169 170
170 171 ! %g3 = cpu index
171 172 1: set STACKSIZE, %g2
172 173 mov %g0, %g1
173 174 2: subcc %g3, 0, %g0
174 175 be 3f
175 176 nop
176 177 add %g1, %g2, %g1
177 178 ba 2b
178 179 sub %g3, 1, %g3
179 180
181 3: set RAMSTART_RAMSIZE-32, %fp
182 sub %fp, %g1, %fp
183 sub %fp, 96, %sp
180 184
185 set RAMSTART, %g1
186
187 jmp %g1
188 nop
189
190 /*
181 191 3:
182 192 set REG_BOOTLOADER, %10
183 193 ld [%10], %11
184 194 tst %11
185 195 be RunProg
186 196 inf_wait_on_boot:
187 197 nop
188 198 ld [%10+4], %11
189 199 tst %11
190 200 be inf_wait_on_boot
191 201 RunProg:
192 202 nop
193 203 ld [%10+8], %11
194 204 set RAMSTART_RAMSIZE-32, %10
195 205 add %11, %10, %fp
196 206 sub %fp, %g1, %fp
197 207 sub %fp, 96, %sp
198 208
199 209 mov %11, %g1
200 210
201 211 jmp %g1
202 212 nop
203
213 */
204 214 .align 32
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@@ -1,10 +1,12
1 1 #define MCFG1 0x10380233
2 2 #define MCFG2 0xe6A26e60
3 3 #define MCFG3 0x000ff000
4 #define ASDCFG 0xfff00100
5 #define DSDCFG 0xe6A06e60
4 //#define ASDCFG 0xfff00100
5 //#define DSDCFG 0xe6A06e60
6 6 #define L2MCTRLIO 0x80000000
7 7 #define IRQCTRL 0x80000200
8 #define RAMSTART 0x40000000
9 #define DSUADDR 0x90000000
8 10 #define RAMSTART_RAMSIZE 0x40100000
9 11
10 12 #define REG_BOOTLOADER 0x80000D00
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@@ -1,248 +1,223
1 1
2 2 ----------------------------------------------------------------------------
3 3 -- This file is a part of the GRLIB VHDL IP LIBRARY
4 4 -- Copyright (C) 2010 Aeroflex Gaisler
5 5 ----------------------------------------------------------------------------
6 6 -- Entity: ahbrom
7 7 -- File: ahbrom.vhd
8 8 -- Author: Jiri Gaisler - Gaisler Research
9 9 -- Description: AHB rom. 0/1-waitstate read
10 10 ----------------------------------------------------------------------------
11 11 library ieee;
12 12 use ieee.std_logic_1164.all;
13 13 library grlib;
14 14 use grlib.amba.all;
15 15 use grlib.stdlib.all;
16 16 use grlib.devices.all;
17 17
18 entity ahbrom is
18 entity bootrom is
19 19 generic (
20 20 hindex : integer := 0;
21 21 haddr : integer := 0;
22 22 hmask : integer := 16#fff#;
23 23 pipe : integer := 0;
24 24 tech : integer := 0;
25 25 kbytes : integer := 1);
26 26 port (
27 27 rst : in std_ulogic;
28 28 clk : in std_ulogic;
29 29 ahbsi : in ahb_slv_in_type;
30 30 ahbso : out ahb_slv_out_type
31 31 );
32 32 end;
33 33
34 architecture rtl of ahbrom is
34 architecture rtl of bootrom is
35 35 constant abits : integer := 10;
36 constant bytes : integer := 624;
36 constant bytes : integer := 528;
37 37
38 38 constant hconfig : ahb_config_type := (
39 39 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
40 40 4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
41 41
42 42 signal romdata : std_logic_vector(31 downto 0);
43 43 signal addr : std_logic_vector(abits-1 downto 2);
44 44 signal hsel, hready : std_ulogic;
45 45
46 46 begin
47 47
48 48 ahbso.hresp <= "00";
49 49 ahbso.hsplit <= (others => '0');
50 50 ahbso.hirq <= (others => '0');
51 ahbso.hcache <= '1';
52 51 ahbso.hconfig <= hconfig;
53 52 ahbso.hindex <= hindex;
54 53
55 54 reg : process (clk)
56 55 begin
57 56 if rising_edge(clk) then
58 57 addr <= ahbsi.haddr(abits-1 downto 2);
59 58 end if;
60 59 end process;
61 60
62 61 p0 : if pipe = 0 generate
63 62 ahbso.hrdata <= ahbdrivedata(romdata);
64 63 ahbso.hready <= '1';
65 64 end generate;
66 65
67 66 p1 : if pipe = 1 generate
68 67 reg2 : process (clk)
69 68 begin
70 69 if rising_edge(clk) then
71 70 hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
72 71 hready <= ahbsi.hready;
73 72 ahbso.hready <= (not rst) or (hsel and hready) or
74 73 (ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
75 74 ahbso.hrdata <= ahbdrivedata(romdata);
76 75 end if;
77 76 end process;
78 77 end generate;
79 78
80 79 comb : process (addr)
81 80 begin
82 81 case conv_integer(addr) is
83 82 when 16#00000# => romdata <= X"81D82000";
84 83 when 16#00001# => romdata <= X"03000004";
85 84 when 16#00002# => romdata <= X"821060E0";
86 85 when 16#00003# => romdata <= X"81884000";
87 86 when 16#00004# => romdata <= X"81900000";
88 87 when 16#00005# => romdata <= X"81980000";
89 88 when 16#00006# => romdata <= X"81800000";
90 89 when 16#00007# => romdata <= X"A1800000";
91 90 when 16#00008# => romdata <= X"01000000";
92 91 when 16#00009# => romdata <= X"03002040";
93 92 when 16#0000A# => romdata <= X"8210600F";
94 93 when 16#0000B# => romdata <= X"C2A00040";
95 94 when 16#0000C# => romdata <= X"84100000";
96 95 when 16#0000D# => romdata <= X"01000000";
97 96 when 16#0000E# => romdata <= X"01000000";
98 97 when 16#0000F# => romdata <= X"01000000";
99 98 when 16#00010# => romdata <= X"01000000";
100 99 when 16#00011# => romdata <= X"01000000";
101 100 when 16#00012# => romdata <= X"80108002";
102 101 when 16#00013# => romdata <= X"01000000";
103 102 when 16#00014# => romdata <= X"01000000";
104 103 when 16#00015# => romdata <= X"01000000";
105 104 when 16#00016# => romdata <= X"01000000";
106 105 when 16#00017# => romdata <= X"01000000";
107 when 16#00018# => romdata <= X"87444000";
108 when 16#00019# => romdata <= X"8608E01F";
109 when 16#0001A# => romdata <= X"88100000";
110 when 16#0001B# => romdata <= X"8A100000";
111 when 16#0001C# => romdata <= X"8C100000";
112 when 16#0001D# => romdata <= X"8E100000";
113 when 16#0001E# => romdata <= X"A0100000";
114 when 16#0001F# => romdata <= X"A2100000";
115 when 16#00020# => romdata <= X"A4100000";
116 when 16#00021# => romdata <= X"A6100000";
117 when 16#00022# => romdata <= X"A8100000";
118 when 16#00023# => romdata <= X"AA100000";
119 when 16#00024# => romdata <= X"AC100000";
120 when 16#00025# => romdata <= X"AE100000";
121 when 16#00026# => romdata <= X"90100000";
122 when 16#00027# => romdata <= X"92100000";
123 when 16#00028# => romdata <= X"94100000";
124 when 16#00029# => romdata <= X"96100000";
125 when 16#0002A# => romdata <= X"98100000";
126 when 16#0002B# => romdata <= X"9A100000";
127 when 16#0002C# => romdata <= X"9C100000";
128 when 16#0002D# => romdata <= X"9E100000";
129 when 16#0002E# => romdata <= X"86A0E001";
130 when 16#0002F# => romdata <= X"16BFFFEF";
131 when 16#00030# => romdata <= X"81E00000";
132 when 16#00031# => romdata <= X"82102002";
133 when 16#00032# => romdata <= X"81904000";
134 when 16#00033# => romdata <= X"03000004";
135 when 16#00034# => romdata <= X"821060E0";
136 when 16#00035# => romdata <= X"81884000";
137 when 16#00036# => romdata <= X"01000000";
138 when 16#00037# => romdata <= X"01000000";
139 when 16#00038# => romdata <= X"01000000";
140 when 16#00039# => romdata <= X"83480000";
141 when 16#0003A# => romdata <= X"8330600C";
142 when 16#0003B# => romdata <= X"80886001";
143 when 16#0003C# => romdata <= X"02800024";
144 when 16#0003D# => romdata <= X"01000000";
145 when 16#0003E# => romdata <= X"07000000";
146 when 16#0003F# => romdata <= X"8610E178";
147 when 16#00040# => romdata <= X"C108C000";
148 when 16#00041# => romdata <= X"C118C000";
149 when 16#00042# => romdata <= X"C518C000";
150 when 16#00043# => romdata <= X"C918C000";
151 when 16#00044# => romdata <= X"CD18C000";
152 when 16#00045# => romdata <= X"D118C000";
153 when 16#00046# => romdata <= X"D518C000";
154 when 16#00047# => romdata <= X"D918C000";
155 when 16#00048# => romdata <= X"DD18C000";
156 when 16#00049# => romdata <= X"E118C000";
157 when 16#0004A# => romdata <= X"E518C000";
158 when 16#0004B# => romdata <= X"E918C000";
159 when 16#0004C# => romdata <= X"ED18C000";
160 when 16#0004D# => romdata <= X"F118C000";
161 when 16#0004E# => romdata <= X"F518C000";
162 when 16#0004F# => romdata <= X"F918C000";
163 when 16#00050# => romdata <= X"FD18C000";
164 when 16#00051# => romdata <= X"01000000";
165 when 16#00052# => romdata <= X"01000000";
166 when 16#00053# => romdata <= X"01000000";
167 when 16#00054# => romdata <= X"01000000";
168 when 16#00055# => romdata <= X"01000000";
169 when 16#00056# => romdata <= X"89A00842";
170 when 16#00057# => romdata <= X"01000000";
171 when 16#00058# => romdata <= X"01000000";
172 when 16#00059# => romdata <= X"01000000";
173 when 16#0005A# => romdata <= X"01000000";
174 when 16#0005B# => romdata <= X"10800005";
175 when 16#0005C# => romdata <= X"01000000";
106 when 16#00018# => romdata <= X"05240000";
107 when 16#00019# => romdata <= X"C0208000";
108 when 16#0001A# => romdata <= X"C020A008";
109 when 16#0001B# => romdata <= X"C020A020";
110 when 16#0001C# => romdata <= X"C020A024";
111 when 16#0001D# => romdata <= X"C020A040";
112 when 16#0001E# => romdata <= X"C020A044";
113 when 16#0001F# => romdata <= X"C020A050";
114 when 16#00020# => romdata <= X"C020A054";
115 when 16#00021# => romdata <= X"C020A058";
116 when 16#00022# => romdata <= X"C020A05C";
117 when 16#00023# => romdata <= X"C020A054";
118 when 16#00024# => romdata <= X"87444000";
119 when 16#00025# => romdata <= X"8608E01F";
120 when 16#00026# => romdata <= X"88100000";
121 when 16#00027# => romdata <= X"8A100000";
122 when 16#00028# => romdata <= X"8C100000";
123 when 16#00029# => romdata <= X"8E100000";
124 when 16#0002A# => romdata <= X"A0100000";
125 when 16#0002B# => romdata <= X"A2100000";
126 when 16#0002C# => romdata <= X"A4100000";
127 when 16#0002D# => romdata <= X"A6100000";
128 when 16#0002E# => romdata <= X"A8100000";
129 when 16#0002F# => romdata <= X"AA100000";
130 when 16#00030# => romdata <= X"AC100000";
131 when 16#00031# => romdata <= X"AE100000";
132 when 16#00032# => romdata <= X"90100000";
133 when 16#00033# => romdata <= X"92100000";
134 when 16#00034# => romdata <= X"94100000";
135 when 16#00035# => romdata <= X"96100000";
136 when 16#00036# => romdata <= X"98100000";
137 when 16#00037# => romdata <= X"9A100000";
138 when 16#00038# => romdata <= X"9C100000";
139 when 16#00039# => romdata <= X"9E100000";
140 when 16#0003A# => romdata <= X"86A0E001";
141 when 16#0003B# => romdata <= X"16BFFFEF";
142 when 16#0003C# => romdata <= X"81E00000";
143 when 16#0003D# => romdata <= X"82102002";
144 when 16#0003E# => romdata <= X"81904000";
145 when 16#0003F# => romdata <= X"03000004";
146 when 16#00040# => romdata <= X"821060E0";
147 when 16#00041# => romdata <= X"81884000";
148 when 16#00042# => romdata <= X"01000000";
149 when 16#00043# => romdata <= X"01000000";
150 when 16#00044# => romdata <= X"01000000";
151 when 16#00045# => romdata <= X"83480000";
152 when 16#00046# => romdata <= X"8330600C";
153 when 16#00047# => romdata <= X"80886001";
154 when 16#00048# => romdata <= X"02800024";
155 when 16#00049# => romdata <= X"01000000";
156 when 16#0004A# => romdata <= X"07000000";
157 when 16#0004B# => romdata <= X"8610E1A8";
158 when 16#0004C# => romdata <= X"C108C000";
159 when 16#0004D# => romdata <= X"C118C000";
160 when 16#0004E# => romdata <= X"C518C000";
161 when 16#0004F# => romdata <= X"C918C000";
162 when 16#00050# => romdata <= X"CD18C000";
163 when 16#00051# => romdata <= X"D118C000";
164 when 16#00052# => romdata <= X"D518C000";
165 when 16#00053# => romdata <= X"D918C000";
166 when 16#00054# => romdata <= X"DD18C000";
167 when 16#00055# => romdata <= X"E118C000";
168 when 16#00056# => romdata <= X"E518C000";
169 when 16#00057# => romdata <= X"E918C000";
170 when 16#00058# => romdata <= X"ED18C000";
171 when 16#00059# => romdata <= X"F118C000";
172 when 16#0005A# => romdata <= X"F518C000";
173 when 16#0005B# => romdata <= X"F918C000";
174 when 16#0005C# => romdata <= X"FD18C000";
176 175 when 16#0005D# => romdata <= X"01000000";
177 when 16#0005E# => romdata <= X"00000000";
178 when 16#0005F# => romdata <= X"00000000";
179 when 16#00060# => romdata <= X"87444000";
180 when 16#00061# => romdata <= X"8730E01C";
181 when 16#00062# => romdata <= X"8688E00F";
182 when 16#00063# => romdata <= X"12800016";
183 when 16#00064# => romdata <= X"03200000";
184 when 16#00065# => romdata <= X"05040E00";
185 when 16#00066# => romdata <= X"8410A233";
186 when 16#00067# => romdata <= X"C4204000";
187 when 16#00068# => romdata <= X"0539A89B";
188 when 16#00069# => romdata <= X"8410A260";
189 when 16#0006A# => romdata <= X"C4206004";
190 when 16#0006B# => romdata <= X"050003FC";
191 when 16#0006C# => romdata <= X"C4206008";
192 when 16#0006D# => romdata <= X"82103860";
193 when 16#0006E# => romdata <= X"C4004000";
194 when 16#0006F# => romdata <= X"8530A00C";
195 when 16#00070# => romdata <= X"03000004";
196 when 16#00071# => romdata <= X"82106009";
197 when 16#00072# => romdata <= X"80A04002";
198 when 16#00073# => romdata <= X"12800006";
199 when 16#00074# => romdata <= X"033FFC00";
200 when 16#00075# => romdata <= X"82106100";
201 when 16#00076# => romdata <= X"0539A81B";
202 when 16#00077# => romdata <= X"8410A260";
203 when 16#00078# => romdata <= X"C4204000";
204 when 16#00079# => romdata <= X"05000080";
205 when 16#0007A# => romdata <= X"82100000";
206 when 16#0007B# => romdata <= X"80A0E000";
207 when 16#0007C# => romdata <= X"02800005";
208 when 16#0007D# => romdata <= X"01000000";
209 when 16#0007E# => romdata <= X"82004002";
210 when 16#0007F# => romdata <= X"10BFFFFC";
211 when 16#00080# => romdata <= X"8620E001";
212 when 16#00081# => romdata <= X"15200003";
213 when 16#00082# => romdata <= X"9412A100";
214 when 16#00083# => romdata <= X"D6028000";
215 when 16#00084# => romdata <= X"8092C000";
216 when 16#00085# => romdata <= X"02800005";
217 when 16#00086# => romdata <= X"01000000";
218 when 16#00087# => romdata <= X"D602A004";
219 when 16#00088# => romdata <= X"8092C000";
220 when 16#00089# => romdata <= X"02BFFFFD";
221 when 16#0008A# => romdata <= X"01000000";
222 when 16#0008B# => romdata <= X"D602A008";
223 when 16#0008C# => romdata <= X"151003FF";
224 when 16#0008D# => romdata <= X"9412A3E0";
225 when 16#0008E# => romdata <= X"BC02C00A";
226 when 16#0008F# => romdata <= X"BC278001";
227 when 16#00090# => romdata <= X"9C27A060";
228 when 16#00091# => romdata <= X"8210000B";
229 when 16#00092# => romdata <= X"81C04000";
230 when 16#00093# => romdata <= X"01000000";
231 when 16#00094# => romdata <= X"01000000";
232 when 16#00095# => romdata <= X"01000000";
233 when 16#00096# => romdata <= X"01000000";
234 when 16#00097# => romdata <= X"01000000";
235 when 16#00098# => romdata <= X"00000000";
236 when 16#00099# => romdata <= X"00000000";
237 when 16#0009A# => romdata <= X"00000000";
238 when 16#0009B# => romdata <= X"00000000";
239 when 16#0009C# => romdata <= X"00000000";
176 when 16#0005E# => romdata <= X"01000000";
177 when 16#0005F# => romdata <= X"01000000";
178 when 16#00060# => romdata <= X"01000000";
179 when 16#00061# => romdata <= X"01000000";
180 when 16#00062# => romdata <= X"89A00842";
181 when 16#00063# => romdata <= X"01000000";
182 when 16#00064# => romdata <= X"01000000";
183 when 16#00065# => romdata <= X"01000000";
184 when 16#00066# => romdata <= X"01000000";
185 when 16#00067# => romdata <= X"10800005";
186 when 16#00068# => romdata <= X"01000000";
187 when 16#00069# => romdata <= X"01000000";
188 when 16#0006A# => romdata <= X"00000000";
189 when 16#0006B# => romdata <= X"00000000";
190 when 16#0006C# => romdata <= X"87444000";
191 when 16#0006D# => romdata <= X"8730E01C";
192 when 16#0006E# => romdata <= X"8688E00F";
193 when 16#0006F# => romdata <= X"12800001";
194 when 16#00070# => romdata <= X"05000080";
195 when 16#00071# => romdata <= X"82100000";
196 when 16#00072# => romdata <= X"80A0E000";
197 when 16#00073# => romdata <= X"02800005";
198 when 16#00074# => romdata <= X"01000000";
199 when 16#00075# => romdata <= X"82004002";
200 when 16#00076# => romdata <= X"10BFFFFC";
201 when 16#00077# => romdata <= X"8620E001";
202 when 16#00078# => romdata <= X"3D1003FF";
203 when 16#00079# => romdata <= X"BC17A3E0";
204 when 16#0007A# => romdata <= X"BC278001";
205 when 16#0007B# => romdata <= X"9C27A060";
206 when 16#0007C# => romdata <= X"03100000";
207 when 16#0007D# => romdata <= X"81C04000";
208 when 16#0007E# => romdata <= X"01000000";
209 when 16#0007F# => romdata <= X"01000000";
210 when 16#00080# => romdata <= X"00000000";
211 when 16#00081# => romdata <= X"00000000";
212 when 16#00082# => romdata <= X"00000000";
213 when 16#00083# => romdata <= X"00000000";
214 when 16#00084# => romdata <= X"00000000";
240 215 when others => romdata <= (others => '-');
241 216 end case;
242 217 end process;
243 218 -- pragma translate_off
244 219 bootmsg : report_version
245 220 generic map ("ahbrom" & tost(hindex) &
246 221 ": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
247 222 -- pragma translate_on
248 223 end;
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@@ -1,145 +1,145
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 USE grlib.devices.ALL;
29 29 LIBRARY lpp;
30 30 USE lpp.lpp_bootloader_pkg.ALL;
31 31 USE lpp.apb_devices_list.ALL;
32 32
33 33
34 34 ENTITY lpp_bootloader IS
35 35
36 36 GENERIC (
37 37 pindex : INTEGER := 1;
38 38 paddr : INTEGER := 1;
39 39 pmask : INTEGER := 16#fff#;
40 40 hindex : INTEGER := 0;
41 41 haddr : INTEGER := 0;
42 42 hmask : INTEGER := 16#fff#
43 43 );
44 44
45 45 PORT (
46 46 -- AMBA AHB system signals
47 47 HCLK : IN STD_ULOGIC;
48 48 HRESETn : IN STD_ULOGIC;
49 49
50 50 -- AMBA APB Slave Interface
51 51 apbi : IN apb_slv_in_type;
52 52 apbo : OUT apb_slv_out_type;
53 53
54 54 -- AMBA AHB Slave Interface
55 55 ahbsi : IN ahb_slv_in_type;
56 56 ahbso : OUT ahb_slv_out_type
57 57 );
58 58
59 59 END lpp_bootloader;
60 60
61 61 ARCHITECTURE Beh OF lpp_bootloader IS
62 62
63 63 CONSTANT REVISION : INTEGER := 1;
64 64
65 65 CONSTANT pconfig : apb_config_type := (
66 66 0 => ahb_device_reg (VENDOR_LPP, LPP_BOOTLOADER_TYPE, 0, REVISION, 0),
67 67 1 => apb_iobar(paddr, pmask));
68 68
69 69 TYPE lpp_bootloader_regs IS RECORD
70 70 config_wait_on_boot : STD_LOGIC;
71 71 config_start_execution : STD_LOGIC;
72 72 addr_start_execution : STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_fp : STD_LOGIC_VECTOR(31 DOWNTO 0);
73 -- addr_fp : STD_LOGIC_VECTOR(31 DOWNTO 0);
74 74 END RECORD;
75 75
76 76 SIGNAL reg : lpp_bootloader_regs;
77 77
78 78 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
79 79
80 80
81 81 BEGIN -- Beh
82 82
83 83 -----------------------------------------------------------------------------
84 84 -- AHBROM
85 85 -----------------------------------------------------------------------------
86 ahbrom_1 : ahbrom
86 ahbrom_1 : bootrom
87 87 GENERIC MAP (
88 88 hindex => hindex,
89 89 haddr => haddr,
90 90 hmask => hmask,
91 91 pipe => 0,
92 92 tech => 0,
93 93 kbytes => 1)
94 94 PORT MAP (
95 95 rst => HRESETn,
96 96 clk => HCLK,
97 97 ahbsi => ahbsi,
98 98 ahbso => ahbso);
99 99
100 100 -----------------------------------------------------------------------------
101 101 -- APB REG
102 102 -----------------------------------------------------------------------------
103 103
104 104 lpp_bootloader_apbreg : PROCESS (HCLK, HRESETn)
105 105 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
106 106 BEGIN -- PROCESS lpp_dma_top
107 107 IF HRESETn = '0' THEN -- asynchronous reset (active low)
108 108 reg.config_wait_on_boot <= '1';
109 109 reg.config_start_execution <= '0';
110 110 reg.addr_start_execution <= X"40000000";
111 111 prdata <= (OTHERS => '0');
112 112 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
113 113
114 114 paddr := "000000";
115 115 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
116 116 prdata <= (OTHERS => '0');
117 117 IF apbi.psel(pindex) = '1' THEN
118 118 -- APB DMA READ --
119 119 CASE paddr(7 DOWNTO 2) IS
120 120 WHEN "000000" => prdata(0) <= reg.config_wait_on_boot;
121 121 prdata(31 DOWNTO 1) <= (OTHERS => '0');
122 122 WHEN "000001" => prdata(0) <= reg.config_start_execution;
123 123 prdata(31 DOWNTO 1) <= (OTHERS => '0');
124 124 WHEN "000010" => prdata <= reg.addr_start_execution;
125 125 WHEN OTHERS => NULL;
126 126 END CASE;
127 127 IF (apbi.pwrite AND apbi.penable) = '1' THEN
128 128 -- APB DMA WRITE --
129 129 CASE paddr(7 DOWNTO 2) IS
130 130 WHEN "000000" => reg.config_wait_on_boot <= apbi.pwdata(0);
131 131 WHEN "000001" => reg.config_start_execution <= apbi.pwdata(0);
132 132 WHEN "000010" => reg.addr_start_execution <= apbi.pwdata;
133 133 WHEN OTHERS => NULL;
134 134 END CASE;
135 135 END IF;
136 136 END IF;
137 137 END IF;
138 138 END PROCESS lpp_bootloader_apbreg;
139 139
140 140 apbo.pirq <= (OTHERS => '0');
141 141 apbo.pindex <= pindex;
142 142 apbo.pconfig <= pconfig;
143 143 apbo.prdata <= prdata;
144 144
145 145 END Beh;
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@@ -1,64 +1,64
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 USE grlib.devices.ALL;
29 29
30 30 PACKAGE lpp_bootloader_pkg IS
31 31
32 32 COMPONENT lpp_bootloader
33 33 GENERIC (
34 34 pindex : INTEGER;
35 35 paddr : INTEGER;
36 36 pmask : INTEGER;
37 37 hindex : INTEGER;
38 38 haddr : INTEGER;
39 39 hmask : INTEGER);
40 40 PORT (
41 41 HCLK : IN STD_ULOGIC;
42 42 HRESETn : IN STD_ULOGIC;
43 43 apbi : IN apb_slv_in_type;
44 44 apbo : OUT apb_slv_out_type;
45 45 ahbsi : IN ahb_slv_in_type;
46 46 ahbso : OUT ahb_slv_out_type);
47 47 END COMPONENT;
48 48
49 COMPONENT ahbrom
49 COMPONENT bootrom
50 50 GENERIC (
51 51 hindex : INTEGER;
52 52 haddr : INTEGER;
53 53 hmask : INTEGER;
54 54 pipe : INTEGER;
55 55 tech : INTEGER;
56 56 kbytes : INTEGER);
57 57 PORT (
58 58 rst : IN STD_ULOGIC;
59 59 clk : IN STD_ULOGIC;
60 60 ahbsi : IN ahb_slv_in_type;
61 61 ahbso : OUT ahb_slv_out_type);
62 62 END COMPONENT;
63 63
64 64 END lpp_bootloader_pkg;
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@@ -1,213 +1,213
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23 -- 1.0 - initial version
24 24 -------------------------------------------------------------------------------
25 25 LIBRARY ieee;
26 26 USE ieee.std_logic_1164.ALL;
27 27 USE ieee.numeric_std.ALL;
28 28 LIBRARY grlib;
29 29 USE grlib.amba.ALL;
30 30 USE grlib.stdlib.ALL;
31 31 USE grlib.devices.ALL;
32 32
33 33 LIBRARY lpp;
34 34 USE lpp.lpp_amba.ALL;
35 35 USE lpp.apb_devices_list.ALL;
36 36 USE lpp.lpp_memory.ALL;
37 37 USE lpp.lpp_dma_pkg.ALL;
38 38 USE lpp.general_purpose.ALL;
39 39 --USE lpp.lpp_waveform_pkg.ALL;
40 40 LIBRARY techmap;
41 41 USE techmap.gencomp.ALL;
42 42
43 43
44 44 ENTITY lpp_dma_SEND16B_FIFO2DMA IS
45 45 GENERIC (
46 46 hindex : INTEGER := 2;
47 47 vendorid : IN INTEGER := 0;
48 48 deviceid : IN INTEGER := 0;
49 49 version : IN INTEGER := 0
50 50 );
51 51 PORT (
52 52 clk : IN STD_LOGIC;
53 53 rstn : IN STD_LOGIC;
54 54
55 55 -- AMBA AHB Master Interface
56 56 AHB_Master_In : IN AHB_Mst_In_Type;
57 57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58 58
59 59 -- FIFO Interface
60 60 ren : OUT STD_LOGIC;
61 61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 62
63 63 -- Controls
64 64 send : IN STD_LOGIC;
65 65 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
66 66 done : OUT STD_LOGIC;
67 67 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
68 68 );
69 69 END;
70 70
71 71 ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS
72 72
73 73 CONSTANT HConfig : AHB_Config_Type := (
74 74 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
75 75 OTHERS => (OTHERS => '0'));
76 76
77 77 TYPE AHB_DMA_FSM_STATE IS (IDLE, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
78 78 SIGNAL state : AHB_DMA_FSM_STATE;
79 79
80 80 SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
81 81 SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
82 82
83 83 SIGNAL data_window : STD_LOGIC;
84 84 SIGNAL ctrl_window : STD_LOGIC;
85 85
86 86 SIGNAL bus_request : STD_LOGIC;
87 87 SIGNAL bus_lock : STD_LOGIC;
88 88
89 89 BEGIN
90 90
91 91 -----------------------------------------------------------------------------
92 92 AHB_Master_Out.HCONFIG <= HConfig;
93 93 AHB_Master_Out.HSIZE <= "010"; --WORDS 32b
94 94 AHB_Master_Out.HINDEX <= hindex;
95 95 AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
96 96 AHB_Master_Out.HIRQ <= (OTHERS => '0');
97 97 AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16
98 98 AHB_Master_Out.HWRITE <= '1';
99 99
100 100 --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE;
101 101
102 102 --AHB_Master_Out.HBUSREQ <= bus_request;
103 103 --AHB_Master_Out.HLOCK <= data_window;
104 104
105 105 --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE
106 106 -- '1' WHEN ctrl_window = '1' ELSE
107 107 -- '0';
108 108
109 109 --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE
110 110 -- '1' WHEN ctrl_window = '1' ELSE '0';
111 111
112 112 -----------------------------------------------------------------------------
113 113 AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
114 114 AHB_Master_Out.HWDATA <= ahbdrivedata(data);
115 115
116 116 -----------------------------------------------------------------------------
117 117 --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
118 118 --ren <= NOT beat;
119 119 -----------------------------------------------------------------------------
120 120 PROCESS (clk, rstn)
121 121 BEGIN -- PROCESS
122 122 IF rstn = '0' THEN -- asynchronous reset (active low)
123 123 state <= IDLE;
124 124 done <= '0';
125 125 address_counter_reg <= (OTHERS => '0');
126 126 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
127 127 AHB_Master_Out.HBUSREQ <= '0';
128 128 AHB_Master_Out.HLOCK <= '0';
129 129 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
130 130 done <= '0';
131 131 CASE state IS
132 132 WHEN IDLE =>
133 133 AHB_Master_Out.HBUSREQ <= '0';
134 134 AHB_Master_Out.HLOCK <= '0';
135 135 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
136 136 address_counter_reg <= (OTHERS => '0');
137 137 IF send = '1' THEN
138 138 AHB_Master_Out.HBUSREQ <= '1';
139 139 AHB_Master_Out.HLOCK <= '1';
140 140 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
141 141 state <= s_ARBITER;
142 142 END IF;
143 143
144 144 WHEN s_ARBITER =>
145 145 AHB_Master_Out.HBUSREQ <= '1';
146 146 AHB_Master_Out.HLOCK <= '1';
147 147 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
148 148 address_counter_reg <= (OTHERS => '0');
149 149
150 IF AHB_Master_In.HGRANT(hindex) = '1' THEN
150 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
151 151 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
152 152 state <= s_CTRL;
153 153 END IF;
154 154
155 155 WHEN s_CTRL =>
156 156 AHB_Master_Out.HBUSREQ <= '1';
157 157 AHB_Master_Out.HLOCK <= '1';
158 158 AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
159 159 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
160 160 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
161 161 state <= s_CTRL_DATA;
162 162 END IF;
163 163
164 164 WHEN s_CTRL_DATA =>
165 165 AHB_Master_Out.HBUSREQ <= '1';
166 166 AHB_Master_Out.HLOCK <= '1';
167 167 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
168 168 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
169 169 address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1);
170 170 END IF;
171 171
172 172 IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
173 173 AHB_Master_Out.HBUSREQ <= '0';
174 174 AHB_Master_Out.HLOCK <= '1';--'0';
175 175 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
176 176 state <= s_DATA;
177 177 END IF;
178 178
179 179 WHEN s_DATA =>
180 180 AHB_Master_Out.HBUSREQ <= '0';
181 181 AHB_Master_Out.HLOCK <= '0';
182 182 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
183 183 IF AHB_Master_In.HREADY = '1' THEN
184 184 state <= IDLE;
185 185 done <= '1';
186 186 END IF;
187 187
188 188 WHEN OTHERS => NULL;
189 189 END CASE;
190 190 END IF;
191 191 END PROCESS;
192 192
193 193 ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
194 194 data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
195 195 -----------------------------------------------------------------------------
196 196 ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
197 197
198 198 -----------------------------------------------------------------------------
199 199 --PROCESS (clk, rstn)
200 200 --BEGIN -- PROCESS
201 201 -- IF rstn = '0' THEN -- asynchronous reset (active low)
202 202 -- address_counter_reg <= (OTHERS => '0');
203 203 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
204 204 -- address_counter_reg <= address_counter;
205 205 -- END IF;
206 206 --END PROCESS;
207 207
208 208 --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE
209 209 -- address_counter_reg;
210 210 -----------------------------------------------------------------------------
211 211
212 212
213 213 END Behavioral;
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