HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r176:ee29877991b1

lib/lpp/dsp/iir_filter/vhdlsyn.txt created 644 +8 0

@@ -0,0 +1,8
	1	iir_filter.vhd
	2	FILTERcfg.vhd
	3	RAM.vhd
	4	RAM_CEL.vhd
	5	RAM_CTRLR_v2.vhd
	6	IIR_CEL_CTRLR_v2_CONTROL.vhd
	7	IIR_CEL_CTRLR_v2_DATAFLOW.vhd
	8	IIR_CEL_CTRLR_v2.vhd

lib/lpp/dsp/lpp_fft/vhdlsyn.txt created 644 +9 0

@@ -0,0 +1,9
	1	APB_FFT.vhd
	2	APB_FFT_half.vhd
	3	Driver_FFT.vhd
	4	FFT.vhd
	5	FFTamont.vhd
	6	FFTaval.vhd
	7	Flag_Extremum.vhd
	8	Linker_FFT.vhd
	9	lpp_fft.vhd

lib/lpp/lpp_ad_Conv/vhdlsyn.txt created 644 +4 0

@@ -0,0 +1,4
	1	lpp_ad_Conv.vhd
	2	AD7688_drvr.vhd
	3	WriteGen_ADC.vhd
	4	TestModule_ADS7886.vhd

lib/lpp/lpp_amba/vhdlsyn.txt created 644 +2 0

@@ -0,0 +1,2
	1	apb_devices_list.vhd
	2	lpp_amba.vhd

lib/lpp/lpp_bootloader/vhdlsyn.txt created 644 +3 0

@@ -0,0 +1,3
	1	lpp_bootloader_pkg.vhd
	2	bootrom.vhd
	3	lpp_bootloader.vhd

lib/lpp/lpp_demux/vhdlsyn.txt created 644 +4 0

@@ -0,0 +1,4
	1	DEMUX.vhd
	2	Demultiplex.vhd
	3	WatchFlag.vhd
	4	lpp_demux.vhd

lib/lpp/lpp_matrix/vhdlsyn.txt created 644 +13 0

@@ -0,0 +1,13
	1	ALU_Driver.vhd
	2	APB_Matrix.vhd
	3	Dispatch.vhd
	4	DriveInputs.vhd
	5	GetResult.vhd
	6	MatriceSpectrale.vhd
	7	Matrix.vhd
	8	SpectralMatrix.vhd
	9	Starter.vhd
	10	TopMatrix_PDR.vhd
	11	TopSpecMatrix.vhd
	12	Top_MatrixSpec.vhd
	13	lpp_matrix.vhd

lib/lpp/lpp_memory/vhdlsyn.txt created 644 +7 0

@@ -0,0 +1,7
	1	lpp_memory.vhd
	2	lpp_FIFO.vhd
	3	APB_FIFO.vhd
	4	Bridge.vhd
	5	SSRAM_plugin.vhd
	6	lppFIFOx5.vhd
	7	lppFIFOxN.vhd

designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/leon3mp.vhd 0 -11

@@ -607,17 +607,6 BEGIN
607	header_val => header_val,	607	header_val => header_val,
608	header_ack => header_ack);	608	header_ack => header_ack);
609		609
610	--fifo_latency_correction_1 : fifo_latency_correction
611	-- PORT MAP (
612	-- HCLK => clkm,
613	-- HRESETn => resetn,
614	-- fifo_data => fifo_data,
615	-- fifo_empty => fifo_empty,
616	-- fifo_ren => fifo_ren,
617	-- dma_data => dma_data,
618	-- dma_empty => dma_empty,
619	-- dma_ren => dma_ren);
620
621	fifo_test_dma_1 : fifo_test_dma	610	fifo_test_dma_1 : fifo_test_dma
622	GENERIC MAP (	611	GENERIC MAP (
623	tech => fabtech,	612	tech => fabtech,

lib/lpp/dirs.txt +6 -6

             ./amba_lcd_16x2_ctrlr
-            ./dsp/iir_filter
-            ./dsp/lpp_downsampling
-            ./dsp/lpp_fft
             ./general_purpose
             ./general_purpose/lpp_AMR
             ./general_purpose/lpp_balise
             ./general_purpose/lpp_delay
+            ./lpp_amba
+            ./dsp/iir_filter
+            ./dsp/lpp_downsampling
+            ./dsp/lpp_fft
             ./lfr_time_management
             ./lpp_ad_Conv
-            ./lpp_amba
             ./lpp_bootloader
             ./lpp_cna
             ./lpp_demux
-            ./lpp_dma
             ./lpp_matrix
             ./lpp_memory
-            ./lpp_top_lfr
+            ./lpp_dma
             ./lpp_uart
             ./lpp_usb
             ./lpp_waveform
+            ./lpp_top_lfr

lib/lpp/general_purpose/vhdlsyn.txt +1 -1

+            general_purpose.vhd
             ADDRcntr.vhd
             ALU.vhd
             Adder.vhd
             REG.vhd
             SYNC_FF.vhd
             Shifter.vhd
-            general_purpose.vhd
             TwoComplementer.vhd

lib/lpp/lfr_time_management/apb_lfr_time_management.vhd +44 -10

                 pmask       : INTEGER := 16#fff#;   --! MASK field of the APB BAR
                 pirq        : INTEGER := 0;         --! 2 consecutive IRQ lines are used
                 masterclk   : INTEGER := 25000000;  --! master clock in Hz
-                otherclk    : INTEGER := 49152000;  --! other clock in Hz
+                timeclk    : INTEGER := 49152000;  --! other clock in Hz
                 finetimeclk : INTEGER := 65536  --! divided clock used for the fine time counter
                 );
             --! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word;
               CONSTANT pconfig : apb_config_type := (
             --!  0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0),
-=> ahb_device_reg (19, 14, 0, REVISION, pirq),
+=> ahb_device_reg (VENDOR_LPP, 0, 0, REVISION, pirq),
 => apb_iobar(paddr, pmask));
               TYPE apb_lfr_time_management_Reg IS RECORD
               SIGNAL soft_tick              : STD_LOGIC;
               SIGNAL reset_next_commutation : STD_LOGIC;
+              SIGNAL irq1 : STD_LOGIC;
+              SIGNAL irq2 : STD_LOGIC;
             BEGIN
               lfrtimemanagement0 : lfr_time_management
-                GENERIC MAP(masterclk => masterclk, timeclk => otherclk, finetimeclk => finetimeclk)
+                GENERIC MAP(
-                PORT MAP(master_clock      => clk25MHz, time_clock => clk49_152MHz, resetn => resetn,
+                  masterclk => masterclk,
-                          grspw_tick       => grspw_tick, soft_tick => soft_tick,
+                  timeclk => timeclk,
-                          coarse_time_load => r.coarse_time_load, coarse_time => r.coarse_time, fine_time => r.fine_time,
+                  finetimeclk => finetimeclk,
-                          next_commutation => r.next_commutation, reset_next_commutation => reset_next_commutation,
+                  nb_clk_div_ticks => 1)
-                          irq1             => apbo.pirq(pirq), irq2 => apbo.pirq(pirq+1));
+                PORT MAP(
+                  master_clock      => clk25MHz,
+                  time_clock => clk49_152MHz,
+                  resetn => resetn,
+                  grspw_tick       => grspw_tick,
+                  soft_tick => soft_tick,
+                  coarse_time_load => r.coarse_time_load,
+                  coarse_time => r.coarse_time,
+                  fine_time => r.fine_time,
+                  next_commutation => r.next_commutation,
+                  reset_next_commutation => reset_next_commutation,
+                  irq1             => irq1,--apbo.pirq(pirq),
+                  irq2 => irq2);--apbo.pirq(pirq+1));
+              	--apbo.pirq <= (OTHERS => '0');
+              all_irq_gen: FOR I IN 15 DOWNTO 0 GENERATE
+                irq1_gen: IF I = pirq GENERATE
+                  apbo.pirq(I) <= irq1;
+                END GENERATE irq1_gen;
+                irq2_gen: IF I = pirq+1 GENERATE
+                  apbo.pirq(I) <= irq2;
+                END GENERATE irq2_gen;
+                others_irq: IF (I < pirq) OR (I > (pirq + 1)) GENERATE
+                  apbo.pirq(I) <= '0';
+                END GENERATE others_irq;
+              END GENERATE all_irq_gen;
+              --all_irq_sig: FOR I IN 31 DOWNTO 0 GENERATE
+              --END GENERATE all_irq_sig;
               PROCESS(resetn, clk25MHz, reset_next_commutation)
               BEGIN
                 IF resetn = '0' THEN
+                  Rdata <=  (OTHERS => '0');
                   r.coarse_time_load  <= x"80000000";
                   r.ctrl              <= x"00000000";
                   r.next_commutation  <= x"ffffffff";
                   END IF;
                 END IF;
-                apbo.pconfig <= pconfig;
               END PROCESS;
-              apbo.prdata <= Rdata WHEN apbi.penable = '1';
+              apbo.prdata  <= Rdata ;--WHEN apbi.penable = '1';
               coarse_time  <= r.coarse_time;
               fine_time    <= r.fine_time;
+              apbo.pconfig <= pconfig;
+              apbo.pindex  <= pindex;
             END Behavioral;

lib/lpp/lfr_time_management/vhdlsyn.txt +2 -2

@@ -1,3 +1,3
1	~~apb~~_lfr_time_management.vhd	1	lpp_lfr_time_management.vhd
2	lfr_time_management.vhd	2	lfr_time_management.vhd
3	~~lpp~~_lfr_time_management.vhd	3	apb_lfr_time_management.vhd

lib/lpp/lpp_memory/SSRAM_plugin.vhd +5 -2

             Type stateT is (idle,st1,st2,st3,st4);
             signal state : stateT;
+            SIGNAL nclk : STD_LOGIC;
             begin
             process(clk , mem_ctrlr_o.RAMSN(0))
                 end if;
             end process;
+            nclk <= NOT clk;
             ssram_clk_pad : outpad generic map (tech => tech)
-                port map (SSRAM_CLK,not clk);
+                port map (SSRAM_CLK,nclk);
             nBWaint  <=  mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0);
             ZZ_pad : outpad generic map (tech => tech)
                 port map (ZZ, '0');
-            end architecture;
  No newline at end of file
+            end architecture;

lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd +5 -1

                   data_f2_in_valid => sample_f2_val,
                   data_f3_in_valid => sample_f3_val);
+              data_f0_in_valid((4*16)-1 DOWNTO 0) <= (others => '0');
+              data_f1_in_valid((4*16)-1 DOWNTO 0) <= (others => '0');
+              data_f2_in_valid((4*16)-1 DOWNTO 0) <= (others => '0');
+              data_f3_in_valid((4*16)-1 DOWNTO 0) <= (others => '0');
               data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s;
               data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s;
               data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s;
               sample_f2_wdata <= sample_f2_wdata_s;
               sample_f3_wdata <= sample_f3_wdata_s;
-            END tb;
+            END tb;
  No newline at end of file

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