diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/leon3mp.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/leon3mp.vhd --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/leon3mp.vhd +++ b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/leon3mp.vhd @@ -607,17 +607,6 @@ BEGIN header_val => header_val, header_ack => header_ack); - --fifo_latency_correction_1 : fifo_latency_correction - -- PORT MAP ( - -- HCLK => clkm, - -- HRESETn => resetn, - -- fifo_data => fifo_data, - -- fifo_empty => fifo_empty, - -- fifo_ren => fifo_ren, - -- dma_data => dma_data, - -- dma_empty => dma_empty, - -- dma_ren => dma_ren); - fifo_test_dma_1 : fifo_test_dma GENERIC MAP ( tech => fabtech, diff --git a/lib/lpp/dirs.txt b/lib/lpp/dirs.txt --- a/lib/lpp/dirs.txt +++ b/lib/lpp/dirs.txt @@ -1,21 +1,21 @@ ./amba_lcd_16x2_ctrlr -./dsp/iir_filter -./dsp/lpp_downsampling -./dsp/lpp_fft ./general_purpose ./general_purpose/lpp_AMR ./general_purpose/lpp_balise ./general_purpose/lpp_delay +./lpp_amba +./dsp/iir_filter +./dsp/lpp_downsampling +./dsp/lpp_fft ./lfr_time_management ./lpp_ad_Conv -./lpp_amba ./lpp_bootloader ./lpp_cna ./lpp_demux -./lpp_dma ./lpp_matrix ./lpp_memory -./lpp_top_lfr +./lpp_dma ./lpp_uart ./lpp_usb ./lpp_waveform +./lpp_top_lfr diff --git a/lib/lpp/dsp/iir_filter/vhdlsyn.txt b/lib/lpp/dsp/iir_filter/vhdlsyn.txt new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/iir_filter/vhdlsyn.txt @@ -0,0 +1,8 @@ +iir_filter.vhd +FILTERcfg.vhd +RAM.vhd +RAM_CEL.vhd +RAM_CTRLR_v2.vhd +IIR_CEL_CTRLR_v2_CONTROL.vhd +IIR_CEL_CTRLR_v2_DATAFLOW.vhd +IIR_CEL_CTRLR_v2.vhd diff --git a/lib/lpp/dsp/lpp_fft/vhdlsyn.txt b/lib/lpp/dsp/lpp_fft/vhdlsyn.txt new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft/vhdlsyn.txt @@ -0,0 +1,9 @@ +APB_FFT.vhd +APB_FFT_half.vhd +Driver_FFT.vhd +FFT.vhd +FFTamont.vhd +FFTaval.vhd +Flag_Extremum.vhd +Linker_FFT.vhd +lpp_fft.vhd diff --git a/lib/lpp/general_purpose/vhdlsyn.txt b/lib/lpp/general_purpose/vhdlsyn.txt --- a/lib/lpp/general_purpose/vhdlsyn.txt +++ b/lib/lpp/general_purpose/vhdlsyn.txt @@ -1,3 +1,4 @@ +general_purpose.vhd ADDRcntr.vhd ALU.vhd Adder.vhd @@ -14,5 +15,4 @@ Multiplier.vhd REG.vhd SYNC_FF.vhd Shifter.vhd -general_purpose.vhd TwoComplementer.vhd diff --git a/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd b/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd --- a/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd +++ b/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd @@ -25,150 +25,184 @@ USE grlib.amba.ALL; USE grlib.stdlib.ALL; USE grlib.devices.ALL; LIBRARY lpp; -USE lpp.apb_devices_list.ALL; -USE lpp.lpp_lfr_time_management.ALL; - -ENTITY apb_lfr_time_management IS - - GENERIC( - pindex : INTEGER := 0; --! APB slave index - paddr : INTEGER := 0; --! ADDR field of the APB BAR - pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR - pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used - masterclk : INTEGER := 25000000; --! master clock in Hz - otherclk : INTEGER := 49152000; --! other clock in Hz - finetimeclk : INTEGER := 65536 --! divided clock used for the fine time counter - ); - - PORT ( - clk25MHz : IN STD_LOGIC; --! Clock - clk49_152MHz : IN STD_LOGIC; --! secondary clock - resetn : IN STD_LOGIC; --! Reset - grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received - apbi : IN apb_slv_in_type; --! APB slave input signals - apbo : OUT apb_slv_out_type; --! APB slave output signals - coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time - fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --! fine time - ); - -END apb_lfr_time_management; - -ARCHITECTURE Behavioral OF apb_lfr_time_management IS - - CONSTANT REVISION : INTEGER := 1; - ---! the following types are defined in the grlib amba package ---! subtype amba_config_word is std_logic_vector(31 downto 0); ---! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; - CONSTANT pconfig : apb_config_type := ( ---! 0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0), - 0 => ahb_device_reg (19, 14, 0, REVISION, pirq), - 1 => apb_iobar(paddr, pmask)); - - TYPE apb_lfr_time_management_Reg IS RECORD - ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0); - coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0); - coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0); - END RECORD; - - SIGNAL r : apb_lfr_time_management_Reg; - SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL force_tick : STD_LOGIC; - SIGNAL previous_force_tick : STD_LOGIC; - SIGNAL soft_tick : STD_LOGIC; - SIGNAL reset_next_commutation : STD_LOGIC; - -BEGIN - - lfrtimemanagement0 : lfr_time_management - GENERIC MAP(masterclk => masterclk, timeclk => otherclk, finetimeclk => finetimeclk) - PORT MAP(master_clock => clk25MHz, time_clock => clk49_152MHz, resetn => resetn, - grspw_tick => grspw_tick, soft_tick => soft_tick, - coarse_time_load => r.coarse_time_load, coarse_time => r.coarse_time, fine_time => r.fine_time, - next_commutation => r.next_commutation, reset_next_commutation => reset_next_commutation, - irq1 => apbo.pirq(pirq), irq2 => apbo.pirq(pirq+1)); - - PROCESS(resetn, clk25MHz, reset_next_commutation) - BEGIN - - IF resetn = '0' THEN - r.coarse_time_load <= x"80000000"; - r.ctrl <= x"00000000"; - r.next_commutation <= x"ffffffff"; - force_tick <= '0'; - previous_force_tick <= '0'; - soft_tick <= '0'; - - ELSIF reset_next_commutation = '1' THEN - r.next_commutation <= x"ffffffff"; - - ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN - - previous_force_tick <= force_tick; - force_tick <= r.ctrl(0); - IF (previous_force_tick = '0') AND (force_tick = '1') THEN - soft_tick <= '1'; - ELSE - soft_tick <= '0'; - END IF; - ---APB Write OP - IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN - CASE apbi.paddr(7 DOWNTO 2) IS - WHEN "000000" => - r.ctrl <= apbi.pwdata(31 DOWNTO 0); - WHEN "000001" => - r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0); - WHEN "000100" => - r.next_commutation <= apbi.pwdata(31 DOWNTO 0); - WHEN OTHERS => - r.coarse_time_load <= x"00000000"; - END CASE; - ELSIF r.ctrl(0) = '1' THEN - r.ctrl(0) <= '0'; - END IF; - ---APB READ OP - IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN - CASE apbi.paddr(7 DOWNTO 2) IS - WHEN "000000" => - Rdata(31 DOWNTO 24) <= r.ctrl(31 DOWNTO 24); - Rdata(23 DOWNTO 16) <= r.ctrl(23 DOWNTO 16); - Rdata(15 DOWNTO 8) <= r.ctrl(15 DOWNTO 8); - Rdata(7 DOWNTO 0) <= r.ctrl(7 DOWNTO 0); - WHEN "000001" => - Rdata(31 DOWNTO 24) <= r.coarse_time_load(31 DOWNTO 24); - Rdata(23 DOWNTO 16) <= r.coarse_time_load(23 DOWNTO 16); - Rdata(15 DOWNTO 8) <= r.coarse_time_load(15 DOWNTO 8); - Rdata(7 DOWNTO 0) <= r.coarse_time_load(7 DOWNTO 0); - WHEN "000010" => - Rdata(31 DOWNTO 24) <= r.coarse_time(31 DOWNTO 24); - Rdata(23 DOWNTO 16) <= r.coarse_time(23 DOWNTO 16); - Rdata(15 DOWNTO 8) <= r.coarse_time(15 DOWNTO 8); - Rdata(7 DOWNTO 0) <= r.coarse_time(7 DOWNTO 0); - WHEN "000011" => - Rdata(31 DOWNTO 24) <= r.fine_time(31 DOWNTO 24); - Rdata(23 DOWNTO 16) <= r.fine_time(23 DOWNTO 16); - Rdata(15 DOWNTO 8) <= r.fine_time(15 DOWNTO 8); - Rdata(7 DOWNTO 0) <= r.fine_time(7 DOWNTO 0); - WHEN "000100" => - Rdata(31 DOWNTO 24) <= r.next_commutation(31 DOWNTO 24); - Rdata(23 DOWNTO 16) <= r.next_commutation(23 DOWNTO 16); - Rdata(15 DOWNTO 8) <= r.next_commutation(15 DOWNTO 8); - Rdata(7 DOWNTO 0) <= r.next_commutation(7 DOWNTO 0); - WHEN OTHERS => - Rdata(31 DOWNTO 0) <= x"00000000"; - END CASE; - END IF; - - END IF; - apbo.pconfig <= pconfig; - END PROCESS; - - apbo.prdata <= Rdata WHEN apbi.penable = '1'; - coarse_time <= r.coarse_time; - fine_time <= r.fine_time; - -END Behavioral; +USE lpp.apb_devices_list.ALL; +USE lpp.lpp_lfr_time_management.ALL; + +ENTITY apb_lfr_time_management IS + + GENERIC( + pindex : INTEGER := 0; --! APB slave index + paddr : INTEGER := 0; --! ADDR field of the APB BAR + pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR + pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used + masterclk : INTEGER := 25000000; --! master clock in Hz + timeclk : INTEGER := 49152000; --! other clock in Hz + finetimeclk : INTEGER := 65536 --! divided clock used for the fine time counter + ); + + PORT ( + clk25MHz : IN STD_LOGIC; --! Clock + clk49_152MHz : IN STD_LOGIC; --! secondary clock + resetn : IN STD_LOGIC; --! Reset + grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received + apbi : IN apb_slv_in_type; --! APB slave input signals + apbo : OUT apb_slv_out_type; --! APB slave output signals + coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time + fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --! fine time + ); + +END apb_lfr_time_management; + +ARCHITECTURE Behavioral OF apb_lfr_time_management IS + + CONSTANT REVISION : INTEGER := 1; + +--! the following types are defined in the grlib amba package +--! subtype amba_config_word is std_logic_vector(31 downto 0); +--! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; + CONSTANT pconfig : apb_config_type := ( +--! 0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0), + 0 => ahb_device_reg (VENDOR_LPP, 0, 0, REVISION, pirq), + 1 => apb_iobar(paddr, pmask)); + + TYPE apb_lfr_time_management_Reg IS RECORD + ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0); + coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0); + coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0); + END RECORD; + + SIGNAL r : apb_lfr_time_management_Reg; + SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL force_tick : STD_LOGIC; + SIGNAL previous_force_tick : STD_LOGIC; + SIGNAL soft_tick : STD_LOGIC; + SIGNAL reset_next_commutation : STD_LOGIC; + + SIGNAL irq1 : STD_LOGIC; + SIGNAL irq2 : STD_LOGIC; + +BEGIN + + lfrtimemanagement0 : lfr_time_management + GENERIC MAP( + masterclk => masterclk, + timeclk => timeclk, + finetimeclk => finetimeclk, + nb_clk_div_ticks => 1) + PORT MAP( + master_clock => clk25MHz, + time_clock => clk49_152MHz, + resetn => resetn, + grspw_tick => grspw_tick, + soft_tick => soft_tick, + coarse_time_load => r.coarse_time_load, + coarse_time => r.coarse_time, + fine_time => r.fine_time, + next_commutation => r.next_commutation, + reset_next_commutation => reset_next_commutation, + irq1 => irq1,--apbo.pirq(pirq), + irq2 => irq2);--apbo.pirq(pirq+1)); + + --apbo.pirq <= (OTHERS => '0'); + + all_irq_gen: FOR I IN 15 DOWNTO 0 GENERATE + irq1_gen: IF I = pirq GENERATE + apbo.pirq(I) <= irq1; + END GENERATE irq1_gen; + irq2_gen: IF I = pirq+1 GENERATE + apbo.pirq(I) <= irq2; + END GENERATE irq2_gen; + others_irq: IF (I < pirq) OR (I > (pirq + 1)) GENERATE + apbo.pirq(I) <= '0'; + END GENERATE others_irq; + END GENERATE all_irq_gen; + + --all_irq_sig: FOR I IN 31 DOWNTO 0 GENERATE + --END GENERATE all_irq_sig; + + PROCESS(resetn, clk25MHz, reset_next_commutation) + BEGIN + + IF resetn = '0' THEN + Rdata <= (OTHERS => '0'); + r.coarse_time_load <= x"80000000"; + r.ctrl <= x"00000000"; + r.next_commutation <= x"ffffffff"; + force_tick <= '0'; + previous_force_tick <= '0'; + soft_tick <= '0'; + + ELSIF reset_next_commutation = '1' THEN + r.next_commutation <= x"ffffffff"; + + ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN + + previous_force_tick <= force_tick; + force_tick <= r.ctrl(0); + IF (previous_force_tick = '0') AND (force_tick = '1') THEN + soft_tick <= '1'; + ELSE + soft_tick <= '0'; + END IF; + +--APB Write OP + IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN + CASE apbi.paddr(7 DOWNTO 2) IS + WHEN "000000" => + r.ctrl <= apbi.pwdata(31 DOWNTO 0); + WHEN "000001" => + r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0); + WHEN "000100" => + r.next_commutation <= apbi.pwdata(31 DOWNTO 0); + WHEN OTHERS => + r.coarse_time_load <= x"00000000"; + END CASE; + ELSIF r.ctrl(0) = '1' THEN + r.ctrl(0) <= '0'; + END IF; + +--APB READ OP + IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN + CASE apbi.paddr(7 DOWNTO 2) IS + WHEN "000000" => + Rdata(31 DOWNTO 24) <= r.ctrl(31 DOWNTO 24); + Rdata(23 DOWNTO 16) <= r.ctrl(23 DOWNTO 16); + Rdata(15 DOWNTO 8) <= r.ctrl(15 DOWNTO 8); + Rdata(7 DOWNTO 0) <= r.ctrl(7 DOWNTO 0); + WHEN "000001" => + Rdata(31 DOWNTO 24) <= r.coarse_time_load(31 DOWNTO 24); + Rdata(23 DOWNTO 16) <= r.coarse_time_load(23 DOWNTO 16); + Rdata(15 DOWNTO 8) <= r.coarse_time_load(15 DOWNTO 8); + Rdata(7 DOWNTO 0) <= r.coarse_time_load(7 DOWNTO 0); + WHEN "000010" => + Rdata(31 DOWNTO 24) <= r.coarse_time(31 DOWNTO 24); + Rdata(23 DOWNTO 16) <= r.coarse_time(23 DOWNTO 16); + Rdata(15 DOWNTO 8) <= r.coarse_time(15 DOWNTO 8); + Rdata(7 DOWNTO 0) <= r.coarse_time(7 DOWNTO 0); + WHEN "000011" => + Rdata(31 DOWNTO 24) <= r.fine_time(31 DOWNTO 24); + Rdata(23 DOWNTO 16) <= r.fine_time(23 DOWNTO 16); + Rdata(15 DOWNTO 8) <= r.fine_time(15 DOWNTO 8); + Rdata(7 DOWNTO 0) <= r.fine_time(7 DOWNTO 0); + WHEN "000100" => + Rdata(31 DOWNTO 24) <= r.next_commutation(31 DOWNTO 24); + Rdata(23 DOWNTO 16) <= r.next_commutation(23 DOWNTO 16); + Rdata(15 DOWNTO 8) <= r.next_commutation(15 DOWNTO 8); + Rdata(7 DOWNTO 0) <= r.next_commutation(7 DOWNTO 0); + WHEN OTHERS => + Rdata(31 DOWNTO 0) <= x"00000000"; + END CASE; + END IF; + + END IF; + END PROCESS; + + apbo.prdata <= Rdata ;--WHEN apbi.penable = '1'; + coarse_time <= r.coarse_time; + fine_time <= r.fine_time; + apbo.pconfig <= pconfig; + apbo.pindex <= pindex; + +END Behavioral; diff --git a/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd b/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd --- a/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd +++ b/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd @@ -1,83 +1,83 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 13:04:01 07/02/2012 --- Design Name: --- Module Name: lpp_lfr_time_management - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:04:01 07/02/2012 +-- Design Name: +-- Module Name: lpp_lfr_time_management - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; -use grlib.devices.all; - +use grlib.devices.all; + package lpp_lfr_time_management is - ---*************************** --- APB_LFR_TIME_MANAGEMENT - -component apb_lfr_time_management is - - generic( - pindex : integer := 0; --! APB slave index - paddr : integer := 0; --! ADDR field of the APB BAR - pmask : integer := 16#fff#; --! MASK field of the APB BAR - pirq : integer := 0; --! 2 consecutive IRQ lines are used - masterclk : integer := 25000000; --! master clock in Hz - timeclk : integer := 49152000; --! other clock in Hz - finetimeclk : integer := 65536 --! divided clock used for the fine time counter - ); - - Port ( - clk25MHz : in STD_LOGIC; --! Clock - clk49_152MHz : in STD_LOGIC; --! secondary clock - resetn : in STD_LOGIC; --! Reset - grspw_tick : in STD_LOGIC; --! grspw signal asserted when a valid time-code is received - apbi : in apb_slv_in_type; --! APB slave input signals - apbo : out apb_slv_out_type; --! APB slave output signals - coarse_time : out std_logic_vector(31 downto 0); --! coarse time - fine_time : out std_logic_vector(31 downto 0) --! fine time - ); - + +--*************************** +-- APB_LFR_TIME_MANAGEMENT + +component apb_lfr_time_management is + + generic( + pindex : integer := 0; --! APB slave index + paddr : integer := 0; --! ADDR field of the APB BAR + pmask : integer := 16#fff#; --! MASK field of the APB BAR + pirq : integer := 0; --! 2 consecutive IRQ lines are used + masterclk : integer := 25000000; --! master clock in Hz + timeclk : integer := 49152000; --! other clock in Hz + finetimeclk : integer := 65536 --! divided clock used for the fine time counter + ); + + Port ( + clk25MHz : in STD_LOGIC; --! Clock + clk49_152MHz : in STD_LOGIC; --! secondary clock + resetn : in STD_LOGIC; --! Reset + grspw_tick : in STD_LOGIC; --! grspw signal asserted when a valid time-code is received + apbi : in apb_slv_in_type; --! APB slave input signals + apbo : out apb_slv_out_type; --! APB slave output signals + coarse_time : out std_logic_vector(31 downto 0); --! coarse time + fine_time : out std_logic_vector(31 downto 0) --! fine time + ); + end component; -component lfr_time_management is - - generic ( - masterclk : integer := 25000000; -- master clock in Hz - timeclk : integer := 49152000; -- 2nd clock in Hz - finetimeclk : integer := 65536; -- divided clock used for the fine time counter - nb_clk_div_ticks : integer := 1 -- nb ticks before commutation to AUTO state - ); - Port ( - master_clock : in std_logic; --! Clock - time_clock : in std_logic; --! 2nd Clock - resetn : in std_logic; --! Reset - grspw_tick : in std_logic; - soft_tick : in std_logic; --! soft tick, load the coarse_time value - coarse_time_load : in std_logic_vector(31 downto 0); - coarse_time : out std_logic_vector(31 downto 0); - fine_time : out std_logic_vector(31 downto 0); - next_commutation : in std_logic_vector(31 downto 0); - reset_next_commutation: out std_logic; - irq1 : out std_logic; - irq2 : out std_logic - ); - -end component; +component lfr_time_management is -end lpp_lfr_time_management; - + generic ( + masterclk : integer := 25000000; -- master clock in Hz + timeclk : integer := 49152000; -- 2nd clock in Hz + finetimeclk : integer := 65536; -- divided clock used for the fine time counter + nb_clk_div_ticks : integer := 1 -- nb ticks before commutation to AUTO state + ); + Port ( + master_clock : in std_logic; --! Clock + time_clock : in std_logic; --! 2nd Clock + resetn : in std_logic; --! Reset + grspw_tick : in std_logic; + soft_tick : in std_logic; --! soft tick, load the coarse_time value + coarse_time_load : in std_logic_vector(31 downto 0); + coarse_time : out std_logic_vector(31 downto 0); + fine_time : out std_logic_vector(31 downto 0); + next_commutation : in std_logic_vector(31 downto 0); + reset_next_commutation: out std_logic; + irq1 : out std_logic; + irq2 : out std_logic + ); + +end component; + +end lpp_lfr_time_management; + diff --git a/lib/lpp/lfr_time_management/vhdlsyn.txt b/lib/lpp/lfr_time_management/vhdlsyn.txt --- a/lib/lpp/lfr_time_management/vhdlsyn.txt +++ b/lib/lpp/lfr_time_management/vhdlsyn.txt @@ -1,3 +1,3 @@ -apb_lfr_time_management.vhd +lpp_lfr_time_management.vhd lfr_time_management.vhd -lpp_lfr_time_management.vhd +apb_lfr_time_management.vhd diff --git a/lib/lpp/lpp_ad_Conv/vhdlsyn.txt b/lib/lpp/lpp_ad_Conv/vhdlsyn.txt new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_ad_Conv/vhdlsyn.txt @@ -0,0 +1,4 @@ +lpp_ad_Conv.vhd +AD7688_drvr.vhd +WriteGen_ADC.vhd +TestModule_ADS7886.vhd diff --git a/lib/lpp/lpp_amba/vhdlsyn.txt b/lib/lpp/lpp_amba/vhdlsyn.txt new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_amba/vhdlsyn.txt @@ -0,0 +1,2 @@ +apb_devices_list.vhd +lpp_amba.vhd diff --git a/lib/lpp/lpp_bootloader/vhdlsyn.txt b/lib/lpp/lpp_bootloader/vhdlsyn.txt new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_bootloader/vhdlsyn.txt @@ -0,0 +1,3 @@ +lpp_bootloader_pkg.vhd +bootrom.vhd +lpp_bootloader.vhd diff --git a/lib/lpp/lpp_demux/vhdlsyn.txt b/lib/lpp/lpp_demux/vhdlsyn.txt new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_demux/vhdlsyn.txt @@ -0,0 +1,4 @@ +DEMUX.vhd +Demultiplex.vhd +WatchFlag.vhd +lpp_demux.vhd diff --git a/lib/lpp/lpp_matrix/vhdlsyn.txt b/lib/lpp/lpp_matrix/vhdlsyn.txt new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_matrix/vhdlsyn.txt @@ -0,0 +1,13 @@ +ALU_Driver.vhd +APB_Matrix.vhd +Dispatch.vhd +DriveInputs.vhd +GetResult.vhd +MatriceSpectrale.vhd +Matrix.vhd +SpectralMatrix.vhd +Starter.vhd +TopMatrix_PDR.vhd +TopSpecMatrix.vhd +Top_MatrixSpec.vhd +lpp_matrix.vhd diff --git a/lib/lpp/lpp_memory/SSRAM_plugin.vhd b/lib/lpp/lpp_memory/SSRAM_plugin.vhd --- a/lib/lpp/lpp_memory/SSRAM_plugin.vhd +++ b/lib/lpp/lpp_memory/SSRAM_plugin.vhd @@ -80,6 +80,8 @@ signal nCE3int : std_logic:='1'; Type stateT is (idle,st1,st2,st3,st4); signal state : stateT; +SIGNAL nclk : STD_LOGIC; + begin process(clk , mem_ctrlr_o.RAMSN(0)) @@ -102,8 +104,9 @@ begin end if; end process; +nclk <= NOT clk; ssram_clk_pad : outpad generic map (tech => tech) - port map (SSRAM_CLK,not clk); + port map (SSRAM_CLK,nclk); nBWaint <= mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0); @@ -181,4 +184,4 @@ MODE_pad : outpad generic map (tech => t ZZ_pad : outpad generic map (tech => tech) port map (ZZ, '0'); -end architecture; \ No newline at end of file +end architecture; diff --git a/lib/lpp/lpp_memory/vhdlsyn.txt b/lib/lpp/lpp_memory/vhdlsyn.txt new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_memory/vhdlsyn.txt @@ -0,0 +1,7 @@ +lpp_memory.vhd +lpp_FIFO.vhd +APB_FIFO.vhd +Bridge.vhd +SSRAM_plugin.vhd +lppFIFOx5.vhd +lppFIFOxN.vhd diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd @@ -1,498 +1,502 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; -USE lpp.iir_filter.ALL; -USE lpp.FILTERcfg.ALL; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_waveform_pkg.ALL; - -LIBRARY techmap; -USE techmap.gencomp.ALL; - -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -USE GRLIB.DMA2AHB_Package.ALL; - -ENTITY lpp_top_lfr_wf_picker_ip IS - GENERIC( - hindex : INTEGER := 2; - nb_burst_available_size : INTEGER := 11; - nb_snapshot_param_size : INTEGER := 11; - delta_snapshot_size : INTEGER := 16; - delta_f2_f0_size : INTEGER := 10; - delta_f2_f1_size : INTEGER := 10; - tech : INTEGER := 0 - ); - PORT ( - -- ADS7886 - cnv_run : IN STD_LOGIC; - cnv : OUT STD_LOGIC; - sck : OUT STD_LOGIC; - sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - -- - cnv_clk : IN STD_LOGIC; - cnv_rstn : IN STD_LOGIC; - -- - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - -- - sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); - sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- - sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); - sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- - sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); - sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- - sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); - sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - - -- AMBA AHB Master Interface - AHB_Master_In : IN AHB_Mst_In_Type; - AHB_Master_Out : OUT AHB_Mst_Out_Type; - - coarse_time_0 : IN STD_LOGIC; - - --config - data_shaping_SP0 : IN STD_LOGIC; - data_shaping_SP1 : IN STD_LOGIC; - data_shaping_R0 : IN STD_LOGIC; - data_shaping_R1 : IN STD_LOGIC; - - delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); - delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); - delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); - - enable_f0 : IN STD_LOGIC; - enable_f1 : IN STD_LOGIC; - enable_f2 : IN STD_LOGIC; - enable_f3 : IN STD_LOGIC; - - burst_f0 : IN STD_LOGIC; - burst_f1 : IN STD_LOGIC; - burst_f2 : IN STD_LOGIC; - - nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); - nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma - - addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END lpp_top_lfr_wf_picker_ip; - -ARCHITECTURE tb OF lpp_top_lfr_wf_picker_ip IS - - COMPONENT Downsampling - GENERIC ( - ChanelCount : INTEGER; - SampleSize : INTEGER; - DivideParam : INTEGER); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - sample_in_val : IN STD_LOGIC; - sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); - sample_out_val : OUT STD_LOGIC; - sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); - END COMPONENT; - - ----------------------------------------------------------------------------- - CONSTANT ChanelCount : INTEGER := 8; - CONSTANT ncycle_cnv_high : INTEGER := 79; - CONSTANT ncycle_cnv : INTEGER := 500; - - ----------------------------------------------------------------------------- - SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL sample_val_delay : STD_LOGIC; - ----------------------------------------------------------------------------- - CONSTANT Coef_SZ : INTEGER := 9; - CONSTANT CoefCntPerCel : INTEGER := 6; - CONSTANT CoefPerCel : INTEGER := 5; - CONSTANT Cels_count : INTEGER := 5; - - SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); - SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); - SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_filter_v2_out_val : STD_LOGIC; - SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_data_shaping_out_val : STD_LOGIC; - SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); - SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); - SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0); - SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); - SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_filter_v2_out_val_s : STD_LOGIC; - SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f0_val : STD_LOGIC; - SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); - SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); - -- - SIGNAL sample_f1_val : STD_LOGIC; - SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); - SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); - -- - SIGNAL sample_f2_val : STD_LOGIC; - SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0); - -- - SIGNAL sample_f3_val : STD_LOGIC; - SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); - SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); - SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); - SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); - ----------------------------------------------------------------------------- - - SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); -BEGIN - - -- component instantiation - ----------------------------------------------------------------------------- - DIGITAL_acquisition : AD7688_drvr - GENERIC MAP ( - ChanelCount => ChanelCount, - ncycle_cnv_high => ncycle_cnv_high, - ncycle_cnv => ncycle_cnv) - PORT MAP ( - cnv_clk => cnv_clk, -- - cnv_rstn => cnv_rstn, -- - cnv_run => cnv_run, -- - cnv => cnv, -- - clk => clk, -- - rstn => rstn, -- - sck => sck, -- - sdo => sdo(ChanelCount-1 DOWNTO 0), -- - sample => sample, - sample_val => sample_val); - - ----------------------------------------------------------------------------- - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - sample_val_delay <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - sample_val_delay <= sample_val; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE - SampleLoop : FOR j IN 0 TO 15 GENERATE - sample_filter_in(i, j) <= sample(i)(j); - END GENERATE; - - sample_filter_in(i, 16) <= sample(i)(15); - sample_filter_in(i, 17) <= sample(i)(15); - END GENERATE; - - coefs_v2 <= CoefsInitValCst_v2; - - IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 - GENERIC MAP ( - tech => 0, - Mem_use => use_RAM, -- use_RAM - Sample_SZ => 18, - Coef_SZ => Coef_SZ, - Coef_Nb => 25, - Coef_sel_SZ => 5, - Cels_count => Cels_count, - ChanelsCount => ChanelCount) - PORT MAP ( - rstn => rstn, - clk => clk, - virg_pos => 7, - coefs => coefs_v2, - sample_in_val => sample_val_delay, - sample_in => sample_filter_in, - sample_out_val => sample_filter_v2_out_val, - sample_out => sample_filter_v2_out); - - ----------------------------------------------------------------------------- - -- DATA_SHAPING - ----------------------------------------------------------------------------- - all_data_shaping_in_loop: FOR I IN 17 DOWNTO 0 GENERATE - sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0,I); - sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1,I); - sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2,I); - END GENERATE all_data_shaping_in_loop; - - sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s; - sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s; - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - sample_data_shaping_out_val <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - sample_data_shaping_out_val <= sample_filter_v2_out_val; - END IF; - END PROCESS; - - SampleLoop_data_shaping: FOR j IN 0 TO 17 GENERATE - PROCESS (clk, rstn) - BEGIN - IF rstn = '0' THEN - sample_data_shaping_out(0,j) <= '0'; - sample_data_shaping_out(1,j) <= '0'; - sample_data_shaping_out(2,j) <= '0'; - sample_data_shaping_out(3,j) <= '0'; - sample_data_shaping_out(4,j) <= '0'; - sample_data_shaping_out(5,j) <= '0'; - sample_data_shaping_out(6,j) <= '0'; - sample_data_shaping_out(7,j) <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - sample_data_shaping_out(0,j) <= sample_filter_v2_out(0,j); - IF data_shaping_SP0 = '1' THEN - sample_data_shaping_out(1,j) <= sample_data_shaping_f1_f0_s(j); - ELSE - sample_data_shaping_out(1,j) <= sample_filter_v2_out(1,j); - END IF; - IF data_shaping_SP1 = '1' THEN - sample_data_shaping_out(2,j) <= sample_data_shaping_f2_f1_s(j); - ELSE - sample_data_shaping_out(2,j) <= sample_filter_v2_out(2,j); - END IF; - sample_data_shaping_out(4,j) <= sample_filter_v2_out(4,j); - sample_data_shaping_out(5,j) <= sample_filter_v2_out(5,j); - sample_data_shaping_out(6,j) <= sample_filter_v2_out(6,j); - sample_data_shaping_out(7,j) <= sample_filter_v2_out(7,j); - END IF; - END PROCESS; - END GENERATE; - - sample_filter_v2_out_val_s <= sample_data_shaping_out_val; - ChanelLoopOut : FOR i IN 0 TO 7 GENERATE - SampleLoopOut : FOR j IN 0 TO 15 GENERATE - sample_filter_v2_out_s(i,j) <= sample_data_shaping_out(i,j); - END GENERATE; - END GENERATE; - ----------------------------------------------------------------------------- - -- F0 -- @24.576 kHz - ----------------------------------------------------------------------------- - Downsampling_f0 : Downsampling - GENERIC MAP ( - ChanelCount => 8, - SampleSize => 16, - DivideParam => 4) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_filter_v2_out_val_s, - sample_in => sample_filter_v2_out_s, - sample_out_val => sample_f0_val, - sample_out => sample_f0); - - all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f0_wdata_s(I) <= sample_f0(0, I); -- V - sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1 - sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2 - sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1 - sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2 - sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3 - END GENERATE all_bit_sample_f0; - - sample_f0_wen <= NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val); - - ----------------------------------------------------------------------------- - -- F1 -- @4096 Hz - ----------------------------------------------------------------------------- - Downsampling_f1 : Downsampling - GENERIC MAP ( - ChanelCount => 8, - SampleSize => 16, - DivideParam => 6) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_f0_val , - sample_in => sample_f0, - sample_out_val => sample_f1_val, - sample_out => sample_f1); - - all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f1_wdata_s(I) <= sample_f1(0, I); -- V - sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1 - sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2 - sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1 - sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2 - sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3 - END GENERATE all_bit_sample_f1; - - sample_f1_wen <= NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val); - - ----------------------------------------------------------------------------- - -- F2 -- @256 Hz - ----------------------------------------------------------------------------- - all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE - sample_f0_s(0, I) <= sample_f0(0, I); -- V - sample_f0_s(1, I) <= sample_f0(1, I); -- E1 - sample_f0_s(2, I) <= sample_f0(2, I); -- E2 - sample_f0_s(3, I) <= sample_f0(5, I); -- B1 - sample_f0_s(4, I) <= sample_f0(6, I); -- B2 - sample_f0_s(5, I) <= sample_f0(7, I); -- B3 - END GENERATE all_bit_sample_f0_s; - - Downsampling_f2 : Downsampling - GENERIC MAP ( - ChanelCount => 6, - SampleSize => 16, - DivideParam => 96) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_f0_val , - sample_in => sample_f0_s, - sample_out_val => sample_f2_val, - sample_out => sample_f2); - - sample_f2_wen <= NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val); - - all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f2_wdata_s(I) <= sample_f2(0, I); - sample_f2_wdata_s(16*1+I) <= sample_f2(1, I); - sample_f2_wdata_s(16*2+I) <= sample_f2(2, I); - sample_f2_wdata_s(16*3+I) <= sample_f2(3, I); - sample_f2_wdata_s(16*4+I) <= sample_f2(4, I); - sample_f2_wdata_s(16*5+I) <= sample_f2(5, I); - END GENERATE all_bit_sample_f2; - - ----------------------------------------------------------------------------- - -- F3 -- @16 Hz - ----------------------------------------------------------------------------- - all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE - sample_f1_s(0, I) <= sample_f1(0, I); -- V - sample_f1_s(1, I) <= sample_f1(1, I); -- E1 - sample_f1_s(2, I) <= sample_f1(2, I); -- E2 - sample_f1_s(3, I) <= sample_f1(5, I); -- B1 - sample_f1_s(4, I) <= sample_f1(6, I); -- B2 - sample_f1_s(5, I) <= sample_f1(7, I); -- B3 - END GENERATE all_bit_sample_f1_s; - - Downsampling_f3 : Downsampling - GENERIC MAP ( - ChanelCount => 6, - SampleSize => 16, - DivideParam => 256) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_f1_val , - sample_in => sample_f1_s, - sample_out_val => sample_f3_val, - sample_out => sample_f3); - - sample_f3_wen <= (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val); - - all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f3_wdata_s(I) <= sample_f3(0, I); - sample_f3_wdata_s(16*1+I) <= sample_f3(1, I); - sample_f3_wdata_s(16*2+I) <= sample_f3(2, I); - sample_f3_wdata_s(16*3+I) <= sample_f3(3, I); - sample_f3_wdata_s(16*4+I) <= sample_f3(4, I); - sample_f3_wdata_s(16*5+I) <= sample_f3(5, I); - END GENERATE all_bit_sample_f3; - - lpp_waveform_1 : lpp_waveform - GENERIC MAP ( - hindex => hindex, - tech => tech, - data_size => 160, - nb_burst_available_size => nb_burst_available_size, - nb_snapshot_param_size => nb_snapshot_param_size, - delta_snapshot_size => delta_snapshot_size, - delta_f2_f0_size => delta_f2_f0_size, - delta_f2_f1_size => delta_f2_f1_size) - PORT MAP ( - clk => clk, - rstn => rstn, - - AHB_Master_In => AHB_Master_In, - AHB_Master_Out => AHB_Master_Out, - - coarse_time_0 => coarse_time_0, -- IN - delta_snapshot => delta_snapshot, -- IN - delta_f2_f1 => delta_f2_f1, -- IN - delta_f2_f0 => delta_f2_f0, -- IN - enable_f0 => enable_f0, -- IN - enable_f1 => enable_f1, -- IN - enable_f2 => enable_f2, -- IN - enable_f3 => enable_f3, -- IN - burst_f0 => burst_f0, -- IN - burst_f1 => burst_f1, -- IN - burst_f2 => burst_f2, -- IN - nb_burst_available => nb_burst_available, - nb_snapshot_param => nb_snapshot_param, - status_full => status_full, - status_full_ack => status_full_ack, -- IN - status_full_err => status_full_err, - status_new_err => status_new_err, - - addr_data_f0 => addr_data_f0, -- IN - addr_data_f1 => addr_data_f1, -- IN - addr_data_f2 => addr_data_f2, -- IN - addr_data_f3 => addr_data_f3, -- IN - - data_f0_in => data_f0_in_valid, - data_f1_in => data_f1_in_valid, - data_f2_in => data_f2_in_valid, - data_f3_in => data_f3_in_valid, - data_f0_in_valid => sample_f0_val, - data_f1_in_valid => sample_f1_val, - data_f2_in_valid => sample_f2_val, - data_f3_in_valid => sample_f3_val); - - data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s; - data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s; - data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s; - data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s; - - sample_f0_wdata <= sample_f0_wdata_s; - sample_f1_wdata <= sample_f1_wdata_s; - sample_f2_wdata <= sample_f2_wdata_s; - sample_f3_wdata <= sample_f3_wdata_s; - -END tb; +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_waveform_pkg.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +ENTITY lpp_top_lfr_wf_picker_ip IS + GENERIC( + hindex : INTEGER := 2; + nb_burst_available_size : INTEGER := 11; + nb_snapshot_param_size : INTEGER := 11; + delta_snapshot_size : INTEGER := 16; + delta_f2_f0_size : INTEGER := 10; + delta_f2_f1_size : INTEGER := 10; + tech : INTEGER := 0 + ); + PORT ( + -- ADS7886 + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + -- + cnv_clk : IN STD_LOGIC; + cnv_rstn : IN STD_LOGIC; + -- + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + -- + sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + -- + sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + -- + sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + -- + sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + + -- AMBA AHB Master Interface + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + + coarse_time_0 : IN STD_LOGIC; + + --config + data_shaping_SP0 : IN STD_LOGIC; + data_shaping_SP1 : IN STD_LOGIC; + data_shaping_R0 : IN STD_LOGIC; + data_shaping_R1 : IN STD_LOGIC; + + delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + + enable_f0 : IN STD_LOGIC; + enable_f1 : IN STD_LOGIC; + enable_f2 : IN STD_LOGIC; + enable_f3 : IN STD_LOGIC; + + burst_f0 : IN STD_LOGIC; + burst_f1 : IN STD_LOGIC; + burst_f2 : IN STD_LOGIC; + + nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma + + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END lpp_top_lfr_wf_picker_ip; + +ARCHITECTURE tb OF lpp_top_lfr_wf_picker_ip IS + + COMPONENT Downsampling + GENERIC ( + ChanelCount : INTEGER; + SampleSize : INTEGER; + DivideParam : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sample_in_val : IN STD_LOGIC; + sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); + sample_out_val : OUT STD_LOGIC; + sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); + END COMPONENT; + + ----------------------------------------------------------------------------- + CONSTANT ChanelCount : INTEGER := 8; + CONSTANT ncycle_cnv_high : INTEGER := 79; + CONSTANT ncycle_cnv : INTEGER := 500; + + ----------------------------------------------------------------------------- + SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + SIGNAL sample_val_delay : STD_LOGIC; + ----------------------------------------------------------------------------- + CONSTANT Coef_SZ : INTEGER := 9; + CONSTANT CoefCntPerCel : INTEGER := 6; + CONSTANT CoefPerCel : INTEGER := 5; + CONSTANT Cels_count : INTEGER := 5; + + SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); + SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); + SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + -- + SIGNAL sample_filter_v2_out_val : STD_LOGIC; + SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_data_shaping_out_val : STD_LOGIC; + SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_filter_v2_out_val_s : STD_LOGIC; + SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_f0_val : STD_LOGIC; + SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); + SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); + -- + SIGNAL sample_f1_val : STD_LOGIC; + SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); + SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); + -- + SIGNAL sample_f2_val : STD_LOGIC; + SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0); + -- + SIGNAL sample_f3_val : STD_LOGIC; + SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + ----------------------------------------------------------------------------- + + SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); +BEGIN + + -- component instantiation + ----------------------------------------------------------------------------- + DIGITAL_acquisition : AD7688_drvr + GENERIC MAP ( + ChanelCount => ChanelCount, + ncycle_cnv_high => ncycle_cnv_high, + ncycle_cnv => ncycle_cnv) + PORT MAP ( + cnv_clk => cnv_clk, -- + cnv_rstn => cnv_rstn, -- + cnv_run => cnv_run, -- + cnv => cnv, -- + clk => clk, -- + rstn => rstn, -- + sck => sck, -- + sdo => sdo(ChanelCount-1 DOWNTO 0), -- + sample => sample, + sample_val => sample_val); + + ----------------------------------------------------------------------------- + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_val_delay <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + sample_val_delay <= sample_val; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE + SampleLoop : FOR j IN 0 TO 15 GENERATE + sample_filter_in(i, j) <= sample(i)(j); + END GENERATE; + + sample_filter_in(i, 16) <= sample(i)(15); + sample_filter_in(i, 17) <= sample(i)(15); + END GENERATE; + + coefs_v2 <= CoefsInitValCst_v2; + + IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 + GENERIC MAP ( + tech => 0, + Mem_use => use_RAM, -- use_RAM + Sample_SZ => 18, + Coef_SZ => Coef_SZ, + Coef_Nb => 25, + Coef_sel_SZ => 5, + Cels_count => Cels_count, + ChanelsCount => ChanelCount) + PORT MAP ( + rstn => rstn, + clk => clk, + virg_pos => 7, + coefs => coefs_v2, + sample_in_val => sample_val_delay, + sample_in => sample_filter_in, + sample_out_val => sample_filter_v2_out_val, + sample_out => sample_filter_v2_out); + + ----------------------------------------------------------------------------- + -- DATA_SHAPING + ----------------------------------------------------------------------------- + all_data_shaping_in_loop: FOR I IN 17 DOWNTO 0 GENERATE + sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0,I); + sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1,I); + sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2,I); + END GENERATE all_data_shaping_in_loop; + + sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s; + sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_data_shaping_out_val <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + sample_data_shaping_out_val <= sample_filter_v2_out_val; + END IF; + END PROCESS; + + SampleLoop_data_shaping: FOR j IN 0 TO 17 GENERATE + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + sample_data_shaping_out(0,j) <= '0'; + sample_data_shaping_out(1,j) <= '0'; + sample_data_shaping_out(2,j) <= '0'; + sample_data_shaping_out(3,j) <= '0'; + sample_data_shaping_out(4,j) <= '0'; + sample_data_shaping_out(5,j) <= '0'; + sample_data_shaping_out(6,j) <= '0'; + sample_data_shaping_out(7,j) <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + sample_data_shaping_out(0,j) <= sample_filter_v2_out(0,j); + IF data_shaping_SP0 = '1' THEN + sample_data_shaping_out(1,j) <= sample_data_shaping_f1_f0_s(j); + ELSE + sample_data_shaping_out(1,j) <= sample_filter_v2_out(1,j); + END IF; + IF data_shaping_SP1 = '1' THEN + sample_data_shaping_out(2,j) <= sample_data_shaping_f2_f1_s(j); + ELSE + sample_data_shaping_out(2,j) <= sample_filter_v2_out(2,j); + END IF; + sample_data_shaping_out(4,j) <= sample_filter_v2_out(4,j); + sample_data_shaping_out(5,j) <= sample_filter_v2_out(5,j); + sample_data_shaping_out(6,j) <= sample_filter_v2_out(6,j); + sample_data_shaping_out(7,j) <= sample_filter_v2_out(7,j); + END IF; + END PROCESS; + END GENERATE; + + sample_filter_v2_out_val_s <= sample_data_shaping_out_val; + ChanelLoopOut : FOR i IN 0 TO 7 GENERATE + SampleLoopOut : FOR j IN 0 TO 15 GENERATE + sample_filter_v2_out_s(i,j) <= sample_data_shaping_out(i,j); + END GENERATE; + END GENERATE; + ----------------------------------------------------------------------------- + -- F0 -- @24.576 kHz + ----------------------------------------------------------------------------- + Downsampling_f0 : Downsampling + GENERIC MAP ( + ChanelCount => 8, + SampleSize => 16, + DivideParam => 4) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_filter_v2_out_val_s, + sample_in => sample_filter_v2_out_s, + sample_out_val => sample_f0_val, + sample_out => sample_f0); + + all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f0_wdata_s(I) <= sample_f0(0, I); -- V + sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1 + sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2 + sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1 + sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2 + sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3 + END GENERATE all_bit_sample_f0; + + sample_f0_wen <= NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val); + + ----------------------------------------------------------------------------- + -- F1 -- @4096 Hz + ----------------------------------------------------------------------------- + Downsampling_f1 : Downsampling + GENERIC MAP ( + ChanelCount => 8, + SampleSize => 16, + DivideParam => 6) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_f0_val , + sample_in => sample_f0, + sample_out_val => sample_f1_val, + sample_out => sample_f1); + + all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f1_wdata_s(I) <= sample_f1(0, I); -- V + sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1 + sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2 + sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1 + sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2 + sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3 + END GENERATE all_bit_sample_f1; + + sample_f1_wen <= NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val); + + ----------------------------------------------------------------------------- + -- F2 -- @256 Hz + ----------------------------------------------------------------------------- + all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE + sample_f0_s(0, I) <= sample_f0(0, I); -- V + sample_f0_s(1, I) <= sample_f0(1, I); -- E1 + sample_f0_s(2, I) <= sample_f0(2, I); -- E2 + sample_f0_s(3, I) <= sample_f0(5, I); -- B1 + sample_f0_s(4, I) <= sample_f0(6, I); -- B2 + sample_f0_s(5, I) <= sample_f0(7, I); -- B3 + END GENERATE all_bit_sample_f0_s; + + Downsampling_f2 : Downsampling + GENERIC MAP ( + ChanelCount => 6, + SampleSize => 16, + DivideParam => 96) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_f0_val , + sample_in => sample_f0_s, + sample_out_val => sample_f2_val, + sample_out => sample_f2); + + sample_f2_wen <= NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val); + + all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f2_wdata_s(I) <= sample_f2(0, I); + sample_f2_wdata_s(16*1+I) <= sample_f2(1, I); + sample_f2_wdata_s(16*2+I) <= sample_f2(2, I); + sample_f2_wdata_s(16*3+I) <= sample_f2(3, I); + sample_f2_wdata_s(16*4+I) <= sample_f2(4, I); + sample_f2_wdata_s(16*5+I) <= sample_f2(5, I); + END GENERATE all_bit_sample_f2; + + ----------------------------------------------------------------------------- + -- F3 -- @16 Hz + ----------------------------------------------------------------------------- + all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE + sample_f1_s(0, I) <= sample_f1(0, I); -- V + sample_f1_s(1, I) <= sample_f1(1, I); -- E1 + sample_f1_s(2, I) <= sample_f1(2, I); -- E2 + sample_f1_s(3, I) <= sample_f1(5, I); -- B1 + sample_f1_s(4, I) <= sample_f1(6, I); -- B2 + sample_f1_s(5, I) <= sample_f1(7, I); -- B3 + END GENERATE all_bit_sample_f1_s; + + Downsampling_f3 : Downsampling + GENERIC MAP ( + ChanelCount => 6, + SampleSize => 16, + DivideParam => 256) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_f1_val , + sample_in => sample_f1_s, + sample_out_val => sample_f3_val, + sample_out => sample_f3); + + sample_f3_wen <= (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val); + + all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f3_wdata_s(I) <= sample_f3(0, I); + sample_f3_wdata_s(16*1+I) <= sample_f3(1, I); + sample_f3_wdata_s(16*2+I) <= sample_f3(2, I); + sample_f3_wdata_s(16*3+I) <= sample_f3(3, I); + sample_f3_wdata_s(16*4+I) <= sample_f3(4, I); + sample_f3_wdata_s(16*5+I) <= sample_f3(5, I); + END GENERATE all_bit_sample_f3; + + lpp_waveform_1 : lpp_waveform + GENERIC MAP ( + hindex => hindex, + tech => tech, + data_size => 160, + nb_burst_available_size => nb_burst_available_size, + nb_snapshot_param_size => nb_snapshot_param_size, + delta_snapshot_size => delta_snapshot_size, + delta_f2_f0_size => delta_f2_f0_size, + delta_f2_f1_size => delta_f2_f1_size) + PORT MAP ( + clk => clk, + rstn => rstn, + + AHB_Master_In => AHB_Master_In, + AHB_Master_Out => AHB_Master_Out, + + coarse_time_0 => coarse_time_0, -- IN + delta_snapshot => delta_snapshot, -- IN + delta_f2_f1 => delta_f2_f1, -- IN + delta_f2_f0 => delta_f2_f0, -- IN + enable_f0 => enable_f0, -- IN + enable_f1 => enable_f1, -- IN + enable_f2 => enable_f2, -- IN + enable_f3 => enable_f3, -- IN + burst_f0 => burst_f0, -- IN + burst_f1 => burst_f1, -- IN + burst_f2 => burst_f2, -- IN + nb_burst_available => nb_burst_available, + nb_snapshot_param => nb_snapshot_param, + status_full => status_full, + status_full_ack => status_full_ack, -- IN + status_full_err => status_full_err, + status_new_err => status_new_err, + + addr_data_f0 => addr_data_f0, -- IN + addr_data_f1 => addr_data_f1, -- IN + addr_data_f2 => addr_data_f2, -- IN + addr_data_f3 => addr_data_f3, -- IN + + data_f0_in => data_f0_in_valid, + data_f1_in => data_f1_in_valid, + data_f2_in => data_f2_in_valid, + data_f3_in => data_f3_in_valid, + data_f0_in_valid => sample_f0_val, + data_f1_in_valid => sample_f1_val, + data_f2_in_valid => sample_f2_val, + data_f3_in_valid => sample_f3_val); + + data_f0_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); + data_f1_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); + data_f2_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); + data_f3_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); + data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s; + data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s; + data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s; + data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s; + + sample_f0_wdata <= sample_f0_wdata_s; + sample_f1_wdata <= sample_f1_wdata_s; + sample_f2_wdata <= sample_f2_wdata_s; + sample_f3_wdata <= sample_f3_wdata_s; + +END tb; \ No newline at end of file