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1 iir_filter.vhd
2 FILTERcfg.vhd
3 RAM.vhd
4 RAM_CEL.vhd
5 RAM_CTRLR_v2.vhd
6 IIR_CEL_CTRLR_v2_CONTROL.vhd
7 IIR_CEL_CTRLR_v2_DATAFLOW.vhd
8 IIR_CEL_CTRLR_v2.vhd
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1 APB_FFT.vhd
2 APB_FFT_half.vhd
3 Driver_FFT.vhd
4 FFT.vhd
5 FFTamont.vhd
6 FFTaval.vhd
7 Flag_Extremum.vhd
8 Linker_FFT.vhd
9 lpp_fft.vhd
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1 lpp_ad_Conv.vhd
2 AD7688_drvr.vhd
3 WriteGen_ADC.vhd
4 TestModule_ADS7886.vhd
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1 apb_devices_list.vhd
2 lpp_amba.vhd
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1 lpp_bootloader_pkg.vhd
2 bootrom.vhd
3 lpp_bootloader.vhd
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1 DEMUX.vhd
2 Demultiplex.vhd
3 WatchFlag.vhd
4 lpp_demux.vhd
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1 ALU_Driver.vhd
2 APB_Matrix.vhd
3 Dispatch.vhd
4 DriveInputs.vhd
5 GetResult.vhd
6 MatriceSpectrale.vhd
7 Matrix.vhd
8 SpectralMatrix.vhd
9 Starter.vhd
10 TopMatrix_PDR.vhd
11 TopSpecMatrix.vhd
12 Top_MatrixSpec.vhd
13 lpp_matrix.vhd
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1 lpp_memory.vhd
2 lpp_FIFO.vhd
3 APB_FIFO.vhd
4 Bridge.vhd
5 SSRAM_plugin.vhd
6 lppFIFOx5.vhd
7 lppFIFOxN.vhd
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1 1 -----------------------------------------------------------------------------
2 2 -- LEON3 Demonstration design
3 3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 4 ------------------------------------------------------------------------------
5 5 -- This file is a part of the GRLIB VHDL IP LIBRARY
6 6 -- Copyright (C) 2010, Aeroflex Gaisler AB - all rights reserved.
7 7 --
8 8 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
9 9 -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED
10 10 -- IN ADVANCE IN WRITING.
11 11 ------------------------------------------------------------------------------
12 12
13 13
14 14 LIBRARY ieee;
15 15 USE ieee.std_logic_1164.ALL;
16 16 LIBRARY grlib;
17 17 USE grlib.amba.ALL;
18 18 USE grlib.stdlib.ALL;
19 19 USE GRLIB.DMA2AHB_Package.ALL;
20 20 LIBRARY techmap;
21 21 USE techmap.gencomp.ALL;
22 22 LIBRARY gaisler;
23 23 USE gaisler.memctrl.ALL;
24 24 USE gaisler.leon3.ALL;
25 25 USE gaisler.uart.ALL;
26 26 USE gaisler.misc.ALL;
27 27 USE gaisler.pci.ALL;
28 28 USE gaisler.net.ALL;
29 29 USE gaisler.jtag.ALL;
30 30 USE gaisler.spacewire.ALL;
31 31 LIBRARY esa;
32 32 USE esa.memoryctrl.ALL;
33 33 USE esa.pcicomp.ALL;
34 34 USE work.config.ALL;
35 35 LIBRARY lpp;
36 36 USE lpp.lpp_bootloader_pkg.ALL;
37 37 USE lpp.lpp_dma_pkg.ALL;
38 38 USE lpp.lpp_memory.ALL;
39 39
40 40 ENTITY leon3mp IS
41 41 GENERIC (
42 42 fabtech : INTEGER := CFG_FABTECH;
43 43 memtech : INTEGER := CFG_MEMTECH;
44 44 padtech : INTEGER := CFG_PADTECH;
45 45 clktech : INTEGER := CFG_CLKTECH;
46 46 ncpu : INTEGER := CFG_NCPU;
47 47 disas : INTEGER := CFG_DISAS; -- Enable disassembly to console
48 48 dbguart : INTEGER := CFG_DUART; -- Print UART on console
49 49 pclow : INTEGER := CFG_PCLOW
50 50 );
51 51 PORT (
52 52 resetn : IN STD_ULOGIC;
53 53 clk : IN STD_ULOGIC;
54 54 pllref : IN STD_ULOGIC;
55 55 errorn : OUT STD_ULOGIC;
56 56 address : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);
57 57 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
58 58
59 59 dsutx : OUT STD_ULOGIC; -- DSU tx data
60 60 dsurx : IN STD_ULOGIC; -- DSU rx data
61 61 dsuen : IN STD_ULOGIC;
62 62 dsubre : IN STD_ULOGIC;
63 63 dsuact : OUT STD_ULOGIC;
64 64 txd1 : OUT STD_ULOGIC; -- UART1 tx data
65 65 rxd1 : IN STD_ULOGIC; -- UART1 rx data
66 66 txd2 : OUT STD_ULOGIC; -- UART2 tx data
67 67 rxd2 : IN STD_ULOGIC; -- UART2 rx data
68 68 ramsn : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
69 69 ramoen : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
70 70 rwen : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
71 71 oen : OUT STD_ULOGIC;
72 72 writen : OUT STD_ULOGIC;
73 73 read : OUT STD_ULOGIC;
74 74 iosn : OUT STD_ULOGIC;
75 75 romsn : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
76 76 gpio : INOUT STD_LOGIC_VECTOR(CFG_GRGPIO_WIDTH-1 DOWNTO 0); -- I/O port
77 77
78 78 emddis : OUT STD_LOGIC;
79 79 epwrdwn : OUT STD_ULOGIC;
80 80 ereset : OUT STD_ULOGIC;
81 81 esleep : OUT STD_ULOGIC;
82 82 epause : OUT STD_ULOGIC;
83 83
84 84 pci_rst : INOUT STD_LOGIC; -- PCI bus
85 85 pci_clk : IN STD_ULOGIC;
86 86 pci_gnt : IN STD_ULOGIC;
87 87 pci_idsel : IN STD_ULOGIC;
88 88 pci_lock : INOUT STD_ULOGIC;
89 89 pci_ad : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 90 pci_cbe : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
91 91 pci_frame : INOUT STD_ULOGIC;
92 92 pci_irdy : INOUT STD_ULOGIC;
93 93 pci_trdy : INOUT STD_ULOGIC;
94 94 pci_devsel : INOUT STD_ULOGIC;
95 95 pci_stop : INOUT STD_ULOGIC;
96 96 pci_perr : INOUT STD_ULOGIC;
97 97 pci_par : INOUT STD_ULOGIC;
98 98 pci_req : INOUT STD_ULOGIC;
99 99 pci_serr : INOUT STD_ULOGIC;
100 100 pci_host : IN STD_ULOGIC;
101 101 pci_66 : IN STD_ULOGIC;
102 102 pci_arb_req : IN STD_LOGIC_VECTOR(0 TO 3);
103 103 pci_arb_gnt : OUT STD_LOGIC_VECTOR(0 TO 3);
104 104
105 105 spw_clk : IN STD_ULOGIC;
106 106 spw_rxd : IN STD_LOGIC_VECTOR(0 TO 2);
107 107 spw_rxdn : IN STD_LOGIC_VECTOR(0 TO 2);
108 108 spw_rxs : IN STD_LOGIC_VECTOR(0 TO 2);
109 109 spw_rxsn : IN STD_LOGIC_VECTOR(0 TO 2);
110 110 spw_txd : OUT STD_LOGIC_VECTOR(0 TO 2);
111 111 spw_txdn : OUT STD_LOGIC_VECTOR(0 TO 2);
112 112 spw_txs : OUT STD_LOGIC_VECTOR(0 TO 2);
113 113 spw_txsn : OUT STD_LOGIC_VECTOR(0 TO 2);
114 114
115 115 ramclk : OUT STD_LOGIC;
116 116
117 117 nBWa : OUT STD_LOGIC;
118 118 nBWb : OUT STD_LOGIC;
119 119 nBWc : OUT STD_LOGIC;
120 120 nBWd : OUT STD_LOGIC;
121 121 nBWE : OUT STD_LOGIC;
122 122 nADSC : OUT STD_LOGIC;
123 123 nADSP : OUT STD_LOGIC;
124 124 nADV : OUT STD_LOGIC;
125 125 nGW : OUT STD_LOGIC;
126 126 nCE1 : OUT STD_LOGIC;
127 127 CE2 : OUT STD_LOGIC;
128 128 nCE3 : OUT STD_LOGIC;
129 129 nOE : OUT STD_LOGIC;
130 130 MODE : OUT STD_LOGIC;
131 131 SSRAM_CLK : OUT STD_LOGIC;
132 132 ZZ : OUT STD_LOGIC;
133 133
134 134 tck, tms, tdi : IN STD_ULOGIC;
135 135 tdo : OUT STD_ULOGIC
136 136 );
137 137 END;
138 138
139 139 ARCHITECTURE rtl OF leon3mp IS
140 140
141 141 CONSTANT blength : INTEGER := 12;
142 142
143 143 CONSTANT maxahbmsp : INTEGER := NCPU+CFG_AHB_UART+
144 144 CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI);
145 145 CONSTANT maxahbm : INTEGER := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp + 1; -- +LPP_DMA
146 146
147 147
148 148
149 149 SIGNAL vcc, gnd : STD_LOGIC_VECTOR(4 DOWNTO 0);
150 150 SIGNAL memi : memory_in_type;
151 151 SIGNAL memo : memory_out_type;
152 152 SIGNAL wpo : wprot_out_type;
153 153 SIGNAL sdi : sdctrl_in_type;
154 154 SIGNAL sdo : sdram_out_type;
155 155 SIGNAL sdo2, sdo3 : sdctrl_out_type;
156 156
157 157 SIGNAL apbi : apb_slv_in_type;
158 158 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
159 159 SIGNAL ahbsi : ahb_slv_in_type;
160 160 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
161 161 SIGNAL ahbmi : ahb_mst_in_type;
162 162 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
163 163
164 164 SIGNAL clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : STD_ULOGIC;
165 165 SIGNAL cgi : clkgen_in_type;
166 166 SIGNAL cgo : clkgen_out_type;
167 167 SIGNAL u1i, u2i, dui : uart_in_type;
168 168 SIGNAL u1o, u2o, duo : uart_out_type;
169 169
170 170 SIGNAL irqi : irq_in_vector(0 TO NCPU-1);
171 171 SIGNAL irqo : irq_out_vector(0 TO NCPU-1);
172 172
173 173 SIGNAL dbgi : l3_debug_in_vector(0 TO NCPU-1);
174 174 SIGNAL dbgo : l3_debug_out_vector(0 TO NCPU-1);
175 175
176 176 SIGNAL dsui : dsu_in_type;
177 177 SIGNAL dsuo : dsu_out_type;
178 178
179 179 SIGNAL pcii : pci_in_type;
180 180 SIGNAL pcio : pci_out_type;
181 181
182 182 SIGNAL ethi, ethi1, ethi2 : eth_in_type;
183 183 SIGNAL etho, etho1, etho2 : eth_out_type;
184 184
185 185 SIGNAL gpti : gptimer_in_type;
186 186
187 187 SIGNAL gpioi : gpio_in_type;
188 188 SIGNAL gpioo : gpio_out_type;
189 189
190 190
191 191 SIGNAL lclk, pci_lclk : STD_ULOGIC := '0';
192 192 SIGNAL pci_arb_req_n, pci_arb_gnt_n : STD_LOGIC_VECTOR(0 TO 3);
193 193
194 194 SIGNAL spwi : grspw_in_type_vector(0 TO 2);
195 195 SIGNAL spwo : grspw_out_type_vector(0 TO 2);
196 196 SIGNAL spw_rx_clk : STD_ULOGIC;
197 197
198 198 ATTRIBUTE sync_set_reset : STRING;
199 199 ATTRIBUTE sync_set_reset OF rstn : SIGNAL IS "true";
200 200
201 201 CONSTANT BOARD_FREQ : INTEGER := 40000; -- Board frequency in KHz
202 202 CONSTANT CPU_FREQ : INTEGER := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;
203 203 CONSTANT IOAEN : INTEGER := CFG_SDCTRL;
204 204 CONSTANT CFG_SDEN : INTEGER := CFG_SDCTRL + CFG_MCTRL_SDEN;
205 205
206 206 CONSTANT sysfreq : INTEGER := (CFG_CLKMUL/CFG_CLKDIV)*40000;
207 207
208 208 -----------------------------------------------------------------------------
209 209
210 210 SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
211 211 SIGNAL fifo_empty : STD_LOGIC;
212 212 SIGNAL fifo_ren : STD_LOGIC;
213 213 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
214 214 SIGNAL dma_empty : STD_LOGIC;
215 215 SIGNAL dma_ren : STD_LOGIC;
216 216 SIGNAL header : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 217 SIGNAL header_val : STD_LOGIC;
218 218 SIGNAL header_ack : STD_LOGIC;
219 219
220 220 SIGNAL lclk2x : STD_ULOGIC;
221 221 SIGNAL clk2x : STD_ULOGIC;
222 222
223 223 CONSTANT boardfreq : INTEGER := 50000;
224 224
225 225 BEGIN
226 226
227 227 ----------------------------------------------------------------------
228 228 --- Reset and Clock generation -------------------------------------
229 229 ----------------------------------------------------------------------
230 230
231 231 vcc <= (OTHERS => '1');
232 232 gnd <= (OTHERS => '0');
233 233 cgi.pllctrl <= "00";
234 234 cgi.pllrst <= rstraw;
235 235
236 236 pllref_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (pllref, cgi.pllref);
237 237
238 238 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk2x);
239 239
240 240 PROCESS(lclk2x)
241 241 BEGIN
242 242 IF lclk2x'EVENT AND lclk2x = '1' THEN
243 243 lclk <= NOT lclk;
244 244 END IF;
245 245 END PROCESS;
246 246
247 247 pci_clk_pad : clkpad GENERIC MAP (tech => padtech, level => pci33) PORT MAP (pci_clk, pci_lclk);
248 248
249 249 clkgen0 : clkgen -- clock generator
250 250 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
251 251 PORT MAP (lclk, lclk, clkm, OPEN, clk2x, sdclkl, pciclk, cgi, cgo);
252 252
253 253 ramclk <= clkm;
254 254
255 255 rst0 : rstgen -- reset generator
256 256 PORT MAP (resetn, clkm, cgo.clklock, rstn, rstraw);
257 257
258 258 ----------------------------------------------------------------------
259 259 --- AHB CONTROLLER --------------------------------------------------
260 260 ----------------------------------------------------------------------
261 261
262 262 ahb0 : ahbctrl -- AHB arbiter/multiplexer
263 263 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
264 264 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
265 265 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
266 266 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
267 267
268 268 ----------------------------------------------------------------------
269 269 --- LEON3 processor and DSU -----------------------------------------
270 270 ----------------------------------------------------------------------
271 271
272 272 l3 : IF CFG_LEON3 = 1 GENERATE
273 273 cpu : FOR i IN 0 TO NCPU-1 GENERATE
274 274 u0 : leon3s -- LEON3 processor
275 275 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
276 276 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
277 277 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
278 278 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
279 279 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
280 280 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1, CFG_DFIXED)
281 281 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
282 282 irqi(i), irqo(i), dbgi(i), dbgo(i));
283 283 END GENERATE;
284 284 errorn_pad : odpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
285 285
286 286
287 287 dsugen : IF CFG_DSU = 1 GENERATE
288 288 dsu0 : dsu3 -- LEON3 Debug Support Unit
289 289 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
290 290 ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
291 291 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
292 292 dsuen_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsuen, dsui.enable);
293 293 dsubre_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsubre, dsui.break);
294 294 dsuact_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (dsuact, dsuo.active);
295 295 END GENERATE;
296 296 END GENERATE;
297 297
298 298 nodsu : IF CFG_DSU = 0 GENERATE
299 299 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
300 300 END GENERATE;
301 301
302 302 dcomgen : IF CFG_AHB_UART = 1 GENERATE
303 303 dcom0 : ahbuart -- Debug UART
304 304 GENERIC MAP (hindex => NCPU, pindex => 7, paddr => 7)
305 305 PORT MAP (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
306 306 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsurx, dui.rxd);
307 307 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (dsutx, duo.txd);
308 308 END GENERATE;
309 309 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(7) <= apb_none; END GENERATE;
310 310
311 311 ahbjtaggen0 : IF CFG_AHB_JTAG = 1 GENERATE
312 312 ahbjtag0 : ahbjtag GENERIC MAP(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
313 313 PORT MAP(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
314 314 OPEN, OPEN, OPEN, OPEN, OPEN, OPEN, OPEN, gnd(0));
315 315 END GENERATE;
316 316
317 317 ----------------------------------------------------------------------
318 318 --- Memory controllers ----------------------------------------------
319 319 ----------------------------------------------------------------------
320 320 -- LEON2 memory controller
321 321 sr1 : mctrl
322 322 GENERIC MAP (
323 323 hindex => 0,
324 324 pindex => 0,
325 325 romaddr => 16#000#,
326 326 rommask => 16#E00#,
327 327 ioaddr => 16#200#,
328 328 iomask => 16#E00#,
329 329 ramaddr => 16#400#,
330 330 rammask => 16#C00#,
331 331 paddr => 0,
332 332 pmask => 16#fff#,
333 333 wprot => 0,
334 334 invclk => 0,
335 335 fast => 0,
336 336 romasel => 28,
337 337 sdrasel => 29,
338 338 srbanks => 4,
339 339 ram8 => 0,
340 340 ram16 => 0,
341 341 sden => 0,
342 342 sepbus => 0,
343 343 sdbits => 32,
344 344 sdlsb => 2, -- set to 12 for the GE-HPE board
345 345 oepol => 0,
346 346 syncrst => 0,
347 347 pageburst => 0,
348 348 scantest => 0,
349 349 mobile => 0
350 350 )
351 351 PORT MAP (
352 352 rst => rstn,
353 353 clk => clkm,
354 354 memi => memi,
355 355 memo => memo,
356 356 ahbsi => ahbsi,
357 357 ahbso => ahbso(0),
358 358 apbi => apbi,
359 359 apbo => apbo(0),
360 360 wpo => wpo,
361 361 sdo => sdo
362 362 );
363 363
364 364
365 365 memi.brdyn <= '1'; memi.bexcn <= '1';
366 366 memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
367 367
368 368 mgpads : IF (CFG_SRCTRL = 1) OR (CFG_MCTRL_LEON2 = 1) GENERATE -- prom/sram pads
369 369 addr_pad : outpadv GENERIC MAP (width => 28, tech => padtech) PORT MAP (address, memo.address(27 DOWNTO 0));
370 370 rams_pad : outpadv GENERIC MAP (width => 5, tech => padtech) PORT MAP (ramsn, memo.ramsn(4 DOWNTO 0));
371 371 roms_pad : outpadv GENERIC MAP (width => 2, tech => padtech) PORT MAP (romsn, memo.romsn(1 DOWNTO 0));
372 372 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (oen, memo.oen);
373 373 rwen_pad : outpadv GENERIC MAP (width => 4, tech => padtech) PORT MAP (rwen, memo.wrn);
374 374 roen_pad : outpadv GENERIC MAP (width => 5, tech => padtech) PORT MAP (ramoen, memo.ramoen(4 DOWNTO 0));
375 375 wri_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (writen, memo.writen);
376 376 read_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (read, memo.read);
377 377 iosn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (iosn, memo.iosn);
378 378
379 379 bdr : FOR i IN 0 TO 3 GENERATE
380 380 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
381 381 PORT MAP (data(31-i*8 DOWNTO 24-i*8), memo.data(31-i*8 DOWNTO 24-i*8),
382 382 memo.bdrive(i), memi.data(31-i*8 DOWNTO 24-i*8));
383 383 END GENERATE;
384 384
385 385 END GENERATE;
386 386
387 387 SSRAM_0 : ssram_plugin
388 388 GENERIC MAP (tech => padtech)
389 389 PORT MAP (lclk2x, memo, SSRAM_CLK,
390 390 nBWa, nBWb, nBWc, nBWd, nBWE, nADSC, nADSP, nADV, nGW, nCE1, CE2, nCE3, nOE, MODE, ZZ);
391 391
392 392
393 393
394 394 ----------------------------------------------------------------------
395 395 --- APB Bridge and various periherals -------------------------------
396 396 ----------------------------------------------------------------------
397 397
398 398 apb0 : apbctrl -- AHB/APB bridge
399 399 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
400 400 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
401 401
402 402 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
403 403 uart1 : apbuart -- UART 1
404 404 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
405 405 fifosize => CFG_UART1_FIFO)
406 406 PORT MAP (rstn, clkm, apbi, apbo(1), u1i, u1o);
407 407 u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
408 408 END GENERATE;
409 409 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
410 410
411 411 ua2 : IF CFG_UART2_ENABLE /= 0 GENERATE
412 412 uart2 : apbuart -- UART 2
413 413 GENERIC MAP (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
414 414 PORT MAP (rstn, clkm, apbi, apbo(9), u2i, u2o);
415 415 u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
416 416 END GENERATE;
417 417 noua1 : IF CFG_UART2_ENABLE = 0 GENERATE apbo(9) <= apb_none; END GENERATE;
418 418
419 419 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
420 420 irqctrl0 : irqmp -- interrupt controller
421 421 GENERIC MAP (pindex => 2, paddr => 2, ncpu => NCPU)
422 422 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
423 423 END GENERATE;
424 424 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
425 425 x : FOR i IN 0 TO NCPU-1 GENERATE
426 426 irqi(i).irl <= "0000";
427 427 END GENERATE;
428 428 apbo(2) <= apb_none;
429 429 END GENERATE;
430 430
431 431 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
432 432 timer0 : gptimer -- timer unit
433 433 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
434 434 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
435 435 nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG)
436 436 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, OPEN);
437 437 gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
438 438 END GENERATE;
439 439 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
440 440
441 441 gpio0 : IF CFG_GRGPIO_ENABLE /= 0 GENERATE -- GR GPIO unit
442 442 grgpio0 : grgpio
443 443 GENERIC MAP(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
444 444 nbits => CFG_GRGPIO_WIDTH)
445 445 PORT MAP(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
446 446
447 447 pio_pads : FOR i IN 0 TO CFG_GRGPIO_WIDTH-1 GENERATE
448 448 pio_pad : iopad GENERIC MAP (tech => padtech)
449 449 PORT MAP (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
450 450 END GENERATE;
451 451 END GENERATE;
452 452
453 453 -----------------------------------------------------------------------
454 454 --- PCI ------------------------------------------------------------
455 455 -----------------------------------------------------------------------
456 456
457 457 pp : IF CFG_PCI /= 0 GENERATE
458 458
459 459 pci_gr0 : IF CFG_PCI = 1 GENERATE -- simple target-only
460 460 pci0 : pci_target GENERIC MAP (hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
461 461 device_id => CFG_PCIDID, vendor_id => CFG_PCIVID)
462 462 PORT MAP (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
463 463 END GENERATE;
464 464
465 465 pci_mtf0 : IF CFG_PCI = 2 GENERATE -- master/target with fifo
466 466 pci0 : pci_mtf GENERIC MAP (memtech => memtech, hmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
467 467 fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
468 468 hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#,
469 469 ioaddr => 16#400#, nsync => 2, hostrst => 1)
470 470 PORT MAP (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
471 471 ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
472 472 END GENERATE;
473 473
474 474 pci_mtf1 : IF CFG_PCI = 3 GENERATE -- master/target with fifo and DMA
475 475 dma : pcidma GENERIC MAP (memtech => memtech, dmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
476 476 dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
477 477 fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
478 478 slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
479 479 nsync => 2, hostrst => 1)
480 480 PORT MAP (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
481 481 apbi, apbo(4), ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
482 482 END GENERATE;
483 483
484 484 pci_trc0 : IF CFG_PCITBUFEN /= 0 GENERATE -- PCI trace buffer
485 485 pt0 : pcitrace GENERIC MAP (depth => (6 + log2(CFG_PCITBUF/256)),
486 486 memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#)
487 487 PORT MAP (rstn, clkm, pciclk, pcii, apbi, apbo(8));
488 488 END GENERATE;
489 489
490 490 pcia0 : IF CFG_PCI_ARB = 1 GENERATE -- PCI arbiter
491 491 pciarb0 : pciarb GENERIC MAP (pindex => 10, paddr => 10,
492 492 apb_en => CFG_PCI_ARBAPB)
493 493 PORT MAP (clk => pciclk, rst_n => pcii.rst,
494 494 req_n => pci_arb_req_n, frame_n => pcii.frame,
495 495 gnt_n => pci_arb_gnt_n, pclk => clkm,
496 496 prst_n => rstn, apbi => apbi, apbo => apbo(10)
497 497 );
498 498 pgnt_pad : outpadv GENERIC MAP (tech => padtech, width => 4)
499 499 PORT MAP (pci_arb_gnt, pci_arb_gnt_n);
500 500 preq_pad : inpadv GENERIC MAP (tech => padtech, width => 4)
501 501 PORT MAP (pci_arb_req, pci_arb_req_n);
502 502 END GENERATE;
503 503
504 504 pcipads0 : pcipads GENERIC MAP (padtech => padtech) -- PCI pads
505 505 PORT MAP (pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
506 506 pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
507 507 pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio);
508 508
509 509 END GENERATE;
510 510
511 511 -- nop1 : IF CFG_PCI <= 1 GENERATE apbo(4) <= apb_none; END GENERATE;
512 512 -- nop2 : IF CFG_PCI <= 2 GENERATE apbo(5) <= apb_none; END GENERATE;
513 513 nop3 : IF CFG_PCI <= 1 GENERATE ahbso(4) <= ahbs_none; END GENERATE;
514 514 notrc : IF CFG_PCITBUFEN = 0 GENERATE apbo(8) <= apb_none; END GENERATE;
515 515 noarb : IF CFG_PCI_ARB = 0 GENERATE apbo(10) <= apb_none; END GENERATE;
516 516
517 517
518 518 -- ahbso(6) <= ahbs_none;
519 519
520 520 -----------------------------------------------------------------------
521 521 --- AHB RAM ----------------------------------------------------------
522 522 -----------------------------------------------------------------------
523 523
524 524 ocram : IF CFG_AHBRAMEN = 1 GENERATE
525 525 ahbram0 : ahbram GENERIC MAP (hindex => 7, haddr => CFG_AHBRADDR,
526 526 tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
527 527 PORT MAP (rstn, clkm, ahbsi, ahbso(7));
528 528 END GENERATE;
529 529 nram : IF CFG_AHBRAMEN = 0 GENERATE ahbso(7) <= ahbs_none; END GENERATE;
530 530
531 531 -----------------------------------------------------------------------
532 532 --- SPACEWIRE -------------------------------------------------------
533 533 -----------------------------------------------------------------------
534 534 --This template does NOT currently support grspw2 so only use grspw1
535 535 spw : IF CFG_SPW_EN > 0 GENERATE
536 536 spw_rx_clk <= '0';
537 537 spw_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (spw_clk, spw_lclk);
538 538 swloop : FOR i IN 0 TO CFG_SPW_NUM-1 GENERATE
539 539 sw0 : grspwm GENERIC MAP(tech => memtech, netlist => CFG_SPW_NETLIST,
540 540 hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i,
541 541 sysfreq => sysfreq, nsync => 1, rmap => 0, ports => 1, dmachan => 1,
542 542 fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO,
543 543 rxclkbuftype => 1, spwcore => CFG_SPW_GRSPW)
544 544 PORT MAP(resetn, clkm, spw_rx_clk, spw_rx_clk, spw_lclk, spw_lclk,
545 545 ahbmi, ahbmo(maxahbmsp+i),
546 546 apbi, apbo(12+i), spwi(i), spwo(i));
547 547 spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
548 548 spwi(i).clkdiv10 <= conv_std_logic_vector(sysfreq/10000-1, 8);
549 549 spw_rxd_pad : inpad_ds GENERIC MAP (padtech, lvds, x25v)
550 550 PORT MAP (spw_rxd(i), spw_rxdn(i), spwi(i).d(0));
551 551 spw_rxs_pad : inpad_ds GENERIC MAP (padtech, lvds, x25v)
552 552 PORT MAP (spw_rxs(i), spw_rxsn(i), spwi(i).s(0));
553 553 spw_txd_pad : outpad_ds GENERIC MAP (padtech, lvds, x25v)
554 554 PORT MAP (spw_txd(i), spw_txdn(i), spwo(i).d(0), gnd(0));
555 555 spw_txs_pad : outpad_ds GENERIC MAP (padtech, lvds, x25v)
556 556 PORT MAP (spw_txs(i), spw_txsn(i), spwo(i).s(0), gnd(0));
557 557 END GENERATE;
558 558 END GENERATE;
559 559
560 560
561 561
562 562 -------------------------------------------------------------------------------
563 563 -- BOOT MEMORY AND REGISTER
564 564 -------------------------------------------------------------------------------
565 565
566 566 lpp_bootloader_1: lpp_bootloader
567 567 GENERIC MAP (
568 568 pindex => 13,
569 569 paddr => 13,
570 570 pmask => 16#fff#,
571 571
572 572 hindex => 6,
573 573 haddr => 16#900#,
574 574 hmask => 16#F00#)
575 575 PORT MAP (
576 576 HCLK => clkm,
577 577 HRESETn => resetn,
578 578 apbi => apbi,
579 579 apbo => apbo(13),
580 580 ahbsi => ahbsi,
581 581 ahbso => ahbso(6));
582 582
583 583
584 584 -------------------------------------------------------------------------------
585 585 -- AHB DMA
586 586 -------------------------------------------------------------------------------
587 587
588 588 lpp_dma_1 : lpp_dma
589 589 GENERIC MAP (
590 590 tech => fabtech,
591 591 hindex => 2,
592 592 pindex => 14,
593 593 paddr => 14,
594 594 pmask => 16#fff#,
595 595 pirq => 0)
596 596 PORT MAP (
597 597 HCLK => clkm,
598 598 HRESETn => resetn,
599 599 apbi => apbi,
600 600 apbo => apbo(14),
601 601 AHB_Master_In => ahbmi,
602 602 AHB_Master_Out => ahbmo(2),
603 603 fifo_data => fifo_data, --dma_data,
604 604 fifo_empty => fifo_empty, --dma_empty,
605 605 fifo_ren => fifo_ren, --dma_ren,
606 606 header => header,
607 607 header_val => header_val,
608 608 header_ack => header_ack);
609 609
610 --fifo_latency_correction_1 : fifo_latency_correction
611 -- PORT MAP (
612 -- HCLK => clkm,
613 -- HRESETn => resetn,
614 -- fifo_data => fifo_data,
615 -- fifo_empty => fifo_empty,
616 -- fifo_ren => fifo_ren,
617 -- dma_data => dma_data,
618 -- dma_empty => dma_empty,
619 -- dma_ren => dma_ren);
620
621 610 fifo_test_dma_1 : fifo_test_dma
622 611 GENERIC MAP (
623 612 tech => fabtech,
624 613 pindex => 15,
625 614 paddr => 15,
626 615 pmask => 16#fff#)
627 616 PORT MAP (
628 617 HCLK => clkm,
629 618 HRESETn => resetn,
630 619 apbi => apbi,
631 620 apbo => apbo(15),
632 621 fifo_data => fifo_data,
633 622 fifo_empty => fifo_empty,
634 623 fifo_ren => fifo_ren,
635 624 header => header,
636 625 header_val => header_val,
637 626 header_ack => header_ack);
638 627
639 628 -----------------------------------------------------------------------
640 629 --- Boot message ----------------------------------------------------
641 630 -----------------------------------------------------------------------
642 631
643 632 -- pragma translate_off
644 633 x : report_version
645 634 GENERIC MAP (
646 635 msg1 => "LEON3 MP Demonstration design",
647 636 msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION MOD 1000)/100)
648 637 & "." & tost(LIBVHDL_VERSION MOD 100) & ", build " & tost(LIBVHDL_BUILD),
649 638 msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
650 639 mdel => 1
651 640 );
652 641 -- pragma translate_on
653 642 END;
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@@ -1,21 +1,21
1 1 ./amba_lcd_16x2_ctrlr
2 ./dsp/iir_filter
3 ./dsp/lpp_downsampling
4 ./dsp/lpp_fft
5 2 ./general_purpose
6 3 ./general_purpose/lpp_AMR
7 4 ./general_purpose/lpp_balise
8 5 ./general_purpose/lpp_delay
6 ./lpp_amba
7 ./dsp/iir_filter
8 ./dsp/lpp_downsampling
9 ./dsp/lpp_fft
9 10 ./lfr_time_management
10 11 ./lpp_ad_Conv
11 ./lpp_amba
12 12 ./lpp_bootloader
13 13 ./lpp_cna
14 14 ./lpp_demux
15 ./lpp_dma
16 15 ./lpp_matrix
17 16 ./lpp_memory
18 ./lpp_top_lfr
17 ./lpp_dma
19 18 ./lpp_uart
20 19 ./lpp_usb
21 20 ./lpp_waveform
21 ./lpp_top_lfr
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@@ -1,18 +1,18
1 general_purpose.vhd
1 2 ADDRcntr.vhd
2 3 ALU.vhd
3 4 Adder.vhd
4 5 Clk_Divider2.vhd
5 6 Clk_divider.vhd
6 7 MAC.vhd
7 8 MAC_CONTROLER.vhd
8 9 MAC_MUX.vhd
9 10 MAC_MUX2.vhd
10 11 MAC_REG.vhd
11 12 MUX2.vhd
12 13 MUXN.vhd
13 14 Multiplier.vhd
14 15 REG.vhd
15 16 SYNC_FF.vhd
16 17 Shifter.vhd
17 general_purpose.vhd
18 18 TwoComplementer.vhd
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@@ -1,174 +1,208
1 1 ----------------------------------------------------------------------------------
2 2 -- Company:
3 3 -- Engineer:
4 4 --
5 5 -- Create Date: 11:17:05 07/02/2012
6 6 -- Design Name:
7 7 -- Module Name: apb_lfr_time_management - Behavioral
8 8 -- Project Name:
9 9 -- Target Devices:
10 10 -- Tool versions:
11 11 -- Description:
12 12 --
13 13 -- Dependencies:
14 14 --
15 15 -- Revision:
16 16 -- Revision 0.01 - File Created
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 20 LIBRARY IEEE;
21 21 USE IEEE.STD_LOGIC_1164.ALL;
22 22 USE IEEE.NUMERIC_STD.ALL;
23 23 LIBRARY grlib;
24 24 USE grlib.amba.ALL;
25 25 USE grlib.stdlib.ALL;
26 26 USE grlib.devices.ALL;
27 27 LIBRARY lpp;
28 28 USE lpp.apb_devices_list.ALL;
29 29 USE lpp.lpp_lfr_time_management.ALL;
30 30
31 31 ENTITY apb_lfr_time_management IS
32 32
33 33 GENERIC(
34 34 pindex : INTEGER := 0; --! APB slave index
35 35 paddr : INTEGER := 0; --! ADDR field of the APB BAR
36 36 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 37 pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used
38 38 masterclk : INTEGER := 25000000; --! master clock in Hz
39 otherclk : INTEGER := 49152000; --! other clock in Hz
39 timeclk : INTEGER := 49152000; --! other clock in Hz
40 40 finetimeclk : INTEGER := 65536 --! divided clock used for the fine time counter
41 41 );
42 42
43 43 PORT (
44 44 clk25MHz : IN STD_LOGIC; --! Clock
45 45 clk49_152MHz : IN STD_LOGIC; --! secondary clock
46 46 resetn : IN STD_LOGIC; --! Reset
47 47 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
48 48 apbi : IN apb_slv_in_type; --! APB slave input signals
49 49 apbo : OUT apb_slv_out_type; --! APB slave output signals
50 50 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
51 51 fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --! fine time
52 52 );
53 53
54 54 END apb_lfr_time_management;
55 55
56 56 ARCHITECTURE Behavioral OF apb_lfr_time_management IS
57 57
58 58 CONSTANT REVISION : INTEGER := 1;
59 59
60 60 --! the following types are defined in the grlib amba package
61 61 --! subtype amba_config_word is std_logic_vector(31 downto 0);
62 62 --! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word;
63 63 CONSTANT pconfig : apb_config_type := (
64 64 --! 0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0),
65 0 => ahb_device_reg (19, 14, 0, REVISION, pirq),
65 0 => ahb_device_reg (VENDOR_LPP, 0, 0, REVISION, pirq),
66 66 1 => apb_iobar(paddr, pmask));
67 67
68 68 TYPE apb_lfr_time_management_Reg IS RECORD
69 69 ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0);
70 70 coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
71 71 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
72 72 fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
73 73 next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0);
74 74 END RECORD;
75 75
76 76 SIGNAL r : apb_lfr_time_management_Reg;
77 77 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
78 78 SIGNAL force_tick : STD_LOGIC;
79 79 SIGNAL previous_force_tick : STD_LOGIC;
80 80 SIGNAL soft_tick : STD_LOGIC;
81 81 SIGNAL reset_next_commutation : STD_LOGIC;
82 82
83 SIGNAL irq1 : STD_LOGIC;
84 SIGNAL irq2 : STD_LOGIC;
85
83 86 BEGIN
84 87
85 88 lfrtimemanagement0 : lfr_time_management
86 GENERIC MAP(masterclk => masterclk, timeclk => otherclk, finetimeclk => finetimeclk)
87 PORT MAP(master_clock => clk25MHz, time_clock => clk49_152MHz, resetn => resetn,
88 grspw_tick => grspw_tick, soft_tick => soft_tick,
89 coarse_time_load => r.coarse_time_load, coarse_time => r.coarse_time, fine_time => r.fine_time,
90 next_commutation => r.next_commutation, reset_next_commutation => reset_next_commutation,
91 irq1 => apbo.pirq(pirq), irq2 => apbo.pirq(pirq+1));
89 GENERIC MAP(
90 masterclk => masterclk,
91 timeclk => timeclk,
92 finetimeclk => finetimeclk,
93 nb_clk_div_ticks => 1)
94 PORT MAP(
95 master_clock => clk25MHz,
96 time_clock => clk49_152MHz,
97 resetn => resetn,
98 grspw_tick => grspw_tick,
99 soft_tick => soft_tick,
100 coarse_time_load => r.coarse_time_load,
101 coarse_time => r.coarse_time,
102 fine_time => r.fine_time,
103 next_commutation => r.next_commutation,
104 reset_next_commutation => reset_next_commutation,
105 irq1 => irq1,--apbo.pirq(pirq),
106 irq2 => irq2);--apbo.pirq(pirq+1));
107
108 --apbo.pirq <= (OTHERS => '0');
109
110 all_irq_gen: FOR I IN 15 DOWNTO 0 GENERATE
111 irq1_gen: IF I = pirq GENERATE
112 apbo.pirq(I) <= irq1;
113 END GENERATE irq1_gen;
114 irq2_gen: IF I = pirq+1 GENERATE
115 apbo.pirq(I) <= irq2;
116 END GENERATE irq2_gen;
117 others_irq: IF (I < pirq) OR (I > (pirq + 1)) GENERATE
118 apbo.pirq(I) <= '0';
119 END GENERATE others_irq;
120 END GENERATE all_irq_gen;
121
122 --all_irq_sig: FOR I IN 31 DOWNTO 0 GENERATE
123 --END GENERATE all_irq_sig;
92 124
93 125 PROCESS(resetn, clk25MHz, reset_next_commutation)
94 126 BEGIN
95 127
96 128 IF resetn = '0' THEN
129 Rdata <= (OTHERS => '0');
97 130 r.coarse_time_load <= x"80000000";
98 131 r.ctrl <= x"00000000";
99 132 r.next_commutation <= x"ffffffff";
100 133 force_tick <= '0';
101 134 previous_force_tick <= '0';
102 135 soft_tick <= '0';
103 136
104 137 ELSIF reset_next_commutation = '1' THEN
105 138 r.next_commutation <= x"ffffffff";
106 139
107 140 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
108 141
109 142 previous_force_tick <= force_tick;
110 143 force_tick <= r.ctrl(0);
111 144 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
112 145 soft_tick <= '1';
113 146 ELSE
114 147 soft_tick <= '0';
115 148 END IF;
116 149
117 150 --APB Write OP
118 151 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
119 152 CASE apbi.paddr(7 DOWNTO 2) IS
120 153 WHEN "000000" =>
121 154 r.ctrl <= apbi.pwdata(31 DOWNTO 0);
122 155 WHEN "000001" =>
123 156 r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0);
124 157 WHEN "000100" =>
125 158 r.next_commutation <= apbi.pwdata(31 DOWNTO 0);
126 159 WHEN OTHERS =>
127 160 r.coarse_time_load <= x"00000000";
128 161 END CASE;
129 162 ELSIF r.ctrl(0) = '1' THEN
130 163 r.ctrl(0) <= '0';
131 164 END IF;
132 165
133 166 --APB READ OP
134 167 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
135 168 CASE apbi.paddr(7 DOWNTO 2) IS
136 169 WHEN "000000" =>
137 170 Rdata(31 DOWNTO 24) <= r.ctrl(31 DOWNTO 24);
138 171 Rdata(23 DOWNTO 16) <= r.ctrl(23 DOWNTO 16);
139 172 Rdata(15 DOWNTO 8) <= r.ctrl(15 DOWNTO 8);
140 173 Rdata(7 DOWNTO 0) <= r.ctrl(7 DOWNTO 0);
141 174 WHEN "000001" =>
142 175 Rdata(31 DOWNTO 24) <= r.coarse_time_load(31 DOWNTO 24);
143 176 Rdata(23 DOWNTO 16) <= r.coarse_time_load(23 DOWNTO 16);
144 177 Rdata(15 DOWNTO 8) <= r.coarse_time_load(15 DOWNTO 8);
145 178 Rdata(7 DOWNTO 0) <= r.coarse_time_load(7 DOWNTO 0);
146 179 WHEN "000010" =>
147 180 Rdata(31 DOWNTO 24) <= r.coarse_time(31 DOWNTO 24);
148 181 Rdata(23 DOWNTO 16) <= r.coarse_time(23 DOWNTO 16);
149 182 Rdata(15 DOWNTO 8) <= r.coarse_time(15 DOWNTO 8);
150 183 Rdata(7 DOWNTO 0) <= r.coarse_time(7 DOWNTO 0);
151 184 WHEN "000011" =>
152 185 Rdata(31 DOWNTO 24) <= r.fine_time(31 DOWNTO 24);
153 186 Rdata(23 DOWNTO 16) <= r.fine_time(23 DOWNTO 16);
154 187 Rdata(15 DOWNTO 8) <= r.fine_time(15 DOWNTO 8);
155 188 Rdata(7 DOWNTO 0) <= r.fine_time(7 DOWNTO 0);
156 189 WHEN "000100" =>
157 190 Rdata(31 DOWNTO 24) <= r.next_commutation(31 DOWNTO 24);
158 191 Rdata(23 DOWNTO 16) <= r.next_commutation(23 DOWNTO 16);
159 192 Rdata(15 DOWNTO 8) <= r.next_commutation(15 DOWNTO 8);
160 193 Rdata(7 DOWNTO 0) <= r.next_commutation(7 DOWNTO 0);
161 194 WHEN OTHERS =>
162 195 Rdata(31 DOWNTO 0) <= x"00000000";
163 196 END CASE;
164 197 END IF;
165 198
166 199 END IF;
167 apbo.pconfig <= pconfig;
168 200 END PROCESS;
169 201
170 apbo.prdata <= Rdata WHEN apbi.penable = '1';
202 apbo.prdata <= Rdata ;--WHEN apbi.penable = '1';
171 203 coarse_time <= r.coarse_time;
172 204 fine_time <= r.fine_time;
205 apbo.pconfig <= pconfig;
206 apbo.pindex <= pindex;
173 207
174 208 END Behavioral;
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@@ -1,3 +1,3
1 apb_lfr_time_management.vhd
1 lpp_lfr_time_management.vhd
2 2 lfr_time_management.vhd
3 lpp_lfr_time_management.vhd
3 apb_lfr_time_management.vhd
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@@ -1,184 +1,187
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2011, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library gaisler;
25 25 use gaisler.misc.all;
26 26 use gaisler.memctrl.all;
27 27 library techmap;
28 28 use techmap.gencomp.all;
29 29 use techmap.allclkgen.all;
30 30
31 31
32 32
33 33
34 34 entity ssram_plugin is
35 35 generic (tech : integer := 0);
36 36 port
37 37 (
38 38 clk : in std_logic;
39 39 mem_ctrlr_o : in memory_out_type;
40 40 SSRAM_CLK : out std_logic;
41 41 nBWa : out std_logic;
42 42 nBWb : out std_logic;
43 43 nBWc : out std_logic;
44 44 nBWd : out std_logic;
45 45 nBWE : out std_logic;
46 46 nADSC : out std_logic;
47 47 nADSP : out std_logic;
48 48 nADV : out std_logic;
49 49 nGW : out std_logic;
50 50 nCE1 : out std_logic;
51 51 CE2 : out std_logic;
52 52 nCE3 : out std_logic;
53 53 nOE : out std_logic;
54 54 MODE : out std_logic;
55 55 ZZ : out std_logic
56 56 );
57 57 end entity;
58 58
59 59
60 60
61 61
62 62
63 63
64 64 architecture ar_ssram_plugin of ssram_plugin is
65 65
66 66
67 67 signal nADSPint : std_logic:='1';
68 68 signal nOEint : std_logic:='1';
69 69 signal RAMSN_reg: std_logic:='1';
70 70 signal OEreg : std_logic:='1';
71 71 signal nBWaint : std_logic:='1';
72 72 signal nBWbint : std_logic:='1';
73 73 signal nBWcint : std_logic:='1';
74 74 signal nBWdint : std_logic:='1';
75 75 signal nBWEint : std_logic:='1';
76 76 signal nCE1int : std_logic:='1';
77 77 signal CE2int : std_logic:='0';
78 78 signal nCE3int : std_logic:='1';
79 79
80 80 Type stateT is (idle,st1,st2,st3,st4);
81 81 signal state : stateT;
82 82
83 SIGNAL nclk : STD_LOGIC;
84
83 85 begin
84 86
85 87 process(clk , mem_ctrlr_o.RAMSN(0))
86 88 begin
87 89 if mem_ctrlr_o.RAMSN(0) ='1' then
88 90 state <= idle;
89 91 elsif clk ='1' and clk'event then
90 92 case state is
91 93 when idle =>
92 94 state <= st1;
93 95 when st1 =>
94 96 state <= st2;
95 97 when st2 =>
96 98 state <= st3;
97 99 when st3 =>
98 100 state <= st4;
99 101 when st4 =>
100 102 state <= st1;
101 103 end case;
102 104 end if;
103 105 end process;
104 106
107 nclk <= NOT clk;
105 108 ssram_clk_pad : outpad generic map (tech => tech)
106 port map (SSRAM_CLK,not clk);
109 port map (SSRAM_CLK,nclk);
107 110
108 111
109 112 nBWaint <= mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0);
110 113 nBWa_pad : outpad generic map (tech => tech)
111 114 port map (nBWa,nBWaint);
112 115
113 116 nBWbint <= mem_ctrlr_o.WRN(2)or mem_ctrlr_o.ramsn(0);
114 117 nBWb_pad : outpad generic map (tech => tech)
115 118 port map (nBWb, nBWbint);
116 119
117 120 nBWcint <= mem_ctrlr_o.WRN(1)or mem_ctrlr_o.ramsn(0);
118 121 nBWc_pad : outpad generic map (tech => tech)
119 122 port map (nBWc, nBWcint);
120 123
121 124 nBWdint <= mem_ctrlr_o.WRN(0)or mem_ctrlr_o.ramsn(0);
122 125 nBWd_pad : outpad generic map (tech => tech)
123 126 port map (nBWd, nBWdint);
124 127
125 128 nBWEint <= mem_ctrlr_o.WRITEN or mem_ctrlr_o.ramsn(0);
126 129 nBWE_pad : outpad generic map (tech => tech)
127 130 port map (nBWE, nBWEint);
128 131
129 132 nADSC_pad : outpad generic map (tech => tech)
130 133 port map (nADSC, '1');
131 134
132 135 --nADSPint <= not((RAMSN_reg xor mem_ctrlr_o.RAMSN(0)) and RAMSN_reg);
133 136 nADSPint <= '0' when state = st1 else '1';
134 137
135 138 process(clk)
136 139 begin
137 140 if clk'event and clk = '1' then
138 141 RAMSN_reg <= mem_ctrlr_o.RAMSN(0);
139 142 end if;
140 143 end process;
141 144
142 145 nADSP_pad : outpad generic map (tech => tech)
143 146 port map (nADSP, nADSPint);
144 147
145 148 nADV_pad : outpad generic map (tech => tech)
146 149 port map (nADV, '1');
147 150
148 151 nGW_pad : outpad generic map (tech => tech)
149 152 port map (nGW, '1');
150 153
151 154 nCE1int <= nADSPint or mem_ctrlr_o.address(31) or (not mem_ctrlr_o.address(30)) or mem_ctrlr_o.address(29) or mem_ctrlr_o.address(28);
152 155 CE2int <= (not mem_ctrlr_o.address(27)) and (not mem_ctrlr_o.address(26)) and (not mem_ctrlr_o.address(25)) and (not mem_ctrlr_o.address(24));
153 156 nCE3int <= mem_ctrlr_o.address(23) or mem_ctrlr_o.address(22) or mem_ctrlr_o.address(21) or mem_ctrlr_o.address(20);
154 157
155 158 nCE1_pad : outpad generic map (tech => tech)
156 159 port map (nCE1, nCE1int);
157 160
158 161 CE2_pad : outpad generic map (tech => tech)
159 162 port map (CE2, CE2int);
160 163
161 164 nCE3_pad : outpad generic map (tech => tech)
162 165 port map (nCE3, nCE3int);
163 166
164 167 nOE_pad : outpad generic map (tech => tech)
165 168 port map (nOE, nOEint);
166 169
167 170 process(clk)
168 171 begin
169 172 if clk'event and clk = '1' then
170 173 OEreg <= mem_ctrlr_o.OEN;
171 174 end if;
172 175 end process;
173 176
174 177
175 178 --nOEint <= OEreg or mem_ctrlr_o.RAMOEN(0);
176 179 nOEint <= '0' when state = st2 or state = st3 or state = st4 else '1';
177 180
178 181 MODE_pad : outpad generic map (tech => tech)
179 182 port map (MODE, '0');
180 183
181 184 ZZ_pad : outpad generic map (tech => tech)
182 185 port map (ZZ, '0');
183 186
184 end architecture; No newline at end of file
187 end architecture;
Show file before | Show file after | Hide comments
@@ -1,498 +1,502
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 10 USE lpp.lpp_waveform_pkg.ALL;
11 11
12 12 LIBRARY techmap;
13 13 USE techmap.gencomp.ALL;
14 14
15 15 LIBRARY grlib;
16 16 USE grlib.amba.ALL;
17 17 USE grlib.stdlib.ALL;
18 18 USE grlib.devices.ALL;
19 19 USE GRLIB.DMA2AHB_Package.ALL;
20 20
21 21 ENTITY lpp_top_lfr_wf_picker_ip IS
22 22 GENERIC(
23 23 hindex : INTEGER := 2;
24 24 nb_burst_available_size : INTEGER := 11;
25 25 nb_snapshot_param_size : INTEGER := 11;
26 26 delta_snapshot_size : INTEGER := 16;
27 27 delta_f2_f0_size : INTEGER := 10;
28 28 delta_f2_f1_size : INTEGER := 10;
29 29 tech : INTEGER := 0
30 30 );
31 31 PORT (
32 32 -- ADS7886
33 33 cnv_run : IN STD_LOGIC;
34 34 cnv : OUT STD_LOGIC;
35 35 sck : OUT STD_LOGIC;
36 36 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
37 37 --
38 38 cnv_clk : IN STD_LOGIC;
39 39 cnv_rstn : IN STD_LOGIC;
40 40 --
41 41 clk : IN STD_LOGIC;
42 42 rstn : IN STD_LOGIC;
43 43 --
44 44 sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
45 45 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
46 46 --
47 47 sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
48 48 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
49 49 --
50 50 sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
51 51 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
52 52 --
53 53 sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
54 54 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
55 55
56 56 -- AMBA AHB Master Interface
57 57 AHB_Master_In : IN AHB_Mst_In_Type;
58 58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59 59
60 60 coarse_time_0 : IN STD_LOGIC;
61 61
62 62 --config
63 63 data_shaping_SP0 : IN STD_LOGIC;
64 64 data_shaping_SP1 : IN STD_LOGIC;
65 65 data_shaping_R0 : IN STD_LOGIC;
66 66 data_shaping_R1 : IN STD_LOGIC;
67 67
68 68 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
69 69 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
70 70 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
71 71
72 72 enable_f0 : IN STD_LOGIC;
73 73 enable_f1 : IN STD_LOGIC;
74 74 enable_f2 : IN STD_LOGIC;
75 75 enable_f3 : IN STD_LOGIC;
76 76
77 77 burst_f0 : IN STD_LOGIC;
78 78 burst_f1 : IN STD_LOGIC;
79 79 burst_f2 : IN STD_LOGIC;
80 80
81 81 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
82 82 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
83 83 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
84 84 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
85 85 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
86 86 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
87 87
88 88 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 89 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 90 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 91 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
92 92 );
93 93 END lpp_top_lfr_wf_picker_ip;
94 94
95 95 ARCHITECTURE tb OF lpp_top_lfr_wf_picker_ip IS
96 96
97 97 COMPONENT Downsampling
98 98 GENERIC (
99 99 ChanelCount : INTEGER;
100 100 SampleSize : INTEGER;
101 101 DivideParam : INTEGER);
102 102 PORT (
103 103 clk : IN STD_LOGIC;
104 104 rstn : IN STD_LOGIC;
105 105 sample_in_val : IN STD_LOGIC;
106 106 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
107 107 sample_out_val : OUT STD_LOGIC;
108 108 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
109 109 END COMPONENT;
110 110
111 111 -----------------------------------------------------------------------------
112 112 CONSTANT ChanelCount : INTEGER := 8;
113 113 CONSTANT ncycle_cnv_high : INTEGER := 79;
114 114 CONSTANT ncycle_cnv : INTEGER := 500;
115 115
116 116 -----------------------------------------------------------------------------
117 117 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
118 118 SIGNAL sample_val : STD_LOGIC;
119 119 SIGNAL sample_val_delay : STD_LOGIC;
120 120 -----------------------------------------------------------------------------
121 121 CONSTANT Coef_SZ : INTEGER := 9;
122 122 CONSTANT CoefCntPerCel : INTEGER := 6;
123 123 CONSTANT CoefPerCel : INTEGER := 5;
124 124 CONSTANT Cels_count : INTEGER := 5;
125 125
126 126 SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
127 127 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
128 128 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
129 129 SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
130 130 --
131 131 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
132 132 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
133 133 -----------------------------------------------------------------------------
134 134 SIGNAL sample_data_shaping_out_val : STD_LOGIC;
135 135 SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
136 136 SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
137 137 SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
138 138 SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
139 139 SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
140 140 SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
141 141 -----------------------------------------------------------------------------
142 142 SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
143 143 SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
144 144 -----------------------------------------------------------------------------
145 145 SIGNAL sample_f0_val : STD_LOGIC;
146 146 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
147 147 SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
148 148 --
149 149 SIGNAL sample_f1_val : STD_LOGIC;
150 150 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
151 151 SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
152 152 --
153 153 SIGNAL sample_f2_val : STD_LOGIC;
154 154 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
155 155 --
156 156 SIGNAL sample_f3_val : STD_LOGIC;
157 157 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
158 158
159 159 -----------------------------------------------------------------------------
160 160 SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
161 161 SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
162 162 SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
163 163 SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
164 164 -----------------------------------------------------------------------------
165 165
166 166 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
167 167 SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
168 168 SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
169 169 SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
170 170 BEGIN
171 171
172 172 -- component instantiation
173 173 -----------------------------------------------------------------------------
174 174 DIGITAL_acquisition : AD7688_drvr
175 175 GENERIC MAP (
176 176 ChanelCount => ChanelCount,
177 177 ncycle_cnv_high => ncycle_cnv_high,
178 178 ncycle_cnv => ncycle_cnv)
179 179 PORT MAP (
180 180 cnv_clk => cnv_clk, --
181 181 cnv_rstn => cnv_rstn, --
182 182 cnv_run => cnv_run, --
183 183 cnv => cnv, --
184 184 clk => clk, --
185 185 rstn => rstn, --
186 186 sck => sck, --
187 187 sdo => sdo(ChanelCount-1 DOWNTO 0), --
188 188 sample => sample,
189 189 sample_val => sample_val);
190 190
191 191 -----------------------------------------------------------------------------
192 192
193 193 PROCESS (clk, rstn)
194 194 BEGIN -- PROCESS
195 195 IF rstn = '0' THEN -- asynchronous reset (active low)
196 196 sample_val_delay <= '0';
197 197 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
198 198 sample_val_delay <= sample_val;
199 199 END IF;
200 200 END PROCESS;
201 201
202 202 -----------------------------------------------------------------------------
203 203 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
204 204 SampleLoop : FOR j IN 0 TO 15 GENERATE
205 205 sample_filter_in(i, j) <= sample(i)(j);
206 206 END GENERATE;
207 207
208 208 sample_filter_in(i, 16) <= sample(i)(15);
209 209 sample_filter_in(i, 17) <= sample(i)(15);
210 210 END GENERATE;
211 211
212 212 coefs_v2 <= CoefsInitValCst_v2;
213 213
214 214 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
215 215 GENERIC MAP (
216 216 tech => 0,
217 217 Mem_use => use_RAM, -- use_RAM
218 218 Sample_SZ => 18,
219 219 Coef_SZ => Coef_SZ,
220 220 Coef_Nb => 25,
221 221 Coef_sel_SZ => 5,
222 222 Cels_count => Cels_count,
223 223 ChanelsCount => ChanelCount)
224 224 PORT MAP (
225 225 rstn => rstn,
226 226 clk => clk,
227 227 virg_pos => 7,
228 228 coefs => coefs_v2,
229 229 sample_in_val => sample_val_delay,
230 230 sample_in => sample_filter_in,
231 231 sample_out_val => sample_filter_v2_out_val,
232 232 sample_out => sample_filter_v2_out);
233 233
234 234 -----------------------------------------------------------------------------
235 235 -- DATA_SHAPING
236 236 -----------------------------------------------------------------------------
237 237 all_data_shaping_in_loop: FOR I IN 17 DOWNTO 0 GENERATE
238 238 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0,I);
239 239 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1,I);
240 240 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2,I);
241 241 END GENERATE all_data_shaping_in_loop;
242 242
243 243 sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
244 244 sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
245 245
246 246 PROCESS (clk, rstn)
247 247 BEGIN -- PROCESS
248 248 IF rstn = '0' THEN -- asynchronous reset (active low)
249 249 sample_data_shaping_out_val <= '0';
250 250 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
251 251 sample_data_shaping_out_val <= sample_filter_v2_out_val;
252 252 END IF;
253 253 END PROCESS;
254 254
255 255 SampleLoop_data_shaping: FOR j IN 0 TO 17 GENERATE
256 256 PROCESS (clk, rstn)
257 257 BEGIN
258 258 IF rstn = '0' THEN
259 259 sample_data_shaping_out(0,j) <= '0';
260 260 sample_data_shaping_out(1,j) <= '0';
261 261 sample_data_shaping_out(2,j) <= '0';
262 262 sample_data_shaping_out(3,j) <= '0';
263 263 sample_data_shaping_out(4,j) <= '0';
264 264 sample_data_shaping_out(5,j) <= '0';
265 265 sample_data_shaping_out(6,j) <= '0';
266 266 sample_data_shaping_out(7,j) <= '0';
267 267 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
268 268 sample_data_shaping_out(0,j) <= sample_filter_v2_out(0,j);
269 269 IF data_shaping_SP0 = '1' THEN
270 270 sample_data_shaping_out(1,j) <= sample_data_shaping_f1_f0_s(j);
271 271 ELSE
272 272 sample_data_shaping_out(1,j) <= sample_filter_v2_out(1,j);
273 273 END IF;
274 274 IF data_shaping_SP1 = '1' THEN
275 275 sample_data_shaping_out(2,j) <= sample_data_shaping_f2_f1_s(j);
276 276 ELSE
277 277 sample_data_shaping_out(2,j) <= sample_filter_v2_out(2,j);
278 278 END IF;
279 279 sample_data_shaping_out(4,j) <= sample_filter_v2_out(4,j);
280 280 sample_data_shaping_out(5,j) <= sample_filter_v2_out(5,j);
281 281 sample_data_shaping_out(6,j) <= sample_filter_v2_out(6,j);
282 282 sample_data_shaping_out(7,j) <= sample_filter_v2_out(7,j);
283 283 END IF;
284 284 END PROCESS;
285 285 END GENERATE;
286 286
287 287 sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
288 288 ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
289 289 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
290 290 sample_filter_v2_out_s(i,j) <= sample_data_shaping_out(i,j);
291 291 END GENERATE;
292 292 END GENERATE;
293 293 -----------------------------------------------------------------------------
294 294 -- F0 -- @24.576 kHz
295 295 -----------------------------------------------------------------------------
296 296 Downsampling_f0 : Downsampling
297 297 GENERIC MAP (
298 298 ChanelCount => 8,
299 299 SampleSize => 16,
300 300 DivideParam => 4)
301 301 PORT MAP (
302 302 clk => clk,
303 303 rstn => rstn,
304 304 sample_in_val => sample_filter_v2_out_val_s,
305 305 sample_in => sample_filter_v2_out_s,
306 306 sample_out_val => sample_f0_val,
307 307 sample_out => sample_f0);
308 308
309 309 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
310 310 sample_f0_wdata_s(I) <= sample_f0(0, I); -- V
311 311 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1
312 312 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2
313 313 sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1
314 314 sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2
315 315 sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3
316 316 END GENERATE all_bit_sample_f0;
317 317
318 318 sample_f0_wen <= NOT(sample_f0_val) &
319 319 NOT(sample_f0_val) &
320 320 NOT(sample_f0_val) &
321 321 NOT(sample_f0_val) &
322 322 NOT(sample_f0_val) &
323 323 NOT(sample_f0_val);
324 324
325 325 -----------------------------------------------------------------------------
326 326 -- F1 -- @4096 Hz
327 327 -----------------------------------------------------------------------------
328 328 Downsampling_f1 : Downsampling
329 329 GENERIC MAP (
330 330 ChanelCount => 8,
331 331 SampleSize => 16,
332 332 DivideParam => 6)
333 333 PORT MAP (
334 334 clk => clk,
335 335 rstn => rstn,
336 336 sample_in_val => sample_f0_val ,
337 337 sample_in => sample_f0,
338 338 sample_out_val => sample_f1_val,
339 339 sample_out => sample_f1);
340 340
341 341 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
342 342 sample_f1_wdata_s(I) <= sample_f1(0, I); -- V
343 343 sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1
344 344 sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2
345 345 sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1
346 346 sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2
347 347 sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3
348 348 END GENERATE all_bit_sample_f1;
349 349
350 350 sample_f1_wen <= NOT(sample_f1_val) &
351 351 NOT(sample_f1_val) &
352 352 NOT(sample_f1_val) &
353 353 NOT(sample_f1_val) &
354 354 NOT(sample_f1_val) &
355 355 NOT(sample_f1_val);
356 356
357 357 -----------------------------------------------------------------------------
358 358 -- F2 -- @256 Hz
359 359 -----------------------------------------------------------------------------
360 360 all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
361 361 sample_f0_s(0, I) <= sample_f0(0, I); -- V
362 362 sample_f0_s(1, I) <= sample_f0(1, I); -- E1
363 363 sample_f0_s(2, I) <= sample_f0(2, I); -- E2
364 364 sample_f0_s(3, I) <= sample_f0(5, I); -- B1
365 365 sample_f0_s(4, I) <= sample_f0(6, I); -- B2
366 366 sample_f0_s(5, I) <= sample_f0(7, I); -- B3
367 367 END GENERATE all_bit_sample_f0_s;
368 368
369 369 Downsampling_f2 : Downsampling
370 370 GENERIC MAP (
371 371 ChanelCount => 6,
372 372 SampleSize => 16,
373 373 DivideParam => 96)
374 374 PORT MAP (
375 375 clk => clk,
376 376 rstn => rstn,
377 377 sample_in_val => sample_f0_val ,
378 378 sample_in => sample_f0_s,
379 379 sample_out_val => sample_f2_val,
380 380 sample_out => sample_f2);
381 381
382 382 sample_f2_wen <= NOT(sample_f2_val) &
383 383 NOT(sample_f2_val) &
384 384 NOT(sample_f2_val) &
385 385 NOT(sample_f2_val) &
386 386 NOT(sample_f2_val) &
387 387 NOT(sample_f2_val);
388 388
389 389 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
390 390 sample_f2_wdata_s(I) <= sample_f2(0, I);
391 391 sample_f2_wdata_s(16*1+I) <= sample_f2(1, I);
392 392 sample_f2_wdata_s(16*2+I) <= sample_f2(2, I);
393 393 sample_f2_wdata_s(16*3+I) <= sample_f2(3, I);
394 394 sample_f2_wdata_s(16*4+I) <= sample_f2(4, I);
395 395 sample_f2_wdata_s(16*5+I) <= sample_f2(5, I);
396 396 END GENERATE all_bit_sample_f2;
397 397
398 398 -----------------------------------------------------------------------------
399 399 -- F3 -- @16 Hz
400 400 -----------------------------------------------------------------------------
401 401 all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE
402 402 sample_f1_s(0, I) <= sample_f1(0, I); -- V
403 403 sample_f1_s(1, I) <= sample_f1(1, I); -- E1
404 404 sample_f1_s(2, I) <= sample_f1(2, I); -- E2
405 405 sample_f1_s(3, I) <= sample_f1(5, I); -- B1
406 406 sample_f1_s(4, I) <= sample_f1(6, I); -- B2
407 407 sample_f1_s(5, I) <= sample_f1(7, I); -- B3
408 408 END GENERATE all_bit_sample_f1_s;
409 409
410 410 Downsampling_f3 : Downsampling
411 411 GENERIC MAP (
412 412 ChanelCount => 6,
413 413 SampleSize => 16,
414 414 DivideParam => 256)
415 415 PORT MAP (
416 416 clk => clk,
417 417 rstn => rstn,
418 418 sample_in_val => sample_f1_val ,
419 419 sample_in => sample_f1_s,
420 420 sample_out_val => sample_f3_val,
421 421 sample_out => sample_f3);
422 422
423 423 sample_f3_wen <= (NOT sample_f3_val) &
424 424 (NOT sample_f3_val) &
425 425 (NOT sample_f3_val) &
426 426 (NOT sample_f3_val) &
427 427 (NOT sample_f3_val) &
428 428 (NOT sample_f3_val);
429 429
430 430 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
431 431 sample_f3_wdata_s(I) <= sample_f3(0, I);
432 432 sample_f3_wdata_s(16*1+I) <= sample_f3(1, I);
433 433 sample_f3_wdata_s(16*2+I) <= sample_f3(2, I);
434 434 sample_f3_wdata_s(16*3+I) <= sample_f3(3, I);
435 435 sample_f3_wdata_s(16*4+I) <= sample_f3(4, I);
436 436 sample_f3_wdata_s(16*5+I) <= sample_f3(5, I);
437 437 END GENERATE all_bit_sample_f3;
438 438
439 439 lpp_waveform_1 : lpp_waveform
440 440 GENERIC MAP (
441 441 hindex => hindex,
442 442 tech => tech,
443 443 data_size => 160,
444 444 nb_burst_available_size => nb_burst_available_size,
445 445 nb_snapshot_param_size => nb_snapshot_param_size,
446 446 delta_snapshot_size => delta_snapshot_size,
447 447 delta_f2_f0_size => delta_f2_f0_size,
448 448 delta_f2_f1_size => delta_f2_f1_size)
449 449 PORT MAP (
450 450 clk => clk,
451 451 rstn => rstn,
452 452
453 453 AHB_Master_In => AHB_Master_In,
454 454 AHB_Master_Out => AHB_Master_Out,
455 455
456 456 coarse_time_0 => coarse_time_0, -- IN
457 457 delta_snapshot => delta_snapshot, -- IN
458 458 delta_f2_f1 => delta_f2_f1, -- IN
459 459 delta_f2_f0 => delta_f2_f0, -- IN
460 460 enable_f0 => enable_f0, -- IN
461 461 enable_f1 => enable_f1, -- IN
462 462 enable_f2 => enable_f2, -- IN
463 463 enable_f3 => enable_f3, -- IN
464 464 burst_f0 => burst_f0, -- IN
465 465 burst_f1 => burst_f1, -- IN
466 466 burst_f2 => burst_f2, -- IN
467 467 nb_burst_available => nb_burst_available,
468 468 nb_snapshot_param => nb_snapshot_param,
469 469 status_full => status_full,
470 470 status_full_ack => status_full_ack, -- IN
471 471 status_full_err => status_full_err,
472 472 status_new_err => status_new_err,
473 473
474 474 addr_data_f0 => addr_data_f0, -- IN
475 475 addr_data_f1 => addr_data_f1, -- IN
476 476 addr_data_f2 => addr_data_f2, -- IN
477 477 addr_data_f3 => addr_data_f3, -- IN
478 478
479 479 data_f0_in => data_f0_in_valid,
480 480 data_f1_in => data_f1_in_valid,
481 481 data_f2_in => data_f2_in_valid,
482 482 data_f3_in => data_f3_in_valid,
483 483 data_f0_in_valid => sample_f0_val,
484 484 data_f1_in_valid => sample_f1_val,
485 485 data_f2_in_valid => sample_f2_val,
486 486 data_f3_in_valid => sample_f3_val);
487 487
488 data_f0_in_valid((4*16)-1 DOWNTO 0) <= (others => '0');
489 data_f1_in_valid((4*16)-1 DOWNTO 0) <= (others => '0');
490 data_f2_in_valid((4*16)-1 DOWNTO 0) <= (others => '0');
491 data_f3_in_valid((4*16)-1 DOWNTO 0) <= (others => '0');
488 492 data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s;
489 493 data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s;
490 494 data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s;
491 495 data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s;
492 496
493 497 sample_f0_wdata <= sample_f0_wdata_s;
494 498 sample_f1_wdata <= sample_f1_wdata_s;
495 499 sample_f2_wdata <= sample_f2_wdata_s;
496 500 sample_f3_wdata <= sample_f3_wdata_s;
497 501
498 END tb;
502 END tb; No newline at end of file
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