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pellion -
r176:ee29877991b1 JC
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@@ -0,0 +1,8
1 iir_filter.vhd
2 FILTERcfg.vhd
3 RAM.vhd
4 RAM_CEL.vhd
5 RAM_CTRLR_v2.vhd
6 IIR_CEL_CTRLR_v2_CONTROL.vhd
7 IIR_CEL_CTRLR_v2_DATAFLOW.vhd
8 IIR_CEL_CTRLR_v2.vhd
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@@ -0,0 +1,9
1 APB_FFT.vhd
2 APB_FFT_half.vhd
3 Driver_FFT.vhd
4 FFT.vhd
5 FFTamont.vhd
6 FFTaval.vhd
7 Flag_Extremum.vhd
8 Linker_FFT.vhd
9 lpp_fft.vhd
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@@ -0,0 +1,4
1 lpp_ad_Conv.vhd
2 AD7688_drvr.vhd
3 WriteGen_ADC.vhd
4 TestModule_ADS7886.vhd
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@@ -0,0 +1,2
1 apb_devices_list.vhd
2 lpp_amba.vhd
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@@ -0,0 +1,3
1 lpp_bootloader_pkg.vhd
2 bootrom.vhd
3 lpp_bootloader.vhd
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@@ -0,0 +1,4
1 DEMUX.vhd
2 Demultiplex.vhd
3 WatchFlag.vhd
4 lpp_demux.vhd
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@@ -0,0 +1,13
1 ALU_Driver.vhd
2 APB_Matrix.vhd
3 Dispatch.vhd
4 DriveInputs.vhd
5 GetResult.vhd
6 MatriceSpectrale.vhd
7 Matrix.vhd
8 SpectralMatrix.vhd
9 Starter.vhd
10 TopMatrix_PDR.vhd
11 TopSpecMatrix.vhd
12 Top_MatrixSpec.vhd
13 lpp_matrix.vhd
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@@ -0,0 +1,7
1 lpp_memory.vhd
2 lpp_FIFO.vhd
3 APB_FIFO.vhd
4 Bridge.vhd
5 SSRAM_plugin.vhd
6 lppFIFOx5.vhd
7 lppFIFOxN.vhd
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@@ -607,17 +607,6 BEGIN
607 607 header_val => header_val,
608 608 header_ack => header_ack);
609 609
610 --fifo_latency_correction_1 : fifo_latency_correction
611 -- PORT MAP (
612 -- HCLK => clkm,
613 -- HRESETn => resetn,
614 -- fifo_data => fifo_data,
615 -- fifo_empty => fifo_empty,
616 -- fifo_ren => fifo_ren,
617 -- dma_data => dma_data,
618 -- dma_empty => dma_empty,
619 -- dma_ren => dma_ren);
620
621 610 fifo_test_dma_1 : fifo_test_dma
622 611 GENERIC MAP (
623 612 tech => fabtech,
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@@ -1,21 +1,21
1 1 ./amba_lcd_16x2_ctrlr
2 ./dsp/iir_filter
3 ./dsp/lpp_downsampling
4 ./dsp/lpp_fft
5 2 ./general_purpose
6 3 ./general_purpose/lpp_AMR
7 4 ./general_purpose/lpp_balise
8 5 ./general_purpose/lpp_delay
6 ./lpp_amba
7 ./dsp/iir_filter
8 ./dsp/lpp_downsampling
9 ./dsp/lpp_fft
9 10 ./lfr_time_management
10 11 ./lpp_ad_Conv
11 ./lpp_amba
12 12 ./lpp_bootloader
13 13 ./lpp_cna
14 14 ./lpp_demux
15 ./lpp_dma
16 15 ./lpp_matrix
17 16 ./lpp_memory
18 ./lpp_top_lfr
17 ./lpp_dma
19 18 ./lpp_uart
20 19 ./lpp_usb
21 20 ./lpp_waveform
21 ./lpp_top_lfr
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@@ -1,3 +1,4
1 general_purpose.vhd
1 2 ADDRcntr.vhd
2 3 ALU.vhd
3 4 Adder.vhd
@@ -14,5 +15,4 Multiplier.vhd
14 15 REG.vhd
15 16 SYNC_FF.vhd
16 17 Shifter.vhd
17 general_purpose.vhd
18 18 TwoComplementer.vhd
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@@ -36,7 +36,7 ENTITY apb_lfr_time_management IS
36 36 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 37 pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used
38 38 masterclk : INTEGER := 25000000; --! master clock in Hz
39 otherclk : INTEGER := 49152000; --! other clock in Hz
39 timeclk : INTEGER := 49152000; --! other clock in Hz
40 40 finetimeclk : INTEGER := 65536 --! divided clock used for the fine time counter
41 41 );
42 42
@@ -62,7 +62,7 ARCHITECTURE Behavioral OF apb_lfr_time_
62 62 --! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word;
63 63 CONSTANT pconfig : apb_config_type := (
64 64 --! 0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0),
65 0 => ahb_device_reg (19, 14, 0, REVISION, pirq),
65 0 => ahb_device_reg (VENDOR_LPP, 0, 0, REVISION, pirq),
66 66 1 => apb_iobar(paddr, pmask));
67 67
68 68 TYPE apb_lfr_time_management_Reg IS RECORD
@@ -80,20 +80,53 ARCHITECTURE Behavioral OF apb_lfr_time_
80 80 SIGNAL soft_tick : STD_LOGIC;
81 81 SIGNAL reset_next_commutation : STD_LOGIC;
82 82
83 SIGNAL irq1 : STD_LOGIC;
84 SIGNAL irq2 : STD_LOGIC;
85
83 86 BEGIN
84 87
85 88 lfrtimemanagement0 : lfr_time_management
86 GENERIC MAP(masterclk => masterclk, timeclk => otherclk, finetimeclk => finetimeclk)
87 PORT MAP(master_clock => clk25MHz, time_clock => clk49_152MHz, resetn => resetn,
88 grspw_tick => grspw_tick, soft_tick => soft_tick,
89 coarse_time_load => r.coarse_time_load, coarse_time => r.coarse_time, fine_time => r.fine_time,
90 next_commutation => r.next_commutation, reset_next_commutation => reset_next_commutation,
91 irq1 => apbo.pirq(pirq), irq2 => apbo.pirq(pirq+1));
89 GENERIC MAP(
90 masterclk => masterclk,
91 timeclk => timeclk,
92 finetimeclk => finetimeclk,
93 nb_clk_div_ticks => 1)
94 PORT MAP(
95 master_clock => clk25MHz,
96 time_clock => clk49_152MHz,
97 resetn => resetn,
98 grspw_tick => grspw_tick,
99 soft_tick => soft_tick,
100 coarse_time_load => r.coarse_time_load,
101 coarse_time => r.coarse_time,
102 fine_time => r.fine_time,
103 next_commutation => r.next_commutation,
104 reset_next_commutation => reset_next_commutation,
105 irq1 => irq1,--apbo.pirq(pirq),
106 irq2 => irq2);--apbo.pirq(pirq+1));
107
108 --apbo.pirq <= (OTHERS => '0');
109
110 all_irq_gen: FOR I IN 15 DOWNTO 0 GENERATE
111 irq1_gen: IF I = pirq GENERATE
112 apbo.pirq(I) <= irq1;
113 END GENERATE irq1_gen;
114 irq2_gen: IF I = pirq+1 GENERATE
115 apbo.pirq(I) <= irq2;
116 END GENERATE irq2_gen;
117 others_irq: IF (I < pirq) OR (I > (pirq + 1)) GENERATE
118 apbo.pirq(I) <= '0';
119 END GENERATE others_irq;
120 END GENERATE all_irq_gen;
121
122 --all_irq_sig: FOR I IN 31 DOWNTO 0 GENERATE
123 --END GENERATE all_irq_sig;
92 124
93 125 PROCESS(resetn, clk25MHz, reset_next_commutation)
94 126 BEGIN
95 127
96 128 IF resetn = '0' THEN
129 Rdata <= (OTHERS => '0');
97 130 r.coarse_time_load <= x"80000000";
98 131 r.ctrl <= x"00000000";
99 132 r.next_commutation <= x"ffffffff";
@@ -164,11 +197,12 BEGIN
164 197 END IF;
165 198
166 199 END IF;
167 apbo.pconfig <= pconfig;
168 200 END PROCESS;
169 201
170 apbo.prdata <= Rdata WHEN apbi.penable = '1';
202 apbo.prdata <= Rdata ;--WHEN apbi.penable = '1';
171 203 coarse_time <= r.coarse_time;
172 204 fine_time <= r.fine_time;
205 apbo.pconfig <= pconfig;
206 apbo.pindex <= pindex;
173 207
174 208 END Behavioral;
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@@ -1,3 +1,3
1 apb_lfr_time_management.vhd
1 lpp_lfr_time_management.vhd
2 2 lfr_time_management.vhd
3 lpp_lfr_time_management.vhd
3 apb_lfr_time_management.vhd
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@@ -80,6 +80,8 signal nCE3int : std_logic:='1';
80 80 Type stateT is (idle,st1,st2,st3,st4);
81 81 signal state : stateT;
82 82
83 SIGNAL nclk : STD_LOGIC;
84
83 85 begin
84 86
85 87 process(clk , mem_ctrlr_o.RAMSN(0))
@@ -102,8 +104,9 begin
102 104 end if;
103 105 end process;
104 106
107 nclk <= NOT clk;
105 108 ssram_clk_pad : outpad generic map (tech => tech)
106 port map (SSRAM_CLK,not clk);
109 port map (SSRAM_CLK,nclk);
107 110
108 111
109 112 nBWaint <= mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0);
@@ -181,4 +184,4 MODE_pad : outpad generic map (tech => t
181 184 ZZ_pad : outpad generic map (tech => tech)
182 185 port map (ZZ, '0');
183 186
184 end architecture; No newline at end of file
187 end architecture;
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@@ -485,6 +485,10 BEGIN
485 485 data_f2_in_valid => sample_f2_val,
486 486 data_f3_in_valid => sample_f3_val);
487 487
488 data_f0_in_valid((4*16)-1 DOWNTO 0) <= (others => '0');
489 data_f1_in_valid((4*16)-1 DOWNTO 0) <= (others => '0');
490 data_f2_in_valid((4*16)-1 DOWNTO 0) <= (others => '0');
491 data_f3_in_valid((4*16)-1 DOWNTO 0) <= (others => '0');
488 492 data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s;
489 493 data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s;
490 494 data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s;
@@ -495,4 +499,4 BEGIN
495 499 sample_f2_wdata <= sample_f2_wdata_s;
496 500 sample_f3_wdata <= sample_f3_wdata_s;
497 501
498 END tb;
502 END tb; No newline at end of file
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