@@ -0,0 +1,8 | |||
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1 | iir_filter.vhd | |
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2 | FILTERcfg.vhd | |
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3 | RAM.vhd | |
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4 | RAM_CEL.vhd | |
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5 | RAM_CTRLR_v2.vhd | |
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6 | IIR_CEL_CTRLR_v2_CONTROL.vhd | |
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7 | IIR_CEL_CTRLR_v2_DATAFLOW.vhd | |
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8 | IIR_CEL_CTRLR_v2.vhd |
@@ -0,0 +1,9 | |||
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1 | APB_FFT.vhd | |
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2 | APB_FFT_half.vhd | |
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3 | Driver_FFT.vhd | |
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4 | FFT.vhd | |
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5 | FFTamont.vhd | |
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6 | FFTaval.vhd | |
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7 | Flag_Extremum.vhd | |
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8 | Linker_FFT.vhd | |
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9 | lpp_fft.vhd |
@@ -0,0 +1,13 | |||
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1 | ALU_Driver.vhd | |
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2 | APB_Matrix.vhd | |
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3 | Dispatch.vhd | |
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4 | DriveInputs.vhd | |
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5 | GetResult.vhd | |
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6 | MatriceSpectrale.vhd | |
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7 | Matrix.vhd | |
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8 | SpectralMatrix.vhd | |
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9 | Starter.vhd | |
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10 | TopMatrix_PDR.vhd | |
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11 | TopSpecMatrix.vhd | |
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12 | Top_MatrixSpec.vhd | |
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13 | lpp_matrix.vhd |
@@ -0,0 +1,7 | |||
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1 | lpp_memory.vhd | |
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2 | lpp_FIFO.vhd | |
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3 | APB_FIFO.vhd | |
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4 | Bridge.vhd | |
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5 | SSRAM_plugin.vhd | |
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6 | lppFIFOx5.vhd | |
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7 | lppFIFOxN.vhd |
@@ -607,17 +607,6 BEGIN | |||
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607 | 607 | header_val => header_val, |
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608 | 608 | header_ack => header_ack); |
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609 | 609 | |
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610 | --fifo_latency_correction_1 : fifo_latency_correction | |
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611 | -- PORT MAP ( | |
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612 | -- HCLK => clkm, | |
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613 | -- HRESETn => resetn, | |
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614 | -- fifo_data => fifo_data, | |
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615 | -- fifo_empty => fifo_empty, | |
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616 | -- fifo_ren => fifo_ren, | |
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617 | -- dma_data => dma_data, | |
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618 | -- dma_empty => dma_empty, | |
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619 | -- dma_ren => dma_ren); | |
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620 | ||
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621 | 610 | fifo_test_dma_1 : fifo_test_dma |
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622 | 611 | GENERIC MAP ( |
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623 | 612 | tech => fabtech, |
@@ -1,21 +1,21 | |||
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1 | 1 | ./amba_lcd_16x2_ctrlr |
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2 | ./dsp/iir_filter | |
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3 | ./dsp/lpp_downsampling | |
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4 | ./dsp/lpp_fft | |
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5 | 2 | ./general_purpose |
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6 | 3 | ./general_purpose/lpp_AMR |
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7 | 4 | ./general_purpose/lpp_balise |
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8 | 5 | ./general_purpose/lpp_delay |
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6 | ./lpp_amba | |
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7 | ./dsp/iir_filter | |
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8 | ./dsp/lpp_downsampling | |
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9 | ./dsp/lpp_fft | |
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9 | 10 | ./lfr_time_management |
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10 | 11 | ./lpp_ad_Conv |
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11 | ./lpp_amba | |
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12 | 12 | ./lpp_bootloader |
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13 | 13 | ./lpp_cna |
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14 | 14 | ./lpp_demux |
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15 | ./lpp_dma | |
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16 | 15 | ./lpp_matrix |
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17 | 16 | ./lpp_memory |
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18 | ./lpp_top_lfr | |
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17 | ./lpp_dma | |
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19 | 18 | ./lpp_uart |
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20 | 19 | ./lpp_usb |
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21 | 20 | ./lpp_waveform |
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21 | ./lpp_top_lfr |
@@ -1,3 +1,4 | |||
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1 | general_purpose.vhd | |
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1 | 2 | ADDRcntr.vhd |
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2 | 3 | ALU.vhd |
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3 | 4 | Adder.vhd |
@@ -14,5 +15,4 Multiplier.vhd | |||
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14 | 15 | REG.vhd |
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15 | 16 | SYNC_FF.vhd |
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16 | 17 | Shifter.vhd |
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17 | general_purpose.vhd | |
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18 | 18 | TwoComplementer.vhd |
@@ -25,150 +25,184 USE grlib.amba.ALL; | |||
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25 | 25 | USE grlib.stdlib.ALL; |
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26 | 26 | USE grlib.devices.ALL; |
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27 | 27 | LIBRARY lpp; |
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28 | USE lpp.apb_devices_list.ALL; | |
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29 | USE lpp.lpp_lfr_time_management.ALL; | |
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30 | ||
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31 | ENTITY apb_lfr_time_management IS | |
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32 | ||
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33 | GENERIC( | |
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34 | pindex : INTEGER := 0; --! APB slave index | |
|
35 | paddr : INTEGER := 0; --! ADDR field of the APB BAR | |
|
36 | pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR | |
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37 | pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used | |
|
38 | masterclk : INTEGER := 25000000; --! master clock in Hz | |
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39 |
|
|
|
40 | finetimeclk : INTEGER := 65536 --! divided clock used for the fine time counter | |
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41 | ); | |
|
42 | ||
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43 | PORT ( | |
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44 | clk25MHz : IN STD_LOGIC; --! Clock | |
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45 | clk49_152MHz : IN STD_LOGIC; --! secondary clock | |
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46 | resetn : IN STD_LOGIC; --! Reset | |
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47 | grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received | |
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48 | apbi : IN apb_slv_in_type; --! APB slave input signals | |
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49 | apbo : OUT apb_slv_out_type; --! APB slave output signals | |
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50 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time | |
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51 | fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --! fine time | |
|
52 | ); | |
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53 | ||
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54 | END apb_lfr_time_management; | |
|
55 | ||
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56 | ARCHITECTURE Behavioral OF apb_lfr_time_management IS | |
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57 | ||
|
58 | CONSTANT REVISION : INTEGER := 1; | |
|
59 | ||
|
60 | --! the following types are defined in the grlib amba package | |
|
61 | --! subtype amba_config_word is std_logic_vector(31 downto 0); | |
|
62 | --! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; | |
|
63 | CONSTANT pconfig : apb_config_type := ( | |
|
64 | --! 0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0), | |
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65 |
0 => ahb_device_reg ( |
|
|
66 | 1 => apb_iobar(paddr, pmask)); | |
|
67 | ||
|
68 | TYPE apb_lfr_time_management_Reg IS RECORD | |
|
69 | ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
70 | coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
71 | coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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72 | fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
73 | next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
74 | END RECORD; | |
|
75 | ||
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76 | SIGNAL r : apb_lfr_time_management_Reg; | |
|
77 | SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
78 | SIGNAL force_tick : STD_LOGIC; | |
|
79 | SIGNAL previous_force_tick : STD_LOGIC; | |
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80 | SIGNAL soft_tick : STD_LOGIC; | |
|
81 | SIGNAL reset_next_commutation : STD_LOGIC; | |
|
82 | ||
|
83 | BEGIN | |
|
84 | ||
|
85 | lfrtimemanagement0 : lfr_time_management | |
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86 | GENERIC MAP(masterclk => masterclk, timeclk => otherclk, finetimeclk => finetimeclk) | |
|
87 | PORT MAP(master_clock => clk25MHz, time_clock => clk49_152MHz, resetn => resetn, | |
|
88 | grspw_tick => grspw_tick, soft_tick => soft_tick, | |
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89 | coarse_time_load => r.coarse_time_load, coarse_time => r.coarse_time, fine_time => r.fine_time, | |
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90 | next_commutation => r.next_commutation, reset_next_commutation => reset_next_commutation, | |
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91 | irq1 => apbo.pirq(pirq), irq2 => apbo.pirq(pirq+1)); | |
|
92 | ||
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93 | PROCESS(resetn, clk25MHz, reset_next_commutation) | |
|
94 | BEGIN | |
|
95 | ||
|
96 | IF resetn = '0' THEN | |
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97 | r.coarse_time_load <= x"80000000"; | |
|
98 | r.ctrl <= x"00000000"; | |
|
99 | r.next_commutation <= x"ffffffff"; | |
|
100 | force_tick <= '0'; | |
|
101 | previous_force_tick <= '0'; | |
|
102 | soft_tick <= '0'; | |
|
103 | ||
|
104 |
|
|
|
105 | r.next_commutation <= x"ffffffff"; | |
|
106 | ||
|
107 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN | |
|
108 | ||
|
109 | previous_force_tick <= force_tick; | |
|
110 | force_tick <= r.ctrl(0); | |
|
111 | IF (previous_force_tick = '0') AND (force_tick = '1') THEN | |
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112 | soft_tick <= '1'; | |
|
113 | ELSE | |
|
114 | soft_tick <= '0'; | |
|
115 | END IF; | |
|
116 | ||
|
117 | --APB Write OP | |
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118 | IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN | |
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119 | CASE apbi.paddr(7 DOWNTO 2) IS | |
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120 | WHEN "000000" => | |
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121 | r.ctrl <= apbi.pwdata(31 DOWNTO 0); | |
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122 | WHEN "000001" => | |
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123 | r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0); | |
|
124 | WHEN "000100" => | |
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125 | r.next_commutation <= apbi.pwdata(31 DOWNTO 0); | |
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126 | WHEN OTHERS => | |
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127 | r.coarse_time_load <= x"00000000"; | |
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128 | END CASE; | |
|
129 | ELSIF r.ctrl(0) = '1' THEN | |
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130 | r.ctrl(0) <= '0'; | |
|
131 | END IF; | |
|
132 | ||
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133 | --APB READ OP | |
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134 | IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN | |
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135 | CASE apbi.paddr(7 DOWNTO 2) IS | |
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136 | WHEN "000000" => | |
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137 | Rdata(31 DOWNTO 24) <= r.ctrl(31 DOWNTO 24); | |
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138 | Rdata(23 DOWNTO 16) <= r.ctrl(23 DOWNTO 16); | |
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139 | Rdata(15 DOWNTO 8) <= r.ctrl(15 DOWNTO 8); | |
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140 | Rdata(7 DOWNTO 0) <= r.ctrl(7 DOWNTO 0); | |
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141 | WHEN "000001" => | |
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142 | Rdata(31 DOWNTO 24) <= r.coarse_time_load(31 DOWNTO 24); | |
|
143 | Rdata(23 DOWNTO 16) <= r.coarse_time_load(23 DOWNTO 16); | |
|
144 | Rdata(15 DOWNTO 8) <= r.coarse_time_load(15 DOWNTO 8); | |
|
145 | Rdata(7 DOWNTO 0) <= r.coarse_time_load(7 DOWNTO 0); | |
|
146 | WHEN "000010" => | |
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147 | Rdata(31 DOWNTO 24) <= r.coarse_time(31 DOWNTO 24); | |
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148 | Rdata(23 DOWNTO 16) <= r.coarse_time(23 DOWNTO 16); | |
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149 | Rdata(15 DOWNTO 8) <= r.coarse_time(15 DOWNTO 8); | |
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150 | Rdata(7 DOWNTO 0) <= r.coarse_time(7 DOWNTO 0); | |
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151 | WHEN "000011" => | |
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152 | Rdata(31 DOWNTO 24) <= r.fine_time(31 DOWNTO 24); | |
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153 | Rdata(23 DOWNTO 16) <= r.fine_time(23 DOWNTO 16); | |
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154 | Rdata(15 DOWNTO 8) <= r.fine_time(15 DOWNTO 8); | |
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155 | Rdata(7 DOWNTO 0) <= r.fine_time(7 DOWNTO 0); | |
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156 | WHEN "000100" => | |
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157 | Rdata(31 DOWNTO 24) <= r.next_commutation(31 DOWNTO 24); | |
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158 |
|
|
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159 | Rdata(15 DOWNTO 8) <= r.next_commutation(15 DOWNTO 8); | |
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160 | Rdata(7 DOWNTO 0) <= r.next_commutation(7 DOWNTO 0); | |
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161 | WHEN OTHERS => | |
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162 | Rdata(31 DOWNTO 0) <= x"00000000"; | |
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163 | END CASE; | |
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164 | END IF; | |
|
165 | ||
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166 | END IF; | |
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167 | apbo.pconfig <= pconfig; | |
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168 | END PROCESS; | |
|
169 | ||
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170 | apbo.prdata <= Rdata WHEN apbi.penable = '1'; | |
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171 | coarse_time <= r.coarse_time; | |
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172 | fine_time <= r.fine_time; | |
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173 | ||
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174 | END Behavioral; | |
|
28 | USE lpp.apb_devices_list.ALL; | |
|
29 | USE lpp.lpp_lfr_time_management.ALL; | |
|
30 | ||
|
31 | ENTITY apb_lfr_time_management IS | |
|
32 | ||
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33 | GENERIC( | |
|
34 | pindex : INTEGER := 0; --! APB slave index | |
|
35 | paddr : INTEGER := 0; --! ADDR field of the APB BAR | |
|
36 | pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR | |
|
37 | pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used | |
|
38 | masterclk : INTEGER := 25000000; --! master clock in Hz | |
|
39 | timeclk : INTEGER := 49152000; --! other clock in Hz | |
|
40 | finetimeclk : INTEGER := 65536 --! divided clock used for the fine time counter | |
|
41 | ); | |
|
42 | ||
|
43 | PORT ( | |
|
44 | clk25MHz : IN STD_LOGIC; --! Clock | |
|
45 | clk49_152MHz : IN STD_LOGIC; --! secondary clock | |
|
46 | resetn : IN STD_LOGIC; --! Reset | |
|
47 | grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received | |
|
48 | apbi : IN apb_slv_in_type; --! APB slave input signals | |
|
49 | apbo : OUT apb_slv_out_type; --! APB slave output signals | |
|
50 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time | |
|
51 | fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --! fine time | |
|
52 | ); | |
|
53 | ||
|
54 | END apb_lfr_time_management; | |
|
55 | ||
|
56 | ARCHITECTURE Behavioral OF apb_lfr_time_management IS | |
|
57 | ||
|
58 | CONSTANT REVISION : INTEGER := 1; | |
|
59 | ||
|
60 | --! the following types are defined in the grlib amba package | |
|
61 | --! subtype amba_config_word is std_logic_vector(31 downto 0); | |
|
62 | --! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; | |
|
63 | CONSTANT pconfig : apb_config_type := ( | |
|
64 | --! 0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0), | |
|
65 | 0 => ahb_device_reg (VENDOR_LPP, 0, 0, REVISION, pirq), | |
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66 | 1 => apb_iobar(paddr, pmask)); | |
|
67 | ||
|
68 | TYPE apb_lfr_time_management_Reg IS RECORD | |
|
69 | ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
70 | coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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71 | coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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72 | fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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73 | next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
74 | END RECORD; | |
|
75 | ||
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76 | SIGNAL r : apb_lfr_time_management_Reg; | |
|
77 | SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
78 | SIGNAL force_tick : STD_LOGIC; | |
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79 | SIGNAL previous_force_tick : STD_LOGIC; | |
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80 | SIGNAL soft_tick : STD_LOGIC; | |
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81 | SIGNAL reset_next_commutation : STD_LOGIC; | |
|
82 | ||
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83 | SIGNAL irq1 : STD_LOGIC; | |
|
84 | SIGNAL irq2 : STD_LOGIC; | |
|
85 | ||
|
86 | BEGIN | |
|
87 | ||
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88 | lfrtimemanagement0 : lfr_time_management | |
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89 | GENERIC MAP( | |
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90 | masterclk => masterclk, | |
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91 | timeclk => timeclk, | |
|
92 | finetimeclk => finetimeclk, | |
|
93 | nb_clk_div_ticks => 1) | |
|
94 | PORT MAP( | |
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95 | master_clock => clk25MHz, | |
|
96 | time_clock => clk49_152MHz, | |
|
97 | resetn => resetn, | |
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98 | grspw_tick => grspw_tick, | |
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99 | soft_tick => soft_tick, | |
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100 | coarse_time_load => r.coarse_time_load, | |
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101 | coarse_time => r.coarse_time, | |
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102 | fine_time => r.fine_time, | |
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103 | next_commutation => r.next_commutation, | |
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104 | reset_next_commutation => reset_next_commutation, | |
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105 | irq1 => irq1,--apbo.pirq(pirq), | |
|
106 | irq2 => irq2);--apbo.pirq(pirq+1)); | |
|
107 | ||
|
108 | --apbo.pirq <= (OTHERS => '0'); | |
|
109 | ||
|
110 | all_irq_gen: FOR I IN 15 DOWNTO 0 GENERATE | |
|
111 | irq1_gen: IF I = pirq GENERATE | |
|
112 | apbo.pirq(I) <= irq1; | |
|
113 | END GENERATE irq1_gen; | |
|
114 | irq2_gen: IF I = pirq+1 GENERATE | |
|
115 | apbo.pirq(I) <= irq2; | |
|
116 | END GENERATE irq2_gen; | |
|
117 | others_irq: IF (I < pirq) OR (I > (pirq + 1)) GENERATE | |
|
118 | apbo.pirq(I) <= '0'; | |
|
119 | END GENERATE others_irq; | |
|
120 | END GENERATE all_irq_gen; | |
|
121 | ||
|
122 | --all_irq_sig: FOR I IN 31 DOWNTO 0 GENERATE | |
|
123 | --END GENERATE all_irq_sig; | |
|
124 | ||
|
125 | PROCESS(resetn, clk25MHz, reset_next_commutation) | |
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126 | BEGIN | |
|
127 | ||
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128 | IF resetn = '0' THEN | |
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129 | Rdata <= (OTHERS => '0'); | |
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130 | r.coarse_time_load <= x"80000000"; | |
|
131 | r.ctrl <= x"00000000"; | |
|
132 | r.next_commutation <= x"ffffffff"; | |
|
133 | force_tick <= '0'; | |
|
134 | previous_force_tick <= '0'; | |
|
135 | soft_tick <= '0'; | |
|
136 | ||
|
137 | ELSIF reset_next_commutation = '1' THEN | |
|
138 | r.next_commutation <= x"ffffffff"; | |
|
139 | ||
|
140 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN | |
|
141 | ||
|
142 | previous_force_tick <= force_tick; | |
|
143 | force_tick <= r.ctrl(0); | |
|
144 | IF (previous_force_tick = '0') AND (force_tick = '1') THEN | |
|
145 | soft_tick <= '1'; | |
|
146 | ELSE | |
|
147 | soft_tick <= '0'; | |
|
148 | END IF; | |
|
149 | ||
|
150 | --APB Write OP | |
|
151 | IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN | |
|
152 | CASE apbi.paddr(7 DOWNTO 2) IS | |
|
153 | WHEN "000000" => | |
|
154 | r.ctrl <= apbi.pwdata(31 DOWNTO 0); | |
|
155 | WHEN "000001" => | |
|
156 | r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0); | |
|
157 | WHEN "000100" => | |
|
158 | r.next_commutation <= apbi.pwdata(31 DOWNTO 0); | |
|
159 | WHEN OTHERS => | |
|
160 | r.coarse_time_load <= x"00000000"; | |
|
161 | END CASE; | |
|
162 | ELSIF r.ctrl(0) = '1' THEN | |
|
163 | r.ctrl(0) <= '0'; | |
|
164 | END IF; | |
|
165 | ||
|
166 | --APB READ OP | |
|
167 | IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN | |
|
168 | CASE apbi.paddr(7 DOWNTO 2) IS | |
|
169 | WHEN "000000" => | |
|
170 | Rdata(31 DOWNTO 24) <= r.ctrl(31 DOWNTO 24); | |
|
171 | Rdata(23 DOWNTO 16) <= r.ctrl(23 DOWNTO 16); | |
|
172 | Rdata(15 DOWNTO 8) <= r.ctrl(15 DOWNTO 8); | |
|
173 | Rdata(7 DOWNTO 0) <= r.ctrl(7 DOWNTO 0); | |
|
174 | WHEN "000001" => | |
|
175 | Rdata(31 DOWNTO 24) <= r.coarse_time_load(31 DOWNTO 24); | |
|
176 | Rdata(23 DOWNTO 16) <= r.coarse_time_load(23 DOWNTO 16); | |
|
177 | Rdata(15 DOWNTO 8) <= r.coarse_time_load(15 DOWNTO 8); | |
|
178 | Rdata(7 DOWNTO 0) <= r.coarse_time_load(7 DOWNTO 0); | |
|
179 | WHEN "000010" => | |
|
180 | Rdata(31 DOWNTO 24) <= r.coarse_time(31 DOWNTO 24); | |
|
181 | Rdata(23 DOWNTO 16) <= r.coarse_time(23 DOWNTO 16); | |
|
182 | Rdata(15 DOWNTO 8) <= r.coarse_time(15 DOWNTO 8); | |
|
183 | Rdata(7 DOWNTO 0) <= r.coarse_time(7 DOWNTO 0); | |
|
184 | WHEN "000011" => | |
|
185 | Rdata(31 DOWNTO 24) <= r.fine_time(31 DOWNTO 24); | |
|
186 | Rdata(23 DOWNTO 16) <= r.fine_time(23 DOWNTO 16); | |
|
187 | Rdata(15 DOWNTO 8) <= r.fine_time(15 DOWNTO 8); | |
|
188 | Rdata(7 DOWNTO 0) <= r.fine_time(7 DOWNTO 0); | |
|
189 | WHEN "000100" => | |
|
190 | Rdata(31 DOWNTO 24) <= r.next_commutation(31 DOWNTO 24); | |
|
191 | Rdata(23 DOWNTO 16) <= r.next_commutation(23 DOWNTO 16); | |
|
192 | Rdata(15 DOWNTO 8) <= r.next_commutation(15 DOWNTO 8); | |
|
193 | Rdata(7 DOWNTO 0) <= r.next_commutation(7 DOWNTO 0); | |
|
194 | WHEN OTHERS => | |
|
195 | Rdata(31 DOWNTO 0) <= x"00000000"; | |
|
196 | END CASE; | |
|
197 | END IF; | |
|
198 | ||
|
199 | END IF; | |
|
200 | END PROCESS; | |
|
201 | ||
|
202 | apbo.prdata <= Rdata ;--WHEN apbi.penable = '1'; | |
|
203 | coarse_time <= r.coarse_time; | |
|
204 | fine_time <= r.fine_time; | |
|
205 | apbo.pconfig <= pconfig; | |
|
206 | apbo.pindex <= pindex; | |
|
207 | ||
|
208 | END Behavioral; |
@@ -1,83 +1,83 | |||
|
1 | ---------------------------------------------------------------------------------- | |
|
2 | -- Company: | |
|
3 | -- Engineer: | |
|
4 | -- | |
|
5 | -- Create Date: 13:04:01 07/02/2012 | |
|
6 | -- Design Name: | |
|
7 | -- Module Name: lpp_lfr_time_management - Behavioral | |
|
8 | -- Project Name: | |
|
9 | -- Target Devices: | |
|
10 | -- Tool versions: | |
|
11 | -- Description: | |
|
12 | -- | |
|
13 | -- Dependencies: | |
|
14 | -- | |
|
15 | -- Revision: | |
|
16 | -- Revision 0.01 - File Created | |
|
17 | -- Additional Comments: | |
|
18 | -- | |
|
19 | ---------------------------------------------------------------------------------- | |
|
1 | ---------------------------------------------------------------------------------- | |
|
2 | -- Company: | |
|
3 | -- Engineer: | |
|
4 | -- | |
|
5 | -- Create Date: 13:04:01 07/02/2012 | |
|
6 | -- Design Name: | |
|
7 | -- Module Name: lpp_lfr_time_management - Behavioral | |
|
8 | -- Project Name: | |
|
9 | -- Target Devices: | |
|
10 | -- Tool versions: | |
|
11 | -- Description: | |
|
12 | -- | |
|
13 | -- Dependencies: | |
|
14 | -- | |
|
15 | -- Revision: | |
|
16 | -- Revision 0.01 - File Created | |
|
17 | -- Additional Comments: | |
|
18 | -- | |
|
19 | ---------------------------------------------------------------------------------- | |
|
20 | 20 | library IEEE; |
|
21 | 21 | use IEEE.STD_LOGIC_1164.all; |
|
22 | 22 | library grlib; |
|
23 | 23 | use grlib.amba.all; |
|
24 | 24 | use grlib.stdlib.all; |
|
25 | use grlib.devices.all; | |
|
26 | ||
|
25 | use grlib.devices.all; | |
|
26 | ||
|
27 | 27 | package lpp_lfr_time_management is |
|
28 | ||
|
29 | --*************************** | |
|
30 | -- APB_LFR_TIME_MANAGEMENT | |
|
31 | ||
|
32 | component apb_lfr_time_management is | |
|
33 | ||
|
34 | generic( | |
|
35 | pindex : integer := 0; --! APB slave index | |
|
36 | paddr : integer := 0; --! ADDR field of the APB BAR | |
|
37 | pmask : integer := 16#fff#; --! MASK field of the APB BAR | |
|
38 | pirq : integer := 0; --! 2 consecutive IRQ lines are used | |
|
39 | masterclk : integer := 25000000; --! master clock in Hz | |
|
40 | timeclk : integer := 49152000; --! other clock in Hz | |
|
41 | finetimeclk : integer := 65536 --! divided clock used for the fine time counter | |
|
42 | ); | |
|
43 | ||
|
44 | Port ( | |
|
45 | clk25MHz : in STD_LOGIC; --! Clock | |
|
46 | clk49_152MHz : in STD_LOGIC; --! secondary clock | |
|
47 | resetn : in STD_LOGIC; --! Reset | |
|
48 | grspw_tick : in STD_LOGIC; --! grspw signal asserted when a valid time-code is received | |
|
49 | apbi : in apb_slv_in_type; --! APB slave input signals | |
|
50 | apbo : out apb_slv_out_type; --! APB slave output signals | |
|
51 | coarse_time : out std_logic_vector(31 downto 0); --! coarse time | |
|
52 | fine_time : out std_logic_vector(31 downto 0) --! fine time | |
|
53 | ); | |
|
54 | ||
|
28 | ||
|
29 | --*************************** | |
|
30 | -- APB_LFR_TIME_MANAGEMENT | |
|
31 | ||
|
32 | component apb_lfr_time_management is | |
|
33 | ||
|
34 | generic( | |
|
35 | pindex : integer := 0; --! APB slave index | |
|
36 | paddr : integer := 0; --! ADDR field of the APB BAR | |
|
37 | pmask : integer := 16#fff#; --! MASK field of the APB BAR | |
|
38 | pirq : integer := 0; --! 2 consecutive IRQ lines are used | |
|
39 | masterclk : integer := 25000000; --! master clock in Hz | |
|
40 | timeclk : integer := 49152000; --! other clock in Hz | |
|
41 | finetimeclk : integer := 65536 --! divided clock used for the fine time counter | |
|
42 | ); | |
|
43 | ||
|
44 | Port ( | |
|
45 | clk25MHz : in STD_LOGIC; --! Clock | |
|
46 | clk49_152MHz : in STD_LOGIC; --! secondary clock | |
|
47 | resetn : in STD_LOGIC; --! Reset | |
|
48 | grspw_tick : in STD_LOGIC; --! grspw signal asserted when a valid time-code is received | |
|
49 | apbi : in apb_slv_in_type; --! APB slave input signals | |
|
50 | apbo : out apb_slv_out_type; --! APB slave output signals | |
|
51 | coarse_time : out std_logic_vector(31 downto 0); --! coarse time | |
|
52 | fine_time : out std_logic_vector(31 downto 0) --! fine time | |
|
53 | ); | |
|
54 | ||
|
55 | 55 | end component; |
|
56 | 56 | |
|
57 | component lfr_time_management is | |
|
58 | ||
|
59 | generic ( | |
|
60 | masterclk : integer := 25000000; -- master clock in Hz | |
|
61 | timeclk : integer := 49152000; -- 2nd clock in Hz | |
|
62 | finetimeclk : integer := 65536; -- divided clock used for the fine time counter | |
|
63 | nb_clk_div_ticks : integer := 1 -- nb ticks before commutation to AUTO state | |
|
64 | ); | |
|
65 | Port ( | |
|
66 | master_clock : in std_logic; --! Clock | |
|
67 | time_clock : in std_logic; --! 2nd Clock | |
|
68 | resetn : in std_logic; --! Reset | |
|
69 | grspw_tick : in std_logic; | |
|
70 | soft_tick : in std_logic; --! soft tick, load the coarse_time value | |
|
71 | coarse_time_load : in std_logic_vector(31 downto 0); | |
|
72 | coarse_time : out std_logic_vector(31 downto 0); | |
|
73 | fine_time : out std_logic_vector(31 downto 0); | |
|
74 | next_commutation : in std_logic_vector(31 downto 0); | |
|
75 | reset_next_commutation: out std_logic; | |
|
76 | irq1 : out std_logic; | |
|
77 | irq2 : out std_logic | |
|
78 | ); | |
|
79 | ||
|
80 | end component; | |
|
57 | component lfr_time_management is | |
|
81 | 58 |
|
|
82 | end lpp_lfr_time_management; | |
|
83 | ||
|
59 | generic ( | |
|
60 | masterclk : integer := 25000000; -- master clock in Hz | |
|
61 | timeclk : integer := 49152000; -- 2nd clock in Hz | |
|
62 | finetimeclk : integer := 65536; -- divided clock used for the fine time counter | |
|
63 | nb_clk_div_ticks : integer := 1 -- nb ticks before commutation to AUTO state | |
|
64 | ); | |
|
65 | Port ( | |
|
66 | master_clock : in std_logic; --! Clock | |
|
67 | time_clock : in std_logic; --! 2nd Clock | |
|
68 | resetn : in std_logic; --! Reset | |
|
69 | grspw_tick : in std_logic; | |
|
70 | soft_tick : in std_logic; --! soft tick, load the coarse_time value | |
|
71 | coarse_time_load : in std_logic_vector(31 downto 0); | |
|
72 | coarse_time : out std_logic_vector(31 downto 0); | |
|
73 | fine_time : out std_logic_vector(31 downto 0); | |
|
74 | next_commutation : in std_logic_vector(31 downto 0); | |
|
75 | reset_next_commutation: out std_logic; | |
|
76 | irq1 : out std_logic; | |
|
77 | irq2 : out std_logic | |
|
78 | ); | |
|
79 | ||
|
80 | end component; | |
|
81 | ||
|
82 | end lpp_lfr_time_management; | |
|
83 |
@@ -1,3 +1,3 | |||
|
1 |
|
|
|
1 | lpp_lfr_time_management.vhd | |
|
2 | 2 | lfr_time_management.vhd |
|
3 |
|
|
|
3 | apb_lfr_time_management.vhd |
@@ -80,6 +80,8 signal nCE3int : std_logic:='1'; | |||
|
80 | 80 | Type stateT is (idle,st1,st2,st3,st4); |
|
81 | 81 | signal state : stateT; |
|
82 | 82 | |
|
83 | SIGNAL nclk : STD_LOGIC; | |
|
84 | ||
|
83 | 85 | begin |
|
84 | 86 | |
|
85 | 87 | process(clk , mem_ctrlr_o.RAMSN(0)) |
@@ -102,8 +104,9 begin | |||
|
102 | 104 | end if; |
|
103 | 105 | end process; |
|
104 | 106 | |
|
107 | nclk <= NOT clk; | |
|
105 | 108 | ssram_clk_pad : outpad generic map (tech => tech) |
|
106 |
port map (SSRAM_CLK,n |
|
|
109 | port map (SSRAM_CLK,nclk); | |
|
107 | 110 | |
|
108 | 111 | |
|
109 | 112 | nBWaint <= mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0); |
@@ -181,4 +184,4 MODE_pad : outpad generic map (tech => t | |||
|
181 | 184 | ZZ_pad : outpad generic map (tech => tech) |
|
182 | 185 | port map (ZZ, '0'); |
|
183 | 186 | |
|
184 | end architecture; No newline at end of file | |
|
187 | end architecture; |
This diff has been collapsed as it changes many lines, (1000 lines changed) Show them Hide them | |||
@@ -1,498 +1,502 | |||
|
1 | LIBRARY ieee; | |
|
2 | USE ieee.std_logic_1164.ALL; | |
|
3 | USE ieee.numeric_std.ALL; | |
|
4 | ||
|
5 | LIBRARY lpp; | |
|
6 | USE lpp.lpp_ad_conv.ALL; | |
|
7 | USE lpp.iir_filter.ALL; | |
|
8 | USE lpp.FILTERcfg.ALL; | |
|
9 | USE lpp.lpp_memory.ALL; | |
|
10 | USE lpp.lpp_waveform_pkg.ALL; | |
|
11 | ||
|
12 | LIBRARY techmap; | |
|
13 | USE techmap.gencomp.ALL; | |
|
14 | ||
|
15 | LIBRARY grlib; | |
|
16 | USE grlib.amba.ALL; | |
|
17 | USE grlib.stdlib.ALL; | |
|
18 | USE grlib.devices.ALL; | |
|
19 | USE GRLIB.DMA2AHB_Package.ALL; | |
|
20 | ||
|
21 | ENTITY lpp_top_lfr_wf_picker_ip IS | |
|
22 | GENERIC( | |
|
23 | hindex : INTEGER := 2; | |
|
24 | nb_burst_available_size : INTEGER := 11; | |
|
25 | nb_snapshot_param_size : INTEGER := 11; | |
|
26 | delta_snapshot_size : INTEGER := 16; | |
|
27 | delta_f2_f0_size : INTEGER := 10; | |
|
28 | delta_f2_f1_size : INTEGER := 10; | |
|
29 | tech : INTEGER := 0 | |
|
30 | ); | |
|
31 | PORT ( | |
|
32 | -- ADS7886 | |
|
33 | cnv_run : IN STD_LOGIC; | |
|
34 | cnv : OUT STD_LOGIC; | |
|
35 | sck : OUT STD_LOGIC; | |
|
36 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
37 | -- | |
|
38 | cnv_clk : IN STD_LOGIC; | |
|
39 | cnv_rstn : IN STD_LOGIC; | |
|
40 | -- | |
|
41 | clk : IN STD_LOGIC; | |
|
42 | rstn : IN STD_LOGIC; | |
|
43 | -- | |
|
44 | sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
|
45 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
46 | -- | |
|
47 | sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
|
48 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
49 | -- | |
|
50 | sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
|
51 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
52 | -- | |
|
53 | sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
|
54 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
55 | ||
|
56 | -- AMBA AHB Master Interface | |
|
57 | AHB_Master_In : IN AHB_Mst_In_Type; | |
|
58 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
|
59 | ||
|
60 | coarse_time_0 : IN STD_LOGIC; | |
|
61 | ||
|
62 | --config | |
|
63 | data_shaping_SP0 : IN STD_LOGIC; | |
|
64 | data_shaping_SP1 : IN STD_LOGIC; | |
|
65 | data_shaping_R0 : IN STD_LOGIC; | |
|
66 | data_shaping_R1 : IN STD_LOGIC; | |
|
67 | ||
|
68 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |
|
69 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |
|
70 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |
|
71 | ||
|
72 | enable_f0 : IN STD_LOGIC; | |
|
73 | enable_f1 : IN STD_LOGIC; | |
|
74 | enable_f2 : IN STD_LOGIC; | |
|
75 | enable_f3 : IN STD_LOGIC; | |
|
76 | ||
|
77 | burst_f0 : IN STD_LOGIC; | |
|
78 | burst_f1 : IN STD_LOGIC; | |
|
79 | burst_f2 : IN STD_LOGIC; | |
|
80 | ||
|
81 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |
|
82 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
|
83 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
84 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
85 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
86 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma | |
|
87 | ||
|
88 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
89 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
90 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
91 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
92 | ); | |
|
93 | END lpp_top_lfr_wf_picker_ip; | |
|
94 | ||
|
95 | ARCHITECTURE tb OF lpp_top_lfr_wf_picker_ip IS | |
|
96 | ||
|
97 | COMPONENT Downsampling | |
|
98 | GENERIC ( | |
|
99 | ChanelCount : INTEGER; | |
|
100 | SampleSize : INTEGER; | |
|
101 | DivideParam : INTEGER); | |
|
102 | PORT ( | |
|
103 | clk : IN STD_LOGIC; | |
|
104 | rstn : IN STD_LOGIC; | |
|
105 | sample_in_val : IN STD_LOGIC; | |
|
106 | sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); | |
|
107 | sample_out_val : OUT STD_LOGIC; | |
|
108 | sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); | |
|
109 | END COMPONENT; | |
|
110 | ||
|
111 | ----------------------------------------------------------------------------- | |
|
112 | CONSTANT ChanelCount : INTEGER := 8; | |
|
113 | CONSTANT ncycle_cnv_high : INTEGER := 79; | |
|
114 | CONSTANT ncycle_cnv : INTEGER := 500; | |
|
115 | ||
|
116 | ----------------------------------------------------------------------------- | |
|
117 | SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); | |
|
118 | SIGNAL sample_val : STD_LOGIC; | |
|
119 | SIGNAL sample_val_delay : STD_LOGIC; | |
|
120 | ----------------------------------------------------------------------------- | |
|
121 | CONSTANT Coef_SZ : INTEGER := 9; | |
|
122 | CONSTANT CoefCntPerCel : INTEGER := 6; | |
|
123 | CONSTANT CoefPerCel : INTEGER := 5; | |
|
124 | CONSTANT Cels_count : INTEGER := 5; | |
|
125 | ||
|
126 | SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); | |
|
127 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); | |
|
128 | SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
|
129 | SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
|
130 | -- | |
|
131 | SIGNAL sample_filter_v2_out_val : STD_LOGIC; | |
|
132 | SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
|
133 | ----------------------------------------------------------------------------- | |
|
134 | SIGNAL sample_data_shaping_out_val : STD_LOGIC; | |
|
135 | SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
|
136 | SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |
|
137 | SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |
|
138 | SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |
|
139 | SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |
|
140 | SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |
|
141 | ----------------------------------------------------------------------------- | |
|
142 | SIGNAL sample_filter_v2_out_val_s : STD_LOGIC; | |
|
143 | SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); | |
|
144 | ----------------------------------------------------------------------------- | |
|
145 | SIGNAL sample_f0_val : STD_LOGIC; | |
|
146 | SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); | |
|
147 | SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |
|
148 | -- | |
|
149 | SIGNAL sample_f1_val : STD_LOGIC; | |
|
150 | SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); | |
|
151 | SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |
|
152 | -- | |
|
153 | SIGNAL sample_f2_val : STD_LOGIC; | |
|
154 | SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |
|
155 | -- | |
|
156 | SIGNAL sample_f3_val : STD_LOGIC; | |
|
157 | SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |
|
158 | ||
|
159 | ----------------------------------------------------------------------------- | |
|
160 | SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |
|
161 | SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |
|
162 | SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |
|
163 | SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |
|
164 | ----------------------------------------------------------------------------- | |
|
165 | ||
|
166 | SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
167 | SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
168 | SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
169 | SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
170 | BEGIN | |
|
171 | ||
|
172 | -- component instantiation | |
|
173 | ----------------------------------------------------------------------------- | |
|
174 | DIGITAL_acquisition : AD7688_drvr | |
|
175 | GENERIC MAP ( | |
|
176 | ChanelCount => ChanelCount, | |
|
177 | ncycle_cnv_high => ncycle_cnv_high, | |
|
178 | ncycle_cnv => ncycle_cnv) | |
|
179 | PORT MAP ( | |
|
180 | cnv_clk => cnv_clk, -- | |
|
181 | cnv_rstn => cnv_rstn, -- | |
|
182 | cnv_run => cnv_run, -- | |
|
183 | cnv => cnv, -- | |
|
184 | clk => clk, -- | |
|
185 | rstn => rstn, -- | |
|
186 | sck => sck, -- | |
|
187 | sdo => sdo(ChanelCount-1 DOWNTO 0), -- | |
|
188 | sample => sample, | |
|
189 | sample_val => sample_val); | |
|
190 | ||
|
191 | ----------------------------------------------------------------------------- | |
|
192 | ||
|
193 | PROCESS (clk, rstn) | |
|
194 | BEGIN -- PROCESS | |
|
195 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
196 | sample_val_delay <= '0'; | |
|
197 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
198 | sample_val_delay <= sample_val; | |
|
199 | END IF; | |
|
200 | END PROCESS; | |
|
201 | ||
|
202 | ----------------------------------------------------------------------------- | |
|
203 | ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE | |
|
204 | SampleLoop : FOR j IN 0 TO 15 GENERATE | |
|
205 | sample_filter_in(i, j) <= sample(i)(j); | |
|
206 | END GENERATE; | |
|
207 | ||
|
208 | sample_filter_in(i, 16) <= sample(i)(15); | |
|
209 | sample_filter_in(i, 17) <= sample(i)(15); | |
|
210 | END GENERATE; | |
|
211 | ||
|
212 | coefs_v2 <= CoefsInitValCst_v2; | |
|
213 | ||
|
214 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 | |
|
215 | GENERIC MAP ( | |
|
216 | tech => 0, | |
|
217 | Mem_use => use_RAM, -- use_RAM | |
|
218 | Sample_SZ => 18, | |
|
219 | Coef_SZ => Coef_SZ, | |
|
220 | Coef_Nb => 25, | |
|
221 | Coef_sel_SZ => 5, | |
|
222 | Cels_count => Cels_count, | |
|
223 | ChanelsCount => ChanelCount) | |
|
224 | PORT MAP ( | |
|
225 | rstn => rstn, | |
|
226 | clk => clk, | |
|
227 | virg_pos => 7, | |
|
228 | coefs => coefs_v2, | |
|
229 | sample_in_val => sample_val_delay, | |
|
230 | sample_in => sample_filter_in, | |
|
231 | sample_out_val => sample_filter_v2_out_val, | |
|
232 | sample_out => sample_filter_v2_out); | |
|
233 | ||
|
234 | ----------------------------------------------------------------------------- | |
|
235 | -- DATA_SHAPING | |
|
236 | ----------------------------------------------------------------------------- | |
|
237 | all_data_shaping_in_loop: FOR I IN 17 DOWNTO 0 GENERATE | |
|
238 | sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0,I); | |
|
239 | sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1,I); | |
|
240 | sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2,I); | |
|
241 | END GENERATE all_data_shaping_in_loop; | |
|
242 | ||
|
243 | sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s; | |
|
244 | sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s; | |
|
245 | ||
|
246 | PROCESS (clk, rstn) | |
|
247 | BEGIN -- PROCESS | |
|
248 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
249 | sample_data_shaping_out_val <= '0'; | |
|
250 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
251 | sample_data_shaping_out_val <= sample_filter_v2_out_val; | |
|
252 | END IF; | |
|
253 | END PROCESS; | |
|
254 | ||
|
255 | SampleLoop_data_shaping: FOR j IN 0 TO 17 GENERATE | |
|
256 | PROCESS (clk, rstn) | |
|
257 | BEGIN | |
|
258 | IF rstn = '0' THEN | |
|
259 | sample_data_shaping_out(0,j) <= '0'; | |
|
260 | sample_data_shaping_out(1,j) <= '0'; | |
|
261 | sample_data_shaping_out(2,j) <= '0'; | |
|
262 | sample_data_shaping_out(3,j) <= '0'; | |
|
263 | sample_data_shaping_out(4,j) <= '0'; | |
|
264 | sample_data_shaping_out(5,j) <= '0'; | |
|
265 | sample_data_shaping_out(6,j) <= '0'; | |
|
266 | sample_data_shaping_out(7,j) <= '0'; | |
|
267 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
268 | sample_data_shaping_out(0,j) <= sample_filter_v2_out(0,j); | |
|
269 | IF data_shaping_SP0 = '1' THEN | |
|
270 | sample_data_shaping_out(1,j) <= sample_data_shaping_f1_f0_s(j); | |
|
271 | ELSE | |
|
272 | sample_data_shaping_out(1,j) <= sample_filter_v2_out(1,j); | |
|
273 | END IF; | |
|
274 | IF data_shaping_SP1 = '1' THEN | |
|
275 | sample_data_shaping_out(2,j) <= sample_data_shaping_f2_f1_s(j); | |
|
276 | ELSE | |
|
277 | sample_data_shaping_out(2,j) <= sample_filter_v2_out(2,j); | |
|
278 | END IF; | |
|
279 | sample_data_shaping_out(4,j) <= sample_filter_v2_out(4,j); | |
|
280 | sample_data_shaping_out(5,j) <= sample_filter_v2_out(5,j); | |
|
281 | sample_data_shaping_out(6,j) <= sample_filter_v2_out(6,j); | |
|
282 | sample_data_shaping_out(7,j) <= sample_filter_v2_out(7,j); | |
|
283 | END IF; | |
|
284 | END PROCESS; | |
|
285 | END GENERATE; | |
|
286 | ||
|
287 | sample_filter_v2_out_val_s <= sample_data_shaping_out_val; | |
|
288 | ChanelLoopOut : FOR i IN 0 TO 7 GENERATE | |
|
289 | SampleLoopOut : FOR j IN 0 TO 15 GENERATE | |
|
290 | sample_filter_v2_out_s(i,j) <= sample_data_shaping_out(i,j); | |
|
291 | END GENERATE; | |
|
292 | END GENERATE; | |
|
293 | ----------------------------------------------------------------------------- | |
|
294 | -- F0 -- @24.576 kHz | |
|
295 | ----------------------------------------------------------------------------- | |
|
296 | Downsampling_f0 : Downsampling | |
|
297 | GENERIC MAP ( | |
|
298 | ChanelCount => 8, | |
|
299 | SampleSize => 16, | |
|
300 | DivideParam => 4) | |
|
301 | PORT MAP ( | |
|
302 | clk => clk, | |
|
303 | rstn => rstn, | |
|
304 | sample_in_val => sample_filter_v2_out_val_s, | |
|
305 | sample_in => sample_filter_v2_out_s, | |
|
306 | sample_out_val => sample_f0_val, | |
|
307 | sample_out => sample_f0); | |
|
308 | ||
|
309 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE | |
|
310 | sample_f0_wdata_s(I) <= sample_f0(0, I); -- V | |
|
311 | sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1 | |
|
312 | sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2 | |
|
313 | sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1 | |
|
314 | sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2 | |
|
315 | sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3 | |
|
316 | END GENERATE all_bit_sample_f0; | |
|
317 | ||
|
318 | sample_f0_wen <= NOT(sample_f0_val) & | |
|
319 | NOT(sample_f0_val) & | |
|
320 | NOT(sample_f0_val) & | |
|
321 | NOT(sample_f0_val) & | |
|
322 | NOT(sample_f0_val) & | |
|
323 | NOT(sample_f0_val); | |
|
324 | ||
|
325 | ----------------------------------------------------------------------------- | |
|
326 | -- F1 -- @4096 Hz | |
|
327 | ----------------------------------------------------------------------------- | |
|
328 | Downsampling_f1 : Downsampling | |
|
329 | GENERIC MAP ( | |
|
330 | ChanelCount => 8, | |
|
331 | SampleSize => 16, | |
|
332 | DivideParam => 6) | |
|
333 | PORT MAP ( | |
|
334 | clk => clk, | |
|
335 | rstn => rstn, | |
|
336 | sample_in_val => sample_f0_val , | |
|
337 | sample_in => sample_f0, | |
|
338 | sample_out_val => sample_f1_val, | |
|
339 | sample_out => sample_f1); | |
|
340 | ||
|
341 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE | |
|
342 | sample_f1_wdata_s(I) <= sample_f1(0, I); -- V | |
|
343 | sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1 | |
|
344 | sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2 | |
|
345 | sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1 | |
|
346 | sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2 | |
|
347 | sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3 | |
|
348 | END GENERATE all_bit_sample_f1; | |
|
349 | ||
|
350 | sample_f1_wen <= NOT(sample_f1_val) & | |
|
351 | NOT(sample_f1_val) & | |
|
352 | NOT(sample_f1_val) & | |
|
353 | NOT(sample_f1_val) & | |
|
354 | NOT(sample_f1_val) & | |
|
355 | NOT(sample_f1_val); | |
|
356 | ||
|
357 | ----------------------------------------------------------------------------- | |
|
358 | -- F2 -- @256 Hz | |
|
359 | ----------------------------------------------------------------------------- | |
|
360 | all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE | |
|
361 | sample_f0_s(0, I) <= sample_f0(0, I); -- V | |
|
362 | sample_f0_s(1, I) <= sample_f0(1, I); -- E1 | |
|
363 | sample_f0_s(2, I) <= sample_f0(2, I); -- E2 | |
|
364 | sample_f0_s(3, I) <= sample_f0(5, I); -- B1 | |
|
365 | sample_f0_s(4, I) <= sample_f0(6, I); -- B2 | |
|
366 | sample_f0_s(5, I) <= sample_f0(7, I); -- B3 | |
|
367 | END GENERATE all_bit_sample_f0_s; | |
|
368 | ||
|
369 | Downsampling_f2 : Downsampling | |
|
370 | GENERIC MAP ( | |
|
371 | ChanelCount => 6, | |
|
372 | SampleSize => 16, | |
|
373 | DivideParam => 96) | |
|
374 | PORT MAP ( | |
|
375 | clk => clk, | |
|
376 | rstn => rstn, | |
|
377 | sample_in_val => sample_f0_val , | |
|
378 | sample_in => sample_f0_s, | |
|
379 | sample_out_val => sample_f2_val, | |
|
380 | sample_out => sample_f2); | |
|
381 | ||
|
382 | sample_f2_wen <= NOT(sample_f2_val) & | |
|
383 | NOT(sample_f2_val) & | |
|
384 | NOT(sample_f2_val) & | |
|
385 | NOT(sample_f2_val) & | |
|
386 | NOT(sample_f2_val) & | |
|
387 | NOT(sample_f2_val); | |
|
388 | ||
|
389 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE | |
|
390 | sample_f2_wdata_s(I) <= sample_f2(0, I); | |
|
391 | sample_f2_wdata_s(16*1+I) <= sample_f2(1, I); | |
|
392 | sample_f2_wdata_s(16*2+I) <= sample_f2(2, I); | |
|
393 | sample_f2_wdata_s(16*3+I) <= sample_f2(3, I); | |
|
394 | sample_f2_wdata_s(16*4+I) <= sample_f2(4, I); | |
|
395 | sample_f2_wdata_s(16*5+I) <= sample_f2(5, I); | |
|
396 | END GENERATE all_bit_sample_f2; | |
|
397 | ||
|
398 | ----------------------------------------------------------------------------- | |
|
399 | -- F3 -- @16 Hz | |
|
400 | ----------------------------------------------------------------------------- | |
|
401 | all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE | |
|
402 | sample_f1_s(0, I) <= sample_f1(0, I); -- V | |
|
403 | sample_f1_s(1, I) <= sample_f1(1, I); -- E1 | |
|
404 | sample_f1_s(2, I) <= sample_f1(2, I); -- E2 | |
|
405 | sample_f1_s(3, I) <= sample_f1(5, I); -- B1 | |
|
406 | sample_f1_s(4, I) <= sample_f1(6, I); -- B2 | |
|
407 | sample_f1_s(5, I) <= sample_f1(7, I); -- B3 | |
|
408 | END GENERATE all_bit_sample_f1_s; | |
|
409 | ||
|
410 | Downsampling_f3 : Downsampling | |
|
411 | GENERIC MAP ( | |
|
412 | ChanelCount => 6, | |
|
413 | SampleSize => 16, | |
|
414 | DivideParam => 256) | |
|
415 | PORT MAP ( | |
|
416 | clk => clk, | |
|
417 | rstn => rstn, | |
|
418 | sample_in_val => sample_f1_val , | |
|
419 | sample_in => sample_f1_s, | |
|
420 | sample_out_val => sample_f3_val, | |
|
421 | sample_out => sample_f3); | |
|
422 | ||
|
423 | sample_f3_wen <= (NOT sample_f3_val) & | |
|
424 | (NOT sample_f3_val) & | |
|
425 | (NOT sample_f3_val) & | |
|
426 | (NOT sample_f3_val) & | |
|
427 | (NOT sample_f3_val) & | |
|
428 | (NOT sample_f3_val); | |
|
429 | ||
|
430 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE | |
|
431 | sample_f3_wdata_s(I) <= sample_f3(0, I); | |
|
432 | sample_f3_wdata_s(16*1+I) <= sample_f3(1, I); | |
|
433 | sample_f3_wdata_s(16*2+I) <= sample_f3(2, I); | |
|
434 | sample_f3_wdata_s(16*3+I) <= sample_f3(3, I); | |
|
435 | sample_f3_wdata_s(16*4+I) <= sample_f3(4, I); | |
|
436 | sample_f3_wdata_s(16*5+I) <= sample_f3(5, I); | |
|
437 | END GENERATE all_bit_sample_f3; | |
|
438 | ||
|
439 | lpp_waveform_1 : lpp_waveform | |
|
440 | GENERIC MAP ( | |
|
441 | hindex => hindex, | |
|
442 | tech => tech, | |
|
443 | data_size => 160, | |
|
444 | nb_burst_available_size => nb_burst_available_size, | |
|
445 | nb_snapshot_param_size => nb_snapshot_param_size, | |
|
446 | delta_snapshot_size => delta_snapshot_size, | |
|
447 | delta_f2_f0_size => delta_f2_f0_size, | |
|
448 | delta_f2_f1_size => delta_f2_f1_size) | |
|
449 | PORT MAP ( | |
|
450 | clk => clk, | |
|
451 | rstn => rstn, | |
|
452 | ||
|
453 | AHB_Master_In => AHB_Master_In, | |
|
454 | AHB_Master_Out => AHB_Master_Out, | |
|
455 | ||
|
456 | coarse_time_0 => coarse_time_0, -- IN | |
|
457 | delta_snapshot => delta_snapshot, -- IN | |
|
458 | delta_f2_f1 => delta_f2_f1, -- IN | |
|
459 | delta_f2_f0 => delta_f2_f0, -- IN | |
|
460 | enable_f0 => enable_f0, -- IN | |
|
461 | enable_f1 => enable_f1, -- IN | |
|
462 | enable_f2 => enable_f2, -- IN | |
|
463 | enable_f3 => enable_f3, -- IN | |
|
464 | burst_f0 => burst_f0, -- IN | |
|
465 | burst_f1 => burst_f1, -- IN | |
|
466 | burst_f2 => burst_f2, -- IN | |
|
467 | nb_burst_available => nb_burst_available, | |
|
468 | nb_snapshot_param => nb_snapshot_param, | |
|
469 | status_full => status_full, | |
|
470 | status_full_ack => status_full_ack, -- IN | |
|
471 | status_full_err => status_full_err, | |
|
472 | status_new_err => status_new_err, | |
|
473 | ||
|
474 | addr_data_f0 => addr_data_f0, -- IN | |
|
475 | addr_data_f1 => addr_data_f1, -- IN | |
|
476 | addr_data_f2 => addr_data_f2, -- IN | |
|
477 | addr_data_f3 => addr_data_f3, -- IN | |
|
478 | ||
|
479 | data_f0_in => data_f0_in_valid, | |
|
480 | data_f1_in => data_f1_in_valid, | |
|
481 | data_f2_in => data_f2_in_valid, | |
|
482 | data_f3_in => data_f3_in_valid, | |
|
483 | data_f0_in_valid => sample_f0_val, | |
|
484 | data_f1_in_valid => sample_f1_val, | |
|
485 | data_f2_in_valid => sample_f2_val, | |
|
486 | data_f3_in_valid => sample_f3_val); | |
|
487 | ||
|
488 |
data_f0_in_valid(( |
|
|
489 |
|
|
|
490 |
data_f2_in_valid(( |
|
|
491 |
|
|
|
492 | ||
|
493 | sample_f0_wdata <= sample_f0_wdata_s; | |
|
494 | sample_f1_wdata <= sample_f1_wdata_s; | |
|
495 | sample_f2_wdata <= sample_f2_wdata_s; | |
|
496 | sample_f3_wdata <= sample_f3_wdata_s; | |
|
497 | ||
|
498 | END tb; | |
|
1 | LIBRARY ieee; | |
|
2 | USE ieee.std_logic_1164.ALL; | |
|
3 | USE ieee.numeric_std.ALL; | |
|
4 | ||
|
5 | LIBRARY lpp; | |
|
6 | USE lpp.lpp_ad_conv.ALL; | |
|
7 | USE lpp.iir_filter.ALL; | |
|
8 | USE lpp.FILTERcfg.ALL; | |
|
9 | USE lpp.lpp_memory.ALL; | |
|
10 | USE lpp.lpp_waveform_pkg.ALL; | |
|
11 | ||
|
12 | LIBRARY techmap; | |
|
13 | USE techmap.gencomp.ALL; | |
|
14 | ||
|
15 | LIBRARY grlib; | |
|
16 | USE grlib.amba.ALL; | |
|
17 | USE grlib.stdlib.ALL; | |
|
18 | USE grlib.devices.ALL; | |
|
19 | USE GRLIB.DMA2AHB_Package.ALL; | |
|
20 | ||
|
21 | ENTITY lpp_top_lfr_wf_picker_ip IS | |
|
22 | GENERIC( | |
|
23 | hindex : INTEGER := 2; | |
|
24 | nb_burst_available_size : INTEGER := 11; | |
|
25 | nb_snapshot_param_size : INTEGER := 11; | |
|
26 | delta_snapshot_size : INTEGER := 16; | |
|
27 | delta_f2_f0_size : INTEGER := 10; | |
|
28 | delta_f2_f1_size : INTEGER := 10; | |
|
29 | tech : INTEGER := 0 | |
|
30 | ); | |
|
31 | PORT ( | |
|
32 | -- ADS7886 | |
|
33 | cnv_run : IN STD_LOGIC; | |
|
34 | cnv : OUT STD_LOGIC; | |
|
35 | sck : OUT STD_LOGIC; | |
|
36 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
37 | -- | |
|
38 | cnv_clk : IN STD_LOGIC; | |
|
39 | cnv_rstn : IN STD_LOGIC; | |
|
40 | -- | |
|
41 | clk : IN STD_LOGIC; | |
|
42 | rstn : IN STD_LOGIC; | |
|
43 | -- | |
|
44 | sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
|
45 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
46 | -- | |
|
47 | sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
|
48 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
49 | -- | |
|
50 | sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
|
51 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
52 | -- | |
|
53 | sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
|
54 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
55 | ||
|
56 | -- AMBA AHB Master Interface | |
|
57 | AHB_Master_In : IN AHB_Mst_In_Type; | |
|
58 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
|
59 | ||
|
60 | coarse_time_0 : IN STD_LOGIC; | |
|
61 | ||
|
62 | --config | |
|
63 | data_shaping_SP0 : IN STD_LOGIC; | |
|
64 | data_shaping_SP1 : IN STD_LOGIC; | |
|
65 | data_shaping_R0 : IN STD_LOGIC; | |
|
66 | data_shaping_R1 : IN STD_LOGIC; | |
|
67 | ||
|
68 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |
|
69 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |
|
70 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |
|
71 | ||
|
72 | enable_f0 : IN STD_LOGIC; | |
|
73 | enable_f1 : IN STD_LOGIC; | |
|
74 | enable_f2 : IN STD_LOGIC; | |
|
75 | enable_f3 : IN STD_LOGIC; | |
|
76 | ||
|
77 | burst_f0 : IN STD_LOGIC; | |
|
78 | burst_f1 : IN STD_LOGIC; | |
|
79 | burst_f2 : IN STD_LOGIC; | |
|
80 | ||
|
81 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |
|
82 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
|
83 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
84 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
85 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
86 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma | |
|
87 | ||
|
88 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
89 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
90 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
91 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
92 | ); | |
|
93 | END lpp_top_lfr_wf_picker_ip; | |
|
94 | ||
|
95 | ARCHITECTURE tb OF lpp_top_lfr_wf_picker_ip IS | |
|
96 | ||
|
97 | COMPONENT Downsampling | |
|
98 | GENERIC ( | |
|
99 | ChanelCount : INTEGER; | |
|
100 | SampleSize : INTEGER; | |
|
101 | DivideParam : INTEGER); | |
|
102 | PORT ( | |
|
103 | clk : IN STD_LOGIC; | |
|
104 | rstn : IN STD_LOGIC; | |
|
105 | sample_in_val : IN STD_LOGIC; | |
|
106 | sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); | |
|
107 | sample_out_val : OUT STD_LOGIC; | |
|
108 | sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); | |
|
109 | END COMPONENT; | |
|
110 | ||
|
111 | ----------------------------------------------------------------------------- | |
|
112 | CONSTANT ChanelCount : INTEGER := 8; | |
|
113 | CONSTANT ncycle_cnv_high : INTEGER := 79; | |
|
114 | CONSTANT ncycle_cnv : INTEGER := 500; | |
|
115 | ||
|
116 | ----------------------------------------------------------------------------- | |
|
117 | SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); | |
|
118 | SIGNAL sample_val : STD_LOGIC; | |
|
119 | SIGNAL sample_val_delay : STD_LOGIC; | |
|
120 | ----------------------------------------------------------------------------- | |
|
121 | CONSTANT Coef_SZ : INTEGER := 9; | |
|
122 | CONSTANT CoefCntPerCel : INTEGER := 6; | |
|
123 | CONSTANT CoefPerCel : INTEGER := 5; | |
|
124 | CONSTANT Cels_count : INTEGER := 5; | |
|
125 | ||
|
126 | SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); | |
|
127 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); | |
|
128 | SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
|
129 | SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
|
130 | -- | |
|
131 | SIGNAL sample_filter_v2_out_val : STD_LOGIC; | |
|
132 | SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
|
133 | ----------------------------------------------------------------------------- | |
|
134 | SIGNAL sample_data_shaping_out_val : STD_LOGIC; | |
|
135 | SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
|
136 | SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |
|
137 | SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |
|
138 | SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |
|
139 | SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |
|
140 | SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |
|
141 | ----------------------------------------------------------------------------- | |
|
142 | SIGNAL sample_filter_v2_out_val_s : STD_LOGIC; | |
|
143 | SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); | |
|
144 | ----------------------------------------------------------------------------- | |
|
145 | SIGNAL sample_f0_val : STD_LOGIC; | |
|
146 | SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); | |
|
147 | SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |
|
148 | -- | |
|
149 | SIGNAL sample_f1_val : STD_LOGIC; | |
|
150 | SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); | |
|
151 | SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |
|
152 | -- | |
|
153 | SIGNAL sample_f2_val : STD_LOGIC; | |
|
154 | SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |
|
155 | -- | |
|
156 | SIGNAL sample_f3_val : STD_LOGIC; | |
|
157 | SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |
|
158 | ||
|
159 | ----------------------------------------------------------------------------- | |
|
160 | SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |
|
161 | SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |
|
162 | SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |
|
163 | SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |
|
164 | ----------------------------------------------------------------------------- | |
|
165 | ||
|
166 | SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
167 | SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
168 | SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
169 | SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
170 | BEGIN | |
|
171 | ||
|
172 | -- component instantiation | |
|
173 | ----------------------------------------------------------------------------- | |
|
174 | DIGITAL_acquisition : AD7688_drvr | |
|
175 | GENERIC MAP ( | |
|
176 | ChanelCount => ChanelCount, | |
|
177 | ncycle_cnv_high => ncycle_cnv_high, | |
|
178 | ncycle_cnv => ncycle_cnv) | |
|
179 | PORT MAP ( | |
|
180 | cnv_clk => cnv_clk, -- | |
|
181 | cnv_rstn => cnv_rstn, -- | |
|
182 | cnv_run => cnv_run, -- | |
|
183 | cnv => cnv, -- | |
|
184 | clk => clk, -- | |
|
185 | rstn => rstn, -- | |
|
186 | sck => sck, -- | |
|
187 | sdo => sdo(ChanelCount-1 DOWNTO 0), -- | |
|
188 | sample => sample, | |
|
189 | sample_val => sample_val); | |
|
190 | ||
|
191 | ----------------------------------------------------------------------------- | |
|
192 | ||
|
193 | PROCESS (clk, rstn) | |
|
194 | BEGIN -- PROCESS | |
|
195 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
196 | sample_val_delay <= '0'; | |
|
197 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
198 | sample_val_delay <= sample_val; | |
|
199 | END IF; | |
|
200 | END PROCESS; | |
|
201 | ||
|
202 | ----------------------------------------------------------------------------- | |
|
203 | ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE | |
|
204 | SampleLoop : FOR j IN 0 TO 15 GENERATE | |
|
205 | sample_filter_in(i, j) <= sample(i)(j); | |
|
206 | END GENERATE; | |
|
207 | ||
|
208 | sample_filter_in(i, 16) <= sample(i)(15); | |
|
209 | sample_filter_in(i, 17) <= sample(i)(15); | |
|
210 | END GENERATE; | |
|
211 | ||
|
212 | coefs_v2 <= CoefsInitValCst_v2; | |
|
213 | ||
|
214 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 | |
|
215 | GENERIC MAP ( | |
|
216 | tech => 0, | |
|
217 | Mem_use => use_RAM, -- use_RAM | |
|
218 | Sample_SZ => 18, | |
|
219 | Coef_SZ => Coef_SZ, | |
|
220 | Coef_Nb => 25, | |
|
221 | Coef_sel_SZ => 5, | |
|
222 | Cels_count => Cels_count, | |
|
223 | ChanelsCount => ChanelCount) | |
|
224 | PORT MAP ( | |
|
225 | rstn => rstn, | |
|
226 | clk => clk, | |
|
227 | virg_pos => 7, | |
|
228 | coefs => coefs_v2, | |
|
229 | sample_in_val => sample_val_delay, | |
|
230 | sample_in => sample_filter_in, | |
|
231 | sample_out_val => sample_filter_v2_out_val, | |
|
232 | sample_out => sample_filter_v2_out); | |
|
233 | ||
|
234 | ----------------------------------------------------------------------------- | |
|
235 | -- DATA_SHAPING | |
|
236 | ----------------------------------------------------------------------------- | |
|
237 | all_data_shaping_in_loop: FOR I IN 17 DOWNTO 0 GENERATE | |
|
238 | sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0,I); | |
|
239 | sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1,I); | |
|
240 | sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2,I); | |
|
241 | END GENERATE all_data_shaping_in_loop; | |
|
242 | ||
|
243 | sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s; | |
|
244 | sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s; | |
|
245 | ||
|
246 | PROCESS (clk, rstn) | |
|
247 | BEGIN -- PROCESS | |
|
248 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
249 | sample_data_shaping_out_val <= '0'; | |
|
250 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
251 | sample_data_shaping_out_val <= sample_filter_v2_out_val; | |
|
252 | END IF; | |
|
253 | END PROCESS; | |
|
254 | ||
|
255 | SampleLoop_data_shaping: FOR j IN 0 TO 17 GENERATE | |
|
256 | PROCESS (clk, rstn) | |
|
257 | BEGIN | |
|
258 | IF rstn = '0' THEN | |
|
259 | sample_data_shaping_out(0,j) <= '0'; | |
|
260 | sample_data_shaping_out(1,j) <= '0'; | |
|
261 | sample_data_shaping_out(2,j) <= '0'; | |
|
262 | sample_data_shaping_out(3,j) <= '0'; | |
|
263 | sample_data_shaping_out(4,j) <= '0'; | |
|
264 | sample_data_shaping_out(5,j) <= '0'; | |
|
265 | sample_data_shaping_out(6,j) <= '0'; | |
|
266 | sample_data_shaping_out(7,j) <= '0'; | |
|
267 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
268 | sample_data_shaping_out(0,j) <= sample_filter_v2_out(0,j); | |
|
269 | IF data_shaping_SP0 = '1' THEN | |
|
270 | sample_data_shaping_out(1,j) <= sample_data_shaping_f1_f0_s(j); | |
|
271 | ELSE | |
|
272 | sample_data_shaping_out(1,j) <= sample_filter_v2_out(1,j); | |
|
273 | END IF; | |
|
274 | IF data_shaping_SP1 = '1' THEN | |
|
275 | sample_data_shaping_out(2,j) <= sample_data_shaping_f2_f1_s(j); | |
|
276 | ELSE | |
|
277 | sample_data_shaping_out(2,j) <= sample_filter_v2_out(2,j); | |
|
278 | END IF; | |
|
279 | sample_data_shaping_out(4,j) <= sample_filter_v2_out(4,j); | |
|
280 | sample_data_shaping_out(5,j) <= sample_filter_v2_out(5,j); | |
|
281 | sample_data_shaping_out(6,j) <= sample_filter_v2_out(6,j); | |
|
282 | sample_data_shaping_out(7,j) <= sample_filter_v2_out(7,j); | |
|
283 | END IF; | |
|
284 | END PROCESS; | |
|
285 | END GENERATE; | |
|
286 | ||
|
287 | sample_filter_v2_out_val_s <= sample_data_shaping_out_val; | |
|
288 | ChanelLoopOut : FOR i IN 0 TO 7 GENERATE | |
|
289 | SampleLoopOut : FOR j IN 0 TO 15 GENERATE | |
|
290 | sample_filter_v2_out_s(i,j) <= sample_data_shaping_out(i,j); | |
|
291 | END GENERATE; | |
|
292 | END GENERATE; | |
|
293 | ----------------------------------------------------------------------------- | |
|
294 | -- F0 -- @24.576 kHz | |
|
295 | ----------------------------------------------------------------------------- | |
|
296 | Downsampling_f0 : Downsampling | |
|
297 | GENERIC MAP ( | |
|
298 | ChanelCount => 8, | |
|
299 | SampleSize => 16, | |
|
300 | DivideParam => 4) | |
|
301 | PORT MAP ( | |
|
302 | clk => clk, | |
|
303 | rstn => rstn, | |
|
304 | sample_in_val => sample_filter_v2_out_val_s, | |
|
305 | sample_in => sample_filter_v2_out_s, | |
|
306 | sample_out_val => sample_f0_val, | |
|
307 | sample_out => sample_f0); | |
|
308 | ||
|
309 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE | |
|
310 | sample_f0_wdata_s(I) <= sample_f0(0, I); -- V | |
|
311 | sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1 | |
|
312 | sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2 | |
|
313 | sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1 | |
|
314 | sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2 | |
|
315 | sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3 | |
|
316 | END GENERATE all_bit_sample_f0; | |
|
317 | ||
|
318 | sample_f0_wen <= NOT(sample_f0_val) & | |
|
319 | NOT(sample_f0_val) & | |
|
320 | NOT(sample_f0_val) & | |
|
321 | NOT(sample_f0_val) & | |
|
322 | NOT(sample_f0_val) & | |
|
323 | NOT(sample_f0_val); | |
|
324 | ||
|
325 | ----------------------------------------------------------------------------- | |
|
326 | -- F1 -- @4096 Hz | |
|
327 | ----------------------------------------------------------------------------- | |
|
328 | Downsampling_f1 : Downsampling | |
|
329 | GENERIC MAP ( | |
|
330 | ChanelCount => 8, | |
|
331 | SampleSize => 16, | |
|
332 | DivideParam => 6) | |
|
333 | PORT MAP ( | |
|
334 | clk => clk, | |
|
335 | rstn => rstn, | |
|
336 | sample_in_val => sample_f0_val , | |
|
337 | sample_in => sample_f0, | |
|
338 | sample_out_val => sample_f1_val, | |
|
339 | sample_out => sample_f1); | |
|
340 | ||
|
341 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE | |
|
342 | sample_f1_wdata_s(I) <= sample_f1(0, I); -- V | |
|
343 | sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1 | |
|
344 | sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2 | |
|
345 | sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1 | |
|
346 | sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2 | |
|
347 | sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3 | |
|
348 | END GENERATE all_bit_sample_f1; | |
|
349 | ||
|
350 | sample_f1_wen <= NOT(sample_f1_val) & | |
|
351 | NOT(sample_f1_val) & | |
|
352 | NOT(sample_f1_val) & | |
|
353 | NOT(sample_f1_val) & | |
|
354 | NOT(sample_f1_val) & | |
|
355 | NOT(sample_f1_val); | |
|
356 | ||
|
357 | ----------------------------------------------------------------------------- | |
|
358 | -- F2 -- @256 Hz | |
|
359 | ----------------------------------------------------------------------------- | |
|
360 | all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE | |
|
361 | sample_f0_s(0, I) <= sample_f0(0, I); -- V | |
|
362 | sample_f0_s(1, I) <= sample_f0(1, I); -- E1 | |
|
363 | sample_f0_s(2, I) <= sample_f0(2, I); -- E2 | |
|
364 | sample_f0_s(3, I) <= sample_f0(5, I); -- B1 | |
|
365 | sample_f0_s(4, I) <= sample_f0(6, I); -- B2 | |
|
366 | sample_f0_s(5, I) <= sample_f0(7, I); -- B3 | |
|
367 | END GENERATE all_bit_sample_f0_s; | |
|
368 | ||
|
369 | Downsampling_f2 : Downsampling | |
|
370 | GENERIC MAP ( | |
|
371 | ChanelCount => 6, | |
|
372 | SampleSize => 16, | |
|
373 | DivideParam => 96) | |
|
374 | PORT MAP ( | |
|
375 | clk => clk, | |
|
376 | rstn => rstn, | |
|
377 | sample_in_val => sample_f0_val , | |
|
378 | sample_in => sample_f0_s, | |
|
379 | sample_out_val => sample_f2_val, | |
|
380 | sample_out => sample_f2); | |
|
381 | ||
|
382 | sample_f2_wen <= NOT(sample_f2_val) & | |
|
383 | NOT(sample_f2_val) & | |
|
384 | NOT(sample_f2_val) & | |
|
385 | NOT(sample_f2_val) & | |
|
386 | NOT(sample_f2_val) & | |
|
387 | NOT(sample_f2_val); | |
|
388 | ||
|
389 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE | |
|
390 | sample_f2_wdata_s(I) <= sample_f2(0, I); | |
|
391 | sample_f2_wdata_s(16*1+I) <= sample_f2(1, I); | |
|
392 | sample_f2_wdata_s(16*2+I) <= sample_f2(2, I); | |
|
393 | sample_f2_wdata_s(16*3+I) <= sample_f2(3, I); | |
|
394 | sample_f2_wdata_s(16*4+I) <= sample_f2(4, I); | |
|
395 | sample_f2_wdata_s(16*5+I) <= sample_f2(5, I); | |
|
396 | END GENERATE all_bit_sample_f2; | |
|
397 | ||
|
398 | ----------------------------------------------------------------------------- | |
|
399 | -- F3 -- @16 Hz | |
|
400 | ----------------------------------------------------------------------------- | |
|
401 | all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE | |
|
402 | sample_f1_s(0, I) <= sample_f1(0, I); -- V | |
|
403 | sample_f1_s(1, I) <= sample_f1(1, I); -- E1 | |
|
404 | sample_f1_s(2, I) <= sample_f1(2, I); -- E2 | |
|
405 | sample_f1_s(3, I) <= sample_f1(5, I); -- B1 | |
|
406 | sample_f1_s(4, I) <= sample_f1(6, I); -- B2 | |
|
407 | sample_f1_s(5, I) <= sample_f1(7, I); -- B3 | |
|
408 | END GENERATE all_bit_sample_f1_s; | |
|
409 | ||
|
410 | Downsampling_f3 : Downsampling | |
|
411 | GENERIC MAP ( | |
|
412 | ChanelCount => 6, | |
|
413 | SampleSize => 16, | |
|
414 | DivideParam => 256) | |
|
415 | PORT MAP ( | |
|
416 | clk => clk, | |
|
417 | rstn => rstn, | |
|
418 | sample_in_val => sample_f1_val , | |
|
419 | sample_in => sample_f1_s, | |
|
420 | sample_out_val => sample_f3_val, | |
|
421 | sample_out => sample_f3); | |
|
422 | ||
|
423 | sample_f3_wen <= (NOT sample_f3_val) & | |
|
424 | (NOT sample_f3_val) & | |
|
425 | (NOT sample_f3_val) & | |
|
426 | (NOT sample_f3_val) & | |
|
427 | (NOT sample_f3_val) & | |
|
428 | (NOT sample_f3_val); | |
|
429 | ||
|
430 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE | |
|
431 | sample_f3_wdata_s(I) <= sample_f3(0, I); | |
|
432 | sample_f3_wdata_s(16*1+I) <= sample_f3(1, I); | |
|
433 | sample_f3_wdata_s(16*2+I) <= sample_f3(2, I); | |
|
434 | sample_f3_wdata_s(16*3+I) <= sample_f3(3, I); | |
|
435 | sample_f3_wdata_s(16*4+I) <= sample_f3(4, I); | |
|
436 | sample_f3_wdata_s(16*5+I) <= sample_f3(5, I); | |
|
437 | END GENERATE all_bit_sample_f3; | |
|
438 | ||
|
439 | lpp_waveform_1 : lpp_waveform | |
|
440 | GENERIC MAP ( | |
|
441 | hindex => hindex, | |
|
442 | tech => tech, | |
|
443 | data_size => 160, | |
|
444 | nb_burst_available_size => nb_burst_available_size, | |
|
445 | nb_snapshot_param_size => nb_snapshot_param_size, | |
|
446 | delta_snapshot_size => delta_snapshot_size, | |
|
447 | delta_f2_f0_size => delta_f2_f0_size, | |
|
448 | delta_f2_f1_size => delta_f2_f1_size) | |
|
449 | PORT MAP ( | |
|
450 | clk => clk, | |
|
451 | rstn => rstn, | |
|
452 | ||
|
453 | AHB_Master_In => AHB_Master_In, | |
|
454 | AHB_Master_Out => AHB_Master_Out, | |
|
455 | ||
|
456 | coarse_time_0 => coarse_time_0, -- IN | |
|
457 | delta_snapshot => delta_snapshot, -- IN | |
|
458 | delta_f2_f1 => delta_f2_f1, -- IN | |
|
459 | delta_f2_f0 => delta_f2_f0, -- IN | |
|
460 | enable_f0 => enable_f0, -- IN | |
|
461 | enable_f1 => enable_f1, -- IN | |
|
462 | enable_f2 => enable_f2, -- IN | |
|
463 | enable_f3 => enable_f3, -- IN | |
|
464 | burst_f0 => burst_f0, -- IN | |
|
465 | burst_f1 => burst_f1, -- IN | |
|
466 | burst_f2 => burst_f2, -- IN | |
|
467 | nb_burst_available => nb_burst_available, | |
|
468 | nb_snapshot_param => nb_snapshot_param, | |
|
469 | status_full => status_full, | |
|
470 | status_full_ack => status_full_ack, -- IN | |
|
471 | status_full_err => status_full_err, | |
|
472 | status_new_err => status_new_err, | |
|
473 | ||
|
474 | addr_data_f0 => addr_data_f0, -- IN | |
|
475 | addr_data_f1 => addr_data_f1, -- IN | |
|
476 | addr_data_f2 => addr_data_f2, -- IN | |
|
477 | addr_data_f3 => addr_data_f3, -- IN | |
|
478 | ||
|
479 | data_f0_in => data_f0_in_valid, | |
|
480 | data_f1_in => data_f1_in_valid, | |
|
481 | data_f2_in => data_f2_in_valid, | |
|
482 | data_f3_in => data_f3_in_valid, | |
|
483 | data_f0_in_valid => sample_f0_val, | |
|
484 | data_f1_in_valid => sample_f1_val, | |
|
485 | data_f2_in_valid => sample_f2_val, | |
|
486 | data_f3_in_valid => sample_f3_val); | |
|
487 | ||
|
488 | data_f0_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); | |
|
489 | data_f1_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); | |
|
490 | data_f2_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); | |
|
491 | data_f3_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); | |
|
492 | data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s; | |
|
493 | data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s; | |
|
494 | data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s; | |
|
495 | data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s; | |
|
496 | ||
|
497 | sample_f0_wdata <= sample_f0_wdata_s; | |
|
498 | sample_f1_wdata <= sample_f1_wdata_s; | |
|
499 | sample_f2_wdata <= sample_f2_wdata_s; | |
|
500 | sample_f3_wdata <= sample_f3_wdata_s; | |
|
501 | ||
|
502 | END tb; No newline at end of file |
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