@@ -426,7 +426,7 BEGIN -- beh | |||||
426 | pirq_ms => 6, |
|
426 | pirq_ms => 6, | |
427 | pirq_wfp => 14, |
|
427 | pirq_wfp => 14, | |
428 | hindex => 2, |
|
428 | hindex => 2, | |
429 |
top_lfr_version => X"00010 |
|
429 | top_lfr_version => X"00010E") -- aa.bb.cc version | |
430 | PORT MAP ( |
|
430 | PORT MAP ( | |
431 | clk => clk_25, |
|
431 | clk => clk_25, | |
432 | rstn => reset, |
|
432 | rstn => reset, |
@@ -133,14 +133,14 ARCHITECTURE beh OF lpp_lfr IS | |||||
133 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
133 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
134 |
|
134 | |||
135 | -- SM |
|
135 | -- SM | |
136 |
SIGNAL ready_matrix_f0 |
|
136 | SIGNAL ready_matrix_f0 : STD_LOGIC; | |
137 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; |
|
137 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; | |
138 | SIGNAL ready_matrix_f1 : STD_LOGIC; |
|
138 | SIGNAL ready_matrix_f1 : STD_LOGIC; | |
139 | SIGNAL ready_matrix_f2 : STD_LOGIC; |
|
139 | SIGNAL ready_matrix_f2 : STD_LOGIC; | |
140 | -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC; |
|
140 | -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC; | |
141 | SIGNAL error_bad_component_error : STD_LOGIC; |
|
141 | SIGNAL error_bad_component_error : STD_LOGIC; | |
142 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
142 | -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
143 |
SIGNAL status_ready_matrix_f0 |
|
143 | SIGNAL status_ready_matrix_f0 : STD_LOGIC; | |
144 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; |
|
144 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; | |
145 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; |
|
145 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; | |
146 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; |
|
146 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; | |
@@ -148,7 +148,7 ARCHITECTURE beh OF lpp_lfr IS | |||||
148 | -- SIGNAL status_error_bad_component_error : STD_LOGIC; |
|
148 | -- SIGNAL status_error_bad_component_error : STD_LOGIC; | |
149 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; |
|
149 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; | |
150 | SIGNAL config_active_interruption_onError : STD_LOGIC; |
|
150 | SIGNAL config_active_interruption_onError : STD_LOGIC; | |
151 |
SIGNAL addr_matrix_f0 |
|
151 | SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
152 | -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
152 | -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
153 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
153 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
154 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
154 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
@@ -260,24 +260,6 ARCHITECTURE beh OF lpp_lfr IS | |||||
260 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
260 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
261 |
|
261 | |||
262 | ----------------------------------------------------------------------------- |
|
262 | ----------------------------------------------------------------------------- | |
263 | -- DEBUG |
|
|||
264 | ----------------------------------------------------------------------------- |
|
|||
265 | -- |
|
|||
266 | SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
|||
267 | SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
|||
268 | SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
|||
269 | SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
|||
270 |
|
||||
271 | SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
272 | SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
273 | SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
274 | SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
275 | SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
276 | SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
277 | SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
278 | SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
279 |
|
||||
280 | ----------------------------------------------------------------------------- |
|
|||
281 | -- MS |
|
263 | -- MS | |
282 | ----------------------------------------------------------------------------- |
|
264 | ----------------------------------------------------------------------------- | |
283 |
|
265 | |||
@@ -291,7 +273,7 ARCHITECTURE beh OF lpp_lfr IS | |||||
291 | SIGNAL run_ms : STD_LOGIC; |
|
273 | SIGNAL run_ms : STD_LOGIC; | |
292 | SIGNAL ms_softandhard_rstn : STD_LOGIC; |
|
274 | SIGNAL ms_softandhard_rstn : STD_LOGIC; | |
293 |
|
275 | |||
294 |
SIGNAL matrix_time_f0 |
|
276 | SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
295 | -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
277 | -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
296 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
278 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
297 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
279 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
@@ -353,7 +335,7 BEGIN | |||||
353 |
|
335 | |||
354 | run_ms => run_ms, |
|
336 | run_ms => run_ms, | |
355 |
|
337 | |||
356 |
ready_matrix_f0 |
|
338 | ready_matrix_f0 => ready_matrix_f0, | |
357 | -- ready_matrix_f0_1 => ready_matrix_f0_1, |
|
339 | -- ready_matrix_f0_1 => ready_matrix_f0_1, | |
358 | ready_matrix_f1 => ready_matrix_f1, |
|
340 | ready_matrix_f1 => ready_matrix_f1, | |
359 | ready_matrix_f2 => ready_matrix_f2, |
|
341 | ready_matrix_f2 => ready_matrix_f2, | |
@@ -361,8 +343,8 BEGIN | |||||
361 | error_bad_component_error => error_bad_component_error, |
|
343 | error_bad_component_error => error_bad_component_error, | |
362 | error_buffer_full => error_buffer_full, -- TODO |
|
344 | error_buffer_full => error_buffer_full, -- TODO | |
363 | error_input_fifo_write => error_input_fifo_write, -- TODO |
|
345 | error_input_fifo_write => error_input_fifo_write, -- TODO | |
364 | debug_reg => debug_reg, |
|
346 | -- debug_reg => debug_reg, | |
365 |
status_ready_matrix_f0 |
|
347 | status_ready_matrix_f0 => status_ready_matrix_f0, | |
366 | -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
348 | -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
367 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
349 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
368 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
350 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
@@ -371,12 +353,12 BEGIN | |||||
371 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
353 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
372 | config_active_interruption_onError => config_active_interruption_onError, |
|
354 | config_active_interruption_onError => config_active_interruption_onError, | |
373 |
|
355 | |||
374 |
matrix_time_f0 |
|
356 | matrix_time_f0 => matrix_time_f0, | |
375 | -- matrix_time_f0_1 => matrix_time_f0_1, |
|
357 | -- matrix_time_f0_1 => matrix_time_f0_1, | |
376 | matrix_time_f1 => matrix_time_f1, |
|
358 | matrix_time_f1 => matrix_time_f1, | |
377 | matrix_time_f2 => matrix_time_f2, |
|
359 | matrix_time_f2 => matrix_time_f2, | |
378 |
|
360 | |||
379 |
addr_matrix_f0 |
|
361 | addr_matrix_f0 => addr_matrix_f0, | |
380 | -- addr_matrix_f0_1 => addr_matrix_f0_1, |
|
362 | -- addr_matrix_f0_1 => addr_matrix_f0_1, | |
381 | addr_matrix_f1 => addr_matrix_f1, |
|
363 | addr_matrix_f1 => addr_matrix_f1, | |
382 | addr_matrix_f2 => addr_matrix_f2, |
|
364 | addr_matrix_f2 => addr_matrix_f2, | |
@@ -410,27 +392,9 BEGIN | |||||
410 | addr_data_f1 => addr_data_f1, |
|
392 | addr_data_f1 => addr_data_f1, | |
411 | addr_data_f2 => addr_data_f2, |
|
393 | addr_data_f2 => addr_data_f2, | |
412 | addr_data_f3 => addr_data_f3, |
|
394 | addr_data_f3 => addr_data_f3, | |
413 |
start_date => start_date |
|
395 | start_date => start_date); | |
414 | --------------------------------------------------------------------------- |
|
|||
415 | debug_reg0 => debug_reg0, |
|
|||
416 | debug_reg1 => debug_reg1, |
|
|||
417 | debug_reg2 => debug_reg2, |
|
|||
418 | debug_reg3 => debug_reg3, |
|
|||
419 | debug_reg4 => debug_reg4, |
|
|||
420 | debug_reg5 => debug_reg5, |
|
|||
421 | debug_reg6 => debug_reg6, |
|
|||
422 | debug_reg7 => debug_reg7); |
|
|||
423 |
|
396 | |||
424 | debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0); |
|
|||
425 | debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); |
|
|||
426 | debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2); |
|
|||
427 | ----------------------------------------------------------------------------- |
|
397 | ----------------------------------------------------------------------------- | |
428 | --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug |
|
|||
429 | --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug |
|
|||
430 | --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug |
|
|||
431 | --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug |
|
|||
432 |
|
||||
433 |
|
||||
434 | ----------------------------------------------------------------------------- |
|
398 | ----------------------------------------------------------------------------- | |
435 | lpp_waveform_1 : lpp_waveform |
|
399 | lpp_waveform_1 : lpp_waveform | |
436 | GENERIC MAP ( |
|
400 | GENERIC MAP ( | |
@@ -476,19 +440,19 BEGIN | |||||
476 | --f0 |
|
440 | --f0 | |
477 | addr_data_f0 => addr_data_f0, |
|
441 | addr_data_f0 => addr_data_f0, | |
478 | data_f0_in_valid => sample_f0_val, |
|
442 | data_f0_in_valid => sample_f0_val, | |
479 |
data_f0_in => sample_f0_data, |
|
443 | data_f0_in => sample_f0_data, | |
480 |
|
|
444 | --f1 | |
481 | addr_data_f1 => addr_data_f1, |
|
445 | addr_data_f1 => addr_data_f1, | |
482 | data_f1_in_valid => sample_f1_val, |
|
446 | data_f1_in_valid => sample_f1_val, | |
483 |
data_f1_in => sample_f1_data, |
|
447 | data_f1_in => sample_f1_data, | |
484 |
|
|
448 | --f2 | |
485 | addr_data_f2 => addr_data_f2, |
|
449 | addr_data_f2 => addr_data_f2, | |
486 | data_f2_in_valid => sample_f2_val, |
|
450 | data_f2_in_valid => sample_f2_val, | |
487 |
data_f2_in => sample_f2_data, |
|
451 | data_f2_in => sample_f2_data, | |
488 |
|
|
452 | --f3 | |
489 | addr_data_f3 => addr_data_f3, |
|
453 | addr_data_f3 => addr_data_f3, | |
490 | data_f3_in_valid => sample_f3_val, |
|
454 | data_f3_in_valid => sample_f3_val, | |
491 |
data_f3_in => sample_f3_data, |
|
455 | data_f3_in => sample_f3_data, | |
492 |
|
|
456 | -- OUTPUT -- DMA interface | |
493 | --f0 |
|
457 | --f0 | |
494 | data_f0_addr_out => data_f0_addr_out_s, |
|
458 | data_f0_addr_out => data_f0_addr_out_s, | |
@@ -663,21 +627,6 BEGIN | |||||
663 | dma_data_2 <= dma_data; |
|
627 | dma_data_2 <= dma_data; | |
664 |
|
628 | |||
665 |
|
629 | |||
666 |
|
||||
667 |
|
||||
668 |
|
||||
669 | ----------------------------------------------------------------------------- |
|
|||
670 | -- DEBUG -- DMA IN |
|
|||
671 | --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; |
|
|||
672 | --debug_f0_data_dma_in <= dma_data; |
|
|||
673 | --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; |
|
|||
674 | --debug_f1_data_dma_in <= dma_data; |
|
|||
675 | --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren; |
|
|||
676 | --debug_f2_data_dma_in <= dma_data; |
|
|||
677 | --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren; |
|
|||
678 | --debug_f3_data_dma_in <= dma_data; |
|
|||
679 | ----------------------------------------------------------------------------- |
|
|||
680 |
|
||||
681 | ----------------------------------------------------------------------------- |
|
630 | ----------------------------------------------------------------------------- | |
682 | -- DMA |
|
631 | -- DMA | |
683 | ----------------------------------------------------------------------------- |
|
632 | ----------------------------------------------------------------------------- | |
@@ -732,8 +681,8 BEGIN | |||||
732 | sample_f0_wdata => sample_f0_wdata, |
|
681 | sample_f0_wdata => sample_f0_wdata, | |
733 | sample_f1_wen => sample_f1_wen, |
|
682 | sample_f1_wen => sample_f1_wen, | |
734 | sample_f1_wdata => sample_f1_wdata, |
|
683 | sample_f1_wdata => sample_f1_wdata, | |
735 |
sample_f2_wen => sample_f3_wen, -- TODO |
|
684 | sample_f2_wen => sample_f3_wen, -- TODO | |
736 |
sample_f2_wdata => sample_f3_wdata,-- TODO |
|
685 | sample_f2_wdata => sample_f3_wdata,-- TODO | |
737 |
|
686 | |||
738 | dma_addr => data_ms_addr, -- |
|
687 | dma_addr => data_ms_addr, -- | |
739 | dma_data => data_ms_data, -- |
|
688 | dma_data => data_ms_data, -- | |
@@ -742,29 +691,26 BEGIN | |||||
742 | dma_ren => data_ms_ren, -- |
|
691 | dma_ren => data_ms_ren, -- | |
743 | dma_done => data_ms_done, -- |
|
692 | dma_done => data_ms_done, -- | |
744 |
|
693 | |||
745 |
ready_matrix_f0 => ready_matrix_f0 |
|
694 | ready_matrix_f0 => ready_matrix_f0, | |
746 | ready_matrix_f1 => ready_matrix_f1, |
|
695 | ready_matrix_f1 => ready_matrix_f1, | |
747 | ready_matrix_f2 => ready_matrix_f2, |
|
696 | ready_matrix_f2 => ready_matrix_f2, | |
748 | --error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
|||
749 | error_bad_component_error => error_bad_component_error, |
|
697 | error_bad_component_error => error_bad_component_error, | |
750 |
error_buffer_full => error_buffer_full, |
|
698 | error_buffer_full => error_buffer_full, | |
751 |
|
|
699 | error_input_fifo_write => error_input_fifo_write, | |
752 |
|
|
700 | ||
753 | debug_reg => observation_reg, |
|
701 | debug_reg => observation_reg, | |
754 |
|
702 | |||
755 |
status_ready_matrix_f0 => status_ready_matrix_f0 |
|
703 | status_ready_matrix_f0 => status_ready_matrix_f0, | |
756 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
704 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
757 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
705 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
758 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,-- TODO |
|
|||
759 | -- status_error_bad_component_error => status_error_bad_component_error,-- TODO |
|
|||
760 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
706 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
761 | config_active_interruption_onError => config_active_interruption_onError, |
|
707 | config_active_interruption_onError => config_active_interruption_onError, | |
762 |
addr_matrix_f0 => addr_matrix_f0 |
|
708 | addr_matrix_f0 => addr_matrix_f0, | |
763 | addr_matrix_f1 => addr_matrix_f1, |
|
709 | addr_matrix_f1 => addr_matrix_f1, | |
764 | addr_matrix_f2 => addr_matrix_f2, |
|
710 | addr_matrix_f2 => addr_matrix_f2, | |
765 |
|
711 | |||
766 |
matrix_time_f0 => matrix_time_f0 |
|
712 | matrix_time_f0 => matrix_time_f0, | |
767 | matrix_time_f1 => matrix_time_f1, |
|
713 | matrix_time_f1 => matrix_time_f1, | |
768 | matrix_time_f2 => matrix_time_f2); |
|
714 | matrix_time_f2 => matrix_time_f2); | |
769 |
|
715 | |||
770 | END beh; No newline at end of file |
|
716 | END beh; |
@@ -28,6 +28,7 USE grlib.amba.ALL; | |||||
28 | USE grlib.stdlib.ALL; |
|
28 | USE grlib.stdlib.ALL; | |
29 | USE grlib.devices.ALL; |
|
29 | USE grlib.devices.ALL; | |
30 | LIBRARY lpp; |
|
30 | LIBRARY lpp; | |
|
31 | USE lpp.lpp_lfr_pkg.ALL; | |||
31 | USE lpp.lpp_amba.ALL; |
|
32 | USE lpp.lpp_amba.ALL; | |
32 | USE lpp.apb_devices_list.ALL; |
|
33 | USE lpp.apb_devices_list.ALL; | |
33 | USE lpp.lpp_memory.ALL; |
|
34 | USE lpp.lpp_memory.ALL; | |
@@ -61,31 +62,29 ENTITY lpp_lfr_apbreg IS | |||||
61 | -- Spectral Matrix Reg |
|
62 | -- Spectral Matrix Reg | |
62 |
run_ms |
|
63 | run_ms : OUT STD_LOGIC; | |
63 | -- IN |
|
64 | -- IN | |
64 |
ready_matrix_f0 |
|
65 | ready_matrix_f0 : IN STD_LOGIC; | |
65 |
ready_matrix_f1 |
|
66 | ready_matrix_f1 : IN STD_LOGIC; | |
66 |
ready_matrix_f2 |
|
67 | ready_matrix_f2 : IN STD_LOGIC; | |
67 |
|
68 | |||
68 |
error_bad_component_error |
|
69 | error_bad_component_error : IN STD_LOGIC; | |
69 |
error_buffer_full |
|
70 | error_buffer_full : IN STD_LOGIC; -- TODO | |
70 |
error_input_fifo_write |
|
71 | error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO | |
71 |
|
72 | |||
72 |
debug_reg |
|
73 | -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
73 |
|
74 | |||
74 | -- OUT |
|
75 | -- OUT | |
75 |
status_ready_matrix_f0 |
|
76 | status_ready_matrix_f0 : OUT STD_LOGIC; | |
76 |
status_ready_matrix_f1 |
|
77 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
77 |
status_ready_matrix_f2 |
|
78 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
78 |
|
79 | |||
79 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
80 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
80 | config_active_interruption_onError : OUT STD_LOGIC; |
|
81 | config_active_interruption_onError : OUT STD_LOGIC; | |
81 |
|
82 | |||
82 |
addr_matrix_f0 |
|
83 | addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
83 | -- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
84 |
addr_matrix_f1 |
|
84 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
85 |
addr_matrix_f2 |
|
85 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
86 |
|
86 | |||
87 |
matrix_time_f0 |
|
87 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
88 | -- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|||
89 |
matrix_time_f1 |
|
88 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
90 |
matrix_time_f2 |
|
89 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
91 |
|
90 | |||
@@ -128,17 +127,7 ENTITY lpp_lfr_apbreg IS | |||||
128 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
127 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
129 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
128 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
130 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
129 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
131 |
start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0) |
|
130 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0) | |
132 | --------------------------------------------------------------------------- |
|
|||
133 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
134 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
135 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
136 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
137 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
138 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
139 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
140 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
|||
141 |
|
||||
142 | --------------------------------------------------------------------------- |
|
131 | --------------------------------------------------------------------------- | |
143 | ); |
|
132 | ); | |
144 |
|
133 | |||
@@ -157,27 +146,28 ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||||
157 | config_active_interruption_onError : STD_LOGIC; |
|
146 | config_active_interruption_onError : STD_LOGIC; | |
158 | config_ms_run : STD_LOGIC; |
|
147 | config_ms_run : STD_LOGIC; | |
159 | status_ready_matrix_f0_0 : STD_LOGIC; |
|
148 | status_ready_matrix_f0_0 : STD_LOGIC; | |
160 |
|
|
149 | status_ready_matrix_f1_0 : STD_LOGIC; | |
161 |
status_ready_matrix_f |
|
150 | status_ready_matrix_f2_0 : STD_LOGIC; | |
162 |
status_ready_matrix_f |
|
151 | status_ready_matrix_f0_1 : STD_LOGIC; | |
163 | -- status_error_anticipating_empty_fifo : STD_LOGIC; |
|
152 | status_ready_matrix_f1_1 : STD_LOGIC; | |
|
153 | status_ready_matrix_f2_1 : STD_LOGIC; | |||
164 | status_error_bad_component_error : STD_LOGIC; |
|
154 | status_error_bad_component_error : STD_LOGIC; | |
165 |
status_error_buffer_full : STD_LOGIC; |
|
155 | status_error_buffer_full : STD_LOGIC; | |
166 |
status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
156 | status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); | |
|
157 | ||||
167 |
|
|
158 | addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
168 |
|
|
159 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
169 |
addr_matrix_f1 |
|
160 | addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
170 |
addr_matrix_f |
|
161 | addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
162 | addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
163 | addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
171 |
|
164 | |||
172 |
|
|
165 | time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
173 |
|
|
166 | time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
174 |
|
|
167 | time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
175 |
|
|
168 | time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
176 |
|
169 | time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | ||
177 |
|
|
170 | time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
178 | -- fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
|||
179 | -- fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
|||
180 | -- fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
|||
181 | END RECORD; |
|
171 | END RECORD; | |
182 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; |
|
172 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; | |
183 |
|
173 | |||
@@ -226,21 +216,46 ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||||
226 | SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
216 | SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
227 | SIGNAL ored_irq_wfp : STD_LOGIC; |
|
217 | SIGNAL ored_irq_wfp : STD_LOGIC; | |
228 |
|
218 | |||
|
219 | ----------------------------------------------------------------------------- | |||
|
220 | -- | |||
|
221 | ----------------------------------------------------------------------------- | |||
|
222 | SIGNAL reg0_ready_matrix_f0 : STD_LOGIC; | |||
|
223 | SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
224 | SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
225 | ||||
|
226 | SIGNAL reg1_ready_matrix_f0 : STD_LOGIC; | |||
|
227 | SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
228 | SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
229 | ||||
|
230 | SIGNAL reg0_ready_matrix_f1 : STD_LOGIC; | |||
|
231 | SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
232 | SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
233 | ||||
|
234 | SIGNAL reg1_ready_matrix_f1 : STD_LOGIC; | |||
|
235 | SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
236 | SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
237 | ||||
|
238 | SIGNAL reg0_ready_matrix_f2 : STD_LOGIC; | |||
|
239 | SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
240 | SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
241 | ||||
|
242 | SIGNAL reg1_ready_matrix_f2 : STD_LOGIC; | |||
|
243 | SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
244 | SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
245 | ||||
229 | BEGIN -- beh |
|
246 | BEGIN -- beh | |
230 |
|
247 | |||
231 |
status_ready_matrix_f0 |
|
248 | -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0; | |
232 |
-- status_ready_matrix_f |
|
249 | -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; | |
233 |
status_ready_matrix_f |
|
250 | -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; | |
234 | status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; |
|
|||
235 | -- status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; |
|
|||
236 | -- status_error_bad_component_error <= reg_sp.status_error_bad_component_error; |
|
|||
237 |
|
251 | |||
238 | config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; |
|
252 | config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; | |
239 | config_active_interruption_onError <= reg_sp.config_active_interruption_onError; |
|
253 | config_active_interruption_onError <= reg_sp.config_active_interruption_onError; | |
240 | addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; |
|
254 | ||
241 | -- addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; |
|
255 | ||
242 |
addr_matrix_f |
|
256 | -- addr_matrix_f0 <= reg_sp.addr_matrix_f0; | |
243 |
addr_matrix_f |
|
257 | -- addr_matrix_f1 <= reg_sp.addr_matrix_f1; | |
|
258 | -- addr_matrix_f2 <= reg_sp.addr_matrix_f2; | |||
244 |
|
259 | |||
245 |
|
260 | |||
246 | data_shaping_BW <= NOT reg_wp.data_shaping_BW; |
|
261 | data_shaping_BW <= NOT reg_wp.data_shaping_BW; | |
@@ -284,27 +299,30 BEGIN -- beh | |||||
284 | reg_sp.config_active_interruption_onError <= '0'; |
|
299 | reg_sp.config_active_interruption_onError <= '0'; | |
285 | reg_sp.config_ms_run <= '1'; |
|
300 | reg_sp.config_ms_run <= '1'; | |
286 | reg_sp.status_ready_matrix_f0_0 <= '0'; |
|
301 | reg_sp.status_ready_matrix_f0_0 <= '0'; | |
287 |
|
|
302 | reg_sp.status_ready_matrix_f1_0 <= '0'; | |
288 |
reg_sp.status_ready_matrix_f |
|
303 | reg_sp.status_ready_matrix_f2_0 <= '0'; | |
289 |
reg_sp.status_ready_matrix_f |
|
304 | reg_sp.status_ready_matrix_f0_1 <= '0'; | |
290 |
|
|
305 | reg_sp.status_ready_matrix_f1_1 <= '0'; | |
|
306 | reg_sp.status_ready_matrix_f2_1 <= '0'; | |||
291 | reg_sp.status_error_bad_component_error <= '0'; |
|
307 | reg_sp.status_error_bad_component_error <= '0'; | |
292 | reg_sp.status_error_buffer_full <= '0'; |
|
308 | reg_sp.status_error_buffer_full <= '0'; | |
293 | reg_sp.status_error_input_fifo_write <= (OTHERS => '0'); |
|
309 | reg_sp.status_error_input_fifo_write <= (OTHERS => '0'); | |
294 |
|
310 | |||
295 |
reg_sp.addr_matrix_f0_0 |
|
311 | reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); | |
296 |
|
|
312 | reg_sp.addr_matrix_f1_0 <= (OTHERS => '0'); | |
297 |
reg_sp.addr_matrix_f |
|
313 | reg_sp.addr_matrix_f2_0 <= (OTHERS => '0'); | |
298 | reg_sp.addr_matrix_f2 <= (OTHERS => '0'); |
|
314 | ||
|
315 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); | |||
|
316 | reg_sp.addr_matrix_f1_1 <= (OTHERS => '0'); | |||
|
317 | reg_sp.addr_matrix_f2_1 <= (OTHERS => '0'); | |||
299 |
|
318 | |||
300 |
reg_sp. |
|
319 | reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok | |
301 |
|
|
320 | reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok | |
302 |
reg_sp. |
|
321 | reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok | |
303 | reg_sp.coarse_time_f2 <= (OTHERS => '0'); |
|
322 | ||
304 |
|
|
323 | reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok | |
305 |
|
|
324 | reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok | |
306 |
|
|
325 | reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok | |
307 | --reg_sp.fine_time_f2 <= (OTHERS => '0'); |
|
|||
308 |
|
326 | |||
309 |
prdata |
|
327 | prdata <= (OTHERS => '0'); | |
310 |
|
328 | |||
@@ -343,24 +361,24 BEGIN -- beh | |||||
343 |
|
361 | |||
344 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
362 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
345 |
|
363 | |||
346 | reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0); |
|
364 | reg_sp.time_matrix_f0_0 <= reg0_matrix_time_f0; -- ok | |
347 | -- reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0); |
|
365 | reg_sp.time_matrix_f1_0 <= reg0_matrix_time_f1; -- ok | |
348 | reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0); |
|
366 | reg_sp.time_matrix_f2_0 <= reg0_matrix_time_f2; -- ok | |
349 | reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0); |
|
|||
350 |
|
367 | |||
351 | --reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0); |
|
368 | reg_sp.time_matrix_f0_1 <= reg1_matrix_time_f0; -- ok | |
352 | --reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0); |
|
369 | reg_sp.time_matrix_f1_1 <= reg1_matrix_time_f1; -- ok | |
353 | --reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0); |
|
370 | reg_sp.time_matrix_f2_1 <= reg1_matrix_time_f2; -- ok | |
354 | --reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0); |
|
|||
355 |
|
371 | |||
356 | status_full_ack <= (OTHERS => '0'); |
|
372 | status_full_ack <= (OTHERS => '0'); | |
357 |
|
373 | |||
358 |
reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0 |
|
374 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0; | |
359 |
|
|
375 | reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1; | |
360 |
reg_sp.status_ready_matrix_f |
|
376 | reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2; | |
361 | reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; |
|
|||
362 |
|
377 | |||
363 | -- reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; |
|
378 | reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0; | |
|
379 | reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1; | |||
|
380 | reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2; | |||
|
381 | ||||
364 |
reg_sp.status_error_bad_component_error |
|
382 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; | |
365 |
|
383 | |||
366 | reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full; |
|
384 | reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full; | |
@@ -371,9 +389,6 BEGIN -- beh | |||||
371 |
|
389 | |||
372 |
|
390 | |||
373 | all_status: FOR I IN 3 DOWNTO 0 LOOP |
|
391 | all_status : FOR I IN 3 DOWNTO 0 LOOP | |
374 | --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; |
|
|||
375 | --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; |
|
|||
376 | --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; |
|
|||
377 | reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; |
|
392 | reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; | |
378 |
reg_wp.status_full_err(I) <= status_full_err(I) |
|
393 | reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run; | |
379 |
reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run |
|
394 | reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run; | |
@@ -385,42 +400,67 BEGIN -- beh | |||||
385 | IF apbi.psel(pindex) = '1' THEN |
|
400 | IF apbi.psel(pindex) = '1' THEN | |
386 | -- APB DMA READ -- |
|
401 | -- APB DMA READ -- | |
387 | CASE paddr(7 DOWNTO 2) IS |
|
402 | CASE paddr(7 DOWNTO 2) IS | |
388 | -- |
|
403 | --0 | |
389 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; |
|
404 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; | |
390 | prdata(1) <= reg_sp.config_active_interruption_onError; |
|
405 | prdata(1) <= reg_sp.config_active_interruption_onError; | |
391 | prdata(2) <= reg_sp.config_ms_run; |
|
406 | prdata(2) <= reg_sp.config_ms_run; | |
|
407 | --1 | |||
392 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; |
|
408 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; | |
393 |
|
|
409 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; | |
394 | prdata(2) <= reg_sp.status_ready_matrix_f1; |
|
410 | prdata(2) <= reg_sp.status_ready_matrix_f1_0; | |
395 |
prdata(3) <= reg_sp.status_ready_matrix_f |
|
411 | prdata(3) <= reg_sp.status_ready_matrix_f1_1; | |
396 |
|
|
412 | prdata(4) <= reg_sp.status_ready_matrix_f2_0; | |
397 |
prdata(5) <= reg_sp.status_ |
|
413 | prdata(5) <= reg_sp.status_ready_matrix_f2_1; | |
398 |
prdata(6) <= reg_sp.status_error_b |
|
414 | prdata(6) <= reg_sp.status_error_bad_component_error; | |
399 |
prdata(7) <= reg_sp.status_error_ |
|
415 | prdata(7) <= reg_sp.status_error_buffer_full; | |
400 |
prdata(8) <= reg_sp.status_error_input_fifo_write( |
|
416 | prdata(8) <= reg_sp.status_error_input_fifo_write(0); | |
401 |
prdata(9) <= reg_sp.status_error_input_fifo_write( |
|
417 | prdata(9) <= reg_sp.status_error_input_fifo_write(1); | |
|
418 | prdata(10) <= reg_sp.status_error_input_fifo_write(2); | |||
|
419 | --2 | |||
402 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; |
|
420 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; | |
403 | -- WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; |
|
421 | --3 | |
404 |
WHEN "000 |
|
422 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; | |
405 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; |
|
423 | --4 | |
406 |
|
424 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0; | ||
407 | WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0; |
|
425 | --5 | |
408 |
|
|
426 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1; | |
409 | WHEN "001000" => prdata <= reg_sp.coarse_time_f1; |
|
427 | --6 | |
410 |
WHEN "0010 |
|
428 | WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0; | |
411 | WHEN "001010" => prdata(15 downto 0) <= matrix_time_f0_0(15 DOWNTO 0);--reg_sp.fine_time_f0_0; |
|
429 | --7 | |
412 | -- WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1; |
|
430 | WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1; | |
413 | WHEN "001100" => prdata(15 downto 0) <= matrix_time_f1 (15 DOWNTO 0);--reg_sp.fine_time_f1; |
|
431 | --8 | |
414 | WHEN "001101" => prdata(15 downto 0) <= matrix_time_f2 (15 DOWNTO 0);--reg_sp.fine_time_f2; |
|
432 | WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16); | |
415 |
|
433 | --9 | ||
416 | WHEN "001111" => prdata <= debug_reg; |
|
434 | WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0); | |
|
435 | --10 | |||
|
436 | WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16); | |||
|
437 | --11 | |||
|
438 | WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0); | |||
|
439 | --12 | |||
|
440 | WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16); | |||
|
441 | --13 | |||
|
442 | WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0); | |||
|
443 | --14 | |||
|
444 | WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16); | |||
|
445 | --15 | |||
|
446 | WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0); | |||
|
447 | --16 | |||
|
448 | WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16); | |||
|
449 | --17 | |||
|
450 | WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0); | |||
|
451 | --18 | |||
|
452 | WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16); | |||
|
453 | --19 | |||
|
454 | WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0); | |||
417 | --------------------------------------------------------------------- |
|
455 | --------------------------------------------------------------------- | |
418 | WHEN "010000" => prdata(0) <= reg_wp.data_shaping_BW; |
|
456 | --20 | |
|
457 | WHEN "010100" => prdata(0) <= reg_wp.data_shaping_BW; | |||
419 | prdata(1) <= reg_wp.data_shaping_SP0; |
|
458 | prdata(1) <= reg_wp.data_shaping_SP0; | |
420 | prdata(2) <= reg_wp.data_shaping_SP1; |
|
459 | prdata(2) <= reg_wp.data_shaping_SP1; | |
421 | prdata(3) <= reg_wp.data_shaping_R0; |
|
460 | prdata(3) <= reg_wp.data_shaping_R0; | |
422 | prdata(4) <= reg_wp.data_shaping_R1; |
|
461 | prdata(4) <= reg_wp.data_shaping_R1; | |
423 | WHEN "010001" => prdata(0) <= reg_wp.enable_f0; |
|
462 | --21 | |
|
463 | WHEN "010101" => prdata(0) <= reg_wp.enable_f0; | |||
424 | prdata(1) <= reg_wp.enable_f1; |
|
464 | prdata(1) <= reg_wp.enable_f1; | |
425 | prdata(2) <= reg_wp.enable_f2; |
|
465 | prdata(2) <= reg_wp.enable_f2; | |
426 | prdata(3) <= reg_wp.enable_f3; |
|
466 | prdata(3) <= reg_wp.enable_f3; | |
@@ -428,31 +468,36 BEGIN -- beh | |||||
428 | prdata(5) <= reg_wp.burst_f1; |
|
468 | prdata(5) <= reg_wp.burst_f1; | |
429 | prdata(6) <= reg_wp.burst_f2; |
|
469 | prdata(6) <= reg_wp.burst_f2; | |
430 | prdata(7) <= reg_wp.run; |
|
470 | prdata(7) <= reg_wp.run; | |
431 | WHEN "010010" => prdata <= reg_wp.addr_data_f0; |
|
471 | --22 | |
432 |
WHEN "010 |
|
472 | WHEN "010110" => prdata <= reg_wp.addr_data_f0; | |
433 | WHEN "010100" => prdata <= reg_wp.addr_data_f2; |
|
473 | --23 | |
434 |
WHEN "0101 |
|
474 | WHEN "010111" => prdata <= reg_wp.addr_data_f1; | |
435 | WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; |
|
475 | --24 | |
|
476 | WHEN "011000" => prdata <= reg_wp.addr_data_f2; | |||
|
477 | --25 | |||
|
478 | WHEN "011001" => prdata <= reg_wp.addr_data_f3; | |||
|
479 | --26 | |||
|
480 | WHEN "011010" => prdata(3 DOWNTO 0) <= reg_wp.status_full; | |||
436 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; |
|
481 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; | |
437 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; |
|
482 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; | |
438 | WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; |
|
483 | --27 | |
439 |
WHEN "0110 |
|
484 | WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; | |
440 | WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; |
|
485 | --28 | |
441 |
WHEN "011 |
|
486 | WHEN "011100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; | |
442 | WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; |
|
487 | --29 | |
443 |
WHEN "01110 |
|
488 | WHEN "011101" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; | |
444 | WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; |
|
489 | --30 | |
445 |
WHEN "011110" => prdata( |
|
490 | WHEN "011110" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; | |
446 | WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; |
|
491 | --31 | |
447 | ---------------------------------------------------- |
|
492 | WHEN "011111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; | |
448 | WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0); |
|
493 | --32 | |
449 |
WHEN "10000 |
|
494 | WHEN "100000" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; | |
450 | WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0); |
|
495 | --33 | |
451 |
WHEN "1000 |
|
496 | WHEN "100001" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; | |
452 | WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0); |
|
497 | --34 | |
453 |
WHEN "100 |
|
498 | WHEN "100010" => prdata(30 DOWNTO 0) <= reg_wp.start_date; | |
454 | WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0); |
|
499 | --35 | |
455 |
WHEN "100 |
|
500 | WHEN "100011" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; | |
456 | ---------------------------------------------------- |
|
501 | ---------------------------------------------------- | |
457 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); |
|
502 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); | |
458 | WHEN OTHERS => NULL; |
|
503 | WHEN OTHERS => NULL; | |
@@ -466,26 +511,31 BEGIN -- beh | |||||
466 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); |
|
511 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); | |
467 | reg_sp.config_ms_run <= apbi.pwdata(2); |
|
512 | reg_sp.config_ms_run <= apbi.pwdata(2); | |
468 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); |
|
513 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); | |
469 |
|
|
514 | reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); | |
470 | reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); |
|
515 | reg_sp.status_ready_matrix_f1_0 <= apbi.pwdata(2); | |
471 |
reg_sp.status_ready_matrix_f |
|
516 | reg_sp.status_ready_matrix_f1_1 <= apbi.pwdata(3); | |
472 |
|
|
517 | reg_sp.status_ready_matrix_f2_0 <= apbi.pwdata(4); | |
473 |
reg_sp.status_ |
|
518 | reg_sp.status_ready_matrix_f2_1 <= apbi.pwdata(5); | |
474 |
reg_sp.status_error_b |
|
519 | reg_sp.status_error_bad_component_error <= apbi.pwdata(6); | |
475 |
reg_sp.status_error_ |
|
520 | reg_sp.status_error_buffer_full <= apbi.pwdata(7); | |
476 |
reg_sp.status_error_input_fifo_write( |
|
521 | reg_sp.status_error_input_fifo_write(0) <= apbi.pwdata(8); | |
477 |
reg_sp.status_error_input_fifo_write( |
|
522 | reg_sp.status_error_input_fifo_write(1) <= apbi.pwdata(9); | |
|
523 | reg_sp.status_error_input_fifo_write(2) <= apbi.pwdata(10); | |||
|
524 | --2 | |||
478 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; |
|
525 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; | |
479 |
|
|
526 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |
480 |
WHEN "000100" => reg_sp.addr_matrix_f1 |
|
527 | WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata; | |
481 |
WHEN "000101" => reg_sp.addr_matrix_f |
|
528 | WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata; | |
482 | -- |
|
529 | WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata; | |
483 |
WHEN "0 |
|
530 | WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata; | |
|
531 | --8 to 19 | |||
|
532 | --20 | |||
|
533 | WHEN "010100" => reg_wp.data_shaping_BW <= apbi.pwdata(0); | |||
484 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); |
|
534 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); | |
485 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); |
|
535 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); | |
486 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); |
|
536 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); | |
487 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); |
|
537 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); | |
488 |
WHEN "010 |
|
538 | WHEN "010101" => reg_wp.enable_f0 <= apbi.pwdata(0); | |
489 | reg_wp.enable_f1 <= apbi.pwdata(1); |
|
539 | reg_wp.enable_f1 <= apbi.pwdata(1); | |
490 | reg_wp.enable_f2 <= apbi.pwdata(2); |
|
540 | reg_wp.enable_f2 <= apbi.pwdata(2); | |
491 | reg_wp.enable_f3 <= apbi.pwdata(3); |
|
541 | reg_wp.enable_f3 <= apbi.pwdata(3); | |
@@ -493,40 +543,40 BEGIN -- beh | |||||
493 | reg_wp.burst_f1 <= apbi.pwdata(5); |
|
543 | reg_wp.burst_f1 <= apbi.pwdata(5); | |
494 | reg_wp.burst_f2 <= apbi.pwdata(6); |
|
544 | reg_wp.burst_f2 <= apbi.pwdata(6); | |
495 | reg_wp.run <= apbi.pwdata(7); |
|
545 | reg_wp.run <= apbi.pwdata(7); | |
496 | WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata; |
|
546 | --22 | |
497 |
WHEN "010 |
|
547 | WHEN "010110" => reg_wp.addr_data_f0 <= apbi.pwdata; | |
498 |
WHEN "0101 |
|
548 | WHEN "010111" => reg_wp.addr_data_f1 <= apbi.pwdata; | |
499 |
WHEN "01 |
|
549 | WHEN "011000" => reg_wp.addr_data_f2 <= apbi.pwdata; | |
500 |
WHEN "0101 |
|
550 | WHEN "011001" => reg_wp.addr_data_f3 <= apbi.pwdata; | |
|
551 | --26 | |||
|
552 | WHEN "011010" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); | |||
501 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); |
|
553 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); | |
502 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); |
|
554 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); | |
503 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); |
|
555 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); | |
504 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); |
|
556 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); | |
505 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); |
|
557 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); | |
506 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); |
|
558 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); | |
507 |
WHEN "01 |
|
559 | WHEN "011011" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
508 |
WHEN "011 |
|
560 | WHEN "011100" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
509 |
WHEN "011 |
|
561 | WHEN "011101" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); | |
510 |
WHEN "011 |
|
562 | WHEN "011110" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
511 |
WHEN "011 |
|
563 | WHEN "011111" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
512 |
WHEN " |
|
564 | WHEN "100000" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); | |
513 |
WHEN " |
|
565 | WHEN "100001" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); | |
514 |
WHEN " |
|
566 | WHEN "100010" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); | |
515 |
WHEN " |
|
567 | WHEN "100011" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); | |
516 | -- |
|
568 | -- | |
517 | WHEN OTHERS => NULL; |
|
569 | WHEN OTHERS => NULL; | |
518 | END CASE; |
|
570 | END CASE; | |
519 | END IF; |
|
571 | END IF; | |
520 | END IF; |
|
572 | END IF; | |
521 |
|
573 | |||
522 |
apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 |
|
574 | apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR | |
523 | -- ready_matrix_f0_1 OR |
|
|||
524 | ready_matrix_f1 OR |
|
575 | ready_matrix_f1 OR | |
525 | ready_matrix_f2) |
|
576 | ready_matrix_f2) | |
526 | ) |
|
577 | ) | |
527 | OR |
|
578 | OR | |
528 | (reg_sp.config_active_interruption_onError AND ( |
|
579 | (reg_sp.config_active_interruption_onError AND ( | |
529 | --error_anticipating_empty_fifo OR |
|
|||
530 |
|
|
580 | error_bad_component_error | |
531 |
|
|
581 | OR error_buffer_full | |
532 |
|
|
582 | OR error_input_fifo_write(0) | |
@@ -552,7 +602,7 BEGIN -- beh | |||||
552 | BEGIN -- PROCESS |
|
602 | BEGIN -- PROCESS | |
553 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
603 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
554 |
irq_wfp_reg |
|
604 | irq_wfp_reg <= (OTHERS => '0'); | |
555 |
ELSIF HCLK' |
|
605 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
556 |
irq_wfp_reg <= irq_wfp_reg_s; |
|
606 | irq_wfp_reg <= irq_wfp_reg_s; | |
557 | END IF; |
|
607 | END IF; | |
558 | END PROCESS; |
|
608 | END PROCESS; | |
@@ -566,4 +616,68 BEGIN -- beh | |||||
566 |
|
616 | |||
567 | run_ms <= reg_sp.config_ms_run; |
|
617 | run_ms <= reg_sp.config_ms_run; | |
568 |
|
618 | |||
569 | END beh; |
|
619 | ----------------------------------------------------------------------------- | |
|
620 | -- | |||
|
621 | ----------------------------------------------------------------------------- | |||
|
622 | lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer | |||
|
623 | PORT MAP ( | |||
|
624 | clk => HCLK, | |||
|
625 | rstn => HRESETn, | |||
|
626 | ||||
|
627 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0, | |||
|
628 | reg0_ready_matrix => reg0_ready_matrix_f0, | |||
|
629 | reg0_addr_matrix => reg0_addr_matrix_f0, | |||
|
630 | reg0_matrix_time => reg0_matrix_time_f0, | |||
|
631 | ||||
|
632 | reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1, | |||
|
633 | reg1_ready_matrix => reg1_ready_matrix_f0, | |||
|
634 | reg1_addr_matrix => reg1_addr_matrix_f0, | |||
|
635 | reg1_matrix_time => reg1_matrix_time_f0, | |||
|
636 | ||||
|
637 | ready_matrix => ready_matrix_f0, | |||
|
638 | status_ready_matrix => status_ready_matrix_f0, | |||
|
639 | addr_matrix => addr_matrix_f0, | |||
|
640 | matrix_time => matrix_time_f0); | |||
|
641 | ||||
|
642 | lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer | |||
|
643 | PORT MAP ( | |||
|
644 | clk => HCLK, | |||
|
645 | rstn => HRESETn, | |||
|
646 | ||||
|
647 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0, | |||
|
648 | reg0_ready_matrix => reg0_ready_matrix_f1, | |||
|
649 | reg0_addr_matrix => reg0_addr_matrix_f1, | |||
|
650 | reg0_matrix_time => reg0_matrix_time_f1, | |||
|
651 | ||||
|
652 | reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1, | |||
|
653 | reg1_ready_matrix => reg1_ready_matrix_f1, | |||
|
654 | reg1_addr_matrix => reg1_addr_matrix_f1, | |||
|
655 | reg1_matrix_time => reg1_matrix_time_f1, | |||
|
656 | ||||
|
657 | ready_matrix => ready_matrix_f1, | |||
|
658 | status_ready_matrix => status_ready_matrix_f1, | |||
|
659 | addr_matrix => addr_matrix_f1, | |||
|
660 | matrix_time => matrix_time_f1); | |||
|
661 | ||||
|
662 | lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer | |||
|
663 | PORT MAP ( | |||
|
664 | clk => HCLK, | |||
|
665 | rstn => HRESETn, | |||
|
666 | ||||
|
667 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0, | |||
|
668 | reg0_ready_matrix => reg0_ready_matrix_f2, | |||
|
669 | reg0_addr_matrix => reg0_addr_matrix_f2, | |||
|
670 | reg0_matrix_time => reg0_matrix_time_f2, | |||
|
671 | ||||
|
672 | reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1, | |||
|
673 | reg1_ready_matrix => reg1_ready_matrix_f2, | |||
|
674 | reg1_addr_matrix => reg1_addr_matrix_f2, | |||
|
675 | reg1_matrix_time => reg1_matrix_time_f2, | |||
|
676 | ||||
|
677 | ready_matrix => ready_matrix_f2, | |||
|
678 | status_ready_matrix => status_ready_matrix_f2, | |||
|
679 | addr_matrix => addr_matrix_f2, | |||
|
680 | matrix_time => matrix_time_f2); | |||
|
681 | ||||
|
682 | ||||
|
683 | END beh; No newline at end of file |
@@ -296,23 +296,23 PACKAGE lpp_lfr_pkg IS | |||||
296 | apbi : IN apb_slv_in_type; |
|
296 | apbi : IN apb_slv_in_type; | |
297 | apbo : OUT apb_slv_out_type; |
|
297 | apbo : OUT apb_slv_out_type; | |
298 | run_ms : OUT STD_LOGIC; |
|
298 | run_ms : OUT STD_LOGIC; | |
299 |
ready_matrix_f0 |
|
299 | ready_matrix_f0 : IN STD_LOGIC; | |
300 | ready_matrix_f1 : IN STD_LOGIC; |
|
300 | ready_matrix_f1 : IN STD_LOGIC; | |
301 | ready_matrix_f2 : IN STD_LOGIC; |
|
301 | ready_matrix_f2 : IN STD_LOGIC; | |
302 | error_bad_component_error : IN STD_LOGIC; |
|
302 | error_bad_component_error : IN STD_LOGIC; | |
303 | error_buffer_full : in STD_LOGIC; |
|
303 | error_buffer_full : in STD_LOGIC; | |
304 | error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
304 | error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0); | |
305 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
305 | --x debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
306 |
status_ready_matrix_f0 |
|
306 | status_ready_matrix_f0 : OUT STD_LOGIC; | |
307 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
307 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
308 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
308 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
309 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
309 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
310 | config_active_interruption_onError : OUT STD_LOGIC; |
|
310 | config_active_interruption_onError : OUT STD_LOGIC; | |
311 |
addr_matrix_f0 |
|
311 | addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
312 | -- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
312 | -- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
313 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
313 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
314 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
314 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
315 |
matrix_time_f0 |
|
315 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
316 | -- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
316 | -- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
317 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
317 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
318 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
318 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
@@ -345,15 +345,8 PACKAGE lpp_lfr_pkg IS | |||||
345 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
345 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
346 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
346 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
347 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
347 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
348 |
start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0) |
|
348 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0) | |
349 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
349 | ); | |
350 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
351 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
352 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
353 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
354 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
355 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
356 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
|||
357 | END COMPONENT; |
|
350 | END COMPONENT; | |
358 |
|
351 | |||
359 |
|
352 | |||
@@ -392,4 +385,22 PACKAGE lpp_lfr_pkg IS | |||||
392 | ); |
|
385 | ); | |
393 | END COMPONENT; |
|
386 | END COMPONENT; | |
394 |
|
387 | |||
|
388 | COMPONENT lpp_apbreg_ms_pointer | |||
|
389 | PORT ( | |||
|
390 | clk : IN STD_LOGIC; | |||
|
391 | rstn : IN STD_LOGIC; | |||
|
392 | reg0_status_ready_matrix : IN STD_LOGIC; | |||
|
393 | reg0_ready_matrix : OUT STD_LOGIC; | |||
|
394 | reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
395 | reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
396 | reg1_status_ready_matrix : IN STD_LOGIC; | |||
|
397 | reg1_ready_matrix : OUT STD_LOGIC; | |||
|
398 | reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
399 | reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
400 | ready_matrix : IN STD_LOGIC; | |||
|
401 | status_ready_matrix : OUT STD_LOGIC; | |||
|
402 | addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
403 | matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0)); | |||
|
404 | END COMPONENT; | |||
|
405 | ||||
395 | END lpp_lfr_pkg; |
|
406 | END lpp_lfr_pkg; |
@@ -2,6 +2,7 lpp_top_lfr_pkg.vhd | |||||
2 | lpp_lfr_pkg.vhd |
|
2 | lpp_lfr_pkg.vhd | |
3 | lpp_lfr_filter.vhd |
|
3 | lpp_lfr_filter.vhd | |
4 | lpp_lfr_apbreg.vhd |
|
4 | lpp_lfr_apbreg.vhd | |
|
5 | lpp_lfr_apbreg_ms_pointer.vhd | |||
5 | lpp_lfr_ms_fsmdma.vhd |
|
6 | lpp_lfr_ms_fsmdma.vhd | |
6 | lpp_lfr_ms_FFT.vhd |
|
7 | lpp_lfr_ms_FFT.vhd | |
7 | lpp_lfr_ms.vhd |
|
8 | lpp_lfr_ms.vhd |
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