HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r370:ed5215f1c298

update reg APB_LFR :...

pellion -

r370:ed5215f1c298 JC

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r370:ed5215f1c298

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designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +1 -1

                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"00010D")  -- aa.bb.cc version
+                  top_lfr_version        => X"00010E")  -- aa.bb.cc version
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => reset,

lib/lpp/lpp_top_lfr/lpp_lfr.vhd +24 -78

               SIGNAL sample_f3_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               -- SM
-              SIGNAL ready_matrix_f0_0                      : STD_LOGIC;
+              SIGNAL ready_matrix_f0                      : STD_LOGIC;
               SIGNAL ready_matrix_f0_1                      : STD_LOGIC;
               SIGNAL ready_matrix_f1                        : STD_LOGIC;
               SIGNAL ready_matrix_f2                        : STD_LOGIC;
             --  SIGNAL error_anticipating_empty_fifo          : STD_LOGIC;
               SIGNAL error_bad_component_error              : STD_LOGIC;
-              SIGNAL debug_reg                              : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL debug_reg                              : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL status_ready_matrix_f0_0               : STD_LOGIC;
+              SIGNAL status_ready_matrix_f0               : STD_LOGIC;
               SIGNAL status_ready_matrix_f0_1               : STD_LOGIC;
               SIGNAL status_ready_matrix_f1                 : STD_LOGIC;
               SIGNAL status_ready_matrix_f2                 : STD_LOGIC;
             --  SIGNAL status_error_bad_component_error       : STD_LOGIC;
               SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
               SIGNAL config_active_interruption_onError     : STD_LOGIC;
-              SIGNAL addr_matrix_f0_0                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
+              SIGNAL addr_matrix_f0                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL addr_matrix_f0_1                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f1                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f2                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL dma_data_2      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
-              -- DEBUG
-              -----------------------------------------------------------------------------
-              --
-              SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
-              SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
-              SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
-              SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
-              SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              -----------------------------------------------------------------------------
               -- MS
               -----------------------------------------------------------------------------
               SIGNAL run_ms              : STD_LOGIC;
               SIGNAL ms_softandhard_rstn : STD_LOGIC;
-              SIGNAL matrix_time_f0_0    : STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL matrix_time_f0    : STD_LOGIC_VECTOR(47 DOWNTO 0);
             --  SIGNAL matrix_time_f0_1    : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL matrix_time_f1      : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL matrix_time_f2      : STD_LOGIC_VECTOR(47 DOWNTO 0);
                   run_ms => run_ms,
-                  ready_matrix_f0_0                      => ready_matrix_f0_0,
+                  ready_matrix_f0                      => ready_matrix_f0,
             --      ready_matrix_f0_1                      => ready_matrix_f0_1,
                   ready_matrix_f1                        => ready_matrix_f1,
                   ready_matrix_f2                        => ready_matrix_f2,
                   error_bad_component_error              => error_bad_component_error,
                   error_buffer_full                      => error_buffer_full,      -- TODO
                   error_input_fifo_write                 => error_input_fifo_write, -- TODO
-                  debug_reg                              => debug_reg,
+            --      debug_reg                              => debug_reg,
-                  status_ready_matrix_f0_0               => status_ready_matrix_f0_0,
+                  status_ready_matrix_f0               => status_ready_matrix_f0,
             --      status_ready_matrix_f0_1               => status_ready_matrix_f0_1,
                   status_ready_matrix_f1                 => status_ready_matrix_f1,
                   status_ready_matrix_f2                 => status_ready_matrix_f2,
                   config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
                   config_active_interruption_onError     => config_active_interruption_onError,
-                  matrix_time_f0_0 => matrix_time_f0_0,
+                  matrix_time_f0 => matrix_time_f0,
             --      matrix_time_f0_1 => matrix_time_f0_1,
                   matrix_time_f1   => matrix_time_f1,
                   matrix_time_f2   => matrix_time_f2,
-                  addr_matrix_f0_0  => addr_matrix_f0_0,
+                  addr_matrix_f0  => addr_matrix_f0,
             --      addr_matrix_f0_1  => addr_matrix_f0_1,
                   addr_matrix_f1    => addr_matrix_f1,
                   addr_matrix_f2    => addr_matrix_f2,
                   addr_data_f1      => addr_data_f1,
                   addr_data_f2      => addr_data_f2,
                   addr_data_f3      => addr_data_f3,
-                  start_date        => start_date,
+                  start_date        => start_date);
-                  ---------------------------------------------------------------------------
-                  debug_reg0        => debug_reg0,
-                  debug_reg1        => debug_reg1,
-                  debug_reg2        => debug_reg2,
-                  debug_reg3        => debug_reg3,
-                  debug_reg4        => debug_reg4,
-                  debug_reg5        => debug_reg5,
-                  debug_reg6        => debug_reg6,
-                  debug_reg7        => debug_reg7);
-              debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
-              debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
-              debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
               -----------------------------------------------------------------------------
-              --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357";  -- TODO : debug
-              --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB";  -- TODO : debug
-              --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773";  -- TODO : debug
-              --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612";  -- TODO : debug
               -----------------------------------------------------------------------------
               lpp_waveform_1 : lpp_waveform
                 GENERIC MAP (
                   --f0
                   addr_data_f0                 => addr_data_f0,
                   data_f0_in_valid             => sample_f0_val,
-                  data_f0_in                   => sample_f0_data,  -- sample_f0_data_debug,  -- TODO : debug
+                  data_f0_in                   => sample_f0_data,
                   --f1
                   addr_data_f1                 => addr_data_f1,
                   data_f1_in_valid             => sample_f1_val,
-                  data_f1_in                   => sample_f1_data,  -- sample_f1_data_debug,  -- TODO : debug,
+                  data_f1_in                   => sample_f1_data,
                   --f2
                   addr_data_f2                 => addr_data_f2,
                   data_f2_in_valid             => sample_f2_val,
-                  data_f2_in                   => sample_f2_data,  -- sample_f2_data_debug,  -- TODO : debug,
+                  data_f2_in                   => sample_f2_data,
                   --f3
                   addr_data_f3                 => addr_data_f3,
                   data_f3_in_valid             => sample_f3_val,
-                  data_f3_in                   => sample_f3_data,  -- sample_f3_data_debug,  -- TODO : debug,
+                  data_f3_in                   => sample_f3_data,
                   -- OUTPUT -- DMA interface
                   --f0
                   data_f0_addr_out             => data_f0_addr_out_s,
               dma_data_2 <= dma_data;
-              -----------------------------------------------------------------------------
-              -- DEBUG -- DMA IN
-              --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren;
-              --debug_f0_data_dma_in       <= dma_data;
-              --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren;
-              --debug_f1_data_dma_in       <= dma_data;
-              --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren;
-              --debug_f2_data_dma_in       <= dma_data;
-              --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren;
-              --debug_f3_data_dma_in       <= dma_data;
-              -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- DMA
               -----------------------------------------------------------------------------
                   sample_f0_wdata => sample_f0_wdata,
                   sample_f1_wen   => sample_f1_wen,
                   sample_f1_wdata => sample_f1_wdata,
-                  sample_f2_wen   => sample_f3_wen,  -- TODO verify that it's the good data
+                  sample_f2_wen   => sample_f3_wen,  -- TODO
-                  sample_f2_wdata => sample_f3_wdata,-- TODO verify that it's the good data
+                  sample_f2_wdata => sample_f3_wdata,-- TODO
                   dma_addr        => data_ms_addr,         --
                   dma_data        => data_ms_data,         --
                   dma_ren         => data_ms_ren,          --
                   dma_done        => data_ms_done,         --
-                  ready_matrix_f0                        => ready_matrix_f0_0,-- TODO rename
+                  ready_matrix_f0                        => ready_matrix_f0,
                   ready_matrix_f1                        => ready_matrix_f1,
                   ready_matrix_f2                        => ready_matrix_f2,
-                  --error_anticipating_empty_fifo          => error_anticipating_empty_fifo,
                   error_bad_component_error              => error_bad_component_error,
-                  error_buffer_full                      => error_buffer_full,      -- TODO
+                  error_buffer_full                      => error_buffer_full,
-                  error_input_fifo_write                 => error_input_fifo_write, -- TODO
+                  error_input_fifo_write                 => error_input_fifo_write,
                   debug_reg                              => observation_reg,
-                  status_ready_matrix_f0                 => status_ready_matrix_f0_0,-- TODO rename
+                  status_ready_matrix_f0                 => status_ready_matrix_f0,
                   status_ready_matrix_f1                 => status_ready_matrix_f1,
                   status_ready_matrix_f2                 => status_ready_matrix_f2,
-            --      status_error_anticipating_empty_fifo   => status_error_anticipating_empty_fifo,-- TODO
-            --      status_error_bad_component_error       => status_error_bad_component_error,-- TODO
                   config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
                   config_active_interruption_onError     => config_active_interruption_onError,
-                  addr_matrix_f0                         => addr_matrix_f0_0,-- TODO rename
+                  addr_matrix_f0                         => addr_matrix_f0,
                   addr_matrix_f1                         => addr_matrix_f1,
                   addr_matrix_f2                         => addr_matrix_f2,
-                  matrix_time_f0                         => matrix_time_f0_0,-- TODO rename
+                  matrix_time_f0                         => matrix_time_f0,
                   matrix_time_f1                         => matrix_time_f1,
                   matrix_time_f2                         => matrix_time_f2);
-            END beh;
  No newline at end of file
+            END beh;

lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +410 -296

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	@@ -28,6 +28,7 USE grlib.amba.ALL;
	28	USE grlib.stdlib.ALL;	28	USE grlib.stdlib.ALL;
	29	USE grlib.devices.ALL;	29	USE grlib.devices.ALL;
	30	LIBRARY lpp;	30	LIBRARY lpp;
			31	USE lpp.lpp_lfr_pkg.ALL;
	31	USE lpp.lpp_amba.ALL;	32	USE lpp.lpp_amba.ALL;
	32	USE lpp.apb_devices_list.ALL;	33	USE lpp.apb_devices_list.ALL;
	33	USE lpp.lpp_memory.ALL;	34	USE lpp.lpp_memory.ALL;
	@@ -38,16 +39,16 ENTITY lpp_lfr_apbreg IS
	38	GENERIC (	39	GENERIC (
	39	nb_data_by_buffer_size : INTEGER := 11;	40	nb_data_by_buffer_size : INTEGER := 11;
	40	nb_word_by_buffer_size : INTEGER := 11;	41	nb_word_by_buffer_size : INTEGER := 11;
	41	nb_snapshot_param_size : INTEGER := 11;	42	nb_snapshot_param_size : INTEGER := 11;
	42	delta_vector_size : INTEGER := 20;	43	delta_vector_size : INTEGER := 20;
	43	delta_vector_size_f0_2 : INTEGER := 3;	44	delta_vector_size_f0_2 : INTEGER := 3;
	44		45
	45	pindex : INTEGER := 4;	46	pindex : INTEGER := 4;
	46	paddr : INTEGER := 4;	47	paddr : INTEGER := 4;
	47	pmask : INTEGER := 16#fff#;	48	pmask : INTEGER := 16#fff#;
	48	pirq_ms : INTEGER := 0;	49	pirq_ms : INTEGER := 0;
	49	pirq_wfp : INTEGER := 1;	50	pirq_wfp : INTEGER := 1;
	50	top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");	51	top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
	51	PORT (	52	PORT (
	52	-- AMBA AHB system signals	53	-- AMBA AHB system signals
	53	HCLK : IN STD_ULOGIC;	54	HCLK : IN STD_ULOGIC;
	@@ -59,44 +60,42 ENTITY lpp_lfr_apbreg IS
	59		60
	60	---------------------------------------------------------------------------	61	---------------------------------------------------------------------------
	61	-- Spectral Matrix Reg	62	-- Spectral Matrix Reg
	62	run_ms : OUT STD_LOGIC;	63	run_ms : OUT STD_LOGIC;
	63	-- IN	64	-- IN
	64	ready_matrix_f0_0 : IN STD_LOGIC;	65	ready_matrix_f0 : IN STD_LOGIC;
	65	ready_matrix_f1 : IN STD_LOGIC;	66	ready_matrix_f1 : IN STD_LOGIC;
	66	ready_matrix_f2 : IN STD_LOGIC;	67	ready_matrix_f2 : IN STD_LOGIC;
	67		68
	68	error_bad_component_error : IN STD_LOGIC;	69	error_bad_component_error : IN STD_LOGIC;
	69	error_buffer_full : in STD_LOGIC; -- TODO	70	error_buffer_full : IN STD_LOGIC; -- TODO
	70	error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO	71	error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
	71		72
	72	debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	73	-- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	73		74
	74	-- OUT	75	-- OUT
	75	status_ready_matrix_f0_0 : OUT STD_LOGIC;	76	status_ready_matrix_f0 : OUT STD_LOGIC;
	76	status_ready_matrix_f1 : OUT STD_LOGIC;	77	status_ready_matrix_f1 : OUT STD_LOGIC;
	77	status_ready_matrix_f2 : OUT STD_LOGIC;	78	status_ready_matrix_f2 : OUT STD_LOGIC;
	78		79
	79	config_active_interruption_onNewMatrix : OUT STD_LOGIC;	80	config_active_interruption_onNewMatrix : OUT STD_LOGIC;
	80	config_active_interruption_onError : OUT STD_LOGIC;	81	config_active_interruption_onError : OUT STD_LOGIC;
	81		82
	82	addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	83	addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	83	-- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	84	addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	84	addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	85	addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	85	addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	86
	86		87	matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	87	matrix_time_f~~0_0~~ : IN STD_LOGIC_VECTOR(47 DOWNTO 0);	88	matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	88	-- matrix_time_f~~0_1~~ : IN STD_LOGIC_VECTOR(47 DOWNTO 0);	89	matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	89	matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);	90
	90	matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	91
	92	---------------------------------------------------------------------------	91	---------------------------------------------------------------------------
	93	---------------------------------------------------------------------------	92	---------------------------------------------------------------------------
	94	-- WaveForm picker Reg	93	-- WaveForm picker Reg
	95	status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);	94	status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	96	status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);	95	status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	97	status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);	96	status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	98	status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);	97	status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	99		98
	100	-- OUT	99	-- OUT
	101	data_shaping_BW : OUT STD_LOGIC;	100	data_shaping_BW : OUT STD_LOGIC;
	102	data_shaping_SP0 : OUT STD_LOGIC;	101	data_shaping_SP0 : OUT STD_LOGIC;
	@@ -104,14 +103,14 ENTITY lpp_lfr_apbreg IS
	104	data_shaping_R0 : OUT STD_LOGIC;	103	data_shaping_R0 : OUT STD_LOGIC;
	105	data_shaping_R1 : OUT STD_LOGIC;	104	data_shaping_R1 : OUT STD_LOGIC;
	106		105
	107	delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	106	delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	108	delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	107	delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	109	delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);	108	delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
	110	delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	109	delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	111	delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	110	delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	112	nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);	111	nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
	113	nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);	112	nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
	114	nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);	113	nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
	115		114
	116	enable_f0 : OUT STD_LOGIC;	115	enable_f0 : OUT STD_LOGIC;
	117	enable_f1 : OUT STD_LOGIC;	116	enable_f1 : OUT STD_LOGIC;
	@@ -128,17 +127,7 ENTITY lpp_lfr_apbreg IS
	128	addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	127	addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	129	addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	128	addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	130	addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	129	addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	131	start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);	130	start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0)
	132	---------------------------------------------------------------------------
	133	debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	134	debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	135	debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	136	debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	137	debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	138	debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	139	debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	140	debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
	141
	142	---------------------------------------------------------------------------	131	---------------------------------------------------------------------------
	143	);	132	);
	144		133
	@@ -157,60 +146,61 ARCHITECTURE beh OF lpp_lfr_apbreg IS
	157	config_active_interruption_onError : STD_LOGIC;	146	config_active_interruption_onError : STD_LOGIC;
	158	config_ms_run : STD_LOGIC;	147	config_ms_run : STD_LOGIC;
	159	status_ready_matrix_f0_0 : STD_LOGIC;	148	status_ready_matrix_f0_0 : STD_LOGIC;
	160	-- status_ready_matrix_f0_1 : STD_LOGIC;	149	status_ready_matrix_f1_0 : STD_LOGIC;
	161	status_ready_matrix_f1 : STD_LOGIC;	150	status_ready_matrix_f2_0 : STD_LOGIC;
	162	status_ready_matrix_f2 : STD_LOGIC;	151	status_ready_matrix_f0_1 : STD_LOGIC;
	163	-- status_error_anticipating_empty_fifo : STD_LOGIC;	152	status_ready_matrix_f1_1 : STD_LOGIC;
			153	status_ready_matrix_f2_1 : STD_LOGIC;
	164	status_error_bad_component_error : STD_LOGIC;	154	status_error_bad_component_error : STD_LOGIC;
	165	status_error_buffer_full : STD_LOGIC; ~~-- TODO~~	155	status_error_buffer_full : STD_LOGIC;
	166	status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); ~~-- TODO~~	156	status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
			157
	167	addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);	158	addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	168	-- addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);	159	addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	169	addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);	160	addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	170	addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);	161	addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
			162	addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
			163	addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	171		164
	172	~~coarse_~~time_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);	165	time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
	173	-- ~~coarse_~~time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);	166	time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
	174	~~coarse_time_f1~~ : STD_LOGIC_VECTOR(31 DOWNTO 0);	167	time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
	175	~~coarse_time_f2~~ : STD_LOGIC_VECTOR(31 DOWNTO 0);	168	time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
	176		169	time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
	177	~~-- fine_time_f0_0~~ : STD_LOGIC_VECTOR(15 DOWNTO 0);	170	time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
	178	-- fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
	179	-- fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
	180	-- fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
	181	END RECORD;	171	END RECORD;
	182	SIGNAL reg_sp : lpp_SpectralMatrix_regs;	172	SIGNAL reg_sp : lpp_SpectralMatrix_regs;
	183		173
	184	TYPE lpp_WaveformPicker_regs IS RECORD	174	TYPE lpp_WaveformPicker_regs IS RECORD
	185	status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);	175	status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
	186	status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);	176	status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
	187	status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);	177	status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
	188	data_shaping_BW : STD_LOGIC;	178	data_shaping_BW : STD_LOGIC;
	189	data_shaping_SP0 : STD_LOGIC;	179	data_shaping_SP0 : STD_LOGIC;
	190	data_shaping_SP1 : STD_LOGIC;	180	data_shaping_SP1 : STD_LOGIC;
	191	data_shaping_R0 : STD_LOGIC;	181	data_shaping_R0 : STD_LOGIC;
	192	data_shaping_R1 : STD_LOGIC;	182	data_shaping_R1 : STD_LOGIC;
	193	delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	183	delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	194	delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	184	delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	195	delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);	185	delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
	196	delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	186	delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	197	delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	187	delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	198	nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);	188	nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
	199	nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);	189	nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
	200	nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);	190	nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
	201	enable_f0 : STD_LOGIC;	191	enable_f0 : STD_LOGIC;
	202	enable_f1 : STD_LOGIC;	192	enable_f1 : STD_LOGIC;
	203	enable_f2 : STD_LOGIC;	193	enable_f2 : STD_LOGIC;
	204	enable_f3 : STD_LOGIC;	194	enable_f3 : STD_LOGIC;
	205	burst_f0 : STD_LOGIC;	195	burst_f0 : STD_LOGIC;
	206	burst_f1 : STD_LOGIC;	196	burst_f1 : STD_LOGIC;
	207	burst_f2 : STD_LOGIC;	197	burst_f2 : STD_LOGIC;
	208	run : STD_LOGIC;	198	run : STD_LOGIC;
	209	addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);	199	addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	210	addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);	200	addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	211	addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);	201	addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	212	addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);	202	addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
	213	start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);	203	start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
	214	END RECORD;	204	END RECORD;
	215	SIGNAL reg_wp : lpp_WaveformPicker_regs;	205	SIGNAL reg_wp : lpp_WaveformPicker_regs;
	216		206
	@@ -219,28 +209,53 ARCHITECTURE beh OF lpp_lfr_apbreg IS
	219	-----------------------------------------------------------------------------	209	-----------------------------------------------------------------------------
	220	-- IRQ	210	-- IRQ
	221	-----------------------------------------------------------------------------	211	-----------------------------------------------------------------------------
	222	CONSTANT IRQ_WFP_SIZE : INTEGER := 12;	212	CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
	223	SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);	213	SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
	224	SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);	214	SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
	225	SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);	215	SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
	226	SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);	216	SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
	227	SIGNAL ored_irq_wfp : STD_LOGIC;	217	SIGNAL ored_irq_wfp : STD_LOGIC;
			218
			219	-----------------------------------------------------------------------------
			220	--
			221	-----------------------------------------------------------------------------
			222	SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
			223	SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
			224	SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
			225
			226	SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
			227	SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
			228	SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
			229
			230	SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
			231	SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
			232	SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
			233
			234	SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
			235	SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
			236	SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
			237
			238	SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
			239	SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
			240	SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
			241
			242	SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
			243	SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
			244	SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
	228		245
	229	BEGIN -- beh	246	BEGIN -- beh
	230		247
	231	status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;	248	-- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
	232	-- status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;	249	-- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
	233	status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;	250	-- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
	234	status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
	235	-- status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
	236	-- status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
	237		251
	238	config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;	252	config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
	239	config_active_interruption_onError <= reg_sp.config_active_interruption_onError;	253	config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
	240	addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;	254
	241	-- addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;	255
	242	addr_matrix_f1 <= reg_sp.addr_matrix_f1;	256	-- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
	243	addr_matrix_f2 <= reg_sp.addr_matrix_f2;	257	-- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
			258	-- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
	244		259
	245		260
	246	data_shaping_BW <= NOT reg_wp.data_shaping_BW;	261	data_shaping_BW <= NOT reg_wp.data_shaping_BW;
	@@ -249,14 +264,14 BEGIN -- beh
	249	data_shaping_R0 <= reg_wp.data_shaping_R0;	264	data_shaping_R0 <= reg_wp.data_shaping_R0;
	250	data_shaping_R1 <= reg_wp.data_shaping_R1;	265	data_shaping_R1 <= reg_wp.data_shaping_R1;
	251		266
	252	delta_snapshot <= reg_wp.delta_snapshot;	267	delta_snapshot <= reg_wp.delta_snapshot;
	253	delta_f0 <= reg_wp.delta_f0;	268	delta_f0 <= reg_wp.delta_f0;
	254	delta_f0_2 <= reg_wp.delta_f0_2;	269	delta_f0_2 <= reg_wp.delta_f0_2;
	255	delta_f1 <= reg_wp.delta_f1;	270	delta_f1 <= reg_wp.delta_f1;
	256	delta_f2 <= reg_wp.delta_f2;	271	delta_f2 <= reg_wp.delta_f2;
	257	nb_data_by_buffer <= reg_wp.nb_data_by_buffer;	272	nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
	258	nb_word_by_buffer <= reg_wp.nb_word_by_buffer;	273	nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
	259	nb_snapshot_param <= reg_wp.nb_snapshot_param;	274	nb_snapshot_param <= reg_wp.nb_snapshot_param;
	260		275
	261	enable_f0 <= reg_wp.enable_f0;	276	enable_f0 <= reg_wp.enable_f0;
	262	enable_f1 <= reg_wp.enable_f1;	277	enable_f1 <= reg_wp.enable_f1;
	@@ -284,99 +299,99 BEGIN -- beh
	284	reg_sp.config_active_interruption_onError <= '0';	299	reg_sp.config_active_interruption_onError <= '0';
	285	reg_sp.config_ms_run <= '1';	300	reg_sp.config_ms_run <= '1';
	286	reg_sp.status_ready_matrix_f0_0 <= '0';	301	reg_sp.status_ready_matrix_f0_0 <= '0';
	287	-- reg_sp.status_ready_matrix_f0_1 <= '0';	302	reg_sp.status_ready_matrix_f1_0 <= '0';
	288	reg_sp.status_ready_matrix_f1 <= '0';	303	reg_sp.status_ready_matrix_f2_0 <= '0';
	289	reg_sp.status_ready_matrix_f2 <= '0';	304	reg_sp.status_ready_matrix_f0_1 <= '0';
	290	-- reg_sp.status_~~error_anticipating_empty_fifo~~ <= '0';	305	reg_sp.status_ready_matrix_f1_1 <= '0';
			306	reg_sp.status_ready_matrix_f2_1 <= '0';
	291	reg_sp.status_error_bad_component_error <= '0';	307	reg_sp.status_error_bad_component_error <= '0';
	292	reg_sp.status_error_buffer_full <= '0';	308	reg_sp.status_error_buffer_full <= '0';
	293	reg_sp.status_error_input_fifo_write <= (OTHERS => '0');	309	reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
	294		310
	295	reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');	311	reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
	296	-- reg_sp.addr_matrix_f~~0_1~~ <= (OTHERS => '0');	312	reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
	297	reg_sp.addr_matrix_f1 <= (OTHERS => '0');	313	reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
	298	reg_sp.addr_matrix_f2 <= (OTHERS => '0');	314
			315	reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
			316	reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
			317	reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
	299		318
	300	reg_sp.~~coarse_~~time_f0_0 <= (OTHERS => '0');	319	reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
	301	-- reg_sp.~~coarse_time_f0_1~~ <= (OTHERS => '0');	320	reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
	302	reg_sp.~~coarse_time_f1~~ <= (OTHERS => '0');	321	reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
	303	reg_sp.coarse_time_f2 <= (OTHERS => '0');	322
	304	~~--reg_sp.fine_time_f0_0 <= (OTHERS => '0');~~	323	reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
	305	--reg_sp.~~fine_time_f0_1~~ <= (OTHERS => '0');	324	reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
	306	--reg_sp.~~fine_time_f1~~ <= (OTHERS => '0');	325	reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
	307	--reg_sp.fine_time_f2 <= (OTHERS => '0');	326
	308		327	prdata <= (OTHERS => '0');
	309	prdata <= (OTHERS => '0');
	310		328
	311	apbo.pirq <= (OTHERS => '0');	329	apbo.pirq <= (OTHERS => '0');
	312		330
	313	status_full_ack <= (OTHERS => '0');	331	status_full_ack <= (OTHERS => '0');
	314		332
	315	reg_wp.data_shaping_BW <= '0';	333	reg_wp.data_shaping_BW <= '0';
	316	reg_wp.data_shaping_SP0 <= '0';	334	reg_wp.data_shaping_SP0 <= '0';
	317	reg_wp.data_shaping_SP1 <= '0';	335	reg_wp.data_shaping_SP1 <= '0';
	318	reg_wp.data_shaping_R0 <= '0';	336	reg_wp.data_shaping_R0 <= '0';
	319	reg_wp.data_shaping_R1 <= '0';	337	reg_wp.data_shaping_R1 <= '0';
	320	reg_wp.enable_f0 <= '0';	338	reg_wp.enable_f0 <= '0';
	321	reg_wp.enable_f1 <= '0';	339	reg_wp.enable_f1 <= '0';
	322	reg_wp.enable_f2 <= '0';	340	reg_wp.enable_f2 <= '0';
	323	reg_wp.enable_f3 <= '0';	341	reg_wp.enable_f3 <= '0';
	324	reg_wp.burst_f0 <= '0';	342	reg_wp.burst_f0 <= '0';
	325	reg_wp.burst_f1 <= '0';	343	reg_wp.burst_f1 <= '0';
	326	reg_wp.burst_f2 <= '0';	344	reg_wp.burst_f2 <= '0';
	327	reg_wp.run <= '0';	345	reg_wp.run <= '0';
	328	reg_wp.addr_data_f0 <= (OTHERS => '0');	346	reg_wp.addr_data_f0 <= (OTHERS => '0');
	329	reg_wp.addr_data_f1 <= (OTHERS => '0');	347	reg_wp.addr_data_f1 <= (OTHERS => '0');
	330	reg_wp.addr_data_f2 <= (OTHERS => '0');	348	reg_wp.addr_data_f2 <= (OTHERS => '0');
	331	reg_wp.addr_data_f3 <= (OTHERS => '0');	349	reg_wp.addr_data_f3 <= (OTHERS => '0');
	332	reg_wp.status_full <= (OTHERS => '0');	350	reg_wp.status_full <= (OTHERS => '0');
	333	reg_wp.status_full_err <= (OTHERS => '0');	351	reg_wp.status_full_err <= (OTHERS => '0');
	334	reg_wp.status_new_err <= (OTHERS => '0');	352	reg_wp.status_new_err <= (OTHERS => '0');
	335	reg_wp.delta_snapshot <= (OTHERS => '0');	353	reg_wp.delta_snapshot <= (OTHERS => '0');
	336	reg_wp.delta_f0 <= (OTHERS => '0');	354	reg_wp.delta_f0 <= (OTHERS => '0');
	337	reg_wp.delta_f0_2 <= (OTHERS => '0');	355	reg_wp.delta_f0_2 <= (OTHERS => '0');
	338	reg_wp.delta_f1 <= (OTHERS => '0');	356	reg_wp.delta_f1 <= (OTHERS => '0');
	339	reg_wp.delta_f2 <= (OTHERS => '0');	357	reg_wp.delta_f2 <= (OTHERS => '0');
	340	reg_wp.nb_data_by_buffer <= (OTHERS => '0');	358	reg_wp.nb_data_by_buffer <= (OTHERS => '0');
	341	reg_wp.nb_snapshot_param <= (OTHERS => '0');	359	reg_wp.nb_snapshot_param <= (OTHERS => '0');
	342	reg_wp.start_date <= (OTHERS => '0');	360	reg_wp.start_date <= (OTHERS => '0');
	343		361
	344	ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge	362	ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
	345		363
	346	reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0);	364	reg_sp.time_matrix_f0_0 <= reg0_matrix_time_f0; -- ok
	347	-- reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0);	365	reg_sp.time_matrix_f1_0 <= reg0_matrix_time_f1; -- ok
	348	reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0);	366	reg_sp.time_matrix_f2_0 <= reg0_matrix_time_f2; -- ok
	349	reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0);	367
	350		368	reg_sp.time_matrix_f0_1 <= reg1_matrix_time_f0; -- ok
	351	--reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0);	369	reg_sp.time_matrix_f1_1 <= reg1_matrix_time_f1; -- ok
	352	--reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0);	370	reg_sp.time_matrix_f2_1 <= reg1_matrix_time_f2; -- ok
	353	--reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0);	371
	354	--reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0);
	355
	356	status_full_ack <= (OTHERS => '0');	372	status_full_ack <= (OTHERS => '0');
	357		373
	358	reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;	374	reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
	359	-- reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;	375	reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
	360	reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;	376	reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
	361	reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
	362		377
	363	-- reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;	378	reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
	364	reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;	379	reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
	365		380	reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
	366	reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;	381
	367	reg_sp.status_error_~~input_fifo_write~~(0) <= reg_sp.status_error_~~input_fifo_write~~(0) OR error_~~input_fifo_write~~(0);	382	reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
	368	reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);	383
	369	reg_sp.status_error_~~input_fifo_write~~(2) <= reg_sp.status_error_~~input_fifo_write~~(2) OR error_~~input_fifo_write~~(2);	384	reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
			385	reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
			386	reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
			387	reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
	370		388
	371		389
	372		390
	373	all_status: FOR I IN 3 DOWNTO 0 LOOP	391	all_status : FOR I IN 3 DOWNTO 0 LOOP
	374	--reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;
	375	--reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run;
	376	--reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ;
	377	reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;	392	reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
	378	reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;	393	reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
	379	reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ;	394	reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run;
	380	END LOOP all_status;	395	END LOOP all_status;
	381		396
	382	paddr := "000000";	397	paddr := "000000";
	@@ -385,42 +400,67 BEGIN -- beh
	385	IF apbi.psel(pindex) = '1' THEN	400	IF apbi.psel(pindex) = '1' THEN
	386	-- APB DMA READ --	401	-- APB DMA READ --
	387	CASE paddr(7 DOWNTO 2) IS	402	CASE paddr(7 DOWNTO 2) IS
	388	--	403	--0
	389	WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;	404	WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
	390	prdata(1) <= reg_sp.config_active_interruption_onError;	405	prdata(1) <= reg_sp.config_active_interruption_onError;
	391	prdata(2) <= reg_sp.config_ms_run;	406	prdata(2) <= reg_sp.config_ms_run;
			407	--1
	392	WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;	408	WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
	393	-- prdata(1) <= reg_sp.status_ready_matrix_f0_1;	409	prdata(1) <= reg_sp.status_ready_matrix_f0_1;
	394	prdata(2) <= reg_sp.status_ready_matrix_f1;	410	prdata(2) <= reg_sp.status_ready_matrix_f1_0;
	395	prdata(3) <= reg_sp.status_ready_matrix_f2;	411	prdata(3) <= reg_sp.status_ready_matrix_f1_1;
	396	-- prdata(4) <= reg_sp.status_~~error_anticipating_empty_fifo~~;	412	prdata(4) <= reg_sp.status_ready_matrix_f2_0;
	397	prdata(5) <= reg_sp.status_~~error_bad_component_error~~;	413	prdata(5) <= reg_sp.status_ready_matrix_f2_1;
	398	prdata(6) <= reg_sp.status_error_b~~uffer_full~~;	414	prdata(6) <= reg_sp.status_error_bad_component_error;
	399	prdata(7) <= reg_sp.status_error_~~input_fifo_write~~(0);	415	prdata(7) <= reg_sp.status_error_buffer_full;
	400	prdata(8) <= reg_sp.status_error_input_fifo_write(1);	416	prdata(8) <= reg_sp.status_error_input_fifo_write(0);
	401	prdata(9) <= reg_sp.status_error_input_fifo_write(2);	417	prdata(9) <= reg_sp.status_error_input_fifo_write(1);
	402	WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;	418	prdata(10) <= reg_sp.status_error_input_fifo_write(2);
	403	-- WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;	419	--2
	404	WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;	420	WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
	405	WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;	421	--3
	406		422	WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
	407	WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0;	423	--4
	408	-- WHEN "000111" => prdata <= reg_sp.~~coarse_time_f0_1~~;	424	WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0;
	409	WHEN "001000" => prdata <= reg_sp.coarse_time_f1;	425	--5
	410	WHEN "001001" => prdata <= reg_sp.~~coarse_time_f2~~;	426	WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1;
	411	WHEN "001010" => prdata(15 downto 0) <= matrix_time_f0_0(15 DOWNTO 0);--reg_sp.fine_time_f0_0;	427	--6
	412	-- WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1;	428	WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0;
	413	WHEN "001100" => prdata(15 downto 0) <= matrix_time_f1 (15 DOWNTO 0);--reg_sp.fine_time_f1;	429	--7
	414	WHEN "001101" => prdata(15 downto 0) <= matrix_time_f2 (15 DOWNTO 0);--reg_sp.fine_time_f2;	430	WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1;
	415		431	--8
	416	WHEN "001111" => prdata <= debug_reg;	432	WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
	417	---------------------------------------------------------------------	433	--9
	418	WHEN "0~~10000~~" => prdata(0) <= reg_wp.~~data_shaping_BW~~;	434	WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
			435	--10
			436	WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
			437	--11
			438	WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
			439	--12
			440	WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
			441	--13
			442	WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
			443	--14
			444	WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
			445	--15
			446	WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
			447	--16
			448	WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
			449	--17
			450	WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
			451	--18
			452	WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
			453	--19
			454	WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
			455	---------------------------------------------------------------------
			456	--20
			457	WHEN "010100" => prdata(0) <= reg_wp.data_shaping_BW;
	419	prdata(1) <= reg_wp.data_shaping_SP0;	458	prdata(1) <= reg_wp.data_shaping_SP0;
	420	prdata(2) <= reg_wp.data_shaping_SP1;	459	prdata(2) <= reg_wp.data_shaping_SP1;
	421	prdata(3) <= reg_wp.data_shaping_R0;	460	prdata(3) <= reg_wp.data_shaping_R0;
	422	prdata(4) <= reg_wp.data_shaping_R1;	461	prdata(4) <= reg_wp.data_shaping_R1;
	423	WHEN "010001" => prdata(0) <= reg_wp.enable_f0;	462	--21
			463	WHEN "010101" => prdata(0) <= reg_wp.enable_f0;
	424	prdata(1) <= reg_wp.enable_f1;	464	prdata(1) <= reg_wp.enable_f1;
	425	prdata(2) <= reg_wp.enable_f2;	465	prdata(2) <= reg_wp.enable_f2;
	426	prdata(3) <= reg_wp.enable_f3;	466	prdata(3) <= reg_wp.enable_f3;
	@@ -428,33 +468,38 BEGIN -- beh
	428	prdata(5) <= reg_wp.burst_f1;	468	prdata(5) <= reg_wp.burst_f1;
	429	prdata(6) <= reg_wp.burst_f2;	469	prdata(6) <= reg_wp.burst_f2;
	430	prdata(7) <= reg_wp.run;	470	prdata(7) <= reg_wp.run;
	431	WHEN "010010" => prdata <= reg_wp.addr_data_f0;	471	--22
	432	WHEN "010011" => prdata <= reg_wp.addr_data_f1;	472	WHEN "010110" => prdata <= reg_wp.addr_data_f0;
	433	WHEN "010100" => prdata <= reg_wp.addr_data_f2;	473	--23
	434	WHEN "010101" => prdata <= reg_wp.addr_data_f3;	474	WHEN "010111" => prdata <= reg_wp.addr_data_f1;
	435	WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;	475	--24
			476	WHEN "011000" => prdata <= reg_wp.addr_data_f2;
			477	--25
			478	WHEN "011001" => prdata <= reg_wp.addr_data_f3;
			479	--26
			480	WHEN "011010" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
	436	prdata(7 DOWNTO 4) <= reg_wp.status_full_err;	481	prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
	437	prdata(11 DOWNTO 8) <= reg_wp.status_new_err;	482	prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
	438	WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;	483	--27
	439	WHEN "011000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;	484	WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
	440	WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;	485	--28
	441	WHEN "011010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;	486	WHEN "011100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
	442	WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;	487	--29
	443	WHEN "011100" => prdata(~~nb_data_by_buffe~~r_size-1 DOWNTO 0) <= reg_wp.~~nb_data_by_buffer~~;	488	WHEN "011101" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
	444	WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;	489	--30
	445	WHEN "011110" => prdata(30 DOWNTO 0) <= reg_wp.~~start_date~~;	490	WHEN "011110" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
	446	WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;	491	--31
	447	----------------------------------------------------	492	WHEN "011111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
	448	WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0);	493	--32
	449	WHEN "100001" => prdata(31 DOWNTO 0) <= ~~debug_reg1~~(31 ~~DOWNTO~~ 0);	494	WHEN "100000" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
	450	WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0);	495	--33
	451	WHEN "100011" => prdata(31 DOWNTO 0) <= ~~debug_reg3~~(31 ~~DOWNTO~~ 0);	496	WHEN "100001" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
	452	WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0);	497	--34
	453	WHEN "100101" => prdata(31 DOWNTO 0) <= ~~debug_reg5~~(31 ~~DOWNTO~~ 0);	498	WHEN "100010" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
	454	WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0);	499	--35
	455	WHEN "100111" => prdata(31 DOWNTO 0) <= ~~debug_reg7~~(31 ~~DOWNTO~~ 0);	500	WHEN "100011" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
	456	----------------------------------------------------	501	----------------------------------------------------
	457	WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);	502	WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
	458	WHEN OTHERS => NULL;	503	WHEN OTHERS => NULL;
	459		504
	460	END CASE;	505	END CASE;
	@@ -465,27 +510,32 BEGIN -- beh
	465	WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);	510	WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
	466	reg_sp.config_active_interruption_onError <= apbi.pwdata(1);	511	reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
	467	reg_sp.config_ms_run <= apbi.pwdata(2);	512	reg_sp.config_ms_run <= apbi.pwdata(2);
	468	WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);	513	WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
	469	-- reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);	514	reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
	470	reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);	515	reg_sp.status_ready_matrix_f1_0 <= apbi.pwdata(2);
	471	reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);	516	reg_sp.status_ready_matrix_f1_1 <= apbi.pwdata(3);
	472	-- reg_sp.status_~~error_anticipating_empty_fifo~~ <= apbi.pwdata(4);	517	reg_sp.status_ready_matrix_f2_0 <= apbi.pwdata(4);
	473	reg_sp.status_~~error_bad_component_error~~ <= apbi.pwdata(5);	518	reg_sp.status_ready_matrix_f2_1 <= apbi.pwdata(5);
	474	reg_sp.status_error_b~~uffer_full~~ <= apbi.pwdata(6);	519	reg_sp.status_error_bad_component_error <= apbi.pwdata(6);
	475	reg_sp.status_error_~~input_fifo_write~~(0) <= apbi.pwdata(7);	520	reg_sp.status_error_buffer_full <= apbi.pwdata(7);
	476	reg_sp.status_error_input_fifo_write(1) <= apbi.pwdata(8);	521	reg_sp.status_error_input_fifo_write(0) <= apbi.pwdata(8);
	477	reg_sp.status_error_input_fifo_write(2) <= apbi.pwdata(9);	522	reg_sp.status_error_input_fifo_write(1) <= apbi.pwdata(9);
	478	WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;	523	reg_sp.status_error_input_fifo_write(2) <= apbi.pwdata(10);
	479	-- WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;	524	--2
	480	WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;	525	WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
	481	WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;	526	WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
	482	--	527	WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
	483	WHEN "010000" => reg_wp.~~data_shaping_BW~~ <= apbi.pwdata(0);	528	WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
			529	WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
			530	WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
			531	--8 to 19
			532	--20
			533	WHEN "010100" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
	484	reg_wp.data_shaping_SP0 <= apbi.pwdata(1);	534	reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
	485	reg_wp.data_shaping_SP1 <= apbi.pwdata(2);	535	reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
	486	reg_wp.data_shaping_R0 <= apbi.pwdata(3);	536	reg_wp.data_shaping_R0 <= apbi.pwdata(3);
	487	reg_wp.data_shaping_R1 <= apbi.pwdata(4);	537	reg_wp.data_shaping_R1 <= apbi.pwdata(4);
	488	WHEN "010001" => reg_wp.enable_f0 <= apbi.pwdata(0);	538	WHEN "010101" => reg_wp.enable_f0 <= apbi.pwdata(0);
	489	reg_wp.enable_f1 <= apbi.pwdata(1);	539	reg_wp.enable_f1 <= apbi.pwdata(1);
	490	reg_wp.enable_f2 <= apbi.pwdata(2);	540	reg_wp.enable_f2 <= apbi.pwdata(2);
	491	reg_wp.enable_f3 <= apbi.pwdata(3);	541	reg_wp.enable_f3 <= apbi.pwdata(3);
	@@ -493,46 +543,46 BEGIN -- beh
	493	reg_wp.burst_f1 <= apbi.pwdata(5);	543	reg_wp.burst_f1 <= apbi.pwdata(5);
	494	reg_wp.burst_f2 <= apbi.pwdata(6);	544	reg_wp.burst_f2 <= apbi.pwdata(6);
	495	reg_wp.run <= apbi.pwdata(7);	545	reg_wp.run <= apbi.pwdata(7);
	496	WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata;	546	--22
	497	WHEN "010011" => reg_wp.addr_data_f1 <= apbi.pwdata;	547	WHEN "010110" => reg_wp.addr_data_f0 <= apbi.pwdata;
	498	WHEN "010100" => reg_wp.addr_data_f2 <= apbi.pwdata;	548	WHEN "010111" => reg_wp.addr_data_f1 <= apbi.pwdata;
	499	WHEN "01~~0101~~" => reg_wp.addr_data_f3 <= apbi.pwdata;	549	WHEN "011000" => reg_wp.addr_data_f2 <= apbi.pwdata;
	500	WHEN "010110" => reg_wp.~~status_full~~ <= apbi.pwdata(3 ~~DOWNTO~~ 0);	550	WHEN "011001" => reg_wp.addr_data_f3 <= apbi.pwdata;
			551	--26
			552	WHEN "011010" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
	501	reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);	553	reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
	502	reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);	554	reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
	503	status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);	555	status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
	504	status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);	556	status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
	505	status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);	557	status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
	506	status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);	558	status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
	507	WHEN "010111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);	559	WHEN "011011" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
	508	WHEN "011000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);	560	WHEN "011100" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
	509	WHEN "011001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);	561	WHEN "011101" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
	510	WHEN "011010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);	562	WHEN "011110" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
	511	WHEN "011011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);	563	WHEN "011111" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
	512	WHEN "~~011~~100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);	564	WHEN "100000" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
	513	WHEN "~~011~~101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);	565	WHEN "100001" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
	514	WHEN "~~011~~110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);	566	WHEN "100010" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
	515	WHEN "~~011~~111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);	567	WHEN "100011" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
	516	--	568	--
	517	WHEN OTHERS => NULL;	569	WHEN OTHERS => NULL;
	518	END CASE;	570	END CASE;
	519	END IF;	571	END IF;
	520	END IF;	572	END IF;
	521		573
	522	apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR	574	apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
	523	-- ready_matrix_f0_1 OR
	524	ready_matrix_f1 OR	575	ready_matrix_f1 OR
	525	ready_matrix_f2)	576	ready_matrix_f2)
	526	)	577	)
	527	OR	578	OR
	528	(reg_sp.config_active_interruption_onError AND (	579	(reg_sp.config_active_interruption_onError AND (
	529	~~--error_anticipating_empty_fifo OR~~	580	error_bad_component_error
	530	error_bad_component_error	581	OR error_buffer_full
	531	OR error_buffer_full	582	OR error_input_fifo_write(0)
	532	OR error_input_fifo_write(0)	583	OR error_input_fifo_write(1)
	533	OR error_input_fifo_write(1)	584	OR error_input_fifo_write(2))
	534	OR error_input_fifo_write(2))	585	));
	535	));
	536		586
	537	apbo.pirq(pirq_wfp) <= ored_irq_wfp;	587	apbo.pirq(pirq_wfp) <= ored_irq_wfp;
	538		588
	@@ -547,17 +597,17 BEGIN -- beh
	547	-- IRQ	597	-- IRQ
	548	-----------------------------------------------------------------------------	598	-----------------------------------------------------------------------------
	549	irq_wfp_reg_s <= status_full & status_full_err & status_new_err;	599	irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
	550		600
	551	PROCESS (HCLK, HRESETn)	601	PROCESS (HCLK, HRESETn)
	552	BEGIN -- PROCESS	602	BEGIN -- PROCESS
	553	IF HRESETn = '0' THEN -- asynchronous reset (active low)	603	IF HRESETn = '0' THEN -- asynchronous reset (active low)
	554	irq_wfp_reg <= (OTHERS => '0');	604	irq_wfp_reg <= (OTHERS => '0');
	555	ELSIF HCLK'~~event~~ AND HCLK = '1' THEN -- rising clock edge	605	ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
	556	irq_wfp_reg <= irq_wfp_reg_s;	606	irq_wfp_reg <= irq_wfp_reg_s;
	557	END IF;	607	END IF;
	558	END PROCESS;	608	END PROCESS;
	559		609
	560	all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE	610	all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
	561	irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);	611	irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
	562	END GENERATE all_irq_wfp;	612	END GENERATE all_irq_wfp;
	563		613
	@@ -565,5 +615,69 BEGIN -- beh
	565	ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';	615	ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
	566		616
	567	run_ms <= reg_sp.config_ms_run;	617	run_ms <= reg_sp.config_ms_run;
			618
			619	-----------------------------------------------------------------------------
			620	--
			621	-----------------------------------------------------------------------------
			622	lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
			623	PORT MAP (
			624	clk => HCLK,
			625	rstn => HRESETn,
			626
			627	reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
			628	reg0_ready_matrix => reg0_ready_matrix_f0,
			629	reg0_addr_matrix => reg0_addr_matrix_f0,
			630	reg0_matrix_time => reg0_matrix_time_f0,
			631
			632	reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
			633	reg1_ready_matrix => reg1_ready_matrix_f0,
			634	reg1_addr_matrix => reg1_addr_matrix_f0,
			635	reg1_matrix_time => reg1_matrix_time_f0,
			636
			637	ready_matrix => ready_matrix_f0,
			638	status_ready_matrix => status_ready_matrix_f0,
			639	addr_matrix => addr_matrix_f0,
			640	matrix_time => matrix_time_f0);
			641
			642	lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
			643	PORT MAP (
			644	clk => HCLK,
			645	rstn => HRESETn,
			646
			647	reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
			648	reg0_ready_matrix => reg0_ready_matrix_f1,
			649	reg0_addr_matrix => reg0_addr_matrix_f1,
			650	reg0_matrix_time => reg0_matrix_time_f1,
			651
			652	reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
			653	reg1_ready_matrix => reg1_ready_matrix_f1,
			654	reg1_addr_matrix => reg1_addr_matrix_f1,
			655	reg1_matrix_time => reg1_matrix_time_f1,
			656
			657	ready_matrix => ready_matrix_f1,
			658	status_ready_matrix => status_ready_matrix_f1,
			659	addr_matrix => addr_matrix_f1,
			660	matrix_time => matrix_time_f1);
	568		661
	569	END beh;	662	lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
			663	PORT MAP (
			664	clk => HCLK,
			665	rstn => HRESETn,
			666
			667	reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
			668	reg0_ready_matrix => reg0_ready_matrix_f2,
			669	reg0_addr_matrix => reg0_addr_matrix_f2,
			670	reg0_matrix_time => reg0_matrix_time_f2,
			671
			672	reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
			673	reg1_ready_matrix => reg1_ready_matrix_f2,
			674	reg1_addr_matrix => reg1_addr_matrix_f2,
			675	reg1_matrix_time => reg1_matrix_time_f2,
			676
			677	ready_matrix => ready_matrix_f2,
			678	status_ready_matrix => status_ready_matrix_f2,
			679	addr_matrix => addr_matrix_f2,
			680	matrix_time => matrix_time_f2);
			681
			682
			683	END beh; No newline at end of file

lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +25 -14

                   apbi                                   : IN  apb_slv_in_type;
                   apbo                                   : OUT apb_slv_out_type;
                   run_ms                                 : OUT STD_LOGIC;
-                  ready_matrix_f0_0                      : IN  STD_LOGIC;
+                  ready_matrix_f0                      : IN  STD_LOGIC;
                   ready_matrix_f1                        : IN  STD_LOGIC;
                   ready_matrix_f2                        : IN  STD_LOGIC;
                   error_bad_component_error              : IN  STD_LOGIC;
                   error_buffer_full                      : in  STD_LOGIC;
                   error_input_fifo_write                 : in  STD_LOGIC_VECTOR(2 DOWNTO 0);
-                  debug_reg                              : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --x      debug_reg                              : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
-                  status_ready_matrix_f0_0               : OUT STD_LOGIC;
+                  status_ready_matrix_f0               : OUT STD_LOGIC;
                   status_ready_matrix_f1                 : OUT STD_LOGIC;
                   status_ready_matrix_f2                 : OUT STD_LOGIC;
                   config_active_interruption_onNewMatrix : OUT STD_LOGIC;
                   config_active_interruption_onError     : OUT STD_LOGIC;
-                  addr_matrix_f0_0                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+                  addr_matrix_f0                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
             --      addr_matrix_f0_1                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f1                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f2                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-                  matrix_time_f0_0                       : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
+                  matrix_time_f0                       : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
             --      matrix_time_f0_1                       : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f1                         : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f2                         : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   addr_data_f1                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f2                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f3                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-                  start_date                             : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
+                  start_date                             : OUT STD_LOGIC_VECTOR(30 DOWNTO 0)
-                  debug_reg0                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+                  );
-                  debug_reg1                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
-                  debug_reg2                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
-                  debug_reg3                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
-                  debug_reg4                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
-                  debug_reg5                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
-                  debug_reg6                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
-                  debug_reg7                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
                   );
               END COMPONENT;
+              COMPONENT lpp_apbreg_ms_pointer
+                PORT (
+                  clk                      : IN  STD_LOGIC;
+                  rstn                     : IN  STD_LOGIC;
+                  reg0_status_ready_matrix : IN  STD_LOGIC;
+                  reg0_ready_matrix        : OUT STD_LOGIC;
+                  reg0_addr_matrix         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+                  reg0_matrix_time         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
+                  reg1_status_ready_matrix : IN  STD_LOGIC;
+                  reg1_ready_matrix        : OUT STD_LOGIC;
+                  reg1_addr_matrix         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+                  reg1_matrix_time         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
+                  ready_matrix             : IN  STD_LOGIC;
+                  status_ready_matrix      : OUT STD_LOGIC;
+                  addr_matrix              : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+                  matrix_time              : IN  STD_LOGIC_VECTOR(47 DOWNTO 0));
+              END COMPONENT;
             END lpp_lfr_pkg;

lib/lpp/lpp_top_lfr/vhdlsyn.txt +1 0

             lpp_lfr_pkg.vhd
             lpp_lfr_filter.vhd
             lpp_lfr_apbreg.vhd
+            lpp_lfr_apbreg_ms_pointer.vhd
             lpp_lfr_ms_fsmdma.vhd
             lpp_lfr_ms_FFT.vhd
             lpp_lfr_ms.vhd

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