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1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Jean-christophe Pellion | |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
|
22 | ---------------------------------------------------------------------------- | |
|
23 | ||
|
24 | LIBRARY ieee; | |
|
25 | USE ieee.std_logic_1164.ALL; | |
|
26 | USE ieee.numeric_std.ALL; | |
|
27 | ||
|
28 | ||
|
29 | LIBRARY lpp; | |
|
30 | USE lpp.cic_pkg.ALL; | |
|
31 | USE lpp.data_type_pkg.ALL; | |
|
32 | ||
|
33 | ENTITY cic_lfr_control_r2 IS | |
|
34 | PORT ( | |
|
35 | clk : IN STD_LOGIC; | |
|
36 | rstn : IN STD_LOGIC; | |
|
37 | run : IN STD_LOGIC; | |
|
38 | -- | |
|
39 | data_in_valid : IN STD_LOGIC; | |
|
40 | data_out_16_valid : OUT STD_LOGIC; | |
|
41 | data_out_256_valid : OUT STD_LOGIC; | |
|
42 | -- | |
|
43 | OPERATION : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) | |
|
44 | ); | |
|
45 | ||
|
46 | END cic_lfr_control_r2; | |
|
47 | ||
|
48 | ARCHITECTURE beh OF cic_lfr_control_r2 IS | |
|
49 | ||
|
50 | TYPE STATE_CIC_LFR_TYPE IS (IDLE, | |
|
51 | RUN_PROG_I, | |
|
52 | RUN_PROG_C16, | |
|
53 | RUN_PROG_C256 | |
|
54 | ); | |
|
55 | ||
|
56 | SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE; | |
|
57 | ||
|
58 | SIGNAL nb_data_receipt : INTEGER := 0; | |
|
59 | SIGNAL current_cmd : INTEGER := 0; | |
|
60 | SIGNAL current_channel : INTEGER := 0; | |
|
61 | SIGNAL sample_16_odd : STD_LOGIC; | |
|
62 | SIGNAL sample_256_odd : STD_LOGIC; | |
|
63 | ||
|
64 | TYPE PROGRAM_ARRAY IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(13 DOWNTO 0); | |
|
65 | --OPERATION( 8 DOWNTO 0) <= PROGRAM_ARRAY( 8 DOWNTO 0) sauf pour PROG_I(0) | |
|
66 | --OPERATION(13 DOWNTO 12) <= PROGRAM_ARRAY(10 DOWNTO 9) | |
|
67 | --OPERATION(11 DOWNTO 9) <= current_channel | |
|
68 | --OPERATION(14) <= PROGRAM_ARRAY(11) selon sample_X_odd et l'etat | |
|
69 | CONSTANT PROG : PROGRAM_ARRAY(0 TO 28) := | |
|
70 | ( | |
|
71 | -- DCBA 98765 43210 | |
|
72 | --PROG I------------------ | |
|
73 | "0001" & "00011" & "00000", --0 | |
|
74 | "0101" & "00010" & "00001", --1 | |
|
75 | "0101" & "00010" & "00001", --2 | |
|
76 | "0001" & "00010" & "01011", --3 | |
|
77 | "0101" & "00010" & "01001", --4 | |
|
78 | "0101" & "00010" & "01001", --5 | |
|
79 | "0001" & "00010" & "01011", --6 | |
|
80 | "0101" & "00010" & "01001", --7 | |
|
81 | "0101" & "00010" & "01001", --8 | |
|
82 | --PROG_C16 | |
|
83 | "1001" & "00100" & "10010", --9 | |
|
84 | "1001" & "10010" & "10101", --10 | |
|
85 | "1001" & "10010" & "10101", --11 | |
|
86 | "1010" & "10010" & "10101", --12 | |
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87 | "1001" & "01000" & "10010", --13 | |
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88 | "1001" & "10010" & "11101", --14 | |
|
89 | "1001" & "10010" & "11101", --15 | |
|
90 | "1010" & "10010" & "11101", --16 | |
|
91 | --PROG_C256 | |
|
92 | "1001" & "00100" & "10010", --17 | |
|
93 | "1001" & "10110" & "10101", --18 | |
|
94 | "1001" & "10110" & "10101", --19 | |
|
95 | "1010" & "10110" & "10101", --20 | |
|
96 | "1001" & "01000" & "10010", --21 | |
|
97 | "1001" & "10110" & "11101", --22 | |
|
98 | "1001" & "10110" & "11101", --23 | |
|
99 | "1010" & "10110" & "11101", --24 | |
|
100 | "1001" & "01100" & "10010", --25 | |
|
101 | "1001" & "10110" & "11101", --26 | |
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102 | "1001" & "10110" & "11101", --27 | |
|
103 | "1010" & "10110" & "11101" --28 | |
|
104 | ); | |
|
105 | ||
|
106 | ||
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107 | CONSTANT PROG_START_I : INTEGER := 0; | |
|
108 | CONSTANT PROG_END_I : INTEGER := 8; | |
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109 | CONSTANT PROG_START_C16 : INTEGER := 9; | |
|
110 | CONSTANT PROG_END_C16 : INTEGER := 16; | |
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111 | CONSTANT PROG_START_C256 : INTEGER := 17; | |
|
112 | CONSTANT PROG_END_C256 : INTEGER := 28; | |
|
113 | ||
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114 | BEGIN | |
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115 | ||
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116 | OPERATION(2 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3)); --SEL_SAMPLE | |
|
117 | OPERATION(4 DOWNTO 3) <= PROG(current_cmd)(1 DOWNTO 0); --SEL_DATA_A | |
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118 | OPERATION(6 DOWNTO 5) <= "00" WHEN STATE_CIC_LFR = IDLE ELSE PROG(current_cmd)(3 DOWNTO 2); --ALU_CMD | |
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119 | OPERATION(7) <= '0' WHEN STATE_CIC_LFR = IDLE ELSE PROG(current_cmd)(4); --CARRY_PUSH | |
|
120 | OPERATION(8) <= PROG(current_cmd)(5); --@_init | |
|
121 | OPERATION(9) <= PROG(current_cmd)(6); --@_add_1 | |
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122 | ||
|
123 | OPERATION(10) <= PROG(current_cmd)(7) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 AND PROG(current_cmd)(9) = '1' ELSE | |
|
124 | PROG(current_cmd)(7); --@_sel(1..0) | |
|
125 | OPERATION(11) <= PROG(current_cmd)(8); | |
|
126 | OPERATION(12) <= PROG(current_cmd)(9) AND sample_16_odd WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE | |
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127 | --PROG(current_cmd)(9) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE | |
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128 | PROG(current_cmd)(9) WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE | |
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129 | '0'; --@_sel(2) | |
|
130 | ||
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131 | ||
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132 | OPERATION(13) <= '0' WHEN STATE_CIC_LFR = IDLE ELSE PROG(current_cmd)(10); --WE | |
|
133 | OPERATION(14) <= PROG(current_cmd)(12); -- SEL_DATA_A = data_b_reg | |
|
134 | OPERATION(15) <= PROG(current_cmd)(13); -- WRITE_ADDR_sel | |
|
135 | data_out_16_valid <= PROG(current_cmd)(11) WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE '0'; | |
|
136 | data_out_256_valid <= PROG(current_cmd)(11) WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0'; | |
|
137 | ||
|
138 | ||
|
139 | ||
|
140 | ||
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141 | ||
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142 | ||
|
143 | ||
|
144 | ||
|
145 | ||
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146 | ||
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147 | --OPERATION(1 DOWNTO 0) <= PROG(current_cmd)(1 DOWNTO 0); | |
|
148 | --OPERATION(2) <= '0' WHEN STATE_CIC_LFR = IDLE ELSE | |
|
149 | -- PROG(current_cmd)(2); | |
|
150 | --OPERATION(5 DOWNTO 3) <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3)) WHEN STATE_CIC_LFR = RUN_PROG_I AND current_cmd = 0 ELSE | |
|
151 | -- PROG(current_cmd)(5 DOWNTO 3); | |
|
152 | ||
|
153 | --OPERATION(8 DOWNTO 6) <= "000" WHEN STATE_CIC_LFR = IDLE ELSE | |
|
154 | -- PROG(current_cmd)(8 DOWNTO 6); | |
|
155 | --OPERATION(11 DOWNTO 9) <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3)); | |
|
156 | --OPERATION(13 DOWNTO 12) <= PROG(current_cmd)(10 DOWNTO 9); | |
|
157 | --OPERATION(14) <= PROG(current_cmd)(11) AND sample_16_odd WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE | |
|
158 | -- PROG(current_cmd)(11) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0'; | |
|
159 | ||
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160 | --OPERATION(15) <= PROG(current_cmd)(12); | |
|
161 | ||
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162 | --data_out_16_valid <= PROG(current_cmd)(13) WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE '0'; | |
|
163 | --data_out_256_valid <= PROG(current_cmd)(13) WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0'; | |
|
164 | ||
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165 | PROCESS (clk, rstn) | |
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166 | BEGIN | |
|
167 | IF rstn = '0' THEN | |
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168 | STATE_CIC_LFR <= IDLE; | |
|
169 | nb_data_receipt <= 0; | |
|
170 | current_channel <= 0; | |
|
171 | current_cmd <= 0; | |
|
172 | sample_16_odd <= '0'; | |
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173 | sample_256_odd <= '0'; | |
|
174 | ||
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175 | ELSIF clk'EVENT AND clk = '1' THEN | |
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176 | ||
|
177 | CASE STATE_CIC_LFR IS | |
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178 | WHEN IDLE => | |
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179 | IF data_in_valid = '1' THEN | |
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180 | STATE_CIC_LFR <= RUN_PROG_I; | |
|
181 | current_cmd <= PROG_START_I; | |
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182 | current_channel <= 0; | |
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183 | nb_data_receipt <= nb_data_receipt + 1; | |
|
184 | END IF; | |
|
185 | ||
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186 | WHEN RUN_PROG_I => | |
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187 | IF current_cmd = PROG_END_I THEN | |
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188 | IF nb_data_receipt MOD 16 = 15 THEN | |
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189 | STATE_CIC_LFR <= RUN_PROG_C16; | |
|
190 | current_cmd <= PROG_START_C16; | |
|
191 | IF current_channel = 0 THEN | |
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192 | sample_16_odd <= NOT sample_16_odd; | |
|
193 | END IF; | |
|
194 | ELSE | |
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195 | IF current_channel = 7 THEN | |
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196 | current_channel <= 0; | |
|
197 | STATE_CIC_LFR <= IDLE; | |
|
198 | ELSE | |
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199 | current_cmd <= PROG_START_I; | |
|
200 | current_channel <= current_channel + 1; | |
|
201 | END IF; | |
|
202 | END IF; | |
|
203 | ELSE | |
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204 | current_cmd <= current_cmd +1; | |
|
205 | END IF; | |
|
206 | ||
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207 | WHEN RUN_PROG_C16 => | |
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208 | IF current_cmd = PROG_END_C16 THEN | |
|
209 | IF nb_data_receipt MOD 256 = 255 AND current_channel < 6 THEN | |
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210 | STATE_CIC_LFR <= RUN_PROG_C256; | |
|
211 | current_cmd <= PROG_START_C256; | |
|
212 | IF current_channel = 0 THEN | |
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213 | sample_256_odd <= NOT sample_256_odd; | |
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214 | END IF; | |
|
215 | ELSE | |
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216 | IF current_channel = 7 THEN | |
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217 | current_channel <= 0; | |
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218 | STATE_CIC_LFR <= IDLE; | |
|
219 | ELSE | |
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220 | STATE_CIC_LFR <= RUN_PROG_I; | |
|
221 | current_cmd <= PROG_START_I; | |
|
222 | current_channel <= current_channel + 1; | |
|
223 | END IF; | |
|
224 | END IF; | |
|
225 | ELSE | |
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226 | current_cmd <= current_cmd +1; | |
|
227 | END IF; | |
|
228 | ||
|
229 | WHEN RUN_PROG_C256 => | |
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230 | IF current_cmd = PROG_END_C256 THEN | |
|
231 | -- data_out_256_valid <= '1'; | |
|
232 | -- IF current_channel = 5 THEN | |
|
233 | -- current_channel <= 0; | |
|
234 | -- STATE_CIC_LFR <= IDLE; | |
|
235 | -- ELSE | |
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236 | STATE_CIC_LFR <= RUN_PROG_I; | |
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237 | current_cmd <= PROG_START_I; | |
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238 | current_channel <= current_channel + 1; | |
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239 | -- END IF; | |
|
240 | ELSE | |
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241 | current_cmd <= current_cmd +1; | |
|
242 | END IF; | |
|
243 | ||
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244 | WHEN OTHERS => NULL; | |
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245 | END CASE; | |
|
246 | END IF; | |
|
247 | END PROCESS; | |
|
248 | ||
|
249 | END beh; |
@@ -0,0 +1,400 | |||
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1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Jean-christophe Pellion | |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
|
22 | ---------------------------------------------------------------------------- | |
|
23 | ||
|
24 | LIBRARY ieee; | |
|
25 | USE ieee.std_logic_1164.ALL; | |
|
26 | USE ieee.numeric_std.all; | |
|
27 | ||
|
28 | LIBRARY lpp; | |
|
29 | USE lpp.cic_pkg.ALL; | |
|
30 | USE lpp.data_type_pkg.ALL; | |
|
31 | USE lpp.iir_filter.ALL; | |
|
32 | ||
|
33 | LIBRARY techmap; | |
|
34 | USE techmap.gencomp.ALL; | |
|
35 | ||
|
36 | ENTITY cic_lfr_r2 IS | |
|
37 | GENERIC( | |
|
38 | tech : INTEGER := 0; | |
|
39 | use_RAM_nCEL : INTEGER := 0 -- 1 => RAM(tech) , 0 => RAM_CEL | |
|
40 | ); | |
|
41 | PORT ( | |
|
42 | clk : IN STD_LOGIC; | |
|
43 | rstn : IN STD_LOGIC; | |
|
44 | run : IN STD_LOGIC; | |
|
45 | ||
|
46 | param_r2 : IN STD_LOGIC; | |
|
47 | ||
|
48 | data_in : IN sample_vector(7 DOWNTO 0,15 DOWNTO 0); | |
|
49 | data_in_valid : IN STD_LOGIC; | |
|
50 | ||
|
51 | data_out_16 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0); | |
|
52 | data_out_16_valid : OUT STD_LOGIC; | |
|
53 | data_out_256 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0); | |
|
54 | data_out_256_valid : OUT STD_LOGIC | |
|
55 | ); | |
|
56 | ||
|
57 | END cic_lfr_r2; | |
|
58 | ||
|
59 | ARCHITECTURE beh OF cic_lfr_r2 IS | |
|
60 | -- | |
|
61 | SIGNAL sel_sample : STD_LOGIC_VECTOR(2 DOWNTO 0); | |
|
62 | SIGNAL sample_temp : sample_vector(5 DOWNTO 0,15 DOWNTO 0); | |
|
63 | SIGNAL sample : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
64 | -- | |
|
65 | SIGNAL sel_A : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
66 | SIGNAL data_A_temp : sample_vector(2 DOWNTO 0,15 DOWNTO 0); | |
|
67 | SIGNAL data_A : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
68 | -- | |
|
69 | SIGNAL ALU_OP : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
70 | SIGNAL data_B : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
71 | SIGNAL data_B_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
72 | SIGNAL data_out : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
73 | SIGNAL data_in_Carry : STD_LOGIC; | |
|
74 | SIGNAL data_out_Carry : STD_LOGIC; | |
|
75 | -- | |
|
76 | CONSTANT S_parameter : INTEGER := 3; | |
|
77 | SIGNAL carry_reg : STD_LOGIC_VECTOR(S_parameter-1 DOWNTO 0); | |
|
78 | SIGNAL CARRY_PUSH : STD_LOGIC; | |
|
79 | SIGNAL CARRY_POP : STD_LOGIC; | |
|
80 | -- | |
|
81 | ||
|
82 | SIGNAL OPERATION : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
83 | SIGNAL OPERATION_reg: STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
84 | SIGNAL OPERATION_reg2: STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
85 | ||
|
86 | ----------------------------------------------------------------------------- | |
|
87 | TYPE ARRAY_OF_ADDR IS ARRAY (7 DOWNTO 0) OF STD_LOGIC_VECTOR(8 DOWNTO 0); | |
|
88 | SIGNAL base_addr_INT : ARRAY_OF_ADDR; | |
|
89 | CONSTANT base_addr_delta : INTEGER := 40; | |
|
90 | SIGNAL addr_base_sel : STD_LOGIC_VECTOR(8 DOWNTO 0); | |
|
91 | SIGNAL addr_gen: STD_LOGIC_VECTOR(8 DOWNTO 0); | |
|
92 | SIGNAL addr_read: STD_LOGIC_VECTOR(8 DOWNTO 0); | |
|
93 | SIGNAL addr_write: STD_LOGIC_VECTOR(8 DOWNTO 0); | |
|
94 | SIGNAL addr_write_mux: STD_LOGIC_VECTOR(8 DOWNTO 0); | |
|
95 | SIGNAL addr_write_s: STD_LOGIC_VECTOR(8 DOWNTO 0); | |
|
96 | SIGNAL data_we: STD_LOGIC; | |
|
97 | SIGNAL data_we_s: STD_LOGIC; | |
|
98 | SIGNAL data_wen : STD_LOGIC; | |
|
99 | -- SIGNAL data_write : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
100 | -- SIGNAL data_read : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
101 | -- SIGNAL data_read_pre : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
102 | ----------------------------------------------------------------------------- | |
|
103 | SIGNAL sample_out_reg16 : sample_vector(8*2-1 DOWNTO 0, 15 DOWNTO 0); | |
|
104 | SIGNAL sample_out_reg256 : sample_vector(6*3-1 DOWNTO 0, 15 DOWNTO 0); | |
|
105 | SIGNAL sample_valid_reg16 : STD_LOGIC_VECTOR(8*2 DOWNTO 0); | |
|
106 | SIGNAL sample_valid_reg256: STD_LOGIC_VECTOR(6*3 DOWNTO 0); | |
|
107 | SIGNAL data_out_16_valid_s : STD_LOGIC; | |
|
108 | SIGNAL data_out_256_valid_s : STD_LOGIC; | |
|
109 | SIGNAL data_out_16_valid_s1 : STD_LOGIC; | |
|
110 | SIGNAL data_out_256_valid_s1 : STD_LOGIC; | |
|
111 | SIGNAL data_out_16_valid_s2 : STD_LOGIC; | |
|
112 | SIGNAL data_out_256_valid_s2 : STD_LOGIC; | |
|
113 | ----------------------------------------------------------------------------- | |
|
114 | SIGNAL sample_out_reg16_s : sample_vector(5 DOWNTO 0, 16*2-1 DOWNTO 0); | |
|
115 | SIGNAL sample_out_reg256_s : sample_vector(5 DOWNTO 0, 16*3-1 DOWNTO 0); | |
|
116 | ----------------------------------------------------------------------------- | |
|
117 | ||
|
118 | ||
|
119 | BEGIN | |
|
120 | ||
|
121 | ||
|
122 | PROCESS (clk, rstn) | |
|
123 | BEGIN -- PROCESS | |
|
124 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
125 | data_B_reg <= (OTHERS => '0'); | |
|
126 | OPERATION_reg <= (OTHERS => '0'); | |
|
127 | OPERATION_reg2 <= (OTHERS => '0'); | |
|
128 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
129 | OPERATION_reg <= OPERATION; | |
|
130 | OPERATION_reg2 <= OPERATION_reg; | |
|
131 | data_B_reg <= data_B; | |
|
132 | END IF; | |
|
133 | END PROCESS; | |
|
134 | ||
|
135 | ||
|
136 | ----------------------------------------------------------------------------- | |
|
137 | -- SEL_SAMPLE | |
|
138 | ----------------------------------------------------------------------------- | |
|
139 | sel_sample <= OPERATION_reg(2 DOWNTO 0); | |
|
140 | ||
|
141 | all_bit: FOR I IN 15 DOWNTO 0 GENERATE | |
|
142 | sample_temp(0,I) <= data_in(0,I) WHEN sel_sample(0) = '0' ELSE data_in(1,I); | |
|
143 | sample_temp(1,I) <= data_in(2,I) WHEN sel_sample(0) = '0' ELSE data_in(3,I); | |
|
144 | sample_temp(2,I) <= data_in(4,I) WHEN sel_sample(0) = '0' ELSE data_in(5,I); | |
|
145 | sample_temp(3,I) <= data_in(6,I) WHEN sel_sample(0) = '0' ELSE data_in(7,I); | |
|
146 | ||
|
147 | sample_temp(4,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE sample_temp(1,I); | |
|
148 | sample_temp(5,I) <= sample_temp(2,I) WHEN sel_sample(1) = '0' ELSE sample_temp(3,I); | |
|
149 | ||
|
150 | sample(I) <= sample_temp(4,I) WHEN sel_sample(2) = '0' ELSE sample_temp(5,I); | |
|
151 | END GENERATE all_bit; | |
|
152 | ||
|
153 | ----------------------------------------------------------------------------- | |
|
154 | -- SEL_DATA_IN_A | |
|
155 | ----------------------------------------------------------------------------- | |
|
156 | sel_A <= OPERATION_reg(4 DOWNTO 3); | |
|
157 | ||
|
158 | all_data_mux_A: FOR I IN 15 DOWNTO 0 GENERATE | |
|
159 | data_A_temp(0,I) <= sample(I) WHEN sel_A(0) = '0' ELSE data_out(I); | |
|
160 | data_A_temp(1,I) <= '0' WHEN sel_A(0) = '0' ELSE sample(15); | |
|
161 | data_A_temp(2,I) <= data_A_temp(0,I) WHEN sel_A(1) = '0' ELSE data_A_temp(1,I); | |
|
162 | data_A(I) <= data_A_temp(2,I) WHEN OPERATION_reg(14) = '0' ELSE data_B_reg(I); | |
|
163 | END GENERATE all_data_mux_A; | |
|
164 | ||
|
165 | ||
|
166 | ||
|
167 | ----------------------------------------------------------------------------- | |
|
168 | -- ALU | |
|
169 | ----------------------------------------------------------------------------- | |
|
170 | ALU_OP <= OPERATION_reg(6 DOWNTO 5); | |
|
171 | ||
|
172 | ALU: cic_lfr_add_sub | |
|
173 | PORT MAP ( | |
|
174 | clk => clk, | |
|
175 | rstn => rstn, | |
|
176 | run => run, | |
|
177 | ||
|
178 | OP => ALU_OP, | |
|
179 | ||
|
180 | data_in_A => data_A, | |
|
181 | data_in_B => data_B, | |
|
182 | data_in_Carry => data_in_Carry, | |
|
183 | ||
|
184 | data_out => data_out, | |
|
185 | data_out_Carry => data_out_Carry); | |
|
186 | ||
|
187 | ----------------------------------------------------------------------------- | |
|
188 | -- CARRY_MANAGER | |
|
189 | ----------------------------------------------------------------------------- | |
|
190 | data_in_Carry <= carry_reg(S_parameter-2) WHEN OPERATION_reg(7) = '0' ELSE carry_reg(S_parameter-1); | |
|
191 | ||
|
192 | -- CARRY_PUSH <= OPERATION_reg(7); | |
|
193 | -- CARRY_POP <= OPERATION_reg(6); | |
|
194 | ||
|
195 | PROCESS (clk, rstn) | |
|
196 | BEGIN -- PROCESS | |
|
197 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
198 | carry_reg <= (OTHERS => '0'); | |
|
199 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
200 | --IF CARRY_POP = '1' OR CARRY_PUSH = '1' THEN | |
|
201 | carry_reg(S_parameter-1 DOWNTO 1) <= carry_reg(S_parameter-2 DOWNTO 0); | |
|
202 | carry_reg(0) <= data_out_Carry; | |
|
203 | --END IF; | |
|
204 | END IF; | |
|
205 | END PROCESS; | |
|
206 | ||
|
207 | ----------------------------------------------------------------------------- | |
|
208 | -- MEMORY | |
|
209 | ----------------------------------------------------------------------------- | |
|
210 | all_bit_base_ADDR: FOR J IN 8 DOWNTO 0 GENERATE | |
|
211 | all_channel: FOR I IN 7 DOWNTO 0 GENERATE | |
|
212 | base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0'; | |
|
213 | END GENERATE all_channel; | |
|
214 | END GENERATE all_bit_base_ADDR; | |
|
215 | ||
|
216 | ||
|
217 | addr_base_sel <= base_addr_INT(to_integer(UNSIGNED(OPERATION(2 DOWNTO 0)))); | |
|
218 | ||
|
219 | cic_lfr_address_gen_1: cic_lfr_address_gen | |
|
220 | GENERIC MAP ( | |
|
221 | ADDR_SIZE => 9) | |
|
222 | PORT MAP ( | |
|
223 | clk => clk, | |
|
224 | rstn => rstn, | |
|
225 | run => run, | |
|
226 | ||
|
227 | addr_base => addr_base_sel, | |
|
228 | addr_init => OPERATION(8), | |
|
229 | addr_add_1 => OPERATION(9), | |
|
230 | addr => addr_gen); | |
|
231 | ||
|
232 | ||
|
233 | addr_read <= addr_gen WHEN OPERATION(12 DOWNTO 10) = "000" ELSE | |
|
234 | STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+2,9)) WHEN OPERATION(12 DOWNTO 10) = "001" ELSE | |
|
235 | STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+5,9)) WHEN OPERATION(12 DOWNTO 10) = "010" ELSE | |
|
236 | STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+8,9)) WHEN OPERATION(12 DOWNTO 10) = "011" ELSE | |
|
237 | STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen ))+6,9)) WHEN OPERATION(12 DOWNTO 10) = "100" ELSE | |
|
238 | STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen ))+15,9)); | |
|
239 | ||
|
240 | PROCESS (clk, rstn) | |
|
241 | BEGIN -- PROCESS | |
|
242 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
243 | addr_write <= (OTHERS => '0'); | |
|
244 | data_we <= '0'; | |
|
245 | addr_write_s <= (OTHERS => '0'); | |
|
246 | data_we_s <= '0'; | |
|
247 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
248 | addr_write_s <= addr_read; | |
|
249 | data_we_s <= OPERATION(13); | |
|
250 | IF OPERATION_reg(15) = '0' THEN | |
|
251 | addr_write <= addr_write_s; | |
|
252 | ELSE | |
|
253 | addr_write <= addr_read; | |
|
254 | END IF; | |
|
255 | data_we <= data_we_s; | |
|
256 | END IF; | |
|
257 | END PROCESS; | |
|
258 | ||
|
259 | memCEL : IF use_RAM_nCEL = 0 GENERATE | |
|
260 | data_wen <= NOT data_we; | |
|
261 | RAMblk : RAM_CEL | |
|
262 | GENERIC MAP(16, 9) | |
|
263 | PORT MAP( | |
|
264 | WD => data_out, | |
|
265 | RD => data_B, | |
|
266 | WEN => data_wen, | |
|
267 | REN => '0', | |
|
268 | WADDR => addr_write, | |
|
269 | RADDR => addr_read, | |
|
270 | RWCLK => clk, | |
|
271 | RESET => rstn | |
|
272 | ) ; | |
|
273 | END GENERATE; | |
|
274 | ||
|
275 | memRAM : IF use_RAM_nCEL = 1 GENERATE | |
|
276 | SRAM : syncram_2p | |
|
277 | GENERIC MAP(tech, 9, 16) | |
|
278 | PORT MAP(clk, '1', addr_read, data_B, | |
|
279 | clk, data_we, addr_write, data_out); | |
|
280 | END GENERATE; | |
|
281 | ||
|
282 | ----------------------------------------------------------------------------- | |
|
283 | -- CONTROL | |
|
284 | ----------------------------------------------------------------------------- | |
|
285 | cic_lfr_control_1: cic_lfr_control_r2 | |
|
286 | PORT MAP ( | |
|
287 | clk => clk, | |
|
288 | rstn => rstn, | |
|
289 | run => run, | |
|
290 | data_in_valid => data_in_valid, | |
|
291 | data_out_16_valid => data_out_16_valid_s, | |
|
292 | data_out_256_valid => data_out_256_valid_s, | |
|
293 | OPERATION => OPERATION); | |
|
294 | ||
|
295 | ----------------------------------------------------------------------------- | |
|
296 | PROCESS (clk, rstn) | |
|
297 | BEGIN -- PROCESS | |
|
298 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
299 | data_out_16_valid_s1 <= '0'; | |
|
300 | data_out_256_valid_s1 <= '0'; | |
|
301 | data_out_16_valid_s2 <= '0'; | |
|
302 | data_out_256_valid_s2 <= '0'; | |
|
303 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
304 | data_out_16_valid_s1 <= data_out_16_valid_s; | |
|
305 | data_out_256_valid_s1 <= data_out_256_valid_s; | |
|
306 | data_out_16_valid_s2 <= data_out_16_valid_s1; | |
|
307 | data_out_256_valid_s2 <= data_out_256_valid_s1; | |
|
308 | END IF; | |
|
309 | END PROCESS; | |
|
310 | ||
|
311 | PROCESS (clk, rstn) | |
|
312 | BEGIN -- PROCESS | |
|
313 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
314 | sample_valid_reg16 <= "00000" & "000000" & "000001"; | |
|
315 | sample_valid_reg256 <= '0' & "000000" & "000000" & "000001"; | |
|
316 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
317 | IF run = '0' THEN | |
|
318 | sample_valid_reg16 <= "00000" & "000000" & "000001"; | |
|
319 | sample_valid_reg256 <= '0' & "000000" & "000000" & "000001"; | |
|
320 | ELSE | |
|
321 | IF data_out_16_valid_s2 = '1' OR sample_valid_reg16(8*2) = '1' THEN | |
|
322 | sample_valid_reg16 <= sample_valid_reg16(8*2-1 DOWNTO 0) & sample_valid_reg16(8*2); | |
|
323 | END IF; | |
|
324 | IF data_out_256_valid_s2 = '1' OR sample_valid_reg256(6*3) = '1' THEN | |
|
325 | sample_valid_reg256 <= sample_valid_reg256(6*3-1 DOWNTO 0) & sample_valid_reg256(6*3); | |
|
326 | END IF; | |
|
327 | END IF; | |
|
328 | END IF; | |
|
329 | END PROCESS; | |
|
330 | ||
|
331 | data_out_16_valid <= sample_valid_reg16(8*2); | |
|
332 | data_out_256_valid <= sample_valid_reg256(6*3); | |
|
333 | ||
|
334 | ----------------------------------------------------------------------------- | |
|
335 | ||
|
336 | all_bits: FOR J IN 15 DOWNTO 0 GENERATE | |
|
337 | all_channel_out16: FOR I IN 8*2-1 DOWNTO 0 GENERATE | |
|
338 | PROCESS (clk, rstn) | |
|
339 | BEGIN -- PROCESS | |
|
340 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
341 | sample_out_reg16(I,J) <= '0'; | |
|
342 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
343 | IF run = '0' THEN | |
|
344 | sample_out_reg16(I,J) <= '0'; | |
|
345 | ELSE | |
|
346 | IF sample_valid_reg16(I) = '1' AND data_out_16_valid_s2 = '1' THEN | |
|
347 | sample_out_reg16(I,J) <= data_out(J); | |
|
348 | END IF; | |
|
349 | END IF; | |
|
350 | END IF; | |
|
351 | END PROCESS; | |
|
352 | END GENERATE all_channel_out16; | |
|
353 | ||
|
354 | all_channel_out256: FOR I IN 6*3-1 DOWNTO 0 GENERATE | |
|
355 | PROCESS (clk, rstn) | |
|
356 | BEGIN -- PROCESS | |
|
357 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
358 | sample_out_reg256(I,J) <= '0'; | |
|
359 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
360 | IF run = '0' THEN | |
|
361 | sample_out_reg256(I,J) <= '0'; | |
|
362 | ELSE | |
|
363 | IF sample_valid_reg256(I) = '1' AND data_out_256_valid_s2 = '1' THEN | |
|
364 | sample_out_reg256(I,J) <= data_out(J); | |
|
365 | END IF; | |
|
366 | END IF; | |
|
367 | END IF; | |
|
368 | END PROCESS; | |
|
369 | END GENERATE all_channel_out256; | |
|
370 | END GENERATE all_bits; | |
|
371 | ||
|
372 | ||
|
373 | all_bits_16: FOR J IN 15 DOWNTO 0 GENERATE | |
|
374 | all_reg_16: FOR K IN 1 DOWNTO 0 GENERATE | |
|
375 | sample_out_reg16_s(0,J+(K*16)) <= sample_out_reg16(2*0+K,J); | |
|
376 | sample_out_reg16_s(1,J+(K*16)) <= sample_out_reg16(2*1+K,J) WHEN param_r2 = '1' ELSE sample_out_reg16(2*6+K,J); | |
|
377 | sample_out_reg16_s(2,J+(K*16)) <= sample_out_reg16(2*2+K,J) WHEN param_r2 = '1' ELSE sample_out_reg16(2*7+K,J); | |
|
378 | sample_out_reg16_s(3,J+(K*16)) <= sample_out_reg16(2*3+K,J); | |
|
379 | sample_out_reg16_s(4,J+(K*16)) <= sample_out_reg16(2*4+K,J); | |
|
380 | sample_out_reg16_s(5,J+(K*16)) <= sample_out_reg16(2*5+K,J); | |
|
381 | END GENERATE all_reg_16; | |
|
382 | END GENERATE all_bits_16; | |
|
383 | ||
|
384 | all_channel_out_256: FOR I IN 5 DOWNTO 0 GENERATE | |
|
385 | all_bits_256: FOR J IN 15 DOWNTO 0 GENERATE | |
|
386 | all_reg_256: FOR K IN 2 DOWNTO 0 GENERATE | |
|
387 | sample_out_reg256_s(I,J+(K*16)) <= sample_out_reg256(3*I+K,J); | |
|
388 | END GENERATE all_reg_256; | |
|
389 | END GENERATE all_bits_256; | |
|
390 | END GENERATE all_channel_out_256; | |
|
391 | ||
|
392 | all_channel_out_v: FOR I IN 5 DOWNTO 0 GENERATE | |
|
393 | all_bits: FOR J IN 15 DOWNTO 0 GENERATE | |
|
394 | data_out_256(I,J) <= sample_out_reg256_s(I,J+16*2-32+27); | |
|
395 | data_out_16(I,J) <= sample_out_reg16_s (I,J+16 -16+15); | |
|
396 | END GENERATE all_bits; | |
|
397 | END GENERATE all_channel_out_v; | |
|
398 | ||
|
399 | END beh; | |
|
400 |
@@ -1,733 +1,733 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------- |
|
22 | 22 | LIBRARY IEEE; |
|
23 | 23 | USE IEEE.numeric_std.ALL; |
|
24 | 24 | USE IEEE.std_logic_1164.ALL; |
|
25 | 25 | LIBRARY grlib; |
|
26 | 26 | USE grlib.amba.ALL; |
|
27 | 27 | USE grlib.stdlib.ALL; |
|
28 | 28 | LIBRARY techmap; |
|
29 | 29 | USE techmap.gencomp.ALL; |
|
30 | 30 | LIBRARY gaisler; |
|
31 | 31 | USE gaisler.memctrl.ALL; |
|
32 | 32 | USE gaisler.leon3.ALL; |
|
33 | 33 | USE gaisler.uart.ALL; |
|
34 | 34 | USE gaisler.misc.ALL; |
|
35 | 35 | USE gaisler.spacewire.ALL; |
|
36 | 36 | LIBRARY esa; |
|
37 | 37 | USE esa.memoryctrl.ALL; |
|
38 | 38 | LIBRARY lpp; |
|
39 | 39 | USE lpp.lpp_memory.ALL; |
|
40 | 40 | USE lpp.lpp_ad_conv.ALL; |
|
41 | 41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
|
42 | 42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
|
43 | 43 | USE lpp.iir_filter.ALL; |
|
44 | 44 | USE lpp.general_purpose.ALL; |
|
45 | 45 | USE lpp.lpp_lfr_management.ALL; |
|
46 | 46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
|
47 | 47 | |
|
48 | 48 | ENTITY MINI_LFR_top IS |
|
49 | 49 | |
|
50 | 50 | PORT ( |
|
51 | 51 | clk_50 : IN STD_LOGIC; |
|
52 | 52 | clk_49 : IN STD_LOGIC; |
|
53 | 53 | reset : IN STD_LOGIC; |
|
54 | 54 | --BPs |
|
55 | 55 | BP0 : IN STD_LOGIC; |
|
56 | 56 | BP1 : IN STD_LOGIC; |
|
57 | 57 | --LEDs |
|
58 | 58 | LED0 : OUT STD_LOGIC; |
|
59 | 59 | LED1 : OUT STD_LOGIC; |
|
60 | 60 | LED2 : OUT STD_LOGIC; |
|
61 | 61 | --UARTs |
|
62 | 62 | TXD1 : IN STD_LOGIC; |
|
63 | 63 | RXD1 : OUT STD_LOGIC; |
|
64 | 64 | nCTS1 : OUT STD_LOGIC; |
|
65 | 65 | nRTS1 : IN STD_LOGIC; |
|
66 | 66 | |
|
67 | 67 | TXD2 : IN STD_LOGIC; |
|
68 | 68 | RXD2 : OUT STD_LOGIC; |
|
69 | 69 | nCTS2 : OUT STD_LOGIC; |
|
70 | 70 | nDTR2 : IN STD_LOGIC; |
|
71 | 71 | nRTS2 : IN STD_LOGIC; |
|
72 | 72 | nDCD2 : OUT STD_LOGIC; |
|
73 | 73 | |
|
74 | 74 | --EXT CONNECTOR |
|
75 | 75 | IO0 : INOUT STD_LOGIC; |
|
76 | 76 | IO1 : INOUT STD_LOGIC; |
|
77 | 77 | IO2 : INOUT STD_LOGIC; |
|
78 | 78 | IO3 : INOUT STD_LOGIC; |
|
79 | 79 | IO4 : INOUT STD_LOGIC; |
|
80 | 80 | IO5 : INOUT STD_LOGIC; |
|
81 | 81 | IO6 : INOUT STD_LOGIC; |
|
82 | 82 | IO7 : INOUT STD_LOGIC; |
|
83 | 83 | IO8 : INOUT STD_LOGIC; |
|
84 | 84 | IO9 : INOUT STD_LOGIC; |
|
85 | 85 | IO10 : INOUT STD_LOGIC; |
|
86 | 86 | IO11 : INOUT STD_LOGIC; |
|
87 | 87 | |
|
88 | 88 | --SPACE WIRE |
|
89 | 89 | SPW_EN : OUT STD_LOGIC; -- 0 => off |
|
90 | 90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK |
|
91 | 91 | SPW_NOM_SIN : IN STD_LOGIC; |
|
92 | 92 | SPW_NOM_DOUT : OUT STD_LOGIC; |
|
93 | 93 | SPW_NOM_SOUT : OUT STD_LOGIC; |
|
94 | 94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK |
|
95 | 95 | SPW_RED_SIN : IN STD_LOGIC; |
|
96 | 96 | SPW_RED_DOUT : OUT STD_LOGIC; |
|
97 | 97 | SPW_RED_SOUT : OUT STD_LOGIC; |
|
98 | 98 | -- MINI LFR ADC INPUTS |
|
99 | 99 | ADC_nCS : OUT STD_LOGIC; |
|
100 | 100 | ADC_CLK : OUT STD_LOGIC; |
|
101 | 101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
102 | 102 | |
|
103 | 103 | -- SRAM |
|
104 | 104 | SRAM_nWE : OUT STD_LOGIC; |
|
105 | 105 | SRAM_CE : OUT STD_LOGIC; |
|
106 | 106 | SRAM_nOE : OUT STD_LOGIC; |
|
107 | 107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
108 | 108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
|
109 | 109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
110 | 110 | ); |
|
111 | 111 | |
|
112 | 112 | END MINI_LFR_top; |
|
113 | 113 | |
|
114 | 114 | |
|
115 | 115 | ARCHITECTURE beh OF MINI_LFR_top IS |
|
116 | 116 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
|
117 | 117 | SIGNAL clk_25 : STD_LOGIC := '0'; |
|
118 | 118 | SIGNAL clk_24 : STD_LOGIC := '0'; |
|
119 | 119 | ----------------------------------------------------------------------------- |
|
120 | 120 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
121 | 121 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
122 | 122 | -- |
|
123 | 123 | SIGNAL errorn : STD_LOGIC; |
|
124 | 124 | -- UART AHB --------------------------------------------------------------- |
|
125 | 125 | -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data |
|
126 | 126 | -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data |
|
127 | 127 | |
|
128 | 128 | -- UART APB --------------------------------------------------------------- |
|
129 | 129 | -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data |
|
130 | 130 | -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data |
|
131 | 131 | -- |
|
132 | 132 | SIGNAL I00_s : STD_LOGIC; |
|
133 | 133 | |
|
134 | 134 | -- CONSTANTS |
|
135 | 135 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
|
136 | 136 | -- |
|
137 | 137 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
|
138 | 138 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
|
139 | 139 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
|
140 | 140 | |
|
141 | 141 | SIGNAL apbi_ext : apb_slv_in_type; |
|
142 | 142 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none); |
|
143 | 143 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
|
144 | 144 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none); |
|
145 | 145 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
|
146 | 146 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none); |
|
147 | 147 | |
|
148 | 148 | -- Spacewire signals |
|
149 | 149 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
150 | 150 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
151 | 151 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
152 | 152 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
|
153 | 153 | SIGNAL spw_rxclkn : STD_ULOGIC; |
|
154 | 154 | SIGNAL spw_clk : STD_LOGIC; |
|
155 | 155 | SIGNAL swni : grspw_in_type; |
|
156 | 156 | SIGNAL swno : grspw_out_type; |
|
157 | 157 | -- SIGNAL clkmn : STD_ULOGIC; |
|
158 | 158 | -- SIGNAL txclk : STD_ULOGIC; |
|
159 | 159 | |
|
160 | 160 | --GPIO |
|
161 | 161 | SIGNAL gpioi : gpio_in_type; |
|
162 | 162 | SIGNAL gpioo : gpio_out_type; |
|
163 | 163 | |
|
164 | 164 | -- AD Converter ADS7886 |
|
165 | 165 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
|
166 | 166 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
|
167 | 167 | SIGNAL sample_val : STD_LOGIC; |
|
168 | 168 | SIGNAL ADC_nCS_sig : STD_LOGIC; |
|
169 | 169 | SIGNAL ADC_CLK_sig : STD_LOGIC; |
|
170 | 170 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
171 | 171 | |
|
172 | 172 | SIGNAL bias_fail_sw_sig : STD_LOGIC; |
|
173 | 173 | |
|
174 | 174 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
175 | 175 | SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
176 | 176 | SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
177 | 177 | ----------------------------------------------------------------------------- |
|
178 | 178 | |
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179 | 179 | SIGNAL LFR_soft_rstn : STD_LOGIC; |
|
180 | 180 | SIGNAL LFR_rstn : STD_LOGIC; |
|
181 | 181 | |
|
182 | 182 | |
|
183 | 183 | SIGNAL rstn_25 : STD_LOGIC; |
|
184 | 184 | SIGNAL rstn_25_d1 : STD_LOGIC; |
|
185 | 185 | SIGNAL rstn_25_d2 : STD_LOGIC; |
|
186 | 186 | SIGNAL rstn_25_d3 : STD_LOGIC; |
|
187 | 187 | |
|
188 | 188 | SIGNAL rstn_50 : STD_LOGIC; |
|
189 | 189 | SIGNAL rstn_50_d1 : STD_LOGIC; |
|
190 | 190 | SIGNAL rstn_50_d2 : STD_LOGIC; |
|
191 | 191 | SIGNAL rstn_50_d3 : STD_LOGIC; |
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192 | 192 | |
|
193 | 193 | SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
194 | 194 | SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
195 | 195 | |
|
196 | 196 | -- |
|
197 | 197 | SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
198 | 198 | |
|
199 | 199 | -- |
|
200 | 200 | SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
201 | 201 | SIGNAL HK_SEL : STD_LOGIC_VECTOR( 1 DOWNTO 0); |
|
202 | 202 | |
|
203 | 203 | BEGIN -- beh |
|
204 | 204 | |
|
205 | 205 | ----------------------------------------------------------------------------- |
|
206 | 206 | -- CLK |
|
207 | 207 | ----------------------------------------------------------------------------- |
|
208 | 208 | |
|
209 | 209 | --PROCESS(clk_50) |
|
210 | 210 | --BEGIN |
|
211 | 211 | -- IF clk_50'EVENT AND clk_50 = '1' THEN |
|
212 | 212 | -- clk_50_s <= NOT clk_50_s; |
|
213 | 213 | -- END IF; |
|
214 | 214 | --END PROCESS; |
|
215 | 215 | |
|
216 | 216 | --PROCESS(clk_50_s) |
|
217 | 217 | --BEGIN |
|
218 | 218 | -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
|
219 | 219 | -- clk_25 <= NOT clk_25; |
|
220 | 220 | -- END IF; |
|
221 | 221 | --END PROCESS; |
|
222 | 222 | |
|
223 | 223 | --PROCESS(clk_49) |
|
224 | 224 | --BEGIN |
|
225 | 225 | -- IF clk_49'EVENT AND clk_49 = '1' THEN |
|
226 | 226 | -- clk_24 <= NOT clk_24; |
|
227 | 227 | -- END IF; |
|
228 | 228 | --END PROCESS; |
|
229 | 229 | |
|
230 | 230 | --PROCESS(clk_25) |
|
231 | 231 | --BEGIN |
|
232 | 232 | -- IF clk_25'EVENT AND clk_25 = '1' THEN |
|
233 | 233 | -- rstn_25 <= reset; |
|
234 | 234 | -- END IF; |
|
235 | 235 | --END PROCESS; |
|
236 | 236 | |
|
237 | 237 | PROCESS (clk_50, reset) |
|
238 | 238 | BEGIN -- PROCESS |
|
239 | 239 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
240 | 240 | clk_50_s <= '0'; |
|
241 | 241 | rstn_50 <= '0'; |
|
242 | 242 | rstn_50_d1 <= '0'; |
|
243 | 243 | rstn_50_d2 <= '0'; |
|
244 | 244 | rstn_50_d3 <= '0'; |
|
245 | 245 | |
|
246 | 246 | ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge |
|
247 | 247 | clk_50_s <= NOT clk_50_s; |
|
248 | 248 | rstn_50_d1 <= '1'; |
|
249 | 249 | rstn_50_d2 <= rstn_50_d1; |
|
250 | 250 | rstn_50_d3 <= rstn_50_d2; |
|
251 | 251 | rstn_50 <= rstn_50_d3; |
|
252 | 252 | END IF; |
|
253 | 253 | END PROCESS; |
|
254 | 254 | |
|
255 | 255 | PROCESS (clk_50_s, rstn_50) |
|
256 | 256 | BEGIN -- PROCESS |
|
257 | 257 | IF rstn_50 = '0' THEN -- asynchronous reset (active low) |
|
258 | 258 | clk_25 <= '0'; |
|
259 | 259 | rstn_25 <= '0'; |
|
260 | 260 | rstn_25_d1 <= '0'; |
|
261 | 261 | rstn_25_d2 <= '0'; |
|
262 | 262 | rstn_25_d3 <= '0'; |
|
263 | 263 | ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge |
|
264 | 264 | clk_25 <= NOT clk_25; |
|
265 | 265 | rstn_25_d1 <= '1'; |
|
266 | 266 | rstn_25_d2 <= rstn_25_d1; |
|
267 | 267 | rstn_25_d3 <= rstn_25_d2; |
|
268 | 268 | rstn_25 <= rstn_25_d3; |
|
269 | 269 | END IF; |
|
270 | 270 | END PROCESS; |
|
271 | 271 | |
|
272 | 272 | PROCESS (clk_49, reset) |
|
273 | 273 | BEGIN -- PROCESS |
|
274 | 274 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
275 | 275 | clk_24 <= '0'; |
|
276 | 276 | ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge |
|
277 | 277 | clk_24 <= NOT clk_24; |
|
278 | 278 | END IF; |
|
279 | 279 | END PROCESS; |
|
280 | 280 | |
|
281 | 281 | ----------------------------------------------------------------------------- |
|
282 | 282 | |
|
283 | 283 | PROCESS (clk_25, rstn_25) |
|
284 | 284 | BEGIN -- PROCESS |
|
285 | 285 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) |
|
286 | 286 | LED0 <= '0'; |
|
287 | 287 | LED1 <= '0'; |
|
288 | 288 | LED2 <= '0'; |
|
289 | 289 | --IO1 <= '0'; |
|
290 | 290 | --IO2 <= '1'; |
|
291 | 291 | --IO3 <= '0'; |
|
292 | 292 | --IO4 <= '0'; |
|
293 | 293 | --IO5 <= '0'; |
|
294 | 294 | --IO6 <= '0'; |
|
295 | 295 | --IO7 <= '0'; |
|
296 | 296 | --IO8 <= '0'; |
|
297 | 297 | --IO9 <= '0'; |
|
298 | 298 | --IO10 <= '0'; |
|
299 | 299 | --IO11 <= '0'; |
|
300 | 300 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
|
301 | 301 | LED0 <= '0'; |
|
302 | 302 | LED1 <= '1'; |
|
303 | 303 | LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
|
304 | 304 | --IO1 <= '1'; |
|
305 | 305 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; |
|
306 | 306 | --IO3 <= ADC_SDO(0); |
|
307 | 307 | --IO4 <= ADC_SDO(1); |
|
308 | 308 | --IO5 <= ADC_SDO(2); |
|
309 | 309 | --IO6 <= ADC_SDO(3); |
|
310 | 310 | --IO7 <= ADC_SDO(4); |
|
311 | 311 | --IO8 <= ADC_SDO(5); |
|
312 | 312 | --IO9 <= ADC_SDO(6); |
|
313 | 313 | --IO10 <= ADC_SDO(7); |
|
314 | 314 | --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
|
315 | 315 | END IF; |
|
316 | 316 | END PROCESS; |
|
317 | 317 | |
|
318 | 318 | PROCESS (clk_24, rstn_25) |
|
319 | 319 | BEGIN -- PROCESS |
|
320 | 320 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) |
|
321 | 321 | I00_s <= '0'; |
|
322 | 322 | ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge |
|
323 | 323 | I00_s <= NOT I00_s; |
|
324 | 324 | END IF; |
|
325 | 325 | END PROCESS; |
|
326 | 326 | -- IO0 <= I00_s; |
|
327 | 327 | |
|
328 | 328 | --UARTs |
|
329 | 329 | nCTS1 <= '1'; |
|
330 | 330 | nCTS2 <= '1'; |
|
331 | 331 | nDCD2 <= '1'; |
|
332 | 332 | |
|
333 | 333 | --EXT CONNECTOR |
|
334 | 334 | |
|
335 | 335 | --SPACE WIRE |
|
336 | 336 | |
|
337 | 337 | leon3_soc_1 : leon3_soc |
|
338 | 338 | GENERIC MAP ( |
|
339 | 339 | fabtech => apa3e, |
|
340 | 340 | memtech => apa3e, |
|
341 | 341 | padtech => inferred, |
|
342 | 342 | clktech => inferred, |
|
343 | 343 | disas => 0, |
|
344 | 344 | dbguart => 0, |
|
345 | 345 | pclow => 2, |
|
346 | 346 | clk_freq => 25000, |
|
347 | 347 | NB_CPU => 1, |
|
348 | 348 | ENABLE_FPU => 1, |
|
349 | 349 | FPU_NETLIST => 0, |
|
350 | 350 | ENABLE_DSU => 1, |
|
351 | 351 | ENABLE_AHB_UART => 1, |
|
352 | 352 | ENABLE_APB_UART => 1, |
|
353 | 353 | ENABLE_IRQMP => 1, |
|
354 | 354 | ENABLE_GPT => 1, |
|
355 | 355 | NB_AHB_MASTER => NB_AHB_MASTER, |
|
356 | 356 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
|
357 | 357 | NB_APB_SLAVE => NB_APB_SLAVE, |
|
358 | 358 | ADDRESS_SIZE => 20, |
|
359 | 359 | USES_IAP_MEMCTRLR => 0) |
|
360 | 360 | PORT MAP ( |
|
361 | 361 | clk => clk_25, |
|
362 | 362 | reset => rstn_25, |
|
363 | 363 | errorn => errorn, |
|
364 | 364 | ahbrxd => TXD1, |
|
365 | 365 | ahbtxd => RXD1, |
|
366 | 366 | urxd1 => TXD2, |
|
367 | 367 | utxd1 => RXD2, |
|
368 | 368 | address => SRAM_A, |
|
369 | 369 | data => SRAM_DQ, |
|
370 | 370 | nSRAM_BE0 => SRAM_nBE(0), |
|
371 | 371 | nSRAM_BE1 => SRAM_nBE(1), |
|
372 | 372 | nSRAM_BE2 => SRAM_nBE(2), |
|
373 | 373 | nSRAM_BE3 => SRAM_nBE(3), |
|
374 | 374 | nSRAM_WE => SRAM_nWE, |
|
375 | 375 | nSRAM_CE => SRAM_CE_s, |
|
376 | 376 | nSRAM_OE => SRAM_nOE, |
|
377 | 377 | nSRAM_READY => '0', |
|
378 | 378 | SRAM_MBE => OPEN, |
|
379 | 379 | apbi_ext => apbi_ext, |
|
380 | 380 | apbo_ext => apbo_ext, |
|
381 | 381 | ahbi_s_ext => ahbi_s_ext, |
|
382 | 382 | ahbo_s_ext => ahbo_s_ext, |
|
383 | 383 | ahbi_m_ext => ahbi_m_ext, |
|
384 | 384 | ahbo_m_ext => ahbo_m_ext); |
|
385 | 385 | |
|
386 | 386 | SRAM_CE <= SRAM_CE_s(0); |
|
387 | 387 | ------------------------------------------------------------------------------- |
|
388 | 388 | -- APB_LFR_MANAGEMENT --------------------------------------------------------- |
|
389 | 389 | ------------------------------------------------------------------------------- |
|
390 | 390 | apb_lfr_management_1 : apb_lfr_management |
|
391 | 391 | GENERIC MAP ( |
|
392 | 392 | pindex => 6, |
|
393 | 393 | paddr => 6, |
|
394 | 394 | pmask => 16#fff#, |
|
395 | 395 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 |
|
396 | 396 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
|
397 | 397 | PORT MAP ( |
|
398 | 398 | clk25MHz => clk_25, |
|
399 | 399 | clk24_576MHz => clk_24, -- 49.152MHz/2 |
|
400 | 400 | resetn => rstn_25, |
|
401 | 401 | grspw_tick => swno.tickout, |
|
402 | 402 | apbi => apbi_ext, |
|
403 | 403 | apbo => apbo_ext(6), |
|
404 | 404 | HK_sample => sample_hk, |
|
405 | 405 | HK_val => sample_val, |
|
406 | 406 | HK_sel => HK_SEL, |
|
407 | 407 | coarse_time => coarse_time, |
|
408 | 408 | fine_time => fine_time, |
|
409 | 409 | LFR_soft_rstn => LFR_soft_rstn |
|
410 | 410 | ); |
|
411 | 411 | |
|
412 | 412 | ----------------------------------------------------------------------- |
|
413 | 413 | --- SpaceWire -------------------------------------------------------- |
|
414 | 414 | ----------------------------------------------------------------------- |
|
415 | 415 | |
|
416 | 416 | SPW_EN <= '1'; |
|
417 | 417 | |
|
418 | 418 | spw_clk <= clk_50_s; |
|
419 | 419 | spw_rxtxclk <= spw_clk; |
|
420 | 420 | spw_rxclkn <= NOT spw_rxtxclk; |
|
421 | 421 | |
|
422 | 422 | -- PADS for SPW1 |
|
423 | 423 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
|
424 | 424 | PORT MAP (SPW_NOM_DIN, dtmp(0)); |
|
425 | 425 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
|
426 | 426 | PORT MAP (SPW_NOM_SIN, stmp(0)); |
|
427 | 427 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
428 | 428 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); |
|
429 | 429 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
430 | 430 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); |
|
431 | 431 | -- PADS FOR SPW2 |
|
432 | 432 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
433 | 433 | PORT MAP (SPW_RED_SIN, dtmp(1)); |
|
434 | 434 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
435 | 435 | PORT MAP (SPW_RED_DIN, stmp(1)); |
|
436 | 436 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
437 | 437 | PORT MAP (SPW_RED_DOUT, swno.d(1)); |
|
438 | 438 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
439 | 439 | PORT MAP (SPW_RED_SOUT, swno.s(1)); |
|
440 | 440 | |
|
441 | 441 | -- GRSPW PHY |
|
442 | 442 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
|
443 | 443 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
|
444 | 444 | spw_phy0 : grspw_phy |
|
445 | 445 | GENERIC MAP( |
|
446 | 446 | tech => apa3e, |
|
447 | 447 | rxclkbuftype => 1, |
|
448 | 448 | scantest => 0) |
|
449 | 449 | PORT MAP( |
|
450 | 450 | rxrst => swno.rxrst, |
|
451 | 451 | di => dtmp(j), |
|
452 | 452 | si => stmp(j), |
|
453 | 453 | rxclko => spw_rxclk(j), |
|
454 | 454 | do => swni.d(j), |
|
455 | 455 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
|
456 | 456 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
457 | 457 | END GENERATE spw_inputloop; |
|
458 | 458 | |
|
459 | 459 | swni.rmapnodeaddr <= (OTHERS => '0'); |
|
460 | 460 | |
|
461 | 461 | -- SPW core |
|
462 | 462 | sw0 : grspwm GENERIC MAP( |
|
463 | 463 | tech => apa3e, |
|
464 | 464 | hindex => 1, |
|
465 | 465 | pindex => 5, |
|
466 | 466 | paddr => 5, |
|
467 | 467 | pirq => 11, |
|
468 | 468 | sysfreq => 25000, -- CPU_FREQ |
|
469 | 469 | rmap => 1, |
|
470 | 470 | rmapcrc => 1, |
|
471 | 471 | fifosize1 => 16, |
|
472 | 472 | fifosize2 => 16, |
|
473 | 473 | rxclkbuftype => 1, |
|
474 | 474 | rxunaligned => 0, |
|
475 | 475 | rmapbufs => 4, |
|
476 | 476 | ft => 0, |
|
477 | 477 | netlist => 0, |
|
478 | 478 | ports => 2, |
|
479 | 479 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
|
480 | 480 | memtech => apa3e, |
|
481 | 481 | destkey => 2, |
|
482 | 482 | spwcore => 1 |
|
483 | 483 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
|
484 | 484 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
|
485 | 485 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
|
486 | 486 | ) |
|
487 | 487 | PORT MAP(rstn_25, clk_25, spw_rxclk(0), |
|
488 | 488 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
|
489 | 489 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
|
490 | 490 | swni, swno); |
|
491 | 491 | |
|
492 | 492 | swni.tickin <= '0'; |
|
493 | 493 | swni.rmapen <= '1'; |
|
494 | 494 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz |
|
495 | 495 | swni.tickinraw <= '0'; |
|
496 | 496 | swni.timein <= (OTHERS => '0'); |
|
497 | 497 | swni.dcrstval <= (OTHERS => '0'); |
|
498 | 498 | swni.timerrstval <= (OTHERS => '0'); |
|
499 | 499 | |
|
500 | 500 | ------------------------------------------------------------------------------- |
|
501 | 501 | -- LFR ------------------------------------------------------------------------ |
|
502 | 502 | ------------------------------------------------------------------------------- |
|
503 | 503 | |
|
504 | 504 | |
|
505 | 505 | LFR_rstn <= LFR_soft_rstn AND rstn_25; |
|
506 | 506 | --LFR_rstn <= rstn_25; |
|
507 | 507 | |
|
508 | 508 | lpp_lfr_1 : lpp_lfr |
|
509 | 509 | GENERIC MAP ( |
|
510 | 510 | Mem_use => use_RAM, |
|
511 | 511 | nb_data_by_buffer_size => 32, |
|
512 | 512 | nb_snapshot_param_size => 32, |
|
513 | 513 | delta_vector_size => 32, |
|
514 | 514 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
515 | 515 | pindex => 15, |
|
516 | 516 | paddr => 15, |
|
517 | 517 | pmask => 16#fff#, |
|
518 | 518 | pirq_ms => 6, |
|
519 | 519 | pirq_wfp => 14, |
|
520 | 520 | hindex => 2, |
|
521 |
top_lfr_version => X"00013 |
|
|
521 | top_lfr_version => X"000138") -- aa.bb.cc version | |
|
522 | 522 | PORT MAP ( |
|
523 | 523 | clk => clk_25, |
|
524 | 524 | rstn => LFR_rstn, |
|
525 | 525 | sample_B => sample_s(2 DOWNTO 0), |
|
526 | 526 | sample_E => sample_s(7 DOWNTO 3), |
|
527 | 527 | sample_val => sample_val, |
|
528 | 528 | apbi => apbi_ext, |
|
529 | 529 | apbo => apbo_ext(15), |
|
530 | 530 | ahbi => ahbi_m_ext, |
|
531 | 531 | ahbo => ahbo_m_ext(2), |
|
532 | 532 | coarse_time => coarse_time, |
|
533 | 533 | fine_time => fine_time, |
|
534 | 534 | data_shaping_BW => bias_fail_sw_sig, |
|
535 | 535 | debug_vector => lfr_debug_vector, |
|
536 | 536 | debug_vector_ms => lfr_debug_vector_ms |
|
537 | 537 | ); |
|
538 | 538 | |
|
539 | 539 | observation_reg(11 DOWNTO 0) <= lfr_debug_vector; |
|
540 | 540 | observation_reg(31 DOWNTO 12) <= (OTHERS => '0'); |
|
541 | 541 | observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector; |
|
542 | 542 | observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector; |
|
543 | 543 | IO0 <= rstn_25; |
|
544 | 544 | IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid |
|
545 | 545 | IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready |
|
546 | 546 | IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full |
|
547 | 547 | IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full |
|
548 | 548 | IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2 |
|
549 | 549 | IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2 |
|
550 | 550 | IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2 |
|
551 | 551 | |
|
552 | 552 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE |
|
553 | 553 | sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; |
|
554 | 554 | END GENERATE all_sample; |
|
555 | 555 | |
|
556 | 556 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 |
|
557 | 557 | GENERIC MAP( |
|
558 | 558 | ChannelCount => 8, |
|
559 | 559 | SampleNbBits => 14, |
|
560 | 560 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 |
|
561 | 561 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 |
|
562 | 562 | PORT MAP ( |
|
563 | 563 | -- CONV |
|
564 | 564 | cnv_clk => clk_24, |
|
565 | 565 | cnv_rstn => rstn_25, |
|
566 | 566 | cnv => ADC_nCS_sig, |
|
567 | 567 | -- DATA |
|
568 | 568 | clk => clk_25, |
|
569 | 569 | rstn => rstn_25, |
|
570 | 570 | sck => ADC_CLK_sig, |
|
571 | 571 | sdo => ADC_SDO_sig, |
|
572 | 572 | -- SAMPLE |
|
573 | 573 | sample => sample, |
|
574 | 574 | sample_val => sample_val); |
|
575 | 575 | |
|
576 | 576 | --IO10 <= ADC_SDO_sig(5); |
|
577 | 577 | --IO9 <= ADC_SDO_sig(4); |
|
578 | 578 | --IO8 <= ADC_SDO_sig(3); |
|
579 | 579 | |
|
580 | 580 | ADC_nCS <= ADC_nCS_sig; |
|
581 | 581 | ADC_CLK <= ADC_CLK_sig; |
|
582 | 582 | ADC_SDO_sig <= ADC_SDO; |
|
583 | 583 | |
|
584 | 584 | sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE |
|
585 | 585 | "0010001000100010" WHEN HK_SEL = "01" ELSE |
|
586 | 586 | "0100010001000100" WHEN HK_SEL = "10" ELSE |
|
587 | 587 | (OTHERS => '0'); |
|
588 | 588 | |
|
589 | 589 | |
|
590 | 590 | ---------------------------------------------------------------------- |
|
591 | 591 | --- GPIO ----------------------------------------------------------- |
|
592 | 592 | ---------------------------------------------------------------------- |
|
593 | 593 | |
|
594 | 594 | grgpio0 : grgpio |
|
595 | 595 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) |
|
596 | 596 | PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); |
|
597 | 597 | |
|
598 | 598 | gpioi.sig_en <= (OTHERS => '0'); |
|
599 | 599 | gpioi.sig_in <= (OTHERS => '0'); |
|
600 | 600 | gpioi.din <= (OTHERS => '0'); |
|
601 | 601 | --pio_pad_0 : iopad |
|
602 | 602 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
603 | 603 | -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); |
|
604 | 604 | --pio_pad_1 : iopad |
|
605 | 605 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
606 | 606 | -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); |
|
607 | 607 | --pio_pad_2 : iopad |
|
608 | 608 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
609 | 609 | -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); |
|
610 | 610 | --pio_pad_3 : iopad |
|
611 | 611 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
612 | 612 | -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); |
|
613 | 613 | --pio_pad_4 : iopad |
|
614 | 614 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
615 | 615 | -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); |
|
616 | 616 | --pio_pad_5 : iopad |
|
617 | 617 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
618 | 618 | -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); |
|
619 | 619 | --pio_pad_6 : iopad |
|
620 | 620 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
621 | 621 | -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); |
|
622 | 622 | --pio_pad_7 : iopad |
|
623 | 623 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
624 | 624 | -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); |
|
625 | 625 | |
|
626 | 626 | PROCESS (clk_25, rstn_25) |
|
627 | 627 | BEGIN -- PROCESS |
|
628 | 628 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) |
|
629 | 629 | -- --IO0 <= '0'; |
|
630 | 630 | -- IO1 <= '0'; |
|
631 | 631 | -- IO2 <= '0'; |
|
632 | 632 | -- IO3 <= '0'; |
|
633 | 633 | -- IO4 <= '0'; |
|
634 | 634 | -- IO5 <= '0'; |
|
635 | 635 | -- IO6 <= '0'; |
|
636 | 636 | -- IO7 <= '0'; |
|
637 | 637 | IO8 <= '0'; |
|
638 | 638 | IO9 <= '0'; |
|
639 | 639 | IO10 <= '0'; |
|
640 | 640 | IO11 <= '0'; |
|
641 | 641 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
|
642 | 642 | CASE gpioo.dout(2 DOWNTO 0) IS |
|
643 | 643 | WHEN "011" => |
|
644 | 644 | -- --IO0 <= observation_reg(0 ); |
|
645 | 645 | -- IO1 <= observation_reg(1 ); |
|
646 | 646 | -- IO2 <= observation_reg(2 ); |
|
647 | 647 | -- IO3 <= observation_reg(3 ); |
|
648 | 648 | -- IO4 <= observation_reg(4 ); |
|
649 | 649 | -- IO5 <= observation_reg(5 ); |
|
650 | 650 | -- IO6 <= observation_reg(6 ); |
|
651 | 651 | -- IO7 <= observation_reg(7 ); |
|
652 | 652 | IO8 <= observation_reg(8); |
|
653 | 653 | IO9 <= observation_reg(9); |
|
654 | 654 | IO10 <= observation_reg(10); |
|
655 | 655 | IO11 <= observation_reg(11); |
|
656 | 656 | WHEN "001" => |
|
657 | 657 | -- --IO0 <= observation_reg(0 + 12); |
|
658 | 658 | -- IO1 <= observation_reg(1 + 12); |
|
659 | 659 | -- IO2 <= observation_reg(2 + 12); |
|
660 | 660 | -- IO3 <= observation_reg(3 + 12); |
|
661 | 661 | -- IO4 <= observation_reg(4 + 12); |
|
662 | 662 | -- IO5 <= observation_reg(5 + 12); |
|
663 | 663 | -- IO6 <= observation_reg(6 + 12); |
|
664 | 664 | -- IO7 <= observation_reg(7 + 12); |
|
665 | 665 | IO8 <= observation_reg(8 + 12); |
|
666 | 666 | IO9 <= observation_reg(9 + 12); |
|
667 | 667 | IO10 <= observation_reg(10 + 12); |
|
668 | 668 | IO11 <= observation_reg(11 + 12); |
|
669 | 669 | WHEN "010" => |
|
670 | 670 | -- --IO0 <= observation_reg(0 + 12 + 12); |
|
671 | 671 | -- IO1 <= observation_reg(1 + 12 + 12); |
|
672 | 672 | -- IO2 <= observation_reg(2 + 12 + 12); |
|
673 | 673 | -- IO3 <= observation_reg(3 + 12 + 12); |
|
674 | 674 | -- IO4 <= observation_reg(4 + 12 + 12); |
|
675 | 675 | -- IO5 <= observation_reg(5 + 12 + 12); |
|
676 | 676 | -- IO6 <= observation_reg(6 + 12 + 12); |
|
677 | 677 | -- IO7 <= observation_reg(7 + 12 + 12); |
|
678 | 678 | IO8 <= '0'; |
|
679 | 679 | IO9 <= '0'; |
|
680 | 680 | IO10 <= '0'; |
|
681 | 681 | IO11 <= '0'; |
|
682 | 682 | WHEN "000" => |
|
683 | 683 | -- --IO0 <= observation_vector_0(0 ); |
|
684 | 684 | -- IO1 <= observation_vector_0(1 ); |
|
685 | 685 | -- IO2 <= observation_vector_0(2 ); |
|
686 | 686 | -- IO3 <= observation_vector_0(3 ); |
|
687 | 687 | -- IO4 <= observation_vector_0(4 ); |
|
688 | 688 | -- IO5 <= observation_vector_0(5 ); |
|
689 | 689 | -- IO6 <= observation_vector_0(6 ); |
|
690 | 690 | -- IO7 <= observation_vector_0(7 ); |
|
691 | 691 | IO8 <= observation_vector_0(8); |
|
692 | 692 | IO9 <= observation_vector_0(9); |
|
693 | 693 | IO10 <= observation_vector_0(10); |
|
694 | 694 | IO11 <= observation_vector_0(11); |
|
695 | 695 | WHEN "100" => |
|
696 | 696 | -- --IO0 <= observation_vector_1(0 ); |
|
697 | 697 | -- IO1 <= observation_vector_1(1 ); |
|
698 | 698 | -- IO2 <= observation_vector_1(2 ); |
|
699 | 699 | -- IO3 <= observation_vector_1(3 ); |
|
700 | 700 | -- IO4 <= observation_vector_1(4 ); |
|
701 | 701 | -- IO5 <= observation_vector_1(5 ); |
|
702 | 702 | -- IO6 <= observation_vector_1(6 ); |
|
703 | 703 | -- IO7 <= observation_vector_1(7 ); |
|
704 | 704 | IO8 <= observation_vector_1(8); |
|
705 | 705 | IO9 <= observation_vector_1(9); |
|
706 | 706 | IO10 <= observation_vector_1(10); |
|
707 | 707 | IO11 <= observation_vector_1(11); |
|
708 | 708 | WHEN OTHERS => NULL; |
|
709 | 709 | END CASE; |
|
710 | 710 | |
|
711 | 711 | END IF; |
|
712 | 712 | END PROCESS; |
|
713 | 713 | ----------------------------------------------------------------------------- |
|
714 | 714 | -- |
|
715 | 715 | ----------------------------------------------------------------------------- |
|
716 | 716 | all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE |
|
717 | 717 | apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE |
|
718 | 718 | apbo_ext(I) <= apb_none; |
|
719 | 719 | END GENERATE apbo_ext_not_used; |
|
720 | 720 | END GENERATE all_apbo_ext; |
|
721 | 721 | |
|
722 | 722 | |
|
723 | 723 | all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE |
|
724 | 724 | ahbo_s_ext(I) <= ahbs_none; |
|
725 | 725 | END GENERATE all_ahbo_ext; |
|
726 | 726 | |
|
727 | 727 | all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE |
|
728 | 728 | ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE |
|
729 | 729 | ahbo_m_ext(I) <= ahbm_none; |
|
730 | 730 | END GENERATE ahbo_m_ext_not_used; |
|
731 | 731 | END GENERATE all_ahbo_m_ext; |
|
732 | 732 | |
|
733 | 733 | END beh; |
@@ -1,23 +1,26 | |||
|
1 | 1 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_pkg.vhd |
|
2 | 2 | |
|
3 | 3 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic.vhd |
|
4 | 4 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_integrator.vhd |
|
5 | 5 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_downsampler.vhd |
|
6 | 6 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_comb.vhd |
|
7 | 7 | |
|
8 | 8 | |
|
9 | 9 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr.vhd |
|
10 | 10 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr_control.vhd |
|
11 | 11 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr_add_sub.vhd |
|
12 | 12 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr_address_gen.vhd |
|
13 | 13 | |
|
14 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr_r2.vhd | |
|
15 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr_control_r2.vhd | |
|
16 | ||
|
14 | 17 | vcom -quiet -93 -work work tb.vhd |
|
15 | 18 | |
|
16 | 19 | vsim work.testbench |
|
17 | 20 | |
|
18 | 21 | log -r * |
|
19 | 22 | |
|
20 |
do wave |
|
|
23 | do wave.do | |
|
21 | 24 | |
|
22 | 25 | run -all |
|
23 | 26 |
@@ -1,238 +1,271 | |||
|
1 | 1 | |
|
2 | 2 | LIBRARY ieee; |
|
3 | 3 | USE ieee.std_logic_1164.ALL; |
|
4 | 4 | USE IEEE.MATH_REAL.ALL; |
|
5 | 5 | USE ieee.numeric_std.ALL; |
|
6 | 6 | |
|
7 | 7 | LIBRARY lpp; |
|
8 | 8 | USE lpp.cic_pkg.ALL; |
|
9 | 9 | USE lpp.data_type_pkg.ALL; |
|
10 | 10 | USE lpp.chirp_pkg.ALL; |
|
11 | 11 | |
|
12 | 12 | ENTITY testbench IS |
|
13 | 13 | END; |
|
14 | 14 | |
|
15 | 15 | ARCHITECTURE behav OF testbench IS |
|
16 | 16 | |
|
17 | 17 | SIGNAL clk : STD_LOGIC := '0'; |
|
18 | 18 | SIGNAL clk_24k : STD_LOGIC := '0'; |
|
19 | 19 | SIGNAL clk_24k_r : STD_LOGIC := '0'; |
|
20 | 20 | SIGNAL rstn : STD_LOGIC; |
|
21 | 21 | SIGNAL run : STD_LOGIC; |
|
22 | 22 | SIGNAL data_in : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
23 |
SIGNAL data_gen |
|
|
23 | SIGNAL data_gen : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
24 | SIGNAL data_in_v_r2 : sample_vector(7 DOWNTO 0,15 DOWNTO 0); | |
|
24 | 25 | SIGNAL data_in_v : sample_vector(5 DOWNTO 0,15 DOWNTO 0); |
|
25 | 26 | SIGNAL data_in_valid : STD_LOGIC; |
|
26 | 27 | |
|
27 | 28 | CONSTANT DATA_VALUE_0 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"7FFF"; |
|
28 | 29 | CONSTANT DATA_VALUE_1 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"FFFF"; |
|
29 | 30 | CONSTANT DATA_VALUE_2 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"8000"; |
|
30 | 31 | CONSTANT DATA_VALUE_3 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0010"; |
|
31 | 32 | CONSTANT DATA_VALUE_4 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0020"; |
|
32 | 33 | CONSTANT DATA_VALUE_5 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0040"; |
|
33 | 34 | |
|
34 | 35 | SIGNAL data_in_0_s : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
35 | 36 | |
|
36 | 37 | SIGNAL data_in_0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
37 | 38 | SIGNAL data_in_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
38 | 39 | SIGNAL data_in_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
39 | 40 | SIGNAL data_in_3 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
40 | 41 | SIGNAL data_in_4 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
41 | 42 | SIGNAL data_in_5 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
42 | 43 | |
|
43 | 44 | SIGNAL data_in_0_temp : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
44 | 45 | SIGNAL data_in_1_temp : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
45 | 46 | SIGNAL data_in_2_temp : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
46 | 47 | SIGNAL data_in_3_temp : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
47 | 48 | SIGNAL data_in_4_temp : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
48 | 49 | SIGNAL data_in_5_temp : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
49 | 50 | |
|
51 | SIGNAL param_r2 : STD_LOGIC; | |
|
52 | ||
|
50 | 53 | BEGIN |
|
51 | 54 | |
|
52 | 55 | |
|
53 | 56 | |
|
54 | 57 | clk <= NOT clk AFTER 5 ns; |
|
55 | 58 | clk_24k <= NOT clk_24k AFTER 20345 ns; |
|
56 | 59 | |
|
57 | 60 | PROCESS (clk, rstn) |
|
58 | 61 | BEGIN -- PROCESS |
|
59 | 62 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
60 | 63 | data_in_valid <= '0'; |
|
61 | 64 | clk_24k_r <= '0'; |
|
62 | 65 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
63 | 66 | clk_24k_r <= clk_24k; |
|
64 | 67 | IF clk_24k = '1' AND clk_24k_r = '0' THEN |
|
65 | 68 | data_in_valid <= '1'; |
|
66 | 69 | ELSE |
|
67 | 70 | data_in_valid <= '0'; |
|
68 | 71 | END IF; |
|
69 | 72 | END IF; |
|
70 | 73 | END PROCESS; |
|
71 | 74 | |
|
72 | 75 | |
|
73 | 76 | PROCESS |
|
74 | 77 | BEGIN -- PROCESS |
|
75 | 78 | WAIT UNTIL clk = '1'; |
|
76 | 79 | rstn <= '0'; |
|
77 | 80 | run <= '0'; |
|
78 | ||
|
81 | param_r2 <= '1'; | |
|
79 | 82 | WAIT UNTIL clk = '1'; |
|
80 | 83 | rstn <= '1'; |
|
81 | 84 | WAIT UNTIL clk = '1'; |
|
82 | 85 | WAIT UNTIL clk = '1'; |
|
83 | 86 | run <= '1'; |
|
84 | 87 | WAIT UNTIL clk = '1'; |
|
85 | ||
|
88 | ||
|
89 | WAIT FOR 30 ms; | |
|
90 | param_r2 <= '0'; | |
|
86 | 91 | |
|
87 | 92 | WAIT FOR 30 ms; |
|
88 | 93 | REPORT "*** END simulation ***" SEVERITY failure; |
|
89 | 94 | WAIT; |
|
90 | 95 | END PROCESS; |
|
91 | 96 | ----------------------------------------------------------------------------- |
|
92 | 97 | cic_lfr_1: cic_lfr |
|
93 | 98 | GENERIC MAP ( |
|
94 | 99 | tech => 0, |
|
95 | 100 | use_RAM_nCEL => 0) |
|
96 | 101 | PORT MAP ( |
|
97 | 102 | clk => clk, |
|
98 | 103 | rstn => rstn, |
|
99 | 104 | run => run, |
|
100 | 105 | data_in => data_in_v, |
|
101 | 106 | data_in_valid => data_in_valid, |
|
102 | 107 | data_out_16 => OPEN, |
|
103 | 108 | data_out_16_valid => OPEN, |
|
104 | 109 | data_out_256 => OPEN, |
|
105 | 110 | data_out_256_valid => OPEN); |
|
106 | 111 | ----------------------------------------------------------------------------- |
|
112 | cic_lfr_r2_1: cic_lfr_r2 | |
|
113 | GENERIC MAP ( | |
|
114 | tech => 0, | |
|
115 | use_RAM_nCEL => 0) | |
|
116 | PORT MAP ( | |
|
117 | clk => clk, | |
|
118 | rstn => rstn, | |
|
119 | run => run, | |
|
120 | param_r2 => param_r2, | |
|
121 | data_in => data_in_v_r2, | |
|
122 | data_in_valid => data_in_valid, | |
|
123 | data_out_16 => OPEN, | |
|
124 | data_out_16_valid => OPEN, | |
|
125 | data_out_256 => OPEN, | |
|
126 | data_out_256_valid => OPEN); | |
|
127 | ||
|
128 | ----------------------------------------------------------------------------- | |
|
129 | all_bit_r2: FOR J IN 15 DOWNTO 0 GENERATE | |
|
130 | data_in_v_r2(0,J) <= data_in_0(J); | |
|
131 | data_in_v_r2(1,J) <= data_in_1(J); | |
|
132 | data_in_v_r2(2,J) <= data_in_2(J); | |
|
133 | data_in_v_r2(3,J) <= data_in_3(J); | |
|
134 | data_in_v_r2(4,J) <= data_in_4(J); | |
|
135 | data_in_v_r2(5,J) <= data_in_5(J); | |
|
136 | data_in_v_r2(6,J) <= data_in_0(J); | |
|
137 | data_in_v_r2(7,J) <= data_in_0(J); | |
|
138 | END GENERATE all_bit_r2; | |
|
139 | ----------------------------------------------------------------------------- | |
|
107 | 140 | all_bit: FOR J IN 15 DOWNTO 0 GENERATE |
|
108 | 141 | data_in_v(0,J) <= data_in_0(J); |
|
109 | 142 | data_in_v(1,J) <= data_in_1(J); |
|
110 | 143 | data_in_v(2,J) <= data_in_2(J); |
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111 | 144 | data_in_v(3,J) <= data_in_3(J); |
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112 | 145 | data_in_v(4,J) <= data_in_4(J); |
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113 | 146 | data_in_v(5,J) <= data_in_5(J); |
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114 | 147 | END GENERATE all_bit; |
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115 | 148 | ----------------------------------------------------------------------------- |
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116 | 149 | --chirp_gen: chirp |
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117 | 150 | -- GENERIC MAP ( |
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118 | 151 | -- LOW_FREQUENCY_LIMIT => 0, |
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119 | 152 | -- HIGH_FREQUENCY_LIMIT => 1000, |
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120 | 153 | -- NB_POINT_TO_GEN => 10000, |
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121 | 154 | -- AMPLITUDE => 200, |
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122 | 155 | -- NB_BITS => 16) |
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123 | 156 | -- PORT MAP ( |
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124 | 157 | -- clk => clk, |
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125 | 158 | -- rstn => rstn, |
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126 | 159 | -- run => run, |
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127 | 160 | -- data_ack => data_in_valid, |
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128 | 161 | -- data => data_in); |
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129 | 162 | |
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130 | 163 | PROCESS (clk, rstn) |
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131 | 164 | BEGIN |
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132 | 165 | IF rstn = '0' THEN |
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133 | 166 | data_in_0_temp <= (OTHERS => '0'); |
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134 | 167 | data_in_1_temp <= (OTHERS => '0'); |
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135 | 168 | data_in_2_temp <= (OTHERS => '0'); |
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136 | 169 | data_in_3_temp <= (OTHERS => '0'); |
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137 | 170 | data_in_4_temp <= (OTHERS => '0'); |
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138 | 171 | data_in_5_temp <= (OTHERS => '0'); |
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139 | 172 | ELSIF clk'event AND clk = '1' THEN |
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140 | 173 | IF data_in_valid = '1' THEN |
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141 | 174 | data_in_0_temp <= DATA_VALUE_0; |
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142 | 175 | data_in_1_temp <= DATA_VALUE_1; |
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143 | 176 | data_in_2_temp <= DATA_VALUE_2; |
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144 | 177 | data_in_3_temp <= DATA_VALUE_3; |
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145 | 178 | data_in_4_temp <= DATA_VALUE_4; |
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146 | 179 | data_in_5_temp <= DATA_VALUE_5; |
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147 | 180 | END IF; |
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148 | 181 | END IF; |
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149 | 182 | END PROCESS; |
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150 | 183 | --data_in_0 <= data_in_0_temp WHEN data_in_valid = '0' ELSE DATA_VALUE_0; |
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151 | 184 | data_in_1 <= data_in_1_temp WHEN data_in_valid = '0' ELSE DATA_VALUE_1; |
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152 | 185 | data_in_2 <= data_in_2_temp WHEN data_in_valid = '0' ELSE DATA_VALUE_2; |
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153 | 186 | data_in_3 <= data_in_3_temp WHEN data_in_valid = '0' ELSE DATA_VALUE_3; |
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154 | 187 | data_in_4 <= data_in_4_temp WHEN data_in_valid = '0' ELSE DATA_VALUE_4; |
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155 | 188 | data_in_5 <= data_in_5_temp WHEN data_in_valid = '0' ELSE DATA_VALUE_5; |
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156 | 189 | |
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157 | 190 | ----------------------------------------------------------------------------- |
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158 | 191 | chirp_gen: chirp |
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159 | 192 | GENERIC MAP ( |
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160 | 193 | LOW_FREQUENCY_LIMIT => 0, |
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161 | 194 | HIGH_FREQUENCY_LIMIT => 1000, |
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162 | 195 | NB_POINT_TO_GEN => 10000, |
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163 | 196 | AMPLITUDE => 200, |
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164 | 197 | NB_BITS => 16) |
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165 | 198 | PORT MAP ( |
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166 | 199 | clk => clk, |
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167 | 200 | rstn => rstn, |
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168 | 201 | run => run, |
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169 | 202 | data_ack => data_in_valid, |
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170 | 203 | data => data_in_0_s); |
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171 | 204 | |
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172 | 205 | ----------------------------------------------------------------------------- |
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173 | 206 | |
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174 | 207 | PROCESS (clk, rstn) |
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175 | 208 | BEGIN -- PROCESS |
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176 | 209 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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177 | 210 | data_in_0 <= (OTHERS => '0'); |
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178 | 211 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
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179 | 212 | IF data_in_valid = '1' THEN |
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180 | 213 | data_in_0 <= data_in_0_s; |
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181 | 214 | END IF; |
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182 | 215 | END IF; |
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183 | 216 | END PROCESS; |
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184 | 217 | |
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185 | 218 | ----------------------------------------------------------------------------- |
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186 | 219 | cic_1: cic |
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187 | 220 | GENERIC MAP ( |
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188 | 221 | D_delay_number => 2, |
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189 | 222 | S_stage_number => 3, |
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190 | 223 | R_downsampling_decimation_factor => 16, |
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191 | 224 | b_data_size => 16, |
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192 | 225 | b_grow => 15) --16 #### log2(RD)*S |
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193 | 226 | PORT MAP ( |
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194 | 227 | clk => clk, |
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195 | 228 | rstn => rstn, |
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196 | 229 | run => run, |
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197 | 230 | data_in => data_in_0_s, |
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198 | 231 | data_in_valid => data_in_valid, |
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199 | 232 | data_out => OPEN, |
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200 | 233 | data_out_valid => OPEN); |
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201 | 234 | |
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202 | 235 | --cic_16: cic |
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203 | 236 | -- GENERIC MAP ( |
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204 | 237 | -- D_delay_number => 2, |
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205 | 238 | -- S_stage_number => 3, |
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206 | 239 | -- R_downsampling_decimation_factor => 16, |
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207 | 240 | -- b_data_size => 16, |
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208 | 241 | -- b_grow => 15) --16 #### log2(RD)*S |
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209 | 242 | -- PORT MAP ( |
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210 | 243 | -- clk => clk, |
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211 | 244 | -- rstn => rstn, |
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212 | 245 | -- run => run, |
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213 | 246 | -- data_in => data_in_0_s, |
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214 | 247 | -- data_in_valid => data_in_valid, |
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215 | 248 | -- data_out => OPEN, |
|
216 | 249 | -- data_out_valid => OPEN); |
|
217 | 250 | |
|
218 | 251 | cic_256: cic |
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219 | 252 | GENERIC MAP ( |
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220 | 253 | D_delay_number => 2, |
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221 | 254 | S_stage_number => 3, |
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222 | 255 | R_downsampling_decimation_factor => 256, |
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223 | 256 | b_data_size => 16, |
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224 | 257 | b_grow => 27) --32 #### log2(RD)*S = log2(256*2)*3 |
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225 | 258 | PORT MAP ( |
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226 | 259 | clk => clk, |
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227 | 260 | rstn => rstn, |
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228 | 261 | run => run, |
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229 | 262 | data_in => data_in_0_s, |
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230 | 263 | data_in_valid => data_in_valid, |
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231 | 264 | data_out => OPEN, |
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232 | 265 | data_out_valid => OPEN); |
|
233 | 266 | |
|
234 | 267 | |
|
235 | 268 | |
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236 | 269 | |
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237 | 270 | |
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238 | 271 | END; |
@@ -1,130 +1,389 | |||
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1 | 1 | onerror {resume} |
|
2 | quietly virtual signal -install /testbench/cic_lfr_r2_1/memCEL/RAMblk { (context /testbench/cic_lfr_r2_1/memCEL/RAMblk )(RAMarray(0) &RAMarray(1) &RAMarray(2) &RAMarray(3) &RAMarray(4) &RAMarray(5) &RAMarray(6) &RAMarray(7) &RAMarray(8) &RAMarray(9) &RAMarray(10) &RAMarray(11) &RAMarray(12) &RAMarray(13) &RAMarray(14) &RAMarray(15) &RAMarray(16) &RAMarray(17) &RAMarray(18) &RAMarray(19) &RAMarray(20) &RAMarray(21) &RAMarray(22) &RAMarray(23) &RAMarray(24) &RAMarray(25) &RAMarray(26) &RAMarray(27) &RAMarray(28) &RAMarray(29) &RAMarray(30) &RAMarray(31) &RAMarray(32) &RAMarray(33) &RAMarray(34) &RAMarray(35) &RAMarray(36) &RAMarray(37) &RAMarray(38) &RAMarray(39) )} R2_RAM_lane0 | |
|
3 | quietly virtual signal -install /testbench/cic_lfr_r2_1/memCEL/RAMblk { (context /testbench/cic_lfr_r2_1/memCEL/RAMblk )(RAMarray(40) &RAMarray(41) &RAMarray(42) &RAMarray(43) &RAMarray(44) &RAMarray(45) &RAMarray(46) &RAMarray(47) &RAMarray(48) &RAMarray(49) &RAMarray(50) &RAMarray(51) &RAMarray(52) &RAMarray(53) &RAMarray(54) &RAMarray(55) &RAMarray(56) &RAMarray(57) &RAMarray(58) &RAMarray(59) &RAMarray(60) &RAMarray(61) &RAMarray(62) &RAMarray(63) &RAMarray(64) &RAMarray(65) &RAMarray(66) &RAMarray(67) &RAMarray(68) &RAMarray(69) &RAMarray(70) &RAMarray(71) &RAMarray(72) &RAMarray(73) &RAMarray(74) &RAMarray(75) &RAMarray(76) &RAMarray(77) &RAMarray(78) &RAMarray(79) )} R2_RAM_lane0001 | |
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4 | quietly virtual signal -install /testbench/cic_lfr_r2_1/memCEL/RAMblk { (context /testbench/cic_lfr_r2_1/memCEL/RAMblk )(RAMarray(80) &RAMarray(81) &RAMarray(82) &RAMarray(83) &RAMarray(84) &RAMarray(85) &RAMarray(86) &RAMarray(87) &RAMarray(88) &RAMarray(89) &RAMarray(90) &RAMarray(91) &RAMarray(92) &RAMarray(93) &RAMarray(94) &RAMarray(95) &RAMarray(96) &RAMarray(97) &RAMarray(98) &RAMarray(99) &RAMarray(100) &RAMarray(101) &RAMarray(102) &RAMarray(103) &RAMarray(104) &RAMarray(105) &RAMarray(106) &RAMarray(107) &RAMarray(108) &RAMarray(109) &RAMarray(110) &RAMarray(111) &RAMarray(112) &RAMarray(113) &RAMarray(114) &RAMarray(115) &RAMarray(116) &RAMarray(117) &RAMarray(118) &RAMarray(119) )} R2_RAM_lane2 | |
|
5 | quietly virtual signal -install /testbench/cic_lfr_r2_1/memCEL/RAMblk { (context /testbench/cic_lfr_r2_1/memCEL/RAMblk )(RAMarray(120) &RAMarray(121) &RAMarray(122) &RAMarray(123) &RAMarray(124) &RAMarray(125) &RAMarray(126) &RAMarray(127) &RAMarray(128) &RAMarray(129) &RAMarray(130) &RAMarray(131) &RAMarray(132) &RAMarray(133) &RAMarray(134) &RAMarray(135) &RAMarray(136) &RAMarray(137) &RAMarray(138) &RAMarray(139) &RAMarray(140) &RAMarray(141) &RAMarray(142) &RAMarray(143) &RAMarray(144) &RAMarray(145) &RAMarray(146) &RAMarray(147) &RAMarray(148) &RAMarray(149) &RAMarray(150) &RAMarray(151) &RAMarray(152) &RAMarray(153) &RAMarray(154) &RAMarray(155) &RAMarray(156) &RAMarray(157) &RAMarray(158) &RAMarray(159) )} R2_RAM_lane3 | |
|
6 | quietly virtual signal -install /testbench/cic_lfr_r2_1/memCEL/RAMblk { (context /testbench/cic_lfr_r2_1/memCEL/RAMblk )(RAMarray(160) &RAMarray(161) &RAMarray(162) &RAMarray(163) &RAMarray(164) &RAMarray(165) &RAMarray(166) &RAMarray(167) &RAMarray(168) &RAMarray(169) &RAMarray(170) &RAMarray(171) &RAMarray(172) &RAMarray(173) &RAMarray(174) &RAMarray(175) &RAMarray(176) &RAMarray(177) &RAMarray(178) &RAMarray(179) &RAMarray(180) &RAMarray(181) &RAMarray(182) &RAMarray(183) &RAMarray(184) &RAMarray(185) &RAMarray(186) &RAMarray(187) &RAMarray(188) &RAMarray(189) &RAMarray(190) &RAMarray(191) &RAMarray(192) &RAMarray(193) &RAMarray(194) &RAMarray(195) &RAMarray(196) &RAMarray(197) &RAMarray(198) &RAMarray(199) )} R2_RAM_lane4 | |
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7 | quietly virtual signal -install /testbench/cic_lfr_r2_1/memCEL/RAMblk { (context /testbench/cic_lfr_r2_1/memCEL/RAMblk )(RAMarray(200) &RAMarray(201) &RAMarray(202) &RAMarray(203) &RAMarray(204) &RAMarray(205) &RAMarray(206) &RAMarray(207) &RAMarray(208) &RAMarray(209) &RAMarray(210) &RAMarray(211) &RAMarray(212) &RAMarray(213) &RAMarray(214) &RAMarray(215) &RAMarray(216) &RAMarray(217) &RAMarray(218) &RAMarray(219) &RAMarray(220) &RAMarray(221) &RAMarray(222) &RAMarray(223) &RAMarray(224) &RAMarray(225) &RAMarray(226) &RAMarray(227) &RAMarray(228) &RAMarray(229) &RAMarray(230) &RAMarray(231) &RAMarray(232) &RAMarray(233) &RAMarray(234) &RAMarray(235) &RAMarray(236) &RAMarray(237) &RAMarray(238) &RAMarray(239) )} R2_RAM_lane5 | |
|
8 | quietly virtual signal -install /testbench/cic_lfr_r2_1/memCEL/RAMblk { (context /testbench/cic_lfr_r2_1/memCEL/RAMblk )(RAMarray(240) &RAMarray(241) &RAMarray(242) &RAMarray(243) &RAMarray(244) &RAMarray(245) &RAMarray(246) &RAMarray(247) &RAMarray(248) &RAMarray(249) &RAMarray(250) &RAMarray(251) &RAMarray(252) &RAMarray(253) &RAMarray(254) &RAMarray(255) &RAMarray(256) &RAMarray(257) &RAMarray(258) &RAMarray(259) &RAMarray(260) &RAMarray(261) &RAMarray(262) &RAMarray(263) &RAMarray(264) &RAMarray(265) &RAMarray(266) &RAMarray(267) &RAMarray(268) &RAMarray(269) &RAMarray(270) &RAMarray(271) &RAMarray(272) &RAMarray(273) &RAMarray(274) &RAMarray(275) &RAMarray(276) &RAMarray(277) &RAMarray(278) &RAMarray(279) )} R2_RAM_lane5001 | |
|
9 | quietly virtual signal -install /testbench/cic_lfr_r2_1/memCEL/RAMblk { (context /testbench/cic_lfr_r2_1/memCEL/RAMblk )(RAMarray(280) &RAMarray(281) &RAMarray(282) &RAMarray(283) &RAMarray(284) &RAMarray(285) &RAMarray(286) &RAMarray(287) &RAMarray(288) &RAMarray(289) &RAMarray(290) &RAMarray(291) &RAMarray(292) &RAMarray(293) &RAMarray(294) &RAMarray(295) &RAMarray(296) &RAMarray(297) &RAMarray(298) &RAMarray(299) &RAMarray(300) &RAMarray(301) &RAMarray(302) &RAMarray(303) &RAMarray(304) &RAMarray(305) &RAMarray(306) &RAMarray(307) &RAMarray(308) &RAMarray(309) &RAMarray(310) &RAMarray(311) &RAMarray(312) &RAMarray(313) &RAMarray(314) &RAMarray(315) &RAMarray(316) &RAMarray(317) &RAMarray(318) &RAMarray(319) )} R2_RAM_lane7 | |
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2 | 10 | quietly WaveActivateNextPane {} 0 |
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3 |
add wave -noupdate - |
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4 |
add wave -noupdate - |
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5 |
add wave -noupdate - |
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6 |
add wave -noupdate - |
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7 | add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group int -radix hexadecimal -childformat {{/testbench/cic_1/I_data(3) -radix hexadecimal} {/testbench/cic_1/I_data(2) -radix hexadecimal} {/testbench/cic_1/I_data(1) -radix hexadecimal} {/testbench/cic_1/I_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/I_data(3) {-radix hexadecimal} /testbench/cic_1/I_data(2) {-radix hexadecimal} /testbench/cic_1/I_data(1) {-radix hexadecimal} /testbench/cic_1/I_data(0) {-radix hexadecimal}} /testbench/cic_1/I_data | |
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8 |
add wave -noupdate - |
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9 | add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group COMB_1 -radix decimal /testbench/cic_1/all_C(1)/cic_comb_1/data_in | |
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10 | add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group COMB_1 -radix decimal /testbench/cic_1/all_C(1)/cic_comb_1/data_in_valid | |
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11 | add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group COMB_1 -radix decimal -childformat {{/testbench/cic_1/all_C(1)/cic_comb_1/data_reg(2) -radix decimal} {/testbench/cic_1/all_C(1)/cic_comb_1/data_reg(1) -radix decimal} {/testbench/cic_1/all_C(1)/cic_comb_1/data_reg(0) -radix decimal}} -expand -subitemconfig {/testbench/cic_1/all_C(1)/cic_comb_1/data_reg(2) {-radix decimal} /testbench/cic_1/all_C(1)/cic_comb_1/data_reg(1) {-radix decimal} /testbench/cic_1/all_C(1)/cic_comb_1/data_reg(0) {-radix decimal}} /testbench/cic_1/all_C(1)/cic_comb_1/data_reg | |
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12 |
add wave -noupdate -expand -group |
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13 |
add wave -noupdate -expand -group |
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14 | add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group comb -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3) -radix hexadecimal} {/testbench/cic_1/C_data(2) -radix hexadecimal} {/testbench/cic_1/C_data(1) -radix hexadecimal} {/testbench/cic_1/C_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/C_data(3) {-radix hexadecimal} /testbench/cic_1/C_data(2) {-radix hexadecimal} /testbench/cic_1/C_data(1) {-radix hexadecimal} /testbench/cic_1/C_data(0) {-radix hexadecimal}} /testbench/cic_1/C_data | |
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15 | add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group comb -radix hexadecimal /testbench/cic_1/C_valid | |
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16 |
add wave -noupdate -expand -group C16 |
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17 | add wave -noupdate -expand -group C16_REG -group C0 -expand -group C0_0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(12) | |
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18 |
add wave -noupdate -expand -group C16 |
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19 | add wave -noupdate -expand -group C16_REG -group C0 -expand -group C0_1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(18) | |
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20 |
add wave -noupdate -expand -group C |
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21 | add wave -noupdate -expand -group C16_REG -group C1 -expand -group C1_0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(10) | |
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22 |
add wave -noupdate -expand -group C |
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23 | add wave -noupdate -expand -group C16_REG -group C1 -expand -group C1_1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(16) | |
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24 |
add wave -noupdate -expand -group C |
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25 | add wave -noupdate -expand -group C16_REG -group C1 -radix hexadecimal /testbench/cic_1/C_data(1) | |
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26 | add wave -noupdate -expand -group C16_REG -group C2 -expand -group C2_0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(11) | |
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27 | add wave -noupdate -expand -group C16_REG -group C2 -expand -group C2_0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(14) | |
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28 | add wave -noupdate -expand -group C16_REG -group C2 -expand -group C2_1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(17) | |
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29 | add wave -noupdate -expand -group C16_REG -group C2 -expand -group C2_1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(20) | |
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30 | add wave -noupdate -expand -group C16_REG -group C2 -radix hexadecimal /testbench/cic_1/C_data(2) | |
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31 | add wave -noupdate -expand -group C16_REG -expand -group {C3 - OUTPUT} -radix decimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/sample_out_reg16_s(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg16_s | |
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32 | add wave -noupdate -expand -group C16_REG -expand -group {C3 - OUTPUT} -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3)(31) -radix hexadecimal} {/testbench/cic_1/C_data(3)(30) -radix hexadecimal} {/testbench/cic_1/C_data(3)(29) -radix hexadecimal} {/testbench/cic_1/C_data(3)(28) -radix hexadecimal} {/testbench/cic_1/C_data(3)(27) -radix hexadecimal} {/testbench/cic_1/C_data(3)(26) -radix hexadecimal} {/testbench/cic_1/C_data(3)(25) -radix hexadecimal} {/testbench/cic_1/C_data(3)(24) -radix hexadecimal} {/testbench/cic_1/C_data(3)(23) -radix hexadecimal} {/testbench/cic_1/C_data(3)(22) -radix hexadecimal} {/testbench/cic_1/C_data(3)(21) -radix hexadecimal} {/testbench/cic_1/C_data(3)(20) -radix hexadecimal} {/testbench/cic_1/C_data(3)(19) -radix hexadecimal} {/testbench/cic_1/C_data(3)(18) -radix hexadecimal} {/testbench/cic_1/C_data(3)(17) -radix hexadecimal} {/testbench/cic_1/C_data(3)(16) -radix hexadecimal} {/testbench/cic_1/C_data(3)(15) -radix hexadecimal} {/testbench/cic_1/C_data(3)(14) -radix hexadecimal} {/testbench/cic_1/C_data(3)(13) -radix hexadecimal} {/testbench/cic_1/C_data(3)(12) -radix hexadecimal} {/testbench/cic_1/C_data(3)(11) -radix hexadecimal} {/testbench/cic_1/C_data(3)(10) -radix hexadecimal} {/testbench/cic_1/C_data(3)(9) -radix hexadecimal} {/testbench/cic_1/C_data(3)(8) -radix hexadecimal} {/testbench/cic_1/C_data(3)(7) -radix hexadecimal} {/testbench/cic_1/C_data(3)(6) -radix hexadecimal} {/testbench/cic_1/C_data(3)(5) -radix hexadecimal} {/testbench/cic_1/C_data(3)(4) -radix hexadecimal} {/testbench/cic_1/C_data(3)(3) -radix hexadecimal} {/testbench/cic_1/C_data(3)(2) -radix hexadecimal} {/testbench/cic_1/C_data(3)(1) -radix hexadecimal} {/testbench/cic_1/C_data(3)(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_1/C_data(3)(31) {-radix hexadecimal} /testbench/cic_1/C_data(3)(30) {-radix hexadecimal} /testbench/cic_1/C_data(3)(29) {-radix hexadecimal} /testbench/cic_1/C_data(3)(28) {-radix hexadecimal} /testbench/cic_1/C_data(3)(27) {-radix hexadecimal} /testbench/cic_1/C_data(3)(26) {-radix hexadecimal} /testbench/cic_1/C_data(3)(25) {-radix hexadecimal} /testbench/cic_1/C_data(3)(24) {-radix hexadecimal} /testbench/cic_1/C_data(3)(23) {-radix hexadecimal} /testbench/cic_1/C_data(3)(22) {-radix hexadecimal} /testbench/cic_1/C_data(3)(21) {-radix hexadecimal} /testbench/cic_1/C_data(3)(20) {-radix hexadecimal} /testbench/cic_1/C_data(3)(19) {-radix hexadecimal} /testbench/cic_1/C_data(3)(18) {-radix hexadecimal} /testbench/cic_1/C_data(3)(17) {-radix hexadecimal} /testbench/cic_1/C_data(3)(16) {-radix hexadecimal} /testbench/cic_1/C_data(3)(15) {-radix hexadecimal} /testbench/cic_1/C_data(3)(14) {-radix hexadecimal} /testbench/cic_1/C_data(3)(13) {-radix hexadecimal} /testbench/cic_1/C_data(3)(12) {-radix hexadecimal} /testbench/cic_1/C_data(3)(11) {-radix hexadecimal} /testbench/cic_1/C_data(3)(10) {-radix hexadecimal} /testbench/cic_1/C_data(3)(9) {-radix hexadecimal} /testbench/cic_1/C_data(3)(8) {-radix hexadecimal} /testbench/cic_1/C_data(3)(7) {-radix hexadecimal} /testbench/cic_1/C_data(3)(6) {-radix hexadecimal} /testbench/cic_1/C_data(3)(5) {-radix hexadecimal} /testbench/cic_1/C_data(3)(4) {-radix hexadecimal} /testbench/cic_1/C_data(3)(3) {-radix hexadecimal} /testbench/cic_1/C_data(3)(2) {-radix hexadecimal} /testbench/cic_1/C_data(3)(1) {-radix hexadecimal} /testbench/cic_1/C_data(3)(0) {-radix hexadecimal}} /testbench/cic_1/C_data(3) | |
|
33 | add wave -noupdate -group Literal -radix hexadecimal /testbench/cic_1/C_data(0) | |
|
34 | add wave -noupdate -group I_REG -radix hexadecimal /testbench/cic_1/I_data(1) | |
|
35 | add wave -noupdate -group I_REG -expand -group I0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(0) | |
|
36 |
add wave -noupdate -group |
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|
37 |
add wave -noupdate -group |
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|
38 |
add wave -noupdate -group |
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|
39 |
add wave -noupdate -group |
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|
40 |
add wave -noupdate -group |
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|
41 |
add wave -noupdate -group |
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|
42 |
add wave -noupdate -group |
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|
43 |
add wave -noupdate -group |
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|
44 |
add wave -noupdate -group |
|
|
45 |
add wave -noupdate -group |
|
|
46 | add wave -noupdate -group OLD -divider DEBUG | |
|
47 |
add wave -noupdate -group |
|
|
48 |
add wave -noupdate -group |
|
|
49 |
add wave -noupdate -group |
|
|
50 |
add wave -noupdate -group |
|
|
51 | add wave -noupdate -group OLD -group INPUT -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_in(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/data_in(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_in | |
|
52 |
add wave -noupdate -group |
|
|
53 | add wave -noupdate -group OLD -group SEL_INPUT -radix unsigned -childformat {{/testbench/cic_lfr_1/sel_sample(2) -radix unsigned} {/testbench/cic_lfr_1/sel_sample(1) -radix unsigned} {/testbench/cic_lfr_1/sel_sample(0) -radix unsigned}} -expand -subitemconfig {/testbench/cic_lfr_1/sel_sample(2) {-height 15 -radix unsigned} /testbench/cic_lfr_1/sel_sample(1) {-height 15 -radix unsigned} /testbench/cic_lfr_1/sel_sample(0) {-height 15 -radix unsigned}} /testbench/cic_lfr_1/sel_sample | |
|
54 |
add wave -noupdate -group |
|
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55 |
add wave -noupdate -group |
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56 |
add wave -noupdate -group |
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|
57 |
add wave -noupdate -group |
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58 |
add wave -noupdate -group |
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59 |
add wave -noupdate -group |
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|
60 |
add wave -noupdate -group |
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|
61 | add wave -noupdate -group OLD -group RAM -radix hexadecimal -childformat {{/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(0) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(1) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(2) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(3) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(4) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(5) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(6) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(7) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(8) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(9) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(10) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(11) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(12) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(13) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(14) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(15) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(16) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(17) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(18) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(19) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(20) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(21) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(22) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(23) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(24) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(25) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(26) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(27) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(28) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(29) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(30) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(31) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(32) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(33) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(34) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(35) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(36) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(37) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(38) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(39) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(40) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(41) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(42) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(43) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(44) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(45) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(46) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(47) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(48) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(49) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(50) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(51) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(52) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(53) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(54) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(55) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(56) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(57) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(58) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(59) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(60) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(61) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(62) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(63) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(64) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(65) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(66) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(67) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(68) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(69) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(70) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(71) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(72) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(73) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(74) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(75) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(76) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(77) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(78) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(79) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(80) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(81) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(82) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(83) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(84) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(85) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(86) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(87) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(88) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(89) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(90) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(91) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(92) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(93) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(94) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(95) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(96) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(97) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(98) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(99) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(100) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(101) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(102) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(103) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(104) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(105) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(106) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(107) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(108) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(109) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(110) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(111) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(112) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(113) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(114) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(115) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(116) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(117) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(118) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(119) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(120) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(121) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(122) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(123) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(124) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(125) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(126) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(127) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(128) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(129) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(130) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(131) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(132) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(133) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(134) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(135) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(136) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(137) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(138) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(139) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(140) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(141) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(142) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(143) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(144) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(145) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(146) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(147) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(148) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(149) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(150) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(151) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(152) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(153) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(154) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(155) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(156) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(157) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(158) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(159) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(160) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(161) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(162) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(163) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(164) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(165) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(166) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(167) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(168) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(169) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(170) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(171) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(172) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(173) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(174) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(175) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(176) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(177) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(178) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(179) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(180) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(181) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(182) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(183) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(184) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(185) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(186) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(187) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(188) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(189) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(190) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(191) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(192) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(193) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(194) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(195) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(196) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(197) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(198) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(199) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(200) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(201) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(202) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(203) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(204) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(205) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(206) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(207) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(208) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(209) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(210) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(211) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(212) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(213) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(214) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(215) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(216) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(217) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(218) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(219) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(220) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(221) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(222) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(223) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(224) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(225) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(226) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(227) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(228) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(229) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(230) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(231) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(232) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(233) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(234) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(235) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(236) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(237) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(238) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(239) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(240) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(241) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(242) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(243) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(244) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(245) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(246) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(247) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(248) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(249) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(250) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(251) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(252) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(253) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(254) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(255) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(0) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(1) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(2) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(3) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(4) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(5) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(6) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(7) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(8) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(9) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(10) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(11) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(12) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(13) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(14) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(15) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(16) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(17) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(18) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(19) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(20) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(21) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(22) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(23) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(24) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(25) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(26) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(27) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(28) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(29) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(30) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(31) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(32) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(33) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(34) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(35) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(36) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(37) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(38) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(39) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(40) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(41) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(42) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(43) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(44) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(45) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(46) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(47) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(48) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(49) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(50) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(51) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(52) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(53) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(54) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(55) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(56) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(57) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(58) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(59) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(60) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(61) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(62) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(63) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(64) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(65) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(66) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(67) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(68) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(69) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(70) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(71) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(72) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(73) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(74) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(75) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(76) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(77) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(78) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(79) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(80) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(81) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(82) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(83) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(84) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(85) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(86) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(87) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(88) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(89) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(90) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(91) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(92) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(93) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(94) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(95) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(96) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(97) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(98) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(99) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(100) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(101) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(102) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(103) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(104) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(105) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(106) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(107) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(108) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(109) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(110) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(111) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(112) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(113) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(114) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(115) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(116) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(117) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(118) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(119) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(120) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(121) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(122) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(123) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(124) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(125) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(126) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(127) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(128) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(129) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(130) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(131) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(132) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(133) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(134) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(135) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(136) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(137) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(138) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(139) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(140) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(141) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(142) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(143) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(144) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(145) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(146) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(147) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(148) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(149) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(150) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(151) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(152) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(153) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(154) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(155) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(156) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(157) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(158) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(159) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(160) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(161) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(162) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(163) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(164) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(165) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(166) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(167) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(168) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(169) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(170) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(171) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(172) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(173) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(174) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(175) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(176) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(177) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(178) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(179) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(180) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(181) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(182) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(183) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(184) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(185) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(186) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(187) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(188) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(189) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(190) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(191) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(192) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(193) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(194) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(195) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(196) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(197) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(198) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(199) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(200) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(201) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(202) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(203) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(204) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(205) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(206) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(207) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(208) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(209) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(210) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(211) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(212) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(213) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(214) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(215) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(216) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(217) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(218) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(219) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(220) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(221) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(222) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(223) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(224) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(225) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(226) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(227) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(228) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(229) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(230) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(231) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(232) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(233) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(234) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(235) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(236) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(237) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(238) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(239) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(240) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(241) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(242) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(243) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(244) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(245) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(246) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(247) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(248) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(249) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(250) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(251) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(252) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(253) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(254) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(255) {-radix hexadecimal}} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray | |
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add wave -noupdate -group |
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add wave -noupdate -group |
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add wave -noupdate -group |
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add wave -noupdate -group |
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add wave -noupdate -group |
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add wave -noupdate -group |
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68 | add wave -noupdate -group OLD /testbench/cic_lfr_1/cic_lfr_address_gen_1/addr_base | |
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69 | add wave -noupdate -group OLD /testbench/cic_lfr_1/cic_lfr_address_gen_1/addr_init | |
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70 | add wave -noupdate -group OLD /testbench/cic_lfr_1/cic_lfr_address_gen_1/addr_add_1 | |
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add wave -noupdate -group |
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72 | add wave -noupdate -group OLD -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/sample_out_reg16(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg16 | |
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add wave -noupdate -group |
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add wave -noupdate -group |
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add wave -noupdate -group |
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add wave -noupdate -group |
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add wave -noupdate -group |
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80 | add wave -noupdate -expand -group CIC_LFR -group CONTROL /testbench/cic_lfr_1/cic_lfr_control_1/STATE_CIC_LFR | |
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81 | add wave -noupdate -expand -group CIC_LFR -group CONTROL /testbench/cic_lfr_1/cic_lfr_control_1/current_channel | |
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82 | add wave -noupdate -expand -group CIC_LFR -group CONTROL /testbench/cic_lfr_1/cic_lfr_control_1/current_cmd | |
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83 | add wave -noupdate -expand -group CIC_LFR -group SEL_SAMPLE /testbench/cic_lfr_1/sel_sample | |
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add wave -noupdate - |
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91 | add wave -noupdate -expand -group CIC_LFR -group ALU /testbench/cic_lfr_1/CARRY_POP | |
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92 |
add wave -noupdate - |
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93 |
add wave -noupdate - |
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94 | add wave -noupdate -expand -group CIC_LFR /testbench/cic_lfr_1/CARRY_PUSH | |
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add wave -noupdate -radix hexadecimal /testbench/cic_lfr_1/ |
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108 |
add wave -noupdate -radix hexadecimal /testbench/cic_lfr_1/ |
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109 | add wave -noupdate -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/data_out_16(5) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(4) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(3) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(2) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(1) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0) {-radix hexadecimal}} /testbench/cic_lfr_1/data_out_16 | |
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110 |
add wave -noupdate -radix hexadecimal /testbench/cic_lfr_1/ |
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111 |
add wave -noupdate -radix hexadecimal /testbench/cic_lfr_1/ |
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112 |
add wave -noupdate -radix hexadecimal /testbench/cic_lfr_1/ |
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11 | add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_in | |
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12 | add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_in_valid | |
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13 | add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_out | |
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14 | add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_out_valid | |
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15 | add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/I_data | |
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16 | add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/I_valid | |
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17 | add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/C_data | |
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18 | add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/C_valid | |
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19 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_in | |
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20 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_in_valid | |
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21 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_out | |
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22 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_out_valid | |
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23 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal -childformat {{/testbench/cic_1/I_data(3) -radix hexadecimal} {/testbench/cic_1/I_data(2) -radix hexadecimal} {/testbench/cic_1/I_data(1) -radix hexadecimal} {/testbench/cic_1/I_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/I_data(3) {-height 15 -radix hexadecimal} /testbench/cic_1/I_data(2) {-height 15 -radix hexadecimal} /testbench/cic_1/I_data(1) {-height 15 -radix hexadecimal} /testbench/cic_1/I_data(0) {-height 15 -radix hexadecimal}} /testbench/cic_1/I_data | |
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24 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/I_valid | |
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25 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3) -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3)(30) -radix hexadecimal} {/testbench/cic_1/C_data(3)(29) -radix hexadecimal} {/testbench/cic_1/C_data(3)(28) -radix hexadecimal} {/testbench/cic_1/C_data(3)(27) -radix hexadecimal} {/testbench/cic_1/C_data(3)(26) -radix hexadecimal} {/testbench/cic_1/C_data(3)(25) -radix hexadecimal} {/testbench/cic_1/C_data(3)(24) -radix hexadecimal} {/testbench/cic_1/C_data(3)(23) -radix hexadecimal} {/testbench/cic_1/C_data(3)(22) -radix hexadecimal} {/testbench/cic_1/C_data(3)(21) -radix hexadecimal} {/testbench/cic_1/C_data(3)(20) -radix hexadecimal} {/testbench/cic_1/C_data(3)(19) -radix hexadecimal} {/testbench/cic_1/C_data(3)(18) -radix hexadecimal} {/testbench/cic_1/C_data(3)(17) -radix hexadecimal} {/testbench/cic_1/C_data(3)(16) -radix hexadecimal} {/testbench/cic_1/C_data(3)(15) -radix hexadecimal} {/testbench/cic_1/C_data(3)(14) -radix hexadecimal} {/testbench/cic_1/C_data(3)(13) -radix hexadecimal} {/testbench/cic_1/C_data(3)(12) -radix hexadecimal} {/testbench/cic_1/C_data(3)(11) -radix hexadecimal} {/testbench/cic_1/C_data(3)(10) -radix hexadecimal} {/testbench/cic_1/C_data(3)(9) -radix hexadecimal} {/testbench/cic_1/C_data(3)(8) -radix hexadecimal} {/testbench/cic_1/C_data(3)(7) -radix hexadecimal} {/testbench/cic_1/C_data(3)(6) -radix hexadecimal} {/testbench/cic_1/C_data(3)(5) -radix hexadecimal} {/testbench/cic_1/C_data(3)(4) -radix hexadecimal} {/testbench/cic_1/C_data(3)(3) -radix hexadecimal} {/testbench/cic_1/C_data(3)(2) -radix hexadecimal} {/testbench/cic_1/C_data(3)(1) -radix hexadecimal} {/testbench/cic_1/C_data(3)(0) -radix hexadecimal}}} {/testbench/cic_1/C_data(2) -radix hexadecimal} {/testbench/cic_1/C_data(1) -radix hexadecimal} {/testbench/cic_1/C_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/C_data(3) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3)(30) -radix hexadecimal} {/testbench/cic_1/C_data(3)(29) -radix hexadecimal} {/testbench/cic_1/C_data(3)(28) -radix hexadecimal} {/testbench/cic_1/C_data(3)(27) -radix hexadecimal} {/testbench/cic_1/C_data(3)(26) -radix hexadecimal} {/testbench/cic_1/C_data(3)(25) -radix hexadecimal} {/testbench/cic_1/C_data(3)(24) -radix hexadecimal} {/testbench/cic_1/C_data(3)(23) -radix hexadecimal} {/testbench/cic_1/C_data(3)(22) -radix hexadecimal} {/testbench/cic_1/C_data(3)(21) -radix hexadecimal} {/testbench/cic_1/C_data(3)(20) -radix hexadecimal} {/testbench/cic_1/C_data(3)(19) -radix hexadecimal} {/testbench/cic_1/C_data(3)(18) -radix hexadecimal} {/testbench/cic_1/C_data(3)(17) -radix hexadecimal} {/testbench/cic_1/C_data(3)(16) -radix hexadecimal} {/testbench/cic_1/C_data(3)(15) -radix hexadecimal} {/testbench/cic_1/C_data(3)(14) -radix hexadecimal} {/testbench/cic_1/C_data(3)(13) -radix hexadecimal} {/testbench/cic_1/C_data(3)(12) -radix hexadecimal} {/testbench/cic_1/C_data(3)(11) -radix hexadecimal} {/testbench/cic_1/C_data(3)(10) -radix hexadecimal} {/testbench/cic_1/C_data(3)(9) -radix hexadecimal} {/testbench/cic_1/C_data(3)(8) -radix hexadecimal} {/testbench/cic_1/C_data(3)(7) -radix hexadecimal} {/testbench/cic_1/C_data(3)(6) -radix hexadecimal} {/testbench/cic_1/C_data(3)(5) -radix hexadecimal} {/testbench/cic_1/C_data(3)(4) -radix hexadecimal} {/testbench/cic_1/C_data(3)(3) -radix hexadecimal} {/testbench/cic_1/C_data(3)(2) -radix hexadecimal} {/testbench/cic_1/C_data(3)(1) -radix hexadecimal} {/testbench/cic_1/C_data(3)(0) -radix hexadecimal}}} /testbench/cic_1/C_data(3)(30) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(29) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(28) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(27) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(26) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(25) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(24) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(23) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(22) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(21) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(20) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(19) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(18) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(17) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(16) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(15) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(14) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(13) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(12) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(11) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(10) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(9) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(8) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(7) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(6) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(5) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(4) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(3) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(2) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(1) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(0) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(2) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(1) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(0) {-height 15 -radix hexadecimal}} /testbench/cic_1/C_data | |
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26 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/C_valid | |
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27 | add wave -noupdate -expand -group CIC_LFR -radix decimal -childformat {{/testbench/cic_lfr_1/data_in(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/data_in(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_in | |
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28 | add wave -noupdate -expand -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_in_valid | |
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29 | add wave -noupdate -expand -group CIC_LFR -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}}}} -expand -subitemconfig {/testbench/cic_lfr_1/data_out_16(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/data_out_16(0)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_out_16 | |
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30 | add wave -noupdate -expand -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_out_16_valid | |
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31 | add wave -noupdate -expand -group CIC_LFR -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_256(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/data_out_256(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_out_256 | |
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32 | add wave -noupdate -expand -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_out_256_valid | |
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33 | add wave -noupdate -format Analog-Step -height 74 -max 6000000.0 -min 6.0000000000000002e-06 -radix decimal /testbench/cic_lfr_1/sample_out_reg16_s(0) | |
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34 | add wave -noupdate -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal /testbench/cic_1/data_out | |
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35 | add wave -noupdate -group temp -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/data_out_16(0)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_out_16(0) | |
|
36 | add wave -noupdate -group temp -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(0) -radix hexadecimal}}} {/testbench/cic_lfr_1/sample_out_reg16_s(4) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(4)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(0) -radix hexadecimal}}} {/testbench/cic_lfr_1/sample_out_reg16_s(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/sample_out_reg16_s(5) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/sample_out_reg16_s(5)(31) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(30) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(29) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(28) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(27) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(26) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(25) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(24) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(23) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(22) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(21) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(20) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(19) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(18) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(17) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(16) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(0) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(4)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/sample_out_reg16_s(4)(31) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(30) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(29) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(28) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(27) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(26) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(25) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(24) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(23) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(22) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(21) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(20) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(19) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(18) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(17) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(16) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(0) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg16_s | |
|
37 | add wave -noupdate -group temp -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg256_s(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/sample_out_reg256_s(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg256_s | |
|
38 | add wave -noupdate -group temp -format Analog-Step -height 74 -max 6000000.0 -min 6.0000000000000002e-06 -radix decimal /testbench/cic_lfr_1/sample_out_reg16_s(0) | |
|
39 | add wave -noupdate -group temp -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal /testbench/cic_1/data_out | |
|
40 | add wave -noupdate -radix hexadecimal -childformat {{/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(0) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(1) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(2) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(3) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(4) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(5) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(6) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(7) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(8) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(9) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(10) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(11) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(12) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(13) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(14) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(15) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(16) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(17) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(18) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(19) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(20) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(21) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(22) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(23) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(24) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(25) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(26) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(27) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(28) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(29) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(30) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(31) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(32) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(33) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(34) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(35) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(36) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(37) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(38) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(39) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(40) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(41) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(42) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(43) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(44) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(45) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(46) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(47) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(48) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(49) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(50) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(51) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(52) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(53) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(54) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(55) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(56) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(57) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(58) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(59) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(60) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(61) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(62) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(63) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(64) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(65) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(66) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(67) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(68) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(69) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(70) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(71) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(72) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(73) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(74) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(75) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(76) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(77) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(78) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(79) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(80) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(81) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(82) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(83) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(84) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(85) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(86) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(87) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(88) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(89) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(90) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(91) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(92) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(93) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(94) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(95) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(96) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(97) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(98) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(99) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(100) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(101) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(102) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(103) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(104) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(105) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(106) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(107) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(108) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(109) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(110) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(111) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(112) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(113) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(114) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(115) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(116) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(117) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(118) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(119) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(120) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(121) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(122) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(123) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(124) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(125) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(126) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(127) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(128) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(129) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(130) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(131) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(132) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(133) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(134) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(135) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(136) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(137) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(138) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(139) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(140) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(141) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(142) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(143) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(144) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(145) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(146) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(147) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(148) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(149) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(150) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(151) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(152) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(153) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(154) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(155) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(156) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(157) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(158) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(159) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(160) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(161) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(162) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(163) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(164) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(165) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(166) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(167) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(168) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(169) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(170) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(171) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(172) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(173) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(174) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(175) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(176) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(177) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(178) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(179) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(180) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(181) -radix hexadecimal} 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/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(105) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(106) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(107) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(108) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(109) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(110) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(111) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(112) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(113) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(114) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(115) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(116) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(117) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(118) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(119) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(120) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(121) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(122) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(123) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(124) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(125) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(126) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(127) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(128) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(129) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(130) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(131) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(132) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(133) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(134) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(135) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(136) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(137) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(138) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(139) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(140) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(141) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(142) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(143) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(144) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(145) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(146) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(147) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(148) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(149) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(150) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(151) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(152) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(153) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(154) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(155) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(156) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(157) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(158) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(159) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(160) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(161) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(162) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(163) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(164) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(165) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(166) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(167) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(168) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(169) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(170) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(171) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(172) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(173) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(174) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(175) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(176) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(177) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(178) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(179) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(180) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(181) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(182) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(183) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(184) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(185) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(186) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(187) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(188) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(189) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(190) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(191) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(192) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(193) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(194) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(195) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(196) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(197) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(198) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(199) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(200) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(201) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(202) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(203) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(204) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(205) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(206) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(207) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(208) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(209) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(210) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(211) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(212) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(213) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(214) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(215) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(216) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(217) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(218) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(219) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(220) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(221) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(222) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(223) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(224) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(225) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(226) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(227) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(228) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(229) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(230) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(231) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(232) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(233) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(234) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(235) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(236) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(237) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(238) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(239) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(240) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(241) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(242) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(243) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(244) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(245) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(246) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(247) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(248) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(249) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(250) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(251) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(252) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(253) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(254) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(255) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray | |
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41 | add wave -noupdate -radix decimal -childformat {{/testbench/cic_lfr_r2_1/data_out_16(5) -radix hexadecimal} {/testbench/cic_lfr_r2_1/data_out_16(4) -radix hexadecimal} {/testbench/cic_lfr_r2_1/data_out_16(3) -radix hexadecimal} {/testbench/cic_lfr_r2_1/data_out_16(2) -radix hexadecimal} {/testbench/cic_lfr_r2_1/data_out_16(1) -radix hexadecimal} {/testbench/cic_lfr_r2_1/data_out_16(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_r2_1/data_out_16(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_r2_1/data_out_16(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_r2_1/data_out_16(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_r2_1/data_out_16(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_r2_1/data_out_16(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_r2_1/data_out_16(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_r2_1/data_out_16 | |
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42 | add wave -noupdate -radix decimal -childformat {{/testbench/cic_lfr_r2_1/data_out_256(5) -radix decimal} {/testbench/cic_lfr_r2_1/data_out_256(4) -radix decimal} {/testbench/cic_lfr_r2_1/data_out_256(3) -radix decimal} {/testbench/cic_lfr_r2_1/data_out_256(2) -radix decimal} {/testbench/cic_lfr_r2_1/data_out_256(1) -radix decimal} {/testbench/cic_lfr_r2_1/data_out_256(0) -radix decimal}} -expand -subitemconfig {/testbench/cic_lfr_r2_1/data_out_256(5) {-height 15 -radix decimal} /testbench/cic_lfr_r2_1/data_out_256(4) {-height 15 -radix decimal} /testbench/cic_lfr_r2_1/data_out_256(3) {-height 15 -radix decimal} /testbench/cic_lfr_r2_1/data_out_256(2) {-height 15 -radix decimal} /testbench/cic_lfr_r2_1/data_out_256(1) {-height 15 -radix decimal} /testbench/cic_lfr_r2_1/data_out_256(0) {-height 15 -radix decimal}} /testbench/cic_lfr_r2_1/data_out_256 | |
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43 | add wave -noupdate /testbench/param_r2 | |
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44 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(0) | |
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45 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(1) | |
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46 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(2) | |
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47 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(3) | |
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48 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(4) | |
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49 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(5) | |
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50 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(6) | |
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51 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(7) | |
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52 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(8) | |
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53 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(9) | |
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54 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(10) | |
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55 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(11) | |
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56 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(12) | |
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57 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(13) | |
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58 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(14) | |
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59 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(15) | |
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60 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(16) | |
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61 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(17) | |
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62 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(18) | |
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63 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(19) | |
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64 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(20) | |
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65 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(21) | |
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66 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(22) | |
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67 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(23) | |
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68 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(24) | |
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69 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(25) | |
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70 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(26) | |
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71 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(27) | |
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72 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(28) | |
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73 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(29) | |
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74 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(30) | |
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75 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(31) | |
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76 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(32) | |
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77 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(33) | |
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78 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(34) | |
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79 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(35) | |
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80 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(36) | |
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81 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(37) | |
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82 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(38) | |
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83 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(39) | |
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84 | add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(40) | |
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85 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(40) | |
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86 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(41) | |
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87 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(42) | |
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88 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(43) | |
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89 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(44) | |
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90 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(45) | |
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91 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(46) | |
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92 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(47) | |
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93 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(48) | |
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94 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(49) | |
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95 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(50) | |
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96 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(51) | |
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97 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(52) | |
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98 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(53) | |
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99 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(54) | |
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100 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(55) | |
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101 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(56) | |
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102 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(57) | |
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103 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(58) | |
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104 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(59) | |
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105 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(60) | |
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106 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(61) | |
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107 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(62) | |
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108 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(63) | |
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109 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(64) | |
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110 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(65) | |
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111 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(66) | |
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112 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(67) | |
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113 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(68) | |
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114 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(69) | |
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115 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(70) | |
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116 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(71) | |
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117 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(72) | |
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118 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(73) | |
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119 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(74) | |
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120 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(75) | |
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121 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(76) | |
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122 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(77) | |
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123 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(78) | |
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124 | add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(79) | |
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125 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(80) | |
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126 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(81) | |
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127 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(82) | |
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128 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(83) | |
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129 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(84) | |
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130 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(85) | |
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131 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(86) | |
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132 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(87) | |
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133 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(88) | |
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134 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(89) | |
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135 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(90) | |
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136 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(91) | |
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137 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(92) | |
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138 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(93) | |
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139 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(94) | |
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140 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(95) | |
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141 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(96) | |
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142 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(97) | |
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143 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(98) | |
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144 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(99) | |
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145 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(100) | |
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146 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(101) | |
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147 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(102) | |
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148 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(103) | |
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149 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(104) | |
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150 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(105) | |
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151 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(106) | |
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152 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(107) | |
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153 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(108) | |
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154 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(109) | |
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155 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(110) | |
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156 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(111) | |
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157 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(112) | |
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158 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(113) | |
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159 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(114) | |
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160 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(115) | |
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161 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(116) | |
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162 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(117) | |
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163 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(118) | |
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164 | add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(119) | |
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165 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(120) | |
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166 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(121) | |
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167 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(122) | |
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168 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(123) | |
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169 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(124) | |
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170 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(125) | |
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171 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(126) | |
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172 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(127) | |
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173 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(128) | |
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174 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(129) | |
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175 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(130) | |
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176 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(131) | |
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177 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(132) | |
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178 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(133) | |
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179 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(134) | |
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180 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(135) | |
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181 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(136) | |
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182 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(137) | |
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183 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(138) | |
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184 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(139) | |
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185 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(140) | |
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186 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(141) | |
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187 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(142) | |
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188 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(143) | |
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189 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(144) | |
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190 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(145) | |
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191 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(146) | |
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192 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(147) | |
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193 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(148) | |
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194 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(149) | |
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195 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(150) | |
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196 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(151) | |
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197 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(152) | |
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198 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(153) | |
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199 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(154) | |
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200 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(155) | |
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201 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(156) | |
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202 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(157) | |
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203 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(158) | |
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204 | add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(159) | |
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205 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(160) | |
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206 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(161) | |
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207 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(162) | |
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208 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(163) | |
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209 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(164) | |
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210 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(165) | |
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211 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(166) | |
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212 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(167) | |
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213 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(168) | |
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214 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(169) | |
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215 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(170) | |
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216 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(171) | |
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217 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(172) | |
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218 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(173) | |
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219 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(174) | |
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220 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(175) | |
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221 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(176) | |
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222 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(177) | |
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223 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(178) | |
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224 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(179) | |
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225 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(180) | |
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226 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(181) | |
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227 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(182) | |
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228 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(183) | |
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229 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(184) | |
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230 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(185) | |
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231 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(186) | |
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232 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(187) | |
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233 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(188) | |
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234 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(189) | |
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235 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(190) | |
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236 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(191) | |
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237 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(192) | |
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238 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(193) | |
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239 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(194) | |
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240 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(195) | |
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241 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(196) | |
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242 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(197) | |
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243 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(198) | |
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244 | add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(199) | |
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245 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(200) | |
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246 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(201) | |
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247 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(202) | |
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248 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(203) | |
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249 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(204) | |
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250 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(205) | |
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251 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(206) | |
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252 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(207) | |
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253 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(208) | |
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254 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(209) | |
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255 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(210) | |
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256 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(211) | |
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257 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(212) | |
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258 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(213) | |
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259 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(214) | |
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260 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(215) | |
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261 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(216) | |
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262 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(217) | |
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263 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(218) | |
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264 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(219) | |
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265 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(220) | |
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266 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(221) | |
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267 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(222) | |
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268 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(223) | |
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269 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(224) | |
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270 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(225) | |
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271 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(226) | |
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272 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(227) | |
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273 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(228) | |
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274 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(229) | |
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275 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(230) | |
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276 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(231) | |
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277 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(232) | |
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278 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(233) | |
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279 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(234) | |
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280 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(235) | |
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281 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(236) | |
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282 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(237) | |
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283 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(238) | |
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284 | add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(239) | |
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285 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(240) | |
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286 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(241) | |
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287 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(242) | |
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288 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(243) | |
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289 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(244) | |
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290 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(245) | |
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291 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(246) | |
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292 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(247) | |
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293 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(248) | |
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294 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(249) | |
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295 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(250) | |
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296 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(251) | |
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297 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(252) | |
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298 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(253) | |
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299 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(254) | |
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300 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(255) | |
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301 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(256) | |
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302 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(257) | |
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303 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(258) | |
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304 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(259) | |
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305 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(260) | |
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306 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(261) | |
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307 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(262) | |
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308 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(263) | |
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309 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(264) | |
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310 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(265) | |
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311 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(266) | |
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312 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(267) | |
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313 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(268) | |
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314 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(269) | |
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315 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(270) | |
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316 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(271) | |
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317 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(272) | |
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318 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(273) | |
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319 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(274) | |
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320 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(275) | |
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321 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(276) | |
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322 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(277) | |
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323 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(278) | |
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324 | add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(279) | |
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325 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(280) | |
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326 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(281) | |
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327 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(282) | |
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328 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(283) | |
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329 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(284) | |
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330 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(285) | |
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331 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(286) | |
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332 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(287) | |
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333 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(288) | |
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334 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(289) | |
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335 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(290) | |
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336 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(291) | |
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337 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(292) | |
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338 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(293) | |
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339 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(294) | |
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340 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(295) | |
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341 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(296) | |
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342 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(297) | |
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343 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(298) | |
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344 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(299) | |
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345 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(300) | |
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346 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(301) | |
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347 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(302) | |
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348 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(303) | |
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349 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(304) | |
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350 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(305) | |
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351 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(306) | |
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352 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(307) | |
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353 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(308) | |
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354 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(309) | |
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355 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(310) | |
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356 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(311) | |
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357 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(312) | |
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358 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(313) | |
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359 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(314) | |
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360 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(315) | |
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361 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(316) | |
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362 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(317) | |
|
363 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(318) | |
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364 | add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(319) | |
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365 | add wave -noupdate -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray | |
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366 | add wave -noupdate -radix hexadecimal /testbench/cic_lfr_r2_1/data_out | |
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367 | add wave -noupdate /testbench/cic_lfr_r2_1/data_out_16_valid_s | |
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368 | add wave -noupdate /testbench/cic_lfr_r2_1/data_out_16_valid_s1 | |
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369 | add wave -noupdate /testbench/cic_lfr_r2_1/data_out_16_valid_s2 | |
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370 | add wave -noupdate -radix hexadecimal -childformat {{/testbench/cic_lfr_r2_1/sample_out_reg16(15) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(14) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(13) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(12) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(11) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(10) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(9) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(8) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(7) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(6) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(5) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(4) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(3) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(2) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(1) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_r2_1/sample_out_reg16(15) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(14) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(13) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(12) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(11) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(10) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(9) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(8) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(7) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(6) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(5) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(4) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(3) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(2) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(1) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(0) {-radix hexadecimal}} /testbench/cic_lfr_r2_1/sample_out_reg16 | |
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371 | add wave -noupdate -radix hexadecimal -childformat {{/testbench/cic_lfr_r2_1/sample_valid_reg16(16) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(15) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(14) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(13) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(12) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(11) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(10) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(9) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(8) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(7) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(6) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(5) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(4) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(3) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(2) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(1) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_r2_1/sample_valid_reg16(16) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(15) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(14) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(13) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(12) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(11) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(10) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(9) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(8) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(7) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(6) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(5) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(4) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(3) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(2) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(1) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(0) {-radix hexadecimal}} /testbench/cic_lfr_r2_1/sample_valid_reg16 | |
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113 | 372 | TreeUpdate [SetDefaultTree] |
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114 |
WaveRestoreCursors {{Cursor 1} { |
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373 | WaveRestoreCursors {{Cursor 1} {29237145000 ps} 0} {{Cursor 2} {514701877948 ps} 0} {{Cursor 3} {392261637 ps} 0} | |
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115 | 374 | quietly wave cursor active 1 |
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116 |
configure wave -namecolwidth 3 |
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375 | configure wave -namecolwidth 353 | |
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117 | 376 | configure wave -valuecolwidth 188 |
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118 | 377 | configure wave -justifyvalue left |
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119 | 378 | configure wave -signalnamewidth 0 |
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120 | 379 | configure wave -snapdistance 10 |
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121 | 380 | configure wave -datasetprefix 0 |
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122 | 381 | configure wave -rowmargin 4 |
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123 | 382 | configure wave -childrowmargin 2 |
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124 | 383 | configure wave -gridoffset 0 |
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125 | 384 | configure wave -gridperiod 1 |
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126 | 385 | configure wave -griddelta 40 |
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127 | 386 | configure wave -timeline 0 |
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128 | 387 | configure wave -timelineunits ns |
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129 | 388 | update |
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130 |
WaveRestoreZoom {0 ps} { |
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389 | WaveRestoreZoom {29232867077 ps} {29241429253 ps} |
@@ -1,385 +1,387 | |||
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1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | -- jean-christophe.pellion@easii-ic.com |
|
22 | 22 | ---------------------------------------------------------------------------- |
|
23 | 23 | |
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24 | 24 | LIBRARY ieee; |
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25 | 25 | USE ieee.std_logic_1164.ALL; |
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26 | 26 | USE ieee.numeric_std.all; |
|
27 | 27 | |
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28 | 28 | LIBRARY lpp; |
|
29 | 29 | USE lpp.cic_pkg.ALL; |
|
30 | 30 | USE lpp.data_type_pkg.ALL; |
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31 | 31 | USE lpp.iir_filter.ALL; |
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32 | 32 | |
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33 | 33 | LIBRARY techmap; |
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34 | 34 | USE techmap.gencomp.ALL; |
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35 | 35 | |
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36 | 36 | ENTITY cic_lfr IS |
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37 | 37 | GENERIC( |
|
38 | 38 | tech : INTEGER := 0; |
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39 | 39 | use_RAM_nCEL : INTEGER := 0 -- 1 => RAM(tech) , 0 => RAM_CEL |
|
40 | 40 | ); |
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41 | 41 | PORT ( |
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42 | 42 | clk : IN STD_LOGIC; |
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43 | 43 | rstn : IN STD_LOGIC; |
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44 | 44 | run : IN STD_LOGIC; |
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45 | 45 | |
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46 | 46 | data_in : IN sample_vector(5 DOWNTO 0,15 DOWNTO 0); |
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47 | 47 | data_in_valid : IN STD_LOGIC; |
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48 | 48 | |
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49 | 49 | data_out_16 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0); |
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50 | 50 | data_out_16_valid : OUT STD_LOGIC; |
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51 | 51 | data_out_256 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0); |
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52 | 52 | data_out_256_valid : OUT STD_LOGIC |
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53 | 53 | ); |
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54 | 54 | |
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55 | 55 | END cic_lfr; |
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56 | 56 | |
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57 | 57 | ARCHITECTURE beh OF cic_lfr IS |
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58 | 58 | -- |
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59 | 59 | SIGNAL sel_sample : STD_LOGIC_VECTOR(2 DOWNTO 0); |
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60 | 60 | SIGNAL sample_temp : sample_vector(5 DOWNTO 0,15 DOWNTO 0); |
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61 | 61 | SIGNAL sample : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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62 | 62 | -- |
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63 | 63 | SIGNAL sel_A : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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64 | 64 | SIGNAL data_A_temp : sample_vector(2 DOWNTO 0,15 DOWNTO 0); |
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65 | 65 | SIGNAL data_A : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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66 | 66 | -- |
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67 | 67 | SIGNAL ALU_OP : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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68 | 68 | SIGNAL data_B : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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69 | 69 | SIGNAL data_B_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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70 | 70 | SIGNAL data_out : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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71 | 71 | SIGNAL data_in_Carry : STD_LOGIC; |
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72 | 72 | SIGNAL data_out_Carry : STD_LOGIC; |
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73 | 73 | -- |
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74 | 74 | CONSTANT S_parameter : INTEGER := 3; |
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75 | 75 | SIGNAL carry_reg : STD_LOGIC_VECTOR(S_parameter-1 DOWNTO 0); |
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76 | 76 | SIGNAL CARRY_PUSH : STD_LOGIC; |
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77 | 77 | SIGNAL CARRY_POP : STD_LOGIC; |
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78 | 78 | -- |
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79 | 79 | |
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80 | 80 | SIGNAL OPERATION : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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81 | 81 | SIGNAL OPERATION_reg: STD_LOGIC_VECTOR(15 DOWNTO 0); |
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82 | 82 | SIGNAL OPERATION_reg2: STD_LOGIC_VECTOR(15 DOWNTO 0); |
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83 | 83 | |
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84 | 84 | ----------------------------------------------------------------------------- |
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85 | 85 | TYPE ARRAY_OF_ADDR IS ARRAY (5 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0); |
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86 | 86 | SIGNAL base_addr_INT : ARRAY_OF_ADDR; |
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87 | 87 | CONSTANT base_addr_delta : INTEGER := 40; |
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88 | 88 | SIGNAL addr_base_sel : STD_LOGIC_VECTOR(7 DOWNTO 0); |
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89 | 89 | SIGNAL addr_gen: STD_LOGIC_VECTOR(7 DOWNTO 0); |
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90 | 90 | SIGNAL addr_read: STD_LOGIC_VECTOR(7 DOWNTO 0); |
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91 | 91 | SIGNAL addr_write: STD_LOGIC_VECTOR(7 DOWNTO 0); |
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92 | 92 | SIGNAL addr_write_mux: STD_LOGIC_VECTOR(7 DOWNTO 0); |
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93 | 93 | SIGNAL addr_write_s: STD_LOGIC_VECTOR(7 DOWNTO 0); |
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94 | 94 | SIGNAL data_we: STD_LOGIC; |
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95 | 95 | SIGNAL data_we_s: STD_LOGIC; |
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96 | 96 | SIGNAL data_wen : STD_LOGIC; |
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97 | 97 | -- SIGNAL data_write : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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98 | 98 | -- SIGNAL data_read : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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99 | 99 | -- SIGNAL data_read_pre : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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100 | 100 | ----------------------------------------------------------------------------- |
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101 | 101 | SIGNAL sample_out_reg16 : sample_vector(6*2-1 DOWNTO 0, 15 DOWNTO 0); |
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102 | 102 | SIGNAL sample_out_reg256 : sample_vector(6*3-1 DOWNTO 0, 15 DOWNTO 0); |
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103 | 103 | SIGNAL sample_valid_reg16 : STD_LOGIC_VECTOR(6*2 DOWNTO 0); |
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104 | 104 | SIGNAL sample_valid_reg256: STD_LOGIC_VECTOR(6*3 DOWNTO 0); |
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105 | 105 | SIGNAL data_out_16_valid_s : STD_LOGIC; |
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106 | 106 | SIGNAL data_out_256_valid_s : STD_LOGIC; |
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107 | 107 | SIGNAL data_out_16_valid_s1 : STD_LOGIC; |
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108 | 108 | SIGNAL data_out_256_valid_s1 : STD_LOGIC; |
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109 | 109 | SIGNAL data_out_16_valid_s2 : STD_LOGIC; |
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110 | 110 | SIGNAL data_out_256_valid_s2 : STD_LOGIC; |
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111 | 111 | ----------------------------------------------------------------------------- |
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112 | 112 | SIGNAL sample_out_reg16_s : sample_vector(5 DOWNTO 0, 16*2-1 DOWNTO 0); |
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113 | 113 | SIGNAL sample_out_reg256_s : sample_vector(5 DOWNTO 0, 16*3-1 DOWNTO 0); |
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114 | 114 | ----------------------------------------------------------------------------- |
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115 | 115 | |
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116 | 116 | |
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117 | 117 | BEGIN |
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118 | 118 | |
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119 | 119 | |
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120 | 120 | PROCESS (clk, rstn) |
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121 | 121 | BEGIN -- PROCESS |
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122 | 122 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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123 | 123 | data_B_reg <= (OTHERS => '0'); |
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124 | 124 | OPERATION_reg <= (OTHERS => '0'); |
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125 | 125 | OPERATION_reg2 <= (OTHERS => '0'); |
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126 | 126 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
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127 | 127 | OPERATION_reg <= OPERATION; |
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128 | 128 | OPERATION_reg2 <= OPERATION_reg; |
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129 | 129 | data_B_reg <= data_B; |
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130 | 130 | END IF; |
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131 | 131 | END PROCESS; |
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132 | 132 | |
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133 | 133 | |
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134 | 134 | ----------------------------------------------------------------------------- |
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135 | 135 | -- SEL_SAMPLE |
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136 | 136 | ----------------------------------------------------------------------------- |
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137 | 137 | sel_sample <= OPERATION_reg(2 DOWNTO 0); |
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138 | 138 | |
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139 | 139 | all_bit: FOR I IN 15 DOWNTO 0 GENERATE |
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140 | 140 | sample_temp(0,I) <= data_in(0,I) WHEN sel_sample(0) = '0' ELSE data_in(1,I); |
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141 | 141 | sample_temp(1,I) <= data_in(2,I) WHEN sel_sample(0) = '0' ELSE data_in(3,I); |
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142 | 142 | sample_temp(2,I) <= data_in(4,I) WHEN sel_sample(0) = '0' ELSE data_in(5,I); |
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143 | 143 | |
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144 | 144 | sample_temp(4,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE sample_temp(1,I); |
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145 | 145 | sample_temp(5,I) <= sample_temp(2,I) WHEN sel_sample(1) = '0' ELSE '0'; |
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146 | 146 | |
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147 | 147 | sample(I) <= sample_temp(4,I) WHEN sel_sample(2) = '0' ELSE sample_temp(5,I); |
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148 | 148 | END GENERATE all_bit; |
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149 | 149 | |
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150 | 150 | ----------------------------------------------------------------------------- |
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151 | 151 | -- SEL_DATA_IN_A |
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152 | 152 | ----------------------------------------------------------------------------- |
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153 | 153 | sel_A <= OPERATION_reg(4 DOWNTO 3); |
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154 | 154 | |
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155 | 155 | all_data_mux_A: FOR I IN 15 DOWNTO 0 GENERATE |
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156 | 156 | data_A_temp(0,I) <= sample(I) WHEN sel_A(0) = '0' ELSE data_out(I); |
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157 | 157 | data_A_temp(1,I) <= '0' WHEN sel_A(0) = '0' ELSE sample(15); |
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158 | 158 | data_A_temp(2,I) <= data_A_temp(0,I) WHEN sel_A(1) = '0' ELSE data_A_temp(1,I); |
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159 | 159 | data_A(I) <= data_A_temp(2,I) WHEN OPERATION_reg(14) = '0' ELSE data_B_reg(I); |
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160 | 160 | END GENERATE all_data_mux_A; |
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161 | 161 | |
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162 | 162 | |
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163 | 163 | |
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164 | 164 | ----------------------------------------------------------------------------- |
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165 | 165 | -- ALU |
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166 | 166 | ----------------------------------------------------------------------------- |
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167 | 167 | ALU_OP <= OPERATION_reg(6 DOWNTO 5); |
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168 | 168 | |
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169 | 169 | ALU: cic_lfr_add_sub |
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170 | 170 | PORT MAP ( |
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171 | 171 | clk => clk, |
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172 | 172 | rstn => rstn, |
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173 | 173 | run => run, |
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174 | 174 | |
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175 | 175 | OP => ALU_OP, |
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176 | 176 | |
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177 | 177 | data_in_A => data_A, |
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178 | 178 | data_in_B => data_B, |
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179 | 179 | data_in_Carry => data_in_Carry, |
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180 | 180 | |
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181 | 181 | data_out => data_out, |
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182 | 182 | data_out_Carry => data_out_Carry); |
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183 | 183 | |
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184 | 184 | ----------------------------------------------------------------------------- |
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185 | 185 | -- CARRY_MANAGER |
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186 | 186 | ----------------------------------------------------------------------------- |
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187 | 187 | data_in_Carry <= carry_reg(S_parameter-2) WHEN OPERATION_reg(7) = '0' ELSE carry_reg(S_parameter-1); |
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188 | 188 | |
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189 | 189 | -- CARRY_PUSH <= OPERATION_reg(7); |
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190 | 190 | -- CARRY_POP <= OPERATION_reg(6); |
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191 | 191 | |
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192 | 192 | PROCESS (clk, rstn) |
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193 | 193 | BEGIN -- PROCESS |
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194 | 194 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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195 | 195 | carry_reg <= (OTHERS => '0'); |
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196 | 196 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
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197 | 197 | --IF CARRY_POP = '1' OR CARRY_PUSH = '1' THEN |
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198 | 198 | carry_reg(S_parameter-1 DOWNTO 1) <= carry_reg(S_parameter-2 DOWNTO 0); |
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199 | 199 | carry_reg(0) <= data_out_Carry; |
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200 | 200 | --END IF; |
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201 | 201 | END IF; |
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202 | 202 | END PROCESS; |
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203 | 203 | |
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204 | 204 | ----------------------------------------------------------------------------- |
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205 | 205 | -- MEMORY |
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206 | 206 | ----------------------------------------------------------------------------- |
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207 | 207 | all_channel: FOR I IN 5 DOWNTO 0 GENERATE |
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208 | 208 | all_bit: FOR J IN 7 DOWNTO 0 GENERATE |
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209 | 209 | base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0'; |
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210 | 210 | END GENERATE all_bit; |
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211 | 211 | END GENERATE all_channel; |
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212 | 212 | addr_base_sel <= base_addr_INT(to_integer(UNSIGNED(OPERATION(2 DOWNTO 0)))); |
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213 | 213 | |
|
214 |
|
|
|
215 |
|
|
|
216 | clk => clk, | |
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217 | rstn => rstn, | |
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218 |
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|
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219 | ||
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220 | addr_base => addr_base_sel, | |
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221 | addr_init => OPERATION(8), | |
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222 | addr_add_1 => OPERATION(9), | |
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223 | addr => addr_gen); | |
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214 | cic_lfr_address_gen_1: cic_lfr_address_gen | |
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215 | GENERIC MAP ( | |
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216 | ADDR_SIZE => 8 ) | |
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217 | PORT MAP ( | |
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218 | clk => clk, | |
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219 | rstn => rstn, | |
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220 | run => run, | |
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221 | ||
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222 | addr_base => addr_base_sel, | |
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223 | addr_init => OPERATION(8), | |
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224 | addr_add_1 => OPERATION(9), | |
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225 | addr => addr_gen); | |
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224 | 226 | |
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225 | 227 | |
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226 | 228 | addr_read <= addr_gen WHEN OPERATION(12 DOWNTO 10) = "000" ELSE |
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227 | 229 | STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+2,8)) WHEN OPERATION(12 DOWNTO 10) = "001" ELSE |
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228 | 230 | STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+5,8)) WHEN OPERATION(12 DOWNTO 10) = "010" ELSE |
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229 | 231 | STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+8,8)) WHEN OPERATION(12 DOWNTO 10) = "011" ELSE |
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230 | 232 | STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen ))+6,8)) WHEN OPERATION(12 DOWNTO 10) = "100" ELSE |
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231 | 233 | STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen ))+15,8)); |
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232 | 234 | |
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233 | 235 | PROCESS (clk, rstn) |
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234 | 236 | BEGIN -- PROCESS |
|
235 | 237 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
236 | 238 | addr_write <= (OTHERS => '0'); |
|
237 | 239 | data_we <= '0'; |
|
238 | 240 | addr_write_s <= (OTHERS => '0'); |
|
239 | 241 | data_we_s <= '0'; |
|
240 | 242 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
241 | 243 | addr_write_s <= addr_read; |
|
242 | 244 | data_we_s <= OPERATION(13); |
|
243 | 245 | IF OPERATION_reg(15) = '0' THEN |
|
244 | 246 | addr_write <= addr_write_s; |
|
245 | 247 | ELSE |
|
246 | 248 | addr_write <= addr_read; |
|
247 | 249 | END IF; |
|
248 | 250 | data_we <= data_we_s; |
|
249 | 251 | END IF; |
|
250 | 252 | END PROCESS; |
|
251 | 253 | |
|
252 | 254 | memCEL : IF use_RAM_nCEL = 0 GENERATE |
|
253 | 255 | data_wen <= NOT data_we; |
|
254 | 256 | RAMblk : RAM_CEL |
|
255 | 257 | GENERIC MAP(16, 8) |
|
256 | 258 | PORT MAP( |
|
257 | 259 | WD => data_out, |
|
258 | 260 | RD => data_B, |
|
259 | 261 | WEN => data_wen, |
|
260 | 262 | REN => '0', |
|
261 | 263 | WADDR => addr_write, |
|
262 | 264 | RADDR => addr_read, |
|
263 | 265 | RWCLK => clk, |
|
264 | 266 | RESET => rstn |
|
265 | 267 | ) ; |
|
266 | 268 | END GENERATE; |
|
267 | 269 | |
|
268 | 270 | memRAM : IF use_RAM_nCEL = 1 GENERATE |
|
269 | 271 | SRAM : syncram_2p |
|
270 | 272 | GENERIC MAP(tech, 8, 16) |
|
271 | 273 | PORT MAP(clk, '1', addr_read, data_B, |
|
272 | 274 | clk, data_we, addr_write, data_out); |
|
273 | 275 | END GENERATE; |
|
274 | 276 | |
|
275 | 277 | ----------------------------------------------------------------------------- |
|
276 | 278 | -- CONTROL |
|
277 | 279 | ----------------------------------------------------------------------------- |
|
278 | 280 | cic_lfr_control_1: cic_lfr_control |
|
279 | 281 | PORT MAP ( |
|
280 | 282 | clk => clk, |
|
281 | 283 | rstn => rstn, |
|
282 | 284 | run => run, |
|
283 | 285 | data_in_valid => data_in_valid, |
|
284 | 286 | data_out_16_valid => data_out_16_valid_s, |
|
285 | 287 | data_out_256_valid => data_out_256_valid_s, |
|
286 | 288 | OPERATION => OPERATION); |
|
287 | 289 | |
|
288 | 290 | ----------------------------------------------------------------------------- |
|
289 | 291 | PROCESS (clk, rstn) |
|
290 | 292 | BEGIN -- PROCESS |
|
291 | 293 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
292 | 294 | data_out_16_valid_s1 <= '0'; |
|
293 | 295 | data_out_256_valid_s1 <= '0'; |
|
294 | 296 | data_out_16_valid_s2 <= '0'; |
|
295 | 297 | data_out_256_valid_s2 <= '0'; |
|
296 | 298 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
297 | 299 | data_out_16_valid_s1 <= data_out_16_valid_s; |
|
298 | 300 | data_out_256_valid_s1 <= data_out_256_valid_s; |
|
299 | 301 | data_out_16_valid_s2 <= data_out_16_valid_s1; |
|
300 | 302 | data_out_256_valid_s2 <= data_out_256_valid_s1; |
|
301 | 303 | END IF; |
|
302 | 304 | END PROCESS; |
|
303 | 305 | |
|
304 | 306 | PROCESS (clk, rstn) |
|
305 | 307 | BEGIN -- PROCESS |
|
306 | 308 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
307 | 309 | sample_valid_reg16 <= '0' & "000000" & "000001"; |
|
308 | 310 | sample_valid_reg256 <= '0' & "000000" & "000000" & "000001"; |
|
309 | 311 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
310 | 312 | IF run = '0' THEN |
|
311 | 313 | sample_valid_reg16 <= '0' & "000000" & "000001"; |
|
312 | 314 | sample_valid_reg256 <= '0' & "000000" & "000000" & "000001"; |
|
313 | 315 | ELSE |
|
314 | 316 | IF data_out_16_valid_s2 = '1' OR sample_valid_reg16(6*2) = '1' THEN |
|
315 | 317 | sample_valid_reg16 <= sample_valid_reg16(6*2-1 DOWNTO 0) & sample_valid_reg16(6*2); |
|
316 | 318 | END IF; |
|
317 | 319 | IF data_out_256_valid_s2 = '1' OR sample_valid_reg256(6*3) = '1' THEN |
|
318 | 320 | sample_valid_reg256 <= sample_valid_reg256(6*3-1 DOWNTO 0) & sample_valid_reg256(6*3); |
|
319 | 321 | END IF; |
|
320 | 322 | END IF; |
|
321 | 323 | END IF; |
|
322 | 324 | END PROCESS; |
|
323 | 325 | |
|
324 | 326 | data_out_16_valid <= sample_valid_reg16(6*2); |
|
325 | 327 | data_out_256_valid <= sample_valid_reg256(6*3); |
|
326 | 328 | |
|
327 | 329 | ----------------------------------------------------------------------------- |
|
328 | 330 | |
|
329 | 331 | all_bits: FOR J IN 15 DOWNTO 0 GENERATE |
|
330 | 332 | all_channel_out16: FOR I IN 6*2-1 DOWNTO 0 GENERATE |
|
331 | 333 | PROCESS (clk, rstn) |
|
332 | 334 | BEGIN -- PROCESS |
|
333 | 335 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
334 | 336 | sample_out_reg16(I,J) <= '0'; |
|
335 | 337 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
336 | 338 | IF run = '0' THEN |
|
337 | 339 | sample_out_reg16(I,J) <= '0'; |
|
338 | 340 | ELSE |
|
339 | 341 | IF sample_valid_reg16(I) = '1' AND data_out_16_valid_s2 = '1' THEN |
|
340 | 342 | sample_out_reg16(I,J) <= data_out(J); |
|
341 | 343 | END IF; |
|
342 | 344 | END IF; |
|
343 | 345 | END IF; |
|
344 | 346 | END PROCESS; |
|
345 | 347 | END GENERATE all_channel_out16; |
|
346 | 348 | |
|
347 | 349 | all_channel_out256: FOR I IN 6*3-1 DOWNTO 0 GENERATE |
|
348 | 350 | PROCESS (clk, rstn) |
|
349 | 351 | BEGIN -- PROCESS |
|
350 | 352 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
351 | 353 | sample_out_reg256(I,J) <= '0'; |
|
352 | 354 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
353 | 355 | IF run = '0' THEN |
|
354 | 356 | sample_out_reg256(I,J) <= '0'; |
|
355 | 357 | ELSE |
|
356 | 358 | IF sample_valid_reg256(I) = '1' AND data_out_256_valid_s2 = '1' THEN |
|
357 | 359 | sample_out_reg256(I,J) <= data_out(J); |
|
358 | 360 | END IF; |
|
359 | 361 | END IF; |
|
360 | 362 | END IF; |
|
361 | 363 | END PROCESS; |
|
362 | 364 | END GENERATE all_channel_out256; |
|
363 | 365 | END GENERATE all_bits; |
|
364 | 366 | |
|
365 | 367 | |
|
366 | 368 | all_channel_out: FOR I IN 5 DOWNTO 0 GENERATE |
|
367 | 369 | all_bits: FOR J IN 15 DOWNTO 0 GENERATE |
|
368 | 370 | all_reg_16: FOR K IN 1 DOWNTO 0 GENERATE |
|
369 | 371 | sample_out_reg16_s(I,J+(K*16)) <= sample_out_reg16(2*I+K,J); |
|
370 | 372 | END GENERATE all_reg_16; |
|
371 | 373 | all_reg_256: FOR K IN 2 DOWNTO 0 GENERATE |
|
372 | 374 | sample_out_reg256_s(I,J+(K*16)) <= sample_out_reg256(3*I+K,J); |
|
373 | 375 | END GENERATE all_reg_256; |
|
374 | 376 | END GENERATE all_bits; |
|
375 | 377 | END GENERATE all_channel_out; |
|
376 | 378 | |
|
377 | 379 | all_channel_out_v: FOR I IN 5 DOWNTO 0 GENERATE |
|
378 | 380 | all_bits: FOR J IN 15 DOWNTO 0 GENERATE |
|
379 | 381 | data_out_256(I,J) <= sample_out_reg256_s(I,J+16*2-32+27); |
|
380 | 382 | data_out_16(I,J) <= sample_out_reg16_s (I,J+16 -16+15); |
|
381 | 383 | END GENERATE all_bits; |
|
382 | 384 | END GENERATE all_channel_out_v; |
|
383 | 385 | |
|
384 | 386 | END beh; |
|
385 | 387 |
@@ -1,69 +1,72 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | -- jean-christophe.pellion@easii-ic.com |
|
22 | 22 | ---------------------------------------------------------------------------- |
|
23 | 23 | |
|
24 | 24 | LIBRARY ieee; |
|
25 | 25 | USE ieee.std_logic_1164.ALL; |
|
26 |
USE ieee.numeric_std. |
|
|
26 | USE ieee.numeric_std.ALL; | |
|
27 | 27 | |
|
28 | 28 | LIBRARY lpp; |
|
29 | 29 | USE lpp.cic_pkg.ALL; |
|
30 | 30 | USE lpp.data_type_pkg.ALL; |
|
31 | 31 | |
|
32 |
ENTITY cic_lfr_address_gen IS |
|
|
32 | ENTITY cic_lfr_address_gen IS | |
|
33 | GENERIC ( | |
|
34 | ADDR_SIZE : INTEGER := 8 | |
|
35 | ); | |
|
33 | 36 | PORT ( |
|
34 |
clk |
|
|
35 |
rstn |
|
|
36 |
run |
|
|
37 | clk : IN STD_LOGIC; | |
|
38 | rstn : IN STD_LOGIC; | |
|
39 | run : IN STD_LOGIC; | |
|
37 | 40 | |
|
38 |
addr_base |
|
|
39 |
addr_init |
|
|
40 |
addr_add_1 |
|
|
41 | ||
|
42 |
addr |
|
|
41 | addr_base : IN STD_LOGIC_VECTOR(ADDR_SIZE-1 DOWNTO 0); | |
|
42 | addr_init : IN STD_LOGIC; | |
|
43 | addr_add_1 : IN STD_LOGIC; | |
|
44 | ||
|
45 | addr : OUT STD_LOGIC_VECTOR(ADDR_SIZE-1 DOWNTO 0) | |
|
43 | 46 | ); |
|
44 | 47 | END cic_lfr_address_gen; |
|
45 | 48 | |
|
46 | 49 | ARCHITECTURE beh OF cic_lfr_address_gen IS |
|
47 |
SIGNAL address_reg_s : STD_LOGIC_VECTOR( |
|
|
48 |
SIGNAL address_reg : STD_LOGIC_VECTOR( |
|
|
50 | SIGNAL address_reg_s : STD_LOGIC_VECTOR(ADDR_SIZE-1 DOWNTO 0); | |
|
51 | SIGNAL address_reg : STD_LOGIC_VECTOR(ADDR_SIZE-1 DOWNTO 0); | |
|
49 | 52 | BEGIN |
|
50 | 53 | |
|
51 | 54 | PROCESS (clk, rstn) |
|
52 | 55 | BEGIN -- PROCESS |
|
53 | 56 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
54 | 57 | address_reg <= (OTHERS => '0'); |
|
55 |
ELSIF clk' |
|
|
58 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
56 | 59 | address_reg <= address_reg_s; |
|
57 | 60 | END IF; |
|
58 | 61 | END PROCESS; |
|
59 | 62 | |
|
60 |
address_reg_s <= (OTHERS => '0') |
|
|
61 |
STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(address_reg)) + 1, |
|
|
62 |
STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base)) + 1, |
|
|
63 | addr_base WHEN addr_add_1 = '0' AND addr_init = '1' ELSE | |
|
63 | address_reg_s <= (OTHERS => '0') WHEN run = '0' ELSE | |
|
64 | STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(address_reg)) + 1, ADDR_SIZE)) WHEN addr_add_1 = '1' AND addr_init = '0' ELSE | |
|
65 | STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base)) + 1, ADDR_SIZE)) WHEN addr_add_1 = '1' AND addr_init = '1' ELSE | |
|
66 | addr_base WHEN addr_add_1 = '0' AND addr_init = '1' ELSE | |
|
64 | 67 | address_reg; |
|
65 | 68 | |
|
66 | 69 | addr <= address_reg WHEN addr_init = '0' ELSE addr_base; |
|
67 | ||
|
70 | ||
|
68 | 71 | END beh; |
|
69 | 72 |
@@ -1,249 +1,251 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | -- jean-christophe.pellion@easii-ic.com |
|
22 | 22 | ---------------------------------------------------------------------------- |
|
23 | 23 | |
|
24 | 24 | LIBRARY ieee; |
|
25 | 25 | USE ieee.std_logic_1164.ALL; |
|
26 | 26 | USE ieee.numeric_std.ALL; |
|
27 | 27 | |
|
28 | 28 | |
|
29 | 29 | LIBRARY lpp; |
|
30 | 30 | USE lpp.cic_pkg.ALL; |
|
31 | 31 | USE lpp.data_type_pkg.ALL; |
|
32 | 32 | |
|
33 | 33 | ENTITY cic_lfr_control IS |
|
34 | 34 | PORT ( |
|
35 | 35 | clk : IN STD_LOGIC; |
|
36 | 36 | rstn : IN STD_LOGIC; |
|
37 | 37 | run : IN STD_LOGIC; |
|
38 | 38 | -- |
|
39 | 39 | data_in_valid : IN STD_LOGIC; |
|
40 | 40 | data_out_16_valid : OUT STD_LOGIC; |
|
41 | 41 | data_out_256_valid : OUT STD_LOGIC; |
|
42 | 42 | -- |
|
43 | 43 | OPERATION : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) |
|
44 | 44 | ); |
|
45 | 45 | |
|
46 | 46 | END cic_lfr_control; |
|
47 | 47 | |
|
48 | 48 | ARCHITECTURE beh OF cic_lfr_control IS |
|
49 | 49 | |
|
50 | 50 | TYPE STATE_CIC_LFR_TYPE IS (IDLE, |
|
51 | 51 | RUN_PROG_I, |
|
52 | 52 | RUN_PROG_C16, |
|
53 | 53 | RUN_PROG_C256 |
|
54 | 54 | ); |
|
55 | 55 | |
|
56 | 56 | SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE; |
|
57 | 57 | |
|
58 | 58 | SIGNAL nb_data_receipt : INTEGER := 0; |
|
59 | 59 | SIGNAL current_cmd : INTEGER := 0; |
|
60 | 60 | SIGNAL current_channel : INTEGER := 0; |
|
61 | 61 | SIGNAL sample_16_odd : STD_LOGIC; |
|
62 | 62 | SIGNAL sample_256_odd : STD_LOGIC; |
|
63 | 63 | |
|
64 | 64 | TYPE PROGRAM_ARRAY IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(13 DOWNTO 0); |
|
65 | 65 | --OPERATION( 8 DOWNTO 0) <= PROGRAM_ARRAY( 8 DOWNTO 0) sauf pour PROG_I(0) |
|
66 | 66 | --OPERATION(13 DOWNTO 12) <= PROGRAM_ARRAY(10 DOWNTO 9) |
|
67 | 67 | --OPERATION(11 DOWNTO 9) <= current_channel |
|
68 | 68 | --OPERATION(14) <= PROGRAM_ARRAY(11) selon sample_X_odd et l'etat |
|
69 | 69 | CONSTANT PROG : PROGRAM_ARRAY(0 TO 28) := |
|
70 | 70 | ( |
|
71 | 71 | -- DCBA 98765 43210 |
|
72 | 72 | --PROG I------------------ |
|
73 | 73 | "0001" & "00011" & "00000", --0 |
|
74 | 74 | "0101" & "00010" & "00001", --1 |
|
75 | 75 | "0101" & "00010" & "00001", --2 |
|
76 | 76 | "0001" & "00010" & "01011", --3 |
|
77 | 77 | "0101" & "00010" & "01001", --4 |
|
78 | 78 | "0101" & "00010" & "01001", --5 |
|
79 | 79 | "0001" & "00010" & "01011", --6 |
|
80 | 80 | "0101" & "00010" & "01001", --7 |
|
81 | 81 | "0101" & "00010" & "01001", --8 |
|
82 | 82 | --PROG_C16 |
|
83 | 83 | "1001" & "00100" & "10010", --9 |
|
84 | 84 | "1001" & "10010" & "10101", --10 |
|
85 | 85 | "1001" & "10010" & "10101", --11 |
|
86 | 86 | "1010" & "10010" & "10101", --12 |
|
87 | 87 | "1001" & "01000" & "10010", --13 |
|
88 | 88 | "1001" & "10010" & "11101", --14 |
|
89 | 89 | "1001" & "10010" & "11101", --15 |
|
90 | 90 | "1010" & "10010" & "11101", --16 |
|
91 | 91 | --PROG_C256 |
|
92 | 92 | "1001" & "00100" & "10010", --17 |
|
93 | 93 | "1001" & "10110" & "10101", --18 |
|
94 | 94 | "1001" & "10110" & "10101", --19 |
|
95 | 95 | "1010" & "10110" & "10101", --20 |
|
96 | 96 | "1001" & "01000" & "10010", --21 |
|
97 | 97 | "1001" & "10110" & "11101", --22 |
|
98 | 98 | "1001" & "10110" & "11101", --23 |
|
99 | 99 | "1010" & "10110" & "11101", --24 |
|
100 | 100 | "1001" & "01100" & "10010", --25 |
|
101 | 101 | "1001" & "10110" & "11101", --26 |
|
102 | 102 | "1001" & "10110" & "11101", --27 |
|
103 | 103 | "1010" & "10110" & "11101" --28 |
|
104 | 104 | ); |
|
105 | 105 | |
|
106 | 106 | |
|
107 | 107 | CONSTANT PROG_START_I : INTEGER := 0; |
|
108 | 108 | CONSTANT PROG_END_I : INTEGER := 8; |
|
109 | 109 | CONSTANT PROG_START_C16 : INTEGER := 9; |
|
110 | 110 | CONSTANT PROG_END_C16 : INTEGER := 16; |
|
111 | 111 | CONSTANT PROG_START_C256 : INTEGER := 17; |
|
112 | 112 | CONSTANT PROG_END_C256 : INTEGER := 28; |
|
113 | 113 | |
|
114 | 114 | BEGIN |
|
115 | 115 | |
|
116 | 116 | OPERATION(2 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3)); --SEL_SAMPLE |
|
117 | 117 | OPERATION(4 DOWNTO 3) <= PROG(current_cmd)(1 DOWNTO 0); --SEL_DATA_A |
|
118 | 118 | OPERATION(6 DOWNTO 5) <= "00" WHEN STATE_CIC_LFR = IDLE ELSE PROG(current_cmd)(3 DOWNTO 2); --ALU_CMD |
|
119 | 119 | OPERATION(7) <= '0' WHEN STATE_CIC_LFR = IDLE ELSE PROG(current_cmd)(4); --CARRY_PUSH |
|
120 | 120 | OPERATION(8) <= PROG(current_cmd)(5); --@_init |
|
121 | 121 | OPERATION(9) <= PROG(current_cmd)(6); --@_add_1 |
|
122 | 122 | |
|
123 | 123 | OPERATION(10) <= PROG(current_cmd)(7) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 AND PROG(current_cmd)(9) = '1' ELSE |
|
124 | 124 | PROG(current_cmd)(7); --@_sel(1..0) |
|
125 | 125 | OPERATION(11) <= PROG(current_cmd)(8); |
|
126 | 126 | OPERATION(12) <= PROG(current_cmd)(9) AND sample_16_odd WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE |
|
127 | 127 | --PROG(current_cmd)(9) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE |
|
128 | 128 | PROG(current_cmd)(9) WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE |
|
129 | 129 | '0'; --@_sel(2) |
|
130 | 130 | |
|
131 | 131 | |
|
132 | 132 | OPERATION(13) <= '0' WHEN STATE_CIC_LFR = IDLE ELSE PROG(current_cmd)(10); --WE |
|
133 | 133 | OPERATION(14) <= PROG(current_cmd)(12); -- SEL_DATA_A = data_b_reg |
|
134 | 134 | OPERATION(15) <= PROG(current_cmd)(13); -- WRITE_ADDR_sel |
|
135 | 135 | data_out_16_valid <= PROG(current_cmd)(11) WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE '0'; |
|
136 | 136 | data_out_256_valid <= PROG(current_cmd)(11) WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0'; |
|
137 | 137 | |
|
138 | 138 | |
|
139 | 139 | |
|
140 | 140 | |
|
141 | 141 | |
|
142 | 142 | |
|
143 | 143 | |
|
144 | 144 | |
|
145 | 145 | |
|
146 | 146 | |
|
147 | 147 | --OPERATION(1 DOWNTO 0) <= PROG(current_cmd)(1 DOWNTO 0); |
|
148 | 148 | --OPERATION(2) <= '0' WHEN STATE_CIC_LFR = IDLE ELSE |
|
149 | 149 | -- PROG(current_cmd)(2); |
|
150 | 150 | --OPERATION(5 DOWNTO 3) <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3)) WHEN STATE_CIC_LFR = RUN_PROG_I AND current_cmd = 0 ELSE |
|
151 | 151 | -- PROG(current_cmd)(5 DOWNTO 3); |
|
152 | 152 | |
|
153 | 153 | --OPERATION(8 DOWNTO 6) <= "000" WHEN STATE_CIC_LFR = IDLE ELSE |
|
154 | 154 | -- PROG(current_cmd)(8 DOWNTO 6); |
|
155 | 155 | --OPERATION(11 DOWNTO 9) <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3)); |
|
156 | 156 | --OPERATION(13 DOWNTO 12) <= PROG(current_cmd)(10 DOWNTO 9); |
|
157 | 157 | --OPERATION(14) <= PROG(current_cmd)(11) AND sample_16_odd WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE |
|
158 | 158 | -- PROG(current_cmd)(11) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0'; |
|
159 | 159 | |
|
160 | 160 | --OPERATION(15) <= PROG(current_cmd)(12); |
|
161 | 161 | |
|
162 | 162 | --data_out_16_valid <= PROG(current_cmd)(13) WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE '0'; |
|
163 | 163 | --data_out_256_valid <= PROG(current_cmd)(13) WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0'; |
|
164 | 164 | |
|
165 | 165 | PROCESS (clk, rstn) |
|
166 | 166 | BEGIN |
|
167 | 167 | IF rstn = '0' THEN |
|
168 | 168 | STATE_CIC_LFR <= IDLE; |
|
169 | 169 | nb_data_receipt <= 0; |
|
170 | 170 | current_channel <= 0; |
|
171 | 171 | current_cmd <= 0; |
|
172 | 172 | sample_16_odd <= '0'; |
|
173 | 173 | sample_256_odd <= '0'; |
|
174 | 174 | |
|
175 | 175 | ELSIF clk'EVENT AND clk = '1' THEN |
|
176 | 176 | |
|
177 | 177 | CASE STATE_CIC_LFR IS |
|
178 | 178 | WHEN IDLE => |
|
179 | 179 | IF data_in_valid = '1' THEN |
|
180 | 180 | STATE_CIC_LFR <= RUN_PROG_I; |
|
181 | 181 | current_cmd <= PROG_START_I; |
|
182 | 182 | current_channel <= 0; |
|
183 | 183 | nb_data_receipt <= nb_data_receipt + 1; |
|
184 | 184 | END IF; |
|
185 | 185 | |
|
186 | 186 | WHEN RUN_PROG_I => |
|
187 | 187 | IF current_cmd = PROG_END_I THEN |
|
188 | 188 | IF nb_data_receipt MOD 16 = 15 THEN |
|
189 | 189 | STATE_CIC_LFR <= RUN_PROG_C16; |
|
190 | 190 | current_cmd <= PROG_START_C16; |
|
191 | 191 | IF current_channel = 0 THEN |
|
192 | 192 | sample_16_odd <= NOT sample_16_odd; |
|
193 | 193 | END IF; |
|
194 | 194 | ELSE |
|
195 | 195 | IF current_channel = 5 THEN |
|
196 | 196 | current_channel <= 0; |
|
197 | 197 | STATE_CIC_LFR <= IDLE; |
|
198 | 198 | ELSE |
|
199 | ||
|
199 | 200 |
|
|
200 | 201 | current_channel <= current_channel + 1; |
|
202 | ||
|
201 | 203 |
|
|
202 | 204 | END IF; |
|
203 | 205 | ELSE |
|
204 | 206 | current_cmd <= current_cmd +1; |
|
205 | 207 | END IF; |
|
206 | 208 | |
|
207 | 209 | WHEN RUN_PROG_C16 => |
|
208 | 210 | IF current_cmd = PROG_END_C16 THEN |
|
209 | 211 | IF nb_data_receipt MOD 256 = 255 THEN |
|
210 | 212 | STATE_CIC_LFR <= RUN_PROG_C256; |
|
211 | 213 | current_cmd <= PROG_START_C256; |
|
212 | 214 | IF current_channel = 0 THEN |
|
213 | 215 | sample_256_odd <= NOT sample_256_odd; |
|
214 | 216 | END IF; |
|
215 | 217 | ELSE |
|
216 | 218 | IF current_channel = 5 THEN |
|
217 | 219 | current_channel <= 0; |
|
218 | 220 | STATE_CIC_LFR <= IDLE; |
|
219 | 221 | ELSE |
|
220 | 222 | STATE_CIC_LFR <= RUN_PROG_I; |
|
221 | 223 | current_cmd <= PROG_START_I; |
|
222 | 224 | current_channel <= current_channel + 1; |
|
223 | 225 | END IF; |
|
224 | 226 | END IF; |
|
225 | 227 | ELSE |
|
226 | 228 | current_cmd <= current_cmd +1; |
|
227 | 229 | END IF; |
|
228 | 230 | |
|
229 | 231 | WHEN RUN_PROG_C256 => |
|
230 | 232 | IF current_cmd = PROG_END_C256 THEN |
|
231 | 233 | -- data_out_256_valid <= '1'; |
|
232 | 234 | IF current_channel = 5 THEN |
|
233 | 235 | current_channel <= 0; |
|
234 | 236 | STATE_CIC_LFR <= IDLE; |
|
235 | 237 | ELSE |
|
236 | 238 | STATE_CIC_LFR <= RUN_PROG_I; |
|
237 | 239 | current_cmd <= PROG_START_I; |
|
238 | 240 | current_channel <= current_channel + 1; |
|
239 | 241 | END IF; |
|
240 | 242 | ELSE |
|
241 | 243 | current_cmd <= current_cmd +1; |
|
242 | 244 | END IF; |
|
243 | 245 | |
|
244 | 246 | WHEN OTHERS => NULL; |
|
245 | 247 | END CASE; |
|
246 | 248 | END IF; |
|
247 | 249 | END PROCESS; |
|
248 | 250 | |
|
249 | 251 | END beh; |
@@ -1,147 +1,177 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | -- jean-christophe.pellion@easii-ic.com |
|
22 | 22 | ---------------------------------------------------------------------------- |
|
23 | 23 | |
|
24 | 24 | LIBRARY ieee; |
|
25 | 25 | USE ieee.std_logic_1164.ALL; |
|
26 | 26 | |
|
27 | 27 | LIBRARY lpp; |
|
28 | 28 | USE lpp.data_type_pkg.ALL; |
|
29 | 29 | |
|
30 | 30 | PACKAGE cic_pkg IS |
|
31 | 31 | |
|
32 | 32 | ----------------------------------------------------------------------------- |
|
33 | 33 | COMPONENT cic |
|
34 | 34 | GENERIC ( |
|
35 | 35 | D_delay_number : INTEGER; |
|
36 | 36 | S_stage_number : INTEGER; |
|
37 | 37 | R_downsampling_decimation_factor : INTEGER; |
|
38 | 38 | b_data_size : INTEGER; |
|
39 | 39 | b_grow : INTEGER); |
|
40 | 40 | PORT ( |
|
41 | 41 | clk : IN STD_LOGIC; |
|
42 | 42 | rstn : IN STD_LOGIC; |
|
43 | 43 | run : IN STD_LOGIC; |
|
44 | 44 | data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0); |
|
45 | 45 | data_in_valid : IN STD_LOGIC; |
|
46 | 46 | data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0); |
|
47 | 47 | data_out_valid : OUT STD_LOGIC); |
|
48 | 48 | END COMPONENT; |
|
49 | 49 | ----------------------------------------------------------------------------- |
|
50 | 50 | COMPONENT cic_integrator |
|
51 | 51 | GENERIC ( |
|
52 | 52 | b_data_size : INTEGER); |
|
53 | 53 | PORT ( |
|
54 | 54 | clk : IN STD_LOGIC; |
|
55 | 55 | rstn : IN STD_LOGIC; |
|
56 | 56 | run : IN STD_LOGIC; |
|
57 | 57 | data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0); |
|
58 | 58 | data_in_valid : IN STD_LOGIC; |
|
59 | 59 | data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0); |
|
60 | 60 | data_out_valid : OUT STD_LOGIC); |
|
61 | 61 | END COMPONENT; |
|
62 | 62 | |
|
63 | 63 | COMPONENT cic_downsampler |
|
64 | 64 | GENERIC ( |
|
65 | 65 | R_downsampling_decimation_factor : INTEGER; |
|
66 | 66 | b_data_size : INTEGER); |
|
67 | 67 | PORT ( |
|
68 | 68 | clk : IN STD_LOGIC; |
|
69 | 69 | rstn : IN STD_LOGIC; |
|
70 | 70 | run : IN STD_LOGIC; |
|
71 | 71 | data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0); |
|
72 | 72 | data_in_valid : IN STD_LOGIC; |
|
73 | 73 | data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0); |
|
74 | 74 | data_out_valid : OUT STD_LOGIC); |
|
75 | 75 | END COMPONENT; |
|
76 | 76 | |
|
77 | 77 | COMPONENT cic_comb |
|
78 | 78 | GENERIC ( |
|
79 | 79 | b_data_size : INTEGER; |
|
80 | 80 | D_delay_number : INTEGER); |
|
81 | 81 | PORT ( |
|
82 | 82 | clk : IN STD_LOGIC; |
|
83 | 83 | rstn : IN STD_LOGIC; |
|
84 | 84 | run : IN STD_LOGIC; |
|
85 | 85 | data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0); |
|
86 | 86 | data_in_valid : IN STD_LOGIC; |
|
87 | 87 | data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0); |
|
88 | 88 | data_out_valid : OUT STD_LOGIC); |
|
89 | 89 | END COMPONENT; |
|
90 | 90 | ----------------------------------------------------------------------------- |
|
91 | 91 | |
|
92 | 92 | |
|
93 | 93 | ----------------------------------------------------------------------------- |
|
94 | 94 | COMPONENT cic_lfr |
|
95 | 95 | GENERIC ( |
|
96 | 96 | tech : INTEGER; |
|
97 | 97 | use_RAM_nCEL : INTEGER); |
|
98 | 98 | PORT ( |
|
99 | 99 | clk : IN STD_LOGIC; |
|
100 | 100 | rstn : IN STD_LOGIC; |
|
101 | 101 | run : IN STD_LOGIC; |
|
102 | 102 | data_in : IN sample_vector(5 DOWNTO 0, 15 DOWNTO 0); |
|
103 | 103 | data_in_valid : IN STD_LOGIC; |
|
104 | 104 | data_out_16 : OUT sample_vector(5 DOWNTO 0, 15 DOWNTO 0); |
|
105 | 105 | data_out_16_valid : OUT STD_LOGIC; |
|
106 | 106 | data_out_256 : OUT sample_vector(5 DOWNTO 0, 15 DOWNTO 0); |
|
107 | 107 | data_out_256_valid : OUT STD_LOGIC); |
|
108 | 108 | END COMPONENT; |
|
109 | 109 | |
|
110 | COMPONENT cic_lfr_r2 | |
|
111 | GENERIC ( | |
|
112 | tech : INTEGER; | |
|
113 | use_RAM_nCEL : INTEGER); | |
|
114 | PORT ( | |
|
115 | clk : IN STD_LOGIC; | |
|
116 | rstn : IN STD_LOGIC; | |
|
117 | run : IN STD_LOGIC; | |
|
118 | param_r2 : IN STD_LOGIC; | |
|
119 | data_in : IN sample_vector(7 DOWNTO 0, 15 DOWNTO 0); | |
|
120 | data_in_valid : IN STD_LOGIC; | |
|
121 | data_out_16 : OUT sample_vector(5 DOWNTO 0, 15 DOWNTO 0); | |
|
122 | data_out_16_valid : OUT STD_LOGIC; | |
|
123 | data_out_256 : OUT sample_vector(5 DOWNTO 0, 15 DOWNTO 0); | |
|
124 | data_out_256_valid : OUT STD_LOGIC); | |
|
125 | END COMPONENT; | |
|
126 | ||
|
110 | 127 | COMPONENT cic_lfr_control |
|
111 | 128 | PORT ( |
|
112 | 129 | clk : IN STD_LOGIC; |
|
113 | 130 | rstn : IN STD_LOGIC; |
|
114 | 131 | run : IN STD_LOGIC; |
|
115 | 132 | data_in_valid : IN STD_LOGIC; |
|
116 | 133 | data_out_16_valid : OUT STD_LOGIC; |
|
117 | 134 | data_out_256_valid : OUT STD_LOGIC; |
|
118 | 135 | OPERATION : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); |
|
119 | 136 | END COMPONENT; |
|
120 | 137 | |
|
138 | COMPONENT cic_lfr_control_r2 | |
|
139 | PORT ( | |
|
140 | clk : IN STD_LOGIC; | |
|
141 | rstn : IN STD_LOGIC; | |
|
142 | run : IN STD_LOGIC; | |
|
143 | data_in_valid : IN STD_LOGIC; | |
|
144 | data_out_16_valid : OUT STD_LOGIC; | |
|
145 | data_out_256_valid : OUT STD_LOGIC; | |
|
146 | OPERATION : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); | |
|
147 | END COMPONENT; | |
|
148 | ||
|
121 | 149 | COMPONENT cic_lfr_add_sub |
|
122 | 150 | PORT ( |
|
123 | 151 | clk : IN STD_LOGIC; |
|
124 | 152 | rstn : IN STD_LOGIC; |
|
125 | 153 | run : IN STD_LOGIC; |
|
126 | 154 | OP : IN STD_LOGIC_VECTOR( 1 DOWNTO 0); |
|
127 | 155 | data_in_A : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
128 | 156 | data_in_B : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
129 | 157 | data_in_Carry : IN STD_LOGIC; |
|
130 | 158 | data_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
131 | 159 | data_out_Carry : OUT STD_LOGIC); |
|
132 | 160 | END COMPONENT; |
|
133 | 161 | |
|
134 | 162 | COMPONENT cic_lfr_address_gen |
|
163 | GENERIC ( | |
|
164 | ADDR_SIZE : INTEGER); | |
|
135 | 165 | PORT ( |
|
136 | 166 | clk : IN STD_LOGIC; |
|
137 | 167 | rstn : IN STD_LOGIC; |
|
138 | 168 | run : IN STD_LOGIC; |
|
139 |
addr_base : IN STD_LOGIC_VECTOR( |
|
|
140 | addr_init : IN STD_LOGIC; | |
|
141 | addr_add_1 : IN STD_LOGIC; | |
|
142 |
addr : OUT STD_LOGIC_VECTOR( |
|
|
169 | addr_base : IN STD_LOGIC_VECTOR(ADDR_SIZE-1 DOWNTO 0); | |
|
170 | addr_init : IN STD_LOGIC; | |
|
171 | addr_add_1 : IN STD_LOGIC; | |
|
172 | addr : OUT STD_LOGIC_VECTOR(ADDR_SIZE-1 DOWNTO 0)); | |
|
143 | 173 | END COMPONENT; |
|
144 | 174 | |
|
145 | 175 | |
|
146 | 176 | ----------------------------------------------------------------------------- |
|
147 | 177 | END cic_pkg; |
@@ -1,9 +1,11 | |||
|
1 | 1 | cic_pkg.vhd |
|
2 | 2 | cic.vhd |
|
3 | 3 | cic_integrator.vhd |
|
4 | 4 | cic_downsampler.vhd |
|
5 | 5 | cic_comb.vhd |
|
6 | 6 | cic_lfr.vhd |
|
7 | 7 | cic_lfr_control.vhd |
|
8 | 8 | cic_lfr_add_sub.vhd |
|
9 | 9 | cic_lfr_address_gen.vhd |
|
10 | cic_lfr_r2.vhd | |
|
11 | cic_lfr_control_r2.vhd |
@@ -1,474 +1,550 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | -- jean-christophe.pellion@easii-ic.com |
|
22 | 22 | ---------------------------------------------------------------------------- |
|
23 | 23 | LIBRARY ieee; |
|
24 | 24 | USE ieee.std_logic_1164.ALL; |
|
25 | 25 | USE ieee.numeric_std.ALL; |
|
26 | 26 | |
|
27 | 27 | LIBRARY lpp; |
|
28 | 28 | USE lpp.lpp_ad_conv.ALL; |
|
29 | 29 | USE lpp.iir_filter.ALL; |
|
30 | 30 | USE lpp.FILTERcfg.ALL; |
|
31 | 31 | USE lpp.lpp_memory.ALL; |
|
32 | 32 | USE lpp.lpp_waveform_pkg.ALL; |
|
33 | 33 | USE lpp.cic_pkg.ALL; |
|
34 | 34 | USE lpp.data_type_pkg.ALL; |
|
35 | 35 | USE lpp.lpp_lfr_filter_coeff.ALL; |
|
36 | 36 | |
|
37 | 37 | LIBRARY techmap; |
|
38 | 38 | USE techmap.gencomp.ALL; |
|
39 | 39 | |
|
40 | 40 | LIBRARY grlib; |
|
41 | 41 | USE grlib.amba.ALL; |
|
42 | 42 | USE grlib.stdlib.ALL; |
|
43 | 43 | USE grlib.devices.ALL; |
|
44 | 44 | USE GRLIB.DMA2AHB_Package.ALL; |
|
45 | 45 | |
|
46 | 46 | ENTITY lpp_lfr_filter IS |
|
47 | 47 | GENERIC( |
|
48 | 48 | Mem_use : INTEGER := use_RAM |
|
49 | 49 | ); |
|
50 | 50 | PORT ( |
|
51 | 51 | sample : IN Samples(7 DOWNTO 0); |
|
52 | 52 | sample_val : IN STD_LOGIC; |
|
53 | 53 | -- |
|
54 | 54 | clk : IN STD_LOGIC; |
|
55 | 55 | rstn : IN STD_LOGIC; |
|
56 | 56 | -- |
|
57 | 57 | data_shaping_SP0 : IN STD_LOGIC; |
|
58 | 58 | data_shaping_SP1 : IN STD_LOGIC; |
|
59 | 59 | data_shaping_R0 : IN STD_LOGIC; |
|
60 | 60 | data_shaping_R1 : IN STD_LOGIC; |
|
61 | 61 | data_shaping_R2 : IN STD_LOGIC; |
|
62 | 62 | -- |
|
63 | 63 | sample_f0_val : OUT STD_LOGIC; |
|
64 | 64 | sample_f1_val : OUT STD_LOGIC; |
|
65 | 65 | sample_f2_val : OUT STD_LOGIC; |
|
66 | 66 | sample_f3_val : OUT STD_LOGIC; |
|
67 | 67 | -- |
|
68 | 68 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
69 | 69 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
70 | 70 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
71 | 71 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0) |
|
72 | 72 | ); |
|
73 | 73 | END lpp_lfr_filter; |
|
74 | 74 | |
|
75 | 75 | ARCHITECTURE tb OF lpp_lfr_filter IS |
|
76 | 76 | |
|
77 | 77 | COMPONENT Downsampling |
|
78 | 78 | GENERIC ( |
|
79 | 79 | ChanelCount : INTEGER; |
|
80 | 80 | SampleSize : INTEGER; |
|
81 | 81 | DivideParam : INTEGER); |
|
82 | 82 | PORT ( |
|
83 | 83 | clk : IN STD_LOGIC; |
|
84 | 84 | rstn : IN STD_LOGIC; |
|
85 | 85 | sample_in_val : IN STD_LOGIC; |
|
86 | 86 | sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); |
|
87 | 87 | sample_out_val : OUT STD_LOGIC; |
|
88 | 88 | sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); |
|
89 | 89 | END COMPONENT; |
|
90 | 90 | |
|
91 | 91 | ----------------------------------------------------------------------------- |
|
92 | 92 | CONSTANT ChanelCount : INTEGER := 8; |
|
93 | 93 | |
|
94 | 94 | ----------------------------------------------------------------------------- |
|
95 | 95 | SIGNAL sample_val_delay : STD_LOGIC; |
|
96 | 96 | ----------------------------------------------------------------------------- |
|
97 | 97 | CONSTANT Coef_SZ : INTEGER := 9; |
|
98 | 98 | CONSTANT CoefCntPerCel : INTEGER := 6; |
|
99 | 99 | CONSTANT CoefPerCel : INTEGER := 5; |
|
100 | 100 | CONSTANT Cels_count : INTEGER := 5; |
|
101 | 101 | |
|
102 | 102 | --SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); |
|
103 | 103 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); |
|
104 | 104 | SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
105 | 105 | --SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
106 | 106 | -- |
|
107 | 107 | SIGNAL sample_filter_v2_out_val : STD_LOGIC; |
|
108 | 108 | SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
109 | 109 | ----------------------------------------------------------------------------- |
|
110 | 110 | SIGNAL sample_data_shaping_out_val : STD_LOGIC; |
|
111 | 111 | SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
112 | 112 | SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); |
|
113 | 113 | SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); |
|
114 | 114 | SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0); |
|
115 | 115 | SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); |
|
116 | 116 | SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); |
|
117 | 117 | ----------------------------------------------------------------------------- |
|
118 | 118 | SIGNAL sample_filter_v2_out_val_s : STD_LOGIC; |
|
119 | 119 | SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); |
|
120 | 120 | ----------------------------------------------------------------------------- |
|
121 | 121 | -- SIGNAL sample_f0_val : STD_LOGIC; |
|
122 | 122 | SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); |
|
123 |
SIGNAL sample_f0_s : sample_vector( |
|
|
123 | SIGNAL sample_f0_s : sample_vector(7 DOWNTO 0, 15 DOWNTO 0); | |
|
124 | 124 | -- |
|
125 | 125 | -- SIGNAL sample_f1_val : STD_LOGIC; |
|
126 | 126 | |
|
127 | 127 | SIGNAL sample_f0_f1_s : samplT(5 DOWNTO 0, 17 DOWNTO 0); |
|
128 | 128 | SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 17 DOWNTO 0); |
|
129 | 129 | SIGNAL sample_f1 : samplT(5 DOWNTO 0, 17 DOWNTO 0); |
|
130 | 130 | -- |
|
131 | 131 | -- SIGNAL sample_f2_val : STD_LOGIC; |
|
132 | 132 | SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0); |
|
133 | 133 | SIGNAL sample_f2_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); |
|
134 | SIGNAL sample_f2_cic_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0); | |
|
135 | SIGNAL sample_f2_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0); | |
|
134 | 136 | SIGNAL sample_f2_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0); |
|
135 | 137 | SIGNAL sample_f2_cic_val : STD_LOGIC; |
|
138 | SIGNAL sample_f2_filter_val : STD_LOGIC; | |
|
136 | 139 | |
|
137 | 140 | SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0); |
|
138 | 141 | SIGNAL sample_f3_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); |
|
142 | SIGNAL sample_f3_cic_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0); | |
|
143 | SIGNAL sample_f3_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0); | |
|
139 | 144 | SIGNAL sample_f3_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0); |
|
140 | 145 | SIGNAL sample_f3_cic_val : STD_LOGIC; |
|
146 | SIGNAL sample_f3_filter_val : STD_LOGIC; | |
|
141 | 147 | |
|
142 | 148 | ----------------------------------------------------------------------------- |
|
143 | 149 | --SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); |
|
144 | 150 | --SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); |
|
145 | 151 | --SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); |
|
146 | 152 | --SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); |
|
147 | 153 | ----------------------------------------------------------------------------- |
|
148 | 154 | |
|
149 | 155 | SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
150 | 156 | SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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151 | 157 | SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
152 | 158 | SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
153 | 159 | |
|
154 | 160 | SIGNAL sample_f0_val_s : STD_LOGIC; |
|
155 | 161 | SIGNAL sample_f1_val_s : STD_LOGIC; |
|
156 | 162 | |
|
157 | 163 | ----------------------------------------------------------------------------- |
|
158 | 164 | -- CONFIG FILTER IIR f0 to f1 |
|
159 | 165 | ----------------------------------------------------------------------------- |
|
160 | 166 | CONSTANT f0_to_f1_CEL_NUMBER : INTEGER := 5; |
|
161 | 167 | CONSTANT f0_to_f1_COEFFICIENT_SIZE : INTEGER := 10; |
|
162 | 168 | CONSTANT f0_to_f1_POINT_POSITION : INTEGER := 8; |
|
163 | 169 | |
|
164 | 170 | CONSTANT f0_to_f1_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) := |
|
165 | 171 | ( |
|
166 | 172 | (1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583), |
|
167 | 173 | (1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351), |
|
168 | 174 | (1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102), |
|
169 | 175 | (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464), |
|
170 | 176 | (1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691) |
|
171 | 177 | ); |
|
172 | 178 | CONSTANT f0_to_f1_gain : COEFF_CEL_REAL := |
|
173 | 179 | ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0); |
|
174 | 180 | |
|
175 | 181 | CONSTANT coefs_iir_cel_f0_to_f1 : STD_LOGIC_VECTOR((f0_to_f1_CEL_NUMBER*f0_to_f1_COEFFICIENT_SIZE*5)-1 DOWNTO 0) |
|
176 | 182 | := get_IIR_CEL_FILTER_CONFIG( |
|
177 | 183 | f0_to_f1_COEFFICIENT_SIZE, |
|
178 | 184 | f0_to_f1_POINT_POSITION, |
|
179 | 185 | f0_to_f1_CEL_NUMBER, |
|
180 | 186 | f0_to_f1_sos, |
|
181 | 187 | f0_to_f1_gain); |
|
182 | 188 | ----------------------------------------------------------------------------- |
|
183 | 189 | |
|
190 | ----------------------------------------------------------------------------- | |
|
191 | -- CONFIG FILTER IIR f2 and f3 | |
|
192 | ----------------------------------------------------------------------------- | |
|
193 | CONSTANT f2_f3_CEL_NUMBER : INTEGER := 5; | |
|
194 | CONSTANT f2_f3_COEFFICIENT_SIZE : INTEGER := 10; | |
|
195 | CONSTANT f2_f3_POINT_POSITION : INTEGER := 8; | |
|
196 | ||
|
197 | CONSTANT f2_f3_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) := | |
|
198 | ( | |
|
199 | (1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583), | |
|
200 | (1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351), | |
|
201 | (1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102), | |
|
202 | (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464), | |
|
203 | (1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691) | |
|
204 | ); | |
|
205 | CONSTANT f2_f3_gain : COEFF_CEL_REAL := | |
|
206 | ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0); | |
|
207 | ||
|
208 | CONSTANT coefs_iir_cel_f2_f3 : STD_LOGIC_VECTOR((f2_f3_CEL_NUMBER*f2_f3_COEFFICIENT_SIZE*5)-1 DOWNTO 0) | |
|
209 | := get_IIR_CEL_FILTER_CONFIG( | |
|
210 | f2_f3_COEFFICIENT_SIZE, | |
|
211 | f2_f3_POINT_POSITION, | |
|
212 | f2_f3_CEL_NUMBER, | |
|
213 | f2_f3_sos, | |
|
214 | f2_f3_gain); | |
|
215 | ----------------------------------------------------------------------------- | |
|
216 | ||
|
184 | 217 | |
|
185 | 218 | BEGIN |
|
186 | 219 | |
|
187 | 220 | ----------------------------------------------------------------------------- |
|
188 | 221 | PROCESS (clk, rstn) |
|
189 | 222 | BEGIN -- PROCESS |
|
190 | 223 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
191 | 224 | sample_val_delay <= '0'; |
|
192 | 225 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
193 | 226 | sample_val_delay <= sample_val; |
|
194 | 227 | END IF; |
|
195 | 228 | END PROCESS; |
|
196 | 229 | |
|
197 | 230 | ----------------------------------------------------------------------------- |
|
198 | 231 | ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE |
|
199 | 232 | SampleLoop : FOR j IN 0 TO 15 GENERATE |
|
200 | 233 | sample_filter_in(i, j) <= sample(i)(j); |
|
201 | 234 | END GENERATE; |
|
202 | 235 | |
|
203 | 236 | sample_filter_in(i, 16) <= sample(i)(15); |
|
204 | 237 | sample_filter_in(i, 17) <= sample(i)(15); |
|
205 | 238 | END GENERATE; |
|
206 | 239 | |
|
207 | 240 | coefs_v2 <= CoefsInitValCst_v2; |
|
208 | 241 | |
|
209 | 242 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 |
|
210 | 243 | GENERIC MAP ( |
|
211 | 244 | tech => 0, |
|
212 | 245 | Mem_use => Mem_use, -- use_RAM |
|
213 | 246 | Sample_SZ => 18, |
|
214 | 247 | Coef_SZ => Coef_SZ, |
|
215 | 248 | Coef_Nb => 25, |
|
216 | 249 | Coef_sel_SZ => 5, |
|
217 | 250 | Cels_count => Cels_count, |
|
218 | 251 | ChanelsCount => ChanelCount) |
|
219 | 252 | PORT MAP ( |
|
220 | 253 | rstn => rstn, |
|
221 | 254 | clk => clk, |
|
222 | 255 | virg_pos => 7, |
|
223 | 256 | coefs => coefs_v2, |
|
224 | 257 | sample_in_val => sample_val_delay, |
|
225 | 258 | sample_in => sample_filter_in, |
|
226 | 259 | sample_out_val => sample_filter_v2_out_val, |
|
227 | 260 | sample_out => sample_filter_v2_out); |
|
228 | 261 | |
|
229 | 262 | ----------------------------------------------------------------------------- |
|
230 | 263 | -- DATA_SHAPING |
|
231 | 264 | ----------------------------------------------------------------------------- |
|
232 | 265 | all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE |
|
233 | 266 | sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I); |
|
234 | 267 | sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I); |
|
235 | 268 | sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I); |
|
236 | 269 | END GENERATE all_data_shaping_in_loop; |
|
237 | 270 | |
|
238 | 271 | sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s; |
|
239 | 272 | sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s; |
|
240 | 273 | |
|
241 | 274 | PROCESS (clk, rstn) |
|
242 | 275 | BEGIN -- PROCESS |
|
243 | 276 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
244 | 277 | sample_data_shaping_out_val <= '0'; |
|
245 | 278 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
246 | 279 | sample_data_shaping_out_val <= sample_filter_v2_out_val; |
|
247 | 280 | END IF; |
|
248 | 281 | END PROCESS; |
|
249 | 282 | |
|
250 | 283 | SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE |
|
251 | 284 | PROCESS (clk, rstn) |
|
252 | 285 | BEGIN |
|
253 | 286 | IF rstn = '0' THEN |
|
254 | 287 | sample_data_shaping_out(0, j) <= '0'; |
|
255 | 288 | sample_data_shaping_out(1, j) <= '0'; |
|
256 | 289 | sample_data_shaping_out(2, j) <= '0'; |
|
257 | 290 | sample_data_shaping_out(3, j) <= '0'; |
|
258 | 291 | sample_data_shaping_out(4, j) <= '0'; |
|
259 | 292 | sample_data_shaping_out(5, j) <= '0'; |
|
260 | 293 | sample_data_shaping_out(6, j) <= '0'; |
|
261 | 294 | sample_data_shaping_out(7, j) <= '0'; |
|
262 | 295 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
263 | 296 | sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j); |
|
264 | 297 | IF data_shaping_SP0 = '1' THEN |
|
265 | 298 | sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j); |
|
266 | 299 | ELSE |
|
267 | 300 | sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j); |
|
268 | 301 | END IF; |
|
269 | 302 | IF data_shaping_SP1 = '1' THEN |
|
270 | 303 | sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j); |
|
271 | 304 | ELSE |
|
272 | 305 | sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j); |
|
273 | 306 | END IF; |
|
274 | 307 | sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j); |
|
275 | 308 | sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j); |
|
276 | 309 | sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j); |
|
277 | 310 | sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j); |
|
278 | 311 | sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j); |
|
279 | 312 | END IF; |
|
280 | 313 | END PROCESS; |
|
281 | 314 | END GENERATE; |
|
282 | 315 | |
|
283 | 316 | sample_filter_v2_out_val_s <= sample_data_shaping_out_val; |
|
284 | 317 | ChanelLoopOut : FOR i IN 0 TO 7 GENERATE |
|
285 | 318 | SampleLoopOut : FOR j IN 0 TO 15 GENERATE |
|
286 | 319 | sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j); |
|
287 | 320 | END GENERATE; |
|
288 | 321 | END GENERATE; |
|
289 | 322 | ----------------------------------------------------------------------------- |
|
290 | 323 | -- F0 -- @24.576 kHz |
|
291 | 324 | ----------------------------------------------------------------------------- |
|
292 | 325 | |
|
293 | 326 | Downsampling_f0 : Downsampling |
|
294 | 327 | GENERIC MAP ( |
|
295 | 328 | ChanelCount => 8, |
|
296 | 329 | SampleSize => 16, |
|
297 | 330 | DivideParam => 4) |
|
298 | 331 | PORT MAP ( |
|
299 | 332 | clk => clk, |
|
300 | 333 | rstn => rstn, |
|
301 | 334 | sample_in_val => sample_filter_v2_out_val_s, |
|
302 | 335 | sample_in => sample_filter_v2_out_s, |
|
303 | 336 | sample_out_val => sample_f0_val_s, |
|
304 | 337 | sample_out => sample_f0); |
|
305 | 338 | |
|
306 | 339 | sample_f0_val <= sample_f0_val_s; |
|
307 | 340 | |
|
308 | 341 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE |
|
309 | 342 | sample_f0_wdata_s(I) <= sample_f0(0, I); -- V |
|
310 | 343 | sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1 |
|
311 | 344 | sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2 |
|
312 | 345 | sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1 |
|
313 | 346 | sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2 |
|
314 | 347 | sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3 |
|
315 | 348 | END GENERATE all_bit_sample_f0; |
|
316 | 349 | |
|
317 | 350 | ----------------------------------------------------------------------------- |
|
318 | 351 | -- F1 -- @4096 Hz |
|
319 | 352 | ----------------------------------------------------------------------------- |
|
320 | 353 | |
|
321 | 354 | all_bit_sample_f0_f1 : FOR I IN 15 DOWNTO 0 GENERATE |
|
322 | 355 | sample_f0_f1_s(0,I) <= sample_f0(0,I); --V |
|
323 | 356 | sample_f0_f1_s(1,I) <= sample_f0(1,I) WHEN data_shaping_R1 = '1' ELSE sample_f0(3,I); --E1 |
|
324 | 357 | sample_f0_f1_s(2,I) <= sample_f0(2,I) WHEN data_shaping_R1 = '1' ELSE sample_f0(4,I); --E2 |
|
325 | 358 | sample_f0_f1_s(3,I) <= sample_f0(5,I); --B1 |
|
326 | 359 | sample_f0_f1_s(4,I) <= sample_f0(6,I); --B2 |
|
327 | 360 | sample_f0_f1_s(5,I) <= sample_f0(7,I); --B3 |
|
328 | 361 | END GENERATE all_bit_sample_f0_f1; |
|
329 | 362 | all_bit_sample_f0_f1_extended : FOR I IN 17 DOWNTO 16 GENERATE |
|
330 | 363 | sample_f0_f1_s(0,I) <= sample_f0(0,15); |
|
331 | 364 | sample_f0_f1_s(1,I) <= sample_f0(1,15) WHEN data_shaping_R1 = '1' ELSE sample_f0(3,15); --E1 |
|
332 | 365 | sample_f0_f1_s(2,I) <= sample_f0(2,15) WHEN data_shaping_R1 = '1' ELSE sample_f0(4,15); --E2 |
|
333 | 366 | sample_f0_f1_s(3,I) <= sample_f0(5,15); --B1 |
|
334 | 367 | sample_f0_f1_s(4,I) <= sample_f0(6,15); --B2 |
|
335 | 368 | sample_f0_f1_s(5,I) <= sample_f0(7,15); --B3 |
|
336 | 369 | END GENERATE all_bit_sample_f0_f1_extended; |
|
337 | 370 | |
|
338 | 371 | |
|
339 | 372 | IIR_CEL_f0_to_f1 : IIR_CEL_CTRLR_v2 |
|
340 | 373 | GENERIC MAP ( |
|
341 | 374 | tech => 0, |
|
342 | 375 | Mem_use => Mem_use, -- use_RAM |
|
343 | 376 | Sample_SZ => 18, |
|
344 | 377 | Coef_SZ => f0_to_f1_COEFFICIENT_SIZE, |
|
345 | 378 | Coef_Nb => f0_to_f1_CEL_NUMBER*5, |
|
346 | 379 | Coef_sel_SZ => 5, |
|
347 | 380 | Cels_count => f0_to_f1_CEL_NUMBER, |
|
348 | 381 | ChanelsCount => 6) |
|
349 | 382 | PORT MAP ( |
|
350 | 383 | rstn => rstn, |
|
351 | 384 | clk => clk, |
|
352 | 385 | virg_pos => f0_to_f1_POINT_POSITION, |
|
353 | 386 | coefs => coefs_iir_cel_f0_to_f1, |
|
354 | 387 | |
|
355 | 388 | sample_in_val => sample_f0_val_s, |
|
356 | 389 | sample_in => sample_f0_f1_s, |
|
357 | 390 | |
|
358 | 391 | sample_out_val => sample_f1_val_s, |
|
359 | 392 | sample_out => sample_f1_s); |
|
360 | 393 | |
|
361 | 394 | Downsampling_f1 : Downsampling |
|
362 | 395 | GENERIC MAP ( |
|
363 | 396 | ChanelCount => 6, |
|
364 | 397 | SampleSize => 18, |
|
365 | 398 | DivideParam => 6) |
|
366 | 399 | PORT MAP ( |
|
367 | 400 | clk => clk, |
|
368 | 401 | rstn => rstn, |
|
369 | 402 | sample_in_val => sample_f1_val_s, |
|
370 | 403 | sample_in => sample_f1_s, |
|
371 | 404 | sample_out_val => sample_f1_val, |
|
372 | 405 | sample_out => sample_f1); |
|
373 | 406 | |
|
374 | 407 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE |
|
375 | 408 | all_channel_sample_f1: FOR J IN 5 DOWNTO 0 GENERATE |
|
376 | 409 | sample_f1_wdata_s(16*J+I) <= sample_f1(J, I); |
|
377 | 410 | END GENERATE all_channel_sample_f1; |
|
378 | 411 | END GENERATE all_bit_sample_f1; |
|
379 | 412 | |
|
380 | 413 | ----------------------------------------------------------------------------- |
|
381 | 414 | -- F2 -- @256 Hz |
|
382 | 415 | -- F3 -- @16 Hz |
|
383 | 416 | ----------------------------------------------------------------------------- |
|
384 | 417 | all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE |
|
385 | 418 | sample_f0_s(0, I) <= sample_f0(0, I); -- V |
|
386 | 419 | sample_f0_s(1, I) <= sample_f0(1, I); -- E1 |
|
387 | 420 | sample_f0_s(2, I) <= sample_f0(2, I); -- E2 |
|
388 | 421 | sample_f0_s(3, I) <= sample_f0(5, I); -- B1 |
|
389 | 422 | sample_f0_s(4, I) <= sample_f0(6, I); -- B2 |
|
390 | 423 | sample_f0_s(5, I) <= sample_f0(7, I); -- B3 |
|
424 | sample_f0_s(6, I) <= sample_f0(3, I); -- | |
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425 | sample_f0_s(7, I) <= sample_f0(4, I); -- | |
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391 | 426 | END GENERATE all_bit_sample_f0_s; |
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392 | 427 | |
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393 | 428 | |
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394 | cic_lfr_1: cic_lfr | |
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429 | cic_lfr_1: cic_lfr_r2 | |
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395 | 430 | GENERIC MAP ( |
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396 | 431 | tech => 0, |
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397 | 432 | use_RAM_nCEL => Mem_use) |
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398 | 433 | PORT MAP ( |
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399 | 434 | clk => clk, |
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400 | 435 | rstn => rstn, |
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401 | 436 | run => '1', |
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437 | ||
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438 | param_r2 => data_shaping_R2, | |
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402 | 439 | |
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403 | 440 | data_in => sample_f0_s, |
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404 | 441 | data_in_valid => sample_f0_val_s, |
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405 | 442 | |
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406 | 443 | data_out_16 => sample_f2_cic, |
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407 | 444 | data_out_16_valid => sample_f2_cic_val, |
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408 | 445 | |
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409 | 446 | data_out_256 => sample_f3_cic, |
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410 | 447 | data_out_256_valid => sample_f3_cic_val); |
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411 | 448 | |
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412 | ----------------------------------------------------------------------------- | |
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449 | ||
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450 | ||
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451 | all_channel_sample_f_cic : FOR J IN 5 DOWNTO 0 GENERATE | |
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452 | all_bit_sample_f_cic : FOR I IN 15 DOWNTO 0 GENERATE | |
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453 | sample_f2_cic_filter(J,I) <= sample_f2_cic(J,I); | |
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454 | sample_f3_cic_filter(J,I) <= sample_f3_cic(J,I); | |
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455 | END GENERATE all_bit_sample_f_cic; | |
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456 | sample_f2_cic_filter(J,16) <= sample_f2_cic(J,15); | |
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457 | sample_f2_cic_filter(J,17) <= sample_f2_cic(J,15); | |
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458 | ||
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459 | sample_f3_cic_filter(J,16) <= sample_f3_cic(J,15); | |
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460 | sample_f3_cic_filter(J,17) <= sample_f3_cic(J,15); | |
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461 | END GENERATE all_channel_sample_f_cic; | |
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462 | ||
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413 | 463 | |
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414 | all_bit_sample_f2_cic : FOR I IN 15 DOWNTO 0 GENERATE | |
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415 | all_channel_sample_f2_cic : FOR J IN 5 DOWNTO 0 GENERATE | |
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416 | sample_f2_cic_s(J,I) <= sample_f2_cic(J,I); | |
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417 | END GENERATE all_channel_sample_f2_cic; | |
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418 | END GENERATE all_bit_sample_f2_cic; | |
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464 | IIR_CEL_CTRLR_v3_1:IIR_CEL_CTRLR_v3 | |
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465 | GENERIC MAP ( | |
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466 | tech => 0, | |
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467 | Mem_use => Mem_use, | |
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468 | Sample_SZ => 18, | |
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469 | Coef_SZ => f2_f3_COEFFICIENT_SIZE, | |
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470 | Coef_Nb => f2_f3_CEL_NUMBER*5, | |
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471 | Coef_sel_SZ => 5, | |
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472 | Cels_count => f2_f3_CEL_NUMBER, | |
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473 | ChanelsCount => 6) | |
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474 | PORT MAP ( | |
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475 | rstn => rstn, | |
|
476 | clk => clk, | |
|
477 | virg_pos => f2_f3_POINT_POSITION, | |
|
478 | coefs => coefs_iir_cel_f2_f3, | |
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479 | ||
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480 | sample_in1_val => sample_f2_cic_val, | |
|
481 | sample_in1 => sample_f2_cic_filter, | |
|
482 | ||
|
483 | sample_in2_val => sample_f3_cic_val, | |
|
484 | sample_in2 => sample_f3_cic_filter, | |
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485 | ||
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486 | sample_out1_val => sample_f2_filter_val, | |
|
487 | sample_out1 => sample_f2_filter, | |
|
488 | sample_out2_val => sample_f3_filter_val, | |
|
489 | sample_out2 => sample_f3_filter); | |
|
490 | ||
|
491 | ||
|
492 | all_channel_sample_f_filter : FOR J IN 5 DOWNTO 0 GENERATE | |
|
493 | all_bit_sample_f_filter : FOR I IN 15 DOWNTO 0 GENERATE | |
|
494 | sample_f2_cic_s(J,I) <= sample_f2_filter(J,I); | |
|
495 | sample_f3_cic_s(J,I) <= sample_f3_filter(J,I); | |
|
496 | END GENERATE all_bit_sample_f_filter; | |
|
497 | END GENERATE all_channel_sample_f_filter; | |
|
498 | ||
|
499 | ||
|
500 | ----------------------------------------------------------------------------- | |
|
419 | 501 | |
|
420 | 502 | Downsampling_f2 : Downsampling |
|
421 | 503 | GENERIC MAP ( |
|
422 | 504 | ChanelCount => 6, |
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423 | 505 | SampleSize => 16, |
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424 | 506 | DivideParam => 6) |
|
425 | 507 | PORT MAP ( |
|
426 | 508 | clk => clk, |
|
427 | 509 | rstn => rstn, |
|
428 |
sample_in_val => sample_f2_ |
|
|
510 | sample_in_val => sample_f2_filter_val , | |
|
429 | 511 | sample_in => sample_f2_cic_s, |
|
430 | 512 | sample_out_val => sample_f2_val, |
|
431 | 513 | sample_out => sample_f2); |
|
432 | 514 | |
|
433 | 515 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE |
|
434 | 516 | all_channel_sample_f2 : FOR J IN 5 DOWNTO 0 GENERATE |
|
435 | 517 | sample_f2_wdata_s(16*J+I) <= sample_f2(J,I); |
|
436 | 518 | END GENERATE all_channel_sample_f2; |
|
437 | 519 | END GENERATE all_bit_sample_f2; |
|
438 | 520 | |
|
439 | 521 | ----------------------------------------------------------------------------- |
|
440 | ||
|
441 | all_bit_sample_f3_cic : FOR I IN 15 DOWNTO 0 GENERATE | |
|
442 | all_channel_sample_f3_cic : FOR J IN 5 DOWNTO 0 GENERATE | |
|
443 | sample_f3_cic_s(J,I) <= sample_f3_cic(J,I); | |
|
444 | END GENERATE all_channel_sample_f3_cic; | |
|
445 | END GENERATE all_bit_sample_f3_cic; | |
|
446 | 522 | |
|
447 | 523 | Downsampling_f3 : Downsampling |
|
448 | 524 | GENERIC MAP ( |
|
449 | 525 | ChanelCount => 6, |
|
450 | 526 | SampleSize => 16, |
|
451 | 527 | DivideParam => 6) |
|
452 | 528 | PORT MAP ( |
|
453 | 529 | clk => clk, |
|
454 | 530 | rstn => rstn, |
|
455 |
sample_in_val => sample_f3_ |
|
|
531 | sample_in_val => sample_f3_filter_val , | |
|
456 | 532 | sample_in => sample_f3_cic_s, |
|
457 | 533 | sample_out_val => sample_f3_val, |
|
458 | 534 | sample_out => sample_f3); |
|
459 | 535 | |
|
460 | 536 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE |
|
461 | 537 | all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE |
|
462 | 538 | sample_f3_wdata_s(16*J+I) <= sample_f3(J,I); |
|
463 | 539 | END GENERATE all_channel_sample_f3; |
|
464 | 540 | END GENERATE all_bit_sample_f3; |
|
465 | 541 | |
|
466 | 542 | ----------------------------------------------------------------------------- |
|
467 | 543 | -- |
|
468 | 544 | ----------------------------------------------------------------------------- |
|
469 | 545 | sample_f0_wdata <= sample_f0_wdata_s; |
|
470 | 546 | sample_f1_wdata <= sample_f1_wdata_s; |
|
471 | 547 | sample_f2_wdata <= sample_f2_wdata_s; |
|
472 | 548 | sample_f3_wdata <= sample_f3_wdata_s; |
|
473 | 549 | |
|
474 | 550 | END tb; |
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