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add r2 param to CIC_LFR IP
pellion -
r521:ed390d662fa9 (MINI-LFR) WFP_MS-0-1-56 (LFR-EM) WFP_MS_1-1-56 JC
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26 USE ieee.numeric_std.ALL;
27
28
29 LIBRARY lpp;
30 USE lpp.cic_pkg.ALL;
31 USE lpp.data_type_pkg.ALL;
32
33 ENTITY cic_lfr_control_r2 IS
34 PORT (
35 clk : IN STD_LOGIC;
36 rstn : IN STD_LOGIC;
37 run : IN STD_LOGIC;
38 --
39 data_in_valid : IN STD_LOGIC;
40 data_out_16_valid : OUT STD_LOGIC;
41 data_out_256_valid : OUT STD_LOGIC;
42 --
43 OPERATION : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
44 );
45
46 END cic_lfr_control_r2;
47
48 ARCHITECTURE beh OF cic_lfr_control_r2 IS
49
50 TYPE STATE_CIC_LFR_TYPE IS (IDLE,
51 RUN_PROG_I,
52 RUN_PROG_C16,
53 RUN_PROG_C256
54 );
55
56 SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
57
58 SIGNAL nb_data_receipt : INTEGER := 0;
59 SIGNAL current_cmd : INTEGER := 0;
60 SIGNAL current_channel : INTEGER := 0;
61 SIGNAL sample_16_odd : STD_LOGIC;
62 SIGNAL sample_256_odd : STD_LOGIC;
63
64 TYPE PROGRAM_ARRAY IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(13 DOWNTO 0);
65 --OPERATION( 8 DOWNTO 0) <= PROGRAM_ARRAY( 8 DOWNTO 0) sauf pour PROG_I(0)
66 --OPERATION(13 DOWNTO 12) <= PROGRAM_ARRAY(10 DOWNTO 9)
67 --OPERATION(11 DOWNTO 9) <= current_channel
68 --OPERATION(14) <= PROGRAM_ARRAY(11) selon sample_X_odd et l'etat
69 CONSTANT PROG : PROGRAM_ARRAY(0 TO 28) :=
70 (
71 -- DCBA 98765 43210
72 --PROG I------------------
73 "0001" & "00011" & "00000", --0
74 "0101" & "00010" & "00001", --1
75 "0101" & "00010" & "00001", --2
76 "0001" & "00010" & "01011", --3
77 "0101" & "00010" & "01001", --4
78 "0101" & "00010" & "01001", --5
79 "0001" & "00010" & "01011", --6
80 "0101" & "00010" & "01001", --7
81 "0101" & "00010" & "01001", --8
82 --PROG_C16
83 "1001" & "00100" & "10010", --9
84 "1001" & "10010" & "10101", --10
85 "1001" & "10010" & "10101", --11
86 "1010" & "10010" & "10101", --12
87 "1001" & "01000" & "10010", --13
88 "1001" & "10010" & "11101", --14
89 "1001" & "10010" & "11101", --15
90 "1010" & "10010" & "11101", --16
91 --PROG_C256
92 "1001" & "00100" & "10010", --17
93 "1001" & "10110" & "10101", --18
94 "1001" & "10110" & "10101", --19
95 "1010" & "10110" & "10101", --20
96 "1001" & "01000" & "10010", --21
97 "1001" & "10110" & "11101", --22
98 "1001" & "10110" & "11101", --23
99 "1010" & "10110" & "11101", --24
100 "1001" & "01100" & "10010", --25
101 "1001" & "10110" & "11101", --26
102 "1001" & "10110" & "11101", --27
103 "1010" & "10110" & "11101" --28
104 );
105
106
107 CONSTANT PROG_START_I : INTEGER := 0;
108 CONSTANT PROG_END_I : INTEGER := 8;
109 CONSTANT PROG_START_C16 : INTEGER := 9;
110 CONSTANT PROG_END_C16 : INTEGER := 16;
111 CONSTANT PROG_START_C256 : INTEGER := 17;
112 CONSTANT PROG_END_C256 : INTEGER := 28;
113
114 BEGIN
115
116 OPERATION(2 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3)); --SEL_SAMPLE
117 OPERATION(4 DOWNTO 3) <= PROG(current_cmd)(1 DOWNTO 0); --SEL_DATA_A
118 OPERATION(6 DOWNTO 5) <= "00" WHEN STATE_CIC_LFR = IDLE ELSE PROG(current_cmd)(3 DOWNTO 2); --ALU_CMD
119 OPERATION(7) <= '0' WHEN STATE_CIC_LFR = IDLE ELSE PROG(current_cmd)(4); --CARRY_PUSH
120 OPERATION(8) <= PROG(current_cmd)(5); --@_init
121 OPERATION(9) <= PROG(current_cmd)(6); --@_add_1
122
123 OPERATION(10) <= PROG(current_cmd)(7) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 AND PROG(current_cmd)(9) = '1' ELSE
124 PROG(current_cmd)(7); --@_sel(1..0)
125 OPERATION(11) <= PROG(current_cmd)(8);
126 OPERATION(12) <= PROG(current_cmd)(9) AND sample_16_odd WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE
127 --PROG(current_cmd)(9) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE
128 PROG(current_cmd)(9) WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE
129 '0'; --@_sel(2)
130
131
132 OPERATION(13) <= '0' WHEN STATE_CIC_LFR = IDLE ELSE PROG(current_cmd)(10); --WE
133 OPERATION(14) <= PROG(current_cmd)(12); -- SEL_DATA_A = data_b_reg
134 OPERATION(15) <= PROG(current_cmd)(13); -- WRITE_ADDR_sel
135 data_out_16_valid <= PROG(current_cmd)(11) WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE '0';
136 data_out_256_valid <= PROG(current_cmd)(11) WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0';
137
138
139
140
141
142
143
144
145
146
147 --OPERATION(1 DOWNTO 0) <= PROG(current_cmd)(1 DOWNTO 0);
148 --OPERATION(2) <= '0' WHEN STATE_CIC_LFR = IDLE ELSE
149 -- PROG(current_cmd)(2);
150 --OPERATION(5 DOWNTO 3) <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3)) WHEN STATE_CIC_LFR = RUN_PROG_I AND current_cmd = 0 ELSE
151 -- PROG(current_cmd)(5 DOWNTO 3);
152
153 --OPERATION(8 DOWNTO 6) <= "000" WHEN STATE_CIC_LFR = IDLE ELSE
154 -- PROG(current_cmd)(8 DOWNTO 6);
155 --OPERATION(11 DOWNTO 9) <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3));
156 --OPERATION(13 DOWNTO 12) <= PROG(current_cmd)(10 DOWNTO 9);
157 --OPERATION(14) <= PROG(current_cmd)(11) AND sample_16_odd WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE
158 -- PROG(current_cmd)(11) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0';
159
160 --OPERATION(15) <= PROG(current_cmd)(12);
161
162 --data_out_16_valid <= PROG(current_cmd)(13) WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE '0';
163 --data_out_256_valid <= PROG(current_cmd)(13) WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0';
164
165 PROCESS (clk, rstn)
166 BEGIN
167 IF rstn = '0' THEN
168 STATE_CIC_LFR <= IDLE;
169 nb_data_receipt <= 0;
170 current_channel <= 0;
171 current_cmd <= 0;
172 sample_16_odd <= '0';
173 sample_256_odd <= '0';
174
175 ELSIF clk'EVENT AND clk = '1' THEN
176
177 CASE STATE_CIC_LFR IS
178 WHEN IDLE =>
179 IF data_in_valid = '1' THEN
180 STATE_CIC_LFR <= RUN_PROG_I;
181 current_cmd <= PROG_START_I;
182 current_channel <= 0;
183 nb_data_receipt <= nb_data_receipt + 1;
184 END IF;
185
186 WHEN RUN_PROG_I =>
187 IF current_cmd = PROG_END_I THEN
188 IF nb_data_receipt MOD 16 = 15 THEN
189 STATE_CIC_LFR <= RUN_PROG_C16;
190 current_cmd <= PROG_START_C16;
191 IF current_channel = 0 THEN
192 sample_16_odd <= NOT sample_16_odd;
193 END IF;
194 ELSE
195 IF current_channel = 7 THEN
196 current_channel <= 0;
197 STATE_CIC_LFR <= IDLE;
198 ELSE
199 current_cmd <= PROG_START_I;
200 current_channel <= current_channel + 1;
201 END IF;
202 END IF;
203 ELSE
204 current_cmd <= current_cmd +1;
205 END IF;
206
207 WHEN RUN_PROG_C16 =>
208 IF current_cmd = PROG_END_C16 THEN
209 IF nb_data_receipt MOD 256 = 255 AND current_channel < 6 THEN
210 STATE_CIC_LFR <= RUN_PROG_C256;
211 current_cmd <= PROG_START_C256;
212 IF current_channel = 0 THEN
213 sample_256_odd <= NOT sample_256_odd;
214 END IF;
215 ELSE
216 IF current_channel = 7 THEN
217 current_channel <= 0;
218 STATE_CIC_LFR <= IDLE;
219 ELSE
220 STATE_CIC_LFR <= RUN_PROG_I;
221 current_cmd <= PROG_START_I;
222 current_channel <= current_channel + 1;
223 END IF;
224 END IF;
225 ELSE
226 current_cmd <= current_cmd +1;
227 END IF;
228
229 WHEN RUN_PROG_C256 =>
230 IF current_cmd = PROG_END_C256 THEN
231 -- data_out_256_valid <= '1';
232 -- IF current_channel = 5 THEN
233 -- current_channel <= 0;
234 -- STATE_CIC_LFR <= IDLE;
235 -- ELSE
236 STATE_CIC_LFR <= RUN_PROG_I;
237 current_cmd <= PROG_START_I;
238 current_channel <= current_channel + 1;
239 -- END IF;
240 ELSE
241 current_cmd <= current_cmd +1;
242 END IF;
243
244 WHEN OTHERS => NULL;
245 END CASE;
246 END IF;
247 END PROCESS;
248
249 END beh;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26 USE ieee.numeric_std.all;
27
28 LIBRARY lpp;
29 USE lpp.cic_pkg.ALL;
30 USE lpp.data_type_pkg.ALL;
31 USE lpp.iir_filter.ALL;
32
33 LIBRARY techmap;
34 USE techmap.gencomp.ALL;
35
36 ENTITY cic_lfr_r2 IS
37 GENERIC(
38 tech : INTEGER := 0;
39 use_RAM_nCEL : INTEGER := 0 -- 1 => RAM(tech) , 0 => RAM_CEL
40 );
41 PORT (
42 clk : IN STD_LOGIC;
43 rstn : IN STD_LOGIC;
44 run : IN STD_LOGIC;
45
46 param_r2 : IN STD_LOGIC;
47
48 data_in : IN sample_vector(7 DOWNTO 0,15 DOWNTO 0);
49 data_in_valid : IN STD_LOGIC;
50
51 data_out_16 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
52 data_out_16_valid : OUT STD_LOGIC;
53 data_out_256 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
54 data_out_256_valid : OUT STD_LOGIC
55 );
56
57 END cic_lfr_r2;
58
59 ARCHITECTURE beh OF cic_lfr_r2 IS
60 --
61 SIGNAL sel_sample : STD_LOGIC_VECTOR(2 DOWNTO 0);
62 SIGNAL sample_temp : sample_vector(5 DOWNTO 0,15 DOWNTO 0);
63 SIGNAL sample : STD_LOGIC_VECTOR(15 DOWNTO 0);
64 --
65 SIGNAL sel_A : STD_LOGIC_VECTOR(1 DOWNTO 0);
66 SIGNAL data_A_temp : sample_vector(2 DOWNTO 0,15 DOWNTO 0);
67 SIGNAL data_A : STD_LOGIC_VECTOR(15 DOWNTO 0);
68 --
69 SIGNAL ALU_OP : STD_LOGIC_VECTOR(1 DOWNTO 0);
70 SIGNAL data_B : STD_LOGIC_VECTOR(15 DOWNTO 0);
71 SIGNAL data_B_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
72 SIGNAL data_out : STD_LOGIC_VECTOR(15 DOWNTO 0);
73 SIGNAL data_in_Carry : STD_LOGIC;
74 SIGNAL data_out_Carry : STD_LOGIC;
75 --
76 CONSTANT S_parameter : INTEGER := 3;
77 SIGNAL carry_reg : STD_LOGIC_VECTOR(S_parameter-1 DOWNTO 0);
78 SIGNAL CARRY_PUSH : STD_LOGIC;
79 SIGNAL CARRY_POP : STD_LOGIC;
80 --
81
82 SIGNAL OPERATION : STD_LOGIC_VECTOR(15 DOWNTO 0);
83 SIGNAL OPERATION_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
84 SIGNAL OPERATION_reg2: STD_LOGIC_VECTOR(15 DOWNTO 0);
85
86 -----------------------------------------------------------------------------
87 TYPE ARRAY_OF_ADDR IS ARRAY (7 DOWNTO 0) OF STD_LOGIC_VECTOR(8 DOWNTO 0);
88 SIGNAL base_addr_INT : ARRAY_OF_ADDR;
89 CONSTANT base_addr_delta : INTEGER := 40;
90 SIGNAL addr_base_sel : STD_LOGIC_VECTOR(8 DOWNTO 0);
91 SIGNAL addr_gen: STD_LOGIC_VECTOR(8 DOWNTO 0);
92 SIGNAL addr_read: STD_LOGIC_VECTOR(8 DOWNTO 0);
93 SIGNAL addr_write: STD_LOGIC_VECTOR(8 DOWNTO 0);
94 SIGNAL addr_write_mux: STD_LOGIC_VECTOR(8 DOWNTO 0);
95 SIGNAL addr_write_s: STD_LOGIC_VECTOR(8 DOWNTO 0);
96 SIGNAL data_we: STD_LOGIC;
97 SIGNAL data_we_s: STD_LOGIC;
98 SIGNAL data_wen : STD_LOGIC;
99 -- SIGNAL data_write : STD_LOGIC_VECTOR(15 DOWNTO 0);
100 -- SIGNAL data_read : STD_LOGIC_VECTOR(15 DOWNTO 0);
101 -- SIGNAL data_read_pre : STD_LOGIC_VECTOR(15 DOWNTO 0);
102 -----------------------------------------------------------------------------
103 SIGNAL sample_out_reg16 : sample_vector(8*2-1 DOWNTO 0, 15 DOWNTO 0);
104 SIGNAL sample_out_reg256 : sample_vector(6*3-1 DOWNTO 0, 15 DOWNTO 0);
105 SIGNAL sample_valid_reg16 : STD_LOGIC_VECTOR(8*2 DOWNTO 0);
106 SIGNAL sample_valid_reg256: STD_LOGIC_VECTOR(6*3 DOWNTO 0);
107 SIGNAL data_out_16_valid_s : STD_LOGIC;
108 SIGNAL data_out_256_valid_s : STD_LOGIC;
109 SIGNAL data_out_16_valid_s1 : STD_LOGIC;
110 SIGNAL data_out_256_valid_s1 : STD_LOGIC;
111 SIGNAL data_out_16_valid_s2 : STD_LOGIC;
112 SIGNAL data_out_256_valid_s2 : STD_LOGIC;
113 -----------------------------------------------------------------------------
114 SIGNAL sample_out_reg16_s : sample_vector(5 DOWNTO 0, 16*2-1 DOWNTO 0);
115 SIGNAL sample_out_reg256_s : sample_vector(5 DOWNTO 0, 16*3-1 DOWNTO 0);
116 -----------------------------------------------------------------------------
117
118
119 BEGIN
120
121
122 PROCESS (clk, rstn)
123 BEGIN -- PROCESS
124 IF rstn = '0' THEN -- asynchronous reset (active low)
125 data_B_reg <= (OTHERS => '0');
126 OPERATION_reg <= (OTHERS => '0');
127 OPERATION_reg2 <= (OTHERS => '0');
128 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
129 OPERATION_reg <= OPERATION;
130 OPERATION_reg2 <= OPERATION_reg;
131 data_B_reg <= data_B;
132 END IF;
133 END PROCESS;
134
135
136 -----------------------------------------------------------------------------
137 -- SEL_SAMPLE
138 -----------------------------------------------------------------------------
139 sel_sample <= OPERATION_reg(2 DOWNTO 0);
140
141 all_bit: FOR I IN 15 DOWNTO 0 GENERATE
142 sample_temp(0,I) <= data_in(0,I) WHEN sel_sample(0) = '0' ELSE data_in(1,I);
143 sample_temp(1,I) <= data_in(2,I) WHEN sel_sample(0) = '0' ELSE data_in(3,I);
144 sample_temp(2,I) <= data_in(4,I) WHEN sel_sample(0) = '0' ELSE data_in(5,I);
145 sample_temp(3,I) <= data_in(6,I) WHEN sel_sample(0) = '0' ELSE data_in(7,I);
146
147 sample_temp(4,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE sample_temp(1,I);
148 sample_temp(5,I) <= sample_temp(2,I) WHEN sel_sample(1) = '0' ELSE sample_temp(3,I);
149
150 sample(I) <= sample_temp(4,I) WHEN sel_sample(2) = '0' ELSE sample_temp(5,I);
151 END GENERATE all_bit;
152
153 -----------------------------------------------------------------------------
154 -- SEL_DATA_IN_A
155 -----------------------------------------------------------------------------
156 sel_A <= OPERATION_reg(4 DOWNTO 3);
157
158 all_data_mux_A: FOR I IN 15 DOWNTO 0 GENERATE
159 data_A_temp(0,I) <= sample(I) WHEN sel_A(0) = '0' ELSE data_out(I);
160 data_A_temp(1,I) <= '0' WHEN sel_A(0) = '0' ELSE sample(15);
161 data_A_temp(2,I) <= data_A_temp(0,I) WHEN sel_A(1) = '0' ELSE data_A_temp(1,I);
162 data_A(I) <= data_A_temp(2,I) WHEN OPERATION_reg(14) = '0' ELSE data_B_reg(I);
163 END GENERATE all_data_mux_A;
164
165
166
167 -----------------------------------------------------------------------------
168 -- ALU
169 -----------------------------------------------------------------------------
170 ALU_OP <= OPERATION_reg(6 DOWNTO 5);
171
172 ALU: cic_lfr_add_sub
173 PORT MAP (
174 clk => clk,
175 rstn => rstn,
176 run => run,
177
178 OP => ALU_OP,
179
180 data_in_A => data_A,
181 data_in_B => data_B,
182 data_in_Carry => data_in_Carry,
183
184 data_out => data_out,
185 data_out_Carry => data_out_Carry);
186
187 -----------------------------------------------------------------------------
188 -- CARRY_MANAGER
189 -----------------------------------------------------------------------------
190 data_in_Carry <= carry_reg(S_parameter-2) WHEN OPERATION_reg(7) = '0' ELSE carry_reg(S_parameter-1);
191
192 -- CARRY_PUSH <= OPERATION_reg(7);
193 -- CARRY_POP <= OPERATION_reg(6);
194
195 PROCESS (clk, rstn)
196 BEGIN -- PROCESS
197 IF rstn = '0' THEN -- asynchronous reset (active low)
198 carry_reg <= (OTHERS => '0');
199 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
200 --IF CARRY_POP = '1' OR CARRY_PUSH = '1' THEN
201 carry_reg(S_parameter-1 DOWNTO 1) <= carry_reg(S_parameter-2 DOWNTO 0);
202 carry_reg(0) <= data_out_Carry;
203 --END IF;
204 END IF;
205 END PROCESS;
206
207 -----------------------------------------------------------------------------
208 -- MEMORY
209 -----------------------------------------------------------------------------
210 all_bit_base_ADDR: FOR J IN 8 DOWNTO 0 GENERATE
211 all_channel: FOR I IN 7 DOWNTO 0 GENERATE
212 base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0';
213 END GENERATE all_channel;
214 END GENERATE all_bit_base_ADDR;
215
216
217 addr_base_sel <= base_addr_INT(to_integer(UNSIGNED(OPERATION(2 DOWNTO 0))));
218
219 cic_lfr_address_gen_1: cic_lfr_address_gen
220 GENERIC MAP (
221 ADDR_SIZE => 9)
222 PORT MAP (
223 clk => clk,
224 rstn => rstn,
225 run => run,
226
227 addr_base => addr_base_sel,
228 addr_init => OPERATION(8),
229 addr_add_1 => OPERATION(9),
230 addr => addr_gen);
231
232
233 addr_read <= addr_gen WHEN OPERATION(12 DOWNTO 10) = "000" ELSE
234 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+2,9)) WHEN OPERATION(12 DOWNTO 10) = "001" ELSE
235 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+5,9)) WHEN OPERATION(12 DOWNTO 10) = "010" ELSE
236 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+8,9)) WHEN OPERATION(12 DOWNTO 10) = "011" ELSE
237 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen ))+6,9)) WHEN OPERATION(12 DOWNTO 10) = "100" ELSE
238 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen ))+15,9));
239
240 PROCESS (clk, rstn)
241 BEGIN -- PROCESS
242 IF rstn = '0' THEN -- asynchronous reset (active low)
243 addr_write <= (OTHERS => '0');
244 data_we <= '0';
245 addr_write_s <= (OTHERS => '0');
246 data_we_s <= '0';
247 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
248 addr_write_s <= addr_read;
249 data_we_s <= OPERATION(13);
250 IF OPERATION_reg(15) = '0' THEN
251 addr_write <= addr_write_s;
252 ELSE
253 addr_write <= addr_read;
254 END IF;
255 data_we <= data_we_s;
256 END IF;
257 END PROCESS;
258
259 memCEL : IF use_RAM_nCEL = 0 GENERATE
260 data_wen <= NOT data_we;
261 RAMblk : RAM_CEL
262 GENERIC MAP(16, 9)
263 PORT MAP(
264 WD => data_out,
265 RD => data_B,
266 WEN => data_wen,
267 REN => '0',
268 WADDR => addr_write,
269 RADDR => addr_read,
270 RWCLK => clk,
271 RESET => rstn
272 ) ;
273 END GENERATE;
274
275 memRAM : IF use_RAM_nCEL = 1 GENERATE
276 SRAM : syncram_2p
277 GENERIC MAP(tech, 9, 16)
278 PORT MAP(clk, '1', addr_read, data_B,
279 clk, data_we, addr_write, data_out);
280 END GENERATE;
281
282 -----------------------------------------------------------------------------
283 -- CONTROL
284 -----------------------------------------------------------------------------
285 cic_lfr_control_1: cic_lfr_control_r2
286 PORT MAP (
287 clk => clk,
288 rstn => rstn,
289 run => run,
290 data_in_valid => data_in_valid,
291 data_out_16_valid => data_out_16_valid_s,
292 data_out_256_valid => data_out_256_valid_s,
293 OPERATION => OPERATION);
294
295 -----------------------------------------------------------------------------
296 PROCESS (clk, rstn)
297 BEGIN -- PROCESS
298 IF rstn = '0' THEN -- asynchronous reset (active low)
299 data_out_16_valid_s1 <= '0';
300 data_out_256_valid_s1 <= '0';
301 data_out_16_valid_s2 <= '0';
302 data_out_256_valid_s2 <= '0';
303 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
304 data_out_16_valid_s1 <= data_out_16_valid_s;
305 data_out_256_valid_s1 <= data_out_256_valid_s;
306 data_out_16_valid_s2 <= data_out_16_valid_s1;
307 data_out_256_valid_s2 <= data_out_256_valid_s1;
308 END IF;
309 END PROCESS;
310
311 PROCESS (clk, rstn)
312 BEGIN -- PROCESS
313 IF rstn = '0' THEN -- asynchronous reset (active low)
314 sample_valid_reg16 <= "00000" & "000000" & "000001";
315 sample_valid_reg256 <= '0' & "000000" & "000000" & "000001";
316 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
317 IF run = '0' THEN
318 sample_valid_reg16 <= "00000" & "000000" & "000001";
319 sample_valid_reg256 <= '0' & "000000" & "000000" & "000001";
320 ELSE
321 IF data_out_16_valid_s2 = '1' OR sample_valid_reg16(8*2) = '1' THEN
322 sample_valid_reg16 <= sample_valid_reg16(8*2-1 DOWNTO 0) & sample_valid_reg16(8*2);
323 END IF;
324 IF data_out_256_valid_s2 = '1' OR sample_valid_reg256(6*3) = '1' THEN
325 sample_valid_reg256 <= sample_valid_reg256(6*3-1 DOWNTO 0) & sample_valid_reg256(6*3);
326 END IF;
327 END IF;
328 END IF;
329 END PROCESS;
330
331 data_out_16_valid <= sample_valid_reg16(8*2);
332 data_out_256_valid <= sample_valid_reg256(6*3);
333
334 -----------------------------------------------------------------------------
335
336 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
337 all_channel_out16: FOR I IN 8*2-1 DOWNTO 0 GENERATE
338 PROCESS (clk, rstn)
339 BEGIN -- PROCESS
340 IF rstn = '0' THEN -- asynchronous reset (active low)
341 sample_out_reg16(I,J) <= '0';
342 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
343 IF run = '0' THEN
344 sample_out_reg16(I,J) <= '0';
345 ELSE
346 IF sample_valid_reg16(I) = '1' AND data_out_16_valid_s2 = '1' THEN
347 sample_out_reg16(I,J) <= data_out(J);
348 END IF;
349 END IF;
350 END IF;
351 END PROCESS;
352 END GENERATE all_channel_out16;
353
354 all_channel_out256: FOR I IN 6*3-1 DOWNTO 0 GENERATE
355 PROCESS (clk, rstn)
356 BEGIN -- PROCESS
357 IF rstn = '0' THEN -- asynchronous reset (active low)
358 sample_out_reg256(I,J) <= '0';
359 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
360 IF run = '0' THEN
361 sample_out_reg256(I,J) <= '0';
362 ELSE
363 IF sample_valid_reg256(I) = '1' AND data_out_256_valid_s2 = '1' THEN
364 sample_out_reg256(I,J) <= data_out(J);
365 END IF;
366 END IF;
367 END IF;
368 END PROCESS;
369 END GENERATE all_channel_out256;
370 END GENERATE all_bits;
371
372
373 all_bits_16: FOR J IN 15 DOWNTO 0 GENERATE
374 all_reg_16: FOR K IN 1 DOWNTO 0 GENERATE
375 sample_out_reg16_s(0,J+(K*16)) <= sample_out_reg16(2*0+K,J);
376 sample_out_reg16_s(1,J+(K*16)) <= sample_out_reg16(2*1+K,J) WHEN param_r2 = '1' ELSE sample_out_reg16(2*6+K,J);
377 sample_out_reg16_s(2,J+(K*16)) <= sample_out_reg16(2*2+K,J) WHEN param_r2 = '1' ELSE sample_out_reg16(2*7+K,J);
378 sample_out_reg16_s(3,J+(K*16)) <= sample_out_reg16(2*3+K,J);
379 sample_out_reg16_s(4,J+(K*16)) <= sample_out_reg16(2*4+K,J);
380 sample_out_reg16_s(5,J+(K*16)) <= sample_out_reg16(2*5+K,J);
381 END GENERATE all_reg_16;
382 END GENERATE all_bits_16;
383
384 all_channel_out_256: FOR I IN 5 DOWNTO 0 GENERATE
385 all_bits_256: FOR J IN 15 DOWNTO 0 GENERATE
386 all_reg_256: FOR K IN 2 DOWNTO 0 GENERATE
387 sample_out_reg256_s(I,J+(K*16)) <= sample_out_reg256(3*I+K,J);
388 END GENERATE all_reg_256;
389 END GENERATE all_bits_256;
390 END GENERATE all_channel_out_256;
391
392 all_channel_out_v: FOR I IN 5 DOWNTO 0 GENERATE
393 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
394 data_out_256(I,J) <= sample_out_reg256_s(I,J+16*2-32+27);
395 data_out_16(I,J) <= sample_out_reg16_s (I,J+16 -16+15);
396 END GENERATE all_bits;
397 END GENERATE all_channel_out_v;
398
399 END beh;
400
Show file before | Show file after | Hide comments
@@ -518,7 +518,7 BEGIN -- beh
518 pirq_ms => 6,
518 pirq_ms => 6,
519 pirq_wfp => 14,
519 pirq_wfp => 14,
520 hindex => 2,
520 hindex => 2,
521 top_lfr_version => X"000135") -- aa.bb.cc version
521 top_lfr_version => X"000138") -- aa.bb.cc version
522 PORT MAP (
522 PORT MAP (
523 clk => clk_25,
523 clk => clk_25,
524 rstn => LFR_rstn,
524 rstn => LFR_rstn,
Show file before | Show file after | Hide comments
@@ -11,13 +11,16 vcom -quiet -93 -work lpp ../../lib/l
11 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr_add_sub.vhd
11 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr_add_sub.vhd
12 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr_address_gen.vhd
12 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr_address_gen.vhd
13
13
14 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr_r2.vhd
15 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr_control_r2.vhd
16
14 vcom -quiet -93 -work work tb.vhd
17 vcom -quiet -93 -work work tb.vhd
15
18
16 vsim work.testbench
19 vsim work.testbench
17
20
18 log -r *
21 log -r *
19
22
20 do wave_inout.do
23 do wave.do
21
24
22 run -all
25 run -all
23
26
Show file before | Show file after | Hide comments
@@ -20,7 +20,8 ARCHITECTURE behav OF testbench IS
20 SIGNAL rstn : STD_LOGIC;
20 SIGNAL rstn : STD_LOGIC;
21 SIGNAL run : STD_LOGIC;
21 SIGNAL run : STD_LOGIC;
22 SIGNAL data_in : STD_LOGIC_VECTOR(15 DOWNTO 0);
22 SIGNAL data_in : STD_LOGIC_VECTOR(15 DOWNTO 0);
23 SIGNAL data_gen : STD_LOGIC_VECTOR(15 DOWNTO 0);
23 SIGNAL data_gen : STD_LOGIC_VECTOR(15 DOWNTO 0);
24 SIGNAL data_in_v_r2 : sample_vector(7 DOWNTO 0,15 DOWNTO 0);
24 SIGNAL data_in_v : sample_vector(5 DOWNTO 0,15 DOWNTO 0);
25 SIGNAL data_in_v : sample_vector(5 DOWNTO 0,15 DOWNTO 0);
25 SIGNAL data_in_valid : STD_LOGIC;
26 SIGNAL data_in_valid : STD_LOGIC;
26
27
@@ -47,6 +48,8 ARCHITECTURE behav OF testbench IS
47 SIGNAL data_in_4_temp : STD_LOGIC_VECTOR(15 DOWNTO 0);
48 SIGNAL data_in_4_temp : STD_LOGIC_VECTOR(15 DOWNTO 0);
48 SIGNAL data_in_5_temp : STD_LOGIC_VECTOR(15 DOWNTO 0);
49 SIGNAL data_in_5_temp : STD_LOGIC_VECTOR(15 DOWNTO 0);
49
50
51 SIGNAL param_r2 : STD_LOGIC;
52
50 BEGIN
53 BEGIN
51
54
52
55
@@ -75,14 +78,16 BEGIN
75 WAIT UNTIL clk = '1';
78 WAIT UNTIL clk = '1';
76 rstn <= '0';
79 rstn <= '0';
77 run <= '0';
80 run <= '0';
78
81 param_r2 <= '1';
79 WAIT UNTIL clk = '1';
82 WAIT UNTIL clk = '1';
80 rstn <= '1';
83 rstn <= '1';
81 WAIT UNTIL clk = '1';
84 WAIT UNTIL clk = '1';
82 WAIT UNTIL clk = '1';
85 WAIT UNTIL clk = '1';
83 run <= '1';
86 run <= '1';
84 WAIT UNTIL clk = '1';
87 WAIT UNTIL clk = '1';
85
88
89 WAIT FOR 30 ms;
90 param_r2 <= '0';
86
91
87 WAIT FOR 30 ms;
92 WAIT FOR 30 ms;
88 REPORT "*** END simulation ***" SEVERITY failure;
93 REPORT "*** END simulation ***" SEVERITY failure;
@@ -104,6 +109,34 BEGIN
104 data_out_256 => OPEN,
109 data_out_256 => OPEN,
105 data_out_256_valid => OPEN);
110 data_out_256_valid => OPEN);
106 -----------------------------------------------------------------------------
111 -----------------------------------------------------------------------------
112 cic_lfr_r2_1: cic_lfr_r2
113 GENERIC MAP (
114 tech => 0,
115 use_RAM_nCEL => 0)
116 PORT MAP (
117 clk => clk,
118 rstn => rstn,
119 run => run,
120 param_r2 => param_r2,
121 data_in => data_in_v_r2,
122 data_in_valid => data_in_valid,
123 data_out_16 => OPEN,
124 data_out_16_valid => OPEN,
125 data_out_256 => OPEN,
126 data_out_256_valid => OPEN);
127
128 -----------------------------------------------------------------------------
129 all_bit_r2: FOR J IN 15 DOWNTO 0 GENERATE
130 data_in_v_r2(0,J) <= data_in_0(J);
131 data_in_v_r2(1,J) <= data_in_1(J);
132 data_in_v_r2(2,J) <= data_in_2(J);
133 data_in_v_r2(3,J) <= data_in_3(J);
134 data_in_v_r2(4,J) <= data_in_4(J);
135 data_in_v_r2(5,J) <= data_in_5(J);
136 data_in_v_r2(6,J) <= data_in_0(J);
137 data_in_v_r2(7,J) <= data_in_0(J);
138 END GENERATE all_bit_r2;
139 -----------------------------------------------------------------------------
107 all_bit: FOR J IN 15 DOWNTO 0 GENERATE
140 all_bit: FOR J IN 15 DOWNTO 0 GENERATE
108 data_in_v(0,J) <= data_in_0(J);
141 data_in_v(0,J) <= data_in_0(J);
109 data_in_v(1,J) <= data_in_1(J);
142 data_in_v(1,J) <= data_in_1(J);
Show file before | Show file after | Hide comments
@@ -1,119 +1,378
1 onerror {resume}
1 onerror {resume}
2 quietly virtual signal -install /testbench/cic_lfr_r2_1/memCEL/RAMblk { (context /testbench/cic_lfr_r2_1/memCEL/RAMblk )(RAMarray(0) &RAMarray(1) &RAMarray(2) &RAMarray(3) &RAMarray(4) &RAMarray(5) &RAMarray(6) &RAMarray(7) &RAMarray(8) &RAMarray(9) &RAMarray(10) &RAMarray(11) &RAMarray(12) &RAMarray(13) &RAMarray(14) &RAMarray(15) &RAMarray(16) &RAMarray(17) &RAMarray(18) &RAMarray(19) &RAMarray(20) &RAMarray(21) &RAMarray(22) &RAMarray(23) &RAMarray(24) &RAMarray(25) &RAMarray(26) &RAMarray(27) &RAMarray(28) &RAMarray(29) &RAMarray(30) &RAMarray(31) &RAMarray(32) &RAMarray(33) &RAMarray(34) &RAMarray(35) &RAMarray(36) &RAMarray(37) &RAMarray(38) &RAMarray(39) )} R2_RAM_lane0
3 quietly virtual signal -install /testbench/cic_lfr_r2_1/memCEL/RAMblk { (context /testbench/cic_lfr_r2_1/memCEL/RAMblk )(RAMarray(40) &RAMarray(41) &RAMarray(42) &RAMarray(43) &RAMarray(44) &RAMarray(45) &RAMarray(46) &RAMarray(47) &RAMarray(48) &RAMarray(49) &RAMarray(50) &RAMarray(51) &RAMarray(52) &RAMarray(53) &RAMarray(54) &RAMarray(55) &RAMarray(56) &RAMarray(57) &RAMarray(58) &RAMarray(59) &RAMarray(60) &RAMarray(61) &RAMarray(62) &RAMarray(63) &RAMarray(64) &RAMarray(65) &RAMarray(66) &RAMarray(67) &RAMarray(68) &RAMarray(69) &RAMarray(70) &RAMarray(71) &RAMarray(72) &RAMarray(73) &RAMarray(74) &RAMarray(75) &RAMarray(76) &RAMarray(77) &RAMarray(78) &RAMarray(79) )} R2_RAM_lane0001
4 quietly virtual signal -install /testbench/cic_lfr_r2_1/memCEL/RAMblk { (context /testbench/cic_lfr_r2_1/memCEL/RAMblk )(RAMarray(80) &RAMarray(81) &RAMarray(82) &RAMarray(83) &RAMarray(84) &RAMarray(85) &RAMarray(86) &RAMarray(87) &RAMarray(88) &RAMarray(89) &RAMarray(90) &RAMarray(91) &RAMarray(92) &RAMarray(93) &RAMarray(94) &RAMarray(95) &RAMarray(96) &RAMarray(97) &RAMarray(98) &RAMarray(99) &RAMarray(100) &RAMarray(101) &RAMarray(102) &RAMarray(103) &RAMarray(104) &RAMarray(105) &RAMarray(106) &RAMarray(107) &RAMarray(108) &RAMarray(109) &RAMarray(110) &RAMarray(111) &RAMarray(112) &RAMarray(113) &RAMarray(114) &RAMarray(115) &RAMarray(116) &RAMarray(117) &RAMarray(118) &RAMarray(119) )} R2_RAM_lane2
5 quietly virtual signal -install /testbench/cic_lfr_r2_1/memCEL/RAMblk { (context /testbench/cic_lfr_r2_1/memCEL/RAMblk )(RAMarray(120) &RAMarray(121) &RAMarray(122) &RAMarray(123) &RAMarray(124) &RAMarray(125) &RAMarray(126) &RAMarray(127) &RAMarray(128) &RAMarray(129) &RAMarray(130) &RAMarray(131) &RAMarray(132) &RAMarray(133) &RAMarray(134) &RAMarray(135) &RAMarray(136) &RAMarray(137) &RAMarray(138) &RAMarray(139) &RAMarray(140) &RAMarray(141) &RAMarray(142) &RAMarray(143) &RAMarray(144) &RAMarray(145) &RAMarray(146) &RAMarray(147) &RAMarray(148) &RAMarray(149) &RAMarray(150) &RAMarray(151) &RAMarray(152) &RAMarray(153) &RAMarray(154) &RAMarray(155) &RAMarray(156) &RAMarray(157) &RAMarray(158) &RAMarray(159) )} R2_RAM_lane3
6 quietly virtual signal -install /testbench/cic_lfr_r2_1/memCEL/RAMblk { (context /testbench/cic_lfr_r2_1/memCEL/RAMblk )(RAMarray(160) &RAMarray(161) &RAMarray(162) &RAMarray(163) &RAMarray(164) &RAMarray(165) &RAMarray(166) &RAMarray(167) &RAMarray(168) &RAMarray(169) &RAMarray(170) &RAMarray(171) &RAMarray(172) &RAMarray(173) &RAMarray(174) &RAMarray(175) &RAMarray(176) &RAMarray(177) &RAMarray(178) &RAMarray(179) &RAMarray(180) &RAMarray(181) &RAMarray(182) &RAMarray(183) &RAMarray(184) &RAMarray(185) &RAMarray(186) &RAMarray(187) &RAMarray(188) &RAMarray(189) &RAMarray(190) &RAMarray(191) &RAMarray(192) &RAMarray(193) &RAMarray(194) &RAMarray(195) &RAMarray(196) &RAMarray(197) &RAMarray(198) &RAMarray(199) )} R2_RAM_lane4
7 quietly virtual signal -install /testbench/cic_lfr_r2_1/memCEL/RAMblk { (context /testbench/cic_lfr_r2_1/memCEL/RAMblk )(RAMarray(200) &RAMarray(201) &RAMarray(202) &RAMarray(203) &RAMarray(204) &RAMarray(205) &RAMarray(206) &RAMarray(207) &RAMarray(208) &RAMarray(209) &RAMarray(210) &RAMarray(211) &RAMarray(212) &RAMarray(213) &RAMarray(214) &RAMarray(215) &RAMarray(216) &RAMarray(217) &RAMarray(218) &RAMarray(219) &RAMarray(220) &RAMarray(221) &RAMarray(222) &RAMarray(223) &RAMarray(224) &RAMarray(225) &RAMarray(226) &RAMarray(227) &RAMarray(228) &RAMarray(229) &RAMarray(230) &RAMarray(231) &RAMarray(232) &RAMarray(233) &RAMarray(234) &RAMarray(235) &RAMarray(236) &RAMarray(237) &RAMarray(238) &RAMarray(239) )} R2_RAM_lane5
8 quietly virtual signal -install /testbench/cic_lfr_r2_1/memCEL/RAMblk { (context /testbench/cic_lfr_r2_1/memCEL/RAMblk )(RAMarray(240) &RAMarray(241) &RAMarray(242) &RAMarray(243) &RAMarray(244) &RAMarray(245) &RAMarray(246) &RAMarray(247) &RAMarray(248) &RAMarray(249) &RAMarray(250) &RAMarray(251) &RAMarray(252) &RAMarray(253) &RAMarray(254) &RAMarray(255) &RAMarray(256) &RAMarray(257) &RAMarray(258) &RAMarray(259) &RAMarray(260) &RAMarray(261) &RAMarray(262) &RAMarray(263) &RAMarray(264) &RAMarray(265) &RAMarray(266) &RAMarray(267) &RAMarray(268) &RAMarray(269) &RAMarray(270) &RAMarray(271) &RAMarray(272) &RAMarray(273) &RAMarray(274) &RAMarray(275) &RAMarray(276) &RAMarray(277) &RAMarray(278) &RAMarray(279) )} R2_RAM_lane5001
9 quietly virtual signal -install /testbench/cic_lfr_r2_1/memCEL/RAMblk { (context /testbench/cic_lfr_r2_1/memCEL/RAMblk )(RAMarray(280) &RAMarray(281) &RAMarray(282) &RAMarray(283) &RAMarray(284) &RAMarray(285) &RAMarray(286) &RAMarray(287) &RAMarray(288) &RAMarray(289) &RAMarray(290) &RAMarray(291) &RAMarray(292) &RAMarray(293) &RAMarray(294) &RAMarray(295) &RAMarray(296) &RAMarray(297) &RAMarray(298) &RAMarray(299) &RAMarray(300) &RAMarray(301) &RAMarray(302) &RAMarray(303) &RAMarray(304) &RAMarray(305) &RAMarray(306) &RAMarray(307) &RAMarray(308) &RAMarray(309) &RAMarray(310) &RAMarray(311) &RAMarray(312) &RAMarray(313) &RAMarray(314) &RAMarray(315) &RAMarray(316) &RAMarray(317) &RAMarray(318) &RAMarray(319) )} R2_RAM_lane7
2 quietly WaveActivateNextPane {} 0
10 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group out -radix hexadecimal /testbench/cic_1/data_out_valid
11 add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_in
4 add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group out -radix decimal /testbench/cic_1/data_out
12 add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_in_valid
5 add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group in -radix decimal /testbench/cic_1/data_in
13 add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_out
6 add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group in -radix hexadecimal /testbench/cic_1/data_in_valid
14 add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_out_valid
7 add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group int -radix hexadecimal -childformat {{/testbench/cic_1/I_data(3) -radix hexadecimal} {/testbench/cic_1/I_data(2) -radix hexadecimal} {/testbench/cic_1/I_data(1) -radix hexadecimal} {/testbench/cic_1/I_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/I_data(3) {-radix hexadecimal} /testbench/cic_1/I_data(2) {-radix hexadecimal} /testbench/cic_1/I_data(1) {-radix hexadecimal} /testbench/cic_1/I_data(0) {-radix hexadecimal}} /testbench/cic_1/I_data
15 add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/I_data
8 add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group int -radix hexadecimal /testbench/cic_1/I_valid
16 add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/I_valid
9 add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group COMB_1 -radix decimal /testbench/cic_1/all_C(1)/cic_comb_1/data_in
17 add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/C_data
10 add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group COMB_1 -radix decimal /testbench/cic_1/all_C(1)/cic_comb_1/data_in_valid
18 add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/C_valid
11 add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group COMB_1 -radix decimal -childformat {{/testbench/cic_1/all_C(1)/cic_comb_1/data_reg(2) -radix decimal} {/testbench/cic_1/all_C(1)/cic_comb_1/data_reg(1) -radix decimal} {/testbench/cic_1/all_C(1)/cic_comb_1/data_reg(0) -radix decimal}} -expand -subitemconfig {/testbench/cic_1/all_C(1)/cic_comb_1/data_reg(2) {-radix decimal} /testbench/cic_1/all_C(1)/cic_comb_1/data_reg(1) {-radix decimal} /testbench/cic_1/all_C(1)/cic_comb_1/data_reg(0) {-radix decimal}} /testbench/cic_1/all_C(1)/cic_comb_1/data_reg
19 add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_in
12 add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group COMB_1 -radix decimal /testbench/cic_1/all_C(1)/cic_comb_1/data_out_valid
20 add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_in_valid
13 add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group COMB_1 -radix decimal /testbench/cic_1/all_C(1)/cic_comb_1/data_out
21 add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_out
14 add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group comb -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3) -radix hexadecimal} {/testbench/cic_1/C_data(2) -radix hexadecimal} {/testbench/cic_1/C_data(1) -radix hexadecimal} {/testbench/cic_1/C_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/C_data(3) {-radix hexadecimal} /testbench/cic_1/C_data(2) {-radix hexadecimal} /testbench/cic_1/C_data(1) {-radix hexadecimal} /testbench/cic_1/C_data(0) {-radix hexadecimal}} /testbench/cic_1/C_data
22 add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_out_valid
15 add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group comb -radix hexadecimal /testbench/cic_1/C_valid
23 add wave -noupdate -expand -group CIC_16 -radix hexadecimal -childformat {{/testbench/cic_1/I_data(3) -radix hexadecimal} {/testbench/cic_1/I_data(2) -radix hexadecimal} {/testbench/cic_1/I_data(1) -radix hexadecimal} {/testbench/cic_1/I_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/I_data(3) {-height 15 -radix hexadecimal} /testbench/cic_1/I_data(2) {-height 15 -radix hexadecimal} /testbench/cic_1/I_data(1) {-height 15 -radix hexadecimal} /testbench/cic_1/I_data(0) {-height 15 -radix hexadecimal}} /testbench/cic_1/I_data
16 add wave -noupdate -expand -group C16_REG -group C0 -expand -group C0_0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(9)
24 add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/I_valid
17 add wave -noupdate -expand -group C16_REG -group C0 -expand -group C0_0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(12)
25 add wave -noupdate -expand -group CIC_16 -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3) -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3)(30) -radix hexadecimal} {/testbench/cic_1/C_data(3)(29) -radix hexadecimal} {/testbench/cic_1/C_data(3)(28) -radix hexadecimal} {/testbench/cic_1/C_data(3)(27) -radix hexadecimal} {/testbench/cic_1/C_data(3)(26) -radix hexadecimal} {/testbench/cic_1/C_data(3)(25) -radix hexadecimal} {/testbench/cic_1/C_data(3)(24) -radix hexadecimal} {/testbench/cic_1/C_data(3)(23) -radix hexadecimal} {/testbench/cic_1/C_data(3)(22) -radix hexadecimal} {/testbench/cic_1/C_data(3)(21) -radix hexadecimal} {/testbench/cic_1/C_data(3)(20) -radix hexadecimal} {/testbench/cic_1/C_data(3)(19) -radix hexadecimal} {/testbench/cic_1/C_data(3)(18) -radix hexadecimal} {/testbench/cic_1/C_data(3)(17) -radix hexadecimal} {/testbench/cic_1/C_data(3)(16) -radix hexadecimal} {/testbench/cic_1/C_data(3)(15) -radix hexadecimal} {/testbench/cic_1/C_data(3)(14) -radix hexadecimal} {/testbench/cic_1/C_data(3)(13) -radix hexadecimal} {/testbench/cic_1/C_data(3)(12) -radix hexadecimal} {/testbench/cic_1/C_data(3)(11) -radix hexadecimal} {/testbench/cic_1/C_data(3)(10) -radix hexadecimal} {/testbench/cic_1/C_data(3)(9) -radix hexadecimal} {/testbench/cic_1/C_data(3)(8) -radix hexadecimal} {/testbench/cic_1/C_data(3)(7) -radix hexadecimal} {/testbench/cic_1/C_data(3)(6) -radix hexadecimal} {/testbench/cic_1/C_data(3)(5) -radix hexadecimal} {/testbench/cic_1/C_data(3)(4) -radix hexadecimal} {/testbench/cic_1/C_data(3)(3) -radix hexadecimal} {/testbench/cic_1/C_data(3)(2) -radix hexadecimal} {/testbench/cic_1/C_data(3)(1) -radix hexadecimal} {/testbench/cic_1/C_data(3)(0) -radix hexadecimal}}} {/testbench/cic_1/C_data(2) -radix hexadecimal} {/testbench/cic_1/C_data(1) -radix hexadecimal} {/testbench/cic_1/C_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/C_data(3) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3)(30) -radix hexadecimal} {/testbench/cic_1/C_data(3)(29) -radix hexadecimal} {/testbench/cic_1/C_data(3)(28) -radix hexadecimal} {/testbench/cic_1/C_data(3)(27) -radix hexadecimal} {/testbench/cic_1/C_data(3)(26) -radix hexadecimal} {/testbench/cic_1/C_data(3)(25) -radix hexadecimal} {/testbench/cic_1/C_data(3)(24) -radix hexadecimal} {/testbench/cic_1/C_data(3)(23) -radix hexadecimal} {/testbench/cic_1/C_data(3)(22) -radix hexadecimal} {/testbench/cic_1/C_data(3)(21) -radix hexadecimal} {/testbench/cic_1/C_data(3)(20) -radix hexadecimal} {/testbench/cic_1/C_data(3)(19) -radix hexadecimal} {/testbench/cic_1/C_data(3)(18) -radix hexadecimal} {/testbench/cic_1/C_data(3)(17) -radix hexadecimal} {/testbench/cic_1/C_data(3)(16) -radix hexadecimal} {/testbench/cic_1/C_data(3)(15) -radix hexadecimal} {/testbench/cic_1/C_data(3)(14) -radix hexadecimal} {/testbench/cic_1/C_data(3)(13) -radix hexadecimal} {/testbench/cic_1/C_data(3)(12) -radix hexadecimal} {/testbench/cic_1/C_data(3)(11) -radix hexadecimal} {/testbench/cic_1/C_data(3)(10) -radix hexadecimal} {/testbench/cic_1/C_data(3)(9) -radix hexadecimal} {/testbench/cic_1/C_data(3)(8) -radix hexadecimal} {/testbench/cic_1/C_data(3)(7) -radix hexadecimal} {/testbench/cic_1/C_data(3)(6) -radix hexadecimal} {/testbench/cic_1/C_data(3)(5) -radix hexadecimal} {/testbench/cic_1/C_data(3)(4) -radix hexadecimal} {/testbench/cic_1/C_data(3)(3) -radix hexadecimal} {/testbench/cic_1/C_data(3)(2) -radix hexadecimal} {/testbench/cic_1/C_data(3)(1) -radix hexadecimal} {/testbench/cic_1/C_data(3)(0) -radix hexadecimal}}} /testbench/cic_1/C_data(3)(30) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(29) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(28) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(27) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(26) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(25) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(24) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(23) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(22) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(21) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(20) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(19) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(18) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(17) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(16) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(15) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(14) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(13) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(12) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(11) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(10) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(9) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(8) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(7) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(6) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(5) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(4) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(3) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(2) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(1) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(0) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(2) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(1) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(0) {-height 15 -radix hexadecimal}} /testbench/cic_1/C_data
18 add wave -noupdate -expand -group C16_REG -group C0 -expand -group C0_1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(15)
26 add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/C_valid
19 add wave -noupdate -expand -group C16_REG -group C0 -expand -group C0_1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(18)
27 add wave -noupdate -expand -group CIC_LFR -radix decimal -childformat {{/testbench/cic_lfr_1/data_in(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/data_in(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_in
20 add wave -noupdate -expand -group C16_REG -group C0 -radix hexadecimal /testbench/cic_1/C_data(0)
28 add wave -noupdate -expand -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_in_valid
21 add wave -noupdate -expand -group C16_REG -group C1 -expand -group C1_0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(10)
29 add wave -noupdate -expand -group CIC_LFR -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}}}} -expand -subitemconfig {/testbench/cic_lfr_1/data_out_16(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/data_out_16(0)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_out_16
22 add wave -noupdate -expand -group C16_REG -group C1 -expand -group C1_0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(13)
30 add wave -noupdate -expand -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_out_16_valid
23 add wave -noupdate -expand -group C16_REG -group C1 -expand -group C1_1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(16)
31 add wave -noupdate -expand -group CIC_LFR -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_256(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/data_out_256(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_out_256
24 add wave -noupdate -expand -group C16_REG -group C1 -expand -group C1_1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(19)
32 add wave -noupdate -expand -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_out_256_valid
25 add wave -noupdate -expand -group C16_REG -group C1 -radix hexadecimal /testbench/cic_1/C_data(1)
33 add wave -noupdate -format Analog-Step -height 74 -max 6000000.0 -min 6.0000000000000002e-06 -radix decimal /testbench/cic_lfr_1/sample_out_reg16_s(0)
26 add wave -noupdate -expand -group C16_REG -group C2 -expand -group C2_0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(11)
34 add wave -noupdate -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal /testbench/cic_1/data_out
27 add wave -noupdate -expand -group C16_REG -group C2 -expand -group C2_0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(14)
35 add wave -noupdate -group temp -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/data_out_16(0)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_out_16(0)
28 add wave -noupdate -expand -group C16_REG -group C2 -expand -group C2_1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(17)
36 add wave -noupdate -group temp -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(0) -radix hexadecimal}}} {/testbench/cic_lfr_1/sample_out_reg16_s(4) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(4)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(0) -radix hexadecimal}}} {/testbench/cic_lfr_1/sample_out_reg16_s(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/sample_out_reg16_s(5) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/sample_out_reg16_s(5)(31) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(30) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(29) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(28) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(27) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(26) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(25) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(24) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(23) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(22) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(21) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(20) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(19) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(18) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(17) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(16) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(0) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(4)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/sample_out_reg16_s(4)(31) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(30) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(29) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(28) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(27) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(26) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(25) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(24) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(23) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(22) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(21) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(20) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(19) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(18) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(17) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(16) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(0) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg16_s
29 add wave -noupdate -expand -group C16_REG -group C2 -expand -group C2_1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(20)
37 add wave -noupdate -group temp -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg256_s(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/sample_out_reg256_s(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg256_s
30 add wave -noupdate -expand -group C16_REG -group C2 -radix hexadecimal /testbench/cic_1/C_data(2)
38 add wave -noupdate -group temp -format Analog-Step -height 74 -max 6000000.0 -min 6.0000000000000002e-06 -radix decimal /testbench/cic_lfr_1/sample_out_reg16_s(0)
31 add wave -noupdate -expand -group C16_REG -expand -group {C3 - OUTPUT} -radix decimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/sample_out_reg16_s(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg16_s
39 add wave -noupdate -group temp -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal /testbench/cic_1/data_out
32 add wave -noupdate -expand -group C16_REG -expand -group {C3 - OUTPUT} -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3)(31) -radix hexadecimal} {/testbench/cic_1/C_data(3)(30) -radix hexadecimal} {/testbench/cic_1/C_data(3)(29) -radix hexadecimal} {/testbench/cic_1/C_data(3)(28) -radix hexadecimal} {/testbench/cic_1/C_data(3)(27) -radix hexadecimal} {/testbench/cic_1/C_data(3)(26) -radix hexadecimal} {/testbench/cic_1/C_data(3)(25) -radix hexadecimal} {/testbench/cic_1/C_data(3)(24) -radix hexadecimal} {/testbench/cic_1/C_data(3)(23) -radix hexadecimal} {/testbench/cic_1/C_data(3)(22) -radix hexadecimal} {/testbench/cic_1/C_data(3)(21) -radix hexadecimal} {/testbench/cic_1/C_data(3)(20) -radix hexadecimal} {/testbench/cic_1/C_data(3)(19) -radix hexadecimal} {/testbench/cic_1/C_data(3)(18) -radix hexadecimal} {/testbench/cic_1/C_data(3)(17) -radix hexadecimal} {/testbench/cic_1/C_data(3)(16) -radix hexadecimal} {/testbench/cic_1/C_data(3)(15) -radix hexadecimal} {/testbench/cic_1/C_data(3)(14) -radix hexadecimal} {/testbench/cic_1/C_data(3)(13) -radix hexadecimal} {/testbench/cic_1/C_data(3)(12) -radix hexadecimal} {/testbench/cic_1/C_data(3)(11) -radix hexadecimal} {/testbench/cic_1/C_data(3)(10) -radix hexadecimal} {/testbench/cic_1/C_data(3)(9) -radix hexadecimal} {/testbench/cic_1/C_data(3)(8) -radix hexadecimal} {/testbench/cic_1/C_data(3)(7) -radix hexadecimal} {/testbench/cic_1/C_data(3)(6) -radix hexadecimal} {/testbench/cic_1/C_data(3)(5) -radix hexadecimal} {/testbench/cic_1/C_data(3)(4) -radix hexadecimal} {/testbench/cic_1/C_data(3)(3) -radix hexadecimal} {/testbench/cic_1/C_data(3)(2) -radix hexadecimal} {/testbench/cic_1/C_data(3)(1) -radix hexadecimal} {/testbench/cic_1/C_data(3)(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_1/C_data(3)(31) {-radix hexadecimal} /testbench/cic_1/C_data(3)(30) {-radix hexadecimal} /testbench/cic_1/C_data(3)(29) {-radix hexadecimal} /testbench/cic_1/C_data(3)(28) {-radix hexadecimal} /testbench/cic_1/C_data(3)(27) {-radix hexadecimal} /testbench/cic_1/C_data(3)(26) {-radix hexadecimal} /testbench/cic_1/C_data(3)(25) {-radix hexadecimal} /testbench/cic_1/C_data(3)(24) {-radix hexadecimal} /testbench/cic_1/C_data(3)(23) {-radix hexadecimal} /testbench/cic_1/C_data(3)(22) {-radix hexadecimal} /testbench/cic_1/C_data(3)(21) {-radix hexadecimal} /testbench/cic_1/C_data(3)(20) {-radix hexadecimal} /testbench/cic_1/C_data(3)(19) {-radix hexadecimal} /testbench/cic_1/C_data(3)(18) {-radix hexadecimal} /testbench/cic_1/C_data(3)(17) {-radix hexadecimal} /testbench/cic_1/C_data(3)(16) {-radix hexadecimal} /testbench/cic_1/C_data(3)(15) {-radix hexadecimal} /testbench/cic_1/C_data(3)(14) {-radix hexadecimal} /testbench/cic_1/C_data(3)(13) {-radix hexadecimal} /testbench/cic_1/C_data(3)(12) {-radix hexadecimal} /testbench/cic_1/C_data(3)(11) {-radix hexadecimal} /testbench/cic_1/C_data(3)(10) {-radix hexadecimal} /testbench/cic_1/C_data(3)(9) {-radix hexadecimal} /testbench/cic_1/C_data(3)(8) {-radix hexadecimal} /testbench/cic_1/C_data(3)(7) {-radix hexadecimal} /testbench/cic_1/C_data(3)(6) {-radix hexadecimal} /testbench/cic_1/C_data(3)(5) {-radix hexadecimal} /testbench/cic_1/C_data(3)(4) {-radix hexadecimal} /testbench/cic_1/C_data(3)(3) {-radix hexadecimal} /testbench/cic_1/C_data(3)(2) {-radix hexadecimal} /testbench/cic_1/C_data(3)(1) {-radix hexadecimal} /testbench/cic_1/C_data(3)(0) {-radix hexadecimal}} /testbench/cic_1/C_data(3)
40 add wave -noupdate -radix hexadecimal -childformat {{/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(0) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(1) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(2) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(3) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(4) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(5) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(6) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(7) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(8) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(9) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(10) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(11) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(12) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(13) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(14) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(15) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(16) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(17) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(18) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(19) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(20) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(21) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(22) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(23) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(24) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(25) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(26) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(27) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(28) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(29) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(30) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(31) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(32) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(33) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(34) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(35) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(36) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(37) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(38) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(39) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(40) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(41) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(42) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(43) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(44) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(45) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(46) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(47) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(48) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(49) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(50) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(51) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(52) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(53) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(54) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(55) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(56) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(57) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(58) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(59) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(60) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(61) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(62) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(63) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(64) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(65) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(66) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(67) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(68) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(69) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(70) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(71) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(72) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(73) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(74) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(75) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(76) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(77) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(78) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(79) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(80) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(81) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(82) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(83) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(84) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(85) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(86) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(87) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(88) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(89) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(90) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(91) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(92) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(93) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(94) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(95) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(96) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(97) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(98) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(99) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(100) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(101) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(102) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(103) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(104) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(105) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(106) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(107) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(108) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(109) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(110) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(111) -radix hexadecimal} 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/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(45) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(46) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(47) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(48) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(49) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(50) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(51) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(52) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(53) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(54) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(55) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(56) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(57) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(58) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(59) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(60) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(61) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(62) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(63) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(64) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(65) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(66) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(67) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(68) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(69) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(70) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(71) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(72) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(73) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(74) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(75) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(76) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(77) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(78) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(79) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(80) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(81) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(82) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(83) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(84) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(85) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(86) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(87) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(88) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(89) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(90) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(91) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(92) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(93) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(94) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(95) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(96) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(97) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(98) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(99) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(100) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(101) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(102) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(103) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(104) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(105) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(106) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(107) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(108) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(109) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(110) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(111) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(112) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(113) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(114) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(115) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(116) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(117) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(118) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(119) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(120) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(121) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(122) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(123) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(124) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(125) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(126) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(127) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(128) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(129) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(130) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(131) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(132) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(133) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(134) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(135) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(136) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(137) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(138) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(139) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(140) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(141) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(142) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(143) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(144) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(145) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(146) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(147) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(148) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(149) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(150) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(151) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(152) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(153) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(154) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(155) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(156) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(157) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(158) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(159) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(160) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(161) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(162) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(163) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(164) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(165) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(166) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(167) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(168) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(169) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(170) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(171) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(172) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(173) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(174) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(175) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(176) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(177) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(178) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(179) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(180) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(181) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(182) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(183) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(184) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(185) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(186) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(187) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(188) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(189) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(190) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(191) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(192) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(193) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(194) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(195) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(196) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(197) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(198) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(199) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(200) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(201) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(202) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(203) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(204) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(205) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(206) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(207) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(208) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(209) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(210) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(211) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(212) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(213) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(214) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(215) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(216) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(217) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(218) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(219) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(220) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(221) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(222) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(223) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(224) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(225) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(226) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(227) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(228) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(229) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(230) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(231) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(232) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(233) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(234) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(235) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(236) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(237) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(238) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(239) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(240) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(241) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(242) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(243) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(244) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(245) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(246) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(247) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(248) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(249) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(250) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(251) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(252) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(253) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(254) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(255) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray
33 add wave -noupdate -group Literal -radix hexadecimal /testbench/cic_1/C_data(0)
41 add wave -noupdate -radix decimal -childformat {{/testbench/cic_lfr_r2_1/data_out_16(5) -radix hexadecimal} {/testbench/cic_lfr_r2_1/data_out_16(4) -radix hexadecimal} {/testbench/cic_lfr_r2_1/data_out_16(3) -radix hexadecimal} {/testbench/cic_lfr_r2_1/data_out_16(2) -radix hexadecimal} {/testbench/cic_lfr_r2_1/data_out_16(1) -radix hexadecimal} {/testbench/cic_lfr_r2_1/data_out_16(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_r2_1/data_out_16(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_r2_1/data_out_16(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_r2_1/data_out_16(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_r2_1/data_out_16(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_r2_1/data_out_16(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_r2_1/data_out_16(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_r2_1/data_out_16
34 add wave -noupdate -group I_REG -radix hexadecimal /testbench/cic_1/I_data(1)
42 add wave -noupdate -radix decimal -childformat {{/testbench/cic_lfr_r2_1/data_out_256(5) -radix decimal} {/testbench/cic_lfr_r2_1/data_out_256(4) -radix decimal} {/testbench/cic_lfr_r2_1/data_out_256(3) -radix decimal} {/testbench/cic_lfr_r2_1/data_out_256(2) -radix decimal} {/testbench/cic_lfr_r2_1/data_out_256(1) -radix decimal} {/testbench/cic_lfr_r2_1/data_out_256(0) -radix decimal}} -expand -subitemconfig {/testbench/cic_lfr_r2_1/data_out_256(5) {-height 15 -radix decimal} /testbench/cic_lfr_r2_1/data_out_256(4) {-height 15 -radix decimal} /testbench/cic_lfr_r2_1/data_out_256(3) {-height 15 -radix decimal} /testbench/cic_lfr_r2_1/data_out_256(2) {-height 15 -radix decimal} /testbench/cic_lfr_r2_1/data_out_256(1) {-height 15 -radix decimal} /testbench/cic_lfr_r2_1/data_out_256(0) {-height 15 -radix decimal}} /testbench/cic_lfr_r2_1/data_out_256
35 add wave -noupdate -group I_REG -expand -group I0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(0)
43 add wave -noupdate /testbench/param_r2
36 add wave -noupdate -group I_REG -expand -group I0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(3)
44 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(0)
37 add wave -noupdate -group I_REG -expand -group I0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(6)
45 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(1)
38 add wave -noupdate -group I_REG -radix hexadecimal /testbench/cic_1/I_data(2)
46 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(2)
39 add wave -noupdate -group I_REG -expand -group I1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(1)
47 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(3)
40 add wave -noupdate -group I_REG -expand -group I1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(4)
48 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(4)
41 add wave -noupdate -group I_REG -expand -group I1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(7)
49 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(5)
42 add wave -noupdate -group I_REG -radix hexadecimal /testbench/cic_1/I_data(3)
50 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(6)
43 add wave -noupdate -group I_REG -expand -group I2 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(2)
51 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(7)
44 add wave -noupdate -group I_REG -expand -group I2 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(5)
52 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(8)
45 add wave -noupdate -group I_REG -expand -group I2 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(8)
53 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(9)
46 add wave -noupdate -group OLD -divider DEBUG
54 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(10)
47 add wave -noupdate -group OLD -group CONTROL -radix hexadecimal /testbench/cic_lfr_1/cic_lfr_control_1/current_channel
55 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(11)
48 add wave -noupdate -group OLD -group CONTROL -radix hexadecimal /testbench/cic_lfr_1/cic_lfr_control_1/STATE_CIC_LFR
56 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(12)
49 add wave -noupdate -group OLD -group CONTROL -radix hexadecimal /testbench/cic_lfr_1/cic_lfr_control_1/OPERATION
57 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(13)
50 add wave -noupdate -group OLD -group CONTROL -radix hexadecimal /testbench/cic_lfr_1/cic_lfr_control_1/current_cmd
58 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(14)
51 add wave -noupdate -group OLD -group INPUT -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_in(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/data_in(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_in
59 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(15)
52 add wave -noupdate -group OLD -group INPUT -radix hexadecimal /testbench/cic_lfr_1/data_in_valid
60 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(16)
53 add wave -noupdate -group OLD -group SEL_INPUT -radix unsigned -childformat {{/testbench/cic_lfr_1/sel_sample(2) -radix unsigned} {/testbench/cic_lfr_1/sel_sample(1) -radix unsigned} {/testbench/cic_lfr_1/sel_sample(0) -radix unsigned}} -expand -subitemconfig {/testbench/cic_lfr_1/sel_sample(2) {-height 15 -radix unsigned} /testbench/cic_lfr_1/sel_sample(1) {-height 15 -radix unsigned} /testbench/cic_lfr_1/sel_sample(0) {-height 15 -radix unsigned}} /testbench/cic_lfr_1/sel_sample
61 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(17)
54 add wave -noupdate -group OLD -group SEL_INPUT -radix hexadecimal /testbench/cic_lfr_1/sample
62 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(18)
55 add wave -noupdate -group OLD -group ALU -radix unsigned -radixenum symbolic /testbench/cic_lfr_1/ALU/OP
63 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(19)
56 add wave -noupdate -group OLD -group ALU -expand -group INPUT -radix hexadecimal /testbench/cic_lfr_1/ALU/data_in_A
64 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(20)
57 add wave -noupdate -group OLD -group ALU -expand -group INPUT -radix hexadecimal /testbench/cic_lfr_1/ALU/data_in_B
65 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(21)
58 add wave -noupdate -group OLD -group ALU -expand -group INPUT /testbench/cic_lfr_1/ALU/data_in_Carry
66 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(22)
59 add wave -noupdate -group OLD -group ALU -expand -group OUTPUT /testbench/cic_lfr_1/ALU/data_out_Carry
67 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(23)
60 add wave -noupdate -group OLD -group ALU -expand -group OUTPUT -radix hexadecimal /testbench/cic_lfr_1/ALU/data_out
68 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(24)
61 add wave -noupdate -group OLD -group RAM -radix hexadecimal -childformat {{/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(0) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(1) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(2) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(3) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(4) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(5) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(6) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(7) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(8) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(9) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(10) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(11) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(12) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(13) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(14) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(15) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(16) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(17) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(18) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(19) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(20) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(21) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(22) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(23) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(24) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(25) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(26) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(27) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(28) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(29) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(30) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(31) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(32) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(33) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(34) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(35) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(36) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(37) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(38) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(39) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(40) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(41) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(42) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(43) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(44) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(45) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(46) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(47) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(48) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(49) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(50) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(51) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(52) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(53) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(54) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(55) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(56) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(57) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(58) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(59) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(60) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(61) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(62) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(63) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(64) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(65) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(66) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(67) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(68) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(69) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(70) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(71) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(72) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(73) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(74) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(75) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(76) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(77) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(78) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(79) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(80) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(81) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(82) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(83) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(84) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(85) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(86) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(87) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(88) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(89) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(90) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(91) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(92) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(93) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(94) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(95) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(96) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(97) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(98) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(99) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(100) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(101) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(102) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(103) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(104) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(105) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(106) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(107) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(108) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(109) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(110) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(111) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(112) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(113) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(114) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(115) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(116) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(117) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(118) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(119) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(120) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(121) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(122) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(123) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(124) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(125) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(126) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(127) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(128) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(129) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(130) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(131) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(132) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(133) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(134) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(135) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(136) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(137) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(138) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(139) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(140) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(141) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(142) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(143) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(144) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(145) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(146) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(147) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(148) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(149) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(150) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(151) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(152) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(153) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(154) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(155) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(156) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(157) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(158) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(159) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(160) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(161) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(162) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(163) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(164) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(165) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(166) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(167) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(168) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(169) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(170) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(171) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(172) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(173) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(174) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(175) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(176) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(177) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(178) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(179) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(180) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(181) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(182) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(183) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(184) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(185) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(186) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(187) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(188) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(189) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(190) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(191) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(192) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(193) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(194) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(195) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(196) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(197) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(198) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(199) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(200) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(201) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(202) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(203) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(204) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(205) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(206) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(207) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(208) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(209) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(210) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(211) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(212) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(213) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(214) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(215) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(216) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(217) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(218) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(219) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(220) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(221) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(222) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(223) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(224) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(225) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(226) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(227) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(228) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(229) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(230) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(231) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(232) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(233) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(234) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(235) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(236) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(237) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(238) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(239) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(240) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(241) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(242) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(243) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(244) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(245) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(246) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(247) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(248) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(249) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(250) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(251) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(252) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(253) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(254) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(255) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(0) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(1) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(2) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(3) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(4) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(5) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(6) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(7) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(8) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(9) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(10) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(11) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(12) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(13) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(14) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(15) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(16) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(17) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(18) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(19) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(20) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(21) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(22) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(23) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(24) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(25) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(26) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(27) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(28) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(29) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(30) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(31) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(32) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(33) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(34) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(35) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(36) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(37) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(38) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(39) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(40) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(41) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(42) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(43) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(44) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(45) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(46) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(47) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(48) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(49) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(50) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(51) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(52) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(53) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(54) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(55) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(56) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(57) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(58) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(59) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(60) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(61) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(62) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(63) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(64) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(65) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(66) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(67) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(68) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(69) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(70) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(71) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(72) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(73) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(74) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(75) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(76) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(77) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(78) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(79) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(80) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(81) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(82) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(83) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(84) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(85) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(86) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(87) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(88) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(89) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(90) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(91) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(92) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(93) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(94) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(95) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(96) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(97) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(98) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(99) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(100) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(101) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(102) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(103) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(104) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(105) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(106) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(107) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(108) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(109) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(110) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(111) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(112) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(113) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(114) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(115) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(116) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(117) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(118) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(119) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(120) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(121) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(122) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(123) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(124) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(125) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(126) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(127) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(128) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(129) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(130) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(131) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(132) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(133) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(134) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(135) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(136) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(137) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(138) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(139) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(140) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(141) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(142) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(143) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(144) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(145) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(146) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(147) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(148) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(149) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(150) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(151) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(152) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(153) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(154) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(155) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(156) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(157) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(158) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(159) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(160) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(161) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(162) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(163) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(164) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(165) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(166) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(167) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(168) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(169) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(170) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(171) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(172) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(173) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(174) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(175) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(176) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(177) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(178) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(179) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(180) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(181) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(182) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(183) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(184) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(185) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(186) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(187) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(188) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(189) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(190) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(191) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(192) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(193) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(194) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(195) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(196) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(197) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(198) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(199) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(200) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(201) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(202) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(203) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(204) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(205) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(206) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(207) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(208) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(209) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(210) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(211) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(212) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(213) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(214) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(215) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(216) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(217) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(218) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(219) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(220) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(221) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(222) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(223) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(224) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(225) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(226) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(227) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(228) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(229) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(230) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(231) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(232) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(233) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(234) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(235) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(236) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(237) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(238) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(239) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(240) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(241) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(242) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(243) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(244) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(245) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(246) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(247) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(248) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(249) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(250) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(251) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(252) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(253) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(254) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(255) {-radix hexadecimal}} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray
69 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(25)
62 add wave -noupdate -group OLD -group RAM -expand -group WRITE /testbench/cic_lfr_1/memCEL/RAMblk/WEN
70 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(26)
63 add wave -noupdate -group OLD -group RAM -expand -group WRITE -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/WD
71 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(27)
64 add wave -noupdate -group OLD -group RAM -expand -group WRITE -radix unsigned /testbench/cic_lfr_1/memCEL/RAMblk/WADDR
72 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(28)
65 add wave -noupdate -group OLD -group RAM -expand -group READ /testbench/cic_lfr_1/memCEL/RAMblk/REN
73 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(29)
66 add wave -noupdate -group OLD -group RAM -expand -group READ -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RD
74 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(30)
67 add wave -noupdate -group OLD -group RAM -expand -group READ -radix unsigned /testbench/cic_lfr_1/memCEL/RAMblk/RADDR
75 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(31)
68 add wave -noupdate -group OLD /testbench/cic_lfr_1/cic_lfr_address_gen_1/addr_base
76 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(32)
69 add wave -noupdate -group OLD /testbench/cic_lfr_1/cic_lfr_address_gen_1/addr_init
77 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(33)
70 add wave -noupdate -group OLD /testbench/cic_lfr_1/cic_lfr_address_gen_1/addr_add_1
78 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(34)
71 add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/cic_lfr_address_gen_1/addr
79 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(35)
72 add wave -noupdate -group OLD -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/sample_out_reg16(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg16
80 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(36)
73 add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/sample_out_reg256
81 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(37)
74 add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/data_out_16_valid
82 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(38)
75 add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/data_out_16
83 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(39)
76 add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/data_out_256
84 add wave -noupdate -group lane0 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(40)
77 add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/data_out_256_valid
85 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(40)
78 add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/sample_out_reg256_s
86 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(41)
79 add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/sample_out_reg16_s
87 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(42)
80 add wave -noupdate -expand -group CIC_LFR -group CONTROL /testbench/cic_lfr_1/cic_lfr_control_1/STATE_CIC_LFR
88 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(43)
81 add wave -noupdate -expand -group CIC_LFR -group CONTROL /testbench/cic_lfr_1/cic_lfr_control_1/current_channel
89 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(44)
82 add wave -noupdate -expand -group CIC_LFR -group CONTROL /testbench/cic_lfr_1/cic_lfr_control_1/current_cmd
90 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(45)
83 add wave -noupdate -expand -group CIC_LFR -group SEL_SAMPLE /testbench/cic_lfr_1/sel_sample
91 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(46)
84 add wave -noupdate -expand -group CIC_LFR -group SEL_SAMPLE -radix hexadecimal /testbench/cic_lfr_1/sample
92 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(47)
85 add wave -noupdate -expand -group CIC_LFR -group SEL_A /testbench/cic_lfr_1/sel_A
93 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(48)
86 add wave -noupdate -expand -group CIC_LFR -group SEL_A -radix hexadecimal /testbench/cic_lfr_1/data_A
94 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(49)
87 add wave -noupdate -expand -group CIC_LFR -group ALU -radix hexadecimal /testbench/cic_lfr_1/ALU/OP
95 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(50)
88 add wave -noupdate -expand -group CIC_LFR -group ALU -expand -group IN -radix hexadecimal /testbench/cic_lfr_1/ALU/data_in_A
96 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(51)
89 add wave -noupdate -expand -group CIC_LFR -group ALU -expand -group IN -radix hexadecimal /testbench/cic_lfr_1/ALU/data_in_B
97 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(52)
90 add wave -noupdate -expand -group CIC_LFR -group ALU -expand -group IN -radix hexadecimal /testbench/cic_lfr_1/ALU/data_in_Carry
98 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(53)
91 add wave -noupdate -expand -group CIC_LFR -group ALU /testbench/cic_lfr_1/CARRY_POP
99 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(54)
92 add wave -noupdate -expand -group CIC_LFR -group ALU -expand -group OUT -radix hexadecimal /testbench/cic_lfr_1/ALU/data_out
100 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(55)
93 add wave -noupdate -expand -group CIC_LFR -group ALU -expand -group OUT -radix hexadecimal /testbench/cic_lfr_1/ALU/data_out_Carry
101 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(56)
94 add wave -noupdate -expand -group CIC_LFR /testbench/cic_lfr_1/CARRY_PUSH
102 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(57)
95 add wave -noupdate -expand -group CIC_LFR /testbench/cic_lfr_1/carry_reg
103 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(58)
96 add wave -noupdate -expand -group CIC_LFR -group RAM -expand -group READ -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/REN
104 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(59)
97 add wave -noupdate -expand -group CIC_LFR -group RAM -expand -group READ -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RD
105 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(60)
98 add wave -noupdate -expand -group CIC_LFR -group RAM -expand -group READ -radix decimal /testbench/cic_lfr_1/memCEL/RAMblk/RADDR
106 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(61)
99 add wave -noupdate -expand -group CIC_LFR -group RAM -expand -group WRITE -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/WEN
107 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(62)
100 add wave -noupdate -expand -group CIC_LFR -group RAM -expand -group WRITE -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/WD
108 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(63)
101 add wave -noupdate -expand -group CIC_LFR -group RAM -expand -group WRITE -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/WADDR
109 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(64)
102 add wave -noupdate -group CARRY -radix hexadecimal /testbench/cic_lfr_1/ALU/data_out_Carry
110 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(65)
103 add wave -noupdate -group CARRY /testbench/cic_lfr_1/CARRY_PUSH
111 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(66)
104 add wave -noupdate -group CARRY /testbench/cic_lfr_1/carry_reg
112 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(67)
105 add wave -noupdate -group CARRY -radix hexadecimal /testbench/cic_lfr_1/ALU/data_in_Carry
113 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(68)
106 add wave -noupdate -group CARRY /testbench/cic_lfr_1/CARRY_POP
114 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(69)
107 add wave -noupdate -radix hexadecimal /testbench/cic_lfr_1/data_in
115 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(70)
108 add wave -noupdate -radix hexadecimal /testbench/cic_lfr_1/data_in_valid
116 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(71)
109 add wave -noupdate -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/data_out_16(5) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(4) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(3) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(2) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(1) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0) {-radix hexadecimal}} /testbench/cic_lfr_1/data_out_16
117 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(72)
110 add wave -noupdate -radix hexadecimal /testbench/cic_lfr_1/data_out_16_valid
118 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(73)
111 add wave -noupdate -radix hexadecimal /testbench/cic_lfr_1/data_out_256
119 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(74)
112 add wave -noupdate -radix hexadecimal /testbench/cic_lfr_1/data_out_256_valid
120 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(75)
121 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(76)
122 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(77)
123 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(78)
124 add wave -noupdate -group lane1 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(79)
125 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(80)
126 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(81)
127 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(82)
128 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(83)
129 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(84)
130 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(85)
131 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(86)
132 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(87)
133 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(88)
134 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(89)
135 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(90)
136 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(91)
137 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(92)
138 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(93)
139 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(94)
140 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(95)
141 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(96)
142 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(97)
143 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(98)
144 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(99)
145 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(100)
146 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(101)
147 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(102)
148 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(103)
149 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(104)
150 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(105)
151 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(106)
152 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(107)
153 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(108)
154 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(109)
155 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(110)
156 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(111)
157 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(112)
158 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(113)
159 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(114)
160 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(115)
161 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(116)
162 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(117)
163 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(118)
164 add wave -noupdate -group lane2 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(119)
165 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(120)
166 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(121)
167 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(122)
168 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(123)
169 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(124)
170 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(125)
171 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(126)
172 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(127)
173 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(128)
174 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(129)
175 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(130)
176 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(131)
177 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(132)
178 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(133)
179 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(134)
180 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(135)
181 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(136)
182 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(137)
183 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(138)
184 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(139)
185 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(140)
186 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(141)
187 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(142)
188 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(143)
189 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(144)
190 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(145)
191 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(146)
192 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(147)
193 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(148)
194 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(149)
195 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(150)
196 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(151)
197 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(152)
198 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(153)
199 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(154)
200 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(155)
201 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(156)
202 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(157)
203 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(158)
204 add wave -noupdate -group lane3 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(159)
205 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(160)
206 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(161)
207 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(162)
208 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(163)
209 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(164)
210 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(165)
211 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(166)
212 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(167)
213 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(168)
214 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(169)
215 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(170)
216 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(171)
217 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(172)
218 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(173)
219 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(174)
220 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(175)
221 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(176)
222 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(177)
223 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(178)
224 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(179)
225 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(180)
226 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(181)
227 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(182)
228 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(183)
229 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(184)
230 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(185)
231 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(186)
232 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(187)
233 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(188)
234 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(189)
235 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(190)
236 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(191)
237 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(192)
238 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(193)
239 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(194)
240 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(195)
241 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(196)
242 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(197)
243 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(198)
244 add wave -noupdate -group lane4 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(199)
245 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(200)
246 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(201)
247 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(202)
248 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(203)
249 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(204)
250 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(205)
251 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(206)
252 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(207)
253 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(208)
254 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(209)
255 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(210)
256 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(211)
257 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(212)
258 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(213)
259 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(214)
260 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(215)
261 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(216)
262 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(217)
263 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(218)
264 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(219)
265 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(220)
266 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(221)
267 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(222)
268 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(223)
269 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(224)
270 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(225)
271 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(226)
272 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(227)
273 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(228)
274 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(229)
275 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(230)
276 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(231)
277 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(232)
278 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(233)
279 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(234)
280 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(235)
281 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(236)
282 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(237)
283 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(238)
284 add wave -noupdate -group lane5 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(239)
285 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(240)
286 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(241)
287 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(242)
288 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(243)
289 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(244)
290 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(245)
291 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(246)
292 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(247)
293 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(248)
294 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(249)
295 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(250)
296 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(251)
297 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(252)
298 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(253)
299 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(254)
300 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(255)
301 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(256)
302 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(257)
303 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(258)
304 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(259)
305 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(260)
306 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(261)
307 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(262)
308 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(263)
309 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(264)
310 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(265)
311 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(266)
312 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(267)
313 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(268)
314 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(269)
315 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(270)
316 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(271)
317 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(272)
318 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(273)
319 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(274)
320 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(275)
321 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(276)
322 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(277)
323 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(278)
324 add wave -noupdate -group lane6 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(279)
325 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(280)
326 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(281)
327 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(282)
328 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(283)
329 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(284)
330 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(285)
331 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(286)
332 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(287)
333 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(288)
334 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(289)
335 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(290)
336 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(291)
337 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(292)
338 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(293)
339 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(294)
340 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(295)
341 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(296)
342 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(297)
343 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(298)
344 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(299)
345 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(300)
346 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(301)
347 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(302)
348 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(303)
349 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(304)
350 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(305)
351 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(306)
352 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(307)
353 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(308)
354 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(309)
355 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(310)
356 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(311)
357 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(312)
358 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(313)
359 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(314)
360 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(315)
361 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(316)
362 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(317)
363 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(318)
364 add wave -noupdate -group lane7 -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray(319)
365 add wave -noupdate -radix hexadecimal /testbench/cic_lfr_r2_1/memCEL/RAMblk/RAMarray
366 add wave -noupdate -radix hexadecimal /testbench/cic_lfr_r2_1/data_out
367 add wave -noupdate /testbench/cic_lfr_r2_1/data_out_16_valid_s
368 add wave -noupdate /testbench/cic_lfr_r2_1/data_out_16_valid_s1
369 add wave -noupdate /testbench/cic_lfr_r2_1/data_out_16_valid_s2
370 add wave -noupdate -radix hexadecimal -childformat {{/testbench/cic_lfr_r2_1/sample_out_reg16(15) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(14) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(13) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(12) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(11) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(10) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(9) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(8) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(7) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(6) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(5) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(4) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(3) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(2) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(1) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_out_reg16(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_r2_1/sample_out_reg16(15) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(14) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(13) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(12) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(11) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(10) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(9) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(8) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(7) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(6) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(5) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(4) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(3) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(2) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(1) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_out_reg16(0) {-radix hexadecimal}} /testbench/cic_lfr_r2_1/sample_out_reg16
371 add wave -noupdate -radix hexadecimal -childformat {{/testbench/cic_lfr_r2_1/sample_valid_reg16(16) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(15) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(14) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(13) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(12) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(11) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(10) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(9) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(8) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(7) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(6) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(5) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(4) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(3) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(2) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(1) -radix hexadecimal} {/testbench/cic_lfr_r2_1/sample_valid_reg16(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_r2_1/sample_valid_reg16(16) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(15) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(14) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(13) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(12) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(11) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(10) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(9) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(8) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(7) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(6) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(5) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(4) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(3) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(2) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(1) {-radix hexadecimal} /testbench/cic_lfr_r2_1/sample_valid_reg16(0) {-radix hexadecimal}} /testbench/cic_lfr_r2_1/sample_valid_reg16
113 TreeUpdate [SetDefaultTree]
372 TreeUpdate [SetDefaultTree]
114 WaveRestoreCursors {{Cursor 1} {6254226873 ps} 0} {{Cursor 2} {10074245984 ps} 0} {{Cursor 3} {36151600 ps} 0}
373 WaveRestoreCursors {{Cursor 1} {29237145000 ps} 0} {{Cursor 2} {514701877948 ps} 0} {{Cursor 3} {392261637 ps} 0}
115 quietly wave cursor active 1
374 quietly wave cursor active 1
116 configure wave -namecolwidth 377
375 configure wave -namecolwidth 353
117 configure wave -valuecolwidth 188
376 configure wave -valuecolwidth 188
118 configure wave -justifyvalue left
377 configure wave -justifyvalue left
119 configure wave -signalnamewidth 0
378 configure wave -signalnamewidth 0
@@ -127,4 +386,4 configure wave -griddelta 40
127 configure wave -timeline 0
386 configure wave -timeline 0
128 configure wave -timelineunits ns
387 configure wave -timelineunits ns
129 update
388 update
130 WaveRestoreZoom {0 ps} {15750047250 ps}
389 WaveRestoreZoom {29232867077 ps} {29241429253 ps}
Show file before | Show file after | Hide comments
@@ -211,16 +211,18 BEGIN
211 END GENERATE all_channel;
211 END GENERATE all_channel;
212 addr_base_sel <= base_addr_INT(to_integer(UNSIGNED(OPERATION(2 DOWNTO 0))));
212 addr_base_sel <= base_addr_INT(to_integer(UNSIGNED(OPERATION(2 DOWNTO 0))));
213
213
214 cic_lfr_address_gen_1: cic_lfr_address_gen
214 cic_lfr_address_gen_1: cic_lfr_address_gen
215 PORT MAP (
215 GENERIC MAP (
216 clk => clk,
216 ADDR_SIZE => 8 )
217 rstn => rstn,
217 PORT MAP (
218 run => run,
218 clk => clk,
219
219 rstn => rstn,
220 addr_base => addr_base_sel,
220 run => run,
221 addr_init => OPERATION(8),
221
222 addr_add_1 => OPERATION(9),
222 addr_base => addr_base_sel,
223 addr => addr_gen);
223 addr_init => OPERATION(8),
224 addr_add_1 => OPERATION(9),
225 addr => addr_gen);
224
226
225
227
226 addr_read <= addr_gen WHEN OPERATION(12 DOWNTO 10) = "000" ELSE
228 addr_read <= addr_gen WHEN OPERATION(12 DOWNTO 10) = "000" ELSE
Show file before | Show file after | Hide comments
@@ -23,47 +23,50
23
23
24 LIBRARY ieee;
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
25 USE ieee.std_logic_1164.ALL;
26 USE ieee.numeric_std.all;
26 USE ieee.numeric_std.ALL;
27
27
28 LIBRARY lpp;
28 LIBRARY lpp;
29 USE lpp.cic_pkg.ALL;
29 USE lpp.cic_pkg.ALL;
30 USE lpp.data_type_pkg.ALL;
30 USE lpp.data_type_pkg.ALL;
31
31
32 ENTITY cic_lfr_address_gen IS
32 ENTITY cic_lfr_address_gen IS
33 GENERIC (
34 ADDR_SIZE : INTEGER := 8
35 );
33 PORT (
36 PORT (
34 clk : IN STD_LOGIC;
37 clk : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
38 rstn : IN STD_LOGIC;
36 run : IN STD_LOGIC;
39 run : IN STD_LOGIC;
37
40
38 addr_base : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
41 addr_base : IN STD_LOGIC_VECTOR(ADDR_SIZE-1 DOWNTO 0);
39 addr_init : IN STD_LOGIC;
42 addr_init : IN STD_LOGIC;
40 addr_add_1 : IN STD_LOGIC;
43 addr_add_1 : IN STD_LOGIC;
41
44
42 addr : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
45 addr : OUT STD_LOGIC_VECTOR(ADDR_SIZE-1 DOWNTO 0)
43 );
46 );
44 END cic_lfr_address_gen;
47 END cic_lfr_address_gen;
45
48
46 ARCHITECTURE beh OF cic_lfr_address_gen IS
49 ARCHITECTURE beh OF cic_lfr_address_gen IS
47 SIGNAL address_reg_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
50 SIGNAL address_reg_s : STD_LOGIC_VECTOR(ADDR_SIZE-1 DOWNTO 0);
48 SIGNAL address_reg : STD_LOGIC_VECTOR(7 DOWNTO 0);
51 SIGNAL address_reg : STD_LOGIC_VECTOR(ADDR_SIZE-1 DOWNTO 0);
49 BEGIN
52 BEGIN
50
53
51 PROCESS (clk, rstn)
54 PROCESS (clk, rstn)
52 BEGIN -- PROCESS
55 BEGIN -- PROCESS
53 IF rstn = '0' THEN -- asynchronous reset (active low)
56 IF rstn = '0' THEN -- asynchronous reset (active low)
54 address_reg <= (OTHERS => '0');
57 address_reg <= (OTHERS => '0');
55 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
58 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
56 address_reg <= address_reg_s;
59 address_reg <= address_reg_s;
57 END IF;
60 END IF;
58 END PROCESS;
61 END PROCESS;
59
62
60 address_reg_s <= (OTHERS => '0') WHEN run = '0' ELSE
63 address_reg_s <= (OTHERS => '0') WHEN run = '0' ELSE
61 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(address_reg)) + 1,8)) WHEN addr_add_1 = '1' AND addr_init = '0' ELSE
64 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(address_reg)) + 1, ADDR_SIZE)) WHEN addr_add_1 = '1' AND addr_init = '0' ELSE
62 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base)) + 1,8)) WHEN addr_add_1 = '1' AND addr_init = '1' ELSE
65 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base)) + 1, ADDR_SIZE)) WHEN addr_add_1 = '1' AND addr_init = '1' ELSE
63 addr_base WHEN addr_add_1 = '0' AND addr_init = '1' ELSE
66 addr_base WHEN addr_add_1 = '0' AND addr_init = '1' ELSE
64 address_reg;
67 address_reg;
65
68
66 addr <= address_reg WHEN addr_init = '0' ELSE addr_base;
69 addr <= address_reg WHEN addr_init = '0' ELSE addr_base;
67
70
68 END beh;
71 END beh;
69
72
Show file before | Show file after | Hide comments
@@ -196,8 +196,10 BEGIN
196 current_channel <= 0;
196 current_channel <= 0;
197 STATE_CIC_LFR <= IDLE;
197 STATE_CIC_LFR <= IDLE;
198 ELSE
198 ELSE
199
199 current_cmd <= PROG_START_I;
200 current_cmd <= PROG_START_I;
200 current_channel <= current_channel + 1;
201 current_channel <= current_channel + 1;
202
201 END IF;
203 END IF;
202 END IF;
204 END IF;
203 ELSE
205 ELSE
Show file before | Show file after | Hide comments
@@ -107,6 +107,23 PACKAGE cic_pkg IS
107 data_out_256_valid : OUT STD_LOGIC);
107 data_out_256_valid : OUT STD_LOGIC);
108 END COMPONENT;
108 END COMPONENT;
109
109
110 COMPONENT cic_lfr_r2
111 GENERIC (
112 tech : INTEGER;
113 use_RAM_nCEL : INTEGER);
114 PORT (
115 clk : IN STD_LOGIC;
116 rstn : IN STD_LOGIC;
117 run : IN STD_LOGIC;
118 param_r2 : IN STD_LOGIC;
119 data_in : IN sample_vector(7 DOWNTO 0, 15 DOWNTO 0);
120 data_in_valid : IN STD_LOGIC;
121 data_out_16 : OUT sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
122 data_out_16_valid : OUT STD_LOGIC;
123 data_out_256 : OUT sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
124 data_out_256_valid : OUT STD_LOGIC);
125 END COMPONENT;
126
110 COMPONENT cic_lfr_control
127 COMPONENT cic_lfr_control
111 PORT (
128 PORT (
112 clk : IN STD_LOGIC;
129 clk : IN STD_LOGIC;
@@ -118,6 +135,17 PACKAGE cic_pkg IS
118 OPERATION : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
135 OPERATION : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
119 END COMPONENT;
136 END COMPONENT;
120
137
138 COMPONENT cic_lfr_control_r2
139 PORT (
140 clk : IN STD_LOGIC;
141 rstn : IN STD_LOGIC;
142 run : IN STD_LOGIC;
143 data_in_valid : IN STD_LOGIC;
144 data_out_16_valid : OUT STD_LOGIC;
145 data_out_256_valid : OUT STD_LOGIC;
146 OPERATION : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
147 END COMPONENT;
148
121 COMPONENT cic_lfr_add_sub
149 COMPONENT cic_lfr_add_sub
122 PORT (
150 PORT (
123 clk : IN STD_LOGIC;
151 clk : IN STD_LOGIC;
@@ -132,14 +160,16 PACKAGE cic_pkg IS
132 END COMPONENT;
160 END COMPONENT;
133
161
134 COMPONENT cic_lfr_address_gen
162 COMPONENT cic_lfr_address_gen
163 GENERIC (
164 ADDR_SIZE : INTEGER);
135 PORT (
165 PORT (
136 clk : IN STD_LOGIC;
166 clk : IN STD_LOGIC;
137 rstn : IN STD_LOGIC;
167 rstn : IN STD_LOGIC;
138 run : IN STD_LOGIC;
168 run : IN STD_LOGIC;
139 addr_base : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
169 addr_base : IN STD_LOGIC_VECTOR(ADDR_SIZE-1 DOWNTO 0);
140 addr_init : IN STD_LOGIC;
170 addr_init : IN STD_LOGIC;
141 addr_add_1 : IN STD_LOGIC;
171 addr_add_1 : IN STD_LOGIC;
142 addr : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
172 addr : OUT STD_LOGIC_VECTOR(ADDR_SIZE-1 DOWNTO 0));
143 END COMPONENT;
173 END COMPONENT;
144
174
145
175
Show file before | Show file after | Hide comments
@@ -7,3 +7,5 cic_lfr.vhd
7 cic_lfr_control.vhd
7 cic_lfr_control.vhd
8 cic_lfr_add_sub.vhd
8 cic_lfr_add_sub.vhd
9 cic_lfr_address_gen.vhd
9 cic_lfr_address_gen.vhd
10 cic_lfr_r2.vhd
11 cic_lfr_control_r2.vhd
Show file before | Show file after | Hide comments
@@ -120,7 +120,7 ARCHITECTURE tb OF lpp_lfr_filter IS
120 -----------------------------------------------------------------------------
120 -----------------------------------------------------------------------------
121 -- SIGNAL sample_f0_val : STD_LOGIC;
121 -- SIGNAL sample_f0_val : STD_LOGIC;
122 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
122 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
123 SIGNAL sample_f0_s : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
123 SIGNAL sample_f0_s : sample_vector(7 DOWNTO 0, 15 DOWNTO 0);
124 --
124 --
125 -- SIGNAL sample_f1_val : STD_LOGIC;
125 -- SIGNAL sample_f1_val : STD_LOGIC;
126
126
@@ -131,13 +131,19 ARCHITECTURE tb OF lpp_lfr_filter IS
131 -- SIGNAL sample_f2_val : STD_LOGIC;
131 -- SIGNAL sample_f2_val : STD_LOGIC;
132 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
132 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
133 SIGNAL sample_f2_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
133 SIGNAL sample_f2_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
134 SIGNAL sample_f2_cic_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0);
135 SIGNAL sample_f2_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0);
134 SIGNAL sample_f2_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
136 SIGNAL sample_f2_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
135 SIGNAL sample_f2_cic_val : STD_LOGIC;
137 SIGNAL sample_f2_cic_val : STD_LOGIC;
138 SIGNAL sample_f2_filter_val : STD_LOGIC;
136
139
137 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
140 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
138 SIGNAL sample_f3_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
141 SIGNAL sample_f3_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
142 SIGNAL sample_f3_cic_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0);
143 SIGNAL sample_f3_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0);
139 SIGNAL sample_f3_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
144 SIGNAL sample_f3_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
140 SIGNAL sample_f3_cic_val : STD_LOGIC;
145 SIGNAL sample_f3_cic_val : STD_LOGIC;
146 SIGNAL sample_f3_filter_val : STD_LOGIC;
141
147
142 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
143 --SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
149 --SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
@@ -181,6 +187,33 ARCHITECTURE tb OF lpp_lfr_filter IS
181 f0_to_f1_gain);
187 f0_to_f1_gain);
182 -----------------------------------------------------------------------------
188 -----------------------------------------------------------------------------
183
189
190 -----------------------------------------------------------------------------
191 -- CONFIG FILTER IIR f2 and f3
192 -----------------------------------------------------------------------------
193 CONSTANT f2_f3_CEL_NUMBER : INTEGER := 5;
194 CONSTANT f2_f3_COEFFICIENT_SIZE : INTEGER := 10;
195 CONSTANT f2_f3_POINT_POSITION : INTEGER := 8;
196
197 CONSTANT f2_f3_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) :=
198 (
199 (1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583),
200 (1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351),
201 (1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102),
202 (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464),
203 (1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691)
204 );
205 CONSTANT f2_f3_gain : COEFF_CEL_REAL :=
206 ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0);
207
208 CONSTANT coefs_iir_cel_f2_f3 : STD_LOGIC_VECTOR((f2_f3_CEL_NUMBER*f2_f3_COEFFICIENT_SIZE*5)-1 DOWNTO 0)
209 := get_IIR_CEL_FILTER_CONFIG(
210 f2_f3_COEFFICIENT_SIZE,
211 f2_f3_POINT_POSITION,
212 f2_f3_CEL_NUMBER,
213 f2_f3_sos,
214 f2_f3_gain);
215 -----------------------------------------------------------------------------
216
184
217
185 BEGIN
218 BEGIN
186
219
@@ -388,10 +421,12 BEGIN
388 sample_f0_s(3, I) <= sample_f0(5, I); -- B1
421 sample_f0_s(3, I) <= sample_f0(5, I); -- B1
389 sample_f0_s(4, I) <= sample_f0(6, I); -- B2
422 sample_f0_s(4, I) <= sample_f0(6, I); -- B2
390 sample_f0_s(5, I) <= sample_f0(7, I); -- B3
423 sample_f0_s(5, I) <= sample_f0(7, I); -- B3
424 sample_f0_s(6, I) <= sample_f0(3, I); --
425 sample_f0_s(7, I) <= sample_f0(4, I); --
391 END GENERATE all_bit_sample_f0_s;
426 END GENERATE all_bit_sample_f0_s;
392
427
393
428
394 cic_lfr_1: cic_lfr
429 cic_lfr_1: cic_lfr_r2
395 GENERIC MAP (
430 GENERIC MAP (
396 tech => 0,
431 tech => 0,
397 use_RAM_nCEL => Mem_use)
432 use_RAM_nCEL => Mem_use)
@@ -399,6 +434,8 BEGIN
399 clk => clk,
434 clk => clk,
400 rstn => rstn,
435 rstn => rstn,
401 run => '1',
436 run => '1',
437
438 param_r2 => data_shaping_R2,
402
439
403 data_in => sample_f0_s,
440 data_in => sample_f0_s,
404 data_in_valid => sample_f0_val_s,
441 data_in_valid => sample_f0_val_s,
@@ -409,13 +446,58 BEGIN
409 data_out_256 => sample_f3_cic,
446 data_out_256 => sample_f3_cic,
410 data_out_256_valid => sample_f3_cic_val);
447 data_out_256_valid => sample_f3_cic_val);
411
448
412 -----------------------------------------------------------------------------
449
450
451 all_channel_sample_f_cic : FOR J IN 5 DOWNTO 0 GENERATE
452 all_bit_sample_f_cic : FOR I IN 15 DOWNTO 0 GENERATE
453 sample_f2_cic_filter(J,I) <= sample_f2_cic(J,I);
454 sample_f3_cic_filter(J,I) <= sample_f3_cic(J,I);
455 END GENERATE all_bit_sample_f_cic;
456 sample_f2_cic_filter(J,16) <= sample_f2_cic(J,15);
457 sample_f2_cic_filter(J,17) <= sample_f2_cic(J,15);
458
459 sample_f3_cic_filter(J,16) <= sample_f3_cic(J,15);
460 sample_f3_cic_filter(J,17) <= sample_f3_cic(J,15);
461 END GENERATE all_channel_sample_f_cic;
462
413
463
414 all_bit_sample_f2_cic : FOR I IN 15 DOWNTO 0 GENERATE
464 IIR_CEL_CTRLR_v3_1:IIR_CEL_CTRLR_v3
415 all_channel_sample_f2_cic : FOR J IN 5 DOWNTO 0 GENERATE
465 GENERIC MAP (
416 sample_f2_cic_s(J,I) <= sample_f2_cic(J,I);
466 tech => 0,
417 END GENERATE all_channel_sample_f2_cic;
467 Mem_use => Mem_use,
418 END GENERATE all_bit_sample_f2_cic;
468 Sample_SZ => 18,
469 Coef_SZ => f2_f3_COEFFICIENT_SIZE,
470 Coef_Nb => f2_f3_CEL_NUMBER*5,
471 Coef_sel_SZ => 5,
472 Cels_count => f2_f3_CEL_NUMBER,
473 ChanelsCount => 6)
474 PORT MAP (
475 rstn => rstn,
476 clk => clk,
477 virg_pos => f2_f3_POINT_POSITION,
478 coefs => coefs_iir_cel_f2_f3,
479
480 sample_in1_val => sample_f2_cic_val,
481 sample_in1 => sample_f2_cic_filter,
482
483 sample_in2_val => sample_f3_cic_val,
484 sample_in2 => sample_f3_cic_filter,
485
486 sample_out1_val => sample_f2_filter_val,
487 sample_out1 => sample_f2_filter,
488 sample_out2_val => sample_f3_filter_val,
489 sample_out2 => sample_f3_filter);
490
491
492 all_channel_sample_f_filter : FOR J IN 5 DOWNTO 0 GENERATE
493 all_bit_sample_f_filter : FOR I IN 15 DOWNTO 0 GENERATE
494 sample_f2_cic_s(J,I) <= sample_f2_filter(J,I);
495 sample_f3_cic_s(J,I) <= sample_f3_filter(J,I);
496 END GENERATE all_bit_sample_f_filter;
497 END GENERATE all_channel_sample_f_filter;
498
499
500 -----------------------------------------------------------------------------
419
501
420 Downsampling_f2 : Downsampling
502 Downsampling_f2 : Downsampling
421 GENERIC MAP (
503 GENERIC MAP (
@@ -425,7 +507,7 BEGIN
425 PORT MAP (
507 PORT MAP (
426 clk => clk,
508 clk => clk,
427 rstn => rstn,
509 rstn => rstn,
428 sample_in_val => sample_f2_cic_val ,
510 sample_in_val => sample_f2_filter_val ,
429 sample_in => sample_f2_cic_s,
511 sample_in => sample_f2_cic_s,
430 sample_out_val => sample_f2_val,
512 sample_out_val => sample_f2_val,
431 sample_out => sample_f2);
513 sample_out => sample_f2);
@@ -437,12 +519,6 BEGIN
437 END GENERATE all_bit_sample_f2;
519 END GENERATE all_bit_sample_f2;
438
520
439 -----------------------------------------------------------------------------
521 -----------------------------------------------------------------------------
440
441 all_bit_sample_f3_cic : FOR I IN 15 DOWNTO 0 GENERATE
442 all_channel_sample_f3_cic : FOR J IN 5 DOWNTO 0 GENERATE
443 sample_f3_cic_s(J,I) <= sample_f3_cic(J,I);
444 END GENERATE all_channel_sample_f3_cic;
445 END GENERATE all_bit_sample_f3_cic;
446
522
447 Downsampling_f3 : Downsampling
523 Downsampling_f3 : Downsampling
448 GENERIC MAP (
524 GENERIC MAP (
@@ -452,7 +528,7 BEGIN
452 PORT MAP (
528 PORT MAP (
453 clk => clk,
529 clk => clk,
454 rstn => rstn,
530 rstn => rstn,
455 sample_in_val => sample_f3_cic_val ,
531 sample_in_val => sample_f3_filter_val ,
456 sample_in => sample_f3_cic_s,
532 sample_in => sample_f3_cic_s,
457 sample_out_val => sample_f3_val,
533 sample_out_val => sample_f3_val,
458 sample_out => sample_f3);
534 sample_out => sample_f3);
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