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pellion -
r611:ec07182522e1 simu_with_Leon3
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@@ -34,7 +34,7 ENTITY cic_lfr_control_r2 IS
34 34 PORT (
35 35 clk : IN STD_LOGIC;
36 36 rstn : IN STD_LOGIC;
37 run : IN STD_LOGIC;
37 -- run : IN STD_LOGIC;
38 38 --
39 39 data_in_valid : IN STD_LOGIC;
40 40 data_out_16_valid : OUT STD_LOGIC;
@@ -55,7 +55,7 ARCHITECTURE beh OF cic_lfr_control_r2 I
55 55
56 56 SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
57 57
58 SIGNAL nb_data_receipt : INTEGER := 0;
58 SIGNAL nb_data_receipt : INTEGER RANGE 0 TO 255:= 0;
59 59 SIGNAL current_cmd : INTEGER := 0;
60 60 SIGNAL current_channel : INTEGER := 0;
61 61 SIGNAL sample_16_odd : STD_LOGIC;
@@ -246,4 +246,4 BEGIN
246 246 END IF;
247 247 END PROCESS;
248 248
249 END beh;
249 END beh; No newline at end of file
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@@ -280,7 +280,7 BEGIN
280 280 PORT MAP (
281 281 clk => clk,
282 282 rstn => rstn,
283 run => run,
283 -- run => run,
284 284 data_in_valid => data_in_valid,
285 285 data_out_16_valid => data_out_16_valid_s,
286 286 data_out_256_valid => data_out_256_valid_s,
@@ -390,4 +390,4 BEGIN
390 390 END GENERATE all_bits;
391 391 END GENERATE all_channel_out_v;
392 392
393 END beh; No newline at end of file
393 END beh;
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@@ -139,7 +139,7 PACKAGE cic_pkg IS
139 139 PORT (
140 140 clk : IN STD_LOGIC;
141 141 rstn : IN STD_LOGIC;
142 run : IN STD_LOGIC;
142 -- run : IN STD_LOGIC;
143 143 data_in_valid : IN STD_LOGIC;
144 144 data_out_16_valid : OUT STD_LOGIC;
145 145 data_out_256_valid : OUT STD_LOGIC;
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@@ -68,7 +68,7 ARCHITECTURE ar_IIR_CEL_CTRLR_v2_CONTROL
68 68 wait_valid_last_output_2);
69 69 SIGNAL IIR_CEL_STATE : fsmIIR_CEL_T;
70 70
71 SIGNAL alu_selected_coeff : INTEGER;
71 SIGNAL alu_selected_coeff : INTEGER RANGE 0 TO 2**Coef_sel_SZ-1;
72 72 SIGNAL Chanel_ongoing : INTEGER;
73 73 SIGNAL Cel_ongoing : INTEGER;
74 74
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@@ -44,7 +44,7 END Downsampling;
44 44
45 45 ARCHITECTURE beh OF Downsampling IS
46 46
47 SIGNAL counter : INTEGER;
47 SIGNAL counter : INTEGER RANGE 0 TO DivideParam-1;
48 48
49 49 BEGIN -- beh
50 50
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@@ -123,7 +123,7 ARCHITECTURE Behavioral OF apb_lfr_manag
123 123 SIGNAL force_reset : STD_LOGIC;
124 124 SIGNAL previous_force_reset : STD_LOGIC;
125 125 SIGNAL soft_reset : STD_LOGIC;
126 SIGNAL soft_reset_sync : STD_LOGIC;
126
127 127 -----------------------------------------------------------------------------
128 128 SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 129
@@ -521,4 +521,5 BEGIN
521 521 );
522 522
523 523 DAC_CAL_EN <= DAC_CAL_EN_s;
524
524 525 END Behavioral;
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@@ -115,5 +115,30 PACKAGE lpp_lfr_management IS
115 115 fine_time_max_value : OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
116 116 END COMPONENT;
117 117
118 COMPONENT apb_lfr_management_nocal
119 GENERIC (
120 tech : INTEGER;
121 pindex : INTEGER;
122 paddr : INTEGER;
123 pmask : INTEGER;
124 NB_SECOND_DESYNC : INTEGER);
125 PORT (
126 clk25MHz : IN STD_LOGIC;
127 resetn_25MHz : IN STD_LOGIC;
128 grspw_tick : IN STD_LOGIC;
129 apbi : IN apb_slv_in_type;
130 apbo : OUT apb_slv_out_type;
131 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
132 HK_val : IN STD_LOGIC;
133 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
134 DAC_SDO : OUT STD_LOGIC;
135 DAC_SCK : OUT STD_LOGIC;
136 DAC_SYNC : OUT STD_LOGIC;
137 DAC_CAL_EN : OUT STD_LOGIC;
138 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
139 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
140 LFR_soft_rstn : OUT STD_LOGIC);
141 END COMPONENT;
142
118 143 END lpp_lfr_management;
119 144
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@@ -1,6 +1,7
1 1 lpp_lfr_management.vhd
2 2 lpp_lfr_management_apbreg_pkg.vhd
3 3 apb_lfr_management.vhd
4 apb_lfr_management_nocal.vhd
4 5 lfr_time_management.vhd
5 6 fine_time_counter.vhd
6 7 coarse_time_counter.vhd
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@@ -30,7 +30,7 END top_ad_conv_RHF1401_withFilter;
30 30
31 31 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
32 32
33 SIGNAL cnv_cycle_counter : INTEGER;
33 SIGNAL cnv_cycle_counter : INTEGER RANGE 0 TO ncycle_cnv-1;
34 34 SIGNAL cnv_s : STD_LOGIC;
35 35 SIGNAL cnv_s_reg : STD_LOGIC;
36 36 SIGNAL cnv_sync : STD_LOGIC;
@@ -225,4 +225,3 END ar_top_ad_conv_RHF1401;
225 225
226 226
227 227
228
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@@ -19,81 +19,82
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@member.fsf.org
21 21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.STD_LOGIC_1164.ALL;
24 use IEEE.NUMERIC_STD.ALL;
22 LIBRARY IEEE;
23 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.NUMERIC_STD.ALL;
25 25
26 entity dynamic_freq_div is
27 generic(
28 PRESZ : integer range 1 to 32:=4;
29 PREMAX : integer := 16#FFFFFF#;
30 CPTSZ : integer range 1 to 32:=16
26 ENTITY dynamic_freq_div IS
27 GENERIC(
28 PRESZ : INTEGER RANGE 1 TO 32 := 4;
29 PREMAX : INTEGER := 16#FFFFFF#;
30 CPTSZ : INTEGER RANGE 1 TO 32 := 16
31 31 );
32 Port (
33 clk : in STD_LOGIC;
34 rstn : in STD_LOGIC;
35 pre : in STD_LOGIC_VECTOR(PRESZ-1 downto 0);
36 N : in STD_LOGIC_VECTOR(CPTSZ-1 downto 0);
37 Reload : in std_logic;
38 clk_out : out STD_LOGIC
32 PORT (
33 clk : IN STD_LOGIC;
34 rstn : IN STD_LOGIC;
35 pre : IN STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
36 N : IN STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
37 Reload : IN STD_LOGIC;
38 clk_out : OUT STD_LOGIC
39 39 );
40 end dynamic_freq_div;
40 END dynamic_freq_div;
41 41
42 architecture Behavioral of dynamic_freq_div is
43 constant prescaller_reg_sz : integer := 2**PRESZ;
44 constant PREMAX_max : STD_LOGIC_VECTOR(PRESZ-1 downto 0):=(others => '1');
45 signal cpt_reg : std_logic_vector(CPTSZ-1 downto 0):=(others => '0');
46 signal prescaller_reg : std_logic_vector(prescaller_reg_sz-1 downto 0);--:=(others => '0');
47 signal internal_clk : std_logic:='0';
48 signal internal_clk_reg : std_logic:='0';
49 signal clk_out_reg : std_logic:='0';
42 ARCHITECTURE Behavioral OF dynamic_freq_div IS
43 CONSTANT prescaller_reg_sz : INTEGER := 2**PRESZ;
44 CONSTANT PREMAX_max : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0) := (OTHERS => '1');
45 SIGNAL cpt_reg : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0) := (OTHERS => '0');
46 SIGNAL prescaller_reg : STD_LOGIC_VECTOR(prescaller_reg_sz-1 DOWNTO 0); --:=(others => '0');
47 SIGNAL internal_clk : STD_LOGIC := '0';
48 SIGNAL internal_clk_reg : STD_LOGIC := '0';
49 SIGNAL clk_out_reg : STD_LOGIC := '0';
50
51 BEGIN
50 52
51 begin
53 max0 : IF (UNSIGNED(PREMAX_max) < PREMAX) GENERATE
52 54
53 max0: if (UNSIGNED(PREMAX_max) < PREMAX) generate
54
55 internal_clk <= prescaller_reg(to_integer(unsigned(pre))) when (to_integer(unsigned(pre))<=UNSIGNED(PREMAX_max)) else
55 internal_clk <= prescaller_reg(to_integer(UNSIGNED(pre))) WHEN (to_integer(UNSIGNED(pre)) <= UNSIGNED(PREMAX_max)) ELSE
56 56 prescaller_reg(to_integer(UNSIGNED(PREMAX_max)));
57 end generate;
58 max1: if UNSIGNED(PREMAX_max) > PREMAX generate
59 internal_clk <= prescaller_reg(to_integer(unsigned(pre))) when (to_integer(unsigned(pre))<=PREMAX) else
57 END GENERATE;
58
59 max1 : IF UNSIGNED(PREMAX_max) > PREMAX GENERATE
60 internal_clk <= prescaller_reg(to_integer(UNSIGNED(pre))) WHEN (to_integer(UNSIGNED(pre)) <= PREMAX) ELSE
60 61 prescaller_reg(PREMAX);
61 end generate;
62 END GENERATE;
62 63
63 64
64 65
65 prescaller: process(rstn, clk)
66 begin
67 if rstn='0' then
68 prescaller_reg <= (others => '0');
69 elsif clk'event and clk = '1' then
70 prescaller_reg <= std_logic_vector(UNSIGNED(prescaller_reg) + 1);
71 end if;
72 end process;
66 prescaller : PROCESS(rstn, clk)
67 BEGIN
68 IF rstn = '0' then
69 prescaller_reg <= (OTHERS => '0');
70 ELSIF clk'EVENT AND clk = '1' THEN
71 prescaller_reg <= STD_LOGIC_VECTOR(UNSIGNED(prescaller_reg) + 1);
72 END IF;
73 END PROCESS;
73 74
74 75
75 76 clk_out <= clk_out_reg;
76 77
77 counter: process(rstn, clk)
78 begin
79 if rstn='0' then
80 cpt_reg <= (others => '0');
78 counter : PROCESS(rstn, clk)
79 BEGIN
80 IF rstn = '0' then
81 cpt_reg <= (OTHERS => '0');
81 82 internal_clk_reg <= '0';
82 83 clk_out_reg <= '0';
83 elsif clk'event and clk = '1' then
84 ELSIF clk'EVENT AND clk = '1' THEN
84 85 internal_clk_reg <= internal_clk;
85 if Reload = '1' then
86 IF Reload = '1' THEN
86 87 clk_out_reg <= '0';
87 cpt_reg <= (others => '0');
88 elsif (internal_clk = '1' and internal_clk_reg = '0') then
89 if cpt_reg = N then
90 clk_out_reg <= not clk_out_reg;
91 cpt_reg <= (others => '0');
92 else
93 cpt_reg <= std_logic_vector(UNSIGNED(cpt_reg) + 1);
94 end if;
95 end if;
96 end if;
97 end process;
88 cpt_reg <= (OTHERS => '0');
89 ELSIF (internal_clk = '1' AND internal_clk_reg = '0') THEN
90 IF cpt_reg = N THEN
91 clk_out_reg <= NOT clk_out_reg;
92 cpt_reg <= (OTHERS => '0');
93 ELSE
94 cpt_reg <= STD_LOGIC_VECTOR(UNSIGNED(cpt_reg) + 1);
95 END IF;
96 END IF;
97 END IF;
98 END PROCESS;
98 99
99 end Behavioral; No newline at end of file
100 END Behavioral;
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@@ -65,7 +65,7 ARCHITECTURE beh OF DMA_SubSystem IS
65 65 PORT (
66 66 clk : IN STD_LOGIC;
67 67 rstn : IN STD_LOGIC;
68 run : IN STD_LOGIC;
68 -- run : IN STD_LOGIC;
69 69 buffer_new : IN STD_LOGIC;
70 70 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
71 71 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
@@ -222,7 +222,7 BEGIN -- beh
222 222 PORT MAP (
223 223 clk => clk,
224 224 rstn => rstn,
225 run => run,
225 -- run => run,
226 226
227 227 buffer_new => buffer_new(I),
228 228 buffer_addr => buffer_addr(32*(I+1)-1 DOWNTO I*32),
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@@ -10,7 +10,7 ENTITY DMA_SubSystem_GestionBuffer IS
10 10 PORT (
11 11 clk : IN STD_LOGIC;
12 12 rstn : IN STD_LOGIC;
13 run : IN STD_LOGIC;
13 -- run : IN STD_LOGIC;
14 14 --
15 15 buffer_new : IN STD_LOGIC;
16 16 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
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@@ -78,14 +78,10 ARCHITECTURE Behavioral OF lpp_dma_SEND1
78 78 SIGNAL state : AHB_DMA_FSM_STATE;
79 79
80 80 SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
81 SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
82 81
83 82 SIGNAL data_window : STD_LOGIC;
84 83 SIGNAL ctrl_window : STD_LOGIC;
85 84
86 SIGNAL bus_request : STD_LOGIC;
87 SIGNAL bus_lock : STD_LOGIC;
88
89 85 SIGNAL data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
90 86
91 87 SIGNAL HREADY_pre : STD_LOGIC;
@@ -252,4 +248,4 BEGIN
252 248 -----------------------------------------------------------------------------
253 249
254 250
255 END Behavioral;
251 END Behavioral; No newline at end of file
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@@ -251,7 +251,7 PACKAGE lpp_dma_pkg IS
251 251 PORT (
252 252 clk : IN STD_LOGIC;
253 253 rstn : IN STD_LOGIC;
254 run : IN STD_LOGIC;
254 -- run : IN STD_LOGIC;
255 255 buffer_new : IN STD_LOGIC;
256 256 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
257 257 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
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@@ -46,8 +46,8 USE iap.memctrl.ALL;
46 46
47 47 ENTITY leon3_soc IS
48 48 GENERIC (
49 fabtech : INTEGER := apa3e;
50 memtech : INTEGER := apa3e;
49 fabtech : INTEGER := axcel;--apa3e;
50 memtech : INTEGER := axcel;--apa3e;
51 51 padtech : INTEGER := inferred;
52 52 clktech : INTEGER := inferred;
53 53 disas : INTEGER := 0; -- Enable disassembly to console
@@ -56,11 +56,11 ENTITY leon3_soc IS
56 56 --
57 57 clk_freq : INTEGER := 25000; --kHz
58 58 --
59 IS_RADHARD : INTEGER := 0;
59 IS_RADHARD : INTEGER := 1;
60 60 --
61 61 NB_CPU : INTEGER := 1;
62 62 ENABLE_FPU : INTEGER := 1;
63 FPU_NETLIST : INTEGER := 1;
63 FPU_NETLIST : INTEGER := 0;
64 64 ENABLE_DSU : INTEGER := 1;
65 65 ENABLE_AHB_UART : INTEGER := 1;
66 66 ENABLE_APB_UART : INTEGER := 1;
@@ -71,8 +71,8 ENTITY leon3_soc IS
71 71 NB_AHB_SLAVE : INTEGER := 1;
72 72 NB_APB_SLAVE : INTEGER := 1;
73 73 --
74 ADDRESS_SIZE : INTEGER := 20;
75 USES_IAP_MEMCTRLR : INTEGER := 0;
74 ADDRESS_SIZE : INTEGER := 19;
75 USES_IAP_MEMCTRLR : INTEGER := 1;
76 76 BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0';
77 77 SRBANKSZ : INTEGER := 8
78 78
@@ -276,7 +276,7 BEGIN
276 276 l3 : IF CFG_LEON3 = 1 GENERATE
277 277 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
278 278 leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
279 u0 : ENTITY gaisler.leon3s -- LEON3 processor
279 u0 : leon3s -- LEON3 processor
280 280 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
281 281 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
282 282 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
@@ -288,7 +288,7 BEGIN
288 288 END GENERATE leon3_non_radhard;
289 289
290 290 leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
291 cpu : ENTITY gaisler.leon3ft
291 cpu : leon3ft
292 292 GENERIC MAP (
293 293 HINDEX => i, --: integer; --CPU_HINDEX,
294 294 FABTECH => fabtech, --CFG_TECH,
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@@ -64,9 +64,6 ARCHITECTURE beh OF MS_calculation IS
64 64 SIGNAL fifo_in_ren_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
65 65
66 66
67 SIGNAL fifo_in_empty_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
68
69
70 67 BEGIN
71 68
72 69
@@ -94,7 +91,6 BEGIN
94 91 select_op1 <= select_R0(0);
95 92 select_op2 <= select_R0;
96 93 res_wen <= '1';
97 fifo_in_empty_reg <= "11";
98 94
99 95 ELSIF clk'EVENT AND clk = '1' THEN
100 96 select_ctrl <= select_ctrl_NOP;
@@ -103,7 +99,6 BEGIN
103 99 fifo_in_ren_s <= "11";
104 100 res_wen <= '1';
105 101 correlation_done <= '0';
106 fifo_in_empty_reg <= fifo_in_empty;
107 102 CASE state IS
108 103 WHEN IDLE =>
109 104 IF correlation_start = '1' THEN
@@ -259,4 +254,4 BEGIN
259 254 END PROCESS;
260 255
261 256
262 END beh;
257 END beh; No newline at end of file
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@@ -26,20 +26,20 ENTITY lpp_lfr IS
26 26 GENERIC (
27 27 Mem_use : INTEGER := use_RAM;
28 28 tech : INTEGER := inferred;
29 nb_data_by_buffer_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
31 delta_vector_size : INTEGER := 20;
29 nb_data_by_buffer_size : INTEGER := 32;
30 nb_snapshot_param_size : INTEGER := 32;
31 delta_vector_size : INTEGER := 32;
32 32 delta_vector_size_f0_2 : INTEGER := 7;
33 33
34 pindex : INTEGER := 4;
35 paddr : INTEGER := 4;
34 pindex : INTEGER := 15;
35 paddr : INTEGER := 15;
36 36 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 0;
38 pirq_wfp : INTEGER := 1;
37 pirq_ms : INTEGER := 6;
38 pirq_wfp : INTEGER := 14;
39 39
40 40 hindex : INTEGER := 2;
41 41
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"020153";
43 43
44 44 DEBUG_FORCE_DATA_DMA : INTEGER := 0
45 45
@@ -86,9 +86,6 ARCHITECTURE beh OF lpp_lfr IS
86 86 SIGNAL sample_f2_val : STD_LOGIC;
87 87 SIGNAL sample_f3_val : STD_LOGIC;
88 88 --
89 SIGNAL sample_f_val : STD_LOGIC_VECTOR(3 DOWNTO 0);
90 SIGNAL sample_f_data : STD_LOGIC_VECTOR((6*16)*4-1 DOWNTO 0);
91 --
92 89 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
93 90 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
94 91 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
@@ -599,4 +596,4 BEGIN
599 596 END GENERATE all_channel_sim;
600 597 -----------------------------------------------------------------------------
601 598
602 END beh;
599 END beh; No newline at end of file
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@@ -153,11 +153,7 ARCHITECTURE beh OF lpp_waveform IS
153 153 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 154 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 155 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 156 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 157 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
162 158 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 159 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
@@ -165,9 +161,6 ARCHITECTURE beh OF lpp_waveform IS
165 161 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 162 --
167 163 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
169 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
171 164 --
172 165 SIGNAL run : STD_LOGIC;
173 166 --
@@ -482,4 +475,4 BEGIN -- beh
482 475 END GENERATE all_channel;
483 476
484 477
485 END beh;
478 END beh; No newline at end of file
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