diff --git a/lib/lpp/dsp/cic/cic_lfr_control_r2.vhd b/lib/lpp/dsp/cic/cic_lfr_control_r2.vhd --- a/lib/lpp/dsp/cic/cic_lfr_control_r2.vhd +++ b/lib/lpp/dsp/cic/cic_lfr_control_r2.vhd @@ -34,7 +34,7 @@ ENTITY cic_lfr_control_r2 IS PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC; - run : IN STD_LOGIC; +-- run : IN STD_LOGIC; -- data_in_valid : IN STD_LOGIC; data_out_16_valid : OUT STD_LOGIC; @@ -55,7 +55,7 @@ ARCHITECTURE beh OF cic_lfr_control_r2 I SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE; - SIGNAL nb_data_receipt : INTEGER := 0; + SIGNAL nb_data_receipt : INTEGER RANGE 0 TO 255:= 0; SIGNAL current_cmd : INTEGER := 0; SIGNAL current_channel : INTEGER := 0; SIGNAL sample_16_odd : STD_LOGIC; @@ -246,4 +246,4 @@ BEGIN END IF; END PROCESS; -END beh; +END beh; \ No newline at end of file diff --git a/lib/lpp/dsp/cic/cic_lfr_r2.vhd b/lib/lpp/dsp/cic/cic_lfr_r2.vhd --- a/lib/lpp/dsp/cic/cic_lfr_r2.vhd +++ b/lib/lpp/dsp/cic/cic_lfr_r2.vhd @@ -280,7 +280,7 @@ BEGIN PORT MAP ( clk => clk, rstn => rstn, - run => run, +-- run => run, data_in_valid => data_in_valid, data_out_16_valid => data_out_16_valid_s, data_out_256_valid => data_out_256_valid_s, @@ -390,4 +390,4 @@ BEGIN END GENERATE all_bits; END GENERATE all_channel_out_v; -END beh; \ No newline at end of file +END beh; diff --git a/lib/lpp/dsp/cic/cic_pkg.vhd b/lib/lpp/dsp/cic/cic_pkg.vhd --- a/lib/lpp/dsp/cic/cic_pkg.vhd +++ b/lib/lpp/dsp/cic/cic_pkg.vhd @@ -139,7 +139,7 @@ PACKAGE cic_pkg IS PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC; - run : IN STD_LOGIC; +-- run : IN STD_LOGIC; data_in_valid : IN STD_LOGIC; data_out_16_valid : OUT STD_LOGIC; data_out_256_valid : OUT STD_LOGIC; diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd --- a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd +++ b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd @@ -68,7 +68,7 @@ ARCHITECTURE ar_IIR_CEL_CTRLR_v2_CONTROL wait_valid_last_output_2); SIGNAL IIR_CEL_STATE : fsmIIR_CEL_T; - SIGNAL alu_selected_coeff : INTEGER; + SIGNAL alu_selected_coeff : INTEGER RANGE 0 TO 2**Coef_sel_SZ-1; SIGNAL Chanel_ongoing : INTEGER; SIGNAL Cel_ongoing : INTEGER; diff --git a/lib/lpp/dsp/lpp_downsampling/Downsampling.vhd b/lib/lpp/dsp/lpp_downsampling/Downsampling.vhd --- a/lib/lpp/dsp/lpp_downsampling/Downsampling.vhd +++ b/lib/lpp/dsp/lpp_downsampling/Downsampling.vhd @@ -44,7 +44,7 @@ END Downsampling; ARCHITECTURE beh OF Downsampling IS - SIGNAL counter : INTEGER; + SIGNAL counter : INTEGER RANGE 0 TO DivideParam-1; BEGIN -- beh diff --git a/lib/lpp/lfr_management/apb_lfr_management.vhd b/lib/lpp/lfr_management/apb_lfr_management.vhd --- a/lib/lpp/lfr_management/apb_lfr_management.vhd +++ b/lib/lpp/lfr_management/apb_lfr_management.vhd @@ -123,7 +123,7 @@ ARCHITECTURE Behavioral OF apb_lfr_manag SIGNAL force_reset : STD_LOGIC; SIGNAL previous_force_reset : STD_LOGIC; SIGNAL soft_reset : STD_LOGIC; - SIGNAL soft_reset_sync : STD_LOGIC; + ----------------------------------------------------------------------------- SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0); @@ -521,4 +521,5 @@ BEGIN ); DAC_CAL_EN <= DAC_CAL_EN_s; + END Behavioral; diff --git a/lib/lpp/lfr_management/lpp_lfr_management.vhd b/lib/lpp/lfr_management/lpp_lfr_management.vhd --- a/lib/lpp/lfr_management/lpp_lfr_management.vhd +++ b/lib/lpp/lfr_management/lpp_lfr_management.vhd @@ -114,6 +114,31 @@ PACKAGE lpp_lfr_management IS fine_time_add : IN STD_LOGIC; fine_time_max_value : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)); END COMPONENT; + + COMPONENT apb_lfr_management_nocal + GENERIC ( + tech : INTEGER; + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER; + NB_SECOND_DESYNC : INTEGER); + PORT ( + clk25MHz : IN STD_LOGIC; + resetn_25MHz : IN STD_LOGIC; + grspw_tick : IN STD_LOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + HK_val : IN STD_LOGIC; + HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + DAC_SDO : OUT STD_LOGIC; + DAC_SCK : OUT STD_LOGIC; + DAC_SYNC : OUT STD_LOGIC; + DAC_CAL_EN : OUT STD_LOGIC; + coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + LFR_soft_rstn : OUT STD_LOGIC); + END COMPONENT; END lpp_lfr_management; diff --git a/lib/lpp/lfr_management/vhdlsyn.txt b/lib/lpp/lfr_management/vhdlsyn.txt --- a/lib/lpp/lfr_management/vhdlsyn.txt +++ b/lib/lpp/lfr_management/vhdlsyn.txt @@ -1,6 +1,7 @@ lpp_lfr_management.vhd lpp_lfr_management_apbreg_pkg.vhd apb_lfr_management.vhd +apb_lfr_management_nocal.vhd lfr_time_management.vhd fine_time_counter.vhd coarse_time_counter.vhd diff --git a/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd b/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd --- a/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd +++ b/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd @@ -30,7 +30,7 @@ END top_ad_conv_RHF1401_withFilter; ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS - SIGNAL cnv_cycle_counter : INTEGER; + SIGNAL cnv_cycle_counter : INTEGER RANGE 0 TO ncycle_cnv-1; SIGNAL cnv_s : STD_LOGIC; SIGNAL cnv_s_reg : STD_LOGIC; SIGNAL cnv_sync : STD_LOGIC; @@ -225,4 +225,3 @@ END ar_top_ad_conv_RHF1401; - diff --git a/lib/lpp/lpp_cna/dynamic_freq_div.vhd b/lib/lpp/lpp_cna/dynamic_freq_div.vhd --- a/lib/lpp/lpp_cna/dynamic_freq_div.vhd +++ b/lib/lpp/lpp_cna/dynamic_freq_div.vhd @@ -19,81 +19,82 @@ -- Author : Alexis Jeandet -- Mail : alexis.jeandet@member.fsf.org ------------------------------------------------------------------------------ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; -entity dynamic_freq_div is - generic( - PRESZ : integer range 1 to 32:=4; - PREMAX : integer := 16#FFFFFF#; - CPTSZ : integer range 1 to 32:=16 - ); - Port ( - clk : in STD_LOGIC; - rstn : in STD_LOGIC; - pre : in STD_LOGIC_VECTOR(PRESZ-1 downto 0); - N : in STD_LOGIC_VECTOR(CPTSZ-1 downto 0); - Reload : in std_logic; - clk_out : out STD_LOGIC - ); -end dynamic_freq_div; +ENTITY dynamic_freq_div IS + GENERIC( + PRESZ : INTEGER RANGE 1 TO 32 := 4; + PREMAX : INTEGER := 16#FFFFFF#; + CPTSZ : INTEGER RANGE 1 TO 32 := 16 + ); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + pre : IN STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0); + N : IN STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0); + Reload : IN STD_LOGIC; + clk_out : OUT STD_LOGIC + ); +END dynamic_freq_div; -architecture Behavioral of dynamic_freq_div is -constant prescaller_reg_sz : integer := 2**PRESZ; -constant PREMAX_max : STD_LOGIC_VECTOR(PRESZ-1 downto 0):=(others => '1'); -signal cpt_reg : std_logic_vector(CPTSZ-1 downto 0):=(others => '0'); -signal prescaller_reg : std_logic_vector(prescaller_reg_sz-1 downto 0);--:=(others => '0'); -signal internal_clk : std_logic:='0'; -signal internal_clk_reg : std_logic:='0'; -signal clk_out_reg : std_logic:='0'; +ARCHITECTURE Behavioral OF dynamic_freq_div IS + CONSTANT prescaller_reg_sz : INTEGER := 2**PRESZ; + CONSTANT PREMAX_max : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0) := (OTHERS => '1'); + SIGNAL cpt_reg : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL prescaller_reg : STD_LOGIC_VECTOR(prescaller_reg_sz-1 DOWNTO 0); --:=(others => '0'); + SIGNAL internal_clk : STD_LOGIC := '0'; + SIGNAL internal_clk_reg : STD_LOGIC := '0'; + SIGNAL clk_out_reg : STD_LOGIC := '0'; + +BEGIN -begin + max0 : IF (UNSIGNED(PREMAX_max) < PREMAX) GENERATE -max0: if (UNSIGNED(PREMAX_max) < PREMAX) generate - -internal_clk <= prescaller_reg(to_integer(unsigned(pre))) when (to_integer(unsigned(pre))<=UNSIGNED(PREMAX_max)) else + internal_clk <= prescaller_reg(to_integer(UNSIGNED(pre))) WHEN (to_integer(UNSIGNED(pre)) <= UNSIGNED(PREMAX_max)) ELSE prescaller_reg(to_integer(UNSIGNED(PREMAX_max))); -end generate; -max1: if UNSIGNED(PREMAX_max) > PREMAX generate -internal_clk <= prescaller_reg(to_integer(unsigned(pre))) when (to_integer(unsigned(pre))<=PREMAX) else + END GENERATE; + + max1 : IF UNSIGNED(PREMAX_max) > PREMAX GENERATE + internal_clk <= prescaller_reg(to_integer(UNSIGNED(pre))) WHEN (to_integer(UNSIGNED(pre)) <= PREMAX) ELSE prescaller_reg(PREMAX); -end generate; + END GENERATE; - -prescaller: process(rstn, clk) -begin -if rstn='0' then - prescaller_reg <= (others => '0'); -elsif clk'event and clk = '1' then - prescaller_reg <= std_logic_vector(UNSIGNED(prescaller_reg) + 1); -end if; -end process; + + prescaller : PROCESS(rstn, clk) + BEGIN + IF rstn = '0' then + prescaller_reg <= (OTHERS => '0'); + ELSIF clk'EVENT AND clk = '1' THEN + prescaller_reg <= STD_LOGIC_VECTOR(UNSIGNED(prescaller_reg) + 1); + END IF; + END PROCESS; -clk_out <= clk_out_reg; + clk_out <= clk_out_reg; -counter: process(rstn, clk) -begin -if rstn='0' then - cpt_reg <= (others => '0'); - internal_clk_reg <= '0'; - clk_out_reg <= '0'; -elsif clk'event and clk = '1' then - internal_clk_reg <= internal_clk; - if Reload = '1' then + counter : PROCESS(rstn, clk) + BEGIN + IF rstn = '0' then + cpt_reg <= (OTHERS => '0'); + internal_clk_reg <= '0'; + clk_out_reg <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN + internal_clk_reg <= internal_clk; + IF Reload = '1' THEN clk_out_reg <= '0'; - cpt_reg <= (others => '0'); - elsif (internal_clk = '1' and internal_clk_reg = '0') then - if cpt_reg = N then - clk_out_reg <= not clk_out_reg; - cpt_reg <= (others => '0'); - else - cpt_reg <= std_logic_vector(UNSIGNED(cpt_reg) + 1); - end if; - end if; -end if; -end process; + cpt_reg <= (OTHERS => '0'); + ELSIF (internal_clk = '1' AND internal_clk_reg = '0') THEN + IF cpt_reg = N THEN + clk_out_reg <= NOT clk_out_reg; + cpt_reg <= (OTHERS => '0'); + ELSE + cpt_reg <= STD_LOGIC_VECTOR(UNSIGNED(cpt_reg) + 1); + END IF; + END IF; + END IF; + END PROCESS; -end Behavioral; \ No newline at end of file +END Behavioral; diff --git a/lib/lpp/lpp_dma/DMA_SubSystem.vhd b/lib/lpp/lpp_dma/DMA_SubSystem.vhd --- a/lib/lpp/lpp_dma/DMA_SubSystem.vhd +++ b/lib/lpp/lpp_dma/DMA_SubSystem.vhd @@ -65,7 +65,7 @@ ARCHITECTURE beh OF DMA_SubSystem IS PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC; - run : IN STD_LOGIC; +-- run : IN STD_LOGIC; buffer_new : IN STD_LOGIC; buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0); buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0); @@ -222,7 +222,7 @@ BEGIN -- beh PORT MAP ( clk => clk, rstn => rstn, - run => run, +-- run => run, buffer_new => buffer_new(I), buffer_addr => buffer_addr(32*(I+1)-1 DOWNTO I*32), diff --git a/lib/lpp/lpp_dma/DMA_SubSystem_GestionBuffer.vhd b/lib/lpp/lpp_dma/DMA_SubSystem_GestionBuffer.vhd --- a/lib/lpp/lpp_dma/DMA_SubSystem_GestionBuffer.vhd +++ b/lib/lpp/lpp_dma/DMA_SubSystem_GestionBuffer.vhd @@ -10,7 +10,7 @@ ENTITY DMA_SubSystem_GestionBuffer IS PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC; - run : IN STD_LOGIC; +-- run : IN STD_LOGIC; -- buffer_new : IN STD_LOGIC; buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0); diff --git a/lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd b/lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd --- a/lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd @@ -1,255 +1,251 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr --- jean-christophe.pellion@easii-ic.com -------------------------------------------------------------------------------- --- 1.0 - initial version -------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; - -LIBRARY lpp; -USE lpp.lpp_amba.ALL; -USE lpp.apb_devices_list.ALL; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_dma_pkg.ALL; -USE lpp.general_purpose.ALL; ---USE lpp.lpp_waveform_pkg.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; - - -ENTITY lpp_dma_SEND16B_FIFO2DMA IS - GENERIC ( - hindex : INTEGER := 2; - vendorid : IN INTEGER := 0; - deviceid : IN INTEGER := 0; - version : IN INTEGER := 0 - ); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - - -- AMBA AHB Master Interface - AHB_Master_In : IN AHB_Mst_In_Type; - AHB_Master_Out : OUT AHB_Mst_Out_Type; - - -- FIFO Interface - ren : OUT STD_LOGIC; - data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - - -- Controls - send : IN STD_LOGIC; - valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE) - done : OUT STD_LOGIC; - address : IN STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END; - -ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS - - CONSTANT HConfig : AHB_Config_Type := ( - 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0), - OTHERS => (OTHERS => '0')); - - TYPE AHB_DMA_FSM_STATE IS (IDLE, s_INIT_TRANS, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA); - SIGNAL state : AHB_DMA_FSM_STATE; - - SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); - - SIGNAL data_window : STD_LOGIC; - SIGNAL ctrl_window : STD_LOGIC; - - SIGNAL bus_request : STD_LOGIC; - SIGNAL bus_lock : STD_LOGIC; - - SIGNAL data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); - - SIGNAL HREADY_pre : STD_LOGIC; - SIGNAL HREADY_falling : STD_LOGIC; - - SIGNAL inhib_ren : STD_LOGIC; - -BEGIN - - ----------------------------------------------------------------------------- - AHB_Master_Out.HCONFIG <= HConfig; - AHB_Master_Out.HSIZE <= "010"; --WORDS 32b - AHB_Master_Out.HINDEX <= hindex; - AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS - AHB_Master_Out.HIRQ <= (OTHERS => '0'); - AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16 - AHB_Master_Out.HWRITE <= '1'; - - --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE; - - --AHB_Master_Out.HBUSREQ <= bus_request; - --AHB_Master_Out.HLOCK <= data_window; - - --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE - -- '1' WHEN ctrl_window = '1' ELSE - -- '0'; - - --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE - -- '1' WHEN ctrl_window = '1' ELSE '0'; - - ----------------------------------------------------------------------------- - AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00"; - AHB_Master_Out.HWDATA <= ahbdrivedata(data) WHEN AHB_Master_In.HREADY = '1' ELSE ahbdrivedata(data_reg); - - ----------------------------------------------------------------------------- - --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY ); - --ren <= NOT beat; - ----------------------------------------------------------------------------- - - HREADY_falling <= inhib_ren WHEN AHB_Master_In.HREADY = '0' AND HREADY_pre = '1' ELSE '1'; - - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - state <= IDLE; - done <= '0'; - ren <= '1'; - address_counter_reg <= (OTHERS => '0'); - AHB_Master_Out.HTRANS <= HTRANS_IDLE; - AHB_Master_Out.HBUSREQ <= '0'; - AHB_Master_Out.HLOCK <= '0'; - - data_reg <= (OTHERS => '0'); - - HREADY_pre <= '0'; - inhib_ren <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - HREADY_pre <= AHB_Master_In.HREADY; - - IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN - data_reg <= data; - END IF; - - done <= '0'; - ren <= '1'; - inhib_ren <= '0'; - CASE state IS - WHEN IDLE => - AHB_Master_Out.HBUSREQ <= '0'; - AHB_Master_Out.HLOCK <= '0'; - AHB_Master_Out.HTRANS <= HTRANS_IDLE; - address_counter_reg <= (OTHERS => '0'); - IF send = '1' THEN - state <= s_INIT_TRANS; - END IF; - - WHEN s_INIT_TRANS => - AHB_Master_Out.HBUSREQ <= '1'; - AHB_Master_Out.HLOCK <= '1'; - AHB_Master_Out.HTRANS <= HTRANS_IDLE; - state <= s_ARBITER; - - WHEN s_ARBITER => - AHB_Master_Out.HBUSREQ <= '1'; - AHB_Master_Out.HLOCK <= '1'; - AHB_Master_Out.HTRANS <= HTRANS_IDLE; - address_counter_reg <= (OTHERS => '0'); - - IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN - AHB_Master_Out.HTRANS <= HTRANS_IDLE; - state <= s_CTRL; - END IF; - - WHEN s_CTRL => - inhib_ren <= '1'; - AHB_Master_Out.HBUSREQ <= '1'; - AHB_Master_Out.HLOCK <= '1'; - AHB_Master_Out.HTRANS <= HTRANS_NONSEQ; - IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN - --AHB_Master_Out.HTRANS <= HTRANS_SEQ; - state <= s_CTRL_DATA; - --ren <= '0'; - END IF; - - WHEN s_CTRL_DATA => - AHB_Master_Out.HBUSREQ <= '1'; - AHB_Master_Out.HLOCK <= '1'; - AHB_Master_Out.HTRANS <= HTRANS_SEQ; - IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN - address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1); - END IF; - - IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN - AHB_Master_Out.HBUSREQ <= '0'; - AHB_Master_Out.HLOCK <= '1';--'0'; - AHB_Master_Out.HTRANS <= HTRANS_IDLE; - state <= s_DATA; - END IF; - - ren <= HREADY_falling; - - --IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' AND address_counter_reg /= "1111" THEN - -- ren <= '0'; - --END IF; - - - WHEN s_DATA => - ren <= HREADY_falling; - - AHB_Master_Out.HBUSREQ <= '0'; - --AHB_Master_Out.HLOCK <= '0'; - AHB_Master_Out.HTRANS <= HTRANS_IDLE; - IF AHB_Master_In.HREADY = '1' THEN - AHB_Master_Out.HLOCK <= '0'; - state <= IDLE; - done <= '1'; - END IF; - - WHEN OTHERS => NULL; - END CASE; - END IF; - END PROCESS; - - ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0'; - data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0'; - ----------------------------------------------------------------------------- - - - --ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1'; - - ----------------------------------------------------------------------------- - --PROCESS (clk, rstn) - --BEGIN -- PROCESS - -- IF rstn = '0' THEN -- asynchronous reset (active low) - -- address_counter_reg <= (OTHERS => '0'); - -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge - -- address_counter_reg <= address_counter; - -- END IF; - --END PROCESS; - - --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE - -- address_counter_reg; - ----------------------------------------------------------------------------- - - -END Behavioral; +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +-- 1.0 - initial version +------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; + +LIBRARY lpp; +USE lpp.lpp_amba.ALL; +USE lpp.apb_devices_list.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_dma_pkg.ALL; +USE lpp.general_purpose.ALL; +--USE lpp.lpp_waveform_pkg.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + + +ENTITY lpp_dma_SEND16B_FIFO2DMA IS + GENERIC ( + hindex : INTEGER := 2; + vendorid : IN INTEGER := 0; + deviceid : IN INTEGER := 0; + version : IN INTEGER := 0 + ); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + -- AMBA AHB Master Interface + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + + -- FIFO Interface + ren : OUT STD_LOGIC; + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + -- Controls + send : IN STD_LOGIC; + valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE) + done : OUT STD_LOGIC; + address : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END; + +ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS + + CONSTANT HConfig : AHB_Config_Type := ( + 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0), + OTHERS => (OTHERS => '0')); + + TYPE AHB_DMA_FSM_STATE IS (IDLE, s_INIT_TRANS, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA); + SIGNAL state : AHB_DMA_FSM_STATE; + + SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + + SIGNAL data_window : STD_LOGIC; + SIGNAL ctrl_window : STD_LOGIC; + + SIGNAL data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL HREADY_pre : STD_LOGIC; + SIGNAL HREADY_falling : STD_LOGIC; + + SIGNAL inhib_ren : STD_LOGIC; + +BEGIN + + ----------------------------------------------------------------------------- + AHB_Master_Out.HCONFIG <= HConfig; + AHB_Master_Out.HSIZE <= "010"; --WORDS 32b + AHB_Master_Out.HINDEX <= hindex; + AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS + AHB_Master_Out.HIRQ <= (OTHERS => '0'); + AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16 + AHB_Master_Out.HWRITE <= '1'; + + --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE; + + --AHB_Master_Out.HBUSREQ <= bus_request; + --AHB_Master_Out.HLOCK <= data_window; + + --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE + -- '1' WHEN ctrl_window = '1' ELSE + -- '0'; + + --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE + -- '1' WHEN ctrl_window = '1' ELSE '0'; + + ----------------------------------------------------------------------------- + AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00"; + AHB_Master_Out.HWDATA <= ahbdrivedata(data) WHEN AHB_Master_In.HREADY = '1' ELSE ahbdrivedata(data_reg); + + ----------------------------------------------------------------------------- + --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY ); + --ren <= NOT beat; + ----------------------------------------------------------------------------- + + HREADY_falling <= inhib_ren WHEN AHB_Master_In.HREADY = '0' AND HREADY_pre = '1' ELSE '1'; + + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + state <= IDLE; + done <= '0'; + ren <= '1'; + address_counter_reg <= (OTHERS => '0'); + AHB_Master_Out.HTRANS <= HTRANS_IDLE; + AHB_Master_Out.HBUSREQ <= '0'; + AHB_Master_Out.HLOCK <= '0'; + + data_reg <= (OTHERS => '0'); + + HREADY_pre <= '0'; + inhib_ren <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + HREADY_pre <= AHB_Master_In.HREADY; + + IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN + data_reg <= data; + END IF; + + done <= '0'; + ren <= '1'; + inhib_ren <= '0'; + CASE state IS + WHEN IDLE => + AHB_Master_Out.HBUSREQ <= '0'; + AHB_Master_Out.HLOCK <= '0'; + AHB_Master_Out.HTRANS <= HTRANS_IDLE; + address_counter_reg <= (OTHERS => '0'); + IF send = '1' THEN + state <= s_INIT_TRANS; + END IF; + + WHEN s_INIT_TRANS => + AHB_Master_Out.HBUSREQ <= '1'; + AHB_Master_Out.HLOCK <= '1'; + AHB_Master_Out.HTRANS <= HTRANS_IDLE; + state <= s_ARBITER; + + WHEN s_ARBITER => + AHB_Master_Out.HBUSREQ <= '1'; + AHB_Master_Out.HLOCK <= '1'; + AHB_Master_Out.HTRANS <= HTRANS_IDLE; + address_counter_reg <= (OTHERS => '0'); + + IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN + AHB_Master_Out.HTRANS <= HTRANS_IDLE; + state <= s_CTRL; + END IF; + + WHEN s_CTRL => + inhib_ren <= '1'; + AHB_Master_Out.HBUSREQ <= '1'; + AHB_Master_Out.HLOCK <= '1'; + AHB_Master_Out.HTRANS <= HTRANS_NONSEQ; + IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN + --AHB_Master_Out.HTRANS <= HTRANS_SEQ; + state <= s_CTRL_DATA; + --ren <= '0'; + END IF; + + WHEN s_CTRL_DATA => + AHB_Master_Out.HBUSREQ <= '1'; + AHB_Master_Out.HLOCK <= '1'; + AHB_Master_Out.HTRANS <= HTRANS_SEQ; + IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN + address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1); + END IF; + + IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN + AHB_Master_Out.HBUSREQ <= '0'; + AHB_Master_Out.HLOCK <= '1';--'0'; + AHB_Master_Out.HTRANS <= HTRANS_IDLE; + state <= s_DATA; + END IF; + + ren <= HREADY_falling; + + --IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' AND address_counter_reg /= "1111" THEN + -- ren <= '0'; + --END IF; + + + WHEN s_DATA => + ren <= HREADY_falling; + + AHB_Master_Out.HBUSREQ <= '0'; + --AHB_Master_Out.HLOCK <= '0'; + AHB_Master_Out.HTRANS <= HTRANS_IDLE; + IF AHB_Master_In.HREADY = '1' THEN + AHB_Master_Out.HLOCK <= '0'; + state <= IDLE; + done <= '1'; + END IF; + + WHEN OTHERS => NULL; + END CASE; + END IF; + END PROCESS; + + ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0'; + data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0'; + ----------------------------------------------------------------------------- + + + --ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1'; + + ----------------------------------------------------------------------------- + --PROCESS (clk, rstn) + --BEGIN -- PROCESS + -- IF rstn = '0' THEN -- asynchronous reset (active low) + -- address_counter_reg <= (OTHERS => '0'); + -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge + -- address_counter_reg <= address_counter; + -- END IF; + --END PROCESS; + + --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE + -- address_counter_reg; + ----------------------------------------------------------------------------- + + +END Behavioral; \ No newline at end of file diff --git a/lib/lpp/lpp_dma/lpp_dma_pkg.vhd b/lib/lpp/lpp_dma/lpp_dma_pkg.vhd --- a/lib/lpp/lpp_dma/lpp_dma_pkg.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_pkg.vhd @@ -251,7 +251,7 @@ PACKAGE lpp_dma_pkg IS PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC; - run : IN STD_LOGIC; +-- run : IN STD_LOGIC; buffer_new : IN STD_LOGIC; buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0); buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0); diff --git a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd --- a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd +++ b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd @@ -46,8 +46,8 @@ USE iap.memctrl.ALL; ENTITY leon3_soc IS GENERIC ( - fabtech : INTEGER := apa3e; - memtech : INTEGER := apa3e; + fabtech : INTEGER := axcel;--apa3e; + memtech : INTEGER := axcel;--apa3e; padtech : INTEGER := inferred; clktech : INTEGER := inferred; disas : INTEGER := 0; -- Enable disassembly to console @@ -56,11 +56,11 @@ ENTITY leon3_soc IS -- clk_freq : INTEGER := 25000; --kHz -- - IS_RADHARD : INTEGER := 0; + IS_RADHARD : INTEGER := 1; -- NB_CPU : INTEGER := 1; ENABLE_FPU : INTEGER := 1; - FPU_NETLIST : INTEGER := 1; + FPU_NETLIST : INTEGER := 0; ENABLE_DSU : INTEGER := 1; ENABLE_AHB_UART : INTEGER := 1; ENABLE_APB_UART : INTEGER := 1; @@ -71,8 +71,8 @@ ENTITY leon3_soc IS NB_AHB_SLAVE : INTEGER := 1; NB_APB_SLAVE : INTEGER := 1; -- - ADDRESS_SIZE : INTEGER := 20; - USES_IAP_MEMCTRLR : INTEGER := 0; + ADDRESS_SIZE : INTEGER := 19; + USES_IAP_MEMCTRLR : INTEGER := 1; BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0'; SRBANKSZ : INTEGER := 8 @@ -276,7 +276,7 @@ BEGIN l3 : IF CFG_LEON3 = 1 GENERATE cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE leon3_non_radhard : IF IS_RADHARD = 0 GENERATE - u0 : ENTITY gaisler.leon3s -- LEON3 processor + u0 : leon3s -- LEON3 processor GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, @@ -288,7 +288,7 @@ BEGIN END GENERATE leon3_non_radhard; leon3_radhard_i : IF IS_RADHARD = 1 GENERATE - cpu : ENTITY gaisler.leon3ft + cpu : leon3ft GENERIC MAP ( HINDEX => i, --: integer; --CPU_HINDEX, FABTECH => fabtech, --CFG_TECH, diff --git a/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd b/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd --- a/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd +++ b/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd @@ -63,9 +63,6 @@ ARCHITECTURE beh OF MS_calculation IS SIGNAL fifo_in_ren_s : STD_LOGIC_VECTOR(1 DOWNTO 0); - - SIGNAL fifo_in_empty_reg : STD_LOGIC_VECTOR(1 DOWNTO 0); - BEGIN @@ -94,7 +91,6 @@ BEGIN select_op1 <= select_R0(0); select_op2 <= select_R0; res_wen <= '1'; - fifo_in_empty_reg <= "11"; ELSIF clk'EVENT AND clk = '1' THEN select_ctrl <= select_ctrl_NOP; @@ -103,7 +99,6 @@ BEGIN fifo_in_ren_s <= "11"; res_wen <= '1'; correlation_done <= '0'; - fifo_in_empty_reg <= fifo_in_empty; CASE state IS WHEN IDLE => IF correlation_start = '1' THEN @@ -259,4 +254,4 @@ BEGIN END PROCESS; -END beh; +END beh; \ No newline at end of file diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -26,20 +26,20 @@ ENTITY lpp_lfr IS GENERIC ( Mem_use : INTEGER := use_RAM; tech : INTEGER := inferred; - nb_data_by_buffer_size : INTEGER := 11; - nb_snapshot_param_size : INTEGER := 11; - delta_vector_size : INTEGER := 20; + nb_data_by_buffer_size : INTEGER := 32; + nb_snapshot_param_size : INTEGER := 32; + delta_vector_size : INTEGER := 32; delta_vector_size_f0_2 : INTEGER := 7; - pindex : INTEGER := 4; - paddr : INTEGER := 4; + pindex : INTEGER := 15; + paddr : INTEGER := 15; pmask : INTEGER := 16#fff#; - pirq_ms : INTEGER := 0; - pirq_wfp : INTEGER := 1; + pirq_ms : INTEGER := 6; + pirq_wfp : INTEGER := 14; hindex : INTEGER := 2; - top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0'); + top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"020153"; DEBUG_FORCE_DATA_DMA : INTEGER := 0 @@ -86,9 +86,6 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL sample_f2_val : STD_LOGIC; SIGNAL sample_f3_val : STD_LOGIC; -- - SIGNAL sample_f_val : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL sample_f_data : STD_LOGIC_VECTOR((6*16)*4-1 DOWNTO 0); - -- SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); @@ -599,4 +596,4 @@ BEGIN END GENERATE all_channel_sim; ----------------------------------------------------------------------------- -END beh; +END beh; \ No newline at end of file diff --git a/lib/lpp/lpp_waveform/lpp_waveform.vhd b/lib/lpp/lpp_waveform/lpp_waveform.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform.vhd @@ -1,485 +1,478 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr --- jean-christophe.pellion@easii-ic.com -------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -USE GRLIB.DMA2AHB_Package.ALL; - -LIBRARY lpp; -USE lpp.lpp_waveform_pkg.ALL; -USE lpp.iir_filter.ALL; -USE lpp.lpp_memory.ALL; - -LIBRARY techmap; -USE techmap.gencomp.ALL; - -ENTITY lpp_waveform IS - - GENERIC ( - tech : INTEGER := inferred; - data_size : INTEGER := 96; --16*6 - nb_data_by_buffer_size : INTEGER := 11; --- nb_word_by_buffer_size : INTEGER := 11; - nb_snapshot_param_size : INTEGER := 11; - delta_vector_size : INTEGER := 20; - delta_vector_size_f0_2 : INTEGER := 3); - - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - - ---- AMBA AHB Master Interface - --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO - --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO - - --config - reg_run : IN STD_LOGIC; - reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); - reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); - reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - - enable_f0 : IN STD_LOGIC; - enable_f1 : IN STD_LOGIC; - enable_f2 : IN STD_LOGIC; - enable_f3 : IN STD_LOGIC; - - burst_f0 : IN STD_LOGIC; - burst_f1 : IN STD_LOGIC; - burst_f2 : IN STD_LOGIC; - - nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); --- nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); - nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - - status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma - - - -- REG DMA - status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - addr_buffer : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); - length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0); - - ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); - error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - - --------------------------------------------------------------------------- - -- INPUT - coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); --- fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - - --f0 - data_f0_in_valid : IN STD_LOGIC; - data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - data_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - --f1 - data_f1_in_valid : IN STD_LOGIC; - data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - data_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - --f2 - data_f2_in_valid : IN STD_LOGIC; - data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - data_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - --f3 - data_f3_in_valid : IN STD_LOGIC; - data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - data_f3_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); - - --------------------------------------------------------------------------- - -- DMA -------------------------------------------------------------------- - - dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); - dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); - dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0); - dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0) - - ); - -END lpp_waveform; - -ARCHITECTURE beh OF lpp_waveform IS - SIGNAL start_snapshot_f0 : STD_LOGIC; - SIGNAL start_snapshot_f1 : STD_LOGIC; - SIGNAL start_snapshot_f2 : STD_LOGIC; - - SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - - SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - - SIGNAL data_f0_out_valid : STD_LOGIC; - SIGNAL data_f1_out_valid : STD_LOGIC; - SIGNAL data_f2_out_valid : STD_LOGIC; - SIGNAL data_f3_out_valid : STD_LOGIC; - SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0); - -- - SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0); - -- - SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0); - -- - SIGNAL run : STD_LOGIC; - -- - TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0); - SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); - SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); - SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0); - SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug - SIGNAL time_reg1 : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); - SIGNAL time_reg2 : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); - -- - - SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b - SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); --- SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); - - -- - SIGNAL arbiter_time_out : STD_LOGIC_VECTOR(47 DOWNTO 0); - SIGNAL arbiter_time_out_new : STD_LOGIC_VECTOR(3 DOWNTO 0); - - SIGNAL fifo_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); - - SIGNAL fifo_buffer_time_s : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); - -BEGIN -- beh - - ----------------------------------------------------------------------------- - - lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler - GENERIC MAP ( - delta_vector_size => delta_vector_size, - delta_vector_size_f0_2 => delta_vector_size_f0_2 - ) - PORT MAP ( - clk => clk, - rstn => rstn, - reg_run => reg_run, - reg_start_date => reg_start_date, - reg_delta_snapshot => reg_delta_snapshot, - reg_delta_f0 => reg_delta_f0, - reg_delta_f0_2 => reg_delta_f0_2, - reg_delta_f1 => reg_delta_f1, - reg_delta_f2 => reg_delta_f2, - coarse_time => coarse_time(30 DOWNTO 0), - data_f0_valid => data_f0_in_valid, - data_f2_valid => data_f2_in_valid, - start_snapshot_f0 => start_snapshot_f0, - start_snapshot_f1 => start_snapshot_f1, - start_snapshot_f2 => start_snapshot_f2, - wfp_on => run); - - lpp_waveform_snapshot_f0 : lpp_waveform_snapshot - GENERIC MAP ( - data_size => data_size, - nb_snapshot_param_size => nb_snapshot_param_size) - PORT MAP ( - clk => clk, - rstn => rstn, - run => run, - enable => enable_f0, - burst_enable => burst_f0, - nb_snapshot_param => nb_snapshot_param, - start_snapshot => start_snapshot_f0, - data_in => data_f0_in, - data_in_valid => data_f0_in_valid, - data_out => data_f0_out, - data_out_valid => data_f0_out_valid); - - nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1; - - lpp_waveform_snapshot_f1 : lpp_waveform_snapshot - GENERIC MAP ( - data_size => data_size, - nb_snapshot_param_size => nb_snapshot_param_size+1) - PORT MAP ( - clk => clk, - rstn => rstn, - run => run, - enable => enable_f1, - burst_enable => burst_f1, - nb_snapshot_param => nb_snapshot_param_more_one, - start_snapshot => start_snapshot_f1, - data_in => data_f1_in, - data_in_valid => data_f1_in_valid, - data_out => data_f1_out, - data_out_valid => data_f1_out_valid); - - lpp_waveform_snapshot_f2 : lpp_waveform_snapshot - GENERIC MAP ( - data_size => data_size, - nb_snapshot_param_size => nb_snapshot_param_size+1) - PORT MAP ( - clk => clk, - rstn => rstn, - run => run, - enable => enable_f2, - burst_enable => burst_f2, - nb_snapshot_param => nb_snapshot_param_more_one, - start_snapshot => start_snapshot_f2, - data_in => data_f2_in, - data_in_valid => data_f2_in_valid, - data_out => data_f2_out, - data_out_valid => data_f2_out_valid); - - lpp_waveform_burst_f3 : lpp_waveform_burst - GENERIC MAP ( - data_size => data_size) - PORT MAP ( - clk => clk, - rstn => rstn, - run => run, - enable => enable_f3, - data_in => data_f3_in, - data_in_valid => data_f3_in_valid, - data_out => data_f3_out, - data_out_valid => data_f3_out_valid); - - ----------------------------------------------------------------------------- - -- DEBUG -- SNAPSHOT OUT - --debug_f0_data_valid <= data_f0_out_valid; - --debug_f0_data <= data_f0_out; - --debug_f1_data_valid <= data_f1_out_valid; - --debug_f1_data <= data_f1_out; - --debug_f2_data_valid <= data_f2_out_valid; - --debug_f2_data <= data_f2_out; - --debug_f3_data_valid <= data_f3_out_valid; - --debug_f3_data <= data_f3_out; - ----------------------------------------------------------------------------- - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - time_reg1 <= (OTHERS => '0'); - time_reg2 <= (OTHERS => '0'); - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - time_reg1(48*1-1 DOWNTO 48*0) <= data_f0_time(15 DOWNTO 0) & data_f0_time(47 DOWNTO 16); - time_reg1(48*2-1 DOWNTO 48*1) <= data_f1_time(15 DOWNTO 0) & data_f1_time(47 DOWNTO 16); - time_reg1(48*3-1 DOWNTO 48*2) <= data_f2_time(15 DOWNTO 0) & data_f2_time(47 DOWNTO 16); - time_reg1(48*4-1 DOWNTO 48*3) <= data_f3_time(15 DOWNTO 0) & data_f3_time(47 DOWNTO 16); - time_reg2 <= time_reg1; - END IF; - END PROCESS; - - valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid; - all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE - lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid - PORT MAP ( - HCLK => clk, - HRESETn => rstn, - run => run, - valid_in => valid_in(I), - ack_in => valid_ack(I), - time_in => time_reg2(48*(I+1)-1 DOWNTO 48*I), -- Todo - valid_out => valid_out(I), - time_out => time_out(I), -- Todo - error => status_new_err(I)); - END GENERATE all_input_valid; - - data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) & - data_f0_out((16*6)-1 DOWNTO 16*5) & - data_f0_out((16*3)-1 DOWNTO 16*2) & - data_f0_out((16*4)-1 DOWNTO 16*3) & - data_f0_out((16*1)-1 DOWNTO 16*0) & - data_f0_out((16*2)-1 DOWNTO 16*1) ; - - data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) & - data_f1_out((16*6)-1 DOWNTO 16*5) & - data_f1_out((16*3)-1 DOWNTO 16*2) & - data_f1_out((16*4)-1 DOWNTO 16*3) & - data_f1_out((16*1)-1 DOWNTO 16*0) & - data_f1_out((16*2)-1 DOWNTO 16*1) ; - - data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) & - data_f2_out((16*6)-1 DOWNTO 16*5) & - data_f2_out((16*3)-1 DOWNTO 16*2) & - data_f2_out((16*4)-1 DOWNTO 16*3) & - data_f2_out((16*1)-1 DOWNTO 16*0) & - data_f2_out((16*2)-1 DOWNTO 16*1) ; - - data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) & - data_f3_out((16*6)-1 DOWNTO 16*5) & - data_f3_out((16*3)-1 DOWNTO 16*2) & - data_f3_out((16*4)-1 DOWNTO 16*3) & - data_f3_out((16*1)-1 DOWNTO 16*0) & - data_f3_out((16*2)-1 DOWNTO 16*1) ; - - all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE - data_out(0, I) <= data_f0_out_swap(I); - data_out(1, I) <= data_f1_out_swap(I); - data_out(2, I) <= data_f2_out_swap(I); - data_out(3, I) <= data_f3_out_swap(I); - END GENERATE all_bit_of_data_out; - - ----------------------------------------------------------------------------- - -- TODO : debug - ----------------------------------------------------------------------------- - all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE - all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE - time_out_2(J, I) <= time_out(J)(I); - END GENERATE all_sample_of_time_out; - END GENERATE all_bit_of_time_out; - - lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter - GENERIC MAP (tech => tech, - nb_data_by_buffer_size => nb_data_by_buffer_size) - PORT MAP ( - clk => clk, - rstn => rstn, - run => run, - nb_data_by_buffer => nb_data_by_buffer, - data_in_valid => valid_out, - data_in_ack => valid_ack, - data_in => data_out, - time_in => time_out_2, - - data_out => wdata, - data_out_wen => data_wen, - full_almost => full_almost, - full => full, - - time_out => arbiter_time_out, - time_out_new => arbiter_time_out_new - - ); - - ----------------------------------------------------------------------------- - ----------------------------------------------------------------------------- - - generate_all_fifo: FOR I IN 0 TO 3 GENERATE - lpp_fifo_1: lpp_fifo - GENERIC MAP ( - tech => 0, - Mem_use => use_RAM, - EMPTY_THRESHOLD_LIMIT => 15, - FULL_THRESHOLD_LIMIT => 3, - DataSz => 32, - AddrSz => 7) - PORT MAP ( - clk => clk, - rstn => rstn, - reUse => '0', - run => run, - ren => data_ren(I), - rdata => s_rdata_v((I+1)*32-1 downto I*32), - wen => data_wen(I), - wdata => wdata, - empty => empty(I), - full => full(I), - full_almost => OPEN, - empty_threshold => empty_almost(I), - full_threshold => full_almost(I) ); - - END GENERATE generate_all_fifo; - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - - all_channel: FOR I IN 3 DOWNTO 0 GENERATE - - PROCESS (clk, rstn) - BEGIN - IF rstn = '0' THEN - fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0'); - ELSIF clk'event AND clk = '1' THEN - IF run = '0' THEN - fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0'); - ELSE - IF arbiter_time_out_new(I) = '1' THEN -- modif JC 15-01-2015 - fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out; - END IF; - END IF; - END IF; - END PROCESS; - - fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out WHEN arbiter_time_out_new(I) = '1' ELSE - fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I); - - lpp_waveform_fsmdma_I: lpp_waveform_fsmdma - PORT MAP ( - clk => clk, - rstn => rstn, - run => run, - - fifo_buffer_time => fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I), - - fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I), - fifo_empty => empty(I), - fifo_empty_threshold => empty_almost(I), - fifo_ren => data_ren(I), - - dma_fifo_valid_burst => dma_fifo_valid_burst(I), - dma_fifo_data => dma_fifo_data(32*(I+1)-1 DOWNTO 32*I), - dma_fifo_ren => dma_fifo_ren(I), - dma_buffer_new => dma_buffer_new(I), - dma_buffer_addr => dma_buffer_addr(32*(I+1)-1 DOWNTO 32*I), - dma_buffer_length => dma_buffer_length(26*(I+1)-1 DOWNTO 26*I), - dma_buffer_full => dma_buffer_full(I), - dma_buffer_full_err => dma_buffer_full_err(I), - - status_buffer_ready => status_buffer_ready(I), -- TODO - addr_buffer => addr_buffer(32*(I+1)-1 DOWNTO 32*I), -- TODO - length_buffer => length_buffer,--(26*(I+1)-1 DOWNTO 26*I), -- TODO - ready_buffer => ready_buffer(I), -- TODO - buffer_time => OPEN,--buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO - error_buffer_full => error_buffer_full(I)); -- TODO - - buffer_time(48*(I+1)-1 DOWNTO 48*I) <= fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I); - - END GENERATE all_channel; - - -END beh; +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +LIBRARY lpp; +USE lpp.lpp_waveform_pkg.ALL; +USE lpp.iir_filter.ALL; +USE lpp.lpp_memory.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_waveform IS + + GENERIC ( + tech : INTEGER := inferred; + data_size : INTEGER := 96; --16*6 + nb_data_by_buffer_size : INTEGER := 11; +-- nb_word_by_buffer_size : INTEGER := 11; + nb_snapshot_param_size : INTEGER := 11; + delta_vector_size : INTEGER := 20; + delta_vector_size_f0_2 : INTEGER := 3); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + ---- AMBA AHB Master Interface + --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO + --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO + + --config + reg_run : IN STD_LOGIC; + reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); + reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); + reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + + enable_f0 : IN STD_LOGIC; + enable_f1 : IN STD_LOGIC; + enable_f2 : IN STD_LOGIC; + enable_f3 : IN STD_LOGIC; + + burst_f0 : IN STD_LOGIC; + burst_f1 : IN STD_LOGIC; + burst_f2 : IN STD_LOGIC; + + nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); +-- nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); + nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + + status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma + + + -- REG DMA + status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + addr_buffer : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); + length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0); + + ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); + error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + + --------------------------------------------------------------------------- + -- INPUT + coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); +-- fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + --f0 + data_f0_in_valid : IN STD_LOGIC; + data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + --f1 + data_f1_in_valid : IN STD_LOGIC; + data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + --f2 + data_f2_in_valid : IN STD_LOGIC; + data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + --f3 + data_f3_in_valid : IN STD_LOGIC; + data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f3_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + + --------------------------------------------------------------------------- + -- DMA -------------------------------------------------------------------- + + dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); + dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); + dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0); + dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0) + + ); + +END lpp_waveform; + +ARCHITECTURE beh OF lpp_waveform IS + SIGNAL start_snapshot_f0 : STD_LOGIC; + SIGNAL start_snapshot_f1 : STD_LOGIC; + SIGNAL start_snapshot_f2 : STD_LOGIC; + + SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + + SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + + SIGNAL data_f0_out_valid : STD_LOGIC; + SIGNAL data_f1_out_valid : STD_LOGIC; + SIGNAL data_f2_out_valid : STD_LOGIC; + SIGNAL data_f3_out_valid : STD_LOGIC; + SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0); + -- + SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0); + -- + SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + -- + SIGNAL run : STD_LOGIC; + -- + TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); + SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); + SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0); + SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug + SIGNAL time_reg1 : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); + SIGNAL time_reg2 : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); + -- + + SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b + SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); +-- SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); + + -- + SIGNAL arbiter_time_out : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL arbiter_time_out_new : STD_LOGIC_VECTOR(3 DOWNTO 0); + + SIGNAL fifo_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); + + SIGNAL fifo_buffer_time_s : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); + +BEGIN -- beh + + ----------------------------------------------------------------------------- + + lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler + GENERIC MAP ( + delta_vector_size => delta_vector_size, + delta_vector_size_f0_2 => delta_vector_size_f0_2 + ) + PORT MAP ( + clk => clk, + rstn => rstn, + reg_run => reg_run, + reg_start_date => reg_start_date, + reg_delta_snapshot => reg_delta_snapshot, + reg_delta_f0 => reg_delta_f0, + reg_delta_f0_2 => reg_delta_f0_2, + reg_delta_f1 => reg_delta_f1, + reg_delta_f2 => reg_delta_f2, + coarse_time => coarse_time(30 DOWNTO 0), + data_f0_valid => data_f0_in_valid, + data_f2_valid => data_f2_in_valid, + start_snapshot_f0 => start_snapshot_f0, + start_snapshot_f1 => start_snapshot_f1, + start_snapshot_f2 => start_snapshot_f2, + wfp_on => run); + + lpp_waveform_snapshot_f0 : lpp_waveform_snapshot + GENERIC MAP ( + data_size => data_size, + nb_snapshot_param_size => nb_snapshot_param_size) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + enable => enable_f0, + burst_enable => burst_f0, + nb_snapshot_param => nb_snapshot_param, + start_snapshot => start_snapshot_f0, + data_in => data_f0_in, + data_in_valid => data_f0_in_valid, + data_out => data_f0_out, + data_out_valid => data_f0_out_valid); + + nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1; + + lpp_waveform_snapshot_f1 : lpp_waveform_snapshot + GENERIC MAP ( + data_size => data_size, + nb_snapshot_param_size => nb_snapshot_param_size+1) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + enable => enable_f1, + burst_enable => burst_f1, + nb_snapshot_param => nb_snapshot_param_more_one, + start_snapshot => start_snapshot_f1, + data_in => data_f1_in, + data_in_valid => data_f1_in_valid, + data_out => data_f1_out, + data_out_valid => data_f1_out_valid); + + lpp_waveform_snapshot_f2 : lpp_waveform_snapshot + GENERIC MAP ( + data_size => data_size, + nb_snapshot_param_size => nb_snapshot_param_size+1) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + enable => enable_f2, + burst_enable => burst_f2, + nb_snapshot_param => nb_snapshot_param_more_one, + start_snapshot => start_snapshot_f2, + data_in => data_f2_in, + data_in_valid => data_f2_in_valid, + data_out => data_f2_out, + data_out_valid => data_f2_out_valid); + + lpp_waveform_burst_f3 : lpp_waveform_burst + GENERIC MAP ( + data_size => data_size) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + enable => enable_f3, + data_in => data_f3_in, + data_in_valid => data_f3_in_valid, + data_out => data_f3_out, + data_out_valid => data_f3_out_valid); + + ----------------------------------------------------------------------------- + -- DEBUG -- SNAPSHOT OUT + --debug_f0_data_valid <= data_f0_out_valid; + --debug_f0_data <= data_f0_out; + --debug_f1_data_valid <= data_f1_out_valid; + --debug_f1_data <= data_f1_out; + --debug_f2_data_valid <= data_f2_out_valid; + --debug_f2_data <= data_f2_out; + --debug_f3_data_valid <= data_f3_out_valid; + --debug_f3_data <= data_f3_out; + ----------------------------------------------------------------------------- + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + time_reg1 <= (OTHERS => '0'); + time_reg2 <= (OTHERS => '0'); + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + time_reg1(48*1-1 DOWNTO 48*0) <= data_f0_time(15 DOWNTO 0) & data_f0_time(47 DOWNTO 16); + time_reg1(48*2-1 DOWNTO 48*1) <= data_f1_time(15 DOWNTO 0) & data_f1_time(47 DOWNTO 16); + time_reg1(48*3-1 DOWNTO 48*2) <= data_f2_time(15 DOWNTO 0) & data_f2_time(47 DOWNTO 16); + time_reg1(48*4-1 DOWNTO 48*3) <= data_f3_time(15 DOWNTO 0) & data_f3_time(47 DOWNTO 16); + time_reg2 <= time_reg1; + END IF; + END PROCESS; + + valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid; + all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE + lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid + PORT MAP ( + HCLK => clk, + HRESETn => rstn, + run => run, + valid_in => valid_in(I), + ack_in => valid_ack(I), + time_in => time_reg2(48*(I+1)-1 DOWNTO 48*I), -- Todo + valid_out => valid_out(I), + time_out => time_out(I), -- Todo + error => status_new_err(I)); + END GENERATE all_input_valid; + + data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) & + data_f0_out((16*6)-1 DOWNTO 16*5) & + data_f0_out((16*3)-1 DOWNTO 16*2) & + data_f0_out((16*4)-1 DOWNTO 16*3) & + data_f0_out((16*1)-1 DOWNTO 16*0) & + data_f0_out((16*2)-1 DOWNTO 16*1) ; + + data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) & + data_f1_out((16*6)-1 DOWNTO 16*5) & + data_f1_out((16*3)-1 DOWNTO 16*2) & + data_f1_out((16*4)-1 DOWNTO 16*3) & + data_f1_out((16*1)-1 DOWNTO 16*0) & + data_f1_out((16*2)-1 DOWNTO 16*1) ; + + data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) & + data_f2_out((16*6)-1 DOWNTO 16*5) & + data_f2_out((16*3)-1 DOWNTO 16*2) & + data_f2_out((16*4)-1 DOWNTO 16*3) & + data_f2_out((16*1)-1 DOWNTO 16*0) & + data_f2_out((16*2)-1 DOWNTO 16*1) ; + + data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) & + data_f3_out((16*6)-1 DOWNTO 16*5) & + data_f3_out((16*3)-1 DOWNTO 16*2) & + data_f3_out((16*4)-1 DOWNTO 16*3) & + data_f3_out((16*1)-1 DOWNTO 16*0) & + data_f3_out((16*2)-1 DOWNTO 16*1) ; + + all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE + data_out(0, I) <= data_f0_out_swap(I); + data_out(1, I) <= data_f1_out_swap(I); + data_out(2, I) <= data_f2_out_swap(I); + data_out(3, I) <= data_f3_out_swap(I); + END GENERATE all_bit_of_data_out; + + ----------------------------------------------------------------------------- + -- TODO : debug + ----------------------------------------------------------------------------- + all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE + all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE + time_out_2(J, I) <= time_out(J)(I); + END GENERATE all_sample_of_time_out; + END GENERATE all_bit_of_time_out; + + lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter + GENERIC MAP (tech => tech, + nb_data_by_buffer_size => nb_data_by_buffer_size) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + nb_data_by_buffer => nb_data_by_buffer, + data_in_valid => valid_out, + data_in_ack => valid_ack, + data_in => data_out, + time_in => time_out_2, + + data_out => wdata, + data_out_wen => data_wen, + full_almost => full_almost, + full => full, + + time_out => arbiter_time_out, + time_out_new => arbiter_time_out_new + + ); + + ----------------------------------------------------------------------------- + ----------------------------------------------------------------------------- + + generate_all_fifo: FOR I IN 0 TO 3 GENERATE + lpp_fifo_1: lpp_fifo + GENERIC MAP ( + tech => 0, + Mem_use => use_RAM, + EMPTY_THRESHOLD_LIMIT => 15, + FULL_THRESHOLD_LIMIT => 3, + DataSz => 32, + AddrSz => 7) + PORT MAP ( + clk => clk, + rstn => rstn, + reUse => '0', + run => run, + ren => data_ren(I), + rdata => s_rdata_v((I+1)*32-1 downto I*32), + wen => data_wen(I), + wdata => wdata, + empty => empty(I), + full => full(I), + full_almost => OPEN, + empty_threshold => empty_almost(I), + full_threshold => full_almost(I) ); + + END GENERATE generate_all_fifo; + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + + all_channel: FOR I IN 3 DOWNTO 0 GENERATE + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN + IF run = '0' THEN + fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0'); + ELSE + IF arbiter_time_out_new(I) = '1' THEN -- modif JC 15-01-2015 + fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out; + END IF; + END IF; + END IF; + END PROCESS; + + fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out WHEN arbiter_time_out_new(I) = '1' ELSE + fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I); + + lpp_waveform_fsmdma_I: lpp_waveform_fsmdma + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + + fifo_buffer_time => fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I), + + fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I), + fifo_empty => empty(I), + fifo_empty_threshold => empty_almost(I), + fifo_ren => data_ren(I), + + dma_fifo_valid_burst => dma_fifo_valid_burst(I), + dma_fifo_data => dma_fifo_data(32*(I+1)-1 DOWNTO 32*I), + dma_fifo_ren => dma_fifo_ren(I), + dma_buffer_new => dma_buffer_new(I), + dma_buffer_addr => dma_buffer_addr(32*(I+1)-1 DOWNTO 32*I), + dma_buffer_length => dma_buffer_length(26*(I+1)-1 DOWNTO 26*I), + dma_buffer_full => dma_buffer_full(I), + dma_buffer_full_err => dma_buffer_full_err(I), + + status_buffer_ready => status_buffer_ready(I), -- TODO + addr_buffer => addr_buffer(32*(I+1)-1 DOWNTO 32*I), -- TODO + length_buffer => length_buffer,--(26*(I+1)-1 DOWNTO 26*I), -- TODO + ready_buffer => ready_buffer(I), -- TODO + buffer_time => OPEN,--buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO + error_buffer_full => error_buffer_full(I)); -- TODO + + buffer_time(48*(I+1)-1 DOWNTO 48*I) <= fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I); + + END GENERATE all_channel; + + +END beh; \ No newline at end of file