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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23
24 24 LIBRARY ieee;
25 25 USE ieee.std_logic_1164.ALL;
26 26 USE ieee.numeric_std.ALL;
27 27
28 28
29 29 LIBRARY lpp;
30 30 USE lpp.cic_pkg.ALL;
31 31 USE lpp.data_type_pkg.ALL;
32 32
33 33 ENTITY cic_lfr_control_r2 IS
34 34 PORT (
35 35 clk : IN STD_LOGIC;
36 36 rstn : IN STD_LOGIC;
37 run : IN STD_LOGIC;
37 -- run : IN STD_LOGIC;
38 38 --
39 39 data_in_valid : IN STD_LOGIC;
40 40 data_out_16_valid : OUT STD_LOGIC;
41 41 data_out_256_valid : OUT STD_LOGIC;
42 42 --
43 43 OPERATION : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
44 44 );
45 45
46 46 END cic_lfr_control_r2;
47 47
48 48 ARCHITECTURE beh OF cic_lfr_control_r2 IS
49 49
50 50 TYPE STATE_CIC_LFR_TYPE IS (IDLE,
51 51 RUN_PROG_I,
52 52 RUN_PROG_C16,
53 53 RUN_PROG_C256
54 54 );
55 55
56 56 SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
57 57
58 SIGNAL nb_data_receipt : INTEGER := 0;
58 SIGNAL nb_data_receipt : INTEGER RANGE 0 TO 255:= 0;
59 59 SIGNAL current_cmd : INTEGER := 0;
60 60 SIGNAL current_channel : INTEGER := 0;
61 61 SIGNAL sample_16_odd : STD_LOGIC;
62 62 SIGNAL sample_256_odd : STD_LOGIC;
63 63
64 64 TYPE PROGRAM_ARRAY IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(13 DOWNTO 0);
65 65 --OPERATION( 8 DOWNTO 0) <= PROGRAM_ARRAY( 8 DOWNTO 0) sauf pour PROG_I(0)
66 66 --OPERATION(13 DOWNTO 12) <= PROGRAM_ARRAY(10 DOWNTO 9)
67 67 --OPERATION(11 DOWNTO 9) <= current_channel
68 68 --OPERATION(14) <= PROGRAM_ARRAY(11) selon sample_X_odd et l'etat
69 69 CONSTANT PROG : PROGRAM_ARRAY(0 TO 28) :=
70 70 (
71 71 -- DCBA 98765 43210
72 72 --PROG I------------------
73 73 "0001" & "00011" & "00000", --0
74 74 "0101" & "00010" & "00001", --1
75 75 "0101" & "00010" & "00001", --2
76 76 "0001" & "00010" & "01011", --3
77 77 "0101" & "00010" & "01001", --4
78 78 "0101" & "00010" & "01001", --5
79 79 "0001" & "00010" & "01011", --6
80 80 "0101" & "00010" & "01001", --7
81 81 "0101" & "00010" & "01001", --8
82 82 --PROG_C16
83 83 "1001" & "00100" & "10010", --9
84 84 "1001" & "10010" & "10101", --10
85 85 "1001" & "10010" & "10101", --11
86 86 "1010" & "10010" & "10101", --12
87 87 "1001" & "01000" & "10010", --13
88 88 "1001" & "10010" & "11101", --14
89 89 "1001" & "10010" & "11101", --15
90 90 "1010" & "10010" & "11101", --16
91 91 --PROG_C256
92 92 "1001" & "00100" & "10010", --17
93 93 "1001" & "10110" & "10101", --18
94 94 "1001" & "10110" & "10101", --19
95 95 "1010" & "10110" & "10101", --20
96 96 "1001" & "01000" & "10010", --21
97 97 "1001" & "10110" & "11101", --22
98 98 "1001" & "10110" & "11101", --23
99 99 "1010" & "10110" & "11101", --24
100 100 "1001" & "01100" & "10010", --25
101 101 "1001" & "10110" & "11101", --26
102 102 "1001" & "10110" & "11101", --27
103 103 "1010" & "10110" & "11101" --28
104 104 );
105 105
106 106
107 107 CONSTANT PROG_START_I : INTEGER := 0;
108 108 CONSTANT PROG_END_I : INTEGER := 8;
109 109 CONSTANT PROG_START_C16 : INTEGER := 9;
110 110 CONSTANT PROG_END_C16 : INTEGER := 16;
111 111 CONSTANT PROG_START_C256 : INTEGER := 17;
112 112 CONSTANT PROG_END_C256 : INTEGER := 28;
113 113
114 114 BEGIN
115 115
116 116 OPERATION(2 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3)); --SEL_SAMPLE
117 117 OPERATION(4 DOWNTO 3) <= PROG(current_cmd)(1 DOWNTO 0); --SEL_DATA_A
118 118 OPERATION(6 DOWNTO 5) <= "00" WHEN STATE_CIC_LFR = IDLE ELSE PROG(current_cmd)(3 DOWNTO 2); --ALU_CMD
119 119 OPERATION(7) <= '0' WHEN STATE_CIC_LFR = IDLE ELSE PROG(current_cmd)(4); --CARRY_PUSH
120 120 OPERATION(8) <= PROG(current_cmd)(5); --@_init
121 121 OPERATION(9) <= PROG(current_cmd)(6); --@_add_1
122 122
123 123 OPERATION(10) <= PROG(current_cmd)(7) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 AND PROG(current_cmd)(9) = '1' ELSE
124 124 PROG(current_cmd)(7); --@_sel(1..0)
125 125 OPERATION(11) <= PROG(current_cmd)(8);
126 126 OPERATION(12) <= PROG(current_cmd)(9) AND sample_16_odd WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE
127 127 --PROG(current_cmd)(9) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE
128 128 PROG(current_cmd)(9) WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE
129 129 '0'; --@_sel(2)
130 130
131 131
132 132 OPERATION(13) <= '0' WHEN STATE_CIC_LFR = IDLE ELSE PROG(current_cmd)(10); --WE
133 133 OPERATION(14) <= PROG(current_cmd)(12); -- SEL_DATA_A = data_b_reg
134 134 OPERATION(15) <= PROG(current_cmd)(13); -- WRITE_ADDR_sel
135 135 data_out_16_valid <= PROG(current_cmd)(11) WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE '0';
136 136 data_out_256_valid <= PROG(current_cmd)(11) WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0';
137 137
138 138
139 139
140 140
141 141
142 142
143 143
144 144
145 145
146 146
147 147 --OPERATION(1 DOWNTO 0) <= PROG(current_cmd)(1 DOWNTO 0);
148 148 --OPERATION(2) <= '0' WHEN STATE_CIC_LFR = IDLE ELSE
149 149 -- PROG(current_cmd)(2);
150 150 --OPERATION(5 DOWNTO 3) <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3)) WHEN STATE_CIC_LFR = RUN_PROG_I AND current_cmd = 0 ELSE
151 151 -- PROG(current_cmd)(5 DOWNTO 3);
152 152
153 153 --OPERATION(8 DOWNTO 6) <= "000" WHEN STATE_CIC_LFR = IDLE ELSE
154 154 -- PROG(current_cmd)(8 DOWNTO 6);
155 155 --OPERATION(11 DOWNTO 9) <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3));
156 156 --OPERATION(13 DOWNTO 12) <= PROG(current_cmd)(10 DOWNTO 9);
157 157 --OPERATION(14) <= PROG(current_cmd)(11) AND sample_16_odd WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE
158 158 -- PROG(current_cmd)(11) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0';
159 159
160 160 --OPERATION(15) <= PROG(current_cmd)(12);
161 161
162 162 --data_out_16_valid <= PROG(current_cmd)(13) WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE '0';
163 163 --data_out_256_valid <= PROG(current_cmd)(13) WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0';
164 164
165 165 PROCESS (clk, rstn)
166 166 BEGIN
167 167 IF rstn = '0' THEN
168 168 STATE_CIC_LFR <= IDLE;
169 169 nb_data_receipt <= 0;
170 170 current_channel <= 0;
171 171 current_cmd <= 0;
172 172 sample_16_odd <= '0';
173 173 sample_256_odd <= '0';
174 174
175 175 ELSIF clk'EVENT AND clk = '1' THEN
176 176
177 177 CASE STATE_CIC_LFR IS
178 178 WHEN IDLE =>
179 179 IF data_in_valid = '1' THEN
180 180 STATE_CIC_LFR <= RUN_PROG_I;
181 181 current_cmd <= PROG_START_I;
182 182 current_channel <= 0;
183 183 nb_data_receipt <= nb_data_receipt + 1;
184 184 END IF;
185 185
186 186 WHEN RUN_PROG_I =>
187 187 IF current_cmd = PROG_END_I THEN
188 188 IF nb_data_receipt MOD 16 = 15 THEN
189 189 STATE_CIC_LFR <= RUN_PROG_C16;
190 190 current_cmd <= PROG_START_C16;
191 191 IF current_channel = 0 THEN
192 192 sample_16_odd <= NOT sample_16_odd;
193 193 END IF;
194 194 ELSE
195 195 IF current_channel = 7 THEN
196 196 current_channel <= 0;
197 197 STATE_CIC_LFR <= IDLE;
198 198 ELSE
199 199 current_cmd <= PROG_START_I;
200 200 current_channel <= current_channel + 1;
201 201 END IF;
202 202 END IF;
203 203 ELSE
204 204 current_cmd <= current_cmd +1;
205 205 END IF;
206 206
207 207 WHEN RUN_PROG_C16 =>
208 208 IF current_cmd = PROG_END_C16 THEN
209 209 IF nb_data_receipt MOD 256 = 255 AND current_channel < 6 THEN
210 210 STATE_CIC_LFR <= RUN_PROG_C256;
211 211 current_cmd <= PROG_START_C256;
212 212 IF current_channel = 0 THEN
213 213 sample_256_odd <= NOT sample_256_odd;
214 214 END IF;
215 215 ELSE
216 216 IF current_channel = 7 THEN
217 217 current_channel <= 0;
218 218 STATE_CIC_LFR <= IDLE;
219 219 ELSE
220 220 STATE_CIC_LFR <= RUN_PROG_I;
221 221 current_cmd <= PROG_START_I;
222 222 current_channel <= current_channel + 1;
223 223 END IF;
224 224 END IF;
225 225 ELSE
226 226 current_cmd <= current_cmd +1;
227 227 END IF;
228 228
229 229 WHEN RUN_PROG_C256 =>
230 230 IF current_cmd = PROG_END_C256 THEN
231 231 -- data_out_256_valid <= '1';
232 232 -- IF current_channel = 5 THEN
233 233 -- current_channel <= 0;
234 234 -- STATE_CIC_LFR <= IDLE;
235 235 -- ELSE
236 236 STATE_CIC_LFR <= RUN_PROG_I;
237 237 current_cmd <= PROG_START_I;
238 238 current_channel <= current_channel + 1;
239 239 -- END IF;
240 240 ELSE
241 241 current_cmd <= current_cmd +1;
242 242 END IF;
243 243
244 244 WHEN OTHERS => NULL;
245 245 END CASE;
246 246 END IF;
247 247 END PROCESS;
248 248
249 END beh;
249 END beh; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,393 +1,393
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23
24 24 LIBRARY ieee;
25 25 USE ieee.std_logic_1164.ALL;
26 26 USE ieee.numeric_std.all;
27 27
28 28 LIBRARY lpp;
29 29 USE lpp.cic_pkg.ALL;
30 30 USE lpp.data_type_pkg.ALL;
31 31 USE lpp.iir_filter.ALL;
32 32
33 33 LIBRARY techmap;
34 34 USE techmap.gencomp.ALL;
35 35
36 36 ENTITY cic_lfr_r2 IS
37 37 GENERIC(
38 38 tech : INTEGER := 0;
39 39 use_RAM_nCEL : INTEGER := 0 -- 1 => RAM(tech) , 0 => RAM_CEL
40 40 );
41 41 PORT (
42 42 clk : IN STD_LOGIC;
43 43 rstn : IN STD_LOGIC;
44 44 run : IN STD_LOGIC;
45 45
46 46 param_r2 : IN STD_LOGIC;
47 47
48 48 data_in : IN sample_vector(7 DOWNTO 0,15 DOWNTO 0);
49 49 data_in_valid : IN STD_LOGIC;
50 50
51 51 data_out_16 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
52 52 data_out_16_valid : OUT STD_LOGIC;
53 53 data_out_256 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
54 54 data_out_256_valid : OUT STD_LOGIC
55 55 );
56 56
57 57 END cic_lfr_r2;
58 58
59 59 ARCHITECTURE beh OF cic_lfr_r2 IS
60 60 --
61 61 SIGNAL sel_sample : STD_LOGIC_VECTOR(2 DOWNTO 0);
62 62 SIGNAL sample_temp : sample_vector(5 DOWNTO 0,15 DOWNTO 0);
63 63 SIGNAL sample : STD_LOGIC_VECTOR(15 DOWNTO 0);
64 64 --
65 65 SIGNAL sel_A : STD_LOGIC_VECTOR(1 DOWNTO 0);
66 66 SIGNAL data_A_temp : sample_vector(2 DOWNTO 0,15 DOWNTO 0);
67 67 SIGNAL data_A : STD_LOGIC_VECTOR(15 DOWNTO 0);
68 68 --
69 69 SIGNAL ALU_OP : STD_LOGIC_VECTOR(1 DOWNTO 0);
70 70 SIGNAL data_B : STD_LOGIC_VECTOR(15 DOWNTO 0);
71 71 SIGNAL data_B_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
72 72 SIGNAL data_out : STD_LOGIC_VECTOR(15 DOWNTO 0);
73 73 SIGNAL data_in_Carry : STD_LOGIC;
74 74 SIGNAL data_out_Carry : STD_LOGIC;
75 75 --
76 76 CONSTANT S_parameter : INTEGER := 3;
77 77 SIGNAL carry_reg : STD_LOGIC_VECTOR(S_parameter-1 DOWNTO 0);
78 78 --
79 79
80 80 SIGNAL OPERATION : STD_LOGIC_VECTOR(15 DOWNTO 0);
81 81 SIGNAL OPERATION_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
82 82 SIGNAL OPERATION_reg2: STD_LOGIC_VECTOR(15 DOWNTO 0);
83 83
84 84 -----------------------------------------------------------------------------
85 85 TYPE ARRAY_OF_ADDR IS ARRAY (7 DOWNTO 0) OF STD_LOGIC_VECTOR(8 DOWNTO 0);
86 86 SIGNAL base_addr_INT : ARRAY_OF_ADDR;
87 87 CONSTANT base_addr_delta : INTEGER := 40;
88 88 SIGNAL addr_base_sel : STD_LOGIC_VECTOR(8 DOWNTO 0);
89 89 SIGNAL addr_gen: STD_LOGIC_VECTOR(8 DOWNTO 0);
90 90 SIGNAL addr_read: STD_LOGIC_VECTOR(8 DOWNTO 0);
91 91 SIGNAL addr_write: STD_LOGIC_VECTOR(8 DOWNTO 0);
92 92 SIGNAL addr_write_s: STD_LOGIC_VECTOR(8 DOWNTO 0);
93 93 SIGNAL data_we: STD_LOGIC;
94 94 SIGNAL data_we_s: STD_LOGIC;
95 95 SIGNAL data_wen : STD_LOGIC;
96 96 -----------------------------------------------------------------------------
97 97 SIGNAL sample_out_reg16 : sample_vector(8*2-1 DOWNTO 0, 15 DOWNTO 0);
98 98 SIGNAL sample_out_reg256 : sample_vector(6*3-1 DOWNTO 0, 15 DOWNTO 0);
99 99 SIGNAL sample_valid_reg16 : STD_LOGIC_VECTOR(8*2 DOWNTO 0);
100 100 SIGNAL sample_valid_reg256: STD_LOGIC_VECTOR(6*3 DOWNTO 0);
101 101 SIGNAL data_out_16_valid_s : STD_LOGIC;
102 102 SIGNAL data_out_256_valid_s : STD_LOGIC;
103 103 SIGNAL data_out_16_valid_s1 : STD_LOGIC;
104 104 SIGNAL data_out_256_valid_s1 : STD_LOGIC;
105 105 SIGNAL data_out_16_valid_s2 : STD_LOGIC;
106 106 SIGNAL data_out_256_valid_s2 : STD_LOGIC;
107 107 -----------------------------------------------------------------------------
108 108 SIGNAL sample_out_reg16_s : sample_vector(5 DOWNTO 0, 16*2-1 DOWNTO 0);
109 109 SIGNAL sample_out_reg256_s : sample_vector(5 DOWNTO 0, 16*3-1 DOWNTO 0);
110 110 -----------------------------------------------------------------------------
111 111
112 112
113 113 BEGIN
114 114
115 115
116 116 PROCESS (clk, rstn)
117 117 BEGIN -- PROCESS
118 118 IF rstn = '0' THEN -- asynchronous reset (active low)
119 119 data_B_reg <= (OTHERS => '0');
120 120 OPERATION_reg <= (OTHERS => '0');
121 121 OPERATION_reg2 <= (OTHERS => '0');
122 122 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
123 123 OPERATION_reg <= OPERATION;
124 124 OPERATION_reg2 <= OPERATION_reg;
125 125 data_B_reg <= data_B;
126 126 END IF;
127 127 END PROCESS;
128 128
129 129
130 130 -----------------------------------------------------------------------------
131 131 -- SEL_SAMPLE
132 132 -----------------------------------------------------------------------------
133 133 sel_sample <= OPERATION_reg(2 DOWNTO 0);
134 134
135 135 all_bit: FOR I IN 15 DOWNTO 0 GENERATE
136 136 sample_temp(0,I) <= data_in(0,I) WHEN sel_sample(0) = '0' ELSE data_in(1,I);
137 137 sample_temp(1,I) <= data_in(2,I) WHEN sel_sample(0) = '0' ELSE data_in(3,I);
138 138 sample_temp(2,I) <= data_in(4,I) WHEN sel_sample(0) = '0' ELSE data_in(5,I);
139 139 sample_temp(3,I) <= data_in(6,I) WHEN sel_sample(0) = '0' ELSE data_in(7,I);
140 140
141 141 sample_temp(4,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE sample_temp(1,I);
142 142 sample_temp(5,I) <= sample_temp(2,I) WHEN sel_sample(1) = '0' ELSE sample_temp(3,I);
143 143
144 144 sample(I) <= sample_temp(4,I) WHEN sel_sample(2) = '0' ELSE sample_temp(5,I);
145 145 END GENERATE all_bit;
146 146
147 147 -----------------------------------------------------------------------------
148 148 -- SEL_DATA_IN_A
149 149 -----------------------------------------------------------------------------
150 150 sel_A <= OPERATION_reg(4 DOWNTO 3);
151 151
152 152 all_data_mux_A: FOR I IN 15 DOWNTO 0 GENERATE
153 153 data_A_temp(0,I) <= sample(I) WHEN sel_A(0) = '0' ELSE data_out(I);
154 154 data_A_temp(1,I) <= '0' WHEN sel_A(0) = '0' ELSE sample(15);
155 155 data_A_temp(2,I) <= data_A_temp(0,I) WHEN sel_A(1) = '0' ELSE data_A_temp(1,I);
156 156 data_A(I) <= data_A_temp(2,I) WHEN OPERATION_reg(14) = '0' ELSE data_B_reg(I);
157 157 END GENERATE all_data_mux_A;
158 158
159 159
160 160
161 161 -----------------------------------------------------------------------------
162 162 -- ALU
163 163 -----------------------------------------------------------------------------
164 164 ALU_OP <= OPERATION_reg(6 DOWNTO 5);
165 165
166 166 ALU: cic_lfr_add_sub
167 167 PORT MAP (
168 168 clk => clk,
169 169 rstn => rstn,
170 170 run => run,
171 171
172 172 OP => ALU_OP,
173 173
174 174 data_in_A => data_A,
175 175 data_in_B => data_B,
176 176 data_in_Carry => data_in_Carry,
177 177
178 178 data_out => data_out,
179 179 data_out_Carry => data_out_Carry);
180 180
181 181 -----------------------------------------------------------------------------
182 182 -- CARRY_MANAGER
183 183 -----------------------------------------------------------------------------
184 184 data_in_Carry <= carry_reg(S_parameter-2) WHEN OPERATION_reg(7) = '0' ELSE carry_reg(S_parameter-1);
185 185
186 186 -- CARRY_PUSH <= OPERATION_reg(7);
187 187 -- CARRY_POP <= OPERATION_reg(6);
188 188
189 189 PROCESS (clk, rstn)
190 190 BEGIN -- PROCESS
191 191 IF rstn = '0' THEN -- asynchronous reset (active low)
192 192 carry_reg <= (OTHERS => '0');
193 193 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
194 194 --IF CARRY_POP = '1' OR CARRY_PUSH = '1' THEN
195 195 carry_reg(S_parameter-1 DOWNTO 1) <= carry_reg(S_parameter-2 DOWNTO 0);
196 196 carry_reg(0) <= data_out_Carry;
197 197 --END IF;
198 198 END IF;
199 199 END PROCESS;
200 200
201 201 -----------------------------------------------------------------------------
202 202 -- MEMORY
203 203 -----------------------------------------------------------------------------
204 204 all_bit_base_ADDR: FOR J IN 8 DOWNTO 0 GENERATE
205 205 all_channel: FOR I IN 7 DOWNTO 0 GENERATE
206 206 base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0';
207 207 END GENERATE all_channel;
208 208 END GENERATE all_bit_base_ADDR;
209 209
210 210
211 211 addr_base_sel <= base_addr_INT(to_integer(UNSIGNED(OPERATION(2 DOWNTO 0))));
212 212
213 213 cic_lfr_address_gen_1: cic_lfr_address_gen
214 214 GENERIC MAP (
215 215 ADDR_SIZE => 9)
216 216 PORT MAP (
217 217 clk => clk,
218 218 rstn => rstn,
219 219 run => run,
220 220
221 221 addr_base => addr_base_sel,
222 222 addr_init => OPERATION(8),
223 223 addr_add_1 => OPERATION(9),
224 224 addr => addr_gen);
225 225
226 226
227 227 addr_read <= addr_gen WHEN OPERATION(12 DOWNTO 10) = "000" ELSE
228 228 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+2,9)) WHEN OPERATION(12 DOWNTO 10) = "001" ELSE
229 229 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+5,9)) WHEN OPERATION(12 DOWNTO 10) = "010" ELSE
230 230 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+8,9)) WHEN OPERATION(12 DOWNTO 10) = "011" ELSE
231 231 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen ))+6,9)) WHEN OPERATION(12 DOWNTO 10) = "100" ELSE
232 232 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen ))+15,9));
233 233
234 234 PROCESS (clk, rstn)
235 235 BEGIN -- PROCESS
236 236 IF rstn = '0' THEN -- asynchronous reset (active low)
237 237 addr_write <= (OTHERS => '0');
238 238 data_we <= '0';
239 239 addr_write_s <= (OTHERS => '0');
240 240 data_we_s <= '0';
241 241 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
242 242 addr_write_s <= addr_read;
243 243 data_we_s <= OPERATION(13);
244 244 IF OPERATION_reg(15) = '0' THEN
245 245 addr_write <= addr_write_s;
246 246 ELSE
247 247 addr_write <= addr_read;
248 248 END IF;
249 249 data_we <= data_we_s;
250 250 END IF;
251 251 END PROCESS;
252 252
253 253 memCEL : IF use_RAM_nCEL = 0 GENERATE
254 254 data_wen <= NOT data_we;
255 255 RAMblk : RAM_CEL
256 256 GENERIC MAP(16, 9)
257 257 PORT MAP(
258 258 WD => data_out,
259 259 RD => data_B,
260 260 WEN => data_wen,
261 261 REN => '0',
262 262 WADDR => addr_write,
263 263 RADDR => addr_read,
264 264 RWCLK => clk,
265 265 RESET => rstn
266 266 ) ;
267 267 END GENERATE;
268 268
269 269 memRAM : IF use_RAM_nCEL = 1 GENERATE
270 270 SRAM : syncram_2p
271 271 GENERIC MAP(tech, 9, 16)
272 272 PORT MAP(clk, '1', addr_read, data_B,
273 273 clk, data_we, addr_write, data_out);
274 274 END GENERATE;
275 275
276 276 -----------------------------------------------------------------------------
277 277 -- CONTROL
278 278 -----------------------------------------------------------------------------
279 279 cic_lfr_control_1: cic_lfr_control_r2
280 280 PORT MAP (
281 281 clk => clk,
282 282 rstn => rstn,
283 run => run,
283 -- run => run,
284 284 data_in_valid => data_in_valid,
285 285 data_out_16_valid => data_out_16_valid_s,
286 286 data_out_256_valid => data_out_256_valid_s,
287 287 OPERATION => OPERATION);
288 288
289 289 -----------------------------------------------------------------------------
290 290 PROCESS (clk, rstn)
291 291 BEGIN -- PROCESS
292 292 IF rstn = '0' THEN -- asynchronous reset (active low)
293 293 data_out_16_valid_s1 <= '0';
294 294 data_out_256_valid_s1 <= '0';
295 295 data_out_16_valid_s2 <= '0';
296 296 data_out_256_valid_s2 <= '0';
297 297 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
298 298 data_out_16_valid_s1 <= data_out_16_valid_s;
299 299 data_out_256_valid_s1 <= data_out_256_valid_s;
300 300 data_out_16_valid_s2 <= data_out_16_valid_s1;
301 301 data_out_256_valid_s2 <= data_out_256_valid_s1;
302 302 END IF;
303 303 END PROCESS;
304 304
305 305 PROCESS (clk, rstn)
306 306 BEGIN -- PROCESS
307 307 IF rstn = '0' THEN -- asynchronous reset (active low)
308 308 sample_valid_reg16 <= "00000" & "000000" & "000001";
309 309 sample_valid_reg256 <= '0' & "000000" & "000000" & "000001";
310 310 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
311 311 IF run = '0' THEN
312 312 sample_valid_reg16 <= "00000" & "000000" & "000001";
313 313 sample_valid_reg256 <= '0' & "000000" & "000000" & "000001";
314 314 ELSE
315 315 IF data_out_16_valid_s2 = '1' OR sample_valid_reg16(8*2) = '1' THEN
316 316 sample_valid_reg16 <= sample_valid_reg16(8*2-1 DOWNTO 0) & sample_valid_reg16(8*2);
317 317 END IF;
318 318 IF data_out_256_valid_s2 = '1' OR sample_valid_reg256(6*3) = '1' THEN
319 319 sample_valid_reg256 <= sample_valid_reg256(6*3-1 DOWNTO 0) & sample_valid_reg256(6*3);
320 320 END IF;
321 321 END IF;
322 322 END IF;
323 323 END PROCESS;
324 324
325 325 data_out_16_valid <= sample_valid_reg16(8*2);
326 326 data_out_256_valid <= sample_valid_reg256(6*3);
327 327
328 328 -----------------------------------------------------------------------------
329 329
330 330 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
331 331 all_channel_out16: FOR I IN 8*2-1 DOWNTO 0 GENERATE
332 332 PROCESS (clk, rstn)
333 333 BEGIN -- PROCESS
334 334 IF rstn = '0' THEN -- asynchronous reset (active low)
335 335 sample_out_reg16(I,J) <= '0';
336 336 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
337 337 IF run = '0' THEN
338 338 sample_out_reg16(I,J) <= '0';
339 339 ELSE
340 340 IF sample_valid_reg16(I) = '1' AND data_out_16_valid_s2 = '1' THEN
341 341 sample_out_reg16(I,J) <= data_out(J);
342 342 END IF;
343 343 END IF;
344 344 END IF;
345 345 END PROCESS;
346 346 END GENERATE all_channel_out16;
347 347
348 348 all_channel_out256: FOR I IN 6*3-1 DOWNTO 0 GENERATE
349 349 PROCESS (clk, rstn)
350 350 BEGIN -- PROCESS
351 351 IF rstn = '0' THEN -- asynchronous reset (active low)
352 352 sample_out_reg256(I,J) <= '0';
353 353 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
354 354 IF run = '0' THEN
355 355 sample_out_reg256(I,J) <= '0';
356 356 ELSE
357 357 IF sample_valid_reg256(I) = '1' AND data_out_256_valid_s2 = '1' THEN
358 358 sample_out_reg256(I,J) <= data_out(J);
359 359 END IF;
360 360 END IF;
361 361 END IF;
362 362 END PROCESS;
363 363 END GENERATE all_channel_out256;
364 364 END GENERATE all_bits;
365 365
366 366
367 367 all_bits_16: FOR J IN 15 DOWNTO 0 GENERATE
368 368 all_reg_16: FOR K IN 1 DOWNTO 0 GENERATE
369 369 sample_out_reg16_s(0,J+(K*16)) <= sample_out_reg16(2*0+K,J);
370 370 sample_out_reg16_s(1,J+(K*16)) <= sample_out_reg16(2*1+K,J) WHEN param_r2 = '1' ELSE sample_out_reg16(2*6+K,J);
371 371 sample_out_reg16_s(2,J+(K*16)) <= sample_out_reg16(2*2+K,J) WHEN param_r2 = '1' ELSE sample_out_reg16(2*7+K,J);
372 372 sample_out_reg16_s(3,J+(K*16)) <= sample_out_reg16(2*3+K,J);
373 373 sample_out_reg16_s(4,J+(K*16)) <= sample_out_reg16(2*4+K,J);
374 374 sample_out_reg16_s(5,J+(K*16)) <= sample_out_reg16(2*5+K,J);
375 375 END GENERATE all_reg_16;
376 376 END GENERATE all_bits_16;
377 377
378 378 all_channel_out_256: FOR I IN 5 DOWNTO 0 GENERATE
379 379 all_bits_256: FOR J IN 15 DOWNTO 0 GENERATE
380 380 all_reg_256: FOR K IN 2 DOWNTO 0 GENERATE
381 381 sample_out_reg256_s(I,J+(K*16)) <= sample_out_reg256(3*I+K,J);
382 382 END GENERATE all_reg_256;
383 383 END GENERATE all_bits_256;
384 384 END GENERATE all_channel_out_256;
385 385
386 386 all_channel_out_v: FOR I IN 5 DOWNTO 0 GENERATE
387 387 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
388 388 data_out_256(I,J) <= sample_out_reg256_s(I,J+16*2-32+27);
389 389 data_out_16(I,J) <= sample_out_reg16_s (I,J+16 -16+15);
390 390 END GENERATE all_bits;
391 391 END GENERATE all_channel_out_v;
392 392
393 END beh; No newline at end of file
393 END beh;
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@@ -1,177 +1,177
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23
24 24 LIBRARY ieee;
25 25 USE ieee.std_logic_1164.ALL;
26 26
27 27 LIBRARY lpp;
28 28 USE lpp.data_type_pkg.ALL;
29 29
30 30 PACKAGE cic_pkg IS
31 31
32 32 -----------------------------------------------------------------------------
33 33 COMPONENT cic
34 34 GENERIC (
35 35 D_delay_number : INTEGER;
36 36 S_stage_number : INTEGER;
37 37 R_downsampling_decimation_factor : INTEGER;
38 38 b_data_size : INTEGER;
39 39 b_grow : INTEGER);
40 40 PORT (
41 41 clk : IN STD_LOGIC;
42 42 rstn : IN STD_LOGIC;
43 43 run : IN STD_LOGIC;
44 44 data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
45 45 data_in_valid : IN STD_LOGIC;
46 46 data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
47 47 data_out_valid : OUT STD_LOGIC);
48 48 END COMPONENT;
49 49 -----------------------------------------------------------------------------
50 50 COMPONENT cic_integrator
51 51 GENERIC (
52 52 b_data_size : INTEGER);
53 53 PORT (
54 54 clk : IN STD_LOGIC;
55 55 rstn : IN STD_LOGIC;
56 56 run : IN STD_LOGIC;
57 57 data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
58 58 data_in_valid : IN STD_LOGIC;
59 59 data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
60 60 data_out_valid : OUT STD_LOGIC);
61 61 END COMPONENT;
62 62
63 63 COMPONENT cic_downsampler
64 64 GENERIC (
65 65 R_downsampling_decimation_factor : INTEGER;
66 66 b_data_size : INTEGER);
67 67 PORT (
68 68 clk : IN STD_LOGIC;
69 69 rstn : IN STD_LOGIC;
70 70 run : IN STD_LOGIC;
71 71 data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
72 72 data_in_valid : IN STD_LOGIC;
73 73 data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
74 74 data_out_valid : OUT STD_LOGIC);
75 75 END COMPONENT;
76 76
77 77 COMPONENT cic_comb
78 78 GENERIC (
79 79 b_data_size : INTEGER;
80 80 D_delay_number : INTEGER);
81 81 PORT (
82 82 clk : IN STD_LOGIC;
83 83 rstn : IN STD_LOGIC;
84 84 run : IN STD_LOGIC;
85 85 data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
86 86 data_in_valid : IN STD_LOGIC;
87 87 data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
88 88 data_out_valid : OUT STD_LOGIC);
89 89 END COMPONENT;
90 90 -----------------------------------------------------------------------------
91 91
92 92
93 93 -----------------------------------------------------------------------------
94 94 COMPONENT cic_lfr
95 95 GENERIC (
96 96 tech : INTEGER;
97 97 use_RAM_nCEL : INTEGER);
98 98 PORT (
99 99 clk : IN STD_LOGIC;
100 100 rstn : IN STD_LOGIC;
101 101 run : IN STD_LOGIC;
102 102 data_in : IN sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
103 103 data_in_valid : IN STD_LOGIC;
104 104 data_out_16 : OUT sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
105 105 data_out_16_valid : OUT STD_LOGIC;
106 106 data_out_256 : OUT sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
107 107 data_out_256_valid : OUT STD_LOGIC);
108 108 END COMPONENT;
109 109
110 110 COMPONENT cic_lfr_r2
111 111 GENERIC (
112 112 tech : INTEGER;
113 113 use_RAM_nCEL : INTEGER);
114 114 PORT (
115 115 clk : IN STD_LOGIC;
116 116 rstn : IN STD_LOGIC;
117 117 run : IN STD_LOGIC;
118 118 param_r2 : IN STD_LOGIC;
119 119 data_in : IN sample_vector(7 DOWNTO 0, 15 DOWNTO 0);
120 120 data_in_valid : IN STD_LOGIC;
121 121 data_out_16 : OUT sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
122 122 data_out_16_valid : OUT STD_LOGIC;
123 123 data_out_256 : OUT sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
124 124 data_out_256_valid : OUT STD_LOGIC);
125 125 END COMPONENT;
126 126
127 127 COMPONENT cic_lfr_control
128 128 PORT (
129 129 clk : IN STD_LOGIC;
130 130 rstn : IN STD_LOGIC;
131 131 run : IN STD_LOGIC;
132 132 data_in_valid : IN STD_LOGIC;
133 133 data_out_16_valid : OUT STD_LOGIC;
134 134 data_out_256_valid : OUT STD_LOGIC;
135 135 OPERATION : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
136 136 END COMPONENT;
137 137
138 138 COMPONENT cic_lfr_control_r2
139 139 PORT (
140 140 clk : IN STD_LOGIC;
141 141 rstn : IN STD_LOGIC;
142 run : IN STD_LOGIC;
142 -- run : IN STD_LOGIC;
143 143 data_in_valid : IN STD_LOGIC;
144 144 data_out_16_valid : OUT STD_LOGIC;
145 145 data_out_256_valid : OUT STD_LOGIC;
146 146 OPERATION : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
147 147 END COMPONENT;
148 148
149 149 COMPONENT cic_lfr_add_sub
150 150 PORT (
151 151 clk : IN STD_LOGIC;
152 152 rstn : IN STD_LOGIC;
153 153 run : IN STD_LOGIC;
154 154 OP : IN STD_LOGIC_VECTOR( 1 DOWNTO 0);
155 155 data_in_A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
156 156 data_in_B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
157 157 data_in_Carry : IN STD_LOGIC;
158 158 data_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
159 159 data_out_Carry : OUT STD_LOGIC);
160 160 END COMPONENT;
161 161
162 162 COMPONENT cic_lfr_address_gen
163 163 GENERIC (
164 164 ADDR_SIZE : INTEGER);
165 165 PORT (
166 166 clk : IN STD_LOGIC;
167 167 rstn : IN STD_LOGIC;
168 168 run : IN STD_LOGIC;
169 169 addr_base : IN STD_LOGIC_VECTOR(ADDR_SIZE-1 DOWNTO 0);
170 170 addr_init : IN STD_LOGIC;
171 171 addr_add_1 : IN STD_LOGIC;
172 172 addr : OUT STD_LOGIC_VECTOR(ADDR_SIZE-1 DOWNTO 0));
173 173 END COMPONENT;
174 174
175 175
176 176 -----------------------------------------------------------------------------
177 177 END cic_pkg;
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@@ -1,315 +1,315
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more Cdetails.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe PELLION
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22
23 23 LIBRARY IEEE;
24 24 USE IEEE.numeric_std.ALL;
25 25 USE IEEE.std_logic_1164.ALL;
26 26 LIBRARY lpp;
27 27 USE lpp.iir_filter.ALL;
28 28 USE lpp.general_purpose.ALL;
29 29
30 30 ENTITY IIR_CEL_CTRLR_v2_CONTROL IS
31 31 GENERIC (
32 32 Coef_sel_SZ : INTEGER;
33 33 Cels_count : INTEGER := 5;
34 34 ChanelsCount : INTEGER := 1);
35 35 PORT (
36 36 rstn : IN STD_LOGIC;
37 37 clk : IN STD_LOGIC;
38 38
39 39 sample_in_val : IN STD_LOGIC;
40 40 sample_in_rot : OUT STD_LOGIC;
41 41 sample_out_val : OUT STD_LOGIC;
42 42 sample_out_rot : OUT STD_LOGIC;
43 43
44 44 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
45 45 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
46 46 ram_write : OUT STD_LOGIC;
47 47 ram_read : OUT STD_LOGIC;
48 48 raddr_rst : OUT STD_LOGIC;
49 49 raddr_add1 : OUT STD_LOGIC;
50 50 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
51 51 alu_sel_input : OUT STD_LOGIC;
52 52 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
53 53 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
54 54 );
55 55 END IIR_CEL_CTRLR_v2_CONTROL;
56 56
57 57 ARCHITECTURE ar_IIR_CEL_CTRLR_v2_CONTROL OF IIR_CEL_CTRLR_v2_CONTROL IS
58 58
59 59 TYPE fsmIIR_CEL_T IS (waiting,
60 60 first_read,
61 61 compute_b0,
62 62 compute_b1,
63 63 compute_b2,
64 64 compute_a1,
65 65 compute_a2,
66 66 LAST_CEL,
67 67 wait_valid_last_output,
68 68 wait_valid_last_output_2);
69 69 SIGNAL IIR_CEL_STATE : fsmIIR_CEL_T;
70 70
71 SIGNAL alu_selected_coeff : INTEGER;
71 SIGNAL alu_selected_coeff : INTEGER RANGE 0 TO 2**Coef_sel_SZ-1;
72 72 SIGNAL Chanel_ongoing : INTEGER;
73 73 SIGNAL Cel_ongoing : INTEGER;
74 74
75 75 BEGIN
76 76
77 77 alu_sel_coeff <= STD_LOGIC_VECTOR(to_unsigned(alu_selected_coeff, Coef_sel_SZ));
78 78
79 79 PROCESS (clk, rstn)
80 80 BEGIN -- PROCESS
81 81 IF rstn = '0' THEN -- asynchronous reset (active low)
82 82 --REG -------------------------------------------------------------------
83 83 in_sel_src <= (OTHERS => '0'); --
84 84 --RAM_WRitE -------------------------------------------------------------
85 85 ram_sel_Wdata <= "00"; --
86 86 ram_write <= '0'; --
87 87 waddr_previous <= "00"; --
88 88 --RAM_READ --------------------------------------------------------------
89 89 ram_read <= '0'; --
90 90 raddr_rst <= '0'; --
91 91 raddr_add1 <= '0'; --
92 92 --ALU -------------------------------------------------------------------
93 93 alu_selected_coeff <= 0; --
94 94 alu_sel_input <= '0'; --
95 95 alu_ctrl <= ctrl_IDLE; --
96 96 --OUT
97 97 sample_out_val <= '0'; --
98 98 sample_out_rot <= '0'; --
99 99
100 100 Chanel_ongoing <= 0; --
101 101 Cel_ongoing <= 0; --
102 102 sample_in_rot <= '0';
103 103
104 104 IIR_CEL_STATE <= waiting;
105 105
106 106 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
107 107
108 108 CASE IIR_CEL_STATE IS
109 109 WHEN waiting =>
110 110 sample_out_rot <= '0';
111 111 sample_in_rot <= '0';
112 112 sample_out_val <= '0';
113 113 alu_ctrl <= ctrl_CLRMAC;
114 114 alu_selected_coeff <= 0;
115 115 in_sel_src <= "01";
116 116 ram_read <= '0';
117 117 ram_sel_Wdata <= "00";
118 118 ram_write <= '0';
119 119 waddr_previous <= "00";
120 120 IF sample_in_val = '1' THEN
121 121 raddr_rst <= '0';
122 122 alu_sel_input <= '1';
123 123 ram_read <= '1';
124 124 raddr_add1 <= '1';
125 125 IIR_CEL_STATE <= first_read;
126 126 Chanel_ongoing <= Chanel_ongoing + 1;
127 127 Cel_ongoing <= 1;
128 128 ELSE
129 129 raddr_add1 <= '0';
130 130 raddr_rst <= '1';
131 131 Chanel_ongoing <= 0;
132 132 Cel_ongoing <= 0;
133 133 END IF;
134 134
135 135 WHEN first_read =>
136 136 IIR_CEL_STATE <= compute_b2;
137 137 ram_read <= '1';
138 138 raddr_add1 <= '1';
139 139 alu_ctrl <= ctrl_MULT;
140 140 alu_sel_input <= '1';
141 141 in_sel_src <= "01";
142 142
143 143
144 144 WHEN compute_b2 =>
145 145 sample_out_rot <= '0';
146 146
147 147 sample_in_rot <= '0';
148 148 sample_out_val <= '0';
149 149
150 150 alu_sel_input <= '1';
151 151 --
152 152 ram_sel_Wdata <= "10";
153 153 ram_write <= '1';
154 154 waddr_previous <= "10";
155 155 --
156 156 ram_read <= '1';
157 157 raddr_rst <= '0';
158 158 raddr_add1 <= '0';
159 159 IF Cel_ongoing = 1 THEN
160 160 in_sel_src <= "00";
161 161 ELSE
162 162 in_sel_src <= "11";
163 163 END IF;
164 164 alu_selected_coeff <= alu_selected_coeff+1;
165 165 alu_ctrl <= ctrl_MAC;
166 166 IIR_CEL_STATE <= compute_b1;
167 167
168 168 WHEN compute_b1 =>
169 169 sample_in_rot <= '0';
170 170 alu_sel_input <= '0';
171 171 --
172 172 ram_sel_Wdata <= "00";
173 173 ram_write <= '1';
174 174 waddr_previous <= "01";
175 175 --
176 176 ram_read <= '1';
177 177 raddr_rst <= '0';
178 178 raddr_add1 <= '1';
179 179 sample_out_rot <= '0';
180 180 IF Cel_ongoing = 1 THEN
181 181 in_sel_src <= "10";
182 182 sample_out_val <= '0';
183 183 ELSE
184 184 sample_out_val <= '0';
185 185 in_sel_src <= "00";
186 186 END IF;
187 187 alu_selected_coeff <= alu_selected_coeff+1;
188 188 alu_ctrl <= ctrl_MAC;
189 189 IIR_CEL_STATE <= compute_b0;
190 190
191 191 WHEN compute_b0 =>
192 192 sample_out_rot <= '0';
193 193 sample_out_val <= '0';
194 194 sample_in_rot <= '0';
195 195 alu_sel_input <= '1';
196 196 ram_sel_Wdata <= "00";
197 197 ram_write <= '0';
198 198 waddr_previous <= "01";
199 199 ram_read <= '1';
200 200 raddr_rst <= '0';
201 201 raddr_add1 <= '0';
202 202 in_sel_src <= "10";
203 203 alu_selected_coeff <= alu_selected_coeff+1;
204 204 alu_ctrl <= ctrl_MAC;
205 205 IIR_CEL_STATE <= compute_a2;
206 206 IF Cel_ongoing = Cels_count THEN
207 207 sample_in_rot <= '1';
208 208 ELSE
209 209 sample_in_rot <= '0';
210 210 END IF;
211 211
212 212 WHEN compute_a2 =>
213 213 sample_out_val <= '0';
214 214 sample_out_rot <= '0';
215 215 alu_sel_input <= '1';
216 216 ram_sel_Wdata <= "00";
217 217 ram_write <= '0';
218 218 waddr_previous <= "01";
219 219 ram_read <= '1';
220 220 raddr_rst <= '0';
221 221 IF Cel_ongoing = Cels_count THEN
222 222 raddr_add1 <= '1';
223 223 ELSE
224 224 raddr_add1 <= '0';
225 225 END IF;
226 226 in_sel_src <= "00";
227 227 alu_selected_coeff <= alu_selected_coeff+1;
228 228 alu_ctrl <= ctrl_MAC;
229 229 IIR_CEL_STATE <= compute_a1;
230 230 sample_in_rot <= '0';
231 231
232 232 WHEN compute_a1 =>
233 233 sample_out_val <= '0';
234 234 sample_out_rot <= '0';
235 235 alu_sel_input <= '0';
236 236 ram_sel_Wdata <= "00";
237 237 ram_write <= '0';
238 238 waddr_previous <= "01";
239 239 ram_read <= '1';
240 240 raddr_rst <= '0';
241 241 alu_ctrl <= ctrl_MULT;
242 242 sample_in_rot <= '0';
243 243 IF Cel_ongoing = Cels_count THEN
244 244 alu_selected_coeff <= 0;
245 245
246 246 ram_sel_Wdata <= "10";
247 247 raddr_add1 <= '1';
248 248 ram_write <= '1';
249 249 waddr_previous <= "10";
250 250
251 251 IF Chanel_ongoing = ChanelsCount THEN
252 252 IIR_CEL_STATE <= wait_valid_last_output;
253 253 ELSE
254 254 Chanel_ongoing <= Chanel_ongoing + 1;
255 255 Cel_ongoing <= 1;
256 256 IIR_CEL_STATE <= LAST_CEL;
257 257 in_sel_src <= "01";
258 258 END IF;
259 259 ELSE
260 260 raddr_add1 <= '1';
261 261 alu_selected_coeff <= alu_selected_coeff+1;
262 262 Cel_ongoing <= Cel_ongoing+1;
263 263 IIR_CEL_STATE <= compute_b2;
264 264 END IF;
265 265
266 266 WHEN LAST_CEL =>
267 267 alu_sel_input <= '1';
268 268 IIR_CEL_STATE <= compute_b2;
269 269 raddr_add1 <= '1';
270 270 ram_sel_Wdata <= "01";
271 271 ram_write <= '1';
272 272 waddr_previous <= "10";
273 273 sample_out_rot <= '1';
274 274
275 275
276 276 WHEN wait_valid_last_output =>
277 277 IIR_CEL_STATE <= wait_valid_last_output_2;
278 278 sample_in_rot <= '0';
279 279 alu_ctrl <= ctrl_IDLE;
280 280 alu_selected_coeff <= 0;
281 281 in_sel_src <= "01";
282 282 ram_read <= '0';
283 283 raddr_rst <= '1';
284 284 raddr_add1 <= '1';
285 285 ram_sel_Wdata <= "01";
286 286 ram_write <= '1';
287 287 waddr_previous <= "10";
288 288 Chanel_ongoing <= 0;
289 289 Cel_ongoing <= 0;
290 290 sample_out_val <= '0';
291 291 sample_out_rot <= '1';
292 292
293 293 WHEN wait_valid_last_output_2 =>
294 294 IIR_CEL_STATE <= waiting;
295 295 sample_in_rot <= '0';
296 296 alu_ctrl <= ctrl_IDLE;
297 297 alu_selected_coeff <= 0;
298 298 in_sel_src <= "01";
299 299 ram_read <= '0';
300 300 raddr_rst <= '1';
301 301 raddr_add1 <= '1';
302 302 ram_sel_Wdata <= "10";
303 303 ram_write <= '1';
304 304 waddr_previous <= "10";
305 305 Chanel_ongoing <= 0;
306 306 Cel_ongoing <= 0;
307 307 sample_out_val <= '1';
308 308 sample_out_rot <= '0';
309 309 WHEN OTHERS => NULL;
310 310 END CASE;
311 311
312 312 END IF;
313 313 END PROCESS;
314 314
315 315 END ar_IIR_CEL_CTRLR_v2_CONTROL; No newline at end of file
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@@ -1,77 +1,77
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe PELLION
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.STD_LOGIC_1164.ALL;
24 24 USE IEEE.std_logic_arith.ALL;
25 25 LIBRARY lpp;
26 26 use lpp.iir_filter.all;
27 27
28 28 ENTITY Downsampling IS
29 29
30 30 GENERIC (
31 31 ChanelCount : INTEGER;
32 32 SampleSize : INTEGER;
33 33 DivideParam : INTEGER );
34 34 PORT (
35 35 clk : IN STD_LOGIC;
36 36 rstn : IN STD_LOGIC;
37 37 sample_in_val : IN STD_LOGIC;
38 38 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
39 39 sample_out_val : OUT STD_LOGIC;
40 40 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)
41 41 );
42 42
43 43 END Downsampling;
44 44
45 45 ARCHITECTURE beh OF Downsampling IS
46 46
47 SIGNAL counter : INTEGER;
47 SIGNAL counter : INTEGER RANGE 0 TO DivideParam-1;
48 48
49 49 BEGIN -- beh
50 50
51 51 PROCESS (clk, rstn)
52 52 BEGIN -- PROCESS
53 53 IF rstn = '0' THEN -- asynchronous reset (active low)
54 54 counter <= 0;
55 55 sample_out_val <= '0';
56 56 all_sampl: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
57 57 all_bit: FOR J IN SampleSize-1 DOWNTO 0 LOOP
58 58 sample_out(I,J) <= '0';
59 59 END LOOP all_bit;
60 60 END LOOP all_sampl;
61 61 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
62 62 IF sample_in_val = '1' THEN
63 63 IF counter = 0 THEN
64 64 counter <= DivideParam-1;
65 65 sample_out_val <= '1';
66 66 sample_out <= sample_in;
67 67 ELSE
68 68 counter <= counter-1;
69 69 sample_out_val <= '0';
70 70 END IF;
71 71 ELSE
72 72 sample_out_val <= '0';
73 73 END IF;
74 74 END IF;
75 75 END PROCESS;
76 76
77 77 END beh; No newline at end of file
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@@ -1,524 +1,525
1 1 ----------------------------------------------------------------------------------
2 2 -- Company:
3 3 -- Engineer:
4 4 --
5 5 -- Create Date: 11:17:05 07/02/2012
6 6 -- Design Name:
7 7 -- Module Name: apb_lfr_time_management - Behavioral
8 8 -- Project Name:
9 9 -- Target Devices:
10 10 -- Tool versions:
11 11 -- Description:
12 12 --
13 13 -- Dependencies:
14 14 --
15 15 -- Revision:
16 16 -- Revision 0.01 - File Created
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 20 LIBRARY IEEE;
21 21 USE IEEE.STD_LOGIC_1164.ALL;
22 22 USE IEEE.NUMERIC_STD.ALL;
23 23 LIBRARY grlib;
24 24 USE grlib.amba.ALL;
25 25 USE grlib.stdlib.ALL;
26 26 USE grlib.devices.ALL;
27 27 LIBRARY lpp;
28 28 USE lpp.apb_devices_list.ALL;
29 29 USE lpp.general_purpose.ALL;
30 30 USE lpp.lpp_lfr_management.ALL;
31 31 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
32 32 USE lpp.lpp_cna.ALL;
33 33 LIBRARY techmap;
34 34 USE techmap.gencomp.ALL;
35 35
36 36
37 37 ENTITY apb_lfr_management IS
38 38
39 39 GENERIC(
40 40 tech : INTEGER := 0;
41 41 pindex : INTEGER := 0; --! APB slave index
42 42 paddr : INTEGER := 0; --! ADDR field of the APB BAR
43 43 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
44 44 -- FIRST_DIVISION : INTEGER := 374;
45 45 NB_SECOND_DESYNC : INTEGER := 60
46 46 );
47 47
48 48 PORT (
49 49 clk25MHz : IN STD_LOGIC; --! Clock
50 50 resetn_25MHz : IN STD_LOGIC; --! Reset
51 51 -- clk24_576MHz : IN STD_LOGIC; --! secondary clock
52 52 -- resetn_24_576MHz : IN STD_LOGIC; --! Reset
53 53
54 54 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
55 55
56 56 apbi : IN apb_slv_in_type; --! APB slave input signals
57 57 apbo : OUT apb_slv_out_type; --! APB slave output signals
58 58 ---------------------------------------------------------------------------
59 59 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
60 60 HK_val : IN STD_LOGIC;
61 61 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
62 62 ---------------------------------------------------------------------------
63 63 DAC_SDO : OUT STD_LOGIC;
64 64 DAC_SCK : OUT STD_LOGIC;
65 65 DAC_SYNC : OUT STD_LOGIC;
66 66 DAC_CAL_EN : OUT STD_LOGIC;
67 67 ---------------------------------------------------------------------------
68 68 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
69 69 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
70 70 ---------------------------------------------------------------------------
71 71 LFR_soft_rstn : OUT STD_LOGIC
72 72 );
73 73
74 74 END apb_lfr_management;
75 75
76 76 ARCHITECTURE Behavioral OF apb_lfr_management IS
77 77
78 78 CONSTANT REVISION : INTEGER := 1;
79 79 CONSTANT pconfig : apb_config_type := (
80 80 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR_MANAGEMENT, 0, REVISION, 0),
81 81 1 => apb_iobar(paddr, pmask)
82 82 );
83 83
84 84 TYPE apb_lfr_time_management_Reg IS RECORD
85 85 ctrl : STD_LOGIC;
86 86 soft_reset : STD_LOGIC;
87 87 coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0);
88 88 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
89 89 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
90 90 LFR_soft_reset : STD_LOGIC;
91 91 HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
92 92 HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
93 93 HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
94 94 END RECORD;
95 95 SIGNAL r : apb_lfr_time_management_Reg;
96 96
97 97 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 98 SIGNAL force_tick : STD_LOGIC;
99 99 SIGNAL previous_force_tick : STD_LOGIC;
100 100 SIGNAL soft_tick : STD_LOGIC;
101 101
102 102 SIGNAL coarsetime_reg_updated : STD_LOGIC;
103 103 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0);
104 104
105 105 --SIGNAL coarse_time_new : STD_LOGIC;
106 106 SIGNAL coarse_time_new_49 : STD_LOGIC;
107 107 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 108 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 109
110 110 --SIGNAL fine_time_new : STD_LOGIC;
111 111 --SIGNAL fine_time_new_temp : STD_LOGIC;
112 112 SIGNAL fine_time_new_49 : STD_LOGIC;
113 113 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
114 114 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
115 115 SIGNAL tick : STD_LOGIC;
116 116 SIGNAL new_timecode : STD_LOGIC;
117 117 SIGNAL new_coarsetime : STD_LOGIC;
118 118
119 119 SIGNAL time_new_49 : STD_LOGIC;
120 120 SIGNAL time_new : STD_LOGIC;
121 121
122 122 -----------------------------------------------------------------------------
123 123 SIGNAL force_reset : STD_LOGIC;
124 124 SIGNAL previous_force_reset : STD_LOGIC;
125 125 SIGNAL soft_reset : STD_LOGIC;
126 SIGNAL soft_reset_sync : STD_LOGIC;
126
127 127 -----------------------------------------------------------------------------
128 128 SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 129
130 130 SIGNAL previous_fine_time_bit : STD_LOGIC;
131 131
132 132 SIGNAL rstn_LFR_TM : STD_LOGIC;
133 133
134 134 -----------------------------------------------------------------------------
135 135 -- DAC
136 136 -----------------------------------------------------------------------------
137 137 CONSTANT PRESZ : INTEGER := 8;
138 138 CONSTANT CPTSZ : INTEGER := 16;
139 139 CONSTANT datawidth : INTEGER := 18;
140 140 CONSTANT dacresolution : INTEGER := 12;
141 141 CONSTANT abits : INTEGER := 8;
142 142
143 143 SIGNAL pre : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
144 144 SIGNAL N : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
145 145 SIGNAL Reload : STD_LOGIC;
146 146 SIGNAL DATA_IN : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
147 147 SIGNAL WEN : STD_LOGIC;
148 148 SIGNAL LOAD_ADDRESSN : STD_LOGIC;
149 149 SIGNAL ADDRESS_IN : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
150 150 SIGNAL ADDRESS_OUT : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
151 151 SIGNAL INTERLEAVED : STD_LOGIC;
152 152 SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0);
153 153 SIGNAL DAC_CAL_EN_s : STD_LOGIC;
154 154
155 155 BEGIN
156 156
157 157 LFR_soft_rstn <= NOT r.LFR_soft_reset;
158 158
159 159 PROCESS(resetn_25MHz, clk25MHz)
160 160 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
161 161 BEGIN
162 162
163 163 IF resetn_25MHz = '0' THEN
164 164 Rdata <= (OTHERS => '0');
165 165 r.coarse_time_load <= (OTHERS => '0');
166 166 r.soft_reset <= '0';
167 167 r.ctrl <= '0';
168 168 r.LFR_soft_reset <= '1';
169 169
170 170 force_tick <= '0';
171 171 previous_force_tick <= '0';
172 172 soft_tick <= '0';
173 173
174 174 coarsetime_reg_updated <= '0';
175 175 --DAC
176 176 pre <= (OTHERS => '1');
177 177 N <= (OTHERS => '1');
178 178 Reload <= '1';
179 179 DATA_IN <= (OTHERS => '0');
180 180 WEN <= '1';
181 181 LOAD_ADDRESSN <= '1';
182 182 ADDRESS_IN <= (OTHERS => '1');
183 183 INTERLEAVED <= '0';
184 184 DAC_CFG <= (OTHERS => '0');
185 185 --
186 186 DAC_CAL_EN_s <= '0';
187 187 force_reset <= '0';
188 188 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
189 189 coarsetime_reg_updated <= '0';
190 190
191 191 force_tick <= r.ctrl;
192 192 previous_force_tick <= force_tick;
193 193 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
194 194 soft_tick <= '1';
195 195 ELSE
196 196 soft_tick <= '0';
197 197 END IF;
198 198
199 199 force_reset <= r.soft_reset;
200 200 previous_force_reset <= force_reset;
201 201 IF (previous_force_reset = '0') AND (force_reset = '1') THEN
202 202 soft_reset <= '1';
203 203 ELSE
204 204 soft_reset <= '0';
205 205 END IF;
206 206
207 207 paddr := "000000";
208 208 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
209 209 Rdata <= (OTHERS => '0');
210 210
211 211 LOAD_ADDRESSN <= '1';
212 212 WEN <= '1';
213 213
214 214 IF apbi.psel(pindex) = '1' THEN
215 215 --APB READ OP
216 216 CASE paddr(7 DOWNTO 2) IS
217 217 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
218 218 Rdata(0) <= r.ctrl;
219 219 Rdata(1) <= r.soft_reset;
220 220 Rdata(2) <= r.LFR_soft_reset;
221 221 Rdata(31 DOWNTO 3) <= (OTHERS => '0');
222 222 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
223 223 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
224 224 WHEN ADDR_LFR_MANAGMENT_TIME_COARSE =>
225 225 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
226 226 WHEN ADDR_LFR_MANAGMENT_TIME_FINE =>
227 227 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
228 228 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
229 229 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 =>
230 230 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
231 231 Rdata(15 DOWNTO 0) <= r.HK_temp_0;
232 232 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 =>
233 233 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
234 234 Rdata(15 DOWNTO 0) <= r.HK_temp_1;
235 235 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
236 236 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
237 237 Rdata(15 DOWNTO 0) <= r.HK_temp_2;
238 238 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
239 239 Rdata(3 DOWNTO 0) <= DAC_CFG;
240 240 Rdata(4) <= Reload;
241 241 Rdata(5) <= INTERLEAVED;
242 242 Rdata(6) <= DAC_CAL_EN_s;
243 243 Rdata(31 DOWNTO 7) <= (OTHERS => '0');
244 244 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
245 245 Rdata(PRESZ-1 DOWNTO 0) <= pre;
246 246 Rdata(31 DOWNTO PRESZ) <= (OTHERS => '0');
247 247 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
248 248 Rdata(CPTSZ-1 DOWNTO 0) <= N;
249 249 Rdata(31 DOWNTO CPTSZ) <= (OTHERS => '0');
250 250 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
251 251 Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT;
252 252 Rdata(31 DOWNTO abits) <= (OTHERS => '0');
253 253 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
254 254 Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
255 255 Rdata(31 DOWNTO datawidth) <= (OTHERS => '0');
256 256 WHEN OTHERS =>
257 257 Rdata(31 DOWNTO 0) <= (OTHERS => '0');
258 258 END CASE;
259 259
260 260 --APB Write OP
261 261 IF (apbi.pwrite AND apbi.penable) = '1' THEN
262 262 CASE paddr(7 DOWNTO 2) IS
263 263 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
264 264 r.ctrl <= apbi.pwdata(0);
265 265 r.soft_reset <= apbi.pwdata(1);
266 266 r.LFR_soft_reset <= apbi.pwdata(2);
267 267 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
268 268 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
269 269 coarsetime_reg_updated <= '1';
270 270 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
271 271 DAC_CFG <= apbi.pwdata(3 DOWNTO 0);
272 272 Reload <= apbi.pwdata(4);
273 273 INTERLEAVED <= apbi.pwdata(5);
274 274 DAC_CAL_EN_s <= apbi.pwdata(6);
275 275 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
276 276 pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
277 277 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
278 278 N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
279 279 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
280 280 ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0);
281 281 LOAD_ADDRESSN <= '0';
282 282 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
283 283 DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
284 284 WEN <= '0';
285 285
286 286 WHEN OTHERS =>
287 287 NULL;
288 288 END CASE;
289 289 ELSE
290 290 IF r.ctrl = '1' THEN
291 291 r.ctrl <= '0';
292 292 END IF;
293 293 IF r.soft_reset = '1' THEN
294 294 r.soft_reset <= '0';
295 295 END IF;
296 296 END IF;
297 297
298 298 END IF;
299 299
300 300 END IF;
301 301 END PROCESS;
302 302
303 303 apbo.pirq <= (OTHERS => '0');
304 304 apbo.prdata <= Rdata;
305 305 apbo.pconfig <= pconfig;
306 306 apbo.pindex <= pindex;
307 307
308 308
309 309
310 310
311 311
312 312
313 313
314 314
315 315
316 316
317 317
318 318
319 319
320 320
321 321 -----------------------------------------------------------------------------
322 322 -- IN
323 323 coarse_time <= r.coarse_time;
324 324 fine_time <= r.fine_time;
325 325 coarsetime_reg <= r.coarse_time_load;
326 326 -----------------------------------------------------------------------------
327 327
328 328 -----------------------------------------------------------------------------
329 329 -- OUT
330 330 r.coarse_time <= coarse_time_s;
331 331 r.fine_time <= fine_time_s;
332 332 -----------------------------------------------------------------------------
333 333
334 334 -----------------------------------------------------------------------------
335 335 tick <= grspw_tick OR soft_tick;
336 336
337 337 --SYNC_VALID_BIT_1 : SYNC_VALID_BIT
338 338 -- GENERIC MAP (
339 339 -- NB_FF_OF_SYNC => 2)
340 340 -- PORT MAP (
341 341 -- clk_in => clk25MHz,
342 342 -- rstn_in => resetn_25MHz,
343 343 -- clk_out => clk24_576MHz,
344 344 -- rstn_out => resetn_24_576MHz,
345 345 -- sin => tick,
346 346 -- sout => new_timecode);
347 347 new_timecode <= tick;
348 348
349 349 --SYNC_VALID_BIT_2 : SYNC_VALID_BIT
350 350 -- GENERIC MAP (
351 351 -- NB_FF_OF_SYNC => 2)
352 352 -- PORT MAP (
353 353 -- clk_in => clk25MHz,
354 354 -- rstn_in => resetn_25MHz,
355 355 -- clk_out => clk24_576MHz,
356 356 -- rstn_out => resetn_24_576MHz,
357 357 -- sin => coarsetime_reg_updated,
358 358 -- sout => new_coarsetime);
359 359
360 360 new_coarsetime <= coarsetime_reg_updated;
361 361
362 362 --SYNC_VALID_BIT_3 : SYNC_VALID_BIT
363 363 -- GENERIC MAP (
364 364 -- NB_FF_OF_SYNC => 2)
365 365 -- PORT MAP (
366 366 -- clk_in => clk25MHz,
367 367 -- rstn_in => resetn_25MHz,
368 368 -- clk_out => clk24_576MHz,
369 369 -- rstn_out => resetn_24_576MHz,
370 370 -- sin => soft_reset,
371 371 -- sout => soft_reset_sync);
372 372
373 373
374 374 -----------------------------------------------------------------------------
375 375 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
376 376
377 377 --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
378 378 -- GENERIC MAP (
379 379 -- NB_FF_OF_SYNC => 2)
380 380 -- PORT MAP (
381 381 -- clk_in => clk24_576MHz,
382 382 -- rstn_in => resetn_24_576MHz,
383 383 -- clk_out => clk25MHz,
384 384 -- rstn_out => resetn_25MHz,
385 385 -- sin => time_new_49,
386 386 -- sout => time_new);
387 387
388 388 time_new <= time_new_49;
389 389
390 390 --PROCESS (clk25MHz, resetn_25MHz)
391 391 --BEGIN -- PROCESS
392 392 -- IF resetn_25MHz = '0' THEN -- asynchronous reset (active low)
393 393 -- fine_time_s <= (OTHERS => '0');
394 394 -- coarse_time_s <= (OTHERS => '0');
395 395 -- ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
396 396 -- IF time_new = '1' THEN
397 397 -- END IF;
398 398 -- END IF;
399 399 --END PROCESS;
400 400
401 401 fine_time_s <= fine_time_49;
402 402 coarse_time_s <= coarse_time_49;
403 403
404 404
405 405 rstn_LFR_TM <= '0' WHEN resetn_25MHz = '0' ELSE
406 406 '0' WHEN soft_reset = '1' ELSE
407 407 '1';
408 408
409 409 -----------------------------------------------------------------------------
410 410 -- LFR_TIME_MANAGMENT
411 411 -----------------------------------------------------------------------------
412 412 lfr_time_management_1 : lfr_time_management
413 413 GENERIC MAP (
414 414 --FIRST_DIVISION => FIRST_DIVISION,
415 415 NB_SECOND_DESYNC => NB_SECOND_DESYNC)
416 416 PORT MAP (
417 417 clk => clk25MHz,
418 418 rstn => rstn_LFR_TM,
419 419
420 420 tick => new_timecode,
421 421 new_coarsetime => new_coarsetime,
422 422 coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
423 423
424 424 fine_time => fine_time_49,
425 425 fine_time_new => fine_time_new_49,
426 426 coarse_time => coarse_time_49,
427 427 coarse_time_new => coarse_time_new_49);
428 428
429 429
430 430
431 431 -----------------------------------------------------------------------------
432 432 -- HK
433 433 -----------------------------------------------------------------------------
434 434
435 435 PROCESS (clk25MHz, resetn_25MHz)
436 436 CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14; -- freq = 2^(16-BIT)
437 437 -- for each HK, the update frequency is freq/3
438 438 --
439 439 -- for 14, the update frequency is
440 440 -- 4Hz and update for each
441 441 -- HK is 1.33Hz
442 442 BEGIN -- PROCESS
443 443 IF resetn_25MHz = '0' THEN -- asynchronous reset (active low)
444 444
445 445 r.HK_temp_0 <= (OTHERS => '0');
446 446 r.HK_temp_1 <= (OTHERS => '0');
447 447 r.HK_temp_2 <= (OTHERS => '0');
448 448
449 449 HK_sel_s <= "00";
450 450
451 451 previous_fine_time_bit <= '0';
452 452
453 453 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
454 454
455 455 IF HK_val = '1' THEN
456 456 IF previous_fine_time_bit = NOT(fine_time_s(BIT_FREQUENCY_UPDATE)) THEN
457 457 previous_fine_time_bit <= fine_time_s(BIT_FREQUENCY_UPDATE);
458 458 CASE HK_sel_s IS
459 459 WHEN "00" =>
460 460 r.HK_temp_0 <= HK_sample;
461 461 HK_sel_s <= "01";
462 462 WHEN "01" =>
463 463 r.HK_temp_1 <= HK_sample;
464 464 HK_sel_s <= "10";
465 465 WHEN "10" =>
466 466 r.HK_temp_2 <= HK_sample;
467 467 HK_sel_s <= "00";
468 468 WHEN OTHERS => NULL;
469 469 END CASE;
470 470 END IF;
471 471 END IF;
472 472
473 473 END IF;
474 474 END PROCESS;
475 475
476 476 HK_sel <= HK_sel_s;
477 477
478 478
479 479
480 480
481 481
482 482
483 483
484 484
485 485
486 486
487 487
488 488
489 489
490 490
491 491 -----------------------------------------------------------------------------
492 492 -- DAC
493 493 -----------------------------------------------------------------------------
494 494 cal : lfr_cal_driver
495 495 GENERIC MAP(
496 496 tech => tech,
497 497 PRESZ => PRESZ,
498 498 CPTSZ => CPTSZ,
499 499 datawidth => datawidth,
500 500 abits => abits
501 501 )
502 502 PORT MAP(
503 503 clk => clk25MHz,
504 504 rstn => resetn_25MHz,
505 505
506 506 pre => pre,
507 507 N => N,
508 508 Reload => Reload,
509 509 DATA_IN => DATA_IN,
510 510 WEN => WEN,
511 511 LOAD_ADDRESSN => LOAD_ADDRESSN,
512 512 ADDRESS_IN => ADDRESS_IN,
513 513 ADDRESS_OUT => ADDRESS_OUT,
514 514 INTERLEAVED => INTERLEAVED,
515 515 DAC_CFG => DAC_CFG,
516 516
517 517 SYNC => DAC_SYNC,
518 518 DOUT => DAC_SDO,
519 519 SCLK => DAC_SCK,
520 520 SMPCLK => OPEN --DAC_SMPCLK
521 521 );
522 522
523 523 DAC_CAL_EN <= DAC_CAL_EN_s;
524
524 525 END Behavioral;
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@@ -1,119 +1,144
1 1 ----------------------------------------------------------------------------------
2 2 -- Company:
3 3 -- Engineer:
4 4 --
5 5 -- Create Date: 13:04:01 07/02/2012
6 6 -- Design Name:
7 7 -- Module Name: lpp_lfr_time_management - Behavioral
8 8 -- Project Name:
9 9 -- Target Devices:
10 10 -- Tool versions:
11 11 -- Description:
12 12 --
13 13 -- Dependencies:
14 14 --
15 15 -- Revision:
16 16 -- Revision 0.01 - File Created
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 20 LIBRARY IEEE;
21 21 USE IEEE.STD_LOGIC_1164.ALL;
22 22 LIBRARY grlib;
23 23 USE grlib.amba.ALL;
24 24 USE grlib.stdlib.ALL;
25 25 USE grlib.devices.ALL;
26 26
27 27 PACKAGE lpp_lfr_management IS
28 28
29 29 --***************************
30 30 -- APB_LFR_MANAGEMENT
31 31
32 32 COMPONENT apb_lfr_management
33 33 GENERIC (
34 34 tech : INTEGER;
35 35 pindex : INTEGER;
36 36 paddr : INTEGER;
37 37 pmask : INTEGER;
38 38 -- FIRST_DIVISION : INTEGER;
39 39 NB_SECOND_DESYNC : INTEGER);
40 40 PORT (
41 41 clk25MHz : IN STD_LOGIC;
42 42 resetn_25MHz : IN STD_LOGIC;
43 43 -- clk24_576MHz : IN STD_LOGIC;
44 44 -- resetn_24_576MHz : IN STD_LOGIC;
45 45 grspw_tick : IN STD_LOGIC;
46 46 apbi : IN apb_slv_in_type;
47 47 apbo : OUT apb_slv_out_type;
48 48 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
49 49 HK_val : IN STD_LOGIC;
50 50 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
51 51 DAC_SDO : OUT STD_LOGIC;
52 52 DAC_SCK : OUT STD_LOGIC;
53 53 DAC_SYNC : OUT STD_LOGIC;
54 54 DAC_CAL_EN : OUT STD_LOGIC;
55 55 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
56 56 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
57 57 LFR_soft_rstn : OUT STD_LOGIC);
58 58 END COMPONENT;
59 59
60 60 COMPONENT lfr_time_management
61 61 GENERIC (
62 62 --FIRST_DIVISION : INTEGER;
63 63 NB_SECOND_DESYNC : INTEGER);
64 64 PORT (
65 65 clk : IN STD_LOGIC;
66 66 rstn : IN STD_LOGIC;
67 67 tick : IN STD_LOGIC;
68 68 new_coarsetime : IN STD_LOGIC;
69 69 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
70 70 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
71 71 fine_time_new : OUT STD_LOGIC;
72 72 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 73 coarse_time_new : OUT STD_LOGIC);
74 74 END COMPONENT;
75 75
76 76 COMPONENT coarse_time_counter
77 77 GENERIC (
78 78 NB_SECOND_DESYNC : INTEGER);
79 79 PORT (
80 80 clk : IN STD_LOGIC;
81 81 rstn : IN STD_LOGIC;
82 82 tick : IN STD_LOGIC;
83 83 set_TCU : IN STD_LOGIC;
84 84 new_TCU : IN STD_LOGIC;
85 85 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
86 86 CT_add1 : IN STD_LOGIC;
87 87 fsm_desync : IN STD_LOGIC;
88 88 FT_max : IN STD_LOGIC;
89 89 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 90 coarse_time_new : OUT STD_LOGIC);
91 91 END COMPONENT;
92 92
93 93 COMPONENT fine_time_counter
94 94 GENERIC (
95 95 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0));--;
96 96 -- FIRST_DIVISION : INTEGER);
97 97 PORT (
98 98 clk : IN STD_LOGIC;
99 99 rstn : IN STD_LOGIC;
100 100 tick : IN STD_LOGIC;
101 101 fsm_transition : IN STD_LOGIC;
102 102 FT_max : OUT STD_LOGIC;
103 103 FT_half : OUT STD_LOGIC;
104 104 FT_wait : OUT STD_LOGIC;
105 105 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
106 106 fine_time_new : OUT STD_LOGIC);
107 107 END COMPONENT;
108 108
109 109 COMPONENT fine_time_max_value_gen
110 110 PORT (
111 111 clk : IN STD_LOGIC;
112 112 rstn : IN STD_LOGIC;
113 113 tick : IN STD_LOGIC;
114 114 fine_time_add : IN STD_LOGIC;
115 115 fine_time_max_value : OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
116 116 END COMPONENT;
117 117
118 COMPONENT apb_lfr_management_nocal
119 GENERIC (
120 tech : INTEGER;
121 pindex : INTEGER;
122 paddr : INTEGER;
123 pmask : INTEGER;
124 NB_SECOND_DESYNC : INTEGER);
125 PORT (
126 clk25MHz : IN STD_LOGIC;
127 resetn_25MHz : IN STD_LOGIC;
128 grspw_tick : IN STD_LOGIC;
129 apbi : IN apb_slv_in_type;
130 apbo : OUT apb_slv_out_type;
131 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
132 HK_val : IN STD_LOGIC;
133 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
134 DAC_SDO : OUT STD_LOGIC;
135 DAC_SCK : OUT STD_LOGIC;
136 DAC_SYNC : OUT STD_LOGIC;
137 DAC_CAL_EN : OUT STD_LOGIC;
138 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
139 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
140 LFR_soft_rstn : OUT STD_LOGIC);
141 END COMPONENT;
142
118 143 END lpp_lfr_management;
119 144
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@@ -1,7 +1,8
1 1 lpp_lfr_management.vhd
2 2 lpp_lfr_management_apbreg_pkg.vhd
3 3 apb_lfr_management.vhd
4 apb_lfr_management_nocal.vhd
4 5 lfr_time_management.vhd
5 6 fine_time_counter.vhd
6 7 coarse_time_counter.vhd
7 8 fine_time_max_value_gen.vhd
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@@ -1,228 +1,227
1 1
2 2 LIBRARY IEEE;
3 3 USE IEEE.STD_LOGIC_1164.ALL;
4 4 USE IEEE.numeric_std.ALL;
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.general_purpose.SYNC_FF;
8 8
9 9 ENTITY top_ad_conv_RHF1401_withFilter IS
10 10 GENERIC(
11 11 ChanelCount : INTEGER := 8;
12 12 ncycle_cnv_high : INTEGER := 13;
13 13 ncycle_cnv : INTEGER := 25;
14 14 FILTER_ENABLED : INTEGER := 16#FF#
15 15 );
16 16 PORT (
17 17 cnv_clk : IN STD_LOGIC; -- 24Mhz
18 18 cnv_rstn : IN STD_LOGIC;
19 19
20 20 cnv : OUT STD_LOGIC;
21 21
22 22 clk : IN STD_LOGIC; -- 25MHz
23 23 rstn : IN STD_LOGIC;
24 24 ADC_data : IN Samples14;
25 25 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
26 26 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
27 27 sample_val : OUT STD_LOGIC
28 28 );
29 29 END top_ad_conv_RHF1401_withFilter;
30 30
31 31 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
32 32
33 SIGNAL cnv_cycle_counter : INTEGER;
33 SIGNAL cnv_cycle_counter : INTEGER RANGE 0 TO ncycle_cnv-1;
34 34 SIGNAL cnv_s : STD_LOGIC;
35 35 SIGNAL cnv_s_reg : STD_LOGIC;
36 36 SIGNAL cnv_sync : STD_LOGIC;
37 37 SIGNAL cnv_sync_pre : STD_LOGIC;
38 38
39 39 SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
40 40 SIGNAL enable_ADC : STD_LOGIC;
41 41
42 42
43 43 SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
44 44
45 45 SIGNAL channel_counter : INTEGER;
46 46 CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
47 47
48 48 SIGNAL ADC_data_selected : Samples14;
49 49 SIGNAL ADC_data_result : Samples15;
50 50
51 51 SIGNAL sample_counter : INTEGER;
52 52 CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9;
53 53
54 54 CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED,ChanelCount));
55 55
56 56 BEGIN
57 57
58 58
59 59 -----------------------------------------------------------------------------
60 60 -- CNV GEN
61 61 -----------------------------------------------------------------------------
62 62 PROCESS (cnv_clk, cnv_rstn)
63 63 BEGIN -- PROCESS
64 64 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
65 65 cnv_cycle_counter <= 0;
66 66 cnv_s <= '0';
67 67 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
68 68 IF cnv_cycle_counter < ncycle_cnv-1 THEN
69 69 cnv_cycle_counter <= cnv_cycle_counter + 1;
70 70 IF cnv_cycle_counter < ncycle_cnv_high THEN
71 71 cnv_s <= '1';
72 72 ELSE
73 73 cnv_s <= '0';
74 74 END IF;
75 75 ELSE
76 76 cnv_s <= '1';
77 77 cnv_cycle_counter <= 0;
78 78 END IF;
79 79 END IF;
80 80 END PROCESS;
81 81
82 82 cnv <= cnv_s;
83 83
84 84 PROCESS (cnv_clk, cnv_rstn)
85 85 BEGIN -- PROCESS
86 86 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
87 87 cnv_s_reg <= '0';
88 88 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
89 89 cnv_s_reg <= cnv_s;
90 90 END IF;
91 91 END PROCESS;
92 92
93 93
94 94 -----------------------------------------------------------------------------
95 95 -- SYNC CNV
96 96 -----------------------------------------------------------------------------
97 97
98 98 SYNC_FF_cnv : SYNC_FF
99 99 GENERIC MAP (
100 100 NB_FF_OF_SYNC => 2)
101 101 PORT MAP (
102 102 clk => clk,
103 103 rstn => rstn,
104 104 A => cnv_s_reg,
105 105 A_sync => cnv_sync);
106 106
107 107
108 108 -----------------------------------------------------------------------------
109 109 -- DATA GEN Output Enable
110 110 -----------------------------------------------------------------------------
111 111 PROCESS (clk, rstn)
112 112 BEGIN -- PROCESS
113 113 IF rstn = '0' THEN -- asynchronous reset (active low)
114 114 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1');
115 115 cnv_sync_pre <= '0';
116 116 enable_ADC <= '0';
117 117 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
118 118 cnv_sync_pre <= cnv_sync;
119 119 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
120 120 enable_ADC <= '1';
121 121 ADC_nOE_reg(0) <= '0';
122 122 ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1');
123 123 ELSE
124 124 enable_ADC <= NOT enable_ADC;
125 125 IF enable_ADC = '0' THEN
126 126 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= ADC_nOE_reg(ChanelCount-2 DOWNTO 0) & '1';
127 127 END IF;
128 128 END IF;
129 129
130 130 END IF;
131 131 END PROCESS;
132 132
133 133 ADC_nOE <= (OTHERS => '1') WHEN enable_ADC = '0' ELSE ADC_nOE_reg;
134 134
135 135 -----------------------------------------------------------------------------
136 136 -- ADC READ DATA
137 137 -----------------------------------------------------------------------------
138 138 PROCESS (clk, rstn)
139 139 BEGIN -- PROCESS
140 140 IF rstn = '0' THEN -- asynchronous reset (active low)
141 141 channel_counter <= MAX_COUNTER;
142 142
143 143 all_sample_reg_init: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
144 144 sample_reg(I) <= (OTHERS => '0');
145 145 END LOOP all_sample_reg_init;
146 146
147 147 sample_val <= '0';
148 148 sample_counter <= 0;
149 149 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
150 150 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
151 151 channel_counter <= 0;
152 152 ELSE
153 153 IF channel_counter < MAX_COUNTER THEN
154 154 channel_counter <= channel_counter + 1;
155 155 END IF;
156 156 END IF;
157 157 sample_val <= '0';
158 158
159 159 all_sample_reg: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
160 160 IF channel_counter = I*2 THEN
161 161 IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN
162 162 sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
163 163 ELSE
164 164 sample_reg(I) <= ADC_data;
165 165 END IF;
166 166 END IF;
167 167 END LOOP all_sample_reg;
168 168
169 169 IF channel_counter = (ChanelCount-1)*2 THEN
170 170
171 171 IF sample_counter = MAX_SAMPLE_COUNTER THEN
172 172 sample_counter <= 0 ;
173 173 sample_val <= '1';
174 174 ELSE
175 175 sample_counter <= sample_counter +1;
176 176 END IF;
177 177
178 178 END IF;
179 179 END IF;
180 180 END PROCESS;
181 181
182 182 -- mux_adc: PROCESS (sample_reg)-- (channel_counter, sample_reg)
183 183 -- BEGIN -- PROCESS mux_adc
184 184 -- CASE channel_counter IS
185 185 -- WHEN OTHERS => ADC_data_selected <= sample_reg(channel_counter/2);
186 186 -- END CASE;
187 187 -- END PROCESS mux_adc;
188 188
189 189
190 190 -----------------------------------------------------------------------------
191 191 -- \/\/\/\/\/\/\/ TODO : this part is not GENERIC !!! \/\/\/\/\/\/\/
192 192 -----------------------------------------------------------------------------
193 193
194 194 WITH channel_counter SELECT
195 195 ADC_data_selected <= sample_reg(0) WHEN 0*2,
196 196 sample_reg(1) WHEN 1*2,
197 197 sample_reg(2) WHEN 2*2,
198 198 sample_reg(3) WHEN 3*2,
199 199 sample_reg(4) WHEN 4*2,
200 200 sample_reg(5) WHEN 5*2,
201 201 sample_reg(6) WHEN 6*2,
202 202 sample_reg(7) WHEN 7*2,
203 203 sample_reg(8) WHEN OTHERS ;
204 204
205 205 -----------------------------------------------------------------------------
206 206 -- /\/\/\/\/\/\/\ ----------------------------------- /\/\/\/\/\/\/\
207 207 -----------------------------------------------------------------------------
208 208
209 209 ADC_data_result <= std_logic_vector( (signed( ADC_data_selected(13) & ADC_data_selected) + signed( ADC_data(13) & ADC_data)) );
210 210
211 211 sample <= sample_reg;
212 212
213 213 END ar_top_ad_conv_RHF1401;
214 214
215 215
216 216
217 217
218 218
219 219
220 220
221 221
222 222
223 223
224 224
225 225
226 226
227 227
228
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@@ -1,99 +1,100
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@member.fsf.org
21 21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.STD_LOGIC_1164.ALL;
24 use IEEE.NUMERIC_STD.ALL;
22 LIBRARY IEEE;
23 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.NUMERIC_STD.ALL;
25 25
26 entity dynamic_freq_div is
27 generic(
28 PRESZ : integer range 1 to 32:=4;
29 PREMAX : integer := 16#FFFFFF#;
30 CPTSZ : integer range 1 to 32:=16
26 ENTITY dynamic_freq_div IS
27 GENERIC(
28 PRESZ : INTEGER RANGE 1 TO 32 := 4;
29 PREMAX : INTEGER := 16#FFFFFF#;
30 CPTSZ : INTEGER RANGE 1 TO 32 := 16
31 31 );
32 Port (
33 clk : in STD_LOGIC;
34 rstn : in STD_LOGIC;
35 pre : in STD_LOGIC_VECTOR(PRESZ-1 downto 0);
36 N : in STD_LOGIC_VECTOR(CPTSZ-1 downto 0);
37 Reload : in std_logic;
38 clk_out : out STD_LOGIC
32 PORT (
33 clk : IN STD_LOGIC;
34 rstn : IN STD_LOGIC;
35 pre : IN STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
36 N : IN STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
37 Reload : IN STD_LOGIC;
38 clk_out : OUT STD_LOGIC
39 39 );
40 end dynamic_freq_div;
40 END dynamic_freq_div;
41 41
42 architecture Behavioral of dynamic_freq_div is
43 constant prescaller_reg_sz : integer := 2**PRESZ;
44 constant PREMAX_max : STD_LOGIC_VECTOR(PRESZ-1 downto 0):=(others => '1');
45 signal cpt_reg : std_logic_vector(CPTSZ-1 downto 0):=(others => '0');
46 signal prescaller_reg : std_logic_vector(prescaller_reg_sz-1 downto 0);--:=(others => '0');
47 signal internal_clk : std_logic:='0';
48 signal internal_clk_reg : std_logic:='0';
49 signal clk_out_reg : std_logic:='0';
42 ARCHITECTURE Behavioral OF dynamic_freq_div IS
43 CONSTANT prescaller_reg_sz : INTEGER := 2**PRESZ;
44 CONSTANT PREMAX_max : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0) := (OTHERS => '1');
45 SIGNAL cpt_reg : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0) := (OTHERS => '0');
46 SIGNAL prescaller_reg : STD_LOGIC_VECTOR(prescaller_reg_sz-1 DOWNTO 0); --:=(others => '0');
47 SIGNAL internal_clk : STD_LOGIC := '0';
48 SIGNAL internal_clk_reg : STD_LOGIC := '0';
49 SIGNAL clk_out_reg : STD_LOGIC := '0';
50
51 BEGIN
50 52
51 begin
53 max0 : IF (UNSIGNED(PREMAX_max) < PREMAX) GENERATE
52 54
53 max0: if (UNSIGNED(PREMAX_max) < PREMAX) generate
54
55 internal_clk <= prescaller_reg(to_integer(unsigned(pre))) when (to_integer(unsigned(pre))<=UNSIGNED(PREMAX_max)) else
55 internal_clk <= prescaller_reg(to_integer(UNSIGNED(pre))) WHEN (to_integer(UNSIGNED(pre)) <= UNSIGNED(PREMAX_max)) ELSE
56 56 prescaller_reg(to_integer(UNSIGNED(PREMAX_max)));
57 end generate;
58 max1: if UNSIGNED(PREMAX_max) > PREMAX generate
59 internal_clk <= prescaller_reg(to_integer(unsigned(pre))) when (to_integer(unsigned(pre))<=PREMAX) else
57 END GENERATE;
58
59 max1 : IF UNSIGNED(PREMAX_max) > PREMAX GENERATE
60 internal_clk <= prescaller_reg(to_integer(UNSIGNED(pre))) WHEN (to_integer(UNSIGNED(pre)) <= PREMAX) ELSE
60 61 prescaller_reg(PREMAX);
61 end generate;
62 END GENERATE;
62 63
63 64
64 65
65 prescaller: process(rstn, clk)
66 begin
67 if rstn='0' then
68 prescaller_reg <= (others => '0');
69 elsif clk'event and clk = '1' then
70 prescaller_reg <= std_logic_vector(UNSIGNED(prescaller_reg) + 1);
71 end if;
72 end process;
66 prescaller : PROCESS(rstn, clk)
67 BEGIN
68 IF rstn = '0' then
69 prescaller_reg <= (OTHERS => '0');
70 ELSIF clk'EVENT AND clk = '1' THEN
71 prescaller_reg <= STD_LOGIC_VECTOR(UNSIGNED(prescaller_reg) + 1);
72 END IF;
73 END PROCESS;
73 74
74 75
75 76 clk_out <= clk_out_reg;
76 77
77 counter: process(rstn, clk)
78 begin
79 if rstn='0' then
80 cpt_reg <= (others => '0');
78 counter : PROCESS(rstn, clk)
79 BEGIN
80 IF rstn = '0' then
81 cpt_reg <= (OTHERS => '0');
81 82 internal_clk_reg <= '0';
82 83 clk_out_reg <= '0';
83 elsif clk'event and clk = '1' then
84 ELSIF clk'EVENT AND clk = '1' THEN
84 85 internal_clk_reg <= internal_clk;
85 if Reload = '1' then
86 IF Reload = '1' THEN
86 87 clk_out_reg <= '0';
87 cpt_reg <= (others => '0');
88 elsif (internal_clk = '1' and internal_clk_reg = '0') then
89 if cpt_reg = N then
90 clk_out_reg <= not clk_out_reg;
91 cpt_reg <= (others => '0');
92 else
93 cpt_reg <= std_logic_vector(UNSIGNED(cpt_reg) + 1);
94 end if;
95 end if;
96 end if;
97 end process;
88 cpt_reg <= (OTHERS => '0');
89 ELSIF (internal_clk = '1' AND internal_clk_reg = '0') THEN
90 IF cpt_reg = N THEN
91 clk_out_reg <= NOT clk_out_reg;
92 cpt_reg <= (OTHERS => '0');
93 ELSE
94 cpt_reg <= STD_LOGIC_VECTOR(UNSIGNED(cpt_reg) + 1);
95 END IF;
96 END IF;
97 END IF;
98 END PROCESS;
98 99
99 end Behavioral; No newline at end of file
100 END Behavioral;
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@@ -1,240 +1,240
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.apb_devices_list.ALL;
7 7 USE lpp.lpp_ad_conv.ALL;
8 8 USE lpp.iir_filter.ALL;
9 9 USE lpp.FILTERcfg.ALL;
10 10 USE lpp.lpp_memory.ALL;
11 11 --USE lpp.lpp_waveform_pkg.ALL;
12 12 USE lpp.lpp_dma_pkg.ALL;
13 13 --USE lpp.lpp_top_lfr_pkg.ALL;
14 14 --USE lpp.lpp_lfr_pkg.ALL;
15 15 USE lpp.general_purpose.ALL;
16 16
17 17 LIBRARY techmap;
18 18 USE techmap.gencomp.ALL;
19 19
20 20 LIBRARY grlib;
21 21 USE grlib.amba.ALL;
22 22 USE grlib.stdlib.ALL;
23 23 USE grlib.devices.ALL;
24 24 USE GRLIB.DMA2AHB_Package.ALL;
25 25
26 26 ENTITY DMA_SubSystem IS
27 27
28 28 GENERIC (
29 29 hindex : INTEGER := 2;
30 30 CUSTOM_DMA : INTEGER := 1);
31 31
32 32 PORT (
33 33 clk : IN STD_LOGIC;
34 34 rstn : IN STD_LOGIC;
35 35 run : IN STD_LOGIC;
36 36 -- AHB
37 37 ahbi : IN AHB_Mst_In_Type;
38 38 ahbo : OUT AHB_Mst_Out_Type;
39 39 ---------------------------------------------------------------------------
40 40 fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
41 41 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
42 42 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
43 43 ---------------------------------------------------------------------------
44 44 buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
45 45 buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
46 46 buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
47 47 buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
48 48 buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
49 49 ---------------------------------------------------------------------------
50 50 grant_error : OUT STD_LOGIC;
51 51 ---------------------------------------------------------------------------
52 52 debug_vector : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
53 53
54 54 );
55 55
56 56 END DMA_SubSystem;
57 57
58 58
59 59 ARCHITECTURE beh OF DMA_SubSystem IS
60 60
61 61 COMPONENT DMA_SubSystem_GestionBuffer
62 62 GENERIC (
63 63 BUFFER_ADDR_SIZE : INTEGER;
64 64 BUFFER_LENGTH_SIZE : INTEGER);
65 65 PORT (
66 66 clk : IN STD_LOGIC;
67 67 rstn : IN STD_LOGIC;
68 run : IN STD_LOGIC;
68 -- run : IN STD_LOGIC;
69 69 buffer_new : IN STD_LOGIC;
70 70 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
71 71 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
72 72 buffer_full : OUT STD_LOGIC;
73 73 buffer_full_err : OUT STD_LOGIC;
74 74 burst_send : IN STD_LOGIC;
75 75 burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0));
76 76 END COMPONENT;
77 77
78 78 COMPONENT DMA_SubSystem_Arbiter
79 79 PORT (
80 80 clk : IN STD_LOGIC;
81 81 rstn : IN STD_LOGIC;
82 82 run : IN STD_LOGIC;
83 83 data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
84 84 data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
85 85 END COMPONENT;
86 86
87 87 COMPONENT DMA_SubSystem_MUX
88 88 PORT (
89 89 clk : IN STD_LOGIC;
90 90 rstn : IN STD_LOGIC;
91 91 run : IN STD_LOGIC;
92 92 fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
93 93 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
94 94 fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
95 95 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
96 96 fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
97 97 dma_send : OUT STD_LOGIC;
98 98 dma_valid_burst : OUT STD_LOGIC;
99 99 dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
100 100 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
101 101 dma_ren : IN STD_LOGIC;
102 102 dma_done : IN STD_LOGIC;
103 103 grant_error : OUT STD_LOGIC);
104 104 END COMPONENT;
105 105
106 106 -----------------------------------------------------------------------------
107 107 SIGNAL dma_send : STD_LOGIC;
108 108 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
109 109 SIGNAL dma_done : STD_LOGIC;
110 110 SIGNAL dma_ren : STD_LOGIC;
111 111 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
112 112 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
113 113 SIGNAL burst_send : STD_LOGIC_VECTOR(4 DOWNTO 0);
114 114 SIGNAL fifo_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
115 115 SIGNAL fifo_address : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --
116 116
117 117 SIGNAL ahbo_s : AHB_Mst_Out_Type;
118 118 SIGNAL fifo_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 119 BEGIN -- beh
120 120
121 121
122 122 debug_vector <= fifo_ren_s(0) &
123 123 dma_data(1 DOWNTO 0) &
124 124 ahbi.HREADY &
125 125 ahbo_s.HWDATA(1 DOWNTO 0) &
126 126 ahbi.HGRANT(hindex) &
127 127 ahbo_s.HTRANS(0) &
128 128 ahbo_s.HLOCK;
129 129
130 130 ahbo <= ahbo_s;
131 131 fifo_ren <= fifo_ren_s;
132 132 -----------------------------------------------------------------------------
133 133 -- DMA
134 134 -----------------------------------------------------------------------------
135 135 GR_DMA : IF CUSTOM_DMA = 0 GENERATE
136 136 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
137 137 GENERIC MAP (
138 138 tech => inferred,
139 139 hindex => hindex)
140 140 PORT MAP (
141 141 HCLK => clk,
142 142 HRESETn => rstn,
143 143 run => run,
144 144 AHB_Master_In => ahbi,
145 145 AHB_Master_Out => ahbo_s,
146 146
147 147 send => dma_send,
148 148 valid_burst => dma_valid_burst,
149 149 done => dma_done,
150 150 ren => dma_ren,
151 151 address => dma_address,
152 152 data => dma_data);
153 153 END GENERATE GR_DMA;
154 154
155 155 LPP_DMA_IP : IF CUSTOM_DMA = 1 GENERATE
156 156 lpp_dma_SEND16B_FIFO2DMA_1 : lpp_dma_SEND16B_FIFO2DMA
157 157 GENERIC MAP (
158 158 hindex => hindex,
159 159 vendorid => VENDOR_LPP,
160 160 deviceid => 10,
161 161 version => 0)
162 162 PORT MAP (
163 163 clk => clk,
164 164 rstn => rstn,
165 165 AHB_Master_In => ahbi,
166 166 AHB_Master_Out => ahbo_s,
167 167
168 168 ren => dma_ren,
169 169 data => dma_data,
170 170 send => dma_send,
171 171 valid_burst => dma_valid_burst,
172 172 done => dma_done,
173 173 address => dma_address);
174 174 END GENERATE LPP_DMA_IP;
175 175
176 176
177 177 -----------------------------------------------------------------------------
178 178 -- RoundRobin Selection Channel For DMA
179 179 -----------------------------------------------------------------------------
180 180 DMA_SubSystem_Arbiter_1: DMA_SubSystem_Arbiter
181 181 PORT MAP (
182 182 clk => clk,
183 183 rstn => rstn,
184 184 run => run,
185 185 data_burst_valid => fifo_burst_valid,
186 186 data_burst_valid_grant => fifo_grant);
187 187
188 188
189 189 -----------------------------------------------------------------------------
190 190 -- Mux between the channel from Waveform Picker and Spectral Matrix
191 191 -----------------------------------------------------------------------------
192 192 DMA_SubSystem_MUX_1: DMA_SubSystem_MUX
193 193 PORT MAP (
194 194 clk => clk,
195 195 rstn => rstn,
196 196 run => run,
197 197
198 198 fifo_grant => fifo_grant,
199 199 fifo_data => fifo_data,
200 200 fifo_address => fifo_address,
201 201 fifo_ren => fifo_ren_s,
202 202 fifo_burst_done => burst_send,
203 203
204 204 dma_send => dma_send,
205 205 dma_valid_burst => dma_valid_burst,
206 206 dma_address => dma_address,
207 207 dma_data => dma_data,
208 208 dma_ren => dma_ren,
209 209 dma_done => dma_done,
210 210
211 211 grant_error => grant_error);
212 212
213 213
214 214 -----------------------------------------------------------------------------
215 215 -- GEN ADDR
216 216 -----------------------------------------------------------------------------
217 217 all_buffer : FOR I IN 4 DOWNTO 0 GENERATE
218 218 DMA_SubSystem_GestionBuffer_I : DMA_SubSystem_GestionBuffer
219 219 GENERIC MAP (
220 220 BUFFER_ADDR_SIZE => 32,
221 221 BUFFER_LENGTH_SIZE => 26)
222 222 PORT MAP (
223 223 clk => clk,
224 224 rstn => rstn,
225 run => run,
225 -- run => run,
226 226
227 227 buffer_new => buffer_new(I),
228 228 buffer_addr => buffer_addr(32*(I+1)-1 DOWNTO I*32),
229 229 buffer_length => buffer_length(26*(I+1)-1 DOWNTO I*26),
230 230 buffer_full => buffer_full(I),
231 231 buffer_full_err => buffer_full_err(I),
232 232
233 233 burst_send => burst_send(I),
234 234 burst_addr => fifo_address(32*(I+1)-1 DOWNTO 32*I)
235 235 );
236 236 END GENERATE all_buffer;
237 237
238 238
239 239
240 240 END beh;
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@@ -1,76 +1,76
1 1
2 2 LIBRARY ieee;
3 3 USE ieee.std_logic_1164.ALL;
4 4 USE ieee.numeric_std.ALL;
5 5
6 6 ENTITY DMA_SubSystem_GestionBuffer IS
7 7 GENERIC (
8 8 BUFFER_ADDR_SIZE : INTEGER := 32;
9 9 BUFFER_LENGTH_SIZE : INTEGER := 26);
10 10 PORT (
11 11 clk : IN STD_LOGIC;
12 12 rstn : IN STD_LOGIC;
13 run : IN STD_LOGIC;
13 -- run : IN STD_LOGIC;
14 14 --
15 15 buffer_new : IN STD_LOGIC;
16 16 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
17 17 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0); --in 64B
18 18 buffer_full : OUT STD_LOGIC;
19 19 buffer_full_err : OUT STD_LOGIC;
20 20 --
21 21 burst_send : IN STD_LOGIC;
22 22 burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0)
23 23 );
24 24 END DMA_SubSystem_GestionBuffer;
25 25
26 26
27 27 ARCHITECTURE beh OF DMA_SubSystem_GestionBuffer IS
28 28
29 29 TYPE state_DMA_GestionBuffer IS (IDLE, ON_GOING);
30 30 SIGNAL state : state_DMA_GestionBuffer;
31 31
32 32 SIGNAL burst_send_counter : STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
33 33 SIGNAL burst_send_counter_add1 : STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
34 34 SIGNAL addr_shift : STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
35 35
36 36 BEGIN
37 37 addr_shift <= burst_send_counter & "000000";
38 38 burst_addr <= STD_LOGIC_VECTOR(unsigned(buffer_addr) + unsigned(addr_shift));
39 39
40 40 burst_send_counter_add1 <= STD_LOGIC_VECTOR(unsigned(burst_send_counter) + 1);
41 41
42 42 PROCESS (clk, rstn)
43 43 BEGIN -- PROCESS
44 44 IF rstn = '0' THEN -- asynchronous reset (active low)
45 45 burst_send_counter <= (OTHERS => '0');
46 46 state <= IDLE;
47 47 buffer_full <= '0';
48 48 buffer_full_err <= '0';
49 49 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
50 50 CASE state IS
51 51 WHEN IDLE =>
52 52 burst_send_counter <= (OTHERS => '0');
53 53 buffer_full_err <= burst_send;
54 54 buffer_full <= '0';
55 55 IF buffer_new = '1' THEN
56 56 state <= ON_GOING;
57 57 END IF;
58 58
59 59 WHEN ON_GOING =>
60 60 buffer_full_err <= '0';
61 61 buffer_full <= '0';
62 62 IF burst_send = '1' THEN
63 63 IF unsigned(burst_send_counter_add1) < unsigned(buffer_length) THEN
64 64 burst_send_counter <= burst_send_counter_add1;
65 65 ELSE
66 66 buffer_full <= '1';
67 67 state <= IDLE;
68 68 END IF;
69 69 END IF;
70 70
71 71 WHEN OTHERS => NULL;
72 72 END CASE;
73 73 END IF;
74 74 END PROCESS;
75 75
76 76 END beh;
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@@ -1,255 +1,251
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23 -- 1.0 - initial version
24 24 -------------------------------------------------------------------------------
25 25 LIBRARY ieee;
26 26 USE ieee.std_logic_1164.ALL;
27 27 USE ieee.numeric_std.ALL;
28 28 LIBRARY grlib;
29 29 USE grlib.amba.ALL;
30 30 USE grlib.stdlib.ALL;
31 31 USE grlib.devices.ALL;
32 32
33 33 LIBRARY lpp;
34 34 USE lpp.lpp_amba.ALL;
35 35 USE lpp.apb_devices_list.ALL;
36 36 USE lpp.lpp_memory.ALL;
37 37 USE lpp.lpp_dma_pkg.ALL;
38 38 USE lpp.general_purpose.ALL;
39 39 --USE lpp.lpp_waveform_pkg.ALL;
40 40 LIBRARY techmap;
41 41 USE techmap.gencomp.ALL;
42 42
43 43
44 44 ENTITY lpp_dma_SEND16B_FIFO2DMA IS
45 45 GENERIC (
46 46 hindex : INTEGER := 2;
47 47 vendorid : IN INTEGER := 0;
48 48 deviceid : IN INTEGER := 0;
49 49 version : IN INTEGER := 0
50 50 );
51 51 PORT (
52 52 clk : IN STD_LOGIC;
53 53 rstn : IN STD_LOGIC;
54 54
55 55 -- AMBA AHB Master Interface
56 56 AHB_Master_In : IN AHB_Mst_In_Type;
57 57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58 58
59 59 -- FIFO Interface
60 60 ren : OUT STD_LOGIC;
61 61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 62
63 63 -- Controls
64 64 send : IN STD_LOGIC;
65 65 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
66 66 done : OUT STD_LOGIC;
67 67 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
68 68 );
69 69 END;
70 70
71 71 ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS
72 72
73 73 CONSTANT HConfig : AHB_Config_Type := (
74 74 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
75 75 OTHERS => (OTHERS => '0'));
76 76
77 77 TYPE AHB_DMA_FSM_STATE IS (IDLE, s_INIT_TRANS, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
78 78 SIGNAL state : AHB_DMA_FSM_STATE;
79 79
80 80 SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
81 SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
82 81
83 82 SIGNAL data_window : STD_LOGIC;
84 83 SIGNAL ctrl_window : STD_LOGIC;
85 84
86 SIGNAL bus_request : STD_LOGIC;
87 SIGNAL bus_lock : STD_LOGIC;
88
89 85 SIGNAL data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
90 86
91 87 SIGNAL HREADY_pre : STD_LOGIC;
92 88 SIGNAL HREADY_falling : STD_LOGIC;
93 89
94 90 SIGNAL inhib_ren : STD_LOGIC;
95 91
96 92 BEGIN
97 93
98 94 -----------------------------------------------------------------------------
99 95 AHB_Master_Out.HCONFIG <= HConfig;
100 96 AHB_Master_Out.HSIZE <= "010"; --WORDS 32b
101 97 AHB_Master_Out.HINDEX <= hindex;
102 98 AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
103 99 AHB_Master_Out.HIRQ <= (OTHERS => '0');
104 100 AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16
105 101 AHB_Master_Out.HWRITE <= '1';
106 102
107 103 --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE;
108 104
109 105 --AHB_Master_Out.HBUSREQ <= bus_request;
110 106 --AHB_Master_Out.HLOCK <= data_window;
111 107
112 108 --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE
113 109 -- '1' WHEN ctrl_window = '1' ELSE
114 110 -- '0';
115 111
116 112 --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE
117 113 -- '1' WHEN ctrl_window = '1' ELSE '0';
118 114
119 115 -----------------------------------------------------------------------------
120 116 AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
121 117 AHB_Master_Out.HWDATA <= ahbdrivedata(data) WHEN AHB_Master_In.HREADY = '1' ELSE ahbdrivedata(data_reg);
122 118
123 119 -----------------------------------------------------------------------------
124 120 --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
125 121 --ren <= NOT beat;
126 122 -----------------------------------------------------------------------------
127 123
128 124 HREADY_falling <= inhib_ren WHEN AHB_Master_In.HREADY = '0' AND HREADY_pre = '1' ELSE '1';
129 125
130 126
131 127 PROCESS (clk, rstn)
132 128 BEGIN -- PROCESS
133 129 IF rstn = '0' THEN -- asynchronous reset (active low)
134 130 state <= IDLE;
135 131 done <= '0';
136 132 ren <= '1';
137 133 address_counter_reg <= (OTHERS => '0');
138 134 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
139 135 AHB_Master_Out.HBUSREQ <= '0';
140 136 AHB_Master_Out.HLOCK <= '0';
141 137
142 138 data_reg <= (OTHERS => '0');
143 139
144 140 HREADY_pre <= '0';
145 141 inhib_ren <= '0';
146 142 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
147 143 HREADY_pre <= AHB_Master_In.HREADY;
148 144
149 145 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
150 146 data_reg <= data;
151 147 END IF;
152 148
153 149 done <= '0';
154 150 ren <= '1';
155 151 inhib_ren <= '0';
156 152 CASE state IS
157 153 WHEN IDLE =>
158 154 AHB_Master_Out.HBUSREQ <= '0';
159 155 AHB_Master_Out.HLOCK <= '0';
160 156 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
161 157 address_counter_reg <= (OTHERS => '0');
162 158 IF send = '1' THEN
163 159 state <= s_INIT_TRANS;
164 160 END IF;
165 161
166 162 WHEN s_INIT_TRANS =>
167 163 AHB_Master_Out.HBUSREQ <= '1';
168 164 AHB_Master_Out.HLOCK <= '1';
169 165 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
170 166 state <= s_ARBITER;
171 167
172 168 WHEN s_ARBITER =>
173 169 AHB_Master_Out.HBUSREQ <= '1';
174 170 AHB_Master_Out.HLOCK <= '1';
175 171 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
176 172 address_counter_reg <= (OTHERS => '0');
177 173
178 174 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
179 175 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
180 176 state <= s_CTRL;
181 177 END IF;
182 178
183 179 WHEN s_CTRL =>
184 180 inhib_ren <= '1';
185 181 AHB_Master_Out.HBUSREQ <= '1';
186 182 AHB_Master_Out.HLOCK <= '1';
187 183 AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
188 184 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
189 185 --AHB_Master_Out.HTRANS <= HTRANS_SEQ;
190 186 state <= s_CTRL_DATA;
191 187 --ren <= '0';
192 188 END IF;
193 189
194 190 WHEN s_CTRL_DATA =>
195 191 AHB_Master_Out.HBUSREQ <= '1';
196 192 AHB_Master_Out.HLOCK <= '1';
197 193 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
198 194 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
199 195 address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1);
200 196 END IF;
201 197
202 198 IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
203 199 AHB_Master_Out.HBUSREQ <= '0';
204 200 AHB_Master_Out.HLOCK <= '1';--'0';
205 201 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
206 202 state <= s_DATA;
207 203 END IF;
208 204
209 205 ren <= HREADY_falling;
210 206
211 207 --IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' AND address_counter_reg /= "1111" THEN
212 208 -- ren <= '0';
213 209 --END IF;
214 210
215 211
216 212 WHEN s_DATA =>
217 213 ren <= HREADY_falling;
218 214
219 215 AHB_Master_Out.HBUSREQ <= '0';
220 216 --AHB_Master_Out.HLOCK <= '0';
221 217 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
222 218 IF AHB_Master_In.HREADY = '1' THEN
223 219 AHB_Master_Out.HLOCK <= '0';
224 220 state <= IDLE;
225 221 done <= '1';
226 222 END IF;
227 223
228 224 WHEN OTHERS => NULL;
229 225 END CASE;
230 226 END IF;
231 227 END PROCESS;
232 228
233 229 ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
234 230 data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
235 231 -----------------------------------------------------------------------------
236 232
237 233
238 234 --ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
239 235
240 236 -----------------------------------------------------------------------------
241 237 --PROCESS (clk, rstn)
242 238 --BEGIN -- PROCESS
243 239 -- IF rstn = '0' THEN -- asynchronous reset (active low)
244 240 -- address_counter_reg <= (OTHERS => '0');
245 241 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
246 242 -- address_counter_reg <= address_counter;
247 243 -- END IF;
248 244 --END PROCESS;
249 245
250 246 --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE
251 247 -- address_counter_reg;
252 248 -----------------------------------------------------------------------------
253 249
254 250
255 END Behavioral;
251 END Behavioral; No newline at end of file
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@@ -1,311 +1,311
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE std.textio.ALL;
28 28 LIBRARY grlib;
29 29 USE grlib.amba.ALL;
30 30 USE grlib.stdlib.ALL;
31 31 USE GRLIB.DMA2AHB_Package.ALL;
32 32 LIBRARY techmap;
33 33 USE techmap.gencomp.ALL;
34 34 --LIBRARY lpp;
35 35 --USE lpp.lpp_amba.ALL;
36 36 --USE lpp.apb_devices_list.ALL;
37 37 --USE lpp.lpp_memory.ALL;
38 38
39 39 PACKAGE lpp_dma_pkg IS
40 40
41 41 COMPONENT lpp_dma
42 42 GENERIC (
43 43 tech : INTEGER;
44 44 hindex : INTEGER;
45 45 pindex : INTEGER;
46 46 paddr : INTEGER;
47 47 pmask : INTEGER;
48 48 pirq : INTEGER);
49 49 PORT (
50 50 HCLK : IN STD_ULOGIC;
51 51 HRESETn : IN STD_ULOGIC;
52 52 apbi : IN apb_slv_in_type;
53 53 apbo : OUT apb_slv_out_type;
54 54 AHB_Master_In : IN AHB_Mst_In_Type;
55 55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
56 56 -- fifo interface
57 57 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 58 fifo_empty : IN STD_LOGIC;
59 59 fifo_ren : OUT STD_LOGIC;
60 60 -- header
61 61 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 62 header_val : IN STD_LOGIC;
63 63 header_ack : OUT STD_LOGIC);
64 64 END COMPONENT;
65 65
66 66 COMPONENT fifo_test_dma
67 67 GENERIC (
68 68 tech : INTEGER;
69 69 pindex : INTEGER;
70 70 paddr : INTEGER;
71 71 pmask : INTEGER);
72 72 PORT (
73 73 HCLK : IN STD_ULOGIC;
74 74 HRESETn : IN STD_ULOGIC;
75 75 apbi : IN apb_slv_in_type;
76 76 apbo : OUT apb_slv_out_type;
77 77 -- fifo interface
78 78 fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 79 fifo_empty : OUT STD_LOGIC;
80 80 fifo_ren : IN STD_LOGIC;
81 81 -- header
82 82 header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 83 header_val : OUT STD_LOGIC;
84 84 header_ack : IN STD_LOGIC
85 85 );
86 86 END COMPONENT;
87 87
88 88 COMPONENT lpp_dma_apbreg
89 89 GENERIC (
90 90 pindex : INTEGER;
91 91 paddr : INTEGER;
92 92 pmask : INTEGER;
93 93 pirq : INTEGER);
94 94 PORT (
95 95 HCLK : IN STD_ULOGIC;
96 96 HRESETn : IN STD_ULOGIC;
97 97 apbi : IN apb_slv_in_type;
98 98 apbo : OUT apb_slv_out_type;
99 99 -- IN
100 100 ready_matrix_f0_0 : IN STD_LOGIC;
101 101 ready_matrix_f0_1 : IN STD_LOGIC;
102 102 ready_matrix_f1 : IN STD_LOGIC;
103 103 ready_matrix_f2 : IN STD_LOGIC;
104 104 error_anticipating_empty_fifo : IN STD_LOGIC;
105 105 error_bad_component_error : IN STD_LOGIC;
106 106 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
107 107
108 108 -- OUT
109 109 status_ready_matrix_f0_0 : OUT STD_LOGIC;
110 110 status_ready_matrix_f0_1 : OUT STD_LOGIC;
111 111 status_ready_matrix_f1 : OUT STD_LOGIC;
112 112 status_ready_matrix_f2 : OUT STD_LOGIC;
113 113 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
114 114 status_error_bad_component_error : OUT STD_LOGIC;
115 115
116 116 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
117 117 config_active_interruption_onError : OUT STD_LOGIC;
118 118 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 119 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 120 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
122 122 );
123 123 END COMPONENT;
124 124
125 125 COMPONENT lpp_dma_send_1word
126 126 PORT (
127 127 HCLK : IN STD_ULOGIC;
128 128 HRESETn : IN STD_ULOGIC;
129 129 DMAIn : OUT DMA_In_Type;
130 130 DMAOut : IN DMA_OUt_Type;
131 131 send : IN STD_LOGIC;
132 132 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 133 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
134 134 ren : OUT STD_LOGIC;
135 135 send_ok : OUT STD_LOGIC;
136 136 send_ko : OUT STD_LOGIC);
137 137 END COMPONENT;
138 138
139 139 COMPONENT lpp_dma_send_16word
140 140 PORT (
141 141 HCLK : IN STD_ULOGIC;
142 142 HRESETn : IN STD_ULOGIC;
143 143 DMAIn : OUT DMA_In_Type;
144 144 DMAOut : IN DMA_OUt_Type;
145 145 send : IN STD_LOGIC;
146 146 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
147 147 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
148 148 ren : OUT STD_LOGIC;
149 149 send_ok : OUT STD_LOGIC;
150 150 send_ko : OUT STD_LOGIC);
151 151 END COMPONENT;
152 152
153 153 COMPONENT fifo_latency_correction
154 154 PORT (
155 155 HCLK : IN STD_ULOGIC;
156 156 HRESETn : IN STD_ULOGIC;
157 157 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
158 158 fifo_empty : IN STD_LOGIC;
159 159 fifo_ren : OUT STD_LOGIC;
160 160 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
161 161 dma_empty : OUT STD_LOGIC;
162 162 dma_ren : IN STD_LOGIC);
163 163 END COMPONENT;
164 164
165 165 COMPONENT lpp_dma_ip
166 166 GENERIC (
167 167 tech : INTEGER;
168 168 hindex : INTEGER);
169 169 PORT (
170 170 HCLK : IN STD_ULOGIC;
171 171 HRESETn : IN STD_ULOGIC;
172 172 AHB_Master_In : IN AHB_Mst_In_Type;
173 173 AHB_Master_Out : OUT AHB_Mst_Out_Type;
174 174 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175 fifo_empty : IN STD_LOGIC;
176 176 fifo_ren : OUT STD_LOGIC;
177 177 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
178 178 header_val : IN STD_LOGIC;
179 179 header_ack : OUT STD_LOGIC;
180 180 ready_matrix_f0_0 : OUT STD_LOGIC;
181 181 ready_matrix_f0_1 : OUT STD_LOGIC;
182 182 ready_matrix_f1 : OUT STD_LOGIC;
183 183 ready_matrix_f2 : OUT STD_LOGIC;
184 184 error_anticipating_empty_fifo : OUT STD_LOGIC;
185 185 error_bad_component_error : OUT STD_LOGIC;
186 186 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
187 187 status_ready_matrix_f0_0 : IN STD_LOGIC;
188 188 status_ready_matrix_f0_1 : IN STD_LOGIC;
189 189 status_ready_matrix_f1 : IN STD_LOGIC;
190 190 status_ready_matrix_f2 : IN STD_LOGIC;
191 191 status_error_anticipating_empty_fifo : IN STD_LOGIC;
192 192 status_error_bad_component_error : IN STD_LOGIC;
193 193 config_active_interruption_onNewMatrix : IN STD_LOGIC;
194 194 config_active_interruption_onError : IN STD_LOGIC;
195 195 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
196 196 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
197 197 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
198 198 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
199 199 END COMPONENT;
200 200
201 201 COMPONENT lpp_dma_singleOrBurst
202 202 GENERIC (
203 203 tech : INTEGER;
204 204 hindex : INTEGER);
205 205 PORT (
206 206 HCLK : IN STD_ULOGIC;
207 207 HRESETn : IN STD_ULOGIC;
208 208 run : IN STD_LOGIC;
209 209 AHB_Master_In : IN AHB_Mst_In_Type;
210 210 AHB_Master_Out : OUT AHB_Mst_Out_Type;
211 211 send : IN STD_LOGIC;
212 212 valid_burst : IN STD_LOGIC;
213 213 done : OUT STD_LOGIC;
214 214 ren : OUT STD_LOGIC;
215 215 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
216 216 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
217 217 debug_dmaout_okay : OUT STD_LOGIC);
218 218 END COMPONENT;
219 219
220 220
221 221 -----------------------------------------------------------------------------
222 222 -- DMA_SubSystem
223 223 -----------------------------------------------------------------------------
224 224 COMPONENT DMA_SubSystem
225 225 GENERIC (
226 226 hindex : INTEGER;
227 227 CUSTOM_DMA : INTEGER := 1);
228 228 PORT (
229 229 clk : IN STD_LOGIC;
230 230 rstn : IN STD_LOGIC;
231 231 run : IN STD_LOGIC;
232 232 ahbi : IN AHB_Mst_In_Type;
233 233 ahbo : OUT AHB_Mst_Out_Type;
234 234 fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
235 235 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
236 236 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
237 237 buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
238 238 buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
239 239 buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
240 240 buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
241 241 buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
242 242 grant_error : OUT STD_LOGIC;
243 243 debug_vector : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
244 244 );
245 245 END COMPONENT;
246 246
247 247 COMPONENT DMA_SubSystem_GestionBuffer
248 248 GENERIC (
249 249 BUFFER_ADDR_SIZE : INTEGER;
250 250 BUFFER_LENGTH_SIZE : INTEGER);
251 251 PORT (
252 252 clk : IN STD_LOGIC;
253 253 rstn : IN STD_LOGIC;
254 run : IN STD_LOGIC;
254 -- run : IN STD_LOGIC;
255 255 buffer_new : IN STD_LOGIC;
256 256 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
257 257 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
258 258 buffer_full : OUT STD_LOGIC;
259 259 buffer_full_err : OUT STD_LOGIC;
260 260 burst_send : IN STD_LOGIC;
261 261 burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0));
262 262 END COMPONENT;
263 263
264 264 COMPONENT DMA_SubSystem_Arbiter
265 265 PORT (
266 266 clk : IN STD_LOGIC;
267 267 rstn : IN STD_LOGIC;
268 268 run : IN STD_LOGIC;
269 269 data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
270 270 data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
271 271 END COMPONENT;
272 272
273 273 COMPONENT DMA_SubSystem_MUX
274 274 PORT (
275 275 clk : IN STD_LOGIC;
276 276 rstn : IN STD_LOGIC;
277 277 run : IN STD_LOGIC;
278 278 fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
279 279 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
280 280 fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
281 281 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
282 282 fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
283 283 dma_send : OUT STD_LOGIC;
284 284 dma_valid_burst : OUT STD_LOGIC;
285 285 dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
286 286 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
287 287 dma_ren : IN STD_LOGIC;
288 288 dma_done : IN STD_LOGIC;
289 289 grant_error : OUT STD_LOGIC);
290 290 END COMPONENT;
291 291
292 292 COMPONENT lpp_dma_SEND16B_FIFO2DMA
293 293 GENERIC (
294 294 hindex : INTEGER;
295 295 vendorid : in Integer;
296 296 deviceid : in Integer;
297 297 version : in Integer);
298 298 PORT (
299 299 clk : IN STD_LOGIC;
300 300 rstn : IN STD_LOGIC;
301 301 AHB_Master_In : IN AHB_Mst_In_Type;
302 302 AHB_Master_Out : OUT AHB_Mst_Out_Type;
303 303 ren : OUT STD_LOGIC;
304 304 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
305 305 send : IN STD_LOGIC;
306 306 valid_burst : IN STD_LOGIC;
307 307 done : OUT STD_LOGIC;
308 308 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
309 309 END COMPONENT;
310 310
311 311 END;
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@@ -1,572 +1,572
1 1 -----------------------------------------------------------------------------
2 2 -- LEON3 Demonstration design
3 3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19
20 20
21 21 LIBRARY ieee;
22 22 USE ieee.std_logic_1164.ALL;
23 23 LIBRARY grlib;
24 24 USE grlib.amba.ALL;
25 25 USE grlib.stdlib.ALL;
26 26 LIBRARY techmap;
27 27 USE techmap.gencomp.ALL;
28 28 LIBRARY gaisler;
29 29 USE gaisler.memctrl.ALL;
30 30 USE gaisler.leon3.ALL;
31 31 USE gaisler.uart.ALL;
32 32 USE gaisler.misc.ALL;
33 33 USE gaisler.spacewire.ALL; -- PLE
34 34 LIBRARY esa;
35 35 USE esa.memoryctrl.ALL;
36 36 LIBRARY lpp;
37 37 USE lpp.lpp_memory.ALL;
38 38 USE lpp.lpp_ad_conv.ALL;
39 39 USE lpp.lpp_lfr_pkg.ALL;
40 40 USE lpp.iir_filter.ALL;
41 41 USE lpp.general_purpose.ALL;
42 42 USE lpp.lpp_leon3_soc_pkg.ALL;
43 43 LIBRARY iap;
44 44 USE iap.memctrl.ALL;
45 45
46 46
47 47 ENTITY leon3_soc IS
48 48 GENERIC (
49 fabtech : INTEGER := apa3e;
50 memtech : INTEGER := apa3e;
49 fabtech : INTEGER := axcel;--apa3e;
50 memtech : INTEGER := axcel;--apa3e;
51 51 padtech : INTEGER := inferred;
52 52 clktech : INTEGER := inferred;
53 53 disas : INTEGER := 0; -- Enable disassembly to console
54 54 dbguart : INTEGER := 0; -- Print UART on console
55 55 pclow : INTEGER := 2;
56 56 --
57 57 clk_freq : INTEGER := 25000; --kHz
58 58 --
59 IS_RADHARD : INTEGER := 0;
59 IS_RADHARD : INTEGER := 1;
60 60 --
61 61 NB_CPU : INTEGER := 1;
62 62 ENABLE_FPU : INTEGER := 1;
63 FPU_NETLIST : INTEGER := 1;
63 FPU_NETLIST : INTEGER := 0;
64 64 ENABLE_DSU : INTEGER := 1;
65 65 ENABLE_AHB_UART : INTEGER := 1;
66 66 ENABLE_APB_UART : INTEGER := 1;
67 67 ENABLE_IRQMP : INTEGER := 1;
68 68 ENABLE_GPT : INTEGER := 1;
69 69 --
70 70 NB_AHB_MASTER : INTEGER := 1;
71 71 NB_AHB_SLAVE : INTEGER := 1;
72 72 NB_APB_SLAVE : INTEGER := 1;
73 73 --
74 ADDRESS_SIZE : INTEGER := 20;
75 USES_IAP_MEMCTRLR : INTEGER := 0;
74 ADDRESS_SIZE : INTEGER := 19;
75 USES_IAP_MEMCTRLR : INTEGER := 1;
76 76 BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0';
77 77 SRBANKSZ : INTEGER := 8
78 78
79 79 );
80 80 PORT (
81 81 clk : IN STD_ULOGIC;
82 82 reset : IN STD_ULOGIC;
83 83
84 84 errorn : OUT STD_ULOGIC;
85 85
86 86 -- UART AHB ---------------------------------------------------------------
87 87 ahbrxd : IN STD_ULOGIC; -- DSU rx data
88 88 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
89 89
90 90 -- UART APB ---------------------------------------------------------------
91 91 urxd1 : IN STD_ULOGIC; -- UART1 rx data
92 92 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
93 93
94 94 -- RAM --------------------------------------------------------------------
95 95 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
96 96 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 97 nSRAM_BE0 : OUT STD_LOGIC;
98 98 nSRAM_BE1 : OUT STD_LOGIC;
99 99 nSRAM_BE2 : OUT STD_LOGIC;
100 100 nSRAM_BE3 : OUT STD_LOGIC;
101 101 nSRAM_WE : OUT STD_LOGIC;
102 102 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
103 103 nSRAM_OE : OUT STD_LOGIC;
104 104 nSRAM_READY : IN STD_LOGIC;
105 105 SRAM_MBE : INOUT STD_LOGIC;
106 106 -- APB --------------------------------------------------------------------
107 107 apbi_ext : OUT apb_slv_in_type;
108 108 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
109 109 -- AHB_Slave --------------------------------------------------------------
110 110 ahbi_s_ext : OUT ahb_slv_in_type;
111 111 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
112 112 -- AHB_Master -------------------------------------------------------------
113 113 ahbi_m_ext : OUT AHB_Mst_In_Type;
114 114 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
115 115
116 116 );
117 117 END;
118 118
119 119 ARCHITECTURE Behavioral OF leon3_soc IS
120 120
121 121 -----------------------------------------------------------------------------
122 122 -- CONFIG -------------------------------------------------------------------
123 123 -----------------------------------------------------------------------------
124 124
125 125 -- Clock generator
126 126 CONSTANT CFG_CLKMUL : INTEGER := (1);
127 127 CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
128 128 CONSTANT CFG_OCLKDIV : INTEGER := (1);
129 129 CONSTANT CFG_CLK_NOFB : INTEGER := 0;
130 130 -- LEON3 processor core
131 131 CONSTANT CFG_LEON3 : INTEGER := 1;
132 132 CONSTANT CFG_NCPU : INTEGER := NB_CPU;
133 133 CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
134 134 CONSTANT CFG_V8 : INTEGER := 0;
135 135 CONSTANT CFG_MAC : INTEGER := 0;
136 136 CONSTANT CFG_SVT : INTEGER := 0;
137 137 CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
138 138 CONSTANT CFG_LDDEL : INTEGER := (1);
139 139 CONSTANT CFG_NWP : INTEGER := (0);
140 140 CONSTANT CFG_PWD : INTEGER := 1*2;
141 141 CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
142 142 -- 1*(8 + 16 * 0) => grfpu-light
143 143 -- 1*(8 + 16 * 1) => netlist
144 144 -- 0*(8 + 16 * 0) => No FPU
145 145 -- 0*(8 + 16 * 1) => No FPU;
146 146 CONSTANT CFG_ICEN : INTEGER := 1;
147 147 CONSTANT CFG_ISETS : INTEGER := 1;
148 148 CONSTANT CFG_ISETSZ : INTEGER := 4;
149 149 CONSTANT CFG_ILINE : INTEGER := 4;
150 150 CONSTANT CFG_IREPL : INTEGER := 0;
151 151 CONSTANT CFG_ILOCK : INTEGER := 0;
152 152 CONSTANT CFG_ILRAMEN : INTEGER := 0;
153 153 CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
154 154 CONSTANT CFG_ILRAMSZ : INTEGER := 1;
155 155 CONSTANT CFG_DCEN : INTEGER := 1;
156 156 CONSTANT CFG_DSETS : INTEGER := 1;
157 157 CONSTANT CFG_DSETSZ : INTEGER := 4;
158 158 CONSTANT CFG_DLINE : INTEGER := 4;
159 159 CONSTANT CFG_DREPL : INTEGER := 0;
160 160 CONSTANT CFG_DLOCK : INTEGER := 0;
161 161 CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
162 162 CONSTANT CFG_DLRAMEN : INTEGER := 0;
163 163 CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
164 164 CONSTANT CFG_DLRAMSZ : INTEGER := 1;
165 165 CONSTANT CFG_MMUEN : INTEGER := 0;
166 166 CONSTANT CFG_ITLBNUM : INTEGER := 2;
167 167 CONSTANT CFG_DTLBNUM : INTEGER := 2;
168 168 CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
169 169 CONSTANT CFG_TLB_REP : INTEGER := 1;
170 170
171 171 CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
172 172 CONSTANT CFG_ITBSZ : INTEGER := 0;
173 173 CONSTANT CFG_ATBSZ : INTEGER := 0;
174 174
175 175 -- AMBA settings
176 176 CONSTANT CFG_DEFMST : INTEGER := (0);
177 177 CONSTANT CFG_RROBIN : INTEGER := 1;
178 178 CONSTANT CFG_SPLIT : INTEGER := 0;
179 179 CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
180 180 CONSTANT CFG_APBADDR : INTEGER := 16#800#;
181 181
182 182 -- DSU UART
183 183 CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
184 184
185 185 -- LEON2 memory controller
186 186 CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
187 187
188 188 -- UART 1
189 189 CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
190 190 CONSTANT CFG_UART1_FIFO : INTEGER := 1;
191 191
192 192 -- LEON3 interrupt controller
193 193 CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
194 194
195 195 -- Modular timer
196 196 CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
197 197 CONSTANT CFG_GPT_NTIM : INTEGER := (2);
198 198 CONSTANT CFG_GPT_SW : INTEGER := (8);
199 199 CONSTANT CFG_GPT_TW : INTEGER := (32);
200 200 CONSTANT CFG_GPT_IRQ : INTEGER := (8);
201 201 CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
202 202 CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
203 203 CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
204 204 -----------------------------------------------------------------------------
205 205
206 206 -----------------------------------------------------------------------------
207 207 -- SIGNALs
208 208 -----------------------------------------------------------------------------
209 209 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
210 210 -- CLK & RST --
211 211 SIGNAL clk2x : STD_ULOGIC;
212 212 SIGNAL clkmn : STD_ULOGIC;
213 213 SIGNAL clkm : STD_ULOGIC;
214 214 SIGNAL rstn : STD_ULOGIC;
215 215 SIGNAL rstraw : STD_ULOGIC;
216 216 SIGNAL pciclk : STD_ULOGIC;
217 217 SIGNAL sdclkl : STD_ULOGIC;
218 218 SIGNAL cgi : clkgen_in_type;
219 219 SIGNAL cgo : clkgen_out_type;
220 220 --- AHB / APB
221 221 SIGNAL apbi : apb_slv_in_type;
222 222 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
223 223 SIGNAL ahbsi : ahb_slv_in_type;
224 224 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
225 225 SIGNAL ahbmi : ahb_mst_in_type;
226 226 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
227 227 --UART
228 228 SIGNAL ahbuarti : uart_in_type;
229 229 SIGNAL ahbuarto : uart_out_type;
230 230 SIGNAL apbuarti : uart_in_type;
231 231 SIGNAL apbuarto : uart_out_type;
232 232 --MEM CTRLR
233 233 SIGNAL memi : memory_in_type;
234 234 SIGNAL memo : memory_out_type;
235 235 SIGNAL wpo : wprot_out_type;
236 236 SIGNAL sdo : sdram_out_type;
237 237 SIGNAL mbe : STD_LOGIC; -- enable memory programming
238 238 SIGNAL mbe_drive : STD_LOGIC; -- drive the MBE memory signal
239 239 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
240 240 SIGNAL nSRAM_OE_s : STD_LOGIC;
241 241 --IRQ
242 242 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
243 243 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
244 244 --Timer
245 245 SIGNAL gpti : gptimer_in_type;
246 246 SIGNAL gpto : gptimer_out_type;
247 247 --DSU
248 248 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
249 249 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
250 250 SIGNAL dsui : dsu_in_type;
251 251 SIGNAL dsuo : dsu_out_type;
252 252 -----------------------------------------------------------------------------
253 253
254 254
255 255 BEGIN
256 256
257 257
258 258 ----------------------------------------------------------------------
259 259 --- Reset and Clock generation -------------------------------------
260 260 ----------------------------------------------------------------------
261 261
262 262 cgi.pllctrl <= "00";
263 263 cgi.pllrst <= rstraw;
264 264
265 265 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
266 266
267 267 clkgen0 : clkgen -- clock generator
268 268 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
269 269 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
270 270 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
271 271
272 272 ----------------------------------------------------------------------
273 273 --- LEON3 processor / DSU / IRQ ------------------------------------
274 274 ----------------------------------------------------------------------
275 275
276 276 l3 : IF CFG_LEON3 = 1 GENERATE
277 277 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
278 278 leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
279 u0 : ENTITY gaisler.leon3s -- LEON3 processor
279 u0 : leon3s -- LEON3 processor
280 280 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
281 281 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
282 282 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
283 283 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
284 284 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
285 285 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
286 286 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
287 287 irqi(i), irqo(i), dbgi(i), dbgo(i));
288 288 END GENERATE leon3_non_radhard;
289 289
290 290 leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
291 cpu : ENTITY gaisler.leon3ft
291 cpu : leon3ft
292 292 GENERIC MAP (
293 293 HINDEX => i, --: integer; --CPU_HINDEX,
294 294 FABTECH => fabtech, --CFG_TECH,
295 295 MEMTECH => memtech, --CFG_TECH,
296 296 NWINDOWS => CFG_NWIN, --CFG_NWIN,
297 297 DSU => CFG_DSU, --condSel (HAS_DEBUG, 1, 0),
298 298 FPU => CFG_FPU, --CFG_FPU,
299 299 V8 => CFG_V8, --CFG_V8,
300 300 CP => 0, --CFG_CP,
301 301 MAC => CFG_MAC, --CFG_MAC,
302 302 PCLOW => pclow, --CFG_PCLOW,
303 303 NOTAG => 0, --CFG_NOTAG,
304 304 NWP => CFG_NWP, --CFG_NWP,
305 305 ICEN => CFG_ICEN, --CFG_ICEN,
306 306 IREPL => CFG_IREPL, --CFG_IREPL,
307 307 ISETS => CFG_ISETS, --CFG_ISETS,
308 308 ILINESIZE => CFG_ILINE, --CFG_ILINE,
309 309 ISETSIZE => CFG_ISETSZ, --CFG_ISETSZ,
310 310 ISETLOCK => CFG_ILOCK, --CFG_ILOCK,
311 311 DCEN => CFG_DCEN, --CFG_DCEN,
312 312 DREPL => CFG_DREPL, --CFG_DREPL,
313 313 DSETS => CFG_DSETS, --CFG_DSETS,
314 314 DLINESIZE => CFG_DLINE, --CFG_DLINE,
315 315 DSETSIZE => CFG_DSETSZ, --CFG_DSETSZ,
316 316 DSETLOCK => CFG_DLOCK, --CFG_DLOCK,
317 317 DSNOOP => CFG_DSNOOP, --CFG_DSNOOP,
318 318 ILRAM => CFG_ILRAMEN, --CFG_ILRAMEN,
319 319 ILRAMSIZE => CFG_ILRAMSZ, --CFG_ILRAMSZ,
320 320 ILRAMSTART => CFG_ILRAMADDR, --CFG_ILRAMADDR,
321 321 DLRAM => CFG_DLRAMEN, --CFG_DLRAMEN,
322 322 DLRAMSIZE => CFG_DLRAMSZ, --CFG_DLRAMSZ,
323 323 DLRAMSTART => CFG_DLRAMADDR, --CFG_DLRAMADDR,
324 324 MMUEN => CFG_MMUEN, --CFG_MMUEN,
325 325 ITLBNUM => CFG_ITLBNUM, --CFG_ITLBNUM,
326 326 DTLBNUM => CFG_DTLBNUM, --CFG_DTLBNUM,
327 327 TLB_TYPE => CFG_TLB_TYPE, --CFG_TLB_TYPE,
328 328 TLB_REP => CFG_TLB_REP, --CFG_TLB_REP,
329 329 LDDEL => CFG_LDDEL, --CFG_LDDEL,
330 330 DISAS => disas, --condSel (SIM_ENABLED, 1, 0),
331 331 TBUF => CFG_ITBSZ, --CFG_ITBSZ,
332 332 PWD => CFG_PWD, --CFG_PWD,
333 333 SVT => CFG_SVT, --CFG_SVT,
334 334 RSTADDR => CFG_RSTADDR, --CFG_RSTADDR,
335 335 SMP => CFG_NCPU-1, --CFG_NCPU-1,
336 336 IUFT => 2, --: integer range 0 to 4;--CFG_IUFT_EN,
337 337 FPFT => 1, --: integer range 0 to 4;--CFG_FPUFT_EN,
338 338 CMFT => 1, --: integer range 0 to 1;--CFG_CACHE_FT_EN,
339 339 IUINJ => 0, --: integer; --CFG_RF_ERRINJ,
340 340 CEINJ => 0, --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
341 341 CACHED => 0, --: integer; --CFG_DFIXED,
342 342 NETLIST => 0, --: integer; --CFG_LEON3_NETLIST,
343 343 SCANTEST => 0, --: integer; --CFG_SCANTEST,
344 344 MMUPGSZ => 0, --: integer range 0 to 5;--CFG_MMU_PAGE,
345 345 BP => 1) --CFG_BP
346 346 PORT MAP ( --
347 347 rstn => rstn, --rst_n,
348 348 clk => clkm, --clk,
349 349 ahbi => ahbmi, --ahbmi,
350 350 ahbo => ahbmo(i), --ahbmo(CPU_HINDEX),
351 351 ahbsi => ahbsi, --ahbsi,
352 352 ahbso => ahbso, --ahbso,
353 353 irqi => irqi(i), --irqi(CPU_HINDEX),
354 354 irqo => irqo(i), --irqo(CPU_HINDEX),
355 355 dbgi => dbgi(i), --dbgi(CPU_HINDEX),
356 356 dbgo => dbgo(i), --dbgo(CPU_HINDEX),
357 357 gclk => clkm --clk
358 358 );
359 359 END GENERATE leon3_radhard_i;
360 360
361 361 END GENERATE;
362 362 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
363 363
364 364 dsugen : IF CFG_DSU = 1 GENERATE
365 365 dsu0 : dsu3 -- LEON3 Debug Support Unit
366 366 GENERIC MAP (hindex => 0, -- TODO : hindex => 2
367 367 haddr => 16#900#, hmask => 16#F00#,
368 368 ncpu => CFG_NCPU, tbits => 30, tech => memtech,
369 369 irq => 0, kbytes => CFG_ATBSZ)
370 370 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(0),-- TODO :ahbso(2)
371 371 dbgo, dbgi, dsui, dsuo);
372 372 dsui.enable <= '1';
373 373 dsui.break <= '0';
374 374 END GENERATE;
375 375 END GENERATE;
376 376
377 377 nodsu : IF CFG_DSU = 0 GENERATE
378 378 ahbso(0) <= ahbs_none;
379 379 dsuo.tstop <= '0';
380 380 dsuo.active <= '0';
381 381 END GENERATE;
382 382
383 383 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
384 384 irqctrl0 : irqmp -- interrupt controller
385 385 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
386 386 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
387 387 END GENERATE;
388 388 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
389 389 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
390 390 irqi(i).irl <= "0000";
391 391 END GENERATE;
392 392 apbo(2) <= apb_none;
393 393 END GENERATE;
394 394
395 395 ----------------------------------------------------------------------
396 396 --- Memory controllers ---------------------------------------------
397 397 ----------------------------------------------------------------------
398 398 ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE
399 399 memctrlr : mctrl GENERIC MAP (
400 400 hindex => 2,
401 401 pindex => 0,
402 402 paddr => 0,
403 403 srbanks => 1
404 404 )
405 405 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(2), apbi, apbo(0), wpo, sdo);
406 406 memi.bexcn <= '1';
407 407 memi.brdyn <= '1';
408 408
409 409 nSRAM_CE_s <= NOT (memo.ramsn(1 DOWNTO 0));
410 410 nSRAM_OE_s <= memo.ramoen(0);
411 411 END GENERATE;
412 412
413 413 IAPMEMCT : IF USES_IAP_MEMCTRLR = 1 GENERATE
414 414 memctrlr : srctrle_0ws
415 415 GENERIC MAP(
416 416 hindex => 2, -- TODO : hindex => 0
417 417 pindex => 0,
418 418 paddr => 0,
419 419 srbanks => 2,
420 420 banksz => SRBANKSZ, --512k * 32
421 421 rmw => 1,
422 422 --Aeroflex memory generics:
423 423 mbpedac => BYPASS_EDAC_MEMCTRLR,
424 424 mprog => 1, -- program memory by default values after reset
425 425 mpsrate => 15, -- default scrub rate period
426 426 mpb2s => 14, -- default busy to scrub delay
427 427 mpapb => 1, -- instantiate apb register
428 428 mchipcnt => 2,
429 429 mpenall => 1 -- when 0 program only E1 chip, else program all dies
430 430 )
431 431 PORT MAP (
432 432 rst => rstn,
433 433 clk => clkm,
434 434 ahbsi => ahbsi,
435 435 ahbso => ahbso(2), -- TODO :ahbso(0),
436 436 apbi => apbi,
437 437 apbo => apbo(0),
438 438 sri => memi,
439 439 sro => memo,
440 440 --Aeroflex memory signals:
441 441 ucerr => OPEN, -- uncorrectable error signal
442 442 mbe => mbe, -- enable memory programming
443 443 mbe_drive => mbe_drive -- drive the MBE memory signal
444 444 );
445 445
446 446 memi.brdyn <= nSRAM_READY;
447 447
448 448 mbe_pad : iopad
449 449 GENERIC MAP(tech => padtech, oepol => USES_IAP_MEMCTRLR)
450 450 PORT MAP(pad => SRAM_MBE,
451 451 i => mbe,
452 452 en => mbe_drive,
453 453 o => memi.bexcn);
454 454
455 455 nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
456 456 nSRAM_OE_s <= memo.oen;
457 457
458 458 END GENERATE;
459 459
460 460
461 461 memi.writen <= '1';
462 462 memi.wrn <= "1111";
463 463 memi.bwidth <= "10";
464 464
465 465 bdr : FOR i IN 0 TO 3 GENERATE
466 466 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
467 467 PORT MAP (
468 468 data(31-i*8 DOWNTO 24-i*8),
469 469 memo.data(31-i*8 DOWNTO 24-i*8),
470 470 memo.bdrive(i),
471 471 memi.data(31-i*8 DOWNTO 24-i*8));
472 472 END GENERATE;
473 473
474 474 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
475 475 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
476 476 rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
477 477 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
478 478 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
479 479 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
480 480 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
481 481 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
482 482 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
483 483
484 484
485 485
486 486 ----------------------------------------------------------------------
487 487 --- AHB CONTROLLER -------------------------------------------------
488 488 ----------------------------------------------------------------------
489 489 ahb0 : ahbctrl -- AHB arbiter/multiplexer
490 490 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
491 491 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
492 492 ioen => 0, nahbm => maxahbmsp, nahbs => 8, fixbrst => 0)
493 493 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
494 494
495 495 ----------------------------------------------------------------------
496 496 --- AHB UART -------------------------------------------------------
497 497 ----------------------------------------------------------------------
498 498 dcomgen : IF CFG_AHB_UART = 1 GENERATE
499 499 dcom0 : ahbuart
500 500 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
501 501 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
502 502 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
503 503 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
504 504 END GENERATE;
505 505 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
506 506
507 507 ----------------------------------------------------------------------
508 508 --- APB Bridge -----------------------------------------------------
509 509 ----------------------------------------------------------------------
510 510 apb0 : apbctrl -- AHB/APB bridge
511 511 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
512 512 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
513 513
514 514 ----------------------------------------------------------------------
515 515 --- GPT Timer ------------------------------------------------------
516 516 ----------------------------------------------------------------------
517 517 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
518 518 timer0 : gptimer -- timer unit
519 519 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
520 520 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
521 521 nbits => CFG_GPT_TW)
522 522 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
523 523 gpti.dhalt <= dsuo.tstop;
524 524 gpti.extclk <= '0';
525 525 END GENERATE;
526 526 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
527 527
528 528
529 529 ----------------------------------------------------------------------
530 530 --- APB UART -------------------------------------------------------
531 531 ----------------------------------------------------------------------
532 532 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
533 533 uart1 : apbuart -- UART 1
534 534 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
535 535 fifosize => CFG_UART1_FIFO)
536 536 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
537 537 apbuarti.rxd <= urxd1;
538 538 apbuarti.extclk <= '0';
539 539 utxd1 <= apbuarto.txd;
540 540 apbuarti.ctsn <= '0';
541 541 END GENERATE;
542 542 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
543 543
544 544 -------------------------------------------------------------------------------
545 545 -- AMBA BUS -------------------------------------------------------------------
546 546 -------------------------------------------------------------------------------
547 547
548 548 -- APB --------------------------------------------------------------------
549 549 apbi_ext <= apbi;
550 550 all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
551 551 max_16_apb : IF I + 5 < 16 GENERATE
552 552 apbo(I+5) <= apbo_ext(I+5);
553 553 END GENERATE max_16_apb;
554 554 END GENERATE all_apb;
555 555 -- AHB_Slave --------------------------------------------------------------
556 556 ahbi_s_ext <= ahbsi;
557 557 all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
558 558 max_16_ahbs : IF I + 3 < 16 GENERATE
559 559 ahbso(I+3) <= ahbo_s_ext(I+3);
560 560 END GENERATE max_16_ahbs;
561 561 END GENERATE all_ahbs;
562 562 -- AHB_Master -------------------------------------------------------------
563 563 ahbi_m_ext <= ahbmi;
564 564 all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
565 565 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
566 566 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
567 567 END GENERATE max_16_ahbm;
568 568 END GENERATE all_ahbm;
569 569
570 570
571 571
572 572 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,262 +1,257
1 1 LIBRARY IEEE;
2 2 USE IEEE.std_logic_1164.ALL;
3 3
4 4 LIBRARY lpp;
5 5 USE lpp.general_purpose.ALL;
6 6
7 7 ENTITY MS_calculation IS
8 8 PORT (
9 9 clk : IN STD_LOGIC;
10 10 rstn : IN STD_LOGIC;
11 11 -- IN
12 12 fifo_in_data : IN STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
13 13 fifo_in_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
14 14 fifo_in_empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
15 15 -- OUT
16 16 fifo_out_data : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0);
17 17 fifo_out_wen : OUT STD_LOGIC;
18 18 fifo_out_full : IN STD_LOGIC;
19 19 --
20 20 correlation_start : IN STD_LOGIC;
21 21 correlation_auto : IN STD_LOGIC; -- 1 => auto correlation / 0 => inter correlation
22 22
23 23 correlation_begin : OUT STD_LOGIC;
24 24 correlation_done : OUT STD_LOGIC
25 25 );
26 26 END MS_calculation;
27 27
28 28 ARCHITECTURE beh OF MS_calculation IS
29 29
30 30 TYPE fsm_calculation_MS IS (IDLE, WF, S1, S2, S3, S4, WFa, S1a, S2a);
31 31 SIGNAL state : fsm_calculation_MS;
32 32
33 33 SIGNAL OP1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
34 34 SIGNAL OP2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
35 35 SIGNAL RES : STD_LOGIC_VECTOR(31 DOWNTO 0);
36 36
37 37 SIGNAL ALU_CTRL : STD_LOGIC_VECTOR(4 DOWNTO 0);
38 38
39 39
40 40 CONSTANT ALU_CTRL_NOP : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000";
41 41 CONSTANT ALU_CTRL_MULT : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00010";
42 42 CONSTANT ALU_CTRL_MAC : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00001";
43 43 CONSTANT ALU_CTRL_MACn : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10001";
44 44
45 45 SIGNAL select_ctrl : STD_LOGIC_VECTOR(1 DOWNTO 0);
46 46 CONSTANT select_ctrl_NOP : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
47 47 CONSTANT select_ctrl_MULT : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
48 48 CONSTANT select_ctrl_MAC : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
49 49 CONSTANT select_ctrl_MACn : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
50 50
51 51 SIGNAL select_op1 : STD_LOGIC;
52 52 SIGNAL select_op2 : STD_LOGIC_VECTOR(1 DOWNTO 0) ;
53 53
54 54 CONSTANT select_R0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
55 55 CONSTANT select_I0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
56 56 CONSTANT select_R1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
57 57 CONSTANT select_I1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
58 58
59 59 SIGNAL res_wen : STD_LOGIC;
60 60 SIGNAL res_wen_reg1 : STD_LOGIC;
61 61 SIGNAL res_wen_reg2 : STD_LOGIC;
62 62 --SIGNAL res_wen_reg3 : STD_LOGIC;
63 63
64 64 SIGNAL fifo_in_ren_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
65 65
66 66
67 SIGNAL fifo_in_empty_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
68
69
70 67 BEGIN
71 68
72 69
73 70 --PROCESS (clk, rstn)
74 71 --BEGIN -- PROCESS
75 72 -- IF rstn = '0' THEN -- asynchronous reset (active low)
76 73 -- fifo_in_ren <= "11";
77 74 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
78 75 -- fifo_in_ren <= fifo_in_ren_s;
79 76 -- END IF;
80 77 --END PROCESS;
81 78
82 79 fifo_in_ren <= fifo_in_ren_s;
83 80
84 81 PROCESS (clk, rstn)
85 82 BEGIN
86 83 IF rstn = '0' THEN
87 84
88 85 correlation_begin <= '0';
89 86 correlation_done <= '0';
90 87 state <= IDLE;
91 88 fifo_in_ren_s <= "11";
92 89 select_ctrl <= select_ctrl_NOP;
93 90 --ALU_CTRL <= ALU_CTRL_NOP;
94 91 select_op1 <= select_R0(0);
95 92 select_op2 <= select_R0;
96 93 res_wen <= '1';
97 fifo_in_empty_reg <= "11";
98 94
99 95 ELSIF clk'EVENT AND clk = '1' THEN
100 96 select_ctrl <= select_ctrl_NOP;
101 97 --ALU_CTRL <= ALU_CTRL_NOP;
102 98 correlation_begin <= '0';
103 99 fifo_in_ren_s <= "11";
104 100 res_wen <= '1';
105 101 correlation_done <= '0';
106 fifo_in_empty_reg <= fifo_in_empty;
107 102 CASE state IS
108 103 WHEN IDLE =>
109 104 IF correlation_start = '1' THEN
110 105 IF correlation_auto = '1' THEN
111 106 IF fifo_out_full = '1' THEN
112 107 state <= WFa;
113 108 ELSE
114 109 correlation_begin <= '1';
115 110 state <= S1a;
116 111 --fifo_in_ren_s <= "10";
117 112 END IF;
118 113 ELSE
119 114 IF fifo_out_full = '1' THEN
120 115 state <= WF;
121 116 ELSE
122 117 correlation_begin <= '1';
123 118 state <= S1;
124 119 --fifo_in_ren_s <= "00";
125 120 END IF;
126 121 END IF;
127 122 END IF;
128 123
129 124 ---------------------------------------------------------------------
130 125 -- INTER CORRELATION
131 126 ---------------------------------------------------------------------
132 127 WHEN WF =>
133 128 IF fifo_out_full = '0' THEN
134 129 correlation_begin <= '1';
135 130 state <= S1;
136 131 --fifo_in_ren_s <= "00";
137 132 END IF;
138 133 WHEN S1 =>
139 134 select_ctrl <= select_ctrl_MULT;
140 135 --ALU_CTRL <= ALU_CTRL_MULT;
141 136 select_op1 <= select_R0(0);
142 137 select_op2 <= select_R1;
143 138 state <= S2;
144 139 WHEN S2 =>
145 140 select_ctrl <= select_ctrl_MAC;
146 141 --ALU_CTRL <= ALU_CTRL_MAC;
147 142 select_op1 <= select_I0(0);
148 143 select_op2 <= select_I1;
149 144 res_wen <= '0';
150 145 state <= S3;
151 146 WHEN S3 =>
152 147 select_ctrl <= select_ctrl_MULT;
153 148 --ALU_CTRL <= ALU_CTRL_MULT;
154 149 select_op1 <= select_I0(0);
155 150 select_op2 <= select_R1;
156 151 fifo_in_ren_s <= fifo_in_empty;
157 152 state <= S4;
158 153 WHEN S4 =>
159 154 select_ctrl <= select_ctrl_MACn;
160 155 --ALU_CTRL <= ALU_CTRL_MACn;
161 156 select_op1 <= select_R0(0);
162 157 select_op2 <= select_I1;
163 158 res_wen <= '0';
164 159 IF fifo_in_empty = "00" THEN
165 160 state <= S1;
166 161 -- fifo_in_ren_s <= "00";
167 162 ELSE
168 163 correlation_done <= '1';
169 164 state <= IDLE;
170 165 END IF;
171 166
172 167
173 168
174 169 ---------------------------------------------------------------------
175 170 -- AUTO CORRELATION
176 171 ---------------------------------------------------------------------
177 172 WHEN WFa =>
178 173 IF fifo_out_full = '0' THEN
179 174 correlation_begin <= '1';
180 175 state <= S1a;
181 176 --fifo_in_ren_s <= "10";
182 177 END IF;
183 178 WHEN S1a =>
184 179 select_ctrl <= select_ctrl_MULT;
185 180 --ALU_CTRL <= ALU_CTRL_MULT;
186 181 select_op1 <= select_R0(0);
187 182 select_op2 <= select_R0;
188 183 fifo_in_ren_s(0) <= fifo_in_empty(0);
189 184 state <= S2a;
190 185 WHEN S2a =>
191 186 select_ctrl <= select_ctrl_MAC;
192 187 --ALU_CTRL <= ALU_CTRL_MAC;
193 188 select_op1 <= select_I0(0);
194 189 select_op2 <= select_I0;
195 190 res_wen <= '0';
196 191 IF fifo_in_empty(0) = '0' THEN
197 192 state <= S1a;
198 193 --fifo_in_ren_s <= "10";
199 194 ELSE
200 195 correlation_done <= '1';
201 196 state <= IDLE;
202 197 END IF;
203 198
204 199
205 200 WHEN OTHERS => NULL;
206 201 END CASE;
207 202
208 203 END IF;
209 204 END PROCESS;
210 205
211 206 ALU_CTRL <= ALU_CTRL_NOP WHEN select_ctrl = select_ctrl_NOP ELSE
212 207 ALU_CTRL_MULT WHEN select_ctrl = select_ctrl_MULT ELSE
213 208 ALU_CTRL_MAC WHEN select_ctrl = select_ctrl_MAC ELSE
214 209 ALU_CTRL_MACn;
215 210
216 211 OP1 <= fifo_in_data(15 DOWNTO 0) WHEN select_op1 = select_R0(0) ELSE
217 212 fifo_in_data(31 DOWNTO 16); -- WHEN select_op1 = select_I0(0) ELSE
218 213
219 214 OP2 <= fifo_in_data(15 DOWNTO 0) WHEN select_op2 = select_R0 ELSE
220 215 fifo_in_data(31 DOWNTO 16) WHEN select_op2 = select_I0 ELSE
221 216 fifo_in_data(47 DOWNTO 32) WHEN select_op2 = select_R1 ELSE
222 217 fifo_in_data(63 DOWNTO 48); -- WHEN select_op2 = select_I1 ELSE
223 218
224 219 ALU_MS : ALU
225 220 GENERIC MAP (
226 221 Arith_en => 1,
227 222 Logic_en => 0,
228 223 Input_SZ_1 => 16,
229 224 Input_SZ_2 => 16,
230 225 COMP_EN => 0) -- 0> Enable and 1> Disable
231 226 PORT MAP (
232 227 clk => clk,
233 228 reset => rstn,
234 229
235 230 ctrl => ALU_CTRL(2 DOWNTO 0),
236 231 comp => ALU_CTRL(4 DOWNTO 3),
237 232
238 233 OP1 => OP1,
239 234 OP2 => OP2,
240 235
241 236 RES => RES);
242 237
243 238 fifo_out_data <= RES;
244 239
245 240
246 241 PROCESS (clk, rstn)
247 242 BEGIN
248 243 IF rstn = '0' THEN
249 244 res_wen_reg1 <= '1';
250 245 res_wen_reg2 <= '1';
251 246 --res_wen_reg3 <= '1';
252 247 fifo_out_wen <= '1';
253 248 ELSIF clk'event AND clk = '1' THEN
254 249 res_wen_reg1 <= res_wen;
255 250 res_wen_reg2 <= res_wen_reg1;
256 251 --res_wen_reg3 <= res_wen_reg2;
257 252 fifo_out_wen <= res_wen_reg2;
258 253 END IF;
259 254 END PROCESS;
260 255
261 256
262 END beh;
257 END beh; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,602 +1,599
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 10 USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.lpp_dma_pkg.ALL;
12 12 USE lpp.lpp_top_lfr_pkg.ALL;
13 13 USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.general_purpose.ALL;
15 15
16 16 LIBRARY techmap;
17 17 USE techmap.gencomp.ALL;
18 18
19 19 LIBRARY grlib;
20 20 USE grlib.amba.ALL;
21 21 USE grlib.stdlib.ALL;
22 22 USE grlib.devices.ALL;
23 23 USE GRLIB.DMA2AHB_Package.ALL;
24 24
25 25 ENTITY lpp_lfr IS
26 26 GENERIC (
27 27 Mem_use : INTEGER := use_RAM;
28 28 tech : INTEGER := inferred;
29 nb_data_by_buffer_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
31 delta_vector_size : INTEGER := 20;
29 nb_data_by_buffer_size : INTEGER := 32;
30 nb_snapshot_param_size : INTEGER := 32;
31 delta_vector_size : INTEGER := 32;
32 32 delta_vector_size_f0_2 : INTEGER := 7;
33 33
34 pindex : INTEGER := 4;
35 paddr : INTEGER := 4;
34 pindex : INTEGER := 15;
35 paddr : INTEGER := 15;
36 36 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 0;
38 pirq_wfp : INTEGER := 1;
37 pirq_ms : INTEGER := 6;
38 pirq_wfp : INTEGER := 14;
39 39
40 40 hindex : INTEGER := 2;
41 41
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"020153";
43 43
44 44 DEBUG_FORCE_DATA_DMA : INTEGER := 0
45 45
46 46 );
47 47 PORT (
48 48 clk : IN STD_LOGIC;
49 49 rstn : IN STD_LOGIC;
50 50 -- SAMPLE
51 51 sample_B : IN Samples(2 DOWNTO 0);
52 52 sample_E : IN Samples(4 DOWNTO 0);
53 53 sample_val : IN STD_LOGIC;
54 54 -- APB
55 55 apbi : IN apb_slv_in_type;
56 56 apbo : OUT apb_slv_out_type;
57 57 -- AHB
58 58 ahbi : IN AHB_Mst_In_Type;
59 59 ahbo : OUT AHB_Mst_Out_Type;
60 60 -- TIME
61 61 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
62 62 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
63 63 --
64 64 data_shaping_BW : OUT STD_LOGIC;
65 65 --
66 66 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
67 67 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
68 68 );
69 69 END lpp_lfr;
70 70
71 71 ARCHITECTURE beh OF lpp_lfr IS
72 72 SIGNAL sample_s : Samples(7 DOWNTO 0);
73 73 --
74 74 SIGNAL data_shaping_SP0 : STD_LOGIC;
75 75 SIGNAL data_shaping_SP1 : STD_LOGIC;
76 76 SIGNAL data_shaping_R0 : STD_LOGIC;
77 77 SIGNAL data_shaping_R1 : STD_LOGIC;
78 78 SIGNAL data_shaping_R2 : STD_LOGIC;
79 79 --
80 80 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
81 81 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
82 82 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
83 83 --
84 84 SIGNAL sample_f0_val : STD_LOGIC;
85 85 SIGNAL sample_f1_val : STD_LOGIC;
86 86 SIGNAL sample_f2_val : STD_LOGIC;
87 87 SIGNAL sample_f3_val : STD_LOGIC;
88 88 --
89 SIGNAL sample_f_val : STD_LOGIC_VECTOR(3 DOWNTO 0);
90 SIGNAL sample_f_data : STD_LOGIC_VECTOR((6*16)*4-1 DOWNTO 0);
91 --
92 89 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
93 90 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
94 91 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
95 92 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
96 93 --
97 94 SIGNAL sample_f0_data_sim : Samples(5 DOWNTO 0);
98 95 SIGNAL sample_f1_data_sim : Samples(5 DOWNTO 0);
99 96 SIGNAL sample_f2_data_sim : Samples(5 DOWNTO 0);
100 97 SIGNAL sample_f3_data_sim : Samples(5 DOWNTO 0);
101 98 --
102 99 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
103 100 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
104 101 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
105 102
106 103 -- SM
107 104 SIGNAL ready_matrix_f0 : STD_LOGIC;
108 105 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
109 106 SIGNAL ready_matrix_f1 : STD_LOGIC;
110 107 SIGNAL ready_matrix_f2 : STD_LOGIC;
111 108 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
112 109 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
113 110 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
114 111 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
115 112 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
116 113 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
117 114 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
118 115 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
119 116 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
120 117 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
121 118
122 119 -- WFP
123 120 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
124 121 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
125 122 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
126 123 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
127 124 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
128 125 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
129 126
130 127 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
131 128 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
132 129 SIGNAL enable_f0 : STD_LOGIC;
133 130 SIGNAL enable_f1 : STD_LOGIC;
134 131 SIGNAL enable_f2 : STD_LOGIC;
135 132 SIGNAL enable_f3 : STD_LOGIC;
136 133 SIGNAL burst_f0 : STD_LOGIC;
137 134 SIGNAL burst_f1 : STD_LOGIC;
138 135 SIGNAL burst_f2 : STD_LOGIC;
139 136
140 137 --SIGNAL run : STD_LOGIC;
141 138 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
142 139
143 140 -----------------------------------------------------------------------------
144 141 --
145 142 -----------------------------------------------------------------------------
146 143 -- SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 144 -- SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
148 145 -- SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
149 146 --f1
150 147 -- SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 148 -- SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
152 149 -- SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
153 150 --f2
154 151 -- SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 152 -- SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
156 153 -- SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
157 154 --f3
158 155 -- SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 156 -- SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
160 157 -- SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
161 158
162 159 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 160 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
164 161 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
165 162 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 163 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
167 164 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 165 -----------------------------------------------------------------------------
169 166 -- DMA RR
170 167 -----------------------------------------------------------------------------
171 168 -- SIGNAL dma_sel_valid : STD_LOGIC;
172 169 -- SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
173 170 -- SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
174 171 -- SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
175 172 -- SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
176 173
177 174 -- SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
178 175 -- SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
179 176
180 177 -----------------------------------------------------------------------------
181 178 -- DMA_REG
182 179 -----------------------------------------------------------------------------
183 180 -- SIGNAL ongoing_reg : STD_LOGIC;
184 181 -- SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
185 182 -- SIGNAL dma_send_reg : STD_LOGIC;
186 183 -- SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
187 184 -- SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
188 185 -- SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 186
190 187
191 188 -----------------------------------------------------------------------------
192 189 -- DMA
193 190 -----------------------------------------------------------------------------
194 191 -- SIGNAL dma_send : STD_LOGIC;
195 192 -- SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
196 193 -- SIGNAL dma_done : STD_LOGIC;
197 194 -- SIGNAL dma_ren : STD_LOGIC;
198 195 -- SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 196 -- SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
200 197 -- SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
201 198
202 199 -----------------------------------------------------------------------------
203 200 -- MS
204 201 -----------------------------------------------------------------------------
205 202
206 203 -- SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
207 204 -- SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
208 205 -- SIGNAL data_ms_valid : STD_LOGIC;
209 206 -- SIGNAL data_ms_valid_burst : STD_LOGIC;
210 207 -- SIGNAL data_ms_ren : STD_LOGIC;
211 208 -- SIGNAL data_ms_done : STD_LOGIC;
212 209 -- SIGNAL dma_ms_ongoing : STD_LOGIC;
213 210
214 211 -- SIGNAL run_ms : STD_LOGIC;
215 212 -- SIGNAL ms_softandhard_rstn : STD_LOGIC;
216 213
217 214 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
218 215 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
219 216 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
220 217 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
221 218
222 219
223 220 SIGNAL error_buffer_full : STD_LOGIC;
224 221 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
225 222
226 223 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
227 224 -- SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
228 225
229 226 -----------------------------------------------------------------------------
230 227 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
231 228 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
232 229 SIGNAL dma_fifo_data_forced_gen : STD_LOGIC_VECTOR(32-1 DOWNTO 0); --21-04-2015
233 230 SIGNAL dma_fifo_data_forced : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015
234 231 SIGNAL dma_fifo_data_debug : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015
235 232 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
236 233 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
237 234 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
238 235 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
239 236 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
240 237 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
241 238 SIGNAL dma_grant_error : STD_LOGIC;
242 239
243 240 SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
244 241 -----------------------------------------------------------------------------
245 242 SIGNAL sample_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
246 243 SIGNAL sample_f0_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
247 244 SIGNAL sample_f1_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
248 245 SIGNAL sample_f2_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
249 246 SIGNAL sample_f3_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
250 247
251 248 BEGIN
252 249
253 250 --apb_reg_debug_vector;
254 251 -----------------------------------------------------------------------------
255 252
256 253 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
257 254 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
258 255 sample_time <= coarse_time & fine_time;
259 256
260 257 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
261 258 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
262 259 --END GENERATE all_channel;
263 260
264 261 -----------------------------------------------------------------------------
265 262 lpp_lfr_filter_1 : lpp_lfr_filter
266 263 GENERIC MAP (
267 264 Mem_use => Mem_use)
268 265 PORT MAP (
269 266 sample => sample_s,
270 267 sample_val => sample_val,
271 268 sample_time => sample_time,
272 269 clk => clk,
273 270 rstn => rstn,
274 271 data_shaping_SP0 => data_shaping_SP0,
275 272 data_shaping_SP1 => data_shaping_SP1,
276 273 data_shaping_R0 => data_shaping_R0,
277 274 data_shaping_R1 => data_shaping_R1,
278 275 data_shaping_R2 => data_shaping_R2,
279 276 sample_f0_val => sample_f0_val,
280 277 sample_f1_val => sample_f1_val,
281 278 sample_f2_val => sample_f2_val,
282 279 sample_f3_val => sample_f3_val,
283 280 sample_f0_wdata => sample_f0_data,
284 281 sample_f1_wdata => sample_f1_data,
285 282 sample_f2_wdata => sample_f2_data,
286 283 sample_f3_wdata => sample_f3_data,
287 284 sample_f0_time => sample_f0_time,
288 285 sample_f1_time => sample_f1_time,
289 286 sample_f2_time => sample_f2_time,
290 287 sample_f3_time => sample_f3_time
291 288 );
292 289
293 290 -----------------------------------------------------------------------------
294 291 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
295 292 GENERIC MAP (
296 293 nb_data_by_buffer_size => nb_data_by_buffer_size,
297 294 -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
298 295 nb_snapshot_param_size => nb_snapshot_param_size,
299 296 delta_vector_size => delta_vector_size,
300 297 delta_vector_size_f0_2 => delta_vector_size_f0_2,
301 298 pindex => pindex,
302 299 paddr => paddr,
303 300 pmask => pmask,
304 301 pirq_ms => pirq_ms,
305 302 pirq_wfp => pirq_wfp,
306 303 top_lfr_version => top_lfr_version)
307 304 PORT MAP (
308 305 HCLK => clk,
309 306 HRESETn => rstn,
310 307 apbi => apbi,
311 308 apbo => apbo,
312 309
313 310 run_ms => OPEN,--run_ms,
314 311
315 312 ready_matrix_f0 => ready_matrix_f0,
316 313 ready_matrix_f1 => ready_matrix_f1,
317 314 ready_matrix_f2 => ready_matrix_f2,
318 315 error_buffer_full => error_buffer_full, -- TODO
319 316 error_input_fifo_write => error_input_fifo_write, -- TODO
320 317 status_ready_matrix_f0 => status_ready_matrix_f0,
321 318 status_ready_matrix_f1 => status_ready_matrix_f1,
322 319 status_ready_matrix_f2 => status_ready_matrix_f2,
323 320
324 321 matrix_time_f0 => matrix_time_f0,
325 322 matrix_time_f1 => matrix_time_f1,
326 323 matrix_time_f2 => matrix_time_f2,
327 324
328 325 addr_matrix_f0 => addr_matrix_f0,
329 326 addr_matrix_f1 => addr_matrix_f1,
330 327 addr_matrix_f2 => addr_matrix_f2,
331 328
332 329 length_matrix_f0 => length_matrix_f0,
333 330 length_matrix_f1 => length_matrix_f1,
334 331 length_matrix_f2 => length_matrix_f2,
335 332 -------------------------------------------------------------------------
336 333 --status_full => status_full, -- TODo
337 334 --status_full_ack => status_full_ack, -- TODo
338 335 --status_full_err => status_full_err, -- TODo
339 336 status_new_err => status_new_err,
340 337 data_shaping_BW => data_shaping_BW,
341 338 data_shaping_SP0 => data_shaping_SP0,
342 339 data_shaping_SP1 => data_shaping_SP1,
343 340 data_shaping_R0 => data_shaping_R0,
344 341 data_shaping_R1 => data_shaping_R1,
345 342 data_shaping_R2 => data_shaping_R2,
346 343 delta_snapshot => delta_snapshot,
347 344 delta_f0 => delta_f0,
348 345 delta_f0_2 => delta_f0_2,
349 346 delta_f1 => delta_f1,
350 347 delta_f2 => delta_f2,
351 348 nb_data_by_buffer => nb_data_by_buffer,
352 349 -- nb_word_by_buffer => nb_word_by_buffer, -- TODO
353 350 nb_snapshot_param => nb_snapshot_param,
354 351 enable_f0 => enable_f0,
355 352 enable_f1 => enable_f1,
356 353 enable_f2 => enable_f2,
357 354 enable_f3 => enable_f3,
358 355 burst_f0 => burst_f0,
359 356 burst_f1 => burst_f1,
360 357 burst_f2 => burst_f2,
361 358 run => OPEN, --run,
362 359 start_date => start_date,
363 360 -- debug_signal => debug_signal,
364 361 wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
365 362 wfp_addr_buffer => wfp_addr_buffer,-- TODO
366 363 wfp_length_buffer => wfp_length_buffer,-- TODO
367 364
368 365 wfp_ready_buffer => wfp_ready_buffer,-- TODO
369 366 wfp_buffer_time => wfp_buffer_time,-- TODO
370 367 wfp_error_buffer_full => wfp_error_buffer_full, -- TODO
371 368 -------------------------------------------------------------------------
372 369 sample_f3_v => sample_f3_data(1*16-1 DOWNTO 0*16),
373 370 sample_f3_e1 => sample_f3_data(2*16-1 DOWNTO 1*16),
374 371 sample_f3_e2 => sample_f3_data(3*16-1 DOWNTO 2*16),
375 372 sample_f3_valid => sample_f3_val,
376 373 debug_vector => apb_reg_debug_vector
377 374 );
378 375
379 376 -----------------------------------------------------------------------------
380 377 -----------------------------------------------------------------------------
381 378 lpp_waveform_1 : lpp_waveform
382 379 GENERIC MAP (
383 380 tech => tech,
384 381 data_size => 6*16,
385 382 nb_data_by_buffer_size => nb_data_by_buffer_size,
386 383 nb_snapshot_param_size => nb_snapshot_param_size,
387 384 delta_vector_size => delta_vector_size,
388 385 delta_vector_size_f0_2 => delta_vector_size_f0_2
389 386 )
390 387 PORT MAP (
391 388 clk => clk,
392 389 rstn => rstn,
393 390
394 391 reg_run => '1',--run,
395 392 reg_start_date => start_date,
396 393 reg_delta_snapshot => delta_snapshot,
397 394 reg_delta_f0 => delta_f0,
398 395 reg_delta_f0_2 => delta_f0_2,
399 396 reg_delta_f1 => delta_f1,
400 397 reg_delta_f2 => delta_f2,
401 398
402 399 enable_f0 => enable_f0,
403 400 enable_f1 => enable_f1,
404 401 enable_f2 => enable_f2,
405 402 enable_f3 => enable_f3,
406 403 burst_f0 => burst_f0,
407 404 burst_f1 => burst_f1,
408 405 burst_f2 => burst_f2,
409 406
410 407 nb_data_by_buffer => nb_data_by_buffer,
411 408 nb_snapshot_param => nb_snapshot_param,
412 409 status_new_err => status_new_err,
413 410
414 411 status_buffer_ready => wfp_status_buffer_ready,
415 412 addr_buffer => wfp_addr_buffer,
416 413 length_buffer => wfp_length_buffer,
417 414 ready_buffer => wfp_ready_buffer,
418 415 buffer_time => wfp_buffer_time,
419 416 error_buffer_full => wfp_error_buffer_full,
420 417
421 418 coarse_time => coarse_time,
422 419 -- fine_time => fine_time,
423 420
424 421 --f0
425 422 data_f0_in_valid => sample_f0_val,
426 423 data_f0_in => sample_f0_data,
427 424 data_f0_time => sample_f0_time,
428 425 --f1
429 426 data_f1_in_valid => sample_f1_val,
430 427 data_f1_in => sample_f1_data,
431 428 data_f1_time => sample_f1_time,
432 429 --f2
433 430 data_f2_in_valid => sample_f2_val,
434 431 data_f2_in => sample_f2_data,
435 432 data_f2_time => sample_f2_time,
436 433 --f3
437 434 data_f3_in_valid => sample_f3_val,
438 435 data_f3_in => sample_f3_data,
439 436 data_f3_time => sample_f3_time,
440 437 -- OUTPUT -- DMA interface
441 438
442 439 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
443 440 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
444 441 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
445 442 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
446 443 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
447 444 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
448 445 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
449 446 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
450 447
451 448 );
452 449
453 450 -----------------------------------------------------------------------------
454 451 -- Matrix Spectral
455 452 -----------------------------------------------------------------------------
456 453 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
457 454 NOT(sample_f0_val) & NOT(sample_f0_val);
458 455 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
459 456 NOT(sample_f1_val) & NOT(sample_f1_val);
460 457 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
461 458 NOT(sample_f2_val) & NOT(sample_f2_val);
462 459
463 460
464 461 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
465 462 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
466 463 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
467 464
468 465 -------------------------------------------------------------------------------
469 466
470 467 --ms_softandhard_rstn <= rstn AND run_ms AND run;
471 468
472 469 -----------------------------------------------------------------------------
473 470 lpp_lfr_ms_1 : lpp_lfr_ms
474 471 GENERIC MAP (
475 472 Mem_use => Mem_use)
476 473 PORT MAP (
477 474 clk => clk,
478 475 --rstn => ms_softandhard_rstn, --rstn,
479 476 rstn => rstn,
480 477
481 478 run => '1',--run_ms,
482 479
483 480 start_date => start_date,
484 481
485 482 coarse_time => coarse_time,
486 483
487 484 sample_f0_wen => sample_f0_wen,
488 485 sample_f0_wdata => sample_f0_wdata,
489 486 sample_f0_time => sample_f0_time,
490 487 sample_f1_wen => sample_f1_wen,
491 488 sample_f1_wdata => sample_f1_wdata,
492 489 sample_f1_time => sample_f1_time,
493 490 sample_f2_wen => sample_f2_wen,
494 491 sample_f2_wdata => sample_f2_wdata,
495 492 sample_f2_time => sample_f2_time,
496 493
497 494 --DMA
498 495 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
499 496 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
500 497 dma_fifo_ren => dma_fifo_ren(4), -- IN
501 498 dma_buffer_new => dma_buffer_new(4), -- OUT
502 499 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
503 500 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
504 501 dma_buffer_full => dma_buffer_full(4), -- IN
505 502 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
506 503
507 504
508 505
509 506 --REG
510 507 ready_matrix_f0 => ready_matrix_f0,
511 508 ready_matrix_f1 => ready_matrix_f1,
512 509 ready_matrix_f2 => ready_matrix_f2,
513 510 error_buffer_full => error_buffer_full,
514 511 error_input_fifo_write => error_input_fifo_write,
515 512
516 513 status_ready_matrix_f0 => status_ready_matrix_f0,
517 514 status_ready_matrix_f1 => status_ready_matrix_f1,
518 515 status_ready_matrix_f2 => status_ready_matrix_f2,
519 516 addr_matrix_f0 => addr_matrix_f0,
520 517 addr_matrix_f1 => addr_matrix_f1,
521 518 addr_matrix_f2 => addr_matrix_f2,
522 519
523 520 length_matrix_f0 => length_matrix_f0,
524 521 length_matrix_f1 => length_matrix_f1,
525 522 length_matrix_f2 => length_matrix_f2,
526 523
527 524 matrix_time_f0 => matrix_time_f0,
528 525 matrix_time_f1 => matrix_time_f1,
529 526 matrix_time_f2 => matrix_time_f2,
530 527
531 528 debug_vector => debug_vector_ms);
532 529
533 530 -----------------------------------------------------------------------------
534 531 PROCESS (clk, rstn)
535 532 BEGIN
536 533 IF rstn = '0' THEN
537 534 dma_fifo_data_forced_gen <= X"00040003";
538 535 ELSIF clk'event AND clk = '1' THEN
539 536 IF dma_fifo_ren(0) = '0' THEN
540 537 CASE dma_fifo_data_forced_gen IS
541 538 WHEN X"00040003" => dma_fifo_data_forced_gen <= X"00050002";
542 539 WHEN X"00050002" => dma_fifo_data_forced_gen <= X"00060001";
543 540 WHEN X"00060001" => dma_fifo_data_forced_gen <= X"00040003";
544 541 WHEN OTHERS => NULL;
545 542 END CASE;
546 543 END IF;
547 544 END IF;
548 545 END PROCESS;
549 546
550 547 dma_fifo_data_forced(32 * 1 -1 DOWNTO 32 * 0) <= dma_fifo_data_forced_gen;
551 548 dma_fifo_data_forced(32 * 2 -1 DOWNTO 32 * 1) <= X"A0000100";
552 549 dma_fifo_data_forced(32 * 3 -1 DOWNTO 32 * 2) <= X"08001000";
553 550 dma_fifo_data_forced(32 * 4 -1 DOWNTO 32 * 3) <= X"80007000";
554 551 dma_fifo_data_forced(32 * 5 -1 DOWNTO 32 * 4) <= X"0A000B00";
555 552
556 553 dma_fifo_data_debug <= dma_fifo_data WHEN DEBUG_FORCE_DATA_DMA = 0 ELSE dma_fifo_data_forced;
557 554
558 555 DMA_SubSystem_1 : DMA_SubSystem
559 556 GENERIC MAP (
560 557 hindex => hindex,
561 558 CUSTOM_DMA => 1)
562 559 PORT MAP (
563 560 clk => clk,
564 561 rstn => rstn,
565 562 run => '1',--run_dma,
566 563 ahbi => ahbi,
567 564 ahbo => ahbo,
568 565
569 566 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
570 567 fifo_data => dma_fifo_data_debug, --fifo_data,
571 568 fifo_ren => dma_fifo_ren, --fifo_ren,
572 569
573 570 buffer_new => dma_buffer_new, --buffer_new,
574 571 buffer_addr => dma_buffer_addr, --buffer_addr,
575 572 buffer_length => dma_buffer_length, --buffer_length,
576 573 buffer_full => dma_buffer_full, --buffer_full,
577 574 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
578 575 grant_error => dma_grant_error,
579 576 debug_vector => debug_vector(8 DOWNTO 0)
580 577 ); --grant_error);
581 578
582 579 -----------------------------------------------------------------------------
583 580 -- OBSERVATION for SIMULATION
584 581 all_channel_sim: FOR I IN 0 TO 5 GENERATE
585 582 PROCESS (clk, rstn)
586 583 BEGIN -- PROCESS
587 584 IF rstn = '0' THEN -- asynchronous reset (active low)
588 585 sample_f0_data_sim(I) <= (OTHERS => '0');
589 586 sample_f1_data_sim(I) <= (OTHERS => '0');
590 587 sample_f2_data_sim(I) <= (OTHERS => '0');
591 588 sample_f3_data_sim(I) <= (OTHERS => '0');
592 589 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
593 590 IF sample_f0_val = '1' THEN sample_f0_data_sim(I) <= sample_f0_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
594 591 IF sample_f1_val = '1' THEN sample_f1_data_sim(I) <= sample_f1_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
595 592 IF sample_f2_val = '1' THEN sample_f2_data_sim(I) <= sample_f2_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
596 593 IF sample_f3_val = '1' THEN sample_f3_data_sim(I) <= sample_f3_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
597 594 END IF;
598 595 END PROCESS;
599 596 END GENERATE all_channel_sim;
600 597 -----------------------------------------------------------------------------
601 598
602 END beh;
599 END beh; No newline at end of file
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23 LIBRARY IEEE;
24 24 USE IEEE.STD_LOGIC_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26
27 27 LIBRARY grlib;
28 28 USE grlib.amba.ALL;
29 29 USE grlib.stdlib.ALL;
30 30 USE grlib.devices.ALL;
31 31 USE GRLIB.DMA2AHB_Package.ALL;
32 32
33 33 LIBRARY lpp;
34 34 USE lpp.lpp_waveform_pkg.ALL;
35 35 USE lpp.iir_filter.ALL;
36 36 USE lpp.lpp_memory.ALL;
37 37
38 38 LIBRARY techmap;
39 39 USE techmap.gencomp.ALL;
40 40
41 41 ENTITY lpp_waveform IS
42 42
43 43 GENERIC (
44 44 tech : INTEGER := inferred;
45 45 data_size : INTEGER := 96; --16*6
46 46 nb_data_by_buffer_size : INTEGER := 11;
47 47 -- nb_word_by_buffer_size : INTEGER := 11;
48 48 nb_snapshot_param_size : INTEGER := 11;
49 49 delta_vector_size : INTEGER := 20;
50 50 delta_vector_size_f0_2 : INTEGER := 3);
51 51
52 52 PORT (
53 53 clk : IN STD_LOGIC;
54 54 rstn : IN STD_LOGIC;
55 55
56 56 ---- AMBA AHB Master Interface
57 57 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
58 58 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
59 59
60 60 --config
61 61 reg_run : IN STD_LOGIC;
62 62 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
63 63 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 64 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 65 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
66 66 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
67 67 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
68 68
69 69 enable_f0 : IN STD_LOGIC;
70 70 enable_f1 : IN STD_LOGIC;
71 71 enable_f2 : IN STD_LOGIC;
72 72 enable_f3 : IN STD_LOGIC;
73 73
74 74 burst_f0 : IN STD_LOGIC;
75 75 burst_f1 : IN STD_LOGIC;
76 76 burst_f2 : IN STD_LOGIC;
77 77
78 78 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
79 79 -- nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
80 80 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
81 81
82 82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
83 83
84 84
85 85 -- REG DMA
86 86 status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
87 87 addr_buffer : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
88 88 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
89 89
90 90 ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
91 91 buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
92 92 error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
93 93
94 94 ---------------------------------------------------------------------------
95 95 -- INPUT
96 96 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
97 97 -- fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
98 98
99 99 --f0
100 100 data_f0_in_valid : IN STD_LOGIC;
101 101 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
102 102 data_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
103 103 --f1
104 104 data_f1_in_valid : IN STD_LOGIC;
105 105 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
106 106 data_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
107 107 --f2
108 108 data_f2_in_valid : IN STD_LOGIC;
109 109 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
110 110 data_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
111 111 --f3
112 112 data_f3_in_valid : IN STD_LOGIC;
113 113 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
114 114 data_f3_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
115 115
116 116 ---------------------------------------------------------------------------
117 117 -- DMA --------------------------------------------------------------------
118 118
119 119 dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
120 120 dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
121 121 dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
122 122 dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
123 123 dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
124 124 dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
125 125 dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
126 126 dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
127 127
128 128 );
129 129
130 130 END lpp_waveform;
131 131
132 132 ARCHITECTURE beh OF lpp_waveform IS
133 133 SIGNAL start_snapshot_f0 : STD_LOGIC;
134 134 SIGNAL start_snapshot_f1 : STD_LOGIC;
135 135 SIGNAL start_snapshot_f2 : STD_LOGIC;
136 136
137 137 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
138 138 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
139 139 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 140 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 141
142 142 SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
143 143 SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 144 SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
145 145 SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
146 146
147 147 SIGNAL data_f0_out_valid : STD_LOGIC;
148 148 SIGNAL data_f1_out_valid : STD_LOGIC;
149 149 SIGNAL data_f2_out_valid : STD_LOGIC;
150 150 SIGNAL data_f3_out_valid : STD_LOGIC;
151 151 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
152 152 --
153 153 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 154 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 155 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 156 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 157 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
162 158 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 159 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 160 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 161 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 162 --
167 163 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
169 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
171 164 --
172 165 SIGNAL run : STD_LOGIC;
173 166 --
174 167 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
175 168 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
176 169 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
177 170 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
178 171 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
179 172 SIGNAL time_reg1 : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
180 173 SIGNAL time_reg2 : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
181 174 --
182 175
183 176 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
184 177 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
185 178 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
186 179 -- SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 180 SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
188 181
189 182 --
190 183 SIGNAL arbiter_time_out : STD_LOGIC_VECTOR(47 DOWNTO 0);
191 184 SIGNAL arbiter_time_out_new : STD_LOGIC_VECTOR(3 DOWNTO 0);
192 185
193 186 SIGNAL fifo_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
194 187
195 188 SIGNAL fifo_buffer_time_s : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
196 189
197 190 BEGIN -- beh
198 191
199 192 -----------------------------------------------------------------------------
200 193
201 194 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
202 195 GENERIC MAP (
203 196 delta_vector_size => delta_vector_size,
204 197 delta_vector_size_f0_2 => delta_vector_size_f0_2
205 198 )
206 199 PORT MAP (
207 200 clk => clk,
208 201 rstn => rstn,
209 202 reg_run => reg_run,
210 203 reg_start_date => reg_start_date,
211 204 reg_delta_snapshot => reg_delta_snapshot,
212 205 reg_delta_f0 => reg_delta_f0,
213 206 reg_delta_f0_2 => reg_delta_f0_2,
214 207 reg_delta_f1 => reg_delta_f1,
215 208 reg_delta_f2 => reg_delta_f2,
216 209 coarse_time => coarse_time(30 DOWNTO 0),
217 210 data_f0_valid => data_f0_in_valid,
218 211 data_f2_valid => data_f2_in_valid,
219 212 start_snapshot_f0 => start_snapshot_f0,
220 213 start_snapshot_f1 => start_snapshot_f1,
221 214 start_snapshot_f2 => start_snapshot_f2,
222 215 wfp_on => run);
223 216
224 217 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
225 218 GENERIC MAP (
226 219 data_size => data_size,
227 220 nb_snapshot_param_size => nb_snapshot_param_size)
228 221 PORT MAP (
229 222 clk => clk,
230 223 rstn => rstn,
231 224 run => run,
232 225 enable => enable_f0,
233 226 burst_enable => burst_f0,
234 227 nb_snapshot_param => nb_snapshot_param,
235 228 start_snapshot => start_snapshot_f0,
236 229 data_in => data_f0_in,
237 230 data_in_valid => data_f0_in_valid,
238 231 data_out => data_f0_out,
239 232 data_out_valid => data_f0_out_valid);
240 233
241 234 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
242 235
243 236 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
244 237 GENERIC MAP (
245 238 data_size => data_size,
246 239 nb_snapshot_param_size => nb_snapshot_param_size+1)
247 240 PORT MAP (
248 241 clk => clk,
249 242 rstn => rstn,
250 243 run => run,
251 244 enable => enable_f1,
252 245 burst_enable => burst_f1,
253 246 nb_snapshot_param => nb_snapshot_param_more_one,
254 247 start_snapshot => start_snapshot_f1,
255 248 data_in => data_f1_in,
256 249 data_in_valid => data_f1_in_valid,
257 250 data_out => data_f1_out,
258 251 data_out_valid => data_f1_out_valid);
259 252
260 253 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
261 254 GENERIC MAP (
262 255 data_size => data_size,
263 256 nb_snapshot_param_size => nb_snapshot_param_size+1)
264 257 PORT MAP (
265 258 clk => clk,
266 259 rstn => rstn,
267 260 run => run,
268 261 enable => enable_f2,
269 262 burst_enable => burst_f2,
270 263 nb_snapshot_param => nb_snapshot_param_more_one,
271 264 start_snapshot => start_snapshot_f2,
272 265 data_in => data_f2_in,
273 266 data_in_valid => data_f2_in_valid,
274 267 data_out => data_f2_out,
275 268 data_out_valid => data_f2_out_valid);
276 269
277 270 lpp_waveform_burst_f3 : lpp_waveform_burst
278 271 GENERIC MAP (
279 272 data_size => data_size)
280 273 PORT MAP (
281 274 clk => clk,
282 275 rstn => rstn,
283 276 run => run,
284 277 enable => enable_f3,
285 278 data_in => data_f3_in,
286 279 data_in_valid => data_f3_in_valid,
287 280 data_out => data_f3_out,
288 281 data_out_valid => data_f3_out_valid);
289 282
290 283 -----------------------------------------------------------------------------
291 284 -- DEBUG -- SNAPSHOT OUT
292 285 --debug_f0_data_valid <= data_f0_out_valid;
293 286 --debug_f0_data <= data_f0_out;
294 287 --debug_f1_data_valid <= data_f1_out_valid;
295 288 --debug_f1_data <= data_f1_out;
296 289 --debug_f2_data_valid <= data_f2_out_valid;
297 290 --debug_f2_data <= data_f2_out;
298 291 --debug_f3_data_valid <= data_f3_out_valid;
299 292 --debug_f3_data <= data_f3_out;
300 293 -----------------------------------------------------------------------------
301 294
302 295 PROCESS (clk, rstn)
303 296 BEGIN -- PROCESS
304 297 IF rstn = '0' THEN -- asynchronous reset (active low)
305 298 time_reg1 <= (OTHERS => '0');
306 299 time_reg2 <= (OTHERS => '0');
307 300 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
308 301 time_reg1(48*1-1 DOWNTO 48*0) <= data_f0_time(15 DOWNTO 0) & data_f0_time(47 DOWNTO 16);
309 302 time_reg1(48*2-1 DOWNTO 48*1) <= data_f1_time(15 DOWNTO 0) & data_f1_time(47 DOWNTO 16);
310 303 time_reg1(48*3-1 DOWNTO 48*2) <= data_f2_time(15 DOWNTO 0) & data_f2_time(47 DOWNTO 16);
311 304 time_reg1(48*4-1 DOWNTO 48*3) <= data_f3_time(15 DOWNTO 0) & data_f3_time(47 DOWNTO 16);
312 305 time_reg2 <= time_reg1;
313 306 END IF;
314 307 END PROCESS;
315 308
316 309 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
317 310 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
318 311 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
319 312 PORT MAP (
320 313 HCLK => clk,
321 314 HRESETn => rstn,
322 315 run => run,
323 316 valid_in => valid_in(I),
324 317 ack_in => valid_ack(I),
325 318 time_in => time_reg2(48*(I+1)-1 DOWNTO 48*I), -- Todo
326 319 valid_out => valid_out(I),
327 320 time_out => time_out(I), -- Todo
328 321 error => status_new_err(I));
329 322 END GENERATE all_input_valid;
330 323
331 324 data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) &
332 325 data_f0_out((16*6)-1 DOWNTO 16*5) &
333 326 data_f0_out((16*3)-1 DOWNTO 16*2) &
334 327 data_f0_out((16*4)-1 DOWNTO 16*3) &
335 328 data_f0_out((16*1)-1 DOWNTO 16*0) &
336 329 data_f0_out((16*2)-1 DOWNTO 16*1) ;
337 330
338 331 data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) &
339 332 data_f1_out((16*6)-1 DOWNTO 16*5) &
340 333 data_f1_out((16*3)-1 DOWNTO 16*2) &
341 334 data_f1_out((16*4)-1 DOWNTO 16*3) &
342 335 data_f1_out((16*1)-1 DOWNTO 16*0) &
343 336 data_f1_out((16*2)-1 DOWNTO 16*1) ;
344 337
345 338 data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) &
346 339 data_f2_out((16*6)-1 DOWNTO 16*5) &
347 340 data_f2_out((16*3)-1 DOWNTO 16*2) &
348 341 data_f2_out((16*4)-1 DOWNTO 16*3) &
349 342 data_f2_out((16*1)-1 DOWNTO 16*0) &
350 343 data_f2_out((16*2)-1 DOWNTO 16*1) ;
351 344
352 345 data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) &
353 346 data_f3_out((16*6)-1 DOWNTO 16*5) &
354 347 data_f3_out((16*3)-1 DOWNTO 16*2) &
355 348 data_f3_out((16*4)-1 DOWNTO 16*3) &
356 349 data_f3_out((16*1)-1 DOWNTO 16*0) &
357 350 data_f3_out((16*2)-1 DOWNTO 16*1) ;
358 351
359 352 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
360 353 data_out(0, I) <= data_f0_out_swap(I);
361 354 data_out(1, I) <= data_f1_out_swap(I);
362 355 data_out(2, I) <= data_f2_out_swap(I);
363 356 data_out(3, I) <= data_f3_out_swap(I);
364 357 END GENERATE all_bit_of_data_out;
365 358
366 359 -----------------------------------------------------------------------------
367 360 -- TODO : debug
368 361 -----------------------------------------------------------------------------
369 362 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
370 363 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
371 364 time_out_2(J, I) <= time_out(J)(I);
372 365 END GENERATE all_sample_of_time_out;
373 366 END GENERATE all_bit_of_time_out;
374 367
375 368 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
376 369 GENERIC MAP (tech => tech,
377 370 nb_data_by_buffer_size => nb_data_by_buffer_size)
378 371 PORT MAP (
379 372 clk => clk,
380 373 rstn => rstn,
381 374 run => run,
382 375 nb_data_by_buffer => nb_data_by_buffer,
383 376 data_in_valid => valid_out,
384 377 data_in_ack => valid_ack,
385 378 data_in => data_out,
386 379 time_in => time_out_2,
387 380
388 381 data_out => wdata,
389 382 data_out_wen => data_wen,
390 383 full_almost => full_almost,
391 384 full => full,
392 385
393 386 time_out => arbiter_time_out,
394 387 time_out_new => arbiter_time_out_new
395 388
396 389 );
397 390
398 391 -----------------------------------------------------------------------------
399 392 -----------------------------------------------------------------------------
400 393
401 394 generate_all_fifo: FOR I IN 0 TO 3 GENERATE
402 395 lpp_fifo_1: lpp_fifo
403 396 GENERIC MAP (
404 397 tech => 0,
405 398 Mem_use => use_RAM,
406 399 EMPTY_THRESHOLD_LIMIT => 15,
407 400 FULL_THRESHOLD_LIMIT => 3,
408 401 DataSz => 32,
409 402 AddrSz => 7)
410 403 PORT MAP (
411 404 clk => clk,
412 405 rstn => rstn,
413 406 reUse => '0',
414 407 run => run,
415 408 ren => data_ren(I),
416 409 rdata => s_rdata_v((I+1)*32-1 downto I*32),
417 410 wen => data_wen(I),
418 411 wdata => wdata,
419 412 empty => empty(I),
420 413 full => full(I),
421 414 full_almost => OPEN,
422 415 empty_threshold => empty_almost(I),
423 416 full_threshold => full_almost(I) );
424 417
425 418 END GENERATE generate_all_fifo;
426 419
427 420 -----------------------------------------------------------------------------
428 421 --
429 422 -----------------------------------------------------------------------------
430 423
431 424 all_channel: FOR I IN 3 DOWNTO 0 GENERATE
432 425
433 426 PROCESS (clk, rstn)
434 427 BEGIN
435 428 IF rstn = '0' THEN
436 429 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
437 430 ELSIF clk'event AND clk = '1' THEN
438 431 IF run = '0' THEN
439 432 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
440 433 ELSE
441 434 IF arbiter_time_out_new(I) = '1' THEN -- modif JC 15-01-2015
442 435 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out;
443 436 END IF;
444 437 END IF;
445 438 END IF;
446 439 END PROCESS;
447 440
448 441 fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out WHEN arbiter_time_out_new(I) = '1' ELSE
449 442 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I);
450 443
451 444 lpp_waveform_fsmdma_I: lpp_waveform_fsmdma
452 445 PORT MAP (
453 446 clk => clk,
454 447 rstn => rstn,
455 448 run => run,
456 449
457 450 fifo_buffer_time => fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I),
458 451
459 452 fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I),
460 453 fifo_empty => empty(I),
461 454 fifo_empty_threshold => empty_almost(I),
462 455 fifo_ren => data_ren(I),
463 456
464 457 dma_fifo_valid_burst => dma_fifo_valid_burst(I),
465 458 dma_fifo_data => dma_fifo_data(32*(I+1)-1 DOWNTO 32*I),
466 459 dma_fifo_ren => dma_fifo_ren(I),
467 460 dma_buffer_new => dma_buffer_new(I),
468 461 dma_buffer_addr => dma_buffer_addr(32*(I+1)-1 DOWNTO 32*I),
469 462 dma_buffer_length => dma_buffer_length(26*(I+1)-1 DOWNTO 26*I),
470 463 dma_buffer_full => dma_buffer_full(I),
471 464 dma_buffer_full_err => dma_buffer_full_err(I),
472 465
473 466 status_buffer_ready => status_buffer_ready(I), -- TODO
474 467 addr_buffer => addr_buffer(32*(I+1)-1 DOWNTO 32*I), -- TODO
475 468 length_buffer => length_buffer,--(26*(I+1)-1 DOWNTO 26*I), -- TODO
476 469 ready_buffer => ready_buffer(I), -- TODO
477 470 buffer_time => OPEN,--buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO
478 471 error_buffer_full => error_buffer_full(I)); -- TODO
479 472
480 473 buffer_time(48*(I+1)-1 DOWNTO 48*I) <= fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I);
481 474
482 475 END GENERATE all_channel;
483 476
484 477
485 END beh;
478 END beh; No newline at end of file
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