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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL; -- PLE
35 USE gaisler.spacewire.ALL; -- PLE
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 USE work.config.ALL;
38 USE work.config.ALL;
39 LIBRARY lpp;
39 LIBRARY lpp;
40 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_memory.ALL;
41 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_ad_conv.ALL;
42 USE lpp.lpp_lfr_pkg.ALL;
42 USE lpp.lpp_lfr_pkg.ALL;
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46
46
47 ENTITY MINI_LFR_top IS
47 ENTITY MINI_LFR_top IS
48
48
49 PORT (
49 PORT (
50 clk_50 : IN STD_LOGIC;
50 clk_50 : IN STD_LOGIC;
51 clk_49 : IN STD_LOGIC;
51 clk_49 : IN STD_LOGIC;
52 reset : IN STD_LOGIC;
52 reset : IN STD_LOGIC;
53 --BPs
53 --BPs
54 BP0 : IN STD_LOGIC;
54 BP0 : IN STD_LOGIC;
55 BP1 : IN STD_LOGIC;
55 BP1 : IN STD_LOGIC;
56 --LEDs
56 --LEDs
57 LED0 : OUT STD_LOGIC;
57 LED0 : OUT STD_LOGIC;
58 LED1 : OUT STD_LOGIC;
58 LED1 : OUT STD_LOGIC;
59 LED2 : OUT STD_LOGIC;
59 LED2 : OUT STD_LOGIC;
60 --UARTs
60 --UARTs
61 TXD1 : IN STD_LOGIC;
61 TXD1 : IN STD_LOGIC;
62 RXD1 : OUT STD_LOGIC;
62 RXD1 : OUT STD_LOGIC;
63 nCTS1 : OUT STD_LOGIC;
63 nCTS1 : OUT STD_LOGIC;
64 nRTS1 : IN STD_LOGIC;
64 nRTS1 : IN STD_LOGIC;
65
65
66 TXD2 : IN STD_LOGIC;
66 TXD2 : IN STD_LOGIC;
67 RXD2 : OUT STD_LOGIC;
67 RXD2 : OUT STD_LOGIC;
68 nCTS2 : OUT STD_LOGIC;
68 nCTS2 : OUT STD_LOGIC;
69 nDTR2 : IN STD_LOGIC;
69 nDTR2 : IN STD_LOGIC;
70 nRTS2 : IN STD_LOGIC;
70 nRTS2 : IN STD_LOGIC;
71 nDCD2 : OUT STD_LOGIC;
71 nDCD2 : OUT STD_LOGIC;
72
72
73 --EXT CONNECTOR
73 --EXT CONNECTOR
74 IO0 : INOUT STD_LOGIC;
74 IO0 : INOUT STD_LOGIC;
75 IO1 : INOUT STD_LOGIC;
75 IO1 : INOUT STD_LOGIC;
76 IO2 : INOUT STD_LOGIC;
76 IO2 : INOUT STD_LOGIC;
77 IO3 : INOUT STD_LOGIC;
77 IO3 : INOUT STD_LOGIC;
78 IO4 : INOUT STD_LOGIC;
78 IO4 : INOUT STD_LOGIC;
79 IO5 : INOUT STD_LOGIC;
79 IO5 : INOUT STD_LOGIC;
80 IO6 : INOUT STD_LOGIC;
80 IO6 : INOUT STD_LOGIC;
81 IO7 : INOUT STD_LOGIC;
81 IO7 : INOUT STD_LOGIC;
82 IO8 : INOUT STD_LOGIC;
82 IO8 : INOUT STD_LOGIC;
83 IO9 : INOUT STD_LOGIC;
83 IO9 : INOUT STD_LOGIC;
84 IO10 : INOUT STD_LOGIC;
84 IO10 : INOUT STD_LOGIC;
85 IO11 : INOUT STD_LOGIC;
85 IO11 : INOUT STD_LOGIC;
86
86
87 --SPACE WIRE
87 --SPACE WIRE
88 SPW_EN : OUT STD_LOGIC; -- 0 => off
88 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
89 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_SIN : IN STD_LOGIC;
90 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_DOUT : OUT STD_LOGIC;
91 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_SOUT : OUT STD_LOGIC;
92 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
93 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_SIN : IN STD_LOGIC;
94 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_DOUT : OUT STD_LOGIC;
95 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_SOUT : OUT STD_LOGIC;
96 SPW_RED_SOUT : OUT STD_LOGIC;
97 -- MINI LFR ADC INPUTS
97 -- MINI LFR ADC INPUTS
98 ADC_nCS : OUT STD_LOGIC;
98 ADC_nCS : OUT STD_LOGIC;
99 ADC_CLK : OUT STD_LOGIC;
99 ADC_CLK : OUT STD_LOGIC;
100 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
100 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101
101
102 -- SRAM
102 -- SRAM
103 SRAM_nWE : OUT STD_LOGIC;
103 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_CE : OUT STD_LOGIC;
104 SRAM_CE : OUT STD_LOGIC;
105 SRAM_nOE : OUT STD_LOGIC;
105 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
106 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
107 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
108 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 );
109 );
110
110
111 END MINI_LFR_top;
111 END MINI_LFR_top;
112
112
113
113
114 ARCHITECTURE beh OF MINI_LFR_top IS
114 ARCHITECTURE beh OF MINI_LFR_top IS
115
115
116 COMPONENT leon3_soc
116 COMPONENT leon3_soc
117 GENERIC (
117 GENERIC (
118 fabtech : INTEGER;
118 fabtech : INTEGER;
119 memtech : INTEGER;
119 memtech : INTEGER;
120 padtech : INTEGER;
120 padtech : INTEGER;
121 clktech : INTEGER;
121 clktech : INTEGER;
122 disas : INTEGER;
122 disas : INTEGER;
123 dbguart : INTEGER;
123 dbguart : INTEGER;
124 pclow : INTEGER);
124 pclow : INTEGER);
125 PORT (
125 PORT (
126 clk100MHz : IN STD_ULOGIC;
126 clk100MHz : IN STD_ULOGIC;
127 reset : IN STD_ULOGIC;
127 reset : IN STD_ULOGIC;
128 errorn : OUT STD_ULOGIC;
128 errorn : OUT STD_ULOGIC;
129 ahbrxd : IN STD_ULOGIC;
129 ahbrxd : IN STD_ULOGIC;
130 ahbtxd : OUT STD_ULOGIC;
130 ahbtxd : OUT STD_ULOGIC;
131 urxd1 : IN STD_ULOGIC;
131 urxd1 : IN STD_ULOGIC;
132 utxd1 : OUT STD_ULOGIC;
132 utxd1 : OUT STD_ULOGIC;
133 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
133 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
134 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
134 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
135 nSRAM_BE0 : OUT STD_LOGIC;
135 nSRAM_BE0 : OUT STD_LOGIC;
136 nSRAM_BE1 : OUT STD_LOGIC;
136 nSRAM_BE1 : OUT STD_LOGIC;
137 nSRAM_BE2 : OUT STD_LOGIC;
137 nSRAM_BE2 : OUT STD_LOGIC;
138 nSRAM_BE3 : OUT STD_LOGIC;
138 nSRAM_BE3 : OUT STD_LOGIC;
139 nSRAM_WE : OUT STD_LOGIC;
139 nSRAM_WE : OUT STD_LOGIC;
140 nSRAM_CE : OUT STD_LOGIC;
140 nSRAM_CE : OUT STD_LOGIC;
141 nSRAM_OE : OUT STD_LOGIC;
141 nSRAM_OE : OUT STD_LOGIC;
142 spw1_din : IN STD_LOGIC;
142 spw1_din : IN STD_LOGIC;
143 spw1_sin : IN STD_LOGIC;
143 spw1_sin : IN STD_LOGIC;
144 spw1_dout : OUT STD_LOGIC;
144 spw1_dout : OUT STD_LOGIC;
145 spw1_sout : OUT STD_LOGIC;
145 spw1_sout : OUT STD_LOGIC;
146 spw2_din : IN STD_LOGIC;
146 spw2_din : IN STD_LOGIC;
147 spw2_sin : IN STD_LOGIC;
147 spw2_sin : IN STD_LOGIC;
148 spw2_dout : OUT STD_LOGIC;
148 spw2_dout : OUT STD_LOGIC;
149 spw2_sout : OUT STD_LOGIC;
149 spw2_sout : OUT STD_LOGIC;
150 apbi_ext : OUT apb_slv_in_type;
150 apbi_ext : OUT apb_slv_in_type;
151 apbo_wfp : IN apb_slv_out_type;
151 apbo_wfp : IN apb_slv_out_type;
152 apbo_ltm : IN apb_slv_out_type;
152 apbo_ltm : IN apb_slv_out_type;
153 ahbi_ext : OUT AHB_Mst_In_Type;
153 ahbi_ext : OUT AHB_Mst_In_Type;
154 ahbo_wfp : IN AHB_Mst_Out_Type);
154 ahbo_wfp : IN AHB_Mst_Out_Type);
155 END COMPONENT;
155 END COMPONENT;
156
156
157 -----------------------------------------------------------------------------
157 -----------------------------------------------------------------------------
158 SIGNAL apbi : apb_slv_in_type;
158 SIGNAL apbi : apb_slv_in_type;
159 SIGNAL apbo_wfp : apb_slv_out_type;
159 SIGNAL apbo_wfp : apb_slv_out_type;
160 SIGNAL apbo_ltm : apb_slv_out_type;
160 SIGNAL apbo_ltm : apb_slv_out_type;
161 SIGNAL ahbi : AHB_Mst_In_Type;
161 SIGNAL ahbi : AHB_Mst_In_Type;
162 SIGNAL ahbo_wfp : AHB_Mst_Out_Type;
162 SIGNAL ahbo_wfp : AHB_Mst_Out_Type;
163 --
163 --
164 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
164 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
165 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
165 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
166 --
166 --
167 SIGNAL errorn : STD_LOGIC;
167 SIGNAL errorn : STD_LOGIC;
168 -- UART AHB ---------------------------------------------------------------
168 -- UART AHB ---------------------------------------------------------------
169 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
169 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
170 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
170 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
171
171
172 -- UART APB ---------------------------------------------------------------
172 -- UART APB ---------------------------------------------------------------
173 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
173 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
174 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
174 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
175 --
175 --
176 SIGNAL I00_s : STD_LOGIC;
176 SIGNAL I00_s : STD_LOGIC;
177
177
178 BEGIN -- beh
178 BEGIN -- beh
179
179
180 PROCESS (clk_50, reset)
180 PROCESS (clk_50, reset)
181 BEGIN -- PROCESS
181 BEGIN -- PROCESS
182 IF reset = '0' THEN -- asynchronous reset (active low)
182 IF reset = '0' THEN -- asynchronous reset (active low)
183 LED0 <= '0';
183 LED0 <= '0';
184 LED1 <= '0';
184 LED1 <= '0';
185 LED2 <= '0';
185 LED2 <= '0';
186 IO1 <= '0';
186 IO1 <= '0';
187 IO2 <= '1';
187 IO2 <= '1';
188 IO3 <= '0';
188 IO3 <= '0';
189 IO4 <= '0';
189 IO4 <= '0';
190 IO5 <= '0';
190 IO5 <= '0';
191 IO6 <= '0';
191 IO6 <= '0';
192 IO7 <= '0';
192 IO7 <= '0';
193 IO8 <= '0';
193 IO8 <= '0';
194 IO9 <= '0';
194 IO9 <= '0';
195 IO10 <= '0';
195 IO10 <= '0';
196 IO11 <= '0';
196 IO11 <= '0';
197 ELSIF clk_50'event AND clk_50 = '1' THEN -- rising clock edge
197 ELSIF clk_50'event AND clk_50 = '1' THEN -- rising clock edge
198 LED0 <= '0';
198 LED0 <= '0';
199 LED1 <= '1';
199 LED1 <= '1';
200 LED2 <= BP0;
200 LED2 <= BP0;
201 IO1 <= '1';
201 IO1 <= '1';
202 IO2 <= '0';
202 IO2 <= '0';
203 IO3 <= ADC_SDO(0);
203 IO3 <= ADC_SDO(0);
204 IO4 <= ADC_SDO(1);
204 IO4 <= ADC_SDO(1);
205 IO5 <= ADC_SDO(2);
205 IO5 <= ADC_SDO(2);
206 IO6 <= ADC_SDO(3);
206 IO6 <= ADC_SDO(3);
207 IO7 <= ADC_SDO(4);
207 IO7 <= ADC_SDO(4);
208 IO8 <= ADC_SDO(5);
208 IO8 <= ADC_SDO(5);
209 IO9 <= ADC_SDO(6);
209 IO9 <= ADC_SDO(6);
210 IO10 <= ADC_SDO(7);
210 IO10 <= ADC_SDO(7);
211 IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
211 IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
212 END IF;
212 END IF;
213 END PROCESS;
213 END PROCESS;
214
214
215 PROCESS (clk_49, reset)
215 PROCESS (clk_49, reset)
216 BEGIN -- PROCESS
216 BEGIN -- PROCESS
217 IF reset = '0' THEN -- asynchronous reset (active low)
217 IF reset = '0' THEN -- asynchronous reset (active low)
218 I00_s <= '0';
218 I00_s <= '0';
219 ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge
219 ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge
220 I00_s <= NOT I00_s;
220 I00_s <= NOT I00_s;
221 END IF;
221 END IF;
222 END PROCESS;
222 END PROCESS;
223 IO0 <= I00_s;
223 IO0 <= I00_s;
224
224
225 --UARTs
225 --UARTs
226 nCTS1 <= '0';
226 nCTS1 <= '1';
227 nCTS2 <= '0';
227 nCTS2 <= '1';
228 nDCD2 <= '0';
228 nDCD2 <= '1';
229
229
230 --EXT CONNECTOR
230 --EXT CONNECTOR
231
231
232 --SPACE WIRE
232 --SPACE WIRE
233 SPW_EN <= '0'; -- 0 => off
233 SPW_EN <= '0'; -- 0 => off
234
234
235 ADC_nCS <= '0';
235 ADC_nCS <= '0';
236 ADC_CLK <= '0';
236 ADC_CLK <= '0';
237
237
238 leon3mp_1: leon3_soc
238 leon3mp_1: leon3_soc
239 GENERIC MAP (
239 GENERIC MAP (
240 fabtech => CFG_FABTECH,
240 fabtech => CFG_FABTECH,
241 memtech => CFG_MEMTECH,
241 memtech => CFG_MEMTECH,
242 padtech => CFG_PADTECH,
242 padtech => CFG_PADTECH,
243 clktech => CFG_CLKTECH,
243 clktech => CFG_CLKTECH,
244 disas => CFG_DISAS,
244 disas => CFG_DISAS,
245 dbguart => CFG_DUART,
245 dbguart => CFG_DUART,
246 pclow => CFG_PCLOW)
246 pclow => CFG_PCLOW)
247 PORT MAP (
247 PORT MAP (
248 clk100MHz => clk_50, --
248 clk100MHz => clk_50, --
249 reset => reset, --
249 reset => reset, --
250 errorn => errorn, --
250 errorn => errorn, --
251
251
252 ahbrxd => TXD1, --
252 ahbrxd => TXD1, --
253 ahbtxd => RXD1, --
253 ahbtxd => RXD1, --
254 urxd1 => TXD2, --
254 urxd1 => TXD2, --
255 utxd1 => RXD2, --
255 utxd1 => RXD2, --
256 --RAM
256 --RAM
257 address => SRAM_A, --
257 address => SRAM_A, --
258 data => SRAM_DQ, --
258 data => SRAM_DQ, --
259 nSRAM_BE0 => SRAM_nBE(0), --
259 nSRAM_BE0 => SRAM_nBE(0), --
260 nSRAM_BE1 => SRAM_nBE(1), --
260 nSRAM_BE1 => SRAM_nBE(1), --
261 nSRAM_BE2 => SRAM_nBE(2), --
261 nSRAM_BE2 => SRAM_nBE(2), --
262 nSRAM_BE3 => SRAM_nBE(3), --
262 nSRAM_BE3 => SRAM_nBE(3), --
263 nSRAM_WE => SRAM_nWE, --
263 nSRAM_WE => SRAM_nWE, --
264 nSRAM_CE => SRAM_CE, --
264 nSRAM_CE => SRAM_CE, --
265 nSRAM_OE => SRAM_nOE, --
265 nSRAM_OE => SRAM_nOE, --
266 --SPW
266 --SPW
267 spw1_din => SPW_NOM_DIN, --
267 spw1_din => SPW_NOM_DIN, --
268 spw1_sin => SPW_NOM_SIN, --
268 spw1_sin => SPW_NOM_SIN, --
269 spw1_dout => SPW_NOM_DOUT, --
269 spw1_dout => SPW_NOM_DOUT, --
270 spw1_sout => SPW_NOM_SOUT, --
270 spw1_sout => SPW_NOM_SOUT, --
271 spw2_din => SPW_RED_DIN, --
271 spw2_din => SPW_RED_DIN, --
272 spw2_sin => SPW_RED_SIN, --
272 spw2_sin => SPW_RED_SIN, --
273 spw2_dout => SPW_RED_DOUT, --
273 spw2_dout => SPW_RED_DOUT, --
274 spw2_sout => SPW_RED_SOUT, --
274 spw2_sout => SPW_RED_SOUT, --
275
275
276 apbi_ext => apbi, --
276 apbi_ext => apbi, --
277 apbo_wfp => apbo_wfp, --
277 apbo_wfp => apbo_wfp, --
278 apbo_ltm => apbo_ltm, -- lfr time management
278 apbo_ltm => apbo_ltm, -- lfr time management
279 ahbi_ext => ahbi, --
279 ahbi_ext => ahbi, --
280 ahbo_wfp => ahbo_wfp); --
280 ahbo_wfp => ahbo_wfp); --
281
281
282 apbo_wfp <= apb_none;
282 apbo_wfp <= apb_none;
283 apbo_ltm <= apb_none;
283 apbo_ltm <= apb_none;
284 ahbo_wfp <= ahbm_none;
284 ahbo_wfp <= ahbm_none;
285
285
286 END beh; No newline at end of file
286 END beh;
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