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EQM debug
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1 #set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout
2 set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout
3 set_io reset -pinname R4 -fixed yes -DIRECTION Inout
4
5 set_io {address[0]} -pinname U3 -fixed yes -DIRECTION Inout
6 set_io {address[1]} -pinname V14 -fixed yes -DIRECTION Inout
7 set_io {address[2]} -pinname V13 -fixed yes -DIRECTION Inout
8 set_io {address[3]} -pinname V16 -fixed yes -DIRECTION Inout
9 set_io {address[4]} -pinname N9 -fixed yes -DIRECTION Inout
10 set_io {address[5]} -pinname T11 -fixed yes -DIRECTION Inout
11 set_io {address[6]} -pinname U13 -fixed yes -DIRECTION Inout
12 set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
13 set_io {address[8]} -pinname U2 -fixed yes -DIRECTION Inout
14 set_io {address[9]} -pinname N11 -fixed yes -DIRECTION Inout
15 set_io {address[10]} -pinname R13 -fixed yes -DIRECTION Inout
16 set_io {address[11]} -pinname R12 -fixed yes -DIRECTION Inout
17 set_io {address[12]} -pinname M15 -fixed yes -DIRECTION Inout
18 set_io {address[13]} -pinname T12 -fixed yes -DIRECTION Inout
19 set_io {address[14]} -pinname M13 -fixed yes -DIRECTION Inout
20 set_io {address[15]} -pinname T13 -fixed yes -DIRECTION Inout
21 set_io {address[16]} -pinname L13 -fixed yes -DIRECTION Inout
22 set_io {address[17]} -pinname V17 -fixed yes -DIRECTION Inout
23 set_io {address[18]} -pinname V15 -fixed yes -DIRECTION Inout
24
25 set_io {data[0]} -pinname V4 -fixed yes -DIRECTION Inout
26 set_io {data[1]} -pinname V3 -fixed yes -DIRECTION Inout
27 set_io {data[2]} -pinname V2 -fixed yes -DIRECTION Inout
28 set_io {data[3]} -pinname T3 -fixed yes -DIRECTION Inout
29 set_io {data[4]} -pinname N6 -fixed yes -DIRECTION Inout
30 set_io {data[5]} -pinname P6 -fixed yes -DIRECTION Inout
31 set_io {data[6]} -pinname R6 -fixed yes -DIRECTION Inout
32 set_io {data[7]} -pinname T4 -fixed yes -DIRECTION Inout
33 set_io {data[8]} -pinname T1 -fixed yes -DIRECTION Inout
34 set_io {data[9]} -pinname R1 -fixed yes -DIRECTION Inout
35 set_io {data[10]} -pinname P1 -fixed yes -DIRECTION Inout
36 set_io {data[11]} -pinname N2 -fixed yes -DIRECTION Inout
37 set_io {data[12]} -pinname R3 -fixed yes -DIRECTION Inout
38 set_io {data[13]} -pinname P4 -fixed yes -DIRECTION Inout
39 set_io {data[14]} -pinname N4 -fixed yes -DIRECTION Inout
40 set_io {data[15]} -pinname N3 -fixed yes -DIRECTION Inout
41 set_io {data[16]} -pinname G12 -fixed yes -DIRECTION Inout
42 set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
43 set_io {data[18]} -pinname H15 -fixed yes -DIRECTION Inout
44 set_io {data[19]} -pinname F17 -fixed yes -DIRECTION Inout
45 set_io {data[20]} -pinname F18 -fixed yes -DIRECTION Inout
46 set_io {data[21]} -pinname G17 -fixed yes -DIRECTION Inout
47 set_io {data[22]} -pinname H18 -fixed yes -DIRECTION Inout
48 set_io {data[23]} -pinname J18 -fixed yes -DIRECTION Inout
49 set_io {data[24]} -pinname R18 -fixed yes -DIRECTION Inout
50 set_io {data[25]} -pinname N18 -fixed yes -DIRECTION Inout
51 set_io {data[26]} -pinname P17 -fixed yes -DIRECTION Inout
52 set_io {data[27]} -pinname N17 -fixed yes -DIRECTION Inout
53 set_io {data[28]} -pinname T18 -fixed yes -DIRECTION Inout
54 set_io {data[29]} -pinname M17 -fixed yes -DIRECTION Inout
55 set_io {data[30]} -pinname U18 -fixed yes -DIRECTION Inout
56 set_io {data[31]} -pinname L18 -fixed yes -DIRECTION Inout
57
58 set_io nSRAM_MBE -pinname E4 -fixed yes -DIRECTION Inout
59 set_io nSRAM_E1 -pinname D1 -fixed yes -DIRECTION Inout
60 set_io nSRAM_E2 -pinname C1 -fixed yes -DIRECTION Inout
61 #set_io nSRAM_SCRUB -pinname C2 -fixed yes -DIRECTION Inout
62 set_io nSRAM_W -pinname D4 -fixed yes -DIRECTION Inout
63 set_io nSRAM_G -pinname E1 -fixed yes -DIRECTION Inout
64 set_io nSRAM_BUSY -pinname F4 -fixed yes -DIRECTION Inout
65
66 set_io spw1_en -pinname G4 -fixed yes -DIRECTION Inout
67 set_io spw1_din -pinname D13 -fixed yes -DIRECTION Inout
68 set_io spw1_sin -pinname D14 -fixed yes -DIRECTION Inout
69 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
70 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
71
72 set_io spw2_en -pinname G3 -fixed yes -DIRECTION Inout
73 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
74 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
75 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
76 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
77
78 set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout
79 set_io TAG2 -pinname K12 -fixed yes -DIRECTION Inout
80 set_io TAG3 -pinname K13 -fixed yes -DIRECTION Inout
81 set_io TAG4 -pinname L16 -fixed yes -DIRECTION Inout
82 #set_io TAG5 -pinname L15 -fixed yes -DIRECTION Inout
83 #set_io TAG6 -pinname M16 -fixed yes -DIRECTION Inout
84 #set_io TAG7 -pinname J14 -fixed yes -DIRECTION Inout
85 set_io TAG8 -pinname K15 -fixed yes -DIRECTION Inout
86 #set_io TAG9 -pinname J17 -fixed yes -DIRECTION Inout
87
88 set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
89
90 set_io {ADC_OEB_bar_CH[0]} -pinname A10 -fixed yes -DIRECTION Inout
91 set_io {ADC_OEB_bar_CH[1]} -pinname B10 -fixed yes -DIRECTION Inout
92 set_io {ADC_OEB_bar_CH[2]} -pinname B12 -fixed yes -DIRECTION Inout
93 set_io {ADC_OEB_bar_CH[3]} -pinname A11 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[5]} -pinname C6 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[6]} -pinname A13 -fixed yes -DIRECTION Inout
97 set_io {ADC_OEB_bar_CH[7]} -pinname A14 -fixed yes -DIRECTION Inout
98
99 set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
100
101 set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout
102 set_io ADC_OEB_bar_HK -pinname D6 -fixed yes -DIRECTION Inout
103 set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout
104 set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout
105
106 #set_io {ADC_data[0]} -pinname G13 -fixed yes -DIRECTION Inout
107 #set_io {ADC_data[1]} -pinname G16 -fixed yes -DIRECTION Inout
108 #set_io {ADC_data[2]} -pinname F16 -fixed yes -DIRECTION Inout
109 #set_io {ADC_data[3]} -pinname E15 -fixed yes -DIRECTION Inout
110 #set_io {ADC_data[4]} -pinname F13 -fixed yes -DIRECTION Inout
111 #set_io {ADC_data[5]} -pinname F15 -fixed yes -DIRECTION Inout
112 #set_io {ADC_data[6]} -pinname D16 -fixed yes -DIRECTION Inout
113 #set_io {ADC_data[7]} -pinname D15 -fixed yes -DIRECTION Inout
114 #set_io {ADC_data[8]} -pinname B17 -fixed yes -DIRECTION Inout
115 #set_io {ADC_data[9]} -pinname A17 -fixed yes -DIRECTION Inout
116 #set_io {ADC_data[10]} -pinname A16 -fixed yes -DIRECTION Inout
117 #set_io {ADC_data[11]} -pinname B16 -fixed yes -DIRECTION Inout
118 #set_io {ADC_data[12]} -pinname C12 -fixed yes -DIRECTION Inout
119 #set_io {ADC_data[13]} -pinname C13 -fixed yes -DIRECTION Inout
120
121 set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout
122 set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout
123 set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout
124 set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout
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1 # Top Level Design Parameters
2
3 # Clocks
4
5 create_clock -period 20.000000 -waveform {0.000000 10.000000} clk50MHz
6 create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz
7 create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25:Q
8 create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q
9 create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin}
10
11
12 # False Paths Between Clocks
13
14
15 # False Path Constraints
16
17
18 # Maximum Delay Constraints
19
20
21 # Multicycle Constraints
22
23
24 # Virtual Clocks
25 # Output Load Constraints
26 # Driving Cell Constraints
27 # Wire Loads
28 # set_wire_load_mode top
29
30 # Other Constraints
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1 # Top Level Design Parameters
2
3 # Clocks
4 create_clock -name{clk_50} -period 20.000000 -waveform { 0.000 10.000000 } {clk50MHz}
5 create_clock -name{clk_49} -period 20.344999 -waveform { 0.000 10.172500 } {clk49_152MHz}
6 create_clock -name{spw_rx_clk} -period 100.00000 -waveform { 0.000 50.000000 } {spw_inputloop_0_spw_phy0/rxclki spw_inputloop_1_spw_phy0/rxclki}
7
8 create_generated_clock -name{clk_25:Q} -divide_by 2 -source{clk_25:CLK}{clk_25:Q}
9 create_generated_clock -name{clk_24:Q} -divide_by 2 -source{clk_24:CLK}{clk_24:Q}
10
11
12
13
14 #create_clock -period 10.000000 -waveform {0.000000 5.000000} clk50MHz
15 #create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz
16 #create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25:Q
17 #create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q
18 #create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin}
19
20
21 # False Paths Between Clocks
22
23
24 # False Path Constraints
25
26
27 # Maximum Delay Constraints
28
29
30 # Multicycle Constraints
31
32
33 # Virtual Clocks
34 # Output Load Constraints
35 # Driving Cell Constraints
36 # Wire Loads
37 # set_wire_load_mode top
38
39 # Other Constraints
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
48 library proasic3e;
49 use proasic3e.clkint;
50
51 ENTITY LFR_EQM IS
52
53 PORT (
54 clk50MHz : IN STD_ULOGIC;
55 clk49_152MHz : IN STD_ULOGIC;
56 reset : IN STD_ULOGIC;
57
58 -- TAG --------------------------------------------------------------------
59 TAG1 : IN STD_ULOGIC; -- DSU rx data
60 TAG3 : OUT STD_ULOGIC; -- DSU tx data
61 -- UART APB ---------------------------------------------------------------
62 TAG2 : IN STD_ULOGIC; -- UART1 rx data
63 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
64 -- RAM --------------------------------------------------------------------
65 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
66 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
67
68 nSRAM_MBE : INOUT STD_LOGIC; -- new
69 nSRAM_E1 : OUT STD_LOGIC; -- new
70 nSRAM_E2 : OUT STD_LOGIC; -- new
71 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
72 nSRAM_W : OUT STD_LOGIC; -- new
73 nSRAM_G : OUT STD_LOGIC; -- new
74 nSRAM_BUSY : IN STD_LOGIC; -- new
75 -- SPW --------------------------------------------------------------------
76 spw1_en : OUT STD_LOGIC; -- new
77 spw1_din : IN STD_LOGIC;
78 spw1_sin : IN STD_LOGIC;
79 spw1_dout : OUT STD_LOGIC;
80 spw1_sout : OUT STD_LOGIC;
81 spw2_en : OUT STD_LOGIC; -- new
82 spw2_din : IN STD_LOGIC;
83 spw2_sin : IN STD_LOGIC;
84 spw2_dout : OUT STD_LOGIC;
85 spw2_sout : OUT STD_LOGIC;
86 -- ADC --------------------------------------------------------------------
87 bias_fail_sw : OUT STD_LOGIC; -- '0'
88 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- '1'
89 ADC_smpclk : OUT STD_LOGIC; -- '0'
90 --ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); -- todo
91 -- DAC --------------------------------------------------------------------
92 DAC_SDO : OUT STD_LOGIC; -- '1'
93 DAC_SCK : OUT STD_LOGIC; -- '0'
94 DAC_SYNC : OUT STD_LOGIC; -- '0'
95 DAC_CAL_EN : OUT STD_LOGIC; -- '0'
96 -- HK ---------------------------------------------------------------------
97 HK_smpclk : OUT STD_LOGIC; -- '0'
98 ADC_OEB_bar_HK : OUT STD_LOGIC; -- '1'
99 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- "00"
100 ---------------------------------------------------------------------------
101 TAG8 : OUT STD_LOGIC
102 );
103
104 END LFR_EQM;
105
106
107 ARCHITECTURE beh OF LFR_EQM IS
108
109 SIGNAL clk_25 : STD_LOGIC := '0';
110 SIGNAL clk_25_int : STD_LOGIC := '0';
111 SIGNAL clk_24 : STD_LOGIC := '0';
112 -----------------------------------------------------------------------------
113 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
114 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
115
116 -- CONSTANTS
117 CONSTANT CFG_PADTECH : INTEGER := inferred;
118 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
119 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
120 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
121
122 SIGNAL apbi_ext : apb_slv_in_type;
123 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
124 SIGNAL ahbi_s_ext : ahb_slv_in_type;
125 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
126 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
127 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
128
129 -- Spacewire signals
130 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
131 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
132 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
133 SIGNAL spw_rxtxclk : STD_ULOGIC;
134 SIGNAL spw_rxclkn : STD_ULOGIC;
135 SIGNAL spw_clk : STD_LOGIC;
136 SIGNAL swni : grspw_in_type;
137 SIGNAL swno : grspw_out_type;
138
139 --GPIO
140 SIGNAL gpioi : gpio_in_type;
141 SIGNAL gpioo : gpio_out_type;
142
143 -- AD Converter ADS7886
144 SIGNAL sample : Samples14v(8 DOWNTO 0);
145 SIGNAL sample_s : Samples(8 DOWNTO 0);
146 SIGNAL sample_val : STD_LOGIC;
147 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
148
149 -----------------------------------------------------------------------------
150 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
151
152 -----------------------------------------------------------------------------
153 SIGNAL rstn_25 : STD_LOGIC;
154 SIGNAL rstn_24 : STD_LOGIC;
155
156 SIGNAL LFR_soft_rstn : STD_LOGIC;
157 SIGNAL LFR_rstn : STD_LOGIC;
158
159 SIGNAL ADC_smpclk_s : STD_LOGIC;
160
161 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
162
163 SIGNAL clk50MHz_int : STD_LOGIC := '0';
164
165 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
166
167 BEGIN -- beh
168
169 -----------------------------------------------------------------------------
170 -- CLK
171 -----------------------------------------------------------------------------
172 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
173 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
174
175 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
176 clk50MHz_int <= clk50MHz;
177 PROCESS(clk50MHz_int)
178 BEGIN
179 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
180 clk_25_int <= NOT clk_25_int;
181 END IF;
182 END PROCESS;
183 clk_pad : clkint port map (A => clk_25_int, Y => clk_25 );
184
185 PROCESS(clk49_152MHz)
186 BEGIN
187 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
188 clk_24 <= NOT clk_24;
189 END IF;
190 END PROCESS;
191
192 -----------------------------------------------------------------------------
193 --
194 leon3_soc_1 : leon3_soc
195 GENERIC MAP (
196 fabtech => apa3e,
197 memtech => apa3e,
198 padtech => inferred,
199 clktech => inferred,
200 disas => 0,
201 dbguart => 0,
202 pclow => 2,
203 clk_freq => 25000,
204 IS_RADHARD => 0,
205 NB_CPU => 1,
206 ENABLE_FPU => 1,
207 FPU_NETLIST => 0,
208 ENABLE_DSU => 1,
209 ENABLE_AHB_UART => 1,
210 ENABLE_APB_UART => 1,
211 ENABLE_IRQMP => 1,
212 ENABLE_GPT => 1,
213 NB_AHB_MASTER => NB_AHB_MASTER,
214 NB_AHB_SLAVE => NB_AHB_SLAVE,
215 NB_APB_SLAVE => NB_APB_SLAVE,
216 ADDRESS_SIZE => 19,
217 USES_IAP_MEMCTRLR => 1)
218 PORT MAP (
219 clk => clk_25,
220 reset => rstn_25,
221 errorn => OPEN,
222
223 ahbrxd => TAG1,
224 ahbtxd => TAG3,
225 urxd1 => TAG2,
226 utxd1 => TAG4,
227
228 address => address,
229 data => data,
230 nSRAM_BE0 => OPEN,
231 nSRAM_BE1 => OPEN,
232 nSRAM_BE2 => OPEN,
233 nSRAM_BE3 => OPEN,
234 nSRAM_WE => nSRAM_W,
235 nSRAM_CE => nSRAM_CE,
236 nSRAM_OE => nSRAM_G,
237 nSRAM_READY => nSRAM_BUSY,
238 SRAM_MBE => nSRAM_MBE,
239
240 apbi_ext => apbi_ext,
241 apbo_ext => apbo_ext,
242 ahbi_s_ext => ahbi_s_ext,
243 ahbo_s_ext => ahbo_s_ext,
244 ahbi_m_ext => ahbi_m_ext,
245 ahbo_m_ext => ahbo_m_ext);
246
247
248 nSRAM_E1 <= nSRAM_CE(0);
249 nSRAM_E2 <= nSRAM_CE(1);
250
251 -------------------------------------------------------------------------------
252 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
253 -------------------------------------------------------------------------------
254 --apb_lfr_management_1 : apb_lfr_management
255 -- GENERIC MAP (
256 -- tech => apa3e,
257 -- pindex => 6,
258 -- paddr => 6,
259 -- pmask => 16#fff#,
260 -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
261 -- NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
262 -- PORT MAP (
263 -- clk25MHz => clk_25,
264 -- resetn_25MHz => rstn_25, -- TODO
265 -- clk24_576MHz => clk_24, -- 49.152MHz/2
266 -- resetn_24_576MHz => rstn_24, -- TODO
267
268 -- grspw_tick => swno.tickout,
269 -- apbi => apbi_ext,
270 -- apbo => apbo_ext(6),
271
272 -- HK_sample => sample_s(8),
273 -- HK_val => sample_val,
274 -- HK_sel => HK_SEL,
275
276 -- DAC_SDO => DAC_SDO,
277 -- DAC_SCK => DAC_SCK,
278 -- DAC_SYNC => DAC_SYNC,
279 -- DAC_CAL_EN => DAC_CAL_EN,
280
281 -- coarse_time => coarse_time,
282 -- fine_time => fine_time,
283 -- LFR_soft_rstn => LFR_soft_rstn
284 -- );
285 HK_sel <= "00";
286
287 DAC_SDO <= '1';
288 DAC_SCK <= '0';
289 DAC_SYNC <= '0';
290 DAC_CAL_EN <= '0';
291
292 -----------------------------------------------------------------------
293 --- SpaceWire --------------------------------------------------------
294 -----------------------------------------------------------------------
295
296 ------------------------------------------------------------------------------
297 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
298 ------------------------------------------------------------------------------
299 spw1_en <= '1';
300 spw2_en <= '1';
301 ------------------------------------------------------------------------------
302 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
303 ------------------------------------------------------------------------------
304
305 --spw_clk <= clk50MHz_int;
306 --spw_rxtxclk <= spw_clk;
307 --spw_rxclkn <= NOT spw_rxtxclk;
308
309 -- PADS for SPW1
310 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
311 PORT MAP (spw1_din, dtmp(0));
312 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
313 PORT MAP (spw1_sin, stmp(0));
314 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
315 PORT MAP (spw1_dout, swno.d(0));
316 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
317 PORT MAP (spw1_sout, swno.s(0));
318 -- PADS FOR SPW2
319 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
320 PORT MAP (spw2_din, dtmp(1));
321 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
322 PORT MAP (spw2_sin, stmp(1));
323 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
324 PORT MAP (spw2_dout, swno.d(1));
325 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
326 PORT MAP (spw2_sout, swno.s(1));
327
328 -- GRSPW PHY
329 --spw1_input: if CFG_SPW_GRSPW = 1 generate
330 spw_inputloop : FOR j IN 0 TO 1 GENERATE
331 spw_phy0 : grspw_phy
332 GENERIC MAP(
333 tech => apa3e,
334 rxclkbuftype => 1,
335 scantest => 0)
336 PORT MAP(
337 rxrst => swno.rxrst,
338 di => dtmp(j),
339 si => stmp(j),
340 rxclko => spw_rxclk(j),
341 do => swni.d(j),
342 ndo => swni.nd(j*5+4 DOWNTO j*5),
343 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
344 END GENERATE spw_inputloop;
345
346 -- SPW core
347 sw0 : grspwm GENERIC MAP(
348 tech => apa3e,
349 hindex => 1,
350 pindex => 5,
351 paddr => 5,
352 pirq => 11,
353 sysfreq => 25000, -- CPU_FREQ
354 rmap => 1,
355 rmapcrc => 1,
356 fifosize1 => 16,
357 fifosize2 => 16,
358 rxclkbuftype => 1,
359 rxunaligned => 0,
360 rmapbufs => 4,
361 ft => 0,
362 netlist => 0,
363 ports => 2,
364 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
365 memtech => apa3e,
366 destkey => 2,
367 spwcore => 1
368 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
369 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
370 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
371 )
372 PORT MAP(rstn_25, clk_25,
373 spw_rxclk(0),
374 spw_rxclk(1),
375 clk50MHz_int,
376 clk50MHz_int,
377 -- spw_rxtxclk, spw_rxtxclk,
378 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
379 swni, swno);
380
381 swni.tickin <= '0';
382 swni.rmapen <= '1';
383 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
384 swni.tickinraw <= '0';
385 swni.timein <= (OTHERS => '0');
386 swni.dcrstval <= (OTHERS => '0');
387 swni.timerrstval <= (OTHERS => '0');
388
389 -------------------------------------------------------------------------------
390 -- LFR ------------------------------------------------------------------------
391 -------------------------------------------------------------------------------
392 LFR_rstn <= LFR_soft_rstn AND rstn_25;
393
394 --lpp_lfr_1 : lpp_lfr
395 -- GENERIC MAP (
396 -- Mem_use => use_RAM,
397 -- nb_data_by_buffer_size => 32,
398 -- --nb_word_by_buffer_size => 30,
399 -- nb_snapshot_param_size => 32,
400 -- delta_vector_size => 32,
401 -- delta_vector_size_f0_2 => 7, -- log2(96)
402 -- pindex => 15,
403 -- paddr => 15,
404 -- pmask => 16#fff#,
405 -- pirq_ms => 6,
406 -- pirq_wfp => 14,
407 -- hindex => 2,
408 -- top_lfr_version => X"020144") -- aa.bb.cc version
409 -- -- AA : BOARD NUMBER
410 -- -- 0 => MINI_LFR
411 -- -- 1 => EM
412 -- -- 2 => EQM (with A3PE3000)
413 -- PORT MAP (
414 -- clk => clk_25,
415 -- rstn => LFR_rstn,
416 -- sample_B => sample_s(2 DOWNTO 0),
417 -- sample_E => sample_s(7 DOWNTO 3),
418 -- sample_val => sample_val,
419 -- apbi => apbi_ext,
420 -- apbo => apbo_ext(15),
421 -- ahbi => ahbi_m_ext,
422 -- ahbo => ahbo_m_ext(2),
423 -- coarse_time => coarse_time,
424 -- fine_time => fine_time,
425 -- data_shaping_BW => bias_fail_sw,
426 -- debug_vector => OPEN,
427 -- debug_vector_ms => OPEN); --,
428
429 --observation_vector_0 => OPEN,
430 --observation_vector_1 => OPEN,
431 --observation_reg => observation_reg);
432 bias_fail_sw <= '0';
433
434 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
435 sample_s(I) <= sample(I) & '0' & '0';
436 END GENERATE all_sample;
437 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
438
439 -----------------------------------------------------------------------------
440 --
441 -----------------------------------------------------------------------------
442 --top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
443 -- GENERIC MAP (
444 -- ChanelCount => 9,
445 -- ncycle_cnv_high => 13,
446 -- ncycle_cnv => 25,
447 -- FILTER_ENABLED => 16#FF#)
448 -- PORT MAP (
449 -- cnv_clk => clk_24,
450 -- cnv_rstn => rstn_24,
451 -- cnv => ADC_smpclk_s,
452 -- clk => clk_25,
453 -- rstn => rstn_25,
454 -- ADC_data => ADC_data,
455 -- ADC_nOE => ADC_OEB_bar_CH_s,
456 -- sample => sample,
457 -- sample_val => sample_val);
458
459 --ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
460 ADC_OEB_bar_CH <= (OTHERS => '1');
461
462 --ADC_smpclk <= ADC_smpclk_s;
463 --HK_smpclk <= ADC_smpclk_s;
464 ADC_smpclk <= '0';
465 HK_smpclk <= '0';
466
467 TAG8 <= '0';
468
469 -----------------------------------------------------------------------------
470 -- HK
471 -----------------------------------------------------------------------------
472 --ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
473 ADC_OEB_bar_HK <= '1';
474
475 END beh;
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1 #GRLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=LFR_EQM
6 BOARD=LFR-EQM
7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
16 VHDLSYNFILES=LFR-EQM.vhd
17 VHDLSIMFILES=testbench.vhd
18 #SIMTOP=testbench
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000_debug.pdc
20 #SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc
21 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route-debug.sdc
22
23 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
24 CLEAN=soft-clean
25
26 TECHLIBS = proasic3e
27
28 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
29 tmtc openchip hynix ihp gleichmann micron usbhc
30
31 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
32 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
33 ./amba_lcd_16x2_ctrlr \
34 ./general_purpose/lpp_AMR \
35 ./general_purpose/lpp_balise \
36 ./general_purpose/lpp_delay \
37 ./lpp_bootloader \
38 ./dsp/lpp_fft_rtax \
39 ./lpp_uart \
40 ./lpp_usb \
41 ./lpp_sim/CY7C1061DV33 \
42
43 FILESKIP = i2cmst.vhd \
44 APB_MULTI_DIODE.vhd \
45 APB_MULTI_DIODE.vhd \
46 Top_MatrixSpec.vhd \
47 APB_FFT.vhd\
48 CoreFFT_simu.vhd \
49 lpp_lfr_apbreg_simu.vhd
50
51 include $(GRLIB)/bin/Makefile
52 include $(GRLIB)/software/leon3/Makefile
53
54 ################## project specific targets ##########################
55
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1 vcom -quiet -93 -work work LFR-em.vhd
2 vcom -quiet -93 -work work testbench.vhd
3
4 vsim work.testbench
5
6 log -r *
7
8 do wave.do
9
10 run 65 ms
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4 use IEEE.std_logic_textio.all;
5 LIBRARY STD;
6 use std.textio.all;
7
8 LIBRARY grlib;
9 USE grlib.stdlib.ALL;
10 LIBRARY gaisler;
11 USE gaisler.libdcom.ALL;
12 USE gaisler.sim.ALL;
13 USE gaisler.jtagtst.ALL;
14 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
16
17 LIBRARY lpp;
18 USE lpp.lpp_sim_pkg.ALL;
19 USE lpp.lpp_lfr_sim_pkg.ALL;
20 USE lpp.lpp_lfr_apbreg_pkg.ALL;
21 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
22
23
24 ENTITY testbench IS
25 END;
26
27 ARCHITECTURE behav OF testbench IS
28
29 COMPONENT LFR_em
30 PORT (
31 clk100MHz : IN STD_ULOGIC;
32 clk49_152MHz : IN STD_ULOGIC;
33 reset : IN STD_ULOGIC;
34 TAG1 : IN STD_ULOGIC;
35 TAG3 : OUT STD_ULOGIC;
36 TAG2 : IN STD_ULOGIC;
37 TAG4 : OUT STD_ULOGIC;
38 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
39 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
40 nSRAM_BE0 : OUT STD_LOGIC;
41 nSRAM_BE1 : OUT STD_LOGIC;
42 nSRAM_BE2 : OUT STD_LOGIC;
43 nSRAM_BE3 : OUT STD_LOGIC;
44 nSRAM_WE : OUT STD_LOGIC;
45 nSRAM_CE : OUT STD_LOGIC;
46 nSRAM_OE : OUT STD_LOGIC;
47 spw1_din : IN STD_LOGIC;
48 spw1_sin : IN STD_LOGIC;
49 spw1_dout : OUT STD_LOGIC;
50 spw1_sout : OUT STD_LOGIC;
51 spw2_din : IN STD_LOGIC;
52 spw2_sin : IN STD_LOGIC;
53 spw2_dout : OUT STD_LOGIC;
54 spw2_sout : OUT STD_LOGIC;
55 bias_fail_sw : OUT STD_LOGIC;
56 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
57 ADC_smpclk : OUT STD_LOGIC;
58 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
59 HK_smpclk : OUT STD_LOGIC;
60 ADC_OEB_bar_HK : OUT STD_LOGIC;
61 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
62 TAG8 : OUT STD_LOGIC;
63 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
64 END COMPONENT;
65
66
67 --COMPONENT MINI_LFR_top
68 -- PORT (
69 -- clk_50 : IN STD_LOGIC;
70 -- clk_49 : IN STD_LOGIC;
71 -- reset : IN STD_LOGIC;
72 -- BP0 : IN STD_LOGIC;
73 -- BP1 : IN STD_LOGIC;
74 -- LED0 : OUT STD_LOGIC;
75 -- LED1 : OUT STD_LOGIC;
76 -- LED2 : OUT STD_LOGIC;
77 -- TXD1 : IN STD_LOGIC;
78 -- RXD1 : OUT STD_LOGIC;
79 -- nCTS1 : OUT STD_LOGIC;
80 -- nRTS1 : IN STD_LOGIC;
81 -- TXD2 : IN STD_LOGIC;
82 -- RXD2 : OUT STD_LOGIC;
83 -- nCTS2 : OUT STD_LOGIC;
84 -- nDTR2 : IN STD_LOGIC;
85 -- nRTS2 : IN STD_LOGIC;
86 -- nDCD2 : OUT STD_LOGIC;
87 -- IO0 : INOUT STD_LOGIC;
88 -- IO1 : INOUT STD_LOGIC;
89 -- IO2 : INOUT STD_LOGIC;
90 -- IO3 : INOUT STD_LOGIC;
91 -- IO4 : INOUT STD_LOGIC;
92 -- IO5 : INOUT STD_LOGIC;
93 -- IO6 : INOUT STD_LOGIC;
94 -- IO7 : INOUT STD_LOGIC;
95 -- IO8 : INOUT STD_LOGIC;
96 -- IO9 : INOUT STD_LOGIC;
97 -- IO10 : INOUT STD_LOGIC;
98 -- IO11 : INOUT STD_LOGIC;
99 -- SPW_EN : OUT STD_LOGIC;
100 -- SPW_NOM_DIN : IN STD_LOGIC;
101 -- SPW_NOM_SIN : IN STD_LOGIC;
102 -- SPW_NOM_DOUT : OUT STD_LOGIC;
103 -- SPW_NOM_SOUT : OUT STD_LOGIC;
104 -- SPW_RED_DIN : IN STD_LOGIC;
105 -- SPW_RED_SIN : IN STD_LOGIC;
106 -- SPW_RED_DOUT : OUT STD_LOGIC;
107 -- SPW_RED_SOUT : OUT STD_LOGIC;
108 -- ADC_nCS : OUT STD_LOGIC;
109 -- ADC_CLK : OUT STD_LOGIC;
110 -- ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
111 -- SRAM_nWE : OUT STD_LOGIC;
112 -- SRAM_CE : OUT STD_LOGIC;
113 -- SRAM_nOE : OUT STD_LOGIC;
114 -- SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
115 -- SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
116 -- SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
117 --END COMPONENT;
118
119 -----------------------------------------------------------------------------
120 SIGNAL clk_50 : STD_LOGIC := '0';
121 SIGNAL clk_49 : STD_LOGIC := '0';
122 SIGNAL reset : STD_LOGIC;
123 SIGNAL BP0 : STD_LOGIC;
124 SIGNAL BP1 : STD_LOGIC;
125 SIGNAL LED0 : STD_LOGIC;
126 SIGNAL LED1 : STD_LOGIC;
127 SIGNAL LED2 : STD_LOGIC;
128 SIGNAL TXD1 : STD_LOGIC;
129 SIGNAL RXD1 : STD_LOGIC;
130 SIGNAL nCTS1 : STD_LOGIC;
131 SIGNAL nRTS1 : STD_LOGIC;
132 SIGNAL TXD2 : STD_LOGIC;
133 SIGNAL RXD2 : STD_LOGIC;
134 SIGNAL nCTS2 : STD_LOGIC;
135 SIGNAL nDTR2 : STD_LOGIC;
136 SIGNAL nRTS2 : STD_LOGIC;
137 SIGNAL nDCD2 : STD_LOGIC;
138 SIGNAL IO0 : STD_LOGIC;
139 SIGNAL IO1 : STD_LOGIC;
140 SIGNAL IO2 : STD_LOGIC;
141 SIGNAL IO3 : STD_LOGIC;
142 SIGNAL IO4 : STD_LOGIC;
143 SIGNAL IO5 : STD_LOGIC;
144 SIGNAL IO6 : STD_LOGIC;
145 SIGNAL IO7 : STD_LOGIC;
146 SIGNAL IO8 : STD_LOGIC;
147 SIGNAL IO9 : STD_LOGIC;
148 SIGNAL IO10 : STD_LOGIC;
149 SIGNAL IO11 : STD_LOGIC;
150 SIGNAL SPW_EN : STD_LOGIC;
151 SIGNAL SPW_NOM_DIN : STD_LOGIC;
152 SIGNAL SPW_NOM_SIN : STD_LOGIC;
153 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
154 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
155 SIGNAL SPW_RED_DIN : STD_LOGIC;
156 SIGNAL SPW_RED_SIN : STD_LOGIC;
157 SIGNAL SPW_RED_DOUT : STD_LOGIC;
158 SIGNAL SPW_RED_SOUT : STD_LOGIC;
159 SIGNAL ADC_nCS : STD_LOGIC;
160 SIGNAL ADC_CLK : STD_LOGIC;
161 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
162 SIGNAL SRAM_nWE : STD_LOGIC;
163 SIGNAL SRAM_CE : STD_LOGIC;
164 SIGNAL SRAM_nOE : STD_LOGIC;
165 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
167 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
168
169 -----------------------------------------------------------------------------
170
171 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0);
172 SIGNAL ADC_smpclk : STD_LOGIC;
173 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0);
174 SIGNAL HK_smpclk : STD_LOGIC;
175 SIGNAL ADC_OEB_bar_HK : STD_LOGIC;
176 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
177
178 SIGNAL all_OEB_bar : STD_LOGIC_VECTOR(8 DOWNTO 0);
179 SIGNAL HK_SEL_DATA : STD_LOGIC_VECTOR(13 DOWNTO 0);
180
181 -----------------------------------------------------------------------------
182
183 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
184 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
185 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
186
187
188 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
189 SIGNAL data_message : STRING(1 TO 15) := "---------------";
190 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
191
192 BEGIN
193
194 -----------------------------------------------------------------------------
195 -- TB
196 -----------------------------------------------------------------------------
197 PROCESS
198 CONSTANT txp : TIME := 320 ns;
199 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
200 BEGIN -- PROCESS
201 TXD1 <= '1';
202 reset <= '0';
203 WAIT FOR 500 ns;
204 reset <= '1';
205 WAIT FOR 10000 ns;
206 message_simu <= "0 - UART init ";
207 UART_INIT(TXD1,txp);
208
209 message_simu <= "1 - UART test ";
210 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
211 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
212 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
213 UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v);
214 data_read <= data_read_v;
215 data_message <= "GPIO_data_write";
216
217 -- UNSET the LFR reset
218 message_simu <= "2 - LFR UNRESET";
219 UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT);
220 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
221 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
222 --
223 message_simu <= "3 - LFR CONFIG ";
224 --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
225 LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR,
226 X"40000000",
227 X"40001000",
228 X"40002000",
229 X"40003000",
230 X"40004000",
231 X"40005000");
232
233
234 LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp,
235 LFR_MODE_SBM1,
236 X"7FFFFFFF", -- START DATE
237
238 "00000",--DATA_SHAPING ( 4 DOWNTO 0)
239 X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0)
240 X"0001280A",--DELTA_F0 (31 DOWNTO 0)
241 X"00000007",--DELTA_F0_2 (31 DOWNTO 0)
242 X"0001283F",--DELTA_F1 (31 DOWNTO 0)
243 X"000127FF",--DELTA_F2 (31 DOWNTO 0)
244
245 ADDR_BASE_LFR,
246 X"40006000",
247 X"40007000",
248 X"40008000",
249 X"40009000",
250 X"4000A000",
251 X"4000B000",
252 X"4000C000",
253 X"4000D000");
254
255 UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F");
256 UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
257
258 message_simu <= "4 - GO GO GO !!";
259 UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000");
260
261 READ_STATUS: LOOP
262 WAIT FOR 2 ms;
263 data_message <= "READ_NEW_STATUS";
264 UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
265 data_read <= data_read_v;
266 UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
267
268 UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v);
269 data_read <= data_read_v;
270 UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v);
271 END LOOP READ_STATUS;
272
273 WAIT;
274 END PROCESS;
275
276 -----------------------------------------------------------------------------
277 -- CLOCK
278 -----------------------------------------------------------------------------
279 clk_50 <= NOT clk_50 AFTER 5 ns;
280 clk_49 <= NOT clk_49 AFTER 10172 ps;
281
282 -----------------------------------------------------------------------------
283 -- DON'T CARE
284 -----------------------------------------------------------------------------
285 BP0 <= '0';
286 BP1 <= '0';
287 nRTS1 <= '0' ;
288
289 TXD2 <= '1';
290 nRTS2 <= '1';
291 nDTR2 <= '1';
292
293 SPW_NOM_DIN <= '1';
294 SPW_NOM_SIN <= '1';
295 SPW_RED_DIN <= '1';
296 SPW_RED_SIN <= '1';
297
298 ADC_SDO <= x"AA";
299
300 SRAM_DQ <= (OTHERS => 'Z');
301 --IO0 <= 'Z';
302 --IO1 <= 'Z';
303 --IO2 <= 'Z';
304 --IO3 <= 'Z';
305 --IO4 <= 'Z';
306 --IO5 <= 'Z';
307 --IO6 <= 'Z';
308 --IO7 <= 'Z';
309 --IO8 <= 'Z';
310 --IO9 <= 'Z';
311 --IO10 <= 'Z';
312 --IO11 <= 'Z';
313
314 -----------------------------------------------------------------------------
315 -- DUT
316 -----------------------------------------------------------------------------
317
318 LFR_em_1: LFR_em
319 PORT MAP (
320 clk100MHz => clk_50,
321 clk49_152MHz => clk_49,
322 reset => reset,
323
324 TAG1 => TXD1,
325 TAG3 => RXD1,
326 TAG2 => TXD2,
327 TAG4 => RXD2,
328
329 address => SRAM_A,
330 data => SRAM_DQ,
331 nSRAM_BE0 => SRAM_nBE(0),
332 nSRAM_BE1 => SRAM_nBE(1),
333 nSRAM_BE2 => SRAM_nBE(2),
334 nSRAM_BE3 => SRAM_nBE(3),
335 nSRAM_WE => SRAM_nWE,
336 nSRAM_CE => SRAM_CE,
337 nSRAM_OE => SRAM_nOE,
338
339 spw1_din => SPW_NOM_DIN,
340 spw1_sin => SPW_NOM_SIN,
341 spw1_dout => SPW_NOM_DOUT,
342 spw1_sout => SPW_NOM_SOUT,
343 spw2_din => SPW_RED_DIN,
344 spw2_sin => SPW_RED_SIN,
345 spw2_dout => SPW_RED_DOUT,
346 spw2_sout => SPW_RED_SOUT,
347
348 bias_fail_sw => OPEN,
349
350 ADC_OEB_bar_CH => ADC_OEB_bar_CH,
351 ADC_smpclk => ADC_smpclk,
352 ADC_data => ADC_data,
353 HK_smpclk => HK_smpclk,
354 ADC_OEB_bar_HK => ADC_OEB_bar_HK,
355 HK_SEL => HK_SEL,
356
357 TAG8 => OPEN,
358 led => OPEN);
359
360 all_OEB_bar <= ADC_OEB_bar_HK & ADC_OEB_bar_CH;
361
362 WITH HK_SEL SELECT
363 HK_SEL_DATA <=
364 "00"&X"00F" WHEN "00",
365 "00"&X"01F" WHEN "01",
366 "00"&X"02F" WHEN "10",
367 "XXXXXXXXXXXXXX" WHEN OTHERS;
368
369 WITH all_OEB_bar SELECT
370 ADC_data <=
371 "00"&X"000" WHEN "111111110",
372 "00"&X"001" WHEN "111111101",
373 "00"&X"002" WHEN "111111011",
374 "00"&X"003" WHEN "111110111",
375 "00"&X"004" WHEN "111101111",
376 "00"&X"005" WHEN "111011111",
377 "00"&X"006" WHEN "110111111",
378 "00"&X"007" WHEN "101111111",
379 HK_SEL_DATA WHEN "011111111",
380 "XXXXXXXXXXXXXX" WHEN OTHERS;
381
382 END;
Show file before | Show file after | Hide comments
@@ -0,0 +1,28
1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -radix hexadecimal -childformat {{/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0 -radix hexadecimal -childformat {{/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(15) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(14) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(13) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(12) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(11) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(10) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(9) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(8) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(7) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(6) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(5) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(4) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(3) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(2) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(1) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(0) -radix hexadecimal}}} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_1 -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_2 -radix hexadecimal}} -expand -subitemconfig {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0 {-radix hexadecimal -childformat {{/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(15) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(14) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(13) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(12) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(11) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(10) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(9) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(8) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(7) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(6) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(5) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(4) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(3) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(2) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(1) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(0) -radix hexadecimal}}} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(15) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(14) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(13) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(12) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(11) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(10) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(9) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(8) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(7) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(6) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(5) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(4) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(3) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(2) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(1) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(0) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_1 {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_2 {-radix hexadecimal}} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk
4 add wave -noupdate /testbench/LFR_em_1/ADC_data
5 add wave -noupdate /testbench/LFR_em_1/ADC_data
6 add wave -noupdate /testbench/LFR_em_1/HK_SEL
7 add wave -noupdate /testbench/LFR_em_1/ADC_OEB_bar_HK
8 add wave -noupdate /testbench/LFR_em_1/HK_smpclk
9 add wave -noupdate /testbench/LFR_em_1/ADC_smpclk
10 add wave -noupdate /testbench/LFR_em_1/ADC_OEB_bar_CH
11 TreeUpdate [SetDefaultTree]
12 WaveRestoreCursors {{Cursor 1} {0 ps} 0}
13 quietly wave cursor active 0
14 configure wave -namecolwidth 233
15 configure wave -valuecolwidth 100
16 configure wave -justifyvalue left
17 configure wave -signalnamewidth 0
18 configure wave -snapdistance 10
19 configure wave -datasetprefix 0
20 configure wave -rowmargin 4
21 configure wave -childrowmargin 2
22 configure wave -gridoffset 0
23 configure wave -gridperiod 1
24 configure wave -griddelta 40
25 configure wave -timeline 0
26 configure wave -timelineunits ns
27 update
28 WaveRestoreZoom {934646651 ps} {1003439650 ps}
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