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Update SDC constraint for LFR-EM board
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r424:de01672a1e7f JC
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1 # Top Level Design Parameters
2
3 # Clocks
4
5 create_clock -period 10.000000 -waveform {0.000000 5.000000} clk100MHz
6 create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz
7 create_clock -period 20.000000 -waveform {0.000000 10.000000} clk_50_s:Q
8 create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25:Q
9 create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q
10 create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {SPW1_DIN SPW1_SIN SPW2_DIN SPW2_SIN}
11
12
13 # False Paths Between Clocks
14
15
16 # False Path Constraints
17
18
19 # Maximum Delay Constraints
20
21
22 # Multicycle Constraints
23
24
25 # Virtual Clocks
26 # Output Load Constraints
27 # Driving Cell Constraints
28 # Wire Loads
29 # set_wire_load_mode top
30
31 # Other Constraints
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1 # Synplicity, Inc. constraint file
2 # /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc
3 # Written on Wed Aug 1 19:29:24 2007
4 # by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor
5
6 #
7 # Collections
8 #
9
10 #
11 # Clocks
12 #
13
14
15 define_clock {clk100MHz} -name {clk100MHz} -freq 100 -clockgroup default_clkgroup -route 5
16 define_clock {clk49_152MHz} -name {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup -route 5
17
18 #
19 # Clock to Clock
20 #
21
22 #
23 # Inputs/Outputs
24 #
25 define_output_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r}
26 define_input_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r}
27
28
29 #
30 # Registers
31 #
32
33 #
34 # Multicycle Path
35 #
36
37 #
38 # False Path
39 #
40
41 #
42 # Path Delay
43 #
44
45 #
46 # Attributes
47 #
48 define_global_attribute syn_useioff {1}
49 define_global_attribute -disable syn_netlist_hierarchy {0}
50 define_attribute {etx_clk} syn_noclockbuf {1}
51
52 #
53 # I/O standards
54 #
55
56 #
57 # Compile Points
58 #
59
60 #
61 # Other Constraints
62 #
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1 #GRLIB=../..
1 #GRLIB=../..
2 VHDLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=LFR_em
5 TOP=LFR_em
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
11 EFFORT=high
12 XSTOPT=
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
16 VHDLSYNFILES=LFR-em.vhd
16 VHDLSYNFILES=LFR-em.vhd
17 #VHDLSIMFILES=testbench.vhd
17 #VHDLSIMFILES=testbench.vhd
18 #SIMTOP=testbench
18 #SIMTOP=testbench
19 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
20 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
20 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
21 PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
21 PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
22
23 SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
24 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc
25
22 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
26 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
23 CLEAN=soft-clean
27 CLEAN=soft-clean
24
28
25 TECHLIBS = proasic3e
29 TECHLIBS = proasic3e
26
30
27 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
31 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
28 tmtc openchip hynix ihp gleichmann micron usbhc
32 tmtc openchip hynix ihp gleichmann micron usbhc
29
33
30 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
34 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
31 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
35 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
32 ./amba_lcd_16x2_ctrlr \
36 ./amba_lcd_16x2_ctrlr \
33 ./general_purpose/lpp_AMR \
37 ./general_purpose/lpp_AMR \
34 ./general_purpose/lpp_balise \
38 ./general_purpose/lpp_balise \
35 ./general_purpose/lpp_delay \
39 ./general_purpose/lpp_delay \
36 ./lpp_bootloader \
40 ./lpp_bootloader \
37 ./lpp_cna \
41 ./lpp_cna \
38 ./dsp/lpp_fft_rtax \
42 ./dsp/lpp_fft_rtax \
39 ./lpp_uart \
43 ./lpp_uart \
40 ./lpp_usb \
44 ./lpp_usb \
41
45
42 FILESKIP = i2cmst.vhd \
46 FILESKIP = i2cmst.vhd \
43 APB_MULTI_DIODE.vhd \
47 APB_MULTI_DIODE.vhd \
44 APB_MULTI_DIODE.vhd \
48 APB_MULTI_DIODE.vhd \
45 Top_MatrixSpec.vhd \
49 Top_MatrixSpec.vhd \
46 APB_FFT.vhd
50 APB_FFT.vhd
47
51
48 include $(GRLIB)/bin/Makefile
52 include $(GRLIB)/bin/Makefile
49 include $(GRLIB)/software/leon3/Makefile
53 include $(GRLIB)/software/leon3/Makefile
50
54
51 ################## project specific targets ##########################
55 ################## project specific targets ##########################
52
56
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