##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

update
pellion -
r359:ddd83014c899 JC
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,129
1 LIBRARY IEEE;
2 USE IEEE.std_logic_1164.ALL;
3 USE IEEE.numeric_std.ALL;
4
5 ENTITY MS_control IS
6 PORT (
7 clk : IN STD_LOGIC;
8 rstn : IN STD_LOGIC;
9
10 -- IN
11 fifo_in_lock : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
12 fifo_in_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
13 fifo_in_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
14 fifo_in_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
15 fifo_in_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
16 fifo_in_reuse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
17 -- OUT
18 fifo_out_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
19 fifo_out_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
20 fifo_out_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
21 -- OUT
22 correlation_start : OUT STD_LOGIC;
23 correlation_auto : OUT STD_LOGIC; -- 1 => auto correlation / 0 => inter correlation
24 correlation_done : IN STD_LOGIC
25 );
26 END MS_control;
27
28 ARCHITECTURE beh OF MS_control IS
29
30 TYPE fsm_control_MS IS (WAIT_DATA, CORRELATION_ONGOING);
31 SIGNAL state : fsm_control_MS;
32
33 SUBTYPE fifo_pointer IS RANGE 0 TO 4;
34 SIGNAL fifo_1 : fifo_pointer;
35 SIGNAL fifo_2 : fifo_pointer;
36
37 SIGNAL fifo_in_lock_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
38 SIGNAL fifo_in_reuse_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
39
40 BEGIN -- beh
41
42 fifo_in_lock <= fifo_in_lock_s;
43 fifo_in_reuse <= fifo_in_reuse_s;
44
45 PROCESS (clk, rstn)
46 BEGIN
47 IF rstn = '0' THEN
48 state <= WAIT_DATA;
49 fifo_1 <= 0;
50 fifo_2 <= 0;
51 fifo_in_lock_s <= (OTHERS => '0');
52 fifo_in_reuse_s <= (OTHERS => '0');
53 correlation_start <= '0';
54 correlation_auto <= '0';
55 ELSIF clk'event AND clk = '1' THEN
56 CASE state IS
57 WHEN WAIT_DATA =>
58 fifo_in_reuse_s <= (OTHERS => '0');
59 IF fifo_in_full[fifo_1] = '1' AND fifo_in_full[fifo_2] = '1' THEN
60 fifo_in_lock_s(fifo_1) <= '1';
61 fifo_in_lock_s(fifo_2) <= '1';
62 correlation_start <= '1';
63 IF fifo_1 = fifo_2 THEN
64 correlation_auto <= '1';
65 END IF;
66 state <= CORRELATION_ONGOING;
67 END IF;
68
69 WHEN CORRELATION_ONGOING =>
70 correlation_start <= '0';
71 correlation_auto <= '0';
72 IF correlation_done = '1' THEN
73 state <= WAIT_DATA;
74 IF fifo_2 = 4 THEN
75 fifo_in_lock_s(fifo_1) <= '0';
76 IF fifo_1 = 4 THEN
77 fifo_1 <= 0;
78 fifo_2 <= 0;
79 ELSE
80 fifo_in_reuse_s(fifo_2) <= '1';
81 fifo_1 <= fifo_1 + 1;
82 fifo_2 <= fifo_1 + 1;
83 END IF;
84 ELSE
85 fifo_in_reuse_s(fifo_2) <= '1';
86 fifo_in_reuse_s(fifo_1) <= '1';
87 fifo_2 <= fifo_2 + 1;
88 END IF;
89 END IF;
90
91 WHEN OTHERS => NULL;
92 END CASE;
93 END IF;
94 END PROCESS;
95
96
97 fifo_out_data(31 DOWNTO 0) <= fifo_in_data(31*1-1 DOWNTO 32*0) WHEN fifo_1 = 0 ELSE
98 fifo_in_data(32*2-1 DOWNTO 32*1) WHEN fifo_1 = 1 ELSE
99 fifo_in_data(32*3-1 DOWNTO 32*2) WHEN fifo_1 = 2 ELSE
100 fifo_in_data(32*4-1 DOWNTO 32*3) WHEN fifo_1 = 3 ELSE
101 fifo_in_data(32*5-1 DOWNTO 32*4);-- WHEN fifo_1 = 4
102
103
104 fifo_out_data(63 DOWNTO 32) <= fifo_in_data(31*1-1 DOWNTO 32*0) WHEN fifo_2 = 0 ELSE
105 fifo_in_data(32*2-1 DOWNTO 32*1) WHEN fifo_2 = 1 ELSE
106 fifo_in_data(32*3-1 DOWNTO 32*2) WHEN fifo_2 = 2 ELSE
107 fifo_in_data(32*4-1 DOWNTO 32*3) WHEN fifo_2 = 3 ELSE
108 fifo_in_data(32*5-1 DOWNTO 32*4);-- WHEN fifo_2 = 4
109
110 fifo_out_empty(0) <= fifo_in_empty(0) WHEN fifo_1 = 0 ELSE
111 fifo_in_empty(1) WHEN fifo_1 = 1 ELSE
112 fifo_in_empty(2) WHEN fifo_1 = 2 ELSE
113 fifo_in_empty(3) WHEN fifo_1 = 3 ELSE
114 fifo_in_empty(4);
115
116 fifo_out_empty(1) <= fifo_in_empty(0) WHEN fifo_2 = 0 ELSE
117 fifo_in_empty(1) WHEN fifo_2 = 1 ELSE
118 fifo_in_empty(2) WHEN fifo_2 = 2 ELSE
119 fifo_in_empty(3) WHEN fifo_2 = 3 ELSE
120 fifo_in_empty(4);
121
122
123 all_fifo: FOR I IN 0 TO 4 GENERATE
124 fifo_in_ren(I) <= fifo_out_ren(I) WHEN fifo_1 = I ELSE
125 fifo_out_ren(I) WHEN fifo_2 = I ELSE
126 '1';
127 END GENERATE all_fifo;
128
129 END beh;
Show file before | Show file after | Hide comments
@@ -1,429 +1,430
1 1 VHDLIB=../..
2 2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 3
4 4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 5 TOP=TB
6 6
7 7 CMD_VLIB=vlib
8 8 CMD_VMAP=vmap
9 9 CMD_VCOM=@vcom -quiet -93 -work
10 10
11 11 ################## project specific targets ##########################
12 12
13 13 all:
14 14 @echo "make vsim"
15 15 @echo "make libs"
16 16 @echo "make clean"
17 17 @echo "make vcom_grlib vcom_lpp vcom_tb"
18 18
19 19 run:
20 20 @vsim work.TB -do run.do
21 21 # @vsim work.TB
22 22 # @vsim lpp.lpp_lfr_ms
23 23
24 24 vsim: libs vcom run
25 25
26 26 libs:
27 27 @$(CMD_VLIB) modelsim
28 28 @$(CMD_VMAP) modelsim modelsim
29 29 @$(CMD_VLIB) modelsim/techmap
30 30 @$(CMD_VMAP) techmap modelsim/techmap
31 31 @$(CMD_VLIB) modelsim/grlib
32 32 @$(CMD_VMAP) grlib modelsim/grlib
33 33 @$(CMD_VLIB) modelsim/gaisler
34 34 @$(CMD_VMAP) gaisler modelsim/gaisler
35 35 @$(CMD_VLIB) modelsim/work
36 36 @$(CMD_VMAP) work modelsim/work
37 37 @$(CMD_VLIB) modelsim/lpp
38 38 @$(CMD_VMAP) lpp modelsim/lpp
39 39 @echo "libs done"
40 40
41 41
42 42 clean:
43 43 @rm -Rf modelsim
44 44 @rm -Rf modelsim.ini
45 45 @rm -Rf *~
46 46 @rm -Rf transcript
47 47 @rm -Rf wlft*
48 48 @rm -Rf *.wlf
49 49 @rm -Rf vish_stacktrace.vstf
50 50 @rm -Rf libs.do
51 51
52 52 vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_tb
53 53
54 54
55 55 vcom_tb:
56 56 $(CMD_VCOM) lpp lpp_memory.vhd
57 57 $(CMD_VCOM) lpp lppFIFOxN.vhd
58 58 $(CMD_VCOM) lpp lpp_FIFO.vhd
59 59 $(CMD_VCOM) lpp spectral_matrix_package.vhd
60 60 $(CMD_VCOM) lpp spectral_matrix_switch_f0.vhd
61 61 $(CMD_VCOM) lpp spectral_matrix_time_managment.vhd
62 62 $(CMD_VCOM) lpp lpp_lfr_ms.vhd
63 63 $(CMD_VCOM) work TB.vhd
64 64 @echo "vcom done"
65 65
66 66 vcom_grlib:
67 67 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd
68 68 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd
69 69 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd
70 70 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd
71 71 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd
72 72 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd
73 73 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd
74 74 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd
75 75 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd
76 76 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd
77 77 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd
78 78 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd
79 79 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd
80 80 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd
81 81 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd
82 82 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd
83 83 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd
84 84 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd
85 85 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd
86 86 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd
87 87 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd
88 88 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd
89 89 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd
90 90 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd
91 91 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd
92 92 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd
93 93 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd
94 94 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd
95 95 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd
96 96 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd
97 97 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd
98 98 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd
99 99 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd
100 100 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd
101 101 @echo "vcom grlib done"
102 102
103 103 vcom_gaisler:
104 104 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd
105 105 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd
106 106 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd
107 107 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd
108 108 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd
109 109 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd
110 110 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd
111 111 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd
112 112 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd
113 113 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd
114 114 # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd
115 115 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd
116 116 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd
117 117 # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd
118 118 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd
119 119 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd
120 120 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd
121 121 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd
122 122 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd
123 123 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd
124 124 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd
125 125 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd
126 126 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd
127 127 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd
128 128 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd
129 129 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd
130 130 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd
131 131 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd
132 132 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd
133 133 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd
134 134 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd
135 135 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd
136 136 # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd
137 137 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd
138 138 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd
139 139 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd
140 140 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd
141 141 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd
142 142 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd
143 143 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd
144 144 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd
145 145 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd
146 146 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd
147 147 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd
148 148 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd
149 149 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd
150 150 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd
151 151 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd
152 152 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd
153 153 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd
154 154 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd
155 155 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd
156 156 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd
157 157 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd
158 158 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd
159 159 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd
160 160 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd
161 161 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd
162 162 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd
163 163 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd
164 164 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd
165 165 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd
166 166 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd
167 167 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd
168 168 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd
169 169 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd
170 170 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd
171 171 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd
172 172 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd
173 173 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd
174 174 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd
175 175 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd
176 176 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd
177 177 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd
178 178 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd
179 179 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd
180 180 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd
181 181 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd
182 182 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd
183 183 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd
184 184 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd
185 185 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd
186 186 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd
187 187 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd
188 188 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd
189 189 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd
190 190 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd
191 191 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd
192 192 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd
193 193 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd
194 194 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd
195 195 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd
196 196 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd
197 197 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd
198 198 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd
199 199 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd
200 200 ## $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd
201 201 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd
202 202 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd
203 203 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd
204 204 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd
205 205 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd
206 206 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd
207 207 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd
208 208 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd
209 209 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd
210 210 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd
211 211 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd
212 212 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd
213 213 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd
214 214 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd
215 215 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd
216 216 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd
217 217 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd
218 218 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd
219 219 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd
220 220 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd
221 221 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd
222 222 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd
223 223 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd
224 224 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd
225 225 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd
226 226 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd
227 227 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd
228 228 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd
229 229 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd
230 230 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd
231 231 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd
232 232 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd
233 233 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd
234 234 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd
235 235 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd
236 236 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd
237 237 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd
238 238 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd
239 239 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd
240 240 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd
241 241 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd
242 242 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd
243 243 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd
244 244 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd
245 245 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd
246 246 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd
247 247 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd
248 248 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd
249 249 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd
250 250 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd
251 251 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd
252 252 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd
253 253 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd
254 254 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd
255 255 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd
256 256 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd
257 257 @echo "vcom gaisler done"
258 258
259 259 vcom_techmap:
260 260 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd
261 261 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd
262 262 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd
263 263 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd
264 264 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd
265 265 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd
266 266 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd
267 267 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd
268 268 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd
269 269 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd
270 270 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd
271 271 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd
272 272 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd
273 273 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd
274 274 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd
275 275 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd
276 276 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd
277 277 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd
278 278 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd
279 279 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd
280 280 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd
281 281 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd
282 282 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd
283 283 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd
284 284 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd
285 285 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd
286 286 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd
287 287 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd
288 288 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd
289 289 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd
290 290 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd
291 291 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd
292 292 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd
293 293 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd
294 294 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd
295 295 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd
296 296 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd
297 297 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd
298 298 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd
299 299 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd
300 300 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd
301 301 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd
302 302 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd
303 303 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd
304 304 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd
305 305 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd
306 306 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd
307 307 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd
308 308 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd
309 309 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd
310 310 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd
311 311 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd
312 312 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd
313 313 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd
314 314 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd
315 315 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd
316 316 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd
317 317 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd
318 318 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd
319 319 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd
320 320 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd
321 321 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd
322 322 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd
323 323 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd
324 324 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd
325 325 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd
326 326 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd
327 327 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd
328 328 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd
329 329 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd
330 330 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd
331 331 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd
332 332 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd
333 333 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd
334 334 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd
335 335 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd
336 336 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd
337 337 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd
338 338 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd
339 339 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd
340 340 @echo "vcom techmap done"
341 341
342 342 vcom_lpp:
343 343 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd
344 344 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd
345 345 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
346 346 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd
347 347 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd
348 348 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd
349 349 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
350 350 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
351 351 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
352 352 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
353 353 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
354 354 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
355 355 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
356 356 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
357 357 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
358 358 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
359 359 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
360 360 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
361 361 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
362 362 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
363 363 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
364 364 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
365 365 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
366 366 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
367 367 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
368 368 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
369 369 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
370 370 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
371 371 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
372 372 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
373 373 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
374 374 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
375 375 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd
376 376 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
377 377 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd
378 378 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd
379 379 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
380 380 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd
381 381 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd
382 382 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd
383 383 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd
384 384 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd
385 385 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
386 386 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd
387 387 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd
388 388 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd
389 389 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd
390 390 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd
391 $(CMD_VCOM) lpp lpp_memory.vhd
391 392 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd
392 393 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
393 394 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
394 395 @echo "vcom lpp done"
395 396
396 397 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
397 398 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
398 399 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
399 400 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
400 401 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
401 402 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
402 403 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
403 404 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
404 405 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
405 406 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
406 407 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
407 408 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
408 409 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
409 410 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
410 411 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
411 412 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
412 413 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
413 414 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
414 415 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
415 416 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
416 417 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
417 418 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
418 419 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
419 420 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
420 421 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
421 422 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
422 423 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd
423 424 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd
424 425 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd
425 426 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd
426 427 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd
427 428 # @echo "vcom lpp done"
428 429
429 430 #include Makefile_vcom_lpp
Show file before | Show file after | Hide comments
@@ -1,895 +1,899
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_memory.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.spectral_matrix_package.ALL;
9 9 USE lpp.lpp_dma_pkg.ALL;
10 10 USE lpp.lpp_Header.ALL;
11 11 USE lpp.lpp_matrix.ALL;
12 12 USE lpp.lpp_matrix.ALL;
13 13 USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.lpp_fft.ALL;
15 15 USE lpp.fft_components.ALL;
16 16
17 17 ENTITY lpp_lfr_ms IS
18 18 GENERIC (
19 19 Mem_use : INTEGER := use_RAM
20 20 );
21 21 PORT (
22 22 clk : IN STD_LOGIC;
23 23 rstn : IN STD_LOGIC;
24 24
25 25 ---------------------------------------------------------------------------
26 26 -- DATA INPUT
27 27 ---------------------------------------------------------------------------
28 28 -- TIME
29 29 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
30 30 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
31 31 --
32 32 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 33 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 34 --
35 35 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 36 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 37 --
38 38 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 39 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40 40
41 41 ---------------------------------------------------------------------------
42 42 -- DMA
43 43 ---------------------------------------------------------------------------
44 44 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
45 45 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
46 46 dma_valid : OUT STD_LOGIC;
47 47 dma_valid_burst : OUT STD_LOGIC;
48 48 dma_ren : IN STD_LOGIC;
49 49 dma_done : IN STD_LOGIC;
50 50
51 51 -- Reg out
52 52 ready_matrix_f0_0 : OUT STD_LOGIC;
53 53 ready_matrix_f0_1 : OUT STD_LOGIC;
54 54 ready_matrix_f1 : OUT STD_LOGIC;
55 55 ready_matrix_f2 : OUT STD_LOGIC;
56 56 error_anticipating_empty_fifo : OUT STD_LOGIC;
57 57 error_bad_component_error : OUT STD_LOGIC;
58 58 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
59 59
60 60 -- Reg In
61 61 status_ready_matrix_f0_0 : IN STD_LOGIC;
62 62 status_ready_matrix_f0_1 : IN STD_LOGIC;
63 63 status_ready_matrix_f1 : IN STD_LOGIC;
64 64 status_ready_matrix_f2 : IN STD_LOGIC;
65 65 status_error_anticipating_empty_fifo : IN STD_LOGIC;
66 66 status_error_bad_component_error : IN STD_LOGIC;
67 67
68 68 config_active_interruption_onNewMatrix : IN STD_LOGIC;
69 69 config_active_interruption_onError : IN STD_LOGIC;
70 70 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71 71 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74 74
75 75 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
76 76 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
77 77 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
78 78 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
79 79
80 80 );
81 81 END;
82 82
83 83 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
84 84
85 85 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
86 86 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 87 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 88 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
89 89 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
90 90
91 91 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
92 92 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 93 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 94 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
95 95 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
96 96
97 97 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
98 98 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 99 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 100 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
101 101
102 102 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
103 103
104 104 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
105 105 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 106 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 107 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
108 108
109 109 SIGNAL error_wen_f0 : STD_LOGIC;
110 110 SIGNAL error_wen_f1 : STD_LOGIC;
111 111 SIGNAL error_wen_f2 : STD_LOGIC;
112 112
113 113 SIGNAL one_sample_f1_full : STD_LOGIC;
114 114 SIGNAL one_sample_f1_wen : STD_LOGIC;
115 115 SIGNAL one_sample_f2_full : STD_LOGIC;
116 116 SIGNAL one_sample_f2_wen : STD_LOGIC;
117 117
118 118 -----------------------------------------------------------------------------
119 119 -- FSM / SWITCH SELECT CHANNEL
120 120 -----------------------------------------------------------------------------
121 121 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
122 122 SIGNAL state_fsm_select_channel : fsm_select_channel;
123 123 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
124 124
125 125 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
126 126 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
127 127 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
128 128 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
129 129
130 130 -----------------------------------------------------------------------------
131 131 -- FSM LOAD FFT
132 132 -----------------------------------------------------------------------------
133 133 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
134 134 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
135 135 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
136 136
137 137 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
138 138 SIGNAL sample_load : STD_LOGIC;
139 139 SIGNAL sample_valid : STD_LOGIC;
140 140 SIGNAL sample_valid_r : STD_LOGIC;
141 141 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
142 142
143 143
144 144 -----------------------------------------------------------------------------
145 145 -- FFT
146 146 -----------------------------------------------------------------------------
147 147 SIGNAL fft_read : STD_LOGIC;
148 148 SIGNAL fft_pong : STD_LOGIC;
149 149 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
150 150 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
151 151 SIGNAL fft_data_valid : STD_LOGIC;
152 152 SIGNAL fft_ready : STD_LOGIC;
153 153 -----------------------------------------------------------------------------
154 154 SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
155 155 -----------------------------------------------------------------------------
156 156 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
157 157 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
158 158 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
159 159 SIGNAL current_fifo_empty : STD_LOGIC;
160 160 SIGNAL current_fifo_locked : STD_LOGIC;
161 161 SIGNAL current_fifo_full : STD_LOGIC;
162 162 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
163 163
164 164 -----------------------------------------------------------------------------
165 165 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 166 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 167 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 168 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
169 169 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
170 170 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
171 171 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
172 172 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
173 173 -----------------------------------------------------------------------------
174 174 SIGNAL HEAD_SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
175 175 SIGNAL HEAD_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
176 176 SIGNAL HEAD_SM_Wen : STD_LOGIC;
177 177 SIGNAL HEAD_Valid : STD_LOGIC;
178 178 SIGNAL HEAD_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 179 SIGNAL HEAD_Empty : STD_LOGIC;
180 180 SIGNAL HEAD_Read : STD_LOGIC;
181 181 -----------------------------------------------------------------------------
182 182 SIGNAL MEM_OUT_SM_ReUse : STD_LOGIC_VECTOR(1 DOWNTO 0);
183 183 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
184 184 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
185 185 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
186 186 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
187 187 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
188 188 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
189 189 -----------------------------------------------------------------------------
190 190 SIGNAL DMA_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 191 SIGNAL DMA_Header_Val : STD_LOGIC;
192 192 SIGNAL DMA_Header_Ack : STD_LOGIC;
193 193
194 194 -----------------------------------------------------------------------------
195 195 -- TIME REG & INFOs
196 196 -----------------------------------------------------------------------------
197 197 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
198 198
199 199 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
200 200 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
201 201 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
202 202 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
203 203
204 204 SIGNAL time_update_f0_A : STD_LOGIC;
205 205 SIGNAL time_update_f0_B : STD_LOGIC;
206 206 SIGNAL time_update_f1 : STD_LOGIC;
207 207 SIGNAL time_update_f2 : STD_LOGIC;
208 208 --
209 209 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
210 210
211 211 SIGNAL dma_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
212 212 -----------------------------------------------------------------------------
213 213
214 214 BEGIN
215 215
216 216 switch_f0_inst : spectral_matrix_switch_f0
217 217 PORT MAP (
218 218 clk => clk,
219 219 rstn => rstn,
220 220
221 221 sample_wen => sample_f0_wen,
222 222
223 223 fifo_A_empty => sample_f0_A_empty,
224 224 fifo_A_full => sample_f0_A_full,
225 225 fifo_A_wen => sample_f0_A_wen,
226 226
227 227 fifo_B_empty => sample_f0_B_empty,
228 228 fifo_B_full => sample_f0_B_full,
229 229 fifo_B_wen => sample_f0_B_wen,
230 230
231 231 error_wen => error_wen_f0); -- TODO
232 232
233 233 -----------------------------------------------------------------------------
234 234 -- FIFO IN
235 235 -----------------------------------------------------------------------------
236 236 lppFIFOxN_f0_a : lppFIFOxN
237 237 GENERIC MAP (
238 238 tech => 0,
239 239 Mem_use => Mem_use,
240 240 Data_sz => 16,
241 241 Addr_sz => 8,
242 242 FifoCnt => 5)
243 243 PORT MAP (
244 244 clk => clk,
245 245 rstn => rstn,
246 246
247 247 ReUse => (OTHERS => '0'),
248 248
249 249 wen => sample_f0_A_wen,
250 250 wdata => sample_f0_wdata,
251 251
252 252 ren => sample_f0_A_ren,
253 253 rdata => sample_f0_A_rdata,
254 254
255 255 empty => sample_f0_A_empty,
256 256 full => sample_f0_A_full,
257 257 almost_full => OPEN);
258 258
259 259 lppFIFOxN_f0_b : lppFIFOxN
260 260 GENERIC MAP (
261 261 tech => 0,
262 262 Mem_use => Mem_use,
263 263 Data_sz => 16,
264 264 Addr_sz => 8,
265 265 FifoCnt => 5)
266 266 PORT MAP (
267 267 clk => clk,
268 268 rstn => rstn,
269 269
270 270 ReUse => (OTHERS => '0'),
271 271
272 272 wen => sample_f0_B_wen,
273 273 wdata => sample_f0_wdata,
274 274 ren => sample_f0_B_ren,
275 275 rdata => sample_f0_B_rdata,
276 276 empty => sample_f0_B_empty,
277 277 full => sample_f0_B_full,
278 278 almost_full => OPEN);
279 279
280 280 lppFIFOxN_f1 : lppFIFOxN
281 281 GENERIC MAP (
282 282 tech => 0,
283 283 Mem_use => Mem_use,
284 284 Data_sz => 16,
285 285 Addr_sz => 8,
286 286 FifoCnt => 5)
287 287 PORT MAP (
288 288 clk => clk,
289 289 rstn => rstn,
290 290
291 291 ReUse => (OTHERS => '0'),
292 292
293 293 wen => sample_f1_wen,
294 294 wdata => sample_f1_wdata,
295 295 ren => sample_f1_ren,
296 296 rdata => sample_f1_rdata,
297 297 empty => sample_f1_empty,
298 298 full => sample_f1_full,
299 299 almost_full => sample_f1_almost_full);
300 300
301 301
302 302 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
303 303
304 304 PROCESS (clk, rstn)
305 305 BEGIN -- PROCESS
306 306 IF rstn = '0' THEN -- asynchronous reset (active low)
307 307 one_sample_f1_full <= '0';
308 308 error_wen_f1 <= '0';
309 309 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
310 310 IF sample_f1_full = "00000" THEN
311 311 one_sample_f1_full <= '0';
312 312 ELSE
313 313 one_sample_f1_full <= '1';
314 314 END IF;
315 315 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
316 316 END IF;
317 317 END PROCESS;
318 318
319 319
320 320 lppFIFOxN_f2 : lppFIFOxN
321 321 GENERIC MAP (
322 322 tech => 0,
323 323 Mem_use => Mem_use,
324 324 Data_sz => 16,
325 325 Addr_sz => 8,
326 326 FifoCnt => 5)
327 327 PORT MAP (
328 328 clk => clk,
329 329 rstn => rstn,
330 330
331 331 ReUse => (OTHERS => '0'),
332 332
333 333 wen => sample_f2_wen,
334 334 wdata => sample_f2_wdata,
335 335 ren => sample_f2_ren,
336 336 rdata => sample_f2_rdata,
337 337 empty => sample_f2_empty,
338 338 full => sample_f2_full,
339 339 almost_full => OPEN);
340 340
341 341
342 342 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
343 343
344 344 PROCESS (clk, rstn)
345 345 BEGIN -- PROCESS
346 346 IF rstn = '0' THEN -- asynchronous reset (active low)
347 347 one_sample_f2_full <= '0';
348 348 error_wen_f2 <= '0';
349 349 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
350 350 IF sample_f2_full = "00000" THEN
351 351 one_sample_f2_full <= '0';
352 352 ELSE
353 353 one_sample_f2_full <= '1';
354 354 END IF;
355 355 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
356 356 END IF;
357 357 END PROCESS;
358 358
359 359 -----------------------------------------------------------------------------
360 360 -- FSM SELECT CHANNEL
361 361 -----------------------------------------------------------------------------
362 362 PROCESS (clk, rstn)
363 363 BEGIN
364 364 IF rstn = '0' THEN
365 365 state_fsm_select_channel <= IDLE;
366 366 ELSIF clk'EVENT AND clk = '1' THEN
367 367 CASE state_fsm_select_channel IS
368 368 WHEN IDLE =>
369 369 IF sample_f1_full = "11111" THEN
370 370 state_fsm_select_channel <= SWITCH_F1;
371 371 ELSIF sample_f1_almost_full = "00000" THEN
372 372 IF sample_f0_A_full = "11111" THEN
373 373 state_fsm_select_channel <= SWITCH_F0_A;
374 374 ELSIF sample_f0_B_full = "11111" THEN
375 375 state_fsm_select_channel <= SWITCH_F0_B;
376 376 ELSIF sample_f2_full = "11111" THEN
377 377 state_fsm_select_channel <= SWITCH_F2;
378 378 END IF;
379 379 END IF;
380 380
381 381 WHEN SWITCH_F0_A =>
382 382 IF sample_f0_A_empty = "11111" THEN
383 383 state_fsm_select_channel <= IDLE;
384 384 END IF;
385 385 WHEN SWITCH_F0_B =>
386 386 IF sample_f0_B_empty = "11111" THEN
387 387 state_fsm_select_channel <= IDLE;
388 388 END IF;
389 389 WHEN SWITCH_F1 =>
390 390 IF sample_f1_empty = "11111" THEN
391 391 state_fsm_select_channel <= IDLE;
392 392 END IF;
393 393 WHEN SWITCH_F2 =>
394 394 IF sample_f2_empty = "11111" THEN
395 395 state_fsm_select_channel <= IDLE;
396 396 END IF;
397 397 WHEN OTHERS => NULL;
398 398 END CASE;
399 399
400 400 END IF;
401 401 END PROCESS;
402 402
403 403 PROCESS (clk, rstn)
404 404 BEGIN
405 405 IF rstn = '0' THEN
406 406 pre_state_fsm_select_channel <= IDLE;
407 407 ELSIF clk'EVENT AND clk = '1' THEN
408 408 pre_state_fsm_select_channel <= state_fsm_select_channel;
409 409 END IF;
410 410 END PROCESS;
411 411
412 412
413 413 -----------------------------------------------------------------------------
414 414 -- SWITCH SELECT CHANNEL
415 415 -----------------------------------------------------------------------------
416 416 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
417 417 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
418 418 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
419 419 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
420 420 (OTHERS => '1');
421 421
422 422 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
423 423 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
424 424 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
425 425 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
426 426 (OTHERS => '0');
427 427
428 428 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
429 429 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
430 430 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
431 431 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
432 432
433 433
434 434 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
435 435 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
436 436 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
437 437 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
438 438
439 439
440 440 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
441 441 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
442 442 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
443 443 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
444 444
445 445 -----------------------------------------------------------------------------
446 446 -- FSM LOAD FFT
447 447 -----------------------------------------------------------------------------
448 448
449 449 sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1');
450 450
451 451 PROCESS (clk, rstn)
452 452 BEGIN
453 453 IF rstn = '0' THEN
454 454 sample_ren_s <= (OTHERS => '1');
455 455 state_fsm_load_FFT <= IDLE;
456 456 --next_state_fsm_load_FFT <= IDLE;
457 457 --sample_valid <= '0';
458 458 ELSIF clk'EVENT AND clk = '1' THEN
459 459 CASE state_fsm_load_FFT IS
460 460 WHEN IDLE =>
461 461 --sample_valid <= '0';
462 462 sample_ren_s <= (OTHERS => '1');
463 463 IF sample_full = "11111" AND sample_load = '1' THEN
464 464 state_fsm_load_FFT <= FIFO_1;
465 465 END IF;
466 466
467 467 WHEN FIFO_1 =>
468 468 sample_ren_s <= "1111" & NOT(sample_load);
469 469 IF sample_empty(0) = '1' THEN
470 470 sample_ren_s <= (OTHERS => '1');
471 471 state_fsm_load_FFT <= FIFO_2;
472 472 END IF;
473 473
474 474 WHEN FIFO_2 =>
475 475 sample_ren_s <= "111" & NOT(sample_load) & '1';
476 476 IF sample_empty(1) = '1' THEN
477 477 sample_ren_s <= (OTHERS => '1');
478 478 state_fsm_load_FFT <= FIFO_3;
479 479 END IF;
480 480
481 481 WHEN FIFO_3 =>
482 482 sample_ren_s <= "11" & NOT(sample_load) & "11";
483 483 IF sample_empty(2) = '1' THEN
484 484 sample_ren_s <= (OTHERS => '1');
485 485 state_fsm_load_FFT <= FIFO_4;
486 486 END IF;
487 487
488 488 WHEN FIFO_4 =>
489 489 sample_ren_s <= '1' & NOT(sample_load) & "111";
490 490 IF sample_empty(3) = '1' THEN
491 491 sample_ren_s <= (OTHERS => '1');
492 492 state_fsm_load_FFT <= FIFO_5;
493 493 END IF;
494 494
495 495 WHEN FIFO_5 =>
496 496 sample_ren_s <= NOT(sample_load) & "1111";
497 497 IF sample_empty(4) = '1' THEN
498 498 sample_ren_s <= (OTHERS => '1');
499 499 state_fsm_load_FFT <= IDLE;
500 500 END IF;
501 501 WHEN OTHERS => NULL;
502 502 END CASE;
503 503 END IF;
504 504 END PROCESS;
505 505
506 506 PROCESS (clk, rstn)
507 507 BEGIN
508 508 IF rstn = '0' THEN
509 509 sample_valid_r <= '0';
510 510 next_state_fsm_load_FFT <= IDLE;
511 511 ELSIF clk'EVENT AND clk = '1' THEN
512 512 next_state_fsm_load_FFT <= state_fsm_load_FFT;
513 513 IF sample_ren_s = "11111" THEN
514 514 sample_valid_r <= '0';
515 515 ELSE
516 516 sample_valid_r <= '1';
517 517 END IF;
518 518 END IF;
519 519 END PROCESS;
520 520
521 521 sample_valid <= sample_valid_r AND sample_load;
522 522
523 523 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
524 524 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
525 525 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
526 526 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
527 527 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
528 528
529 529 -----------------------------------------------------------------------------
530 530 -- FFT
531 531 -----------------------------------------------------------------------------
532 532 CoreFFT_1 : CoreFFT
533 533 GENERIC MAP (
534 534 LOGPTS => gLOGPTS,
535 535 LOGLOGPTS => gLOGLOGPTS,
536 536 WSIZE => gWSIZE,
537 537 TWIDTH => gTWIDTH,
538 538 DWIDTH => gDWIDTH,
539 539 TDWIDTH => gTDWIDTH,
540 540 RND_MODE => gRND_MODE,
541 541 SCALE_MODE => gSCALE_MODE,
542 542 PTS => gPTS,
543 543 HALFPTS => gHALFPTS,
544 544 inBuf_RWDLY => gInBuf_RWDLY)
545 545 PORT MAP (
546 546 clk => clk,
547 547 ifiStart => '1',
548 548 ifiNreset => rstn,
549 549
550 550 ifiD_valid => sample_valid, -- IN
551 551 ifiRead_y => fft_read,
552 552 ifiD_im => (OTHERS => '0'), -- IN
553 553 ifiD_re => sample_data, -- IN
554 554 ifoLoad => sample_load, -- IN
555 555
556 556 ifoPong => fft_pong,
557 557 ifoY_im => fft_data_im,
558 558 ifoY_re => fft_data_re,
559 559 ifoY_valid => fft_data_valid,
560 560 ifoY_rdy => fft_ready);
561 561
562 562 -----------------------------------------------------------------------------
563 563 -- in fft_data_im & fft_data_re
564 564 -- in fft_data_valid
565 565 -- in fft_ready
566 566 -- out fft_read
567 567 PROCESS (clk, rstn)
568 568 BEGIN
569 569 IF rstn = '0' THEN
570 570 state_fsm_load_MS_memory <= IDLE;
571 571 current_fifo_load <= "00001";
572 572 ELSIF clk'event AND clk = '1' THEN
573 573 CASE state_fsm_load_MS_memory IS
574 574 WHEN IDLE =>
575 575 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
576 576 state_fsm_load_MS_memory <= LOAD_FIFO;
577 577 END IF;
578 578 WHEN LOAD_FIFO =>
579 579 IF current_fifo_full = '1' THEN
580 580 state_fsm_load_MS_memory <= TRASH_FFT;
581 581 END IF;
582 582 WHEN TRASH_FFT =>
583 583 IF fft_ready = '0' THEN
584 584 state_fsm_load_MS_memory <= IDLE;
585 585 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
586 586 END IF;
587 587 WHEN OTHERS => NULL;
588 588 END CASE;
589 589
590 590 END IF;
591 591 END PROCESS;
592 592
593 593 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
594 594 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
595 595 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
596 596 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
597 597 MEM_IN_SM_Empty(4);-- WHEN current_fifo_load(3) = '1' ELSE
598 598
599 599 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
600 600 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
601 601 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
602 602 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
603 603 MEM_IN_SM_Full(4);-- WHEN current_fifo_load(3) = '1' ELSE
604 604
605 605 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
606 606 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
607 607 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
608 608 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
609 609 MEM_IN_SM_locked(4);-- WHEN current_fifo_load(3) = '1' ELSE
610 610
611 611 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
612 612
613 613 all_fifo: FOR I IN 4 DOWNTO 0 GENERATE
614 614 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
615 615 AND state_fsm_load_MS_memory = LOAD_FIFO
616 616 AND current_fifo_load(I) = '1'
617 617 ELSE '1';
618 618 END GENERATE all_fifo;
619 619
620 620 PROCESS (clk, rstn)
621 621 BEGIN
622 622 IF rstn = '0' THEN
623 623 MEM_IN_SM_wen <= (OTHERS => '1');
624 624 ELSIF clk'event AND clk = '1' THEN
625 625 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
626 626 END IF;
627 627 END PROCESS;
628 628
629 629 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
630 630 (fft_data_im & fft_data_re) &
631 631 (fft_data_im & fft_data_re) &
632 632 (fft_data_im & fft_data_re) &
633 633 (fft_data_im & fft_data_re);
634 634
635 635
636 636 -- out SM_MEM_IN_wData
637 637 -- out SM_MEM_IN_wen
638 638 -- out SM_MEM_IN_Full
639 639
640 640 -- out SM_MEM_IN_locked
641 641 -----------------------------------------------------------------------------
642 642 -----------------------------------------------------------------------------
643 643 -----------------------------------------------------------------------------
644 644 -----------------------------------------------------------------------------
645 645 --Linker_FFT_1 : Linker_FFT
646 646 -- GENERIC MAP (
647 647 -- Data_sz => 16,
648 648 -- NbData => 256)
649 649 -- PORT MAP (
650 650 -- clk => clk,
651 651 -- rstn => rstn,
652 652
653 653 -- Ready => fft_ready,
654 654 -- Valid => fft_data_valid,
655 655
656 656 -- Full => MEM_IN_SM_Full,
657 657
658 658 -- Data_re => fft_data_re,
659 659 -- Data_im => fft_data_im,
660 660 -- Read => fft_read,
661 661
662 662 -- Write => MEM_IN_SM_wen,
663 663 -- ReUse => fft_linker_ReUse,
664 664 -- DATA => MEM_IN_SM_wData);
665 665
666 666 -----------------------------------------------------------------------------
667 667 Mem_In_SpectralMatrix : lppFIFOxN
668 668 GENERIC MAP (
669 669 tech => 0,
670 670 Mem_use => Mem_use,
671 671 Data_sz => 32, --16,
672 672 Addr_sz => 7, --8
673 673 FifoCnt => 5)
674 674 PORT MAP (
675 675 clk => clk,
676 676 rstn => rstn,
677 677
678 678 ReUse => MEM_IN_SM_ReUse,
679 679
680 680 wen => MEM_IN_SM_wen,
681 681 wdata => MEM_IN_SM_wData,
682 682
683 683 ren => MEM_IN_SM_ren,
684 684 rdata => MEM_IN_SM_rData,
685 685 full => MEM_IN_SM_Full,
686 686 empty => MEM_IN_SM_Empty);
687 687
688 688
689 689 all_lock: FOR I IN 4 DOWNTO 0 GENERATE
690 690 PROCESS (clk, rstn)
691 691 BEGIN
692 692 IF rstn = '0' THEN
693 693 MEM_IN_SM_locked(I) <= '0';
694 694 ELSIF clk'event AND clk = '1' THEN
695 695 MEM_IN_SM_locked(I) <= MEM_IN_SM_Full(I) OR MEM_IN_SM_locked(I); -- TODO
696 696 END IF;
697 697 END PROCESS;
698 698 END GENERATE all_lock;
699 699
700 -----------------------------------------------------------------------------
701
700 702
703
704
701 705
702 706 -----------------------------------------------------------------------------
703 707 SM0 : MatriceSpectrale
704 708 GENERIC MAP (
705 709 Input_SZ => 16,
706 710 Result_SZ => 32)
707 711 PORT MAP (
708 712 clkm => clk,
709 713 rstn => rstn,
710 714
711 715 FifoIN_Full => MEM_IN_SM_Full,
712 716 Data_IN => MEM_IN_SM_rData(79 DOWNTO 0),
713 717 Read => MEM_IN_SM_ren,
714 718 ReUse => MEM_IN_SM_ReUse,
715 719
716 720 SetReUse => fft_linker_ReUse,
717 721
718 722 Valid => HEAD_Valid,
719 723 ACK => DMA_Header_Ack,
720 724 SM_Write => HEAD_SM_Wen,
721 725 FlagError => OPEN,
722 726 Statu => HEAD_SM_Param,
723 727 Write => MEM_OUT_SM_Write,
724 728 Data_OUT => MEM_OUT_SM_Data_in);
725 729 -----------------------------------------------------------------------------
726 730 Mem_Out_SpectralMatrix : lppFIFOxN
727 731 GENERIC MAP (
728 732 tech => 0,
729 733 Mem_use => Mem_use,
730 734 Data_sz => 32,
731 735 Addr_sz => 8,
732 736 FifoCnt => 2)
733 737 PORT MAP (
734 738 clk => clk,
735 739 rstn => rstn,
736 740
737 741 ReUse => (OTHERS => '0'),
738 742
739 743 wen => MEM_OUT_SM_Write,
740 744 wdata => MEM_OUT_SM_Data_in,
741 745 ren => MEM_OUT_SM_Read,
742 746 rdata => MEM_OUT_SM_Data_out,
743 747
744 748 full => MEM_OUT_SM_Full,
745 749 empty => MEM_OUT_SM_Empty);
746 750 -----------------------------------------------------------------------------
747 751 Head0 : HeaderBuilder
748 752 GENERIC MAP (
749 753 Data_sz => 32)
750 754 PORT MAP (
751 755 clkm => clk,
752 756 rstn => rstn,
753 757
754 758 Statu => HEAD_SM_Param,
755 759 Matrix_Type => HEAD_WorkFreq, -- TODO IN
756 760 Matrix_Write => HEAD_SM_Wen,
757 761 Valid => HEAD_Valid,
758 762
759 763 dataIN => MEM_OUT_SM_Data_out,
760 764 emptyIN => MEM_OUT_SM_Empty,
761 765 RenOUT => MEM_OUT_SM_Read,
762 766
763 767 dataOUT => HEAD_Data,
764 768 emptyOUT => HEAD_Empty,
765 769 RenIN => HEAD_Read,
766 770
767 771 header => DMA_Header,
768 772 header_val => DMA_Header_Val,
769 773 header_ack => DMA_Header_Ack);
770 774 -----------------------------------------------------------------------------
771 775 -----------------------------------------------------------------------------
772 776 lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
773 777 PORT MAP (
774 778 HCLK => clk,
775 779 HRESETn => rstn,
776 780
777 781 data_time => dma_time,
778 782
779 783 fifo_data => HEAD_Data,
780 784 fifo_empty => HEAD_Empty,
781 785 fifo_ren => HEAD_Read,
782 786
783 787 header => DMA_Header,
784 788 header_val => DMA_Header_Val,
785 789 header_ack => DMA_Header_Ack,
786 790
787 791 dma_addr => dma_addr,
788 792 dma_data => dma_data,
789 793 dma_valid => dma_valid,
790 794 dma_valid_burst => dma_valid_burst,
791 795 dma_ren => dma_ren,
792 796 dma_done => dma_done,
793 797
794 798 ready_matrix_f0_0 => ready_matrix_f0_0,
795 799 ready_matrix_f0_1 => ready_matrix_f0_1,
796 800 ready_matrix_f1 => ready_matrix_f1,
797 801 ready_matrix_f2 => ready_matrix_f2,
798 802 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
799 803 error_bad_component_error => error_bad_component_error,
800 804 debug_reg => debug_reg,
801 805 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
802 806 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
803 807 status_ready_matrix_f1 => status_ready_matrix_f1,
804 808 status_ready_matrix_f2 => status_ready_matrix_f2,
805 809 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
806 810 status_error_bad_component_error => status_error_bad_component_error,
807 811 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
808 812 config_active_interruption_onError => config_active_interruption_onError,
809 813 addr_matrix_f0_0 => addr_matrix_f0_0,
810 814 addr_matrix_f0_1 => addr_matrix_f0_1,
811 815 addr_matrix_f1 => addr_matrix_f1,
812 816 addr_matrix_f2 => addr_matrix_f2,
813 817
814 818 matrix_time_f0_0 => matrix_time_f0_0,
815 819 matrix_time_f0_1 => matrix_time_f0_1,
816 820 matrix_time_f1 => matrix_time_f1,
817 821 matrix_time_f2 => matrix_time_f2
818 822 );
819 823 -----------------------------------------------------------------------------
820 824
821 825 -----------------------------------------------------------------------------
822 826 -----------------------------------------------------------------------------
823 827 -----------------------------------------------------------------------------
824 828 -----------------------------------------------------------------------------
825 829 -----------------------------------------------------------------------------
826 830 -----------------------------------------------------------------------------
827 831
828 832
829 833
830 834
831 835
832 836
833 837 -----------------------------------------------------------------------------
834 838 -- TIME MANAGMENT
835 839 -----------------------------------------------------------------------------
836 840 all_time <= coarse_time & fine_time;
837 841 --
838 842 time_update_f0_A <= '0' WHEN sample_f0_A_wen = "11111" ELSE
839 843 '1' WHEN sample_f0_A_empty = "11111" ELSE
840 844 '0';
841 845
842 846 s_m_t_m_f0_A : spectral_matrix_time_managment
843 847 PORT MAP (
844 848 clk => clk,
845 849 rstn => rstn,
846 850 time_in => all_time,
847 851 update_1 => time_update_f0_A,
848 852 time_out => time_reg_f0_A);
849 853
850 854 --
851 855 time_update_f0_B <= '0' WHEN sample_f0_B_wen = "11111" ELSE
852 856 '1' WHEN sample_f0_B_empty = "11111" ELSE
853 857 '0';
854 858
855 859 s_m_t_m_f0_B : spectral_matrix_time_managment
856 860 PORT MAP (
857 861 clk => clk,
858 862 rstn => rstn,
859 863 time_in => all_time,
860 864 update_1 => time_update_f0_B,
861 865 time_out => time_reg_f0_B);
862 866
863 867 --
864 868 time_update_f1 <= '0' WHEN sample_f1_wen = "11111" ELSE
865 869 '1' WHEN sample_f1_empty = "11111" ELSE
866 870 '0';
867 871
868 872 s_m_t_m_f1 : spectral_matrix_time_managment
869 873 PORT MAP (
870 874 clk => clk,
871 875 rstn => rstn,
872 876 time_in => all_time,
873 877 update_1 => time_update_f1,
874 878 time_out => time_reg_f1);
875 879
876 880 --
877 881 time_update_f2 <= '0' WHEN sample_f2_wen = "11111" ELSE
878 882 '1' WHEN sample_f2_empty = "11111" ELSE
879 883 '0';
880 884
881 885 s_m_t_m_f2 : spectral_matrix_time_managment
882 886 PORT MAP (
883 887 clk => clk,
884 888 rstn => rstn,
885 889 time_in => all_time,
886 890 update_1 => time_update_f2,
887 891 time_out => time_reg_f2);
888 892
889 893 -----------------------------------------------------------------------------
890 894 dma_time <= (OTHERS => '0'); -- TODO
891 895 -----------------------------------------------------------------------------
892 896
893 897
894 898
895 899 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,220 +1,220
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE std.textio.ALL;
28 28 LIBRARY grlib;
29 29 USE grlib.amba.ALL;
30 30 USE grlib.stdlib.ALL;
31 31 USE GRLIB.DMA2AHB_Package.ALL;
32 32 LIBRARY techmap;
33 33 USE techmap.gencomp.ALL;
34 LIBRARY lpp;
35 USE lpp.lpp_amba.ALL;
36 USE lpp.apb_devices_list.ALL;
37 USE lpp.lpp_memory.ALL;
34 --LIBRARY lpp;
35 --USE lpp.lpp_amba.ALL;
36 --USE lpp.apb_devices_list.ALL;
37 --USE lpp.lpp_memory.ALL;
38 38
39 39 PACKAGE lpp_dma_pkg IS
40 40
41 41 COMPONENT lpp_dma
42 42 GENERIC (
43 43 tech : INTEGER;
44 44 hindex : INTEGER;
45 45 pindex : INTEGER;
46 46 paddr : INTEGER;
47 47 pmask : INTEGER;
48 48 pirq : INTEGER);
49 49 PORT (
50 50 HCLK : IN STD_ULOGIC;
51 51 HRESETn : IN STD_ULOGIC;
52 52 apbi : IN apb_slv_in_type;
53 53 apbo : OUT apb_slv_out_type;
54 54 AHB_Master_In : IN AHB_Mst_In_Type;
55 55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
56 56 -- fifo interface
57 57 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 58 fifo_empty : IN STD_LOGIC;
59 59 fifo_ren : OUT STD_LOGIC;
60 60 -- header
61 61 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 62 header_val : IN STD_LOGIC;
63 63 header_ack : OUT STD_LOGIC);
64 64 END COMPONENT;
65 65
66 66 COMPONENT fifo_test_dma
67 67 GENERIC (
68 68 tech : INTEGER;
69 69 pindex : INTEGER;
70 70 paddr : INTEGER;
71 71 pmask : INTEGER);
72 72 PORT (
73 73 HCLK : IN STD_ULOGIC;
74 74 HRESETn : IN STD_ULOGIC;
75 75 apbi : IN apb_slv_in_type;
76 76 apbo : OUT apb_slv_out_type;
77 77 -- fifo interface
78 78 fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 79 fifo_empty : OUT STD_LOGIC;
80 80 fifo_ren : IN STD_LOGIC;
81 81 -- header
82 82 header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 83 header_val : OUT STD_LOGIC;
84 84 header_ack : IN STD_LOGIC
85 85 );
86 86 END COMPONENT;
87 87
88 88 COMPONENT lpp_dma_apbreg
89 89 GENERIC (
90 90 pindex : INTEGER;
91 91 paddr : INTEGER;
92 92 pmask : INTEGER;
93 93 pirq : INTEGER);
94 94 PORT (
95 95 HCLK : IN STD_ULOGIC;
96 96 HRESETn : IN STD_ULOGIC;
97 97 apbi : IN apb_slv_in_type;
98 98 apbo : OUT apb_slv_out_type;
99 99 -- IN
100 100 ready_matrix_f0_0 : IN STD_LOGIC;
101 101 ready_matrix_f0_1 : IN STD_LOGIC;
102 102 ready_matrix_f1 : IN STD_LOGIC;
103 103 ready_matrix_f2 : IN STD_LOGIC;
104 104 error_anticipating_empty_fifo : IN STD_LOGIC;
105 105 error_bad_component_error : IN STD_LOGIC;
106 106 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
107 107
108 108 -- OUT
109 109 status_ready_matrix_f0_0 : OUT STD_LOGIC;
110 110 status_ready_matrix_f0_1 : OUT STD_LOGIC;
111 111 status_ready_matrix_f1 : OUT STD_LOGIC;
112 112 status_ready_matrix_f2 : OUT STD_LOGIC;
113 113 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
114 114 status_error_bad_component_error : OUT STD_LOGIC;
115 115
116 116 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
117 117 config_active_interruption_onError : OUT STD_LOGIC;
118 118 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 119 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 120 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
122 122 );
123 123 END COMPONENT;
124 124
125 125 COMPONENT lpp_dma_send_1word
126 126 PORT (
127 127 HCLK : IN STD_ULOGIC;
128 128 HRESETn : IN STD_ULOGIC;
129 129 DMAIn : OUT DMA_In_Type;
130 130 DMAOut : IN DMA_OUt_Type;
131 131 send : IN STD_LOGIC;
132 132 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 133 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
134 134 ren : OUT STD_LOGIC;
135 135 send_ok : OUT STD_LOGIC;
136 136 send_ko : OUT STD_LOGIC);
137 137 END COMPONENT;
138 138
139 139 COMPONENT lpp_dma_send_16word
140 140 PORT (
141 141 HCLK : IN STD_ULOGIC;
142 142 HRESETn : IN STD_ULOGIC;
143 143 DMAIn : OUT DMA_In_Type;
144 144 DMAOut : IN DMA_OUt_Type;
145 145 send : IN STD_LOGIC;
146 146 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
147 147 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
148 148 ren : OUT STD_LOGIC;
149 149 send_ok : OUT STD_LOGIC;
150 150 send_ko : OUT STD_LOGIC);
151 151 END COMPONENT;
152 152
153 153 COMPONENT fifo_latency_correction
154 154 PORT (
155 155 HCLK : IN STD_ULOGIC;
156 156 HRESETn : IN STD_ULOGIC;
157 157 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
158 158 fifo_empty : IN STD_LOGIC;
159 159 fifo_ren : OUT STD_LOGIC;
160 160 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
161 161 dma_empty : OUT STD_LOGIC;
162 162 dma_ren : IN STD_LOGIC);
163 163 END COMPONENT;
164 164
165 165 COMPONENT lpp_dma_ip
166 166 GENERIC (
167 167 tech : INTEGER;
168 168 hindex : INTEGER);
169 169 PORT (
170 170 HCLK : IN STD_ULOGIC;
171 171 HRESETn : IN STD_ULOGIC;
172 172 AHB_Master_In : IN AHB_Mst_In_Type;
173 173 AHB_Master_Out : OUT AHB_Mst_Out_Type;
174 174 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175 fifo_empty : IN STD_LOGIC;
176 176 fifo_ren : OUT STD_LOGIC;
177 177 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
178 178 header_val : IN STD_LOGIC;
179 179 header_ack : OUT STD_LOGIC;
180 180 ready_matrix_f0_0 : OUT STD_LOGIC;
181 181 ready_matrix_f0_1 : OUT STD_LOGIC;
182 182 ready_matrix_f1 : OUT STD_LOGIC;
183 183 ready_matrix_f2 : OUT STD_LOGIC;
184 184 error_anticipating_empty_fifo : OUT STD_LOGIC;
185 185 error_bad_component_error : OUT STD_LOGIC;
186 186 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
187 187 status_ready_matrix_f0_0 : IN STD_LOGIC;
188 188 status_ready_matrix_f0_1 : IN STD_LOGIC;
189 189 status_ready_matrix_f1 : IN STD_LOGIC;
190 190 status_ready_matrix_f2 : IN STD_LOGIC;
191 191 status_error_anticipating_empty_fifo : IN STD_LOGIC;
192 192 status_error_bad_component_error : IN STD_LOGIC;
193 193 config_active_interruption_onNewMatrix : IN STD_LOGIC;
194 194 config_active_interruption_onError : IN STD_LOGIC;
195 195 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
196 196 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
197 197 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
198 198 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
199 199 END COMPONENT;
200 200
201 201 COMPONENT lpp_dma_singleOrBurst
202 202 GENERIC (
203 203 tech : INTEGER;
204 204 hindex : INTEGER);
205 205 PORT (
206 206 HCLK : IN STD_ULOGIC;
207 207 HRESETn : IN STD_ULOGIC;
208 208 run : IN STD_LOGIC;
209 209 AHB_Master_In : IN AHB_Mst_In_Type;
210 210 AHB_Master_Out : OUT AHB_Mst_Out_Type;
211 211 send : IN STD_LOGIC;
212 212 valid_burst : IN STD_LOGIC;
213 213 done : OUT STD_LOGIC;
214 214 ren : OUT STD_LOGIC;
215 215 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
216 216 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
217 217 debug_dmaout_okay : OUT STD_LOGIC);
218 218 END COMPONENT;
219 219
220 220 END;
General Comments 0
You need to be logged in to leave comments. Login now