@@ -0,0 +1,129 | |||||
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1 | LIBRARY IEEE; | |||
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2 | USE IEEE.std_logic_1164.ALL; | |||
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3 | USE IEEE.numeric_std.ALL; | |||
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4 | ||||
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5 | ENTITY MS_control IS | |||
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6 | PORT ( | |||
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7 | clk : IN STD_LOGIC; | |||
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8 | rstn : IN STD_LOGIC; | |||
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9 | ||||
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10 | -- IN | |||
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11 | fifo_in_lock : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
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12 | fifo_in_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); | |||
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13 | fifo_in_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
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14 | fifo_in_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
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15 | fifo_in_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
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16 | fifo_in_reuse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
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17 | -- OUT | |||
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18 | fifo_out_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); | |||
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19 | fifo_out_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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20 | fifo_out_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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21 | -- OUT | |||
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22 | correlation_start : OUT STD_LOGIC; | |||
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23 | correlation_auto : OUT STD_LOGIC; -- 1 => auto correlation / 0 => inter correlation | |||
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24 | correlation_done : IN STD_LOGIC | |||
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25 | ); | |||
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26 | END MS_control; | |||
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27 | ||||
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28 | ARCHITECTURE beh OF MS_control IS | |||
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29 | ||||
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30 | TYPE fsm_control_MS IS (WAIT_DATA, CORRELATION_ONGOING); | |||
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31 | SIGNAL state : fsm_control_MS; | |||
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32 | ||||
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33 | SUBTYPE fifo_pointer IS RANGE 0 TO 4; | |||
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34 | SIGNAL fifo_1 : fifo_pointer; | |||
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35 | SIGNAL fifo_2 : fifo_pointer; | |||
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36 | ||||
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37 | SIGNAL fifo_in_lock_s : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
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38 | SIGNAL fifo_in_reuse_s : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
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39 | ||||
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40 | BEGIN -- beh | |||
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41 | ||||
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42 | fifo_in_lock <= fifo_in_lock_s; | |||
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43 | fifo_in_reuse <= fifo_in_reuse_s; | |||
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44 | ||||
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45 | PROCESS (clk, rstn) | |||
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46 | BEGIN | |||
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47 | IF rstn = '0' THEN | |||
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48 | state <= WAIT_DATA; | |||
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49 | fifo_1 <= 0; | |||
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50 | fifo_2 <= 0; | |||
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51 | fifo_in_lock_s <= (OTHERS => '0'); | |||
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52 | fifo_in_reuse_s <= (OTHERS => '0'); | |||
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53 | correlation_start <= '0'; | |||
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54 | correlation_auto <= '0'; | |||
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55 | ELSIF clk'event AND clk = '1' THEN | |||
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56 | CASE state IS | |||
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57 | WHEN WAIT_DATA => | |||
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58 | fifo_in_reuse_s <= (OTHERS => '0'); | |||
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59 | IF fifo_in_full[fifo_1] = '1' AND fifo_in_full[fifo_2] = '1' THEN | |||
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60 | fifo_in_lock_s(fifo_1) <= '1'; | |||
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61 | fifo_in_lock_s(fifo_2) <= '1'; | |||
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62 | correlation_start <= '1'; | |||
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63 | IF fifo_1 = fifo_2 THEN | |||
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64 | correlation_auto <= '1'; | |||
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65 | END IF; | |||
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66 | state <= CORRELATION_ONGOING; | |||
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67 | END IF; | |||
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68 | ||||
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69 | WHEN CORRELATION_ONGOING => | |||
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70 | correlation_start <= '0'; | |||
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71 | correlation_auto <= '0'; | |||
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72 | IF correlation_done = '1' THEN | |||
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73 | state <= WAIT_DATA; | |||
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74 | IF fifo_2 = 4 THEN | |||
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75 | fifo_in_lock_s(fifo_1) <= '0'; | |||
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76 | IF fifo_1 = 4 THEN | |||
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77 | fifo_1 <= 0; | |||
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78 | fifo_2 <= 0; | |||
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79 | ELSE | |||
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80 | fifo_in_reuse_s(fifo_2) <= '1'; | |||
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81 | fifo_1 <= fifo_1 + 1; | |||
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82 | fifo_2 <= fifo_1 + 1; | |||
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83 | END IF; | |||
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84 | ELSE | |||
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85 | fifo_in_reuse_s(fifo_2) <= '1'; | |||
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86 | fifo_in_reuse_s(fifo_1) <= '1'; | |||
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87 | fifo_2 <= fifo_2 + 1; | |||
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88 | END IF; | |||
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89 | END IF; | |||
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90 | ||||
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91 | WHEN OTHERS => NULL; | |||
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92 | END CASE; | |||
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93 | END IF; | |||
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94 | END PROCESS; | |||
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95 | ||||
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96 | ||||
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97 | fifo_out_data(31 DOWNTO 0) <= fifo_in_data(31*1-1 DOWNTO 32*0) WHEN fifo_1 = 0 ELSE | |||
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98 | fifo_in_data(32*2-1 DOWNTO 32*1) WHEN fifo_1 = 1 ELSE | |||
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99 | fifo_in_data(32*3-1 DOWNTO 32*2) WHEN fifo_1 = 2 ELSE | |||
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100 | fifo_in_data(32*4-1 DOWNTO 32*3) WHEN fifo_1 = 3 ELSE | |||
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101 | fifo_in_data(32*5-1 DOWNTO 32*4);-- WHEN fifo_1 = 4 | |||
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102 | ||||
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103 | ||||
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104 | fifo_out_data(63 DOWNTO 32) <= fifo_in_data(31*1-1 DOWNTO 32*0) WHEN fifo_2 = 0 ELSE | |||
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105 | fifo_in_data(32*2-1 DOWNTO 32*1) WHEN fifo_2 = 1 ELSE | |||
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106 | fifo_in_data(32*3-1 DOWNTO 32*2) WHEN fifo_2 = 2 ELSE | |||
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107 | fifo_in_data(32*4-1 DOWNTO 32*3) WHEN fifo_2 = 3 ELSE | |||
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108 | fifo_in_data(32*5-1 DOWNTO 32*4);-- WHEN fifo_2 = 4 | |||
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109 | ||||
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110 | fifo_out_empty(0) <= fifo_in_empty(0) WHEN fifo_1 = 0 ELSE | |||
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111 | fifo_in_empty(1) WHEN fifo_1 = 1 ELSE | |||
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112 | fifo_in_empty(2) WHEN fifo_1 = 2 ELSE | |||
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113 | fifo_in_empty(3) WHEN fifo_1 = 3 ELSE | |||
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114 | fifo_in_empty(4); | |||
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115 | ||||
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116 | fifo_out_empty(1) <= fifo_in_empty(0) WHEN fifo_2 = 0 ELSE | |||
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117 | fifo_in_empty(1) WHEN fifo_2 = 1 ELSE | |||
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118 | fifo_in_empty(2) WHEN fifo_2 = 2 ELSE | |||
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119 | fifo_in_empty(3) WHEN fifo_2 = 3 ELSE | |||
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120 | fifo_in_empty(4); | |||
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121 | ||||
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122 | ||||
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123 | all_fifo: FOR I IN 0 TO 4 GENERATE | |||
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124 | fifo_in_ren(I) <= fifo_out_ren(I) WHEN fifo_1 = I ELSE | |||
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125 | fifo_out_ren(I) WHEN fifo_2 = I ELSE | |||
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126 | '1'; | |||
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127 | END GENERATE all_fifo; | |||
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128 | ||||
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129 | END beh; |
@@ -1,429 +1,430 | |||||
1 | VHDLIB=../.. |
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1 | VHDLIB=../.. | |
2 | SCRIPTSDIR=$(VHDLIB)/scripts/ |
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2 | SCRIPTSDIR=$(VHDLIB)/scripts/ | |
3 |
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3 | |||
4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) |
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4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) | |
5 | TOP=TB |
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5 | TOP=TB | |
6 |
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6 | |||
7 | CMD_VLIB=vlib |
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7 | CMD_VLIB=vlib | |
8 | CMD_VMAP=vmap |
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8 | CMD_VMAP=vmap | |
9 | CMD_VCOM=@vcom -quiet -93 -work |
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9 | CMD_VCOM=@vcom -quiet -93 -work | |
10 |
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10 | |||
11 | ################## project specific targets ########################## |
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11 | ################## project specific targets ########################## | |
12 |
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12 | |||
13 | all: |
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13 | all: | |
14 | @echo "make vsim" |
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14 | @echo "make vsim" | |
15 | @echo "make libs" |
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15 | @echo "make libs" | |
16 | @echo "make clean" |
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16 | @echo "make clean" | |
17 | @echo "make vcom_grlib vcom_lpp vcom_tb" |
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17 | @echo "make vcom_grlib vcom_lpp vcom_tb" | |
18 |
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18 | |||
19 | run: |
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19 | run: | |
20 | @vsim work.TB -do run.do |
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20 | @vsim work.TB -do run.do | |
21 | # @vsim work.TB |
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21 | # @vsim work.TB | |
22 | # @vsim lpp.lpp_lfr_ms |
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22 | # @vsim lpp.lpp_lfr_ms | |
23 |
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23 | |||
24 | vsim: libs vcom run |
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24 | vsim: libs vcom run | |
25 |
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25 | |||
26 | libs: |
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26 | libs: | |
27 | @$(CMD_VLIB) modelsim |
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27 | @$(CMD_VLIB) modelsim | |
28 | @$(CMD_VMAP) modelsim modelsim |
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28 | @$(CMD_VMAP) modelsim modelsim | |
29 | @$(CMD_VLIB) modelsim/techmap |
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29 | @$(CMD_VLIB) modelsim/techmap | |
30 | @$(CMD_VMAP) techmap modelsim/techmap |
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30 | @$(CMD_VMAP) techmap modelsim/techmap | |
31 | @$(CMD_VLIB) modelsim/grlib |
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31 | @$(CMD_VLIB) modelsim/grlib | |
32 | @$(CMD_VMAP) grlib modelsim/grlib |
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32 | @$(CMD_VMAP) grlib modelsim/grlib | |
33 | @$(CMD_VLIB) modelsim/gaisler |
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33 | @$(CMD_VLIB) modelsim/gaisler | |
34 | @$(CMD_VMAP) gaisler modelsim/gaisler |
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34 | @$(CMD_VMAP) gaisler modelsim/gaisler | |
35 | @$(CMD_VLIB) modelsim/work |
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35 | @$(CMD_VLIB) modelsim/work | |
36 | @$(CMD_VMAP) work modelsim/work |
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36 | @$(CMD_VMAP) work modelsim/work | |
37 | @$(CMD_VLIB) modelsim/lpp |
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37 | @$(CMD_VLIB) modelsim/lpp | |
38 | @$(CMD_VMAP) lpp modelsim/lpp |
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38 | @$(CMD_VMAP) lpp modelsim/lpp | |
39 | @echo "libs done" |
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39 | @echo "libs done" | |
40 |
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40 | |||
41 |
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41 | |||
42 | clean: |
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42 | clean: | |
43 | @rm -Rf modelsim |
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43 | @rm -Rf modelsim | |
44 | @rm -Rf modelsim.ini |
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44 | @rm -Rf modelsim.ini | |
45 | @rm -Rf *~ |
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45 | @rm -Rf *~ | |
46 | @rm -Rf transcript |
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46 | @rm -Rf transcript | |
47 | @rm -Rf wlft* |
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47 | @rm -Rf wlft* | |
48 | @rm -Rf *.wlf |
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48 | @rm -Rf *.wlf | |
49 | @rm -Rf vish_stacktrace.vstf |
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49 | @rm -Rf vish_stacktrace.vstf | |
50 | @rm -Rf libs.do |
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50 | @rm -Rf libs.do | |
51 |
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51 | |||
52 | vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_tb |
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52 | vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_tb | |
53 |
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53 | |||
54 |
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54 | |||
55 | vcom_tb: |
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55 | vcom_tb: | |
56 | $(CMD_VCOM) lpp lpp_memory.vhd |
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56 | $(CMD_VCOM) lpp lpp_memory.vhd | |
57 | $(CMD_VCOM) lpp lppFIFOxN.vhd |
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57 | $(CMD_VCOM) lpp lppFIFOxN.vhd | |
58 | $(CMD_VCOM) lpp lpp_FIFO.vhd |
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58 | $(CMD_VCOM) lpp lpp_FIFO.vhd | |
59 | $(CMD_VCOM) lpp spectral_matrix_package.vhd |
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59 | $(CMD_VCOM) lpp spectral_matrix_package.vhd | |
60 | $(CMD_VCOM) lpp spectral_matrix_switch_f0.vhd |
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60 | $(CMD_VCOM) lpp spectral_matrix_switch_f0.vhd | |
61 | $(CMD_VCOM) lpp spectral_matrix_time_managment.vhd |
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61 | $(CMD_VCOM) lpp spectral_matrix_time_managment.vhd | |
62 | $(CMD_VCOM) lpp lpp_lfr_ms.vhd |
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62 | $(CMD_VCOM) lpp lpp_lfr_ms.vhd | |
63 | $(CMD_VCOM) work TB.vhd |
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63 | $(CMD_VCOM) work TB.vhd | |
64 | @echo "vcom done" |
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64 | @echo "vcom done" | |
65 |
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65 | |||
66 | vcom_grlib: |
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66 | vcom_grlib: | |
67 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd |
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67 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd | |
68 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd |
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68 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd | |
69 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd |
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69 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd | |
70 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd |
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70 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd | |
71 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd |
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71 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd | |
72 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd |
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72 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd | |
73 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd |
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73 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd | |
74 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd |
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74 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd | |
75 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd |
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75 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd | |
76 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd |
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76 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd | |
77 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd |
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77 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd | |
78 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd |
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78 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd | |
79 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd |
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79 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd | |
80 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd |
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80 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd | |
81 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd |
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81 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd | |
82 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd |
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82 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd | |
83 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd |
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83 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd | |
84 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd |
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84 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd | |
85 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd |
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85 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd | |
86 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd |
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86 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd | |
87 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd |
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87 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd | |
88 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd |
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88 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd | |
89 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd |
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89 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd | |
90 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd |
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90 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd | |
91 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd |
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91 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd | |
92 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd |
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92 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd | |
93 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd |
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93 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd | |
94 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd |
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94 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd | |
95 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd |
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95 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd | |
96 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd |
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96 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd | |
97 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd |
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97 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd | |
98 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd |
|
98 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd | |
99 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd |
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99 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd | |
100 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd |
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100 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd | |
101 | @echo "vcom grlib done" |
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101 | @echo "vcom grlib done" | |
102 |
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102 | |||
103 | vcom_gaisler: |
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103 | vcom_gaisler: | |
104 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd |
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104 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd | |
105 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd |
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105 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd | |
106 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd |
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106 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd | |
107 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd |
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107 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd | |
108 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd |
|
108 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd | |
109 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd |
|
109 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd | |
110 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd |
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110 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd | |
111 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd |
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111 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd | |
112 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd |
|
112 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd | |
113 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd |
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113 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd | |
114 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd |
|
114 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd | |
115 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd |
|
115 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd | |
116 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd |
|
116 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd | |
117 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd |
|
117 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd | |
118 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd |
|
118 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd | |
119 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd |
|
119 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd | |
120 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd |
|
120 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd | |
121 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd |
|
121 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd | |
122 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd |
|
122 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd | |
123 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd |
|
123 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd | |
124 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd |
|
124 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd | |
125 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd |
|
125 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd | |
126 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd |
|
126 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd | |
127 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd |
|
127 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd | |
128 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd |
|
128 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd | |
129 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd |
|
129 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd | |
130 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd |
|
130 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd | |
131 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd |
|
131 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd | |
132 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd |
|
132 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd | |
133 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd |
|
133 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd | |
134 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd |
|
134 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd | |
135 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd |
|
135 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd | |
136 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd |
|
136 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd | |
137 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd |
|
137 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd | |
138 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd |
|
138 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd | |
139 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd |
|
139 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd | |
140 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd |
|
140 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd | |
141 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd |
|
141 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd | |
142 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd |
|
142 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd | |
143 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd |
|
143 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd | |
144 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd |
|
144 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd | |
145 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd |
|
145 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd | |
146 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd |
|
146 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd | |
147 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd |
|
147 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd | |
148 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd |
|
148 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd | |
149 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd |
|
149 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd | |
150 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd |
|
150 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd | |
151 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd |
|
151 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd | |
152 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd |
|
152 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd | |
153 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd |
|
153 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd | |
154 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd |
|
154 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd | |
155 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd |
|
155 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd | |
156 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd |
|
156 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd | |
157 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd |
|
157 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd | |
158 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd |
|
158 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd | |
159 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd |
|
159 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd | |
160 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd |
|
160 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd | |
161 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd |
|
161 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd | |
162 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd |
|
162 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd | |
163 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd |
|
163 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd | |
164 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd |
|
164 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd | |
165 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd |
|
165 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd | |
166 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd |
|
166 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd | |
167 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd |
|
167 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd | |
168 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd |
|
168 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd | |
169 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd |
|
169 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd | |
170 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd |
|
170 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd | |
171 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd |
|
171 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd | |
172 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd |
|
172 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd | |
173 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd |
|
173 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd | |
174 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd |
|
174 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd | |
175 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd |
|
175 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd | |
176 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd |
|
176 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd | |
177 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd |
|
177 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd | |
178 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd |
|
178 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd | |
179 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd |
|
179 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd | |
180 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd |
|
180 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd | |
181 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd |
|
181 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd | |
182 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd |
|
182 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd | |
183 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd |
|
183 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd | |
184 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd |
|
184 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd | |
185 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd |
|
185 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd | |
186 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd |
|
186 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd | |
187 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd |
|
187 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd | |
188 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd |
|
188 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd | |
189 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd |
|
189 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd | |
190 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd |
|
190 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd | |
191 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd |
|
191 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd | |
192 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd |
|
192 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd | |
193 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd |
|
193 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd | |
194 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd |
|
194 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd | |
195 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd |
|
195 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd | |
196 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd |
|
196 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd | |
197 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd |
|
197 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd | |
198 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd |
|
198 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd | |
199 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd |
|
199 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd | |
200 | ## $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd |
|
200 | ## $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd | |
201 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd |
|
201 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd | |
202 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd |
|
202 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd | |
203 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd |
|
203 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd | |
204 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd |
|
204 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd | |
205 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd |
|
205 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd | |
206 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd |
|
206 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd | |
207 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd |
|
207 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd | |
208 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd |
|
208 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd | |
209 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd |
|
209 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd | |
210 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd |
|
210 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd | |
211 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd |
|
211 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd | |
212 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd |
|
212 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd | |
213 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd |
|
213 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd | |
214 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd |
|
214 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd | |
215 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd |
|
215 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd | |
216 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd |
|
216 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd | |
217 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd |
|
217 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd | |
218 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd |
|
218 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd | |
219 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd |
|
219 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd | |
220 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd |
|
220 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd | |
221 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd |
|
221 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd | |
222 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd |
|
222 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd | |
223 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd |
|
223 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd | |
224 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd |
|
224 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd | |
225 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd |
|
225 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd | |
226 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd |
|
226 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd | |
227 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd |
|
227 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd | |
228 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd |
|
228 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd | |
229 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd |
|
229 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd | |
230 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd |
|
230 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd | |
231 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd |
|
231 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd | |
232 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd |
|
232 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd | |
233 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd |
|
233 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd | |
234 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd |
|
234 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd | |
235 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd |
|
235 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd | |
236 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd |
|
236 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd | |
237 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd |
|
237 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd | |
238 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd |
|
238 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd | |
239 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd |
|
239 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd | |
240 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd |
|
240 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd | |
241 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd |
|
241 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd | |
242 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd |
|
242 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd | |
243 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd |
|
243 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd | |
244 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd |
|
244 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd | |
245 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd |
|
245 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd | |
246 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd |
|
246 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd | |
247 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd |
|
247 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd | |
248 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd |
|
248 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd | |
249 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd |
|
249 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd | |
250 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd |
|
250 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd | |
251 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd |
|
251 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd | |
252 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd |
|
252 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd | |
253 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd |
|
253 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd | |
254 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd |
|
254 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd | |
255 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd |
|
255 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd | |
256 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd |
|
256 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd | |
257 | @echo "vcom gaisler done" |
|
257 | @echo "vcom gaisler done" | |
258 |
|
258 | |||
259 | vcom_techmap: |
|
259 | vcom_techmap: | |
260 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd |
|
260 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd | |
261 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd |
|
261 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd | |
262 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd |
|
262 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd | |
263 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd |
|
263 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd | |
264 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd |
|
264 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd | |
265 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd |
|
265 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd | |
266 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd |
|
266 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd | |
267 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd |
|
267 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd | |
268 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd |
|
268 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd | |
269 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd |
|
269 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd | |
270 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd |
|
270 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd | |
271 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd |
|
271 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd | |
272 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd |
|
272 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd | |
273 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd |
|
273 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd | |
274 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd |
|
274 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd | |
275 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd |
|
275 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd | |
276 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd |
|
276 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd | |
277 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd |
|
277 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd | |
278 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd |
|
278 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd | |
279 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd |
|
279 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd | |
280 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd |
|
280 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd | |
281 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd |
|
281 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd | |
282 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd |
|
282 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd | |
283 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd |
|
283 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd | |
284 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd |
|
284 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd | |
285 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd |
|
285 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd | |
286 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd |
|
286 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd | |
287 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd |
|
287 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd | |
288 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd |
|
288 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd | |
289 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd |
|
289 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd | |
290 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd |
|
290 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd | |
291 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd |
|
291 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd | |
292 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd |
|
292 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd | |
293 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd |
|
293 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd | |
294 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd |
|
294 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd | |
295 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd |
|
295 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd | |
296 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd |
|
296 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd | |
297 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd |
|
297 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd | |
298 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd |
|
298 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd | |
299 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd |
|
299 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd | |
300 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd |
|
300 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd | |
301 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd |
|
301 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd | |
302 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd |
|
302 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd | |
303 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd |
|
303 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd | |
304 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd |
|
304 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd | |
305 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd |
|
305 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd | |
306 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd |
|
306 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd | |
307 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd |
|
307 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd | |
308 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd |
|
308 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd | |
309 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd |
|
309 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd | |
310 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd |
|
310 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd | |
311 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd |
|
311 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd | |
312 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd |
|
312 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd | |
313 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd |
|
313 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd | |
314 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd |
|
314 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd | |
315 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd |
|
315 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd | |
316 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd |
|
316 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd | |
317 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd |
|
317 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd | |
318 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd |
|
318 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd | |
319 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd |
|
319 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd | |
320 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd |
|
320 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd | |
321 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd |
|
321 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd | |
322 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd |
|
322 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd | |
323 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd |
|
323 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd | |
324 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd |
|
324 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd | |
325 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd |
|
325 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd | |
326 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd |
|
326 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd | |
327 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd |
|
327 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd | |
328 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd |
|
328 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd | |
329 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd |
|
329 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd | |
330 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd |
|
330 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd | |
331 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd |
|
331 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd | |
332 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd |
|
332 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd | |
333 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd |
|
333 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd | |
334 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd |
|
334 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd | |
335 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd |
|
335 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd | |
336 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd |
|
336 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd | |
337 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd |
|
337 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd | |
338 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd |
|
338 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd | |
339 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd |
|
339 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd | |
340 | @echo "vcom techmap done" |
|
340 | @echo "vcom techmap done" | |
341 |
|
341 | |||
342 | vcom_lpp: |
|
342 | vcom_lpp: | |
343 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd |
|
343 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd | |
344 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd |
|
344 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd | |
345 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd |
|
345 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd | |
346 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd |
|
346 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd | |
347 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd |
|
347 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd | |
348 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd |
|
348 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd | |
349 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd |
|
349 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd | |
350 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd |
|
350 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd | |
351 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd |
|
351 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd | |
352 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd |
|
352 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd | |
353 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd |
|
353 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd | |
354 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd |
|
354 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd | |
355 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd |
|
355 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd | |
356 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd |
|
356 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd | |
357 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd |
|
357 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd | |
358 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd |
|
358 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd | |
359 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd |
|
359 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd | |
360 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd |
|
360 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd | |
361 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd |
|
361 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd | |
362 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd |
|
362 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd | |
363 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd |
|
363 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd | |
364 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd |
|
364 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd | |
365 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd |
|
365 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd | |
366 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd |
|
366 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd | |
367 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd |
|
367 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd | |
368 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd |
|
368 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd | |
369 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd |
|
369 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd | |
370 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd |
|
370 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd | |
371 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd |
|
371 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd | |
372 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd |
|
372 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd | |
373 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd |
|
373 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd | |
374 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd |
|
374 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd | |
375 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd |
|
375 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd | |
376 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd |
|
376 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd | |
377 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd |
|
377 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd | |
378 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd |
|
378 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd | |
379 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd |
|
379 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd | |
380 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd |
|
380 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd | |
381 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd |
|
381 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd | |
382 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd |
|
382 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd | |
383 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd |
|
383 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd | |
384 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd |
|
384 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd | |
385 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd |
|
385 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd | |
386 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd |
|
386 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd | |
387 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd |
|
387 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd | |
388 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd |
|
388 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd | |
389 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd |
|
389 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd | |
390 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd |
|
390 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd | |
|
391 | $(CMD_VCOM) lpp lpp_memory.vhd | |||
391 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd |
|
392 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd | |
392 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd |
|
393 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd | |
393 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd |
|
394 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd | |
394 | @echo "vcom lpp done" |
|
395 | @echo "vcom lpp done" | |
395 |
|
396 | |||
396 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd |
|
397 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd | |
397 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd |
|
398 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd | |
398 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd |
|
399 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd | |
399 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd |
|
400 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd | |
400 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd |
|
401 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd | |
401 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd |
|
402 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd | |
402 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd |
|
403 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd | |
403 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd |
|
404 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd | |
404 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd |
|
405 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd | |
405 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd |
|
406 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd | |
406 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd |
|
407 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd | |
407 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd |
|
408 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd | |
408 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd |
|
409 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd | |
409 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd |
|
410 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd | |
410 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd |
|
411 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd | |
411 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd |
|
412 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd | |
412 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd |
|
413 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd | |
413 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd |
|
414 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd | |
414 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd |
|
415 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd | |
415 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd |
|
416 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd | |
416 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd |
|
417 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd | |
417 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd |
|
418 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd | |
418 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd |
|
419 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd | |
419 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd |
|
420 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd | |
420 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd |
|
421 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd | |
421 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd |
|
422 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd | |
422 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd |
|
423 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd | |
423 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd |
|
424 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd | |
424 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd |
|
425 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd | |
425 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd |
|
426 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd | |
426 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd |
|
427 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd | |
427 | # @echo "vcom lpp done" |
|
428 | # @echo "vcom lpp done" | |
428 |
|
429 | |||
429 | #include Makefile_vcom_lpp |
|
430 | #include Makefile_vcom_lpp |
@@ -1,895 +1,899 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 |
|
3 | |||
4 |
|
4 | |||
5 | LIBRARY lpp; |
|
5 | LIBRARY lpp; | |
6 | USE lpp.lpp_memory.ALL; |
|
6 | USE lpp.lpp_memory.ALL; | |
7 | USE lpp.iir_filter.ALL; |
|
7 | USE lpp.iir_filter.ALL; | |
8 | USE lpp.spectral_matrix_package.ALL; |
|
8 | USE lpp.spectral_matrix_package.ALL; | |
9 | USE lpp.lpp_dma_pkg.ALL; |
|
9 | USE lpp.lpp_dma_pkg.ALL; | |
10 | USE lpp.lpp_Header.ALL; |
|
10 | USE lpp.lpp_Header.ALL; | |
11 | USE lpp.lpp_matrix.ALL; |
|
11 | USE lpp.lpp_matrix.ALL; | |
12 | USE lpp.lpp_matrix.ALL; |
|
12 | USE lpp.lpp_matrix.ALL; | |
13 | USE lpp.lpp_lfr_pkg.ALL; |
|
13 | USE lpp.lpp_lfr_pkg.ALL; | |
14 | USE lpp.lpp_fft.ALL; |
|
14 | USE lpp.lpp_fft.ALL; | |
15 | USE lpp.fft_components.ALL; |
|
15 | USE lpp.fft_components.ALL; | |
16 |
|
16 | |||
17 | ENTITY lpp_lfr_ms IS |
|
17 | ENTITY lpp_lfr_ms IS | |
18 | GENERIC ( |
|
18 | GENERIC ( | |
19 | Mem_use : INTEGER := use_RAM |
|
19 | Mem_use : INTEGER := use_RAM | |
20 | ); |
|
20 | ); | |
21 | PORT ( |
|
21 | PORT ( | |
22 | clk : IN STD_LOGIC; |
|
22 | clk : IN STD_LOGIC; | |
23 | rstn : IN STD_LOGIC; |
|
23 | rstn : IN STD_LOGIC; | |
24 |
|
24 | |||
25 | --------------------------------------------------------------------------- |
|
25 | --------------------------------------------------------------------------- | |
26 | -- DATA INPUT |
|
26 | -- DATA INPUT | |
27 | --------------------------------------------------------------------------- |
|
27 | --------------------------------------------------------------------------- | |
28 | -- TIME |
|
28 | -- TIME | |
29 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
29 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
30 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
30 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
31 | -- |
|
31 | -- | |
32 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
32 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
33 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
33 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
34 | -- |
|
34 | -- | |
35 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
35 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
36 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
36 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
37 | -- |
|
37 | -- | |
38 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
38 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
39 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
39 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
40 |
|
40 | |||
41 | --------------------------------------------------------------------------- |
|
41 | --------------------------------------------------------------------------- | |
42 | -- DMA |
|
42 | -- DMA | |
43 | --------------------------------------------------------------------------- |
|
43 | --------------------------------------------------------------------------- | |
44 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
44 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
45 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
45 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
46 | dma_valid : OUT STD_LOGIC; |
|
46 | dma_valid : OUT STD_LOGIC; | |
47 | dma_valid_burst : OUT STD_LOGIC; |
|
47 | dma_valid_burst : OUT STD_LOGIC; | |
48 | dma_ren : IN STD_LOGIC; |
|
48 | dma_ren : IN STD_LOGIC; | |
49 | dma_done : IN STD_LOGIC; |
|
49 | dma_done : IN STD_LOGIC; | |
50 |
|
50 | |||
51 | -- Reg out |
|
51 | -- Reg out | |
52 | ready_matrix_f0_0 : OUT STD_LOGIC; |
|
52 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
53 | ready_matrix_f0_1 : OUT STD_LOGIC; |
|
53 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
54 | ready_matrix_f1 : OUT STD_LOGIC; |
|
54 | ready_matrix_f1 : OUT STD_LOGIC; | |
55 | ready_matrix_f2 : OUT STD_LOGIC; |
|
55 | ready_matrix_f2 : OUT STD_LOGIC; | |
56 | error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
56 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
57 | error_bad_component_error : OUT STD_LOGIC; |
|
57 | error_bad_component_error : OUT STD_LOGIC; | |
58 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
58 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
59 |
|
59 | |||
60 | -- Reg In |
|
60 | -- Reg In | |
61 | status_ready_matrix_f0_0 : IN STD_LOGIC; |
|
61 | status_ready_matrix_f0_0 : IN STD_LOGIC; | |
62 | status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
62 | status_ready_matrix_f0_1 : IN STD_LOGIC; | |
63 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
63 | status_ready_matrix_f1 : IN STD_LOGIC; | |
64 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
64 | status_ready_matrix_f2 : IN STD_LOGIC; | |
65 | status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
65 | status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
66 | status_error_bad_component_error : IN STD_LOGIC; |
|
66 | status_error_bad_component_error : IN STD_LOGIC; | |
67 |
|
67 | |||
68 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
68 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
69 | config_active_interruption_onError : IN STD_LOGIC; |
|
69 | config_active_interruption_onError : IN STD_LOGIC; | |
70 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
70 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
71 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
71 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
72 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
72 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
73 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
73 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
74 |
|
74 | |||
75 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
75 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
76 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
76 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
77 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
77 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
78 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
78 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
79 |
|
79 | |||
80 | ); |
|
80 | ); | |
81 | END; |
|
81 | END; | |
82 |
|
82 | |||
83 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS |
|
83 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |
84 |
|
84 | |||
85 | SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
85 | SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
86 | SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
86 | SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
87 | SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
87 | SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
88 | SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
88 | SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
89 | SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
89 | SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
90 |
|
90 | |||
91 | SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
91 | SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
92 | SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
92 | SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
93 | SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
93 | SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
94 | SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
94 | SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
95 | SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
95 | SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
96 |
|
96 | |||
97 | SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
97 | SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
98 | SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
98 | SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
99 | SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
99 | SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
100 | SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
100 | SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
101 |
|
101 | |||
102 | SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
102 | SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
103 |
|
103 | |||
104 | SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
104 | SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
105 | SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
105 | SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
106 | SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
106 | SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
107 | SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
107 | SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
108 |
|
108 | |||
109 | SIGNAL error_wen_f0 : STD_LOGIC; |
|
109 | SIGNAL error_wen_f0 : STD_LOGIC; | |
110 | SIGNAL error_wen_f1 : STD_LOGIC; |
|
110 | SIGNAL error_wen_f1 : STD_LOGIC; | |
111 | SIGNAL error_wen_f2 : STD_LOGIC; |
|
111 | SIGNAL error_wen_f2 : STD_LOGIC; | |
112 |
|
112 | |||
113 | SIGNAL one_sample_f1_full : STD_LOGIC; |
|
113 | SIGNAL one_sample_f1_full : STD_LOGIC; | |
114 | SIGNAL one_sample_f1_wen : STD_LOGIC; |
|
114 | SIGNAL one_sample_f1_wen : STD_LOGIC; | |
115 | SIGNAL one_sample_f2_full : STD_LOGIC; |
|
115 | SIGNAL one_sample_f2_full : STD_LOGIC; | |
116 | SIGNAL one_sample_f2_wen : STD_LOGIC; |
|
116 | SIGNAL one_sample_f2_wen : STD_LOGIC; | |
117 |
|
117 | |||
118 | ----------------------------------------------------------------------------- |
|
118 | ----------------------------------------------------------------------------- | |
119 | -- FSM / SWITCH SELECT CHANNEL |
|
119 | -- FSM / SWITCH SELECT CHANNEL | |
120 | ----------------------------------------------------------------------------- |
|
120 | ----------------------------------------------------------------------------- | |
121 | TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2); |
|
121 | TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2); | |
122 | SIGNAL state_fsm_select_channel : fsm_select_channel; |
|
122 | SIGNAL state_fsm_select_channel : fsm_select_channel; | |
123 | SIGNAL pre_state_fsm_select_channel : fsm_select_channel; |
|
123 | SIGNAL pre_state_fsm_select_channel : fsm_select_channel; | |
124 |
|
124 | |||
125 | SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
125 | SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
126 | SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
126 | SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
127 | SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
127 | SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
128 | SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
128 | SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
129 |
|
129 | |||
130 | ----------------------------------------------------------------------------- |
|
130 | ----------------------------------------------------------------------------- | |
131 | -- FSM LOAD FFT |
|
131 | -- FSM LOAD FFT | |
132 | ----------------------------------------------------------------------------- |
|
132 | ----------------------------------------------------------------------------- | |
133 | TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5); |
|
133 | TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5); | |
134 | SIGNAL state_fsm_load_FFT : fsm_load_FFT; |
|
134 | SIGNAL state_fsm_load_FFT : fsm_load_FFT; | |
135 | SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; |
|
135 | SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; | |
136 |
|
136 | |||
137 | SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
137 | SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
138 | SIGNAL sample_load : STD_LOGIC; |
|
138 | SIGNAL sample_load : STD_LOGIC; | |
139 | SIGNAL sample_valid : STD_LOGIC; |
|
139 | SIGNAL sample_valid : STD_LOGIC; | |
140 | SIGNAL sample_valid_r : STD_LOGIC; |
|
140 | SIGNAL sample_valid_r : STD_LOGIC; | |
141 | SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
141 | SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
142 |
|
142 | |||
143 |
|
143 | |||
144 | ----------------------------------------------------------------------------- |
|
144 | ----------------------------------------------------------------------------- | |
145 | -- FFT |
|
145 | -- FFT | |
146 | ----------------------------------------------------------------------------- |
|
146 | ----------------------------------------------------------------------------- | |
147 | SIGNAL fft_read : STD_LOGIC; |
|
147 | SIGNAL fft_read : STD_LOGIC; | |
148 | SIGNAL fft_pong : STD_LOGIC; |
|
148 | SIGNAL fft_pong : STD_LOGIC; | |
149 | SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
149 | SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
150 | SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
150 | SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
151 | SIGNAL fft_data_valid : STD_LOGIC; |
|
151 | SIGNAL fft_data_valid : STD_LOGIC; | |
152 | SIGNAL fft_ready : STD_LOGIC; |
|
152 | SIGNAL fft_ready : STD_LOGIC; | |
153 | ----------------------------------------------------------------------------- |
|
153 | ----------------------------------------------------------------------------- | |
154 | SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
154 | SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
155 | ----------------------------------------------------------------------------- |
|
155 | ----------------------------------------------------------------------------- | |
156 | TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT); |
|
156 | TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT); | |
157 | SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory; |
|
157 | SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory; | |
158 | SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
158 | SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
159 | SIGNAL current_fifo_empty : STD_LOGIC; |
|
159 | SIGNAL current_fifo_empty : STD_LOGIC; | |
160 | SIGNAL current_fifo_locked : STD_LOGIC; |
|
160 | SIGNAL current_fifo_locked : STD_LOGIC; | |
161 | SIGNAL current_fifo_full : STD_LOGIC; |
|
161 | SIGNAL current_fifo_full : STD_LOGIC; | |
162 | SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
162 | SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
163 |
|
163 | |||
164 | ----------------------------------------------------------------------------- |
|
164 | ----------------------------------------------------------------------------- | |
165 | SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
165 | SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
166 | SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
166 | SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
167 | SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
167 | SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
168 | SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
168 | SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
169 | SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); |
|
169 | SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); | |
170 | SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); |
|
170 | SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); | |
171 | SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
171 | SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
172 | SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
172 | SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
173 | ----------------------------------------------------------------------------- |
|
173 | ----------------------------------------------------------------------------- | |
174 | SIGNAL HEAD_SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
174 | SIGNAL HEAD_SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
175 | SIGNAL HEAD_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
175 | SIGNAL HEAD_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
176 | SIGNAL HEAD_SM_Wen : STD_LOGIC; |
|
176 | SIGNAL HEAD_SM_Wen : STD_LOGIC; | |
177 | SIGNAL HEAD_Valid : STD_LOGIC; |
|
177 | SIGNAL HEAD_Valid : STD_LOGIC; | |
178 | SIGNAL HEAD_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
178 | SIGNAL HEAD_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
179 | SIGNAL HEAD_Empty : STD_LOGIC; |
|
179 | SIGNAL HEAD_Empty : STD_LOGIC; | |
180 | SIGNAL HEAD_Read : STD_LOGIC; |
|
180 | SIGNAL HEAD_Read : STD_LOGIC; | |
181 | ----------------------------------------------------------------------------- |
|
181 | ----------------------------------------------------------------------------- | |
182 | SIGNAL MEM_OUT_SM_ReUse : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
182 | SIGNAL MEM_OUT_SM_ReUse : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
183 | SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
183 | SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
184 | SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
184 | SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
185 | SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
185 | SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
186 | SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
186 | SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
187 | SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
187 | SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
188 | SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
188 | SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
189 | ----------------------------------------------------------------------------- |
|
189 | ----------------------------------------------------------------------------- | |
190 | SIGNAL DMA_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
190 | SIGNAL DMA_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
191 | SIGNAL DMA_Header_Val : STD_LOGIC; |
|
191 | SIGNAL DMA_Header_Val : STD_LOGIC; | |
192 | SIGNAL DMA_Header_Ack : STD_LOGIC; |
|
192 | SIGNAL DMA_Header_Ack : STD_LOGIC; | |
193 |
|
193 | |||
194 | ----------------------------------------------------------------------------- |
|
194 | ----------------------------------------------------------------------------- | |
195 | -- TIME REG & INFOs |
|
195 | -- TIME REG & INFOs | |
196 | ----------------------------------------------------------------------------- |
|
196 | ----------------------------------------------------------------------------- | |
197 | SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
197 | SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
198 |
|
198 | |||
199 | SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
199 | SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
200 | SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
200 | SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
201 | SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
201 | SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
202 | SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
202 | SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
203 |
|
203 | |||
204 | SIGNAL time_update_f0_A : STD_LOGIC; |
|
204 | SIGNAL time_update_f0_A : STD_LOGIC; | |
205 | SIGNAL time_update_f0_B : STD_LOGIC; |
|
205 | SIGNAL time_update_f0_B : STD_LOGIC; | |
206 | SIGNAL time_update_f1 : STD_LOGIC; |
|
206 | SIGNAL time_update_f1 : STD_LOGIC; | |
207 | SIGNAL time_update_f2 : STD_LOGIC; |
|
207 | SIGNAL time_update_f2 : STD_LOGIC; | |
208 | -- |
|
208 | -- | |
209 | SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
209 | SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0); | |
210 |
|
210 | |||
211 | SIGNAL dma_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
211 | SIGNAL dma_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
212 | ----------------------------------------------------------------------------- |
|
212 | ----------------------------------------------------------------------------- | |
213 |
|
213 | |||
214 | BEGIN |
|
214 | BEGIN | |
215 |
|
215 | |||
216 | switch_f0_inst : spectral_matrix_switch_f0 |
|
216 | switch_f0_inst : spectral_matrix_switch_f0 | |
217 | PORT MAP ( |
|
217 | PORT MAP ( | |
218 | clk => clk, |
|
218 | clk => clk, | |
219 | rstn => rstn, |
|
219 | rstn => rstn, | |
220 |
|
220 | |||
221 | sample_wen => sample_f0_wen, |
|
221 | sample_wen => sample_f0_wen, | |
222 |
|
222 | |||
223 | fifo_A_empty => sample_f0_A_empty, |
|
223 | fifo_A_empty => sample_f0_A_empty, | |
224 | fifo_A_full => sample_f0_A_full, |
|
224 | fifo_A_full => sample_f0_A_full, | |
225 | fifo_A_wen => sample_f0_A_wen, |
|
225 | fifo_A_wen => sample_f0_A_wen, | |
226 |
|
226 | |||
227 | fifo_B_empty => sample_f0_B_empty, |
|
227 | fifo_B_empty => sample_f0_B_empty, | |
228 | fifo_B_full => sample_f0_B_full, |
|
228 | fifo_B_full => sample_f0_B_full, | |
229 | fifo_B_wen => sample_f0_B_wen, |
|
229 | fifo_B_wen => sample_f0_B_wen, | |
230 |
|
230 | |||
231 | error_wen => error_wen_f0); -- TODO |
|
231 | error_wen => error_wen_f0); -- TODO | |
232 |
|
232 | |||
233 | ----------------------------------------------------------------------------- |
|
233 | ----------------------------------------------------------------------------- | |
234 | -- FIFO IN |
|
234 | -- FIFO IN | |
235 | ----------------------------------------------------------------------------- |
|
235 | ----------------------------------------------------------------------------- | |
236 | lppFIFOxN_f0_a : lppFIFOxN |
|
236 | lppFIFOxN_f0_a : lppFIFOxN | |
237 | GENERIC MAP ( |
|
237 | GENERIC MAP ( | |
238 | tech => 0, |
|
238 | tech => 0, | |
239 | Mem_use => Mem_use, |
|
239 | Mem_use => Mem_use, | |
240 | Data_sz => 16, |
|
240 | Data_sz => 16, | |
241 | Addr_sz => 8, |
|
241 | Addr_sz => 8, | |
242 | FifoCnt => 5) |
|
242 | FifoCnt => 5) | |
243 | PORT MAP ( |
|
243 | PORT MAP ( | |
244 | clk => clk, |
|
244 | clk => clk, | |
245 | rstn => rstn, |
|
245 | rstn => rstn, | |
246 |
|
246 | |||
247 | ReUse => (OTHERS => '0'), |
|
247 | ReUse => (OTHERS => '0'), | |
248 |
|
248 | |||
249 | wen => sample_f0_A_wen, |
|
249 | wen => sample_f0_A_wen, | |
250 | wdata => sample_f0_wdata, |
|
250 | wdata => sample_f0_wdata, | |
251 |
|
251 | |||
252 | ren => sample_f0_A_ren, |
|
252 | ren => sample_f0_A_ren, | |
253 | rdata => sample_f0_A_rdata, |
|
253 | rdata => sample_f0_A_rdata, | |
254 |
|
254 | |||
255 | empty => sample_f0_A_empty, |
|
255 | empty => sample_f0_A_empty, | |
256 | full => sample_f0_A_full, |
|
256 | full => sample_f0_A_full, | |
257 | almost_full => OPEN); |
|
257 | almost_full => OPEN); | |
258 |
|
258 | |||
259 | lppFIFOxN_f0_b : lppFIFOxN |
|
259 | lppFIFOxN_f0_b : lppFIFOxN | |
260 | GENERIC MAP ( |
|
260 | GENERIC MAP ( | |
261 | tech => 0, |
|
261 | tech => 0, | |
262 | Mem_use => Mem_use, |
|
262 | Mem_use => Mem_use, | |
263 | Data_sz => 16, |
|
263 | Data_sz => 16, | |
264 | Addr_sz => 8, |
|
264 | Addr_sz => 8, | |
265 | FifoCnt => 5) |
|
265 | FifoCnt => 5) | |
266 | PORT MAP ( |
|
266 | PORT MAP ( | |
267 | clk => clk, |
|
267 | clk => clk, | |
268 | rstn => rstn, |
|
268 | rstn => rstn, | |
269 |
|
269 | |||
270 | ReUse => (OTHERS => '0'), |
|
270 | ReUse => (OTHERS => '0'), | |
271 |
|
271 | |||
272 | wen => sample_f0_B_wen, |
|
272 | wen => sample_f0_B_wen, | |
273 | wdata => sample_f0_wdata, |
|
273 | wdata => sample_f0_wdata, | |
274 | ren => sample_f0_B_ren, |
|
274 | ren => sample_f0_B_ren, | |
275 | rdata => sample_f0_B_rdata, |
|
275 | rdata => sample_f0_B_rdata, | |
276 | empty => sample_f0_B_empty, |
|
276 | empty => sample_f0_B_empty, | |
277 | full => sample_f0_B_full, |
|
277 | full => sample_f0_B_full, | |
278 | almost_full => OPEN); |
|
278 | almost_full => OPEN); | |
279 |
|
279 | |||
280 | lppFIFOxN_f1 : lppFIFOxN |
|
280 | lppFIFOxN_f1 : lppFIFOxN | |
281 | GENERIC MAP ( |
|
281 | GENERIC MAP ( | |
282 | tech => 0, |
|
282 | tech => 0, | |
283 | Mem_use => Mem_use, |
|
283 | Mem_use => Mem_use, | |
284 | Data_sz => 16, |
|
284 | Data_sz => 16, | |
285 | Addr_sz => 8, |
|
285 | Addr_sz => 8, | |
286 | FifoCnt => 5) |
|
286 | FifoCnt => 5) | |
287 | PORT MAP ( |
|
287 | PORT MAP ( | |
288 | clk => clk, |
|
288 | clk => clk, | |
289 | rstn => rstn, |
|
289 | rstn => rstn, | |
290 |
|
290 | |||
291 | ReUse => (OTHERS => '0'), |
|
291 | ReUse => (OTHERS => '0'), | |
292 |
|
292 | |||
293 | wen => sample_f1_wen, |
|
293 | wen => sample_f1_wen, | |
294 | wdata => sample_f1_wdata, |
|
294 | wdata => sample_f1_wdata, | |
295 | ren => sample_f1_ren, |
|
295 | ren => sample_f1_ren, | |
296 | rdata => sample_f1_rdata, |
|
296 | rdata => sample_f1_rdata, | |
297 | empty => sample_f1_empty, |
|
297 | empty => sample_f1_empty, | |
298 | full => sample_f1_full, |
|
298 | full => sample_f1_full, | |
299 | almost_full => sample_f1_almost_full); |
|
299 | almost_full => sample_f1_almost_full); | |
300 |
|
300 | |||
301 |
|
301 | |||
302 | one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1'; |
|
302 | one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1'; | |
303 |
|
303 | |||
304 | PROCESS (clk, rstn) |
|
304 | PROCESS (clk, rstn) | |
305 | BEGIN -- PROCESS |
|
305 | BEGIN -- PROCESS | |
306 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
306 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
307 | one_sample_f1_full <= '0'; |
|
307 | one_sample_f1_full <= '0'; | |
308 | error_wen_f1 <= '0'; |
|
308 | error_wen_f1 <= '0'; | |
309 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
309 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
310 | IF sample_f1_full = "00000" THEN |
|
310 | IF sample_f1_full = "00000" THEN | |
311 | one_sample_f1_full <= '0'; |
|
311 | one_sample_f1_full <= '0'; | |
312 | ELSE |
|
312 | ELSE | |
313 | one_sample_f1_full <= '1'; |
|
313 | one_sample_f1_full <= '1'; | |
314 | END IF; |
|
314 | END IF; | |
315 | error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full; |
|
315 | error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full; | |
316 | END IF; |
|
316 | END IF; | |
317 | END PROCESS; |
|
317 | END PROCESS; | |
318 |
|
318 | |||
319 |
|
319 | |||
320 | lppFIFOxN_f2 : lppFIFOxN |
|
320 | lppFIFOxN_f2 : lppFIFOxN | |
321 | GENERIC MAP ( |
|
321 | GENERIC MAP ( | |
322 | tech => 0, |
|
322 | tech => 0, | |
323 | Mem_use => Mem_use, |
|
323 | Mem_use => Mem_use, | |
324 | Data_sz => 16, |
|
324 | Data_sz => 16, | |
325 | Addr_sz => 8, |
|
325 | Addr_sz => 8, | |
326 | FifoCnt => 5) |
|
326 | FifoCnt => 5) | |
327 | PORT MAP ( |
|
327 | PORT MAP ( | |
328 | clk => clk, |
|
328 | clk => clk, | |
329 | rstn => rstn, |
|
329 | rstn => rstn, | |
330 |
|
330 | |||
331 | ReUse => (OTHERS => '0'), |
|
331 | ReUse => (OTHERS => '0'), | |
332 |
|
332 | |||
333 | wen => sample_f2_wen, |
|
333 | wen => sample_f2_wen, | |
334 | wdata => sample_f2_wdata, |
|
334 | wdata => sample_f2_wdata, | |
335 | ren => sample_f2_ren, |
|
335 | ren => sample_f2_ren, | |
336 | rdata => sample_f2_rdata, |
|
336 | rdata => sample_f2_rdata, | |
337 | empty => sample_f2_empty, |
|
337 | empty => sample_f2_empty, | |
338 | full => sample_f2_full, |
|
338 | full => sample_f2_full, | |
339 | almost_full => OPEN); |
|
339 | almost_full => OPEN); | |
340 |
|
340 | |||
341 |
|
341 | |||
342 | one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1'; |
|
342 | one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1'; | |
343 |
|
343 | |||
344 | PROCESS (clk, rstn) |
|
344 | PROCESS (clk, rstn) | |
345 | BEGIN -- PROCESS |
|
345 | BEGIN -- PROCESS | |
346 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
346 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
347 | one_sample_f2_full <= '0'; |
|
347 | one_sample_f2_full <= '0'; | |
348 | error_wen_f2 <= '0'; |
|
348 | error_wen_f2 <= '0'; | |
349 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
349 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
350 | IF sample_f2_full = "00000" THEN |
|
350 | IF sample_f2_full = "00000" THEN | |
351 | one_sample_f2_full <= '0'; |
|
351 | one_sample_f2_full <= '0'; | |
352 | ELSE |
|
352 | ELSE | |
353 | one_sample_f2_full <= '1'; |
|
353 | one_sample_f2_full <= '1'; | |
354 | END IF; |
|
354 | END IF; | |
355 | error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full; |
|
355 | error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full; | |
356 | END IF; |
|
356 | END IF; | |
357 | END PROCESS; |
|
357 | END PROCESS; | |
358 |
|
358 | |||
359 | ----------------------------------------------------------------------------- |
|
359 | ----------------------------------------------------------------------------- | |
360 | -- FSM SELECT CHANNEL |
|
360 | -- FSM SELECT CHANNEL | |
361 | ----------------------------------------------------------------------------- |
|
361 | ----------------------------------------------------------------------------- | |
362 | PROCESS (clk, rstn) |
|
362 | PROCESS (clk, rstn) | |
363 | BEGIN |
|
363 | BEGIN | |
364 | IF rstn = '0' THEN |
|
364 | IF rstn = '0' THEN | |
365 | state_fsm_select_channel <= IDLE; |
|
365 | state_fsm_select_channel <= IDLE; | |
366 | ELSIF clk'EVENT AND clk = '1' THEN |
|
366 | ELSIF clk'EVENT AND clk = '1' THEN | |
367 | CASE state_fsm_select_channel IS |
|
367 | CASE state_fsm_select_channel IS | |
368 | WHEN IDLE => |
|
368 | WHEN IDLE => | |
369 | IF sample_f1_full = "11111" THEN |
|
369 | IF sample_f1_full = "11111" THEN | |
370 | state_fsm_select_channel <= SWITCH_F1; |
|
370 | state_fsm_select_channel <= SWITCH_F1; | |
371 | ELSIF sample_f1_almost_full = "00000" THEN |
|
371 | ELSIF sample_f1_almost_full = "00000" THEN | |
372 | IF sample_f0_A_full = "11111" THEN |
|
372 | IF sample_f0_A_full = "11111" THEN | |
373 | state_fsm_select_channel <= SWITCH_F0_A; |
|
373 | state_fsm_select_channel <= SWITCH_F0_A; | |
374 | ELSIF sample_f0_B_full = "11111" THEN |
|
374 | ELSIF sample_f0_B_full = "11111" THEN | |
375 | state_fsm_select_channel <= SWITCH_F0_B; |
|
375 | state_fsm_select_channel <= SWITCH_F0_B; | |
376 | ELSIF sample_f2_full = "11111" THEN |
|
376 | ELSIF sample_f2_full = "11111" THEN | |
377 | state_fsm_select_channel <= SWITCH_F2; |
|
377 | state_fsm_select_channel <= SWITCH_F2; | |
378 | END IF; |
|
378 | END IF; | |
379 | END IF; |
|
379 | END IF; | |
380 |
|
380 | |||
381 | WHEN SWITCH_F0_A => |
|
381 | WHEN SWITCH_F0_A => | |
382 | IF sample_f0_A_empty = "11111" THEN |
|
382 | IF sample_f0_A_empty = "11111" THEN | |
383 | state_fsm_select_channel <= IDLE; |
|
383 | state_fsm_select_channel <= IDLE; | |
384 | END IF; |
|
384 | END IF; | |
385 | WHEN SWITCH_F0_B => |
|
385 | WHEN SWITCH_F0_B => | |
386 | IF sample_f0_B_empty = "11111" THEN |
|
386 | IF sample_f0_B_empty = "11111" THEN | |
387 | state_fsm_select_channel <= IDLE; |
|
387 | state_fsm_select_channel <= IDLE; | |
388 | END IF; |
|
388 | END IF; | |
389 | WHEN SWITCH_F1 => |
|
389 | WHEN SWITCH_F1 => | |
390 | IF sample_f1_empty = "11111" THEN |
|
390 | IF sample_f1_empty = "11111" THEN | |
391 | state_fsm_select_channel <= IDLE; |
|
391 | state_fsm_select_channel <= IDLE; | |
392 | END IF; |
|
392 | END IF; | |
393 | WHEN SWITCH_F2 => |
|
393 | WHEN SWITCH_F2 => | |
394 | IF sample_f2_empty = "11111" THEN |
|
394 | IF sample_f2_empty = "11111" THEN | |
395 | state_fsm_select_channel <= IDLE; |
|
395 | state_fsm_select_channel <= IDLE; | |
396 | END IF; |
|
396 | END IF; | |
397 | WHEN OTHERS => NULL; |
|
397 | WHEN OTHERS => NULL; | |
398 | END CASE; |
|
398 | END CASE; | |
399 |
|
399 | |||
400 | END IF; |
|
400 | END IF; | |
401 | END PROCESS; |
|
401 | END PROCESS; | |
402 |
|
402 | |||
403 | PROCESS (clk, rstn) |
|
403 | PROCESS (clk, rstn) | |
404 | BEGIN |
|
404 | BEGIN | |
405 | IF rstn = '0' THEN |
|
405 | IF rstn = '0' THEN | |
406 | pre_state_fsm_select_channel <= IDLE; |
|
406 | pre_state_fsm_select_channel <= IDLE; | |
407 | ELSIF clk'EVENT AND clk = '1' THEN |
|
407 | ELSIF clk'EVENT AND clk = '1' THEN | |
408 | pre_state_fsm_select_channel <= state_fsm_select_channel; |
|
408 | pre_state_fsm_select_channel <= state_fsm_select_channel; | |
409 | END IF; |
|
409 | END IF; | |
410 | END PROCESS; |
|
410 | END PROCESS; | |
411 |
|
411 | |||
412 |
|
412 | |||
413 | ----------------------------------------------------------------------------- |
|
413 | ----------------------------------------------------------------------------- | |
414 | -- SWITCH SELECT CHANNEL |
|
414 | -- SWITCH SELECT CHANNEL | |
415 | ----------------------------------------------------------------------------- |
|
415 | ----------------------------------------------------------------------------- | |
416 | sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
416 | sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE | |
417 | sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
417 | sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE | |
418 | sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
418 | sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE | |
419 | sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
419 | sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE | |
420 | (OTHERS => '1'); |
|
420 | (OTHERS => '1'); | |
421 |
|
421 | |||
422 | sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
422 | sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE | |
423 | sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
423 | sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE | |
424 | sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
424 | sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE | |
425 | sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
425 | sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE | |
426 | (OTHERS => '0'); |
|
426 | (OTHERS => '0'); | |
427 |
|
427 | |||
428 | sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE |
|
428 | sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE | |
429 | sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE |
|
429 | sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE | |
430 | sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE |
|
430 | sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE | |
431 | sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
431 | sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE | |
432 |
|
432 | |||
433 |
|
433 | |||
434 | sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1'); |
|
434 | sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1'); | |
435 | sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1'); |
|
435 | sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1'); | |
436 | sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1'); |
|
436 | sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1'); | |
437 | sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1'); |
|
437 | sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1'); | |
438 |
|
438 | |||
439 |
|
439 | |||
440 | status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
440 | status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE | |
441 | time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
441 | time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE | |
442 | time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
442 | time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE | |
443 | time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2 |
|
443 | time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2 | |
444 |
|
444 | |||
445 | ----------------------------------------------------------------------------- |
|
445 | ----------------------------------------------------------------------------- | |
446 | -- FSM LOAD FFT |
|
446 | -- FSM LOAD FFT | |
447 | ----------------------------------------------------------------------------- |
|
447 | ----------------------------------------------------------------------------- | |
448 |
|
448 | |||
449 | sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1'); |
|
449 | sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1'); | |
450 |
|
450 | |||
451 | PROCESS (clk, rstn) |
|
451 | PROCESS (clk, rstn) | |
452 | BEGIN |
|
452 | BEGIN | |
453 | IF rstn = '0' THEN |
|
453 | IF rstn = '0' THEN | |
454 | sample_ren_s <= (OTHERS => '1'); |
|
454 | sample_ren_s <= (OTHERS => '1'); | |
455 | state_fsm_load_FFT <= IDLE; |
|
455 | state_fsm_load_FFT <= IDLE; | |
456 | --next_state_fsm_load_FFT <= IDLE; |
|
456 | --next_state_fsm_load_FFT <= IDLE; | |
457 | --sample_valid <= '0'; |
|
457 | --sample_valid <= '0'; | |
458 | ELSIF clk'EVENT AND clk = '1' THEN |
|
458 | ELSIF clk'EVENT AND clk = '1' THEN | |
459 | CASE state_fsm_load_FFT IS |
|
459 | CASE state_fsm_load_FFT IS | |
460 | WHEN IDLE => |
|
460 | WHEN IDLE => | |
461 | --sample_valid <= '0'; |
|
461 | --sample_valid <= '0'; | |
462 | sample_ren_s <= (OTHERS => '1'); |
|
462 | sample_ren_s <= (OTHERS => '1'); | |
463 | IF sample_full = "11111" AND sample_load = '1' THEN |
|
463 | IF sample_full = "11111" AND sample_load = '1' THEN | |
464 | state_fsm_load_FFT <= FIFO_1; |
|
464 | state_fsm_load_FFT <= FIFO_1; | |
465 | END IF; |
|
465 | END IF; | |
466 |
|
466 | |||
467 | WHEN FIFO_1 => |
|
467 | WHEN FIFO_1 => | |
468 | sample_ren_s <= "1111" & NOT(sample_load); |
|
468 | sample_ren_s <= "1111" & NOT(sample_load); | |
469 | IF sample_empty(0) = '1' THEN |
|
469 | IF sample_empty(0) = '1' THEN | |
470 | sample_ren_s <= (OTHERS => '1'); |
|
470 | sample_ren_s <= (OTHERS => '1'); | |
471 | state_fsm_load_FFT <= FIFO_2; |
|
471 | state_fsm_load_FFT <= FIFO_2; | |
472 | END IF; |
|
472 | END IF; | |
473 |
|
473 | |||
474 | WHEN FIFO_2 => |
|
474 | WHEN FIFO_2 => | |
475 | sample_ren_s <= "111" & NOT(sample_load) & '1'; |
|
475 | sample_ren_s <= "111" & NOT(sample_load) & '1'; | |
476 | IF sample_empty(1) = '1' THEN |
|
476 | IF sample_empty(1) = '1' THEN | |
477 | sample_ren_s <= (OTHERS => '1'); |
|
477 | sample_ren_s <= (OTHERS => '1'); | |
478 | state_fsm_load_FFT <= FIFO_3; |
|
478 | state_fsm_load_FFT <= FIFO_3; | |
479 | END IF; |
|
479 | END IF; | |
480 |
|
480 | |||
481 | WHEN FIFO_3 => |
|
481 | WHEN FIFO_3 => | |
482 | sample_ren_s <= "11" & NOT(sample_load) & "11"; |
|
482 | sample_ren_s <= "11" & NOT(sample_load) & "11"; | |
483 | IF sample_empty(2) = '1' THEN |
|
483 | IF sample_empty(2) = '1' THEN | |
484 | sample_ren_s <= (OTHERS => '1'); |
|
484 | sample_ren_s <= (OTHERS => '1'); | |
485 | state_fsm_load_FFT <= FIFO_4; |
|
485 | state_fsm_load_FFT <= FIFO_4; | |
486 | END IF; |
|
486 | END IF; | |
487 |
|
487 | |||
488 | WHEN FIFO_4 => |
|
488 | WHEN FIFO_4 => | |
489 | sample_ren_s <= '1' & NOT(sample_load) & "111"; |
|
489 | sample_ren_s <= '1' & NOT(sample_load) & "111"; | |
490 | IF sample_empty(3) = '1' THEN |
|
490 | IF sample_empty(3) = '1' THEN | |
491 | sample_ren_s <= (OTHERS => '1'); |
|
491 | sample_ren_s <= (OTHERS => '1'); | |
492 | state_fsm_load_FFT <= FIFO_5; |
|
492 | state_fsm_load_FFT <= FIFO_5; | |
493 | END IF; |
|
493 | END IF; | |
494 |
|
494 | |||
495 | WHEN FIFO_5 => |
|
495 | WHEN FIFO_5 => | |
496 | sample_ren_s <= NOT(sample_load) & "1111"; |
|
496 | sample_ren_s <= NOT(sample_load) & "1111"; | |
497 | IF sample_empty(4) = '1' THEN |
|
497 | IF sample_empty(4) = '1' THEN | |
498 | sample_ren_s <= (OTHERS => '1'); |
|
498 | sample_ren_s <= (OTHERS => '1'); | |
499 | state_fsm_load_FFT <= IDLE; |
|
499 | state_fsm_load_FFT <= IDLE; | |
500 | END IF; |
|
500 | END IF; | |
501 | WHEN OTHERS => NULL; |
|
501 | WHEN OTHERS => NULL; | |
502 | END CASE; |
|
502 | END CASE; | |
503 | END IF; |
|
503 | END IF; | |
504 | END PROCESS; |
|
504 | END PROCESS; | |
505 |
|
505 | |||
506 | PROCESS (clk, rstn) |
|
506 | PROCESS (clk, rstn) | |
507 | BEGIN |
|
507 | BEGIN | |
508 | IF rstn = '0' THEN |
|
508 | IF rstn = '0' THEN | |
509 | sample_valid_r <= '0'; |
|
509 | sample_valid_r <= '0'; | |
510 | next_state_fsm_load_FFT <= IDLE; |
|
510 | next_state_fsm_load_FFT <= IDLE; | |
511 | ELSIF clk'EVENT AND clk = '1' THEN |
|
511 | ELSIF clk'EVENT AND clk = '1' THEN | |
512 | next_state_fsm_load_FFT <= state_fsm_load_FFT; |
|
512 | next_state_fsm_load_FFT <= state_fsm_load_FFT; | |
513 | IF sample_ren_s = "11111" THEN |
|
513 | IF sample_ren_s = "11111" THEN | |
514 | sample_valid_r <= '0'; |
|
514 | sample_valid_r <= '0'; | |
515 | ELSE |
|
515 | ELSE | |
516 | sample_valid_r <= '1'; |
|
516 | sample_valid_r <= '1'; | |
517 | END IF; |
|
517 | END IF; | |
518 | END IF; |
|
518 | END IF; | |
519 | END PROCESS; |
|
519 | END PROCESS; | |
520 |
|
520 | |||
521 | sample_valid <= sample_valid_r AND sample_load; |
|
521 | sample_valid <= sample_valid_r AND sample_load; | |
522 |
|
522 | |||
523 | sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE |
|
523 | sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE | |
524 | sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE |
|
524 | sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE | |
525 | sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE |
|
525 | sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE | |
526 | sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE |
|
526 | sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE | |
527 | sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE |
|
527 | sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE | |
528 |
|
528 | |||
529 | ----------------------------------------------------------------------------- |
|
529 | ----------------------------------------------------------------------------- | |
530 | -- FFT |
|
530 | -- FFT | |
531 | ----------------------------------------------------------------------------- |
|
531 | ----------------------------------------------------------------------------- | |
532 | CoreFFT_1 : CoreFFT |
|
532 | CoreFFT_1 : CoreFFT | |
533 | GENERIC MAP ( |
|
533 | GENERIC MAP ( | |
534 | LOGPTS => gLOGPTS, |
|
534 | LOGPTS => gLOGPTS, | |
535 | LOGLOGPTS => gLOGLOGPTS, |
|
535 | LOGLOGPTS => gLOGLOGPTS, | |
536 | WSIZE => gWSIZE, |
|
536 | WSIZE => gWSIZE, | |
537 | TWIDTH => gTWIDTH, |
|
537 | TWIDTH => gTWIDTH, | |
538 | DWIDTH => gDWIDTH, |
|
538 | DWIDTH => gDWIDTH, | |
539 | TDWIDTH => gTDWIDTH, |
|
539 | TDWIDTH => gTDWIDTH, | |
540 | RND_MODE => gRND_MODE, |
|
540 | RND_MODE => gRND_MODE, | |
541 | SCALE_MODE => gSCALE_MODE, |
|
541 | SCALE_MODE => gSCALE_MODE, | |
542 | PTS => gPTS, |
|
542 | PTS => gPTS, | |
543 | HALFPTS => gHALFPTS, |
|
543 | HALFPTS => gHALFPTS, | |
544 | inBuf_RWDLY => gInBuf_RWDLY) |
|
544 | inBuf_RWDLY => gInBuf_RWDLY) | |
545 | PORT MAP ( |
|
545 | PORT MAP ( | |
546 | clk => clk, |
|
546 | clk => clk, | |
547 | ifiStart => '1', |
|
547 | ifiStart => '1', | |
548 | ifiNreset => rstn, |
|
548 | ifiNreset => rstn, | |
549 |
|
549 | |||
550 | ifiD_valid => sample_valid, -- IN |
|
550 | ifiD_valid => sample_valid, -- IN | |
551 | ifiRead_y => fft_read, |
|
551 | ifiRead_y => fft_read, | |
552 | ifiD_im => (OTHERS => '0'), -- IN |
|
552 | ifiD_im => (OTHERS => '0'), -- IN | |
553 | ifiD_re => sample_data, -- IN |
|
553 | ifiD_re => sample_data, -- IN | |
554 | ifoLoad => sample_load, -- IN |
|
554 | ifoLoad => sample_load, -- IN | |
555 |
|
555 | |||
556 | ifoPong => fft_pong, |
|
556 | ifoPong => fft_pong, | |
557 | ifoY_im => fft_data_im, |
|
557 | ifoY_im => fft_data_im, | |
558 | ifoY_re => fft_data_re, |
|
558 | ifoY_re => fft_data_re, | |
559 | ifoY_valid => fft_data_valid, |
|
559 | ifoY_valid => fft_data_valid, | |
560 | ifoY_rdy => fft_ready); |
|
560 | ifoY_rdy => fft_ready); | |
561 |
|
561 | |||
562 | ----------------------------------------------------------------------------- |
|
562 | ----------------------------------------------------------------------------- | |
563 | -- in fft_data_im & fft_data_re |
|
563 | -- in fft_data_im & fft_data_re | |
564 | -- in fft_data_valid |
|
564 | -- in fft_data_valid | |
565 | -- in fft_ready |
|
565 | -- in fft_ready | |
566 | -- out fft_read |
|
566 | -- out fft_read | |
567 | PROCESS (clk, rstn) |
|
567 | PROCESS (clk, rstn) | |
568 | BEGIN |
|
568 | BEGIN | |
569 | IF rstn = '0' THEN |
|
569 | IF rstn = '0' THEN | |
570 | state_fsm_load_MS_memory <= IDLE; |
|
570 | state_fsm_load_MS_memory <= IDLE; | |
571 | current_fifo_load <= "00001"; |
|
571 | current_fifo_load <= "00001"; | |
572 | ELSIF clk'event AND clk = '1' THEN |
|
572 | ELSIF clk'event AND clk = '1' THEN | |
573 | CASE state_fsm_load_MS_memory IS |
|
573 | CASE state_fsm_load_MS_memory IS | |
574 | WHEN IDLE => |
|
574 | WHEN IDLE => | |
575 | IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN |
|
575 | IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN | |
576 | state_fsm_load_MS_memory <= LOAD_FIFO; |
|
576 | state_fsm_load_MS_memory <= LOAD_FIFO; | |
577 | END IF; |
|
577 | END IF; | |
578 | WHEN LOAD_FIFO => |
|
578 | WHEN LOAD_FIFO => | |
579 | IF current_fifo_full = '1' THEN |
|
579 | IF current_fifo_full = '1' THEN | |
580 | state_fsm_load_MS_memory <= TRASH_FFT; |
|
580 | state_fsm_load_MS_memory <= TRASH_FFT; | |
581 | END IF; |
|
581 | END IF; | |
582 | WHEN TRASH_FFT => |
|
582 | WHEN TRASH_FFT => | |
583 | IF fft_ready = '0' THEN |
|
583 | IF fft_ready = '0' THEN | |
584 | state_fsm_load_MS_memory <= IDLE; |
|
584 | state_fsm_load_MS_memory <= IDLE; | |
585 | current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4); |
|
585 | current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4); | |
586 | END IF; |
|
586 | END IF; | |
587 | WHEN OTHERS => NULL; |
|
587 | WHEN OTHERS => NULL; | |
588 | END CASE; |
|
588 | END CASE; | |
589 |
|
589 | |||
590 | END IF; |
|
590 | END IF; | |
591 | END PROCESS; |
|
591 | END PROCESS; | |
592 |
|
592 | |||
593 | current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE |
|
593 | current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE | |
594 | MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE |
|
594 | MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE | |
595 | MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE |
|
595 | MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE | |
596 | MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE |
|
596 | MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE | |
597 | MEM_IN_SM_Empty(4);-- WHEN current_fifo_load(3) = '1' ELSE |
|
597 | MEM_IN_SM_Empty(4);-- WHEN current_fifo_load(3) = '1' ELSE | |
598 |
|
598 | |||
599 | current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE |
|
599 | current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE | |
600 | MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE |
|
600 | MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE | |
601 | MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE |
|
601 | MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE | |
602 | MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE |
|
602 | MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE | |
603 | MEM_IN_SM_Full(4);-- WHEN current_fifo_load(3) = '1' ELSE |
|
603 | MEM_IN_SM_Full(4);-- WHEN current_fifo_load(3) = '1' ELSE | |
604 |
|
604 | |||
605 | current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE |
|
605 | current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE | |
606 | MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE |
|
606 | MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE | |
607 | MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE |
|
607 | MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE | |
608 | MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE |
|
608 | MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE | |
609 | MEM_IN_SM_locked(4);-- WHEN current_fifo_load(3) = '1' ELSE |
|
609 | MEM_IN_SM_locked(4);-- WHEN current_fifo_load(3) = '1' ELSE | |
610 |
|
610 | |||
611 | fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1'; |
|
611 | fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1'; | |
612 |
|
612 | |||
613 | all_fifo: FOR I IN 4 DOWNTO 0 GENERATE |
|
613 | all_fifo: FOR I IN 4 DOWNTO 0 GENERATE | |
614 | MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1' |
|
614 | MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1' | |
615 | AND state_fsm_load_MS_memory = LOAD_FIFO |
|
615 | AND state_fsm_load_MS_memory = LOAD_FIFO | |
616 | AND current_fifo_load(I) = '1' |
|
616 | AND current_fifo_load(I) = '1' | |
617 | ELSE '1'; |
|
617 | ELSE '1'; | |
618 | END GENERATE all_fifo; |
|
618 | END GENERATE all_fifo; | |
619 |
|
619 | |||
620 | PROCESS (clk, rstn) |
|
620 | PROCESS (clk, rstn) | |
621 | BEGIN |
|
621 | BEGIN | |
622 | IF rstn = '0' THEN |
|
622 | IF rstn = '0' THEN | |
623 | MEM_IN_SM_wen <= (OTHERS => '1'); |
|
623 | MEM_IN_SM_wen <= (OTHERS => '1'); | |
624 | ELSIF clk'event AND clk = '1' THEN |
|
624 | ELSIF clk'event AND clk = '1' THEN | |
625 | MEM_IN_SM_wen <= MEM_IN_SM_wen_s; |
|
625 | MEM_IN_SM_wen <= MEM_IN_SM_wen_s; | |
626 | END IF; |
|
626 | END IF; | |
627 | END PROCESS; |
|
627 | END PROCESS; | |
628 |
|
628 | |||
629 | MEM_IN_SM_wData <= (fft_data_im & fft_data_re) & |
|
629 | MEM_IN_SM_wData <= (fft_data_im & fft_data_re) & | |
630 | (fft_data_im & fft_data_re) & |
|
630 | (fft_data_im & fft_data_re) & | |
631 | (fft_data_im & fft_data_re) & |
|
631 | (fft_data_im & fft_data_re) & | |
632 | (fft_data_im & fft_data_re) & |
|
632 | (fft_data_im & fft_data_re) & | |
633 | (fft_data_im & fft_data_re); |
|
633 | (fft_data_im & fft_data_re); | |
634 |
|
634 | |||
635 |
|
635 | |||
636 | -- out SM_MEM_IN_wData |
|
636 | -- out SM_MEM_IN_wData | |
637 | -- out SM_MEM_IN_wen |
|
637 | -- out SM_MEM_IN_wen | |
638 | -- out SM_MEM_IN_Full |
|
638 | -- out SM_MEM_IN_Full | |
639 |
|
639 | |||
640 | -- out SM_MEM_IN_locked |
|
640 | -- out SM_MEM_IN_locked | |
641 | ----------------------------------------------------------------------------- |
|
641 | ----------------------------------------------------------------------------- | |
642 | ----------------------------------------------------------------------------- |
|
642 | ----------------------------------------------------------------------------- | |
643 | ----------------------------------------------------------------------------- |
|
643 | ----------------------------------------------------------------------------- | |
644 | ----------------------------------------------------------------------------- |
|
644 | ----------------------------------------------------------------------------- | |
645 | --Linker_FFT_1 : Linker_FFT |
|
645 | --Linker_FFT_1 : Linker_FFT | |
646 | -- GENERIC MAP ( |
|
646 | -- GENERIC MAP ( | |
647 | -- Data_sz => 16, |
|
647 | -- Data_sz => 16, | |
648 | -- NbData => 256) |
|
648 | -- NbData => 256) | |
649 | -- PORT MAP ( |
|
649 | -- PORT MAP ( | |
650 | -- clk => clk, |
|
650 | -- clk => clk, | |
651 | -- rstn => rstn, |
|
651 | -- rstn => rstn, | |
652 |
|
652 | |||
653 | -- Ready => fft_ready, |
|
653 | -- Ready => fft_ready, | |
654 | -- Valid => fft_data_valid, |
|
654 | -- Valid => fft_data_valid, | |
655 |
|
655 | |||
656 | -- Full => MEM_IN_SM_Full, |
|
656 | -- Full => MEM_IN_SM_Full, | |
657 |
|
657 | |||
658 | -- Data_re => fft_data_re, |
|
658 | -- Data_re => fft_data_re, | |
659 | -- Data_im => fft_data_im, |
|
659 | -- Data_im => fft_data_im, | |
660 | -- Read => fft_read, |
|
660 | -- Read => fft_read, | |
661 |
|
661 | |||
662 | -- Write => MEM_IN_SM_wen, |
|
662 | -- Write => MEM_IN_SM_wen, | |
663 | -- ReUse => fft_linker_ReUse, |
|
663 | -- ReUse => fft_linker_ReUse, | |
664 | -- DATA => MEM_IN_SM_wData); |
|
664 | -- DATA => MEM_IN_SM_wData); | |
665 |
|
665 | |||
666 | ----------------------------------------------------------------------------- |
|
666 | ----------------------------------------------------------------------------- | |
667 | Mem_In_SpectralMatrix : lppFIFOxN |
|
667 | Mem_In_SpectralMatrix : lppFIFOxN | |
668 | GENERIC MAP ( |
|
668 | GENERIC MAP ( | |
669 | tech => 0, |
|
669 | tech => 0, | |
670 | Mem_use => Mem_use, |
|
670 | Mem_use => Mem_use, | |
671 | Data_sz => 32, --16, |
|
671 | Data_sz => 32, --16, | |
672 | Addr_sz => 7, --8 |
|
672 | Addr_sz => 7, --8 | |
673 | FifoCnt => 5) |
|
673 | FifoCnt => 5) | |
674 | PORT MAP ( |
|
674 | PORT MAP ( | |
675 | clk => clk, |
|
675 | clk => clk, | |
676 | rstn => rstn, |
|
676 | rstn => rstn, | |
677 |
|
677 | |||
678 | ReUse => MEM_IN_SM_ReUse, |
|
678 | ReUse => MEM_IN_SM_ReUse, | |
679 |
|
679 | |||
680 | wen => MEM_IN_SM_wen, |
|
680 | wen => MEM_IN_SM_wen, | |
681 | wdata => MEM_IN_SM_wData, |
|
681 | wdata => MEM_IN_SM_wData, | |
682 |
|
682 | |||
683 | ren => MEM_IN_SM_ren, |
|
683 | ren => MEM_IN_SM_ren, | |
684 | rdata => MEM_IN_SM_rData, |
|
684 | rdata => MEM_IN_SM_rData, | |
685 | full => MEM_IN_SM_Full, |
|
685 | full => MEM_IN_SM_Full, | |
686 | empty => MEM_IN_SM_Empty); |
|
686 | empty => MEM_IN_SM_Empty); | |
687 |
|
687 | |||
688 |
|
688 | |||
689 | all_lock: FOR I IN 4 DOWNTO 0 GENERATE |
|
689 | all_lock: FOR I IN 4 DOWNTO 0 GENERATE | |
690 | PROCESS (clk, rstn) |
|
690 | PROCESS (clk, rstn) | |
691 | BEGIN |
|
691 | BEGIN | |
692 | IF rstn = '0' THEN |
|
692 | IF rstn = '0' THEN | |
693 | MEM_IN_SM_locked(I) <= '0'; |
|
693 | MEM_IN_SM_locked(I) <= '0'; | |
694 | ELSIF clk'event AND clk = '1' THEN |
|
694 | ELSIF clk'event AND clk = '1' THEN | |
695 | MEM_IN_SM_locked(I) <= MEM_IN_SM_Full(I) OR MEM_IN_SM_locked(I); -- TODO |
|
695 | MEM_IN_SM_locked(I) <= MEM_IN_SM_Full(I) OR MEM_IN_SM_locked(I); -- TODO | |
696 | END IF; |
|
696 | END IF; | |
697 | END PROCESS; |
|
697 | END PROCESS; | |
698 | END GENERATE all_lock; |
|
698 | END GENERATE all_lock; | |
699 |
|
699 | |||
|
700 | ----------------------------------------------------------------------------- | |||
|
701 | ||||
|
702 | ||||
|
703 | ||||
700 |
|
704 | |||
701 |
|
705 | |||
702 | ----------------------------------------------------------------------------- |
|
706 | ----------------------------------------------------------------------------- | |
703 | SM0 : MatriceSpectrale |
|
707 | SM0 : MatriceSpectrale | |
704 | GENERIC MAP ( |
|
708 | GENERIC MAP ( | |
705 | Input_SZ => 16, |
|
709 | Input_SZ => 16, | |
706 | Result_SZ => 32) |
|
710 | Result_SZ => 32) | |
707 | PORT MAP ( |
|
711 | PORT MAP ( | |
708 | clkm => clk, |
|
712 | clkm => clk, | |
709 | rstn => rstn, |
|
713 | rstn => rstn, | |
710 |
|
714 | |||
711 | FifoIN_Full => MEM_IN_SM_Full, |
|
715 | FifoIN_Full => MEM_IN_SM_Full, | |
712 | Data_IN => MEM_IN_SM_rData(79 DOWNTO 0), |
|
716 | Data_IN => MEM_IN_SM_rData(79 DOWNTO 0), | |
713 | Read => MEM_IN_SM_ren, |
|
717 | Read => MEM_IN_SM_ren, | |
714 | ReUse => MEM_IN_SM_ReUse, |
|
718 | ReUse => MEM_IN_SM_ReUse, | |
715 |
|
719 | |||
716 | SetReUse => fft_linker_ReUse, |
|
720 | SetReUse => fft_linker_ReUse, | |
717 |
|
721 | |||
718 | Valid => HEAD_Valid, |
|
722 | Valid => HEAD_Valid, | |
719 | ACK => DMA_Header_Ack, |
|
723 | ACK => DMA_Header_Ack, | |
720 | SM_Write => HEAD_SM_Wen, |
|
724 | SM_Write => HEAD_SM_Wen, | |
721 | FlagError => OPEN, |
|
725 | FlagError => OPEN, | |
722 | Statu => HEAD_SM_Param, |
|
726 | Statu => HEAD_SM_Param, | |
723 | Write => MEM_OUT_SM_Write, |
|
727 | Write => MEM_OUT_SM_Write, | |
724 | Data_OUT => MEM_OUT_SM_Data_in); |
|
728 | Data_OUT => MEM_OUT_SM_Data_in); | |
725 | ----------------------------------------------------------------------------- |
|
729 | ----------------------------------------------------------------------------- | |
726 | Mem_Out_SpectralMatrix : lppFIFOxN |
|
730 | Mem_Out_SpectralMatrix : lppFIFOxN | |
727 | GENERIC MAP ( |
|
731 | GENERIC MAP ( | |
728 | tech => 0, |
|
732 | tech => 0, | |
729 | Mem_use => Mem_use, |
|
733 | Mem_use => Mem_use, | |
730 | Data_sz => 32, |
|
734 | Data_sz => 32, | |
731 | Addr_sz => 8, |
|
735 | Addr_sz => 8, | |
732 | FifoCnt => 2) |
|
736 | FifoCnt => 2) | |
733 | PORT MAP ( |
|
737 | PORT MAP ( | |
734 | clk => clk, |
|
738 | clk => clk, | |
735 | rstn => rstn, |
|
739 | rstn => rstn, | |
736 |
|
740 | |||
737 | ReUse => (OTHERS => '0'), |
|
741 | ReUse => (OTHERS => '0'), | |
738 |
|
742 | |||
739 | wen => MEM_OUT_SM_Write, |
|
743 | wen => MEM_OUT_SM_Write, | |
740 | wdata => MEM_OUT_SM_Data_in, |
|
744 | wdata => MEM_OUT_SM_Data_in, | |
741 | ren => MEM_OUT_SM_Read, |
|
745 | ren => MEM_OUT_SM_Read, | |
742 | rdata => MEM_OUT_SM_Data_out, |
|
746 | rdata => MEM_OUT_SM_Data_out, | |
743 |
|
747 | |||
744 | full => MEM_OUT_SM_Full, |
|
748 | full => MEM_OUT_SM_Full, | |
745 | empty => MEM_OUT_SM_Empty); |
|
749 | empty => MEM_OUT_SM_Empty); | |
746 | ----------------------------------------------------------------------------- |
|
750 | ----------------------------------------------------------------------------- | |
747 | Head0 : HeaderBuilder |
|
751 | Head0 : HeaderBuilder | |
748 | GENERIC MAP ( |
|
752 | GENERIC MAP ( | |
749 | Data_sz => 32) |
|
753 | Data_sz => 32) | |
750 | PORT MAP ( |
|
754 | PORT MAP ( | |
751 | clkm => clk, |
|
755 | clkm => clk, | |
752 | rstn => rstn, |
|
756 | rstn => rstn, | |
753 |
|
757 | |||
754 | Statu => HEAD_SM_Param, |
|
758 | Statu => HEAD_SM_Param, | |
755 | Matrix_Type => HEAD_WorkFreq, -- TODO IN |
|
759 | Matrix_Type => HEAD_WorkFreq, -- TODO IN | |
756 | Matrix_Write => HEAD_SM_Wen, |
|
760 | Matrix_Write => HEAD_SM_Wen, | |
757 | Valid => HEAD_Valid, |
|
761 | Valid => HEAD_Valid, | |
758 |
|
762 | |||
759 | dataIN => MEM_OUT_SM_Data_out, |
|
763 | dataIN => MEM_OUT_SM_Data_out, | |
760 | emptyIN => MEM_OUT_SM_Empty, |
|
764 | emptyIN => MEM_OUT_SM_Empty, | |
761 | RenOUT => MEM_OUT_SM_Read, |
|
765 | RenOUT => MEM_OUT_SM_Read, | |
762 |
|
766 | |||
763 | dataOUT => HEAD_Data, |
|
767 | dataOUT => HEAD_Data, | |
764 | emptyOUT => HEAD_Empty, |
|
768 | emptyOUT => HEAD_Empty, | |
765 | RenIN => HEAD_Read, |
|
769 | RenIN => HEAD_Read, | |
766 |
|
770 | |||
767 | header => DMA_Header, |
|
771 | header => DMA_Header, | |
768 | header_val => DMA_Header_Val, |
|
772 | header_val => DMA_Header_Val, | |
769 | header_ack => DMA_Header_Ack); |
|
773 | header_ack => DMA_Header_Ack); | |
770 | ----------------------------------------------------------------------------- |
|
774 | ----------------------------------------------------------------------------- | |
771 | ----------------------------------------------------------------------------- |
|
775 | ----------------------------------------------------------------------------- | |
772 | lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma |
|
776 | lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma | |
773 | PORT MAP ( |
|
777 | PORT MAP ( | |
774 | HCLK => clk, |
|
778 | HCLK => clk, | |
775 | HRESETn => rstn, |
|
779 | HRESETn => rstn, | |
776 |
|
780 | |||
777 | data_time => dma_time, |
|
781 | data_time => dma_time, | |
778 |
|
782 | |||
779 | fifo_data => HEAD_Data, |
|
783 | fifo_data => HEAD_Data, | |
780 | fifo_empty => HEAD_Empty, |
|
784 | fifo_empty => HEAD_Empty, | |
781 | fifo_ren => HEAD_Read, |
|
785 | fifo_ren => HEAD_Read, | |
782 |
|
786 | |||
783 | header => DMA_Header, |
|
787 | header => DMA_Header, | |
784 | header_val => DMA_Header_Val, |
|
788 | header_val => DMA_Header_Val, | |
785 | header_ack => DMA_Header_Ack, |
|
789 | header_ack => DMA_Header_Ack, | |
786 |
|
790 | |||
787 | dma_addr => dma_addr, |
|
791 | dma_addr => dma_addr, | |
788 | dma_data => dma_data, |
|
792 | dma_data => dma_data, | |
789 | dma_valid => dma_valid, |
|
793 | dma_valid => dma_valid, | |
790 | dma_valid_burst => dma_valid_burst, |
|
794 | dma_valid_burst => dma_valid_burst, | |
791 | dma_ren => dma_ren, |
|
795 | dma_ren => dma_ren, | |
792 | dma_done => dma_done, |
|
796 | dma_done => dma_done, | |
793 |
|
797 | |||
794 | ready_matrix_f0_0 => ready_matrix_f0_0, |
|
798 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
795 | ready_matrix_f0_1 => ready_matrix_f0_1, |
|
799 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
796 | ready_matrix_f1 => ready_matrix_f1, |
|
800 | ready_matrix_f1 => ready_matrix_f1, | |
797 | ready_matrix_f2 => ready_matrix_f2, |
|
801 | ready_matrix_f2 => ready_matrix_f2, | |
798 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
802 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
799 | error_bad_component_error => error_bad_component_error, |
|
803 | error_bad_component_error => error_bad_component_error, | |
800 | debug_reg => debug_reg, |
|
804 | debug_reg => debug_reg, | |
801 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
|
805 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
802 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
806 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
803 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
807 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
804 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
808 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
805 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
809 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
806 | status_error_bad_component_error => status_error_bad_component_error, |
|
810 | status_error_bad_component_error => status_error_bad_component_error, | |
807 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
811 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
808 | config_active_interruption_onError => config_active_interruption_onError, |
|
812 | config_active_interruption_onError => config_active_interruption_onError, | |
809 | addr_matrix_f0_0 => addr_matrix_f0_0, |
|
813 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
810 | addr_matrix_f0_1 => addr_matrix_f0_1, |
|
814 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
811 | addr_matrix_f1 => addr_matrix_f1, |
|
815 | addr_matrix_f1 => addr_matrix_f1, | |
812 | addr_matrix_f2 => addr_matrix_f2, |
|
816 | addr_matrix_f2 => addr_matrix_f2, | |
813 |
|
817 | |||
814 | matrix_time_f0_0 => matrix_time_f0_0, |
|
818 | matrix_time_f0_0 => matrix_time_f0_0, | |
815 | matrix_time_f0_1 => matrix_time_f0_1, |
|
819 | matrix_time_f0_1 => matrix_time_f0_1, | |
816 | matrix_time_f1 => matrix_time_f1, |
|
820 | matrix_time_f1 => matrix_time_f1, | |
817 | matrix_time_f2 => matrix_time_f2 |
|
821 | matrix_time_f2 => matrix_time_f2 | |
818 | ); |
|
822 | ); | |
819 | ----------------------------------------------------------------------------- |
|
823 | ----------------------------------------------------------------------------- | |
820 |
|
824 | |||
821 | ----------------------------------------------------------------------------- |
|
825 | ----------------------------------------------------------------------------- | |
822 | ----------------------------------------------------------------------------- |
|
826 | ----------------------------------------------------------------------------- | |
823 | ----------------------------------------------------------------------------- |
|
827 | ----------------------------------------------------------------------------- | |
824 | ----------------------------------------------------------------------------- |
|
828 | ----------------------------------------------------------------------------- | |
825 | ----------------------------------------------------------------------------- |
|
829 | ----------------------------------------------------------------------------- | |
826 | ----------------------------------------------------------------------------- |
|
830 | ----------------------------------------------------------------------------- | |
827 |
|
831 | |||
828 |
|
832 | |||
829 |
|
833 | |||
830 |
|
834 | |||
831 |
|
835 | |||
832 |
|
836 | |||
833 | ----------------------------------------------------------------------------- |
|
837 | ----------------------------------------------------------------------------- | |
834 | -- TIME MANAGMENT |
|
838 | -- TIME MANAGMENT | |
835 | ----------------------------------------------------------------------------- |
|
839 | ----------------------------------------------------------------------------- | |
836 | all_time <= coarse_time & fine_time; |
|
840 | all_time <= coarse_time & fine_time; | |
837 | -- |
|
841 | -- | |
838 | time_update_f0_A <= '0' WHEN sample_f0_A_wen = "11111" ELSE |
|
842 | time_update_f0_A <= '0' WHEN sample_f0_A_wen = "11111" ELSE | |
839 | '1' WHEN sample_f0_A_empty = "11111" ELSE |
|
843 | '1' WHEN sample_f0_A_empty = "11111" ELSE | |
840 | '0'; |
|
844 | '0'; | |
841 |
|
845 | |||
842 | s_m_t_m_f0_A : spectral_matrix_time_managment |
|
846 | s_m_t_m_f0_A : spectral_matrix_time_managment | |
843 | PORT MAP ( |
|
847 | PORT MAP ( | |
844 | clk => clk, |
|
848 | clk => clk, | |
845 | rstn => rstn, |
|
849 | rstn => rstn, | |
846 | time_in => all_time, |
|
850 | time_in => all_time, | |
847 | update_1 => time_update_f0_A, |
|
851 | update_1 => time_update_f0_A, | |
848 | time_out => time_reg_f0_A); |
|
852 | time_out => time_reg_f0_A); | |
849 |
|
853 | |||
850 | -- |
|
854 | -- | |
851 | time_update_f0_B <= '0' WHEN sample_f0_B_wen = "11111" ELSE |
|
855 | time_update_f0_B <= '0' WHEN sample_f0_B_wen = "11111" ELSE | |
852 | '1' WHEN sample_f0_B_empty = "11111" ELSE |
|
856 | '1' WHEN sample_f0_B_empty = "11111" ELSE | |
853 | '0'; |
|
857 | '0'; | |
854 |
|
858 | |||
855 | s_m_t_m_f0_B : spectral_matrix_time_managment |
|
859 | s_m_t_m_f0_B : spectral_matrix_time_managment | |
856 | PORT MAP ( |
|
860 | PORT MAP ( | |
857 | clk => clk, |
|
861 | clk => clk, | |
858 | rstn => rstn, |
|
862 | rstn => rstn, | |
859 | time_in => all_time, |
|
863 | time_in => all_time, | |
860 | update_1 => time_update_f0_B, |
|
864 | update_1 => time_update_f0_B, | |
861 | time_out => time_reg_f0_B); |
|
865 | time_out => time_reg_f0_B); | |
862 |
|
866 | |||
863 | -- |
|
867 | -- | |
864 | time_update_f1 <= '0' WHEN sample_f1_wen = "11111" ELSE |
|
868 | time_update_f1 <= '0' WHEN sample_f1_wen = "11111" ELSE | |
865 | '1' WHEN sample_f1_empty = "11111" ELSE |
|
869 | '1' WHEN sample_f1_empty = "11111" ELSE | |
866 | '0'; |
|
870 | '0'; | |
867 |
|
871 | |||
868 | s_m_t_m_f1 : spectral_matrix_time_managment |
|
872 | s_m_t_m_f1 : spectral_matrix_time_managment | |
869 | PORT MAP ( |
|
873 | PORT MAP ( | |
870 | clk => clk, |
|
874 | clk => clk, | |
871 | rstn => rstn, |
|
875 | rstn => rstn, | |
872 | time_in => all_time, |
|
876 | time_in => all_time, | |
873 | update_1 => time_update_f1, |
|
877 | update_1 => time_update_f1, | |
874 | time_out => time_reg_f1); |
|
878 | time_out => time_reg_f1); | |
875 |
|
879 | |||
876 | -- |
|
880 | -- | |
877 | time_update_f2 <= '0' WHEN sample_f2_wen = "11111" ELSE |
|
881 | time_update_f2 <= '0' WHEN sample_f2_wen = "11111" ELSE | |
878 | '1' WHEN sample_f2_empty = "11111" ELSE |
|
882 | '1' WHEN sample_f2_empty = "11111" ELSE | |
879 | '0'; |
|
883 | '0'; | |
880 |
|
884 | |||
881 | s_m_t_m_f2 : spectral_matrix_time_managment |
|
885 | s_m_t_m_f2 : spectral_matrix_time_managment | |
882 | PORT MAP ( |
|
886 | PORT MAP ( | |
883 | clk => clk, |
|
887 | clk => clk, | |
884 | rstn => rstn, |
|
888 | rstn => rstn, | |
885 | time_in => all_time, |
|
889 | time_in => all_time, | |
886 | update_1 => time_update_f2, |
|
890 | update_1 => time_update_f2, | |
887 | time_out => time_reg_f2); |
|
891 | time_out => time_reg_f2); | |
888 |
|
892 | |||
889 | ----------------------------------------------------------------------------- |
|
893 | ----------------------------------------------------------------------------- | |
890 | dma_time <= (OTHERS => '0'); -- TODO |
|
894 | dma_time <= (OTHERS => '0'); -- TODO | |
891 | ----------------------------------------------------------------------------- |
|
895 | ----------------------------------------------------------------------------- | |
892 |
|
896 | |||
893 |
|
897 | |||
894 |
|
898 | |||
895 | END Behavioral; |
|
899 | END Behavioral; |
@@ -1,220 +1,220 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | -- jean-christophe.pellion@easii-ic.com |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
22 | ---------------------------------------------------------------------------- |
|
22 | ---------------------------------------------------------------------------- | |
23 | LIBRARY ieee; |
|
23 | LIBRARY ieee; | |
24 | USE ieee.std_logic_1164.ALL; |
|
24 | USE ieee.std_logic_1164.ALL; | |
25 | LIBRARY grlib; |
|
25 | LIBRARY grlib; | |
26 | USE grlib.amba.ALL; |
|
26 | USE grlib.amba.ALL; | |
27 | USE std.textio.ALL; |
|
27 | USE std.textio.ALL; | |
28 | LIBRARY grlib; |
|
28 | LIBRARY grlib; | |
29 | USE grlib.amba.ALL; |
|
29 | USE grlib.amba.ALL; | |
30 | USE grlib.stdlib.ALL; |
|
30 | USE grlib.stdlib.ALL; | |
31 | USE GRLIB.DMA2AHB_Package.ALL; |
|
31 | USE GRLIB.DMA2AHB_Package.ALL; | |
32 | LIBRARY techmap; |
|
32 | LIBRARY techmap; | |
33 | USE techmap.gencomp.ALL; |
|
33 | USE techmap.gencomp.ALL; | |
34 | LIBRARY lpp; |
|
34 | --LIBRARY lpp; | |
35 | USE lpp.lpp_amba.ALL; |
|
35 | --USE lpp.lpp_amba.ALL; | |
36 | USE lpp.apb_devices_list.ALL; |
|
36 | --USE lpp.apb_devices_list.ALL; | |
37 | USE lpp.lpp_memory.ALL; |
|
37 | --USE lpp.lpp_memory.ALL; | |
38 |
|
38 | |||
39 | PACKAGE lpp_dma_pkg IS |
|
39 | PACKAGE lpp_dma_pkg IS | |
40 |
|
40 | |||
41 | COMPONENT lpp_dma |
|
41 | COMPONENT lpp_dma | |
42 | GENERIC ( |
|
42 | GENERIC ( | |
43 | tech : INTEGER; |
|
43 | tech : INTEGER; | |
44 | hindex : INTEGER; |
|
44 | hindex : INTEGER; | |
45 | pindex : INTEGER; |
|
45 | pindex : INTEGER; | |
46 | paddr : INTEGER; |
|
46 | paddr : INTEGER; | |
47 | pmask : INTEGER; |
|
47 | pmask : INTEGER; | |
48 | pirq : INTEGER); |
|
48 | pirq : INTEGER); | |
49 | PORT ( |
|
49 | PORT ( | |
50 | HCLK : IN STD_ULOGIC; |
|
50 | HCLK : IN STD_ULOGIC; | |
51 | HRESETn : IN STD_ULOGIC; |
|
51 | HRESETn : IN STD_ULOGIC; | |
52 | apbi : IN apb_slv_in_type; |
|
52 | apbi : IN apb_slv_in_type; | |
53 | apbo : OUT apb_slv_out_type; |
|
53 | apbo : OUT apb_slv_out_type; | |
54 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
54 | AHB_Master_In : IN AHB_Mst_In_Type; | |
55 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
55 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
56 | -- fifo interface |
|
56 | -- fifo interface | |
57 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
57 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
58 | fifo_empty : IN STD_LOGIC; |
|
58 | fifo_empty : IN STD_LOGIC; | |
59 | fifo_ren : OUT STD_LOGIC; |
|
59 | fifo_ren : OUT STD_LOGIC; | |
60 | -- header |
|
60 | -- header | |
61 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
61 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
62 | header_val : IN STD_LOGIC; |
|
62 | header_val : IN STD_LOGIC; | |
63 | header_ack : OUT STD_LOGIC); |
|
63 | header_ack : OUT STD_LOGIC); | |
64 | END COMPONENT; |
|
64 | END COMPONENT; | |
65 |
|
65 | |||
66 | COMPONENT fifo_test_dma |
|
66 | COMPONENT fifo_test_dma | |
67 | GENERIC ( |
|
67 | GENERIC ( | |
68 | tech : INTEGER; |
|
68 | tech : INTEGER; | |
69 | pindex : INTEGER; |
|
69 | pindex : INTEGER; | |
70 | paddr : INTEGER; |
|
70 | paddr : INTEGER; | |
71 | pmask : INTEGER); |
|
71 | pmask : INTEGER); | |
72 | PORT ( |
|
72 | PORT ( | |
73 | HCLK : IN STD_ULOGIC; |
|
73 | HCLK : IN STD_ULOGIC; | |
74 | HRESETn : IN STD_ULOGIC; |
|
74 | HRESETn : IN STD_ULOGIC; | |
75 | apbi : IN apb_slv_in_type; |
|
75 | apbi : IN apb_slv_in_type; | |
76 | apbo : OUT apb_slv_out_type; |
|
76 | apbo : OUT apb_slv_out_type; | |
77 | -- fifo interface |
|
77 | -- fifo interface | |
78 | fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
78 | fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
79 | fifo_empty : OUT STD_LOGIC; |
|
79 | fifo_empty : OUT STD_LOGIC; | |
80 | fifo_ren : IN STD_LOGIC; |
|
80 | fifo_ren : IN STD_LOGIC; | |
81 | -- header |
|
81 | -- header | |
82 | header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
82 | header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
83 | header_val : OUT STD_LOGIC; |
|
83 | header_val : OUT STD_LOGIC; | |
84 | header_ack : IN STD_LOGIC |
|
84 | header_ack : IN STD_LOGIC | |
85 | ); |
|
85 | ); | |
86 | END COMPONENT; |
|
86 | END COMPONENT; | |
87 |
|
87 | |||
88 | COMPONENT lpp_dma_apbreg |
|
88 | COMPONENT lpp_dma_apbreg | |
89 | GENERIC ( |
|
89 | GENERIC ( | |
90 | pindex : INTEGER; |
|
90 | pindex : INTEGER; | |
91 | paddr : INTEGER; |
|
91 | paddr : INTEGER; | |
92 | pmask : INTEGER; |
|
92 | pmask : INTEGER; | |
93 | pirq : INTEGER); |
|
93 | pirq : INTEGER); | |
94 | PORT ( |
|
94 | PORT ( | |
95 | HCLK : IN STD_ULOGIC; |
|
95 | HCLK : IN STD_ULOGIC; | |
96 | HRESETn : IN STD_ULOGIC; |
|
96 | HRESETn : IN STD_ULOGIC; | |
97 | apbi : IN apb_slv_in_type; |
|
97 | apbi : IN apb_slv_in_type; | |
98 | apbo : OUT apb_slv_out_type; |
|
98 | apbo : OUT apb_slv_out_type; | |
99 | -- IN |
|
99 | -- IN | |
100 | ready_matrix_f0_0 : IN STD_LOGIC; |
|
100 | ready_matrix_f0_0 : IN STD_LOGIC; | |
101 | ready_matrix_f0_1 : IN STD_LOGIC; |
|
101 | ready_matrix_f0_1 : IN STD_LOGIC; | |
102 | ready_matrix_f1 : IN STD_LOGIC; |
|
102 | ready_matrix_f1 : IN STD_LOGIC; | |
103 | ready_matrix_f2 : IN STD_LOGIC; |
|
103 | ready_matrix_f2 : IN STD_LOGIC; | |
104 | error_anticipating_empty_fifo : IN STD_LOGIC; |
|
104 | error_anticipating_empty_fifo : IN STD_LOGIC; | |
105 | error_bad_component_error : IN STD_LOGIC; |
|
105 | error_bad_component_error : IN STD_LOGIC; | |
106 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
106 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
107 |
|
107 | |||
108 | -- OUT |
|
108 | -- OUT | |
109 | status_ready_matrix_f0_0 : OUT STD_LOGIC; |
|
109 | status_ready_matrix_f0_0 : OUT STD_LOGIC; | |
110 | status_ready_matrix_f0_1 : OUT STD_LOGIC; |
|
110 | status_ready_matrix_f0_1 : OUT STD_LOGIC; | |
111 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
111 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
112 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
112 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
113 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
113 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; | |
114 | status_error_bad_component_error : OUT STD_LOGIC; |
|
114 | status_error_bad_component_error : OUT STD_LOGIC; | |
115 |
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115 | |||
116 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
116 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
117 | config_active_interruption_onError : OUT STD_LOGIC; |
|
117 | config_active_interruption_onError : OUT STD_LOGIC; | |
118 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
118 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
119 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
119 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
120 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
120 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
121 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
121 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
122 | ); |
|
122 | ); | |
123 | END COMPONENT; |
|
123 | END COMPONENT; | |
124 |
|
124 | |||
125 | COMPONENT lpp_dma_send_1word |
|
125 | COMPONENT lpp_dma_send_1word | |
126 | PORT ( |
|
126 | PORT ( | |
127 | HCLK : IN STD_ULOGIC; |
|
127 | HCLK : IN STD_ULOGIC; | |
128 | HRESETn : IN STD_ULOGIC; |
|
128 | HRESETn : IN STD_ULOGIC; | |
129 | DMAIn : OUT DMA_In_Type; |
|
129 | DMAIn : OUT DMA_In_Type; | |
130 | DMAOut : IN DMA_OUt_Type; |
|
130 | DMAOut : IN DMA_OUt_Type; | |
131 | send : IN STD_LOGIC; |
|
131 | send : IN STD_LOGIC; | |
132 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
132 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
133 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
133 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
134 | ren : OUT STD_LOGIC; |
|
134 | ren : OUT STD_LOGIC; | |
135 | send_ok : OUT STD_LOGIC; |
|
135 | send_ok : OUT STD_LOGIC; | |
136 | send_ko : OUT STD_LOGIC); |
|
136 | send_ko : OUT STD_LOGIC); | |
137 | END COMPONENT; |
|
137 | END COMPONENT; | |
138 |
|
138 | |||
139 | COMPONENT lpp_dma_send_16word |
|
139 | COMPONENT lpp_dma_send_16word | |
140 | PORT ( |
|
140 | PORT ( | |
141 | HCLK : IN STD_ULOGIC; |
|
141 | HCLK : IN STD_ULOGIC; | |
142 | HRESETn : IN STD_ULOGIC; |
|
142 | HRESETn : IN STD_ULOGIC; | |
143 | DMAIn : OUT DMA_In_Type; |
|
143 | DMAIn : OUT DMA_In_Type; | |
144 | DMAOut : IN DMA_OUt_Type; |
|
144 | DMAOut : IN DMA_OUt_Type; | |
145 | send : IN STD_LOGIC; |
|
145 | send : IN STD_LOGIC; | |
146 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
146 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
147 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
147 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
148 | ren : OUT STD_LOGIC; |
|
148 | ren : OUT STD_LOGIC; | |
149 | send_ok : OUT STD_LOGIC; |
|
149 | send_ok : OUT STD_LOGIC; | |
150 | send_ko : OUT STD_LOGIC); |
|
150 | send_ko : OUT STD_LOGIC); | |
151 | END COMPONENT; |
|
151 | END COMPONENT; | |
152 |
|
152 | |||
153 | COMPONENT fifo_latency_correction |
|
153 | COMPONENT fifo_latency_correction | |
154 | PORT ( |
|
154 | PORT ( | |
155 | HCLK : IN STD_ULOGIC; |
|
155 | HCLK : IN STD_ULOGIC; | |
156 | HRESETn : IN STD_ULOGIC; |
|
156 | HRESETn : IN STD_ULOGIC; | |
157 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
157 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
158 | fifo_empty : IN STD_LOGIC; |
|
158 | fifo_empty : IN STD_LOGIC; | |
159 | fifo_ren : OUT STD_LOGIC; |
|
159 | fifo_ren : OUT STD_LOGIC; | |
160 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
160 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
161 | dma_empty : OUT STD_LOGIC; |
|
161 | dma_empty : OUT STD_LOGIC; | |
162 | dma_ren : IN STD_LOGIC); |
|
162 | dma_ren : IN STD_LOGIC); | |
163 | END COMPONENT; |
|
163 | END COMPONENT; | |
164 |
|
164 | |||
165 | COMPONENT lpp_dma_ip |
|
165 | COMPONENT lpp_dma_ip | |
166 | GENERIC ( |
|
166 | GENERIC ( | |
167 | tech : INTEGER; |
|
167 | tech : INTEGER; | |
168 | hindex : INTEGER); |
|
168 | hindex : INTEGER); | |
169 | PORT ( |
|
169 | PORT ( | |
170 | HCLK : IN STD_ULOGIC; |
|
170 | HCLK : IN STD_ULOGIC; | |
171 | HRESETn : IN STD_ULOGIC; |
|
171 | HRESETn : IN STD_ULOGIC; | |
172 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
172 | AHB_Master_In : IN AHB_Mst_In_Type; | |
173 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
173 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
174 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
174 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
175 | fifo_empty : IN STD_LOGIC; |
|
175 | fifo_empty : IN STD_LOGIC; | |
176 | fifo_ren : OUT STD_LOGIC; |
|
176 | fifo_ren : OUT STD_LOGIC; | |
177 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
177 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
178 | header_val : IN STD_LOGIC; |
|
178 | header_val : IN STD_LOGIC; | |
179 | header_ack : OUT STD_LOGIC; |
|
179 | header_ack : OUT STD_LOGIC; | |
180 | ready_matrix_f0_0 : OUT STD_LOGIC; |
|
180 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
181 | ready_matrix_f0_1 : OUT STD_LOGIC; |
|
181 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
182 | ready_matrix_f1 : OUT STD_LOGIC; |
|
182 | ready_matrix_f1 : OUT STD_LOGIC; | |
183 | ready_matrix_f2 : OUT STD_LOGIC; |
|
183 | ready_matrix_f2 : OUT STD_LOGIC; | |
184 | error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
184 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
185 | error_bad_component_error : OUT STD_LOGIC; |
|
185 | error_bad_component_error : OUT STD_LOGIC; | |
186 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
186 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
187 | status_ready_matrix_f0_0 : IN STD_LOGIC; |
|
187 | status_ready_matrix_f0_0 : IN STD_LOGIC; | |
188 | status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
188 | status_ready_matrix_f0_1 : IN STD_LOGIC; | |
189 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
189 | status_ready_matrix_f1 : IN STD_LOGIC; | |
190 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
190 | status_ready_matrix_f2 : IN STD_LOGIC; | |
191 | status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
191 | status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
192 | status_error_bad_component_error : IN STD_LOGIC; |
|
192 | status_error_bad_component_error : IN STD_LOGIC; | |
193 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
193 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
194 | config_active_interruption_onError : IN STD_LOGIC; |
|
194 | config_active_interruption_onError : IN STD_LOGIC; | |
195 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
195 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
196 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
196 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
197 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
197 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
198 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
198 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
199 | END COMPONENT; |
|
199 | END COMPONENT; | |
200 |
|
200 | |||
201 | COMPONENT lpp_dma_singleOrBurst |
|
201 | COMPONENT lpp_dma_singleOrBurst | |
202 | GENERIC ( |
|
202 | GENERIC ( | |
203 | tech : INTEGER; |
|
203 | tech : INTEGER; | |
204 | hindex : INTEGER); |
|
204 | hindex : INTEGER); | |
205 | PORT ( |
|
205 | PORT ( | |
206 | HCLK : IN STD_ULOGIC; |
|
206 | HCLK : IN STD_ULOGIC; | |
207 | HRESETn : IN STD_ULOGIC; |
|
207 | HRESETn : IN STD_ULOGIC; | |
208 | run : IN STD_LOGIC; |
|
208 | run : IN STD_LOGIC; | |
209 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
209 | AHB_Master_In : IN AHB_Mst_In_Type; | |
210 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
210 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
211 | send : IN STD_LOGIC; |
|
211 | send : IN STD_LOGIC; | |
212 | valid_burst : IN STD_LOGIC; |
|
212 | valid_burst : IN STD_LOGIC; | |
213 | done : OUT STD_LOGIC; |
|
213 | done : OUT STD_LOGIC; | |
214 | ren : OUT STD_LOGIC; |
|
214 | ren : OUT STD_LOGIC; | |
215 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
215 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
216 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
216 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
217 | debug_dmaout_okay : OUT STD_LOGIC); |
|
217 | debug_dmaout_okay : OUT STD_LOGIC); | |
218 | END COMPONENT; |
|
218 | END COMPONENT; | |
219 |
|
219 | |||
220 | END; |
|
220 | END; |
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