##// END OF EJS Templates
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r455:dd974e065c5c JC
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@@ -73,7 +73,7 BEGIN -- beh
73 counter_downsampler <= counter_downsampler + 1;
73 counter_downsampler <= counter_downsampler + 1;
74 END IF;
74 END IF;
75
75
76 IF counter_downsampler = 0 THEN
76 IF counter_downsampler = R_downsampling_decimation_factor-1 THEN
77 data_out_valid <= '1';
77 data_out_valid <= '1';
78 data_out <= data_in;
78 data_out <= data_in;
79 END IF;
79 END IF;
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@@ -56,17 +56,18 BEGIN -- beh
56
56
57 data_add <= STD_LOGIC_VECTOR(resize(SIGNED(data_in)+SIGNED(data_reg),b_data_size));
57 data_add <= STD_LOGIC_VECTOR(resize(SIGNED(data_in)+SIGNED(data_reg),b_data_size));
58
58
59 data_out_valid <= data_in_valid;
60
59 PROCESS (clk, rstn)
61 PROCESS (clk, rstn)
60 BEGIN -- PROCESS
62 BEGIN -- PROCESS
61 IF rstn = '0' THEN -- asynchronous reset (active low)
63 IF rstn = '0' THEN -- asynchronous reset (active low)
62 data_reg <= (OTHERS => '0');
64 data_reg <= (OTHERS => '0');
63 data_out_valid <= '0';
65 --data_out_valid <= '0';
64 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
66 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
65 IF run = '0' THEN
67 IF run = '0' THEN
66 data_reg <= (OTHERS => '0');
68 data_reg <= (OTHERS => '0');
67 data_out_valid <= '0';
69 --data_out_valid <= '0';
68 ELSE
70 ELSE
69 data_out_valid <= data_in_valid;
70 IF data_in_valid = '1' THEN
71 IF data_in_valid = '1' THEN
71 data_reg <= data_add;
72 data_reg <= data_add;
72 END IF;
73 END IF;
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@@ -58,11 +58,11 ARCHITECTURE beh OF cic_lfr IS
58 --
58 --
59 CONSTANT S_parameter : INTEGER := 2;
59 CONSTANT S_parameter : INTEGER := 2;
60 --
60 --
61 SIGNAL sel_sample : STD_LOGIC_VECTOR(2 DOWNTO 0);
61 SIGNAL sel_sample : STD_LOGIC_VECTOR(3 DOWNTO 0);
62 SIGNAL sample_temp : sample_vector(5 DOWNTO 0,15 DOWNTO 0);
62 SIGNAL sample_temp : sample_vector(6 DOWNTO 0,15 DOWNTO 0);
63 SIGNAL sample : STD_LOGIC_VECTOR(15 DOWNTO 0);
63 SIGNAL sample : STD_LOGIC_VECTOR(15 DOWNTO 0);
64
64
65 SIGNAL OPERATION : STD_LOGIC_VECTOR(14 DOWNTO 0);
65 SIGNAL OPERATION : STD_LOGIC_VECTOR(15 DOWNTO 0);
66
66
67 -- ALU
67 -- ALU
68 SIGNAL data_in_A : STD_LOGIC_VECTOR(15 DOWNTO 0);
68 SIGNAL data_in_A : STD_LOGIC_VECTOR(15 DOWNTO 0);
@@ -80,34 +80,65 ARCHITECTURE beh OF cic_lfr IS
80 SIGNAL addr_gen: STD_LOGIC_VECTOR(7 DOWNTO 0);
80 SIGNAL addr_gen: STD_LOGIC_VECTOR(7 DOWNTO 0);
81 SIGNAL addr_read: STD_LOGIC_VECTOR(7 DOWNTO 0);
81 SIGNAL addr_read: STD_LOGIC_VECTOR(7 DOWNTO 0);
82 SIGNAL addr_write: STD_LOGIC_VECTOR(7 DOWNTO 0);
82 SIGNAL addr_write: STD_LOGIC_VECTOR(7 DOWNTO 0);
83 SIGNAL addr_write_s: STD_LOGIC_VECTOR(7 DOWNTO 0);
83 SIGNAL data_we: STD_LOGIC;
84 SIGNAL data_we: STD_LOGIC;
85 SIGNAL data_we_s: STD_LOGIC;
84 SIGNAL data_wen : STD_LOGIC;
86 SIGNAL data_wen : STD_LOGIC;
85 SIGNAL data_write : STD_LOGIC_VECTOR(15 DOWNTO 0);
87 SIGNAL data_write : STD_LOGIC_VECTOR(15 DOWNTO 0);
86 SIGNAL data_read : STD_LOGIC_VECTOR(15 DOWNTO 0);
88 SIGNAL data_read : STD_LOGIC_VECTOR(15 DOWNTO 0);
89 SIGNAL data_read_pre : STD_LOGIC_VECTOR(15 DOWNTO 0);
87 -----------------------------------------------------------------------------
90 -----------------------------------------------------------------------------
88 SIGNAL sample_out_reg16 : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
91 SIGNAL sample_out_reg16 : sample_vector(6*2-1 DOWNTO 0, 15 DOWNTO 0);
89 SIGNAL sample_out_reg256 : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
92 SIGNAL sample_out_reg256 : sample_vector(6*3-1 DOWNTO 0, 15 DOWNTO 0);
90 SIGNAL sample_valid_reg16 : STD_LOGIC_VECTOR(6 DOWNTO 0);
93 SIGNAL sample_valid_reg16 : STD_LOGIC_VECTOR(6*2 DOWNTO 0);
91 SIGNAL sample_valid_reg256: STD_LOGIC_VECTOR(6 DOWNTO 0);
94 SIGNAL sample_valid_reg256: STD_LOGIC_VECTOR(6*3 DOWNTO 0);
92 SIGNAL data_out_16_valid_s : STD_LOGIC;
95 SIGNAL data_out_16_valid_s : STD_LOGIC;
93 SIGNAL data_out_256_valid_s : STD_LOGIC;
96 SIGNAL data_out_256_valid_s : STD_LOGIC;
94
97 SIGNAL data_out_16_valid_s2 : STD_LOGIC;
98 SIGNAL data_out_256_valid_s2 : STD_LOGIC;
99 -----------------------------------------------------------------------------
100 SIGNAL sample_out_reg16_s : sample_vector(5 DOWNTO 0, 16*2-1 DOWNTO 0);
101 SIGNAL sample_out_reg256_s : sample_vector(5 DOWNTO 0, 16*3-1 DOWNTO 0);
102 -----------------------------------------------------------------------------
103 SIGNAL ALU_OP : STD_LOGIC_VECTOR(1 DOWNTO 0);
104
105
95 BEGIN
106 BEGIN
96
107 -----------------------------------------------------------------------------
108 --
109 -----------------------------------------------------------------------------
110 PROCESS (clk, rstn)
111 BEGIN -- PROCESS
112 IF rstn = '0' THEN -- asynchronous reset (active low)
113 data_read_pre <= (OTHERS => '0');
114 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
115 data_read_pre <= data_read;
116 END IF;
117 END PROCESS;
118
97 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
98 -- SEL_SAMPLE
120 -- SEL_SAMPLE
99 -----------------------------------------------------------------------------
121 -----------------------------------------------------------------------------
100 sel_sample <= OPERATION(5 DOWNTO 3);
122 PROCESS (clk, rstn)
123 BEGIN -- PROCESS
124 IF rstn = '0' THEN -- asynchronous reset (active low)
125 sel_sample <= (OTHERS => '0');
126 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
127 sel_sample <= OPERATION(15) & OPERATION(5 DOWNTO 3);
128 END IF;
129 END PROCESS;
130
101 all_bit: FOR I IN 15 DOWNTO 0 GENERATE
131 all_bit: FOR I IN 15 DOWNTO 0 GENERATE
102 sample_temp(0,I) <= data_in(0,I) WHEN sel_sample(0) = '0' ELSE data_in(1,I);
132 sample_temp(0,I) <= data_in(0,I) WHEN sel_sample(0) = '0' ELSE data_in(1,I);
103 sample_temp(1,I) <= data_in(2,I) WHEN sel_sample(0) = '0' ELSE data_in(3,I);
133 sample_temp(1,I) <= data_in(2,I) WHEN sel_sample(0) = '0' ELSE data_in(3,I);
104 sample_temp(2,I) <= data_in(4,I) WHEN sel_sample(0) = '0' ELSE data_in(5,I);
134 sample_temp(2,I) <= data_in(4,I) WHEN sel_sample(0) = '0' ELSE data_in(5,I);
105 sample_temp(3,I) <= data_write(I) WHEN sel_sample(0) = '0' ELSE '0';
135 sample_temp(3,I) <= data_write(I) WHEN sel_sample(0) = '0' ELSE data_read_pre(I);
106
136
107 sample_temp(4,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE sample_temp(1,I);
137 sample_temp(4,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE sample_temp(1,I);
108 sample_temp(5,I) <= sample_temp(2,I) WHEN sel_sample(1) = '0' ELSE sample_temp(3,I);
138 sample_temp(5,I) <= sample_temp(2,I) WHEN sel_sample(1) = '0' ELSE sample_temp(3,I);
109
139 sample_temp(6,I) <= sample_temp(4,I) WHEN sel_sample(2) = '0' ELSE sample_temp(5,I);
110 sample(I) <= sample_temp(4,I) WHEN sel_sample(2) = '0' ELSE sample_temp(5,I);
140 sample(I) <= sample_temp(6,I) WHEN sel_sample(3) = '0' ELSE
141 data_in(0,15) WHEN sel_sample(0) = '0' ELSE '0';
111 END GENERATE all_bit;
142 END GENERATE all_bit;
112
143
113 data_in_A <= sample;
144 data_in_A <= sample;
@@ -115,13 +146,23 BEGIN
115 -----------------------------------------------------------------------------
146 -----------------------------------------------------------------------------
116 -- ALU
147 -- ALU
117 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
149 PROCESS (clk, rstn)
150 BEGIN -- PROCESS
151 IF rstn = '0' THEN -- asynchronous reset (active low)
152 ALU_OP <= (OTHERS => '0');
153 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
154 ALU_OP <= OPERATION(1 DOWNTO 0);
155 END IF;
156 END PROCESS;
157
158
118 ALU: cic_lfr_add_sub
159 ALU: cic_lfr_add_sub
119 PORT MAP (
160 PORT MAP (
120 clk => clk,
161 clk => clk,
121 rstn => rstn,
162 rstn => rstn,
122 run => run,
163 run => run,
123
164
124 OP => OPERATION(1 DOWNTO 0),
165 OP => ALU_OP,
125
166
126 data_in_A => sample,
167 data_in_A => sample,
127 data_in_B => data_read,
168 data_in_B => data_read,
@@ -179,9 +220,13 BEGIN
179 IF rstn = '0' THEN -- asynchronous reset (active low)
220 IF rstn = '0' THEN -- asynchronous reset (active low)
180 addr_write <= (OTHERS => '0');
221 addr_write <= (OTHERS => '0');
181 data_we <= '0';
222 data_we <= '0';
223 addr_write_s <= (OTHERS => '0');
224 data_we_s <= '0';
182 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
225 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
183 addr_write <= addr_read;
226 addr_write_s <= addr_read;
184 data_we <= OPERATION(6);
227 data_we_s <= OPERATION(6);
228 addr_write <= addr_write_s;
229 data_we <= data_we_s;
185 END IF;
230 END IF;
186 END PROCESS;
231 END PROCESS;
187
232
@@ -220,60 +265,99 BEGIN
220 data_out_16_valid => data_out_16_valid_s,
265 data_out_16_valid => data_out_16_valid_s,
221 data_out_256_valid => data_out_256_valid_s,
266 data_out_256_valid => data_out_256_valid_s,
222 OPERATION => OPERATION);
267 OPERATION => OPERATION);
268 -----------------------------------------------------------------------------
269 PROCESS (clk, rstn)
270 BEGIN -- PROCESS
271 IF rstn = '0' THEN -- asynchronous reset (active low)
272 data_out_16_valid_s2 <= '0';
273 data_out_256_valid_s2 <= '0';
274 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
275 data_out_16_valid_s2 <= data_out_16_valid_s;
276 data_out_256_valid_s2 <= data_out_256_valid_s;
277 END IF;
278 END PROCESS;
223
279
224 PROCESS (clk, rstn)
280 PROCESS (clk, rstn)
225 BEGIN -- PROCESS
281 BEGIN -- PROCESS
226 IF rstn = '0' THEN -- asynchronous reset (active low)
282 IF rstn = '0' THEN -- asynchronous reset (active low)
227 sample_valid_reg16 <= "0000001";
283 sample_valid_reg16 <= '0' & "000000" & "000001";
228 sample_valid_reg256 <= "0000001";
284 sample_valid_reg256 <= '0' & "000000" & "000000" & "000001";
229 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
285 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
230 IF run = '0' THEN
286 IF run = '0' THEN
231 sample_valid_reg16 <= "0000001";
287 sample_valid_reg16 <= '0' & "000000" & "000001";
232 sample_valid_reg256 <= "0000001";
288 sample_valid_reg256 <= '0' & "000000" & "000000" & "000001";
233 ELSE
289 ELSE
234 IF data_out_16_valid_s = '1' OR sample_valid_reg16(6) = '1' THEN
290 IF data_out_16_valid_s2 = '1' OR sample_valid_reg16(6*2) = '1' THEN
235 sample_valid_reg16 <= sample_valid_reg16(5 DOWNTO 0) & sample_valid_reg16(6);
291 sample_valid_reg16 <= sample_valid_reg16(6*2-1 DOWNTO 0) & sample_valid_reg16(6*2);
236 END IF;
292 END IF;
237 IF data_out_256_valid_s = '1' OR sample_valid_reg256(6) = '1' THEN
293 IF data_out_256_valid_s2 = '1' OR sample_valid_reg256(6*3) = '1' THEN
238 sample_valid_reg256 <= sample_valid_reg256(5 DOWNTO 0) & sample_valid_reg256(6);
294 sample_valid_reg256 <= sample_valid_reg256(6*3-1 DOWNTO 0) & sample_valid_reg256(6*3);
239 END IF;
295 END IF;
240 END IF;
296 END IF;
241 END IF;
297 END IF;
242 END PROCESS;
298 END PROCESS;
243
299
244 data_out_16_valid <= sample_valid_reg16(6);
300 data_out_16_valid <= sample_valid_reg16(6*2);
245 data_out_256_valid <= sample_valid_reg256(6);
301 data_out_256_valid <= sample_valid_reg256(6*3);
246
302
247 -----------------------------------------------------------------------------
303 -----------------------------------------------------------------------------
248 data_out_256 <= sample_out_reg256;
249 data_out_16 <= sample_out_reg16;
250
304
251 all_channel_out: FOR I IN 5 DOWNTO 0 GENERATE
305 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
252 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
306 all_channel_out16: FOR I IN 6*2-1 DOWNTO 0 GENERATE
253
254 PROCESS (clk, rstn)
307 PROCESS (clk, rstn)
255 BEGIN -- PROCESS
308 BEGIN -- PROCESS
256 IF rstn = '0' THEN -- asynchronous reset (active low)
309 IF rstn = '0' THEN -- asynchronous reset (active low)
257 sample_out_reg16(I,J) <= '0';
310 sample_out_reg16(I,J) <= '0';
258 sample_out_reg256(I,J) <= '0';
259 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
311 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
260 IF run = '0' THEN
312 IF run = '0' THEN
261 sample_out_reg16(I,J) <= '0';
313 sample_out_reg16(I,J) <= '0';
314 ELSE
315 IF sample_valid_reg16(I) = '1' AND data_out_16_valid_s2 = '1' THEN
316 sample_out_reg16(I,J) <= data_read(J);
317 END IF;
318 END IF;
319 END IF;
320 END PROCESS;
321 END GENERATE all_channel_out16;
322
323 all_channel_out256: FOR I IN 6*3-1 DOWNTO 0 GENERATE
324 PROCESS (clk, rstn)
325 BEGIN -- PROCESS
326 IF rstn = '0' THEN -- asynchronous reset (active low)
327 sample_out_reg256(I,J) <= '0';
328 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
329 IF run = '0' THEN
262 sample_out_reg256(I,J) <= '0';
330 sample_out_reg256(I,J) <= '0';
263 ELSE
331 ELSE
264 IF sample_valid_reg16(I) = '1' AND data_out_16_valid_s = '1' THEN
332 IF sample_valid_reg256(I) = '1' AND data_out_256_valid_s2 = '1' THEN
265 sample_out_reg16(I,J) <= data_write(J);
333 sample_out_reg256(I,J) <= data_read(J);
266 END IF;
267 IF sample_valid_reg256(I) = '1' AND data_out_256_valid_s = '1' THEN
268 sample_out_reg256(I,J) <= data_write(J);
269 END IF;
334 END IF;
270 END IF;
335 END IF;
271 END IF;
336 END IF;
272 END PROCESS;
337 END PROCESS;
273
338 END GENERATE all_channel_out256;
339 END GENERATE all_bits;
340
341
342 all_channel_out: FOR I IN 5 DOWNTO 0 GENERATE
343 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
344 all_reg_16: FOR K IN 1 DOWNTO 0 GENERATE
345 sample_out_reg16_s(I,J+(K*16)) <= sample_out_reg16(2*I+K,J);
346 END GENERATE all_reg_16;
347 all_reg_256: FOR K IN 2 DOWNTO 0 GENERATE
348 sample_out_reg256_s(I,J+(K*16)) <= sample_out_reg256(3*I+K,J);
349 END GENERATE all_reg_256;
274 END GENERATE all_bits;
350 END GENERATE all_bits;
275 END GENERATE all_channel_out;
351 END GENERATE all_channel_out;
276
352
353 all_channel_out_v: FOR I IN 5 DOWNTO 0 GENERATE
354 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
355 data_out_256(I,J) <= sample_out_reg256_s(I,J);
356
357 END GENERATE all_bits;
358 END GENERATE all_channel_out_v;
359
360 -- data_out_16 <= sample_out_reg16;
277
361
278 END beh;
362 END beh;
279
363
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@@ -32,15 +32,15 USE lpp.data_type_pkg.ALL;
32
32
33 ENTITY cic_lfr_control IS
33 ENTITY cic_lfr_control IS
34 PORT (
34 PORT (
35 clk : IN STD_LOGIC;
35 clk : IN STD_LOGIC;
36 rstn : IN STD_LOGIC;
36 rstn : IN STD_LOGIC;
37 run : IN STD_LOGIC;
37 run : IN STD_LOGIC;
38 --
38 --
39 data_in_valid : IN STD_LOGIC;
39 data_in_valid : IN STD_LOGIC;
40 data_out_16_valid : OUT STD_LOGIC;
40 data_out_16_valid : OUT STD_LOGIC;
41 data_out_256_valid : OUT STD_LOGIC;
41 data_out_256_valid : OUT STD_LOGIC;
42 --
42 --
43 OPERATION : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
43 OPERATION : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
44 );
44 );
45
45
46 END cic_lfr_control;
46 END cic_lfr_control;
@@ -52,55 +52,56 ARCHITECTURE beh OF cic_lfr_control IS
52 RUN_PROG_C16,
52 RUN_PROG_C16,
53 RUN_PROG_C256
53 RUN_PROG_C256
54 );
54 );
55
55
56 SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
56 SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
57
57
58 SIGNAL nb_data_receipt : INTEGER := 0;
58 SIGNAL nb_data_receipt : INTEGER := 0;
59 SIGNAL current_cmd : INTEGER := 0;
59 SIGNAL current_cmd : INTEGER := 0;
60 SIGNAL current_channel : INTEGER := 0;
60 SIGNAL current_channel : INTEGER := 0;
61 SIGNAL sample_16_odd : STD_LOGIC;
61 SIGNAL sample_16_odd : STD_LOGIC;
62 SIGNAL sample_256_odd : STD_LOGIC;
62 SIGNAL sample_256_odd : STD_LOGIC;
63
63
64 TYPE PROGRAM_ARRAY IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(11 DOWNTO 0);
64 TYPE PROGRAM_ARRAY IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(13 DOWNTO 0);
65 --OPERATION( 8 DOWNTO 0) <= PROGRAM_ARRAY( 8 DOWNTO 0) sauf pour PROG_I(0)
65 --OPERATION( 8 DOWNTO 0) <= PROGRAM_ARRAY( 8 DOWNTO 0) sauf pour PROG_I(0)
66 --OPERATION(13 DOWNTO 12) <= PROGRAM_ARRAY(10 DOWNTO 9)
66 --OPERATION(13 DOWNTO 12) <= PROGRAM_ARRAY(10 DOWNTO 9)
67 --OPERATION(11 DOWNTO 9) <= current_channel
67 --OPERATION(11 DOWNTO 9) <= current_channel
68 --OPERATION(14) <= PROGRAM_ARRAY(11) selon sample_X_odd et l'etat
68 --OPERATION(14) <= PROGRAM_ARRAY(11) selon sample_X_odd et l'etat
69 CONSTANT PROG : PROGRAM_ARRAY(0 TO 28) :=
69 CONSTANT PROG : PROGRAM_ARRAY(0 TO 28) :=
70 (
70 (
71 --PROG I
71 -- BA9876 543210
72 "0001"&X"C0", --0
72 --PROG I
73 "0001"&X"70", --1
73 "00"&"000111"&"000000" --C0 --0
74 "0001"&X"70", --2
74 "00"&"000101"&"111000" --78 --1
75 "0001"&X"7A", --3
75 "00"&"000101"&"111000" --78 --2
76 "0001"&X"7A", --4
76 "01"&"000101"&"000010" --42 --3
77 "0001"&X"7A", --5
77 "01"&"000101"&"111010" --7A --4
78 "0001"&X"7A", --6
78 "01"&"000101"&"111010" --7A --5
79 "0001"&X"7A", --7
79 "01"&"000101"&"000010" --42 --6
80 "0001"&X"7A", --8
80 "01"&"000101"&"111010" --7A --7
81 --PROG_C16
81 "01"&"000101"&"111010" --7A --8
82 "0010"&X"38", --9
82 --PROG_C16
83 "1001"&X"71", --10
83 "11"&"001000"&"111000" --38 --9
84 "1001"&X"71", --11
84 "00"&"100101"&"110001" --71 --10
85 "1001"&X"71", --12
85 "00"&"100101"&"110001" --71 --11
86 "0100"&X"38", --13
86 "00"&"100101"&"110001" --71 --12
87 "1001"&X"77", --14
87 "11"&"010000"&"111000" --38 --13
88 "1001"&X"77", --15
88 "00"&"100101"&"111111" --7F --14
89 "1001"&X"77", --16
89 "00"&"100101"&"110111" --77 --15
90 --PROG_C256
90 "00"&"100101"&"110111" --77 --16
91 "0010"&X"38", --17
91 --PROG_C256
92 "1001"&X"71", --18
92 "11"&"001000"&"111000" --38 --17
93 "1001"&X"71", --19
93 "00"&"100101"&"110001" --71 --18
94 "1001"&X"71", --20
94 "00"&"100101"&"110001" --71 --19
95 "0100"&X"38", --21
95 "00"&"100101"&"110001" --71 --20
96 "1001"&X"77", --22
96 "11"&"010000"&"111000" --38 --21
97 "1001"&X"77", --23
97 "00"&"100101"&"111111" --7F --22
98 "1001"&X"77", --24
98 "00"&"100101"&"110111" --77 --23
99 "0110"&X"38", --25
99 "00"&"100101"&"110111" --77 --24
100 "1001"&X"77", --26
100 "11"&"011000"&"111000" --38 --25
101 "1001"&X"77", --27
101 "00"&"100101"&"111111" --7F --26
102 "1001"&X"77" --28
102 "00"&"100101"&"110111" --77 --27
103 );
103 "00"&"100101"&"110111" --77 --28
104 );
104
105
105
106
106 CONSTANT PROG_START_I : INTEGER := 0;
107 CONSTANT PROG_START_I : INTEGER := 0;
@@ -112,33 +113,41 ARCHITECTURE beh OF cic_lfr_control IS
112
113
113 BEGIN
114 BEGIN
114
115
115 OPERATION( 1 DOWNTO 0) <= PROG(current_cmd)( 1 DOWNTO 0);
116 OPERATION(1 DOWNTO 0) <= PROG(current_cmd)(1 DOWNTO 0);
116 OPERATION( 2 ) <= '0' WHEN STATE_CIC_LFR = IDLE ELSE
117 OPERATION(2) <= '0' WHEN STATE_CIC_LFR = IDLE ELSE
117 PROG(current_cmd)( 2 );
118 PROG(current_cmd)(2);
118 OPERATION( 5 DOWNTO 3) <= STD_LOGIC_VECTOR(to_unsigned(current_channel,3)) WHEN STATE_CIC_LFR = RUN_PROG_I AND current_cmd = 0 ELSE
119 OPERATION(5 DOWNTO 3) <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3)) WHEN STATE_CIC_LFR = RUN_PROG_I AND current_cmd = 0 ELSE
119 PROG(current_cmd)(5 DOWNTO 3);
120 PROG(current_cmd)(5 DOWNTO 3);
120 OPERATION( 8 DOWNTO 6) <= "000" WHEN STATE_CIC_LFR = IDLE ELSE
121
121 PROG(current_cmd)( 8 DOWNTO 6);
122 OPERATION(8 DOWNTO 6) <= "000" WHEN STATE_CIC_LFR = IDLE ELSE
122 OPERATION(11 DOWNTO 9) <= STD_LOGIC_VECTOR(to_unsigned(current_channel,3));
123 PROG(current_cmd)(8 DOWNTO 6);
123 OPERATION(13 DOWNTO 12) <= PROG(current_cmd)(10 DOWNTO 9);
124 OPERATION(11 DOWNTO 9) <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3));
124 OPERATION(14) <= PROG(current_cmd)(11) AND sample_16_odd WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE
125 OPERATION(13 DOWNTO 12) <= PROG(current_cmd)(10 DOWNTO 9);
126 OPERATION(14) <= PROG(current_cmd)(11) AND sample_16_odd WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE
125 PROG(current_cmd)(11) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0';
127 PROG(current_cmd)(11) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0';
126
128
129 OPERATION(15) <= PROG(current_cmd)(12);
130
131 data_out_16_valid <= PROG(current_cmd)(13) WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE '0';
132 data_out_256_valid <= PROG(current_cmd)(13) WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0';
133
127 PROCESS (clk, rstn)
134 PROCESS (clk, rstn)
128 BEGIN
135 BEGIN
129 IF rstn = '0' THEN
136 IF rstn = '0' THEN
130 STATE_CIC_LFR <= IDLE;
137 STATE_CIC_LFR <= IDLE;
131 nb_data_receipt <= 0;
138 nb_data_receipt <= 0;
132 current_channel <= 0;
139 current_channel <= 0;
133 current_cmd <= 0;
140 current_cmd <= 0;
134 sample_16_odd <= '0';
141 sample_16_odd <= '0';
135 sample_256_odd <= '0';
142 sample_256_odd <= '0';
136 data_out_16_valid <= '0';
143 -- data_out_16_valid <= '0';
137 data_out_256_valid <= '0';
144 -- data_out_256_valid <= '0';
138
145
139 ELSIF clk'event AND clk = '1' THEN
146 ELSIF clk'EVENT AND clk = '1' THEN
140 data_out_16_valid <= '0';
147
141 data_out_256_valid <= '0';
148 -- data_out_16_valid <= '0';
149 -- data_out_256_valid <= '0';
150
142 CASE STATE_CIC_LFR IS
151 CASE STATE_CIC_LFR IS
143 WHEN IDLE =>
152 WHEN IDLE =>
144 IF data_in_valid = '1' THEN
153 IF data_in_valid = '1' THEN
@@ -150,18 +159,20 BEGIN
150
159
151 WHEN RUN_PROG_I =>
160 WHEN RUN_PROG_I =>
152 IF current_cmd = PROG_END_I THEN
161 IF current_cmd = PROG_END_I THEN
153 IF current_channel = 5 THEN
162 IF nb_data_receipt MOD 16 = 15 THEN
154 current_channel <= 0;
163 STATE_CIC_LFR <= RUN_PROG_C16;
155 IF nb_data_receipt MOD 16 = 0 THEN
164 current_cmd <= PROG_START_C16;
156 STATE_CIC_LFR <= RUN_PROG_C16;
165 IF current_channel = 0 THEN
157 current_cmd <= PROG_START_C16;
166 sample_16_odd <= NOT sample_16_odd;
158 sample_16_odd <= NOT sample_16_odd;
167 END IF;
168 ELSE
169 IF current_channel = 5 THEN
170 current_channel <= 0;
171 STATE_CIC_LFR <= IDLE;
159 ELSE
172 ELSE
160 STATE_CIC_LFR <= IDLE;
173 current_cmd <= PROG_START_I;
161 END IF;
174 current_channel <= current_channel + 1;
162 ELSE
175 END IF;
163 current_channel <= current_channel +1;
164 current_cmd <= PROG_START_I;
165 END IF;
176 END IF;
166 ELSE
177 ELSE
167 current_cmd <= current_cmd +1;
178 current_cmd <= current_cmd +1;
@@ -169,34 +180,37 BEGIN
169
180
170 WHEN RUN_PROG_C16 =>
181 WHEN RUN_PROG_C16 =>
171 IF current_cmd = PROG_END_C16 THEN
182 IF current_cmd = PROG_END_C16 THEN
172 data_out_16_valid <= '1';
183 -- data_out_16_valid <= '1';
173 IF current_channel = 5 THEN
184 IF nb_data_receipt MOD 256 = 255 THEN
174 current_channel <= 0;
185 STATE_CIC_LFR <= RUN_PROG_C256;
175 IF nb_data_receipt MOD 256 = 0 THEN
186 current_cmd <= PROG_START_C256;
176 sample_256_odd <= NOT sample_256_odd;
187 IF current_channel = 0 THEN
177 STATE_CIC_LFR <= RUN_PROG_C256;
188 sample_256_odd <= NOT sample_256_odd;
178 current_cmd <= PROG_START_C256;
189 END IF;
190 ELSE
191 IF current_channel = 5 THEN
192 current_channel <= 0;
193 STATE_CIC_LFR <= IDLE;
179 ELSE
194 ELSE
180 STATE_CIC_LFR <= IDLE;
195 STATE_CIC_LFR <= RUN_PROG_I;
181 END IF;
196 current_cmd <= PROG_START_I;
182 ELSE
197 current_channel <= current_channel + 1;
183 current_channel <= current_channel +1;
198 END IF;
184 current_cmd <= PROG_START_C16;
185 END IF;
199 END IF;
186 ELSE
200 ELSE
187 current_cmd <= current_cmd +1;
201 current_cmd <= current_cmd +1;
188 END IF;
202 END IF;
189
203
190 WHEN RUN_PROG_C256 =>
204 WHEN RUN_PROG_C256 =>
191 IF current_cmd = PROG_END_C256 THEN
205 IF current_cmd = PROG_END_C256 THEN
192 data_out_256_valid <= '1';
206 -- data_out_256_valid <= '1';
193 IF current_channel = 5 THEN
207 IF current_channel = 5 THEN
194 nb_data_receipt <= 0;
195 current_channel <= 0;
208 current_channel <= 0;
196 STATE_CIC_LFR <= IDLE;
209 STATE_CIC_LFR <= IDLE;
197 ELSE
210 ELSE
198 current_channel <= current_channel +1;
211 STATE_CIC_LFR <= RUN_PROG_I;
199 current_cmd <= PROG_START_C256;
212 current_cmd <= PROG_START_I;
213 current_channel <= current_channel + 1;
200 END IF;
214 END IF;
201 ELSE
215 ELSE
202 current_cmd <= current_cmd +1;
216 current_cmd <= current_cmd +1;
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@@ -115,7 +115,7 PACKAGE cic_pkg IS
115 data_in_valid : IN STD_LOGIC;
115 data_in_valid : IN STD_LOGIC;
116 data_out_16_valid : OUT STD_LOGIC;
116 data_out_16_valid : OUT STD_LOGIC;
117 data_out_256_valid : OUT STD_LOGIC;
117 data_out_256_valid : OUT STD_LOGIC;
118 OPERATION : OUT STD_LOGIC_VECTOR(14 DOWNTO 0));
118 OPERATION : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
119 END COMPONENT;
119 END COMPONENT;
120
120
121 COMPONENT cic_lfr_add_sub
121 COMPONENT cic_lfr_add_sub
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