##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Update TAG connexion (cross UART link)
pellion -
r343:db9610d754c6 (LFR-EM) WFP_MS_0-1-9b JC
parent child
Show More
Show file before | Show file after | Hide comments
@@ -1,396 +1,396
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY LFR_em IS
48 ENTITY LFR_em IS
49
49
50 PORT (
50 PORT (
51 clk100MHz : IN STD_ULOGIC;
51 clk100MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
54
54
55 -- TAG --------------------------------------------------------------------
55 -- TAG --------------------------------------------------------------------
56 TAG3 : IN STD_ULOGIC; -- DSU rx data
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 TAG1 : OUT STD_ULOGIC; -- DSU tx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 -- UART APB ---------------------------------------------------------------
58 -- UART APB ---------------------------------------------------------------
59 TAG4 : IN STD_ULOGIC; -- UART1 rx data
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 TAG2 : OUT STD_ULOGIC; -- UART1 tx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 -- RAM --------------------------------------------------------------------
61 -- RAM --------------------------------------------------------------------
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 nSRAM_BE0 : OUT STD_LOGIC;
64 nSRAM_BE0 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
71 -- SPW --------------------------------------------------------------------
71 -- SPW --------------------------------------------------------------------
72 spw1_din : IN STD_LOGIC;
72 spw1_din : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
80 -- ADC --------------------------------------------------------------------
80 -- ADC --------------------------------------------------------------------
81 bias_fail_sw : OUT STD_LOGIC;
81 bias_fail_sw : OUT STD_LOGIC;
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 ADC_smpclk : OUT STD_LOGIC;
83 ADC_smpclk : OUT STD_LOGIC;
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 ---------------------------------------------------------------------------
85 ---------------------------------------------------------------------------
86 TAG8 : OUT STD_LOGIC;
86 TAG8 : OUT STD_LOGIC;
87 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
87 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
88 );
88 );
89
89
90 END LFR_em;
90 END LFR_em;
91
91
92
92
93 ARCHITECTURE beh OF LFR_em IS
93 ARCHITECTURE beh OF LFR_em IS
94 SIGNAL clk_50_s : STD_LOGIC := '0';
94 SIGNAL clk_50_s : STD_LOGIC := '0';
95 SIGNAL clk_25 : STD_LOGIC := '0';
95 SIGNAL clk_25 : STD_LOGIC := '0';
96 SIGNAL clk_24 : STD_LOGIC := '0';
96 SIGNAL clk_24 : STD_LOGIC := '0';
97 -----------------------------------------------------------------------------
97 -----------------------------------------------------------------------------
98 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
99 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
100
100
101 -- CONSTANTS
101 -- CONSTANTS
102 CONSTANT CFG_PADTECH : INTEGER := inferred;
102 CONSTANT CFG_PADTECH : INTEGER := inferred;
103 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
103 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
104 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
104 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
105 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
105 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
106
106
107 SIGNAL apbi_ext : apb_slv_in_type;
107 SIGNAL apbi_ext : apb_slv_in_type;
108 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
108 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
109 SIGNAL ahbi_s_ext : ahb_slv_in_type;
109 SIGNAL ahbi_s_ext : ahb_slv_in_type;
110 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
110 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
111 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
111 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
112 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
112 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
113
113
114 -- Spacewire signals
114 -- Spacewire signals
115 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
115 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 SIGNAL spw_rxtxclk : STD_ULOGIC;
118 SIGNAL spw_rxtxclk : STD_ULOGIC;
119 SIGNAL spw_rxclkn : STD_ULOGIC;
119 SIGNAL spw_rxclkn : STD_ULOGIC;
120 SIGNAL spw_clk : STD_LOGIC;
120 SIGNAL spw_clk : STD_LOGIC;
121 SIGNAL swni : grspw_in_type;
121 SIGNAL swni : grspw_in_type;
122 SIGNAL swno : grspw_out_type;
122 SIGNAL swno : grspw_out_type;
123
123
124 --GPIO
124 --GPIO
125 SIGNAL gpioi : gpio_in_type;
125 SIGNAL gpioi : gpio_in_type;
126 SIGNAL gpioo : gpio_out_type;
126 SIGNAL gpioo : gpio_out_type;
127
127
128 -- AD Converter ADS7886
128 -- AD Converter ADS7886
129 SIGNAL sample : Samples14v(7 DOWNTO 0);
129 SIGNAL sample : Samples14v(7 DOWNTO 0);
130 SIGNAL sample_val : STD_LOGIC;
130 SIGNAL sample_val : STD_LOGIC;
131 SIGNAL ADC_nCS_sig : STD_LOGIC;
131 SIGNAL ADC_nCS_sig : STD_LOGIC;
132 SIGNAL ADC_CLK_sig : STD_LOGIC;
132 SIGNAL ADC_CLK_sig : STD_LOGIC;
133 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
133 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
134
134
135 -----------------------------------------------------------------------------
135 -----------------------------------------------------------------------------
136 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
136 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
137
137
138 -----------------------------------------------------------------------------
138 -----------------------------------------------------------------------------
139 SIGNAL rstn : STD_LOGIC;
139 SIGNAL rstn : STD_LOGIC;
140 BEGIN -- beh
140 BEGIN -- beh
141
141
142 -----------------------------------------------------------------------------
142 -----------------------------------------------------------------------------
143 -- CLK
143 -- CLK
144 -----------------------------------------------------------------------------
144 -----------------------------------------------------------------------------
145 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
145 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
146
146
147 PROCESS(clk100MHz)
147 PROCESS(clk100MHz)
148 BEGIN
148 BEGIN
149 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
149 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
150 clk_50_s <= NOT clk_50_s;
150 clk_50_s <= NOT clk_50_s;
151 END IF;
151 END IF;
152 END PROCESS;
152 END PROCESS;
153
153
154 PROCESS(clk_50_s)
154 PROCESS(clk_50_s)
155 BEGIN
155 BEGIN
156 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
156 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
157 clk_25 <= NOT clk_25;
157 clk_25 <= NOT clk_25;
158 END IF;
158 END IF;
159 END PROCESS;
159 END PROCESS;
160
160
161 PROCESS(clk49_152MHz)
161 PROCESS(clk49_152MHz)
162 BEGIN
162 BEGIN
163 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
163 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
164 clk_24 <= NOT clk_24;
164 clk_24 <= NOT clk_24;
165 END IF;
165 END IF;
166 END PROCESS;
166 END PROCESS;
167
167
168 -----------------------------------------------------------------------------
168 -----------------------------------------------------------------------------
169
169
170 PROCESS (clk_25, rstn)
170 PROCESS (clk_25, rstn)
171 BEGIN -- PROCESS
171 BEGIN -- PROCESS
172 IF rstn = '0' THEN -- asynchronous reset (active low)
172 IF rstn = '0' THEN -- asynchronous reset (active low)
173 led(0) <= '0';
173 led(0) <= '0';
174 led(1) <= '0';
174 led(1) <= '0';
175 led(2) <= '0';
175 led(2) <= '0';
176 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
176 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
177 led(0) <= '0';
177 led(0) <= '0';
178 led(1) <= '1';
178 led(1) <= '1';
179 led(2) <= '1';
179 led(2) <= '1';
180 END IF;
180 END IF;
181 END PROCESS;
181 END PROCESS;
182
182
183 --
183 --
184 leon3_soc_1 : leon3_soc
184 leon3_soc_1 : leon3_soc
185 GENERIC MAP (
185 GENERIC MAP (
186 fabtech => apa3e,
186 fabtech => apa3e,
187 memtech => apa3e,
187 memtech => apa3e,
188 padtech => inferred,
188 padtech => inferred,
189 clktech => inferred,
189 clktech => inferred,
190 disas => 0,
190 disas => 0,
191 dbguart => 0,
191 dbguart => 0,
192 pclow => 2,
192 pclow => 2,
193 clk_freq => 25000,
193 clk_freq => 25000,
194 NB_CPU => 1,
194 NB_CPU => 1,
195 ENABLE_FPU => 1,
195 ENABLE_FPU => 1,
196 FPU_NETLIST => 0,
196 FPU_NETLIST => 0,
197 ENABLE_DSU => 1,
197 ENABLE_DSU => 1,
198 ENABLE_AHB_UART => 1,
198 ENABLE_AHB_UART => 1,
199 ENABLE_APB_UART => 1,
199 ENABLE_APB_UART => 1,
200 ENABLE_IRQMP => 1,
200 ENABLE_IRQMP => 1,
201 ENABLE_GPT => 1,
201 ENABLE_GPT => 1,
202 NB_AHB_MASTER => NB_AHB_MASTER,
202 NB_AHB_MASTER => NB_AHB_MASTER,
203 NB_AHB_SLAVE => NB_AHB_SLAVE,
203 NB_AHB_SLAVE => NB_AHB_SLAVE,
204 NB_APB_SLAVE => NB_APB_SLAVE)
204 NB_APB_SLAVE => NB_APB_SLAVE)
205 PORT MAP (
205 PORT MAP (
206 clk => clk_25,
206 clk => clk_25,
207 reset => rstn,
207 reset => rstn,
208 errorn => OPEN,
208 errorn => OPEN,
209
209
210 ahbrxd => TAG3,
210 ahbrxd => TAG1,
211 ahbtxd => TAG1,
211 ahbtxd => TAG3,
212 urxd1 => TAG4,
212 urxd1 => TAG2,
213 utxd1 => TAG2,
213 utxd1 => TAG4,
214
214
215 address => address,
215 address => address,
216 data => data,
216 data => data,
217 nSRAM_BE0 => nSRAM_BE0,
217 nSRAM_BE0 => nSRAM_BE0,
218 nSRAM_BE1 => nSRAM_BE1,
218 nSRAM_BE1 => nSRAM_BE1,
219 nSRAM_BE2 => nSRAM_BE2,
219 nSRAM_BE2 => nSRAM_BE2,
220 nSRAM_BE3 => nSRAM_BE3,
220 nSRAM_BE3 => nSRAM_BE3,
221 nSRAM_WE => nSRAM_WE,
221 nSRAM_WE => nSRAM_WE,
222 nSRAM_CE => nSRAM_CE,
222 nSRAM_CE => nSRAM_CE,
223 nSRAM_OE => nSRAM_OE,
223 nSRAM_OE => nSRAM_OE,
224
224
225 apbi_ext => apbi_ext,
225 apbi_ext => apbi_ext,
226 apbo_ext => apbo_ext,
226 apbo_ext => apbo_ext,
227 ahbi_s_ext => ahbi_s_ext,
227 ahbi_s_ext => ahbi_s_ext,
228 ahbo_s_ext => ahbo_s_ext,
228 ahbo_s_ext => ahbo_s_ext,
229 ahbi_m_ext => ahbi_m_ext,
229 ahbi_m_ext => ahbi_m_ext,
230 ahbo_m_ext => ahbo_m_ext);
230 ahbo_m_ext => ahbo_m_ext);
231
231
232
232
233 -------------------------------------------------------------------------------
233 -------------------------------------------------------------------------------
234 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
234 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
235 -------------------------------------------------------------------------------
235 -------------------------------------------------------------------------------
236 apb_lfr_time_management_1 : apb_lfr_time_management
236 apb_lfr_time_management_1 : apb_lfr_time_management
237 GENERIC MAP (
237 GENERIC MAP (
238 pindex => 6,
238 pindex => 6,
239 paddr => 6,
239 paddr => 6,
240 pmask => 16#fff#,
240 pmask => 16#fff#,
241 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
241 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
242 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
242 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
243 PORT MAP (
243 PORT MAP (
244 clk25MHz => clk_25,
244 clk25MHz => clk_25,
245 clk24_576MHz => clk_24, -- 49.152MHz/2
245 clk24_576MHz => clk_24, -- 49.152MHz/2
246 resetn => rstn,
246 resetn => rstn,
247 grspw_tick => swno.tickout,
247 grspw_tick => swno.tickout,
248 apbi => apbi_ext,
248 apbi => apbi_ext,
249 apbo => apbo_ext(6),
249 apbo => apbo_ext(6),
250 coarse_time => coarse_time,
250 coarse_time => coarse_time,
251 fine_time => fine_time);
251 fine_time => fine_time);
252
252
253 -----------------------------------------------------------------------
253 -----------------------------------------------------------------------
254 --- SpaceWire --------------------------------------------------------
254 --- SpaceWire --------------------------------------------------------
255 -----------------------------------------------------------------------
255 -----------------------------------------------------------------------
256
256
257 -- SPW_EN <= '1';
257 -- SPW_EN <= '1';
258
258
259 spw_clk <= clk_50_s;
259 spw_clk <= clk_50_s;
260 spw_rxtxclk <= spw_clk;
260 spw_rxtxclk <= spw_clk;
261 spw_rxclkn <= NOT spw_rxtxclk;
261 spw_rxclkn <= NOT spw_rxtxclk;
262
262
263 -- PADS for SPW1
263 -- PADS for SPW1
264 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
264 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
265 PORT MAP (spw1_din, dtmp(0));
265 PORT MAP (spw1_din, dtmp(0));
266 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
266 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
267 PORT MAP (spw1_sin, stmp(0));
267 PORT MAP (spw1_sin, stmp(0));
268 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
268 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
269 PORT MAP (spw1_dout, swno.d(0));
269 PORT MAP (spw1_dout, swno.d(0));
270 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
270 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
271 PORT MAP (spw1_sout, swno.s(0));
271 PORT MAP (spw1_sout, swno.s(0));
272 -- PADS FOR SPW2
272 -- PADS FOR SPW2
273 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
273 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
274 PORT MAP (spw2_sin, dtmp(1));
274 PORT MAP (spw2_sin, dtmp(1));
275 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
275 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
276 PORT MAP (spw2_din, stmp(1));
276 PORT MAP (spw2_din, stmp(1));
277 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
277 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
278 PORT MAP (spw2_dout, swno.d(1));
278 PORT MAP (spw2_dout, swno.d(1));
279 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
279 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
280 PORT MAP (spw2_sout, swno.s(1));
280 PORT MAP (spw2_sout, swno.s(1));
281
281
282 -- GRSPW PHY
282 -- GRSPW PHY
283 --spw1_input: if CFG_SPW_GRSPW = 1 generate
283 --spw1_input: if CFG_SPW_GRSPW = 1 generate
284 spw_inputloop : FOR j IN 0 TO 1 GENERATE
284 spw_inputloop : FOR j IN 0 TO 1 GENERATE
285 spw_phy0 : grspw_phy
285 spw_phy0 : grspw_phy
286 GENERIC MAP(
286 GENERIC MAP(
287 tech => apa3e,
287 tech => apa3e,
288 rxclkbuftype => 1,
288 rxclkbuftype => 1,
289 scantest => 0)
289 scantest => 0)
290 PORT MAP(
290 PORT MAP(
291 rxrst => swno.rxrst,
291 rxrst => swno.rxrst,
292 di => dtmp(j),
292 di => dtmp(j),
293 si => stmp(j),
293 si => stmp(j),
294 rxclko => spw_rxclk(j),
294 rxclko => spw_rxclk(j),
295 do => swni.d(j),
295 do => swni.d(j),
296 ndo => swni.nd(j*5+4 DOWNTO j*5),
296 ndo => swni.nd(j*5+4 DOWNTO j*5),
297 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
297 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
298 END GENERATE spw_inputloop;
298 END GENERATE spw_inputloop;
299
299
300 -- SPW core
300 -- SPW core
301 sw0 : grspwm GENERIC MAP(
301 sw0 : grspwm GENERIC MAP(
302 tech => apa3e,
302 tech => apa3e,
303 hindex => 1,
303 hindex => 1,
304 pindex => 5,
304 pindex => 5,
305 paddr => 5,
305 paddr => 5,
306 pirq => 11,
306 pirq => 11,
307 sysfreq => 25000, -- CPU_FREQ
307 sysfreq => 25000, -- CPU_FREQ
308 rmap => 1,
308 rmap => 1,
309 rmapcrc => 1,
309 rmapcrc => 1,
310 fifosize1 => 16,
310 fifosize1 => 16,
311 fifosize2 => 16,
311 fifosize2 => 16,
312 rxclkbuftype => 1,
312 rxclkbuftype => 1,
313 rxunaligned => 0,
313 rxunaligned => 0,
314 rmapbufs => 4,
314 rmapbufs => 4,
315 ft => 0,
315 ft => 0,
316 netlist => 0,
316 netlist => 0,
317 ports => 2,
317 ports => 2,
318 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
318 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
319 memtech => apa3e,
319 memtech => apa3e,
320 destkey => 2,
320 destkey => 2,
321 spwcore => 1
321 spwcore => 1
322 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
322 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
323 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
323 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
324 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
324 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
325 )
325 )
326 PORT MAP(rstn, clk_25, spw_rxclk(0),
326 PORT MAP(rstn, clk_25, spw_rxclk(0),
327 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
327 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
328 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
328 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
329 swni, swno);
329 swni, swno);
330
330
331 swni.tickin <= '0';
331 swni.tickin <= '0';
332 swni.rmapen <= '1';
332 swni.rmapen <= '1';
333 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
333 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
334 swni.tickinraw <= '0';
334 swni.tickinraw <= '0';
335 swni.timein <= (OTHERS => '0');
335 swni.timein <= (OTHERS => '0');
336 swni.dcrstval <= (OTHERS => '0');
336 swni.dcrstval <= (OTHERS => '0');
337 swni.timerrstval <= (OTHERS => '0');
337 swni.timerrstval <= (OTHERS => '0');
338
338
339 -------------------------------------------------------------------------------
339 -------------------------------------------------------------------------------
340 -- LFR ------------------------------------------------------------------------
340 -- LFR ------------------------------------------------------------------------
341 -------------------------------------------------------------------------------
341 -------------------------------------------------------------------------------
342 lpp_lfr_1 : lpp_lfr_WFP_nMS
342 lpp_lfr_1 : lpp_lfr_WFP_nMS
343 GENERIC MAP (
343 GENERIC MAP (
344 Mem_use => use_RAM,
344 Mem_use => use_RAM,
345 nb_data_by_buffer_size => 32,
345 nb_data_by_buffer_size => 32,
346 nb_word_by_buffer_size => 30,
346 nb_word_by_buffer_size => 30,
347 nb_snapshot_param_size => 32,
347 nb_snapshot_param_size => 32,
348 delta_vector_size => 32,
348 delta_vector_size => 32,
349 delta_vector_size_f0_2 => 7, -- log2(96)
349 delta_vector_size_f0_2 => 7, -- log2(96)
350 pindex => 15,
350 pindex => 15,
351 paddr => 15,
351 paddr => 15,
352 pmask => 16#fff#,
352 pmask => 16#fff#,
353 pirq_ms => 6,
353 pirq_ms => 6,
354 pirq_wfp => 14,
354 pirq_wfp => 14,
355 hindex => 2,
355 hindex => 2,
356 top_lfr_version => X"000109") -- aa.bb.cc version
356 top_lfr_version => X"000109") -- aa.bb.cc version
357 -- AA : BOARD NUMBER
357 -- AA : BOARD NUMBER
358 -- 0 => MINI_LFR
358 -- 0 => MINI_LFR
359 -- 1 => EM
359 -- 1 => EM
360 PORT MAP (
360 PORT MAP (
361 clk => clk_25,
361 clk => clk_25,
362 rstn => rstn,
362 rstn => rstn,
363 sample_B => sample(2 DOWNTO 0),
363 sample_B => sample(2 DOWNTO 0),
364 sample_E => sample(7 DOWNTO 3),
364 sample_E => sample(7 DOWNTO 3),
365 sample_val => sample_val,
365 sample_val => sample_val,
366 apbi => apbi_ext,
366 apbi => apbi_ext,
367 apbo => apbo_ext(15),
367 apbo => apbo_ext(15),
368 ahbi => ahbi_m_ext,
368 ahbi => ahbi_m_ext,
369 ahbo => ahbo_m_ext(2),
369 ahbo => ahbo_m_ext(2),
370 coarse_time => coarse_time,
370 coarse_time => coarse_time,
371 fine_time => fine_time,
371 fine_time => fine_time,
372 data_shaping_BW => bias_fail_sw,
372 data_shaping_BW => bias_fail_sw,
373 observation_reg => observation_reg);
373 observation_reg => observation_reg);
374
374
375 -----------------------------------------------------------------------------
375 -----------------------------------------------------------------------------
376 --
376 --
377 -----------------------------------------------------------------------------
377 -----------------------------------------------------------------------------
378 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
378 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
379 GENERIC MAP (
379 GENERIC MAP (
380 ChanelCount => 8,
380 ChanelCount => 8,
381 ncycle_cnv_high => 40, -- TODO : 79
381 ncycle_cnv_high => 40, -- TODO : 79
382 ncycle_cnv => 250) -- TODO : 500
382 ncycle_cnv => 250) -- TODO : 500
383 PORT MAP (
383 PORT MAP (
384 cnv_clk => clk_24, -- TODO : 49.152
384 cnv_clk => clk_24, -- TODO : 49.152
385 cnv_rstn => rstn, -- ok
385 cnv_rstn => rstn, -- ok
386 cnv => ADC_smpclk, -- ok
386 cnv => ADC_smpclk, -- ok
387 clk => clk_25, -- ok
387 clk => clk_25, -- ok
388 rstn => rstn, -- ok
388 rstn => rstn, -- ok
389 ADC_data => ADC_data, -- ok
389 ADC_data => ADC_data, -- ok
390 ADC_nOE => ADC_OEB_bar_CH, -- ok
390 ADC_nOE => ADC_OEB_bar_CH, -- ok
391 sample => sample, -- ok
391 sample => sample, -- ok
392 sample_val => sample_val); -- ok
392 sample_val => sample_val); -- ok
393
393
394 TAG8 <= ADC_smpclk;
394 TAG8 <= ADC_smpclk;
395
395
396 END beh;
396 END beh;
General Comments 0
You need to be logged in to leave comments. Login now