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1 | ------------------------------------------------------------------------------ | |||
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
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4 | -- | |||
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5 | -- This program is free software; you can redistribute it and/or modify | |||
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6 | -- it under the terms of the GNU General Public License as published by | |||
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7 | -- the Free Software Foundation; either version 3 of the License, or | |||
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8 | -- (at your option) any later version. | |||
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9 | -- | |||
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10 | -- This program is distributed in the hope that it will be useful, | |||
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
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13 | -- GNU General Public License for more details. | |||
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14 | -- | |||
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15 | -- You should have received a copy of the GNU General Public License | |||
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16 | -- along with this program; if not, write to the Free Software | |||
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
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18 | ------------------------------------------------------------------------------- | |||
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19 | -- Author : Jean-christophe Pellion | |||
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
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21 | ------------------------------------------------------------------------------- | |||
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22 | LIBRARY IEEE; | |||
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23 | USE IEEE.numeric_std.ALL; | |||
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24 | USE IEEE.std_logic_1164.ALL; | |||
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25 | LIBRARY grlib; | |||
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26 | USE grlib.amba.ALL; | |||
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27 | USE grlib.stdlib.ALL; | |||
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28 | LIBRARY techmap; | |||
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29 | USE techmap.gencomp.ALL; | |||
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30 | LIBRARY gaisler; | |||
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31 | USE gaisler.memctrl.ALL; | |||
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32 | USE gaisler.leon3.ALL; | |||
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33 | USE gaisler.uart.ALL; | |||
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34 | USE gaisler.misc.ALL; | |||
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35 | USE gaisler.spacewire.ALL; | |||
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36 | LIBRARY esa; | |||
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37 | USE esa.memoryctrl.ALL; | |||
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38 | LIBRARY lpp; | |||
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39 | USE lpp.lpp_memory.ALL; | |||
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40 | USE lpp.lpp_ad_conv.ALL; | |||
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41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib | |||
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42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker | |||
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43 | USE lpp.iir_filter.ALL; | |||
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44 | USE lpp.general_purpose.ALL; | |||
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45 | USE lpp.lpp_lfr_time_management.ALL; | |||
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46 | USE lpp.lpp_leon3_soc_pkg.ALL; | |||
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47 | ||||
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48 | ENTITY MINI_LFR_top IS | |||
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49 | ||||
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50 | PORT ( | |||
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51 | clk_50 : IN STD_LOGIC; | |||
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52 | clk_49 : IN STD_LOGIC; | |||
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53 | reset : IN STD_LOGIC; | |||
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54 | --BPs | |||
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55 | BP0 : IN STD_LOGIC; | |||
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56 | BP1 : IN STD_LOGIC; | |||
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57 | --LEDs | |||
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58 | LED0 : OUT STD_LOGIC; | |||
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59 | LED1 : OUT STD_LOGIC; | |||
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60 | LED2 : OUT STD_LOGIC; | |||
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61 | --UARTs | |||
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62 | TXD1 : IN STD_LOGIC; | |||
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63 | RXD1 : OUT STD_LOGIC; | |||
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64 | nCTS1 : OUT STD_LOGIC; | |||
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65 | nRTS1 : IN STD_LOGIC; | |||
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66 | ||||
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67 | TXD2 : IN STD_LOGIC; | |||
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68 | RXD2 : OUT STD_LOGIC; | |||
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69 | nCTS2 : OUT STD_LOGIC; | |||
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70 | nDTR2 : IN STD_LOGIC; | |||
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71 | nRTS2 : IN STD_LOGIC; | |||
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72 | nDCD2 : OUT STD_LOGIC; | |||
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73 | ||||
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74 | --EXT CONNECTOR | |||
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75 | IO0 : INOUT STD_LOGIC; | |||
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76 | IO1 : INOUT STD_LOGIC; | |||
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77 | IO2 : INOUT STD_LOGIC; | |||
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78 | IO3 : INOUT STD_LOGIC; | |||
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79 | IO4 : INOUT STD_LOGIC; | |||
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80 | IO5 : INOUT STD_LOGIC; | |||
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81 | IO6 : INOUT STD_LOGIC; | |||
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82 | IO7 : INOUT STD_LOGIC; | |||
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83 | IO8 : INOUT STD_LOGIC; | |||
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84 | IO9 : INOUT STD_LOGIC; | |||
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85 | IO10 : INOUT STD_LOGIC; | |||
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86 | IO11 : INOUT STD_LOGIC; | |||
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87 | ||||
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88 | --SPACE WIRE | |||
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89 | SPW_EN : OUT STD_LOGIC; -- 0 => off | |||
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90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK | |||
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91 | SPW_NOM_SIN : IN STD_LOGIC; | |||
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92 | SPW_NOM_DOUT : OUT STD_LOGIC; | |||
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93 | SPW_NOM_SOUT : OUT STD_LOGIC; | |||
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94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK | |||
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95 | SPW_RED_SIN : IN STD_LOGIC; | |||
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96 | SPW_RED_DOUT : OUT STD_LOGIC; | |||
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97 | SPW_RED_SOUT : OUT STD_LOGIC; | |||
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98 | -- MINI LFR ADC INPUTS | |||
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99 | ADC_nCS : OUT STD_LOGIC; | |||
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100 | ADC_CLK : OUT STD_LOGIC; | |||
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101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |||
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102 | ||||
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103 | -- SRAM | |||
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104 | SRAM_nWE : OUT STD_LOGIC; | |||
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105 | SRAM_CE : OUT STD_LOGIC; | |||
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106 | SRAM_nOE : OUT STD_LOGIC; | |||
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107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |||
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109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
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110 | ); | |||
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111 | ||||
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112 | END MINI_LFR_top; | |||
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113 | ||||
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114 | ||||
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115 | ARCHITECTURE beh OF MINI_LFR_top IS | |||
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116 | SIGNAL clk_50_s : STD_LOGIC := '0'; | |||
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117 | SIGNAL clk_25 : STD_LOGIC := '0'; | |||
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118 | SIGNAL clk_24 : STD_LOGIC := '0'; | |||
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119 | ----------------------------------------------------------------------------- | |||
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120 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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121 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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122 | -- | |||
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123 | SIGNAL errorn : STD_LOGIC; | |||
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124 | -- UART AHB --------------------------------------------------------------- | |||
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125 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data | |||
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126 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data | |||
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127 | ||||
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128 | -- UART APB --------------------------------------------------------------- | |||
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129 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data | |||
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130 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data | |||
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131 | -- | |||
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132 | SIGNAL I00_s : STD_LOGIC; | |||
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133 | ||||
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134 | -- CONSTANTS | |||
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135 | CONSTANT CFG_PADTECH : INTEGER := inferred; | |||
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136 | -- | |||
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137 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f | |||
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138 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; | |||
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139 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker | |||
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140 | ||||
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141 | SIGNAL apbi_ext : apb_slv_in_type; | |||
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142 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); | |||
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143 | SIGNAL ahbi_s_ext : ahb_slv_in_type; | |||
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144 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); | |||
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145 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |||
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146 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); | |||
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147 | ||||
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148 | -- Spacewire signals | |||
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149 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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150 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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151 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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152 | SIGNAL spw_rxtxclk : STD_ULOGIC; | |||
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153 | SIGNAL spw_rxclkn : STD_ULOGIC; | |||
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154 | SIGNAL spw_clk : STD_LOGIC; | |||
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155 | SIGNAL swni : grspw_in_type; | |||
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156 | SIGNAL swno : grspw_out_type; | |||
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157 | -- SIGNAL clkmn : STD_ULOGIC; | |||
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158 | -- SIGNAL txclk : STD_ULOGIC; | |||
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159 | ||||
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160 | --GPIO | |||
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161 | SIGNAL gpioi : gpio_in_type; | |||
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162 | SIGNAL gpioo : gpio_out_type; | |||
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163 | ||||
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164 | -- AD Converter ADS7886 | |||
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165 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |||
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166 | SIGNAL sample_val : STD_LOGIC; | |||
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167 | SIGNAL ADC_nCS_sig : STD_LOGIC; | |||
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168 | SIGNAL ADC_CLK_sig : STD_LOGIC; | |||
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169 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); | |||
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170 | ||||
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171 | SIGNAL bias_fail_sw_sig : STD_LOGIC; | |||
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172 | ||||
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173 | ----------------------------------------------------------------------------- | |||
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174 | ||||
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175 | BEGIN -- beh | |||
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176 | ||||
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177 | ----------------------------------------------------------------------------- | |||
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178 | -- CLK | |||
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179 | ----------------------------------------------------------------------------- | |||
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180 | ||||
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181 | PROCESS(clk_50) | |||
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182 | BEGIN | |||
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183 | IF clk_50'EVENT AND clk_50 = '1' THEN | |||
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184 | clk_50_s <= NOT clk_50_s; | |||
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185 | END IF; | |||
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186 | END PROCESS; | |||
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187 | ||||
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188 | PROCESS(clk_50_s) | |||
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189 | BEGIN | |||
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190 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN | |||
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191 | clk_25 <= NOT clk_25; | |||
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192 | END IF; | |||
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193 | END PROCESS; | |||
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194 | ||||
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195 | PROCESS(clk_49) | |||
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196 | BEGIN | |||
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197 | IF clk_49'EVENT AND clk_49 = '1' THEN | |||
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198 | clk_24 <= NOT clk_24; | |||
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199 | END IF; | |||
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200 | END PROCESS; | |||
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201 | ||||
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202 | ----------------------------------------------------------------------------- | |||
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203 | ||||
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204 | PROCESS (clk_25, reset) | |||
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205 | BEGIN -- PROCESS | |||
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206 | IF reset = '0' THEN -- asynchronous reset (active low) | |||
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207 | LED0 <= '0'; | |||
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208 | LED1 <= '0'; | |||
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209 | LED2 <= '0'; | |||
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210 | --IO1 <= '0'; | |||
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211 | --IO2 <= '1'; | |||
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212 | --IO3 <= '0'; | |||
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213 | --IO4 <= '0'; | |||
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214 | --IO5 <= '0'; | |||
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215 | --IO6 <= '0'; | |||
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216 | --IO7 <= '0'; | |||
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217 | --IO8 <= '0'; | |||
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218 | --IO9 <= '0'; | |||
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219 | --IO10 <= '0'; | |||
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220 | --IO11 <= '0'; | |||
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221 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |||
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222 | LED0 <= '0'; | |||
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223 | LED1 <= '1'; | |||
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224 | LED2 <= BP0; | |||
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225 | --IO1 <= '1'; | |||
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226 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; | |||
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227 | --IO3 <= ADC_SDO(0); | |||
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228 | --IO4 <= ADC_SDO(1); | |||
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229 | --IO5 <= ADC_SDO(2); | |||
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230 | --IO6 <= ADC_SDO(3); | |||
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231 | --IO7 <= ADC_SDO(4); | |||
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232 | --IO8 <= ADC_SDO(5); | |||
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233 | --IO9 <= ADC_SDO(6); | |||
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234 | --IO10 <= ADC_SDO(7); | |||
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235 | IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |||
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236 | END IF; | |||
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237 | END PROCESS; | |||
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238 | ||||
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239 | PROCESS (clk_24, reset) | |||
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240 | BEGIN -- PROCESS | |||
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241 | IF reset = '0' THEN -- asynchronous reset (active low) | |||
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242 | I00_s <= '0'; | |||
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243 | ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge | |||
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244 | I00_s <= NOT I00_s; | |||
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245 | END IF; | |||
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246 | END PROCESS; | |||
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247 | -- IO0 <= I00_s; | |||
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248 | ||||
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249 | --UARTs | |||
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250 | nCTS1 <= '1'; | |||
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251 | nCTS2 <= '1'; | |||
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252 | nDCD2 <= '1'; | |||
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253 | ||||
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254 | --EXT CONNECTOR | |||
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255 | ||||
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256 | --SPACE WIRE | |||
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257 | ||||
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258 | leon3_soc_1 : leon3_soc | |||
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259 | GENERIC MAP ( | |||
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260 | fabtech => apa3e, | |||
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261 | memtech => apa3e, | |||
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262 | padtech => inferred, | |||
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263 | clktech => inferred, | |||
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264 | disas => 0, | |||
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265 | dbguart => 0, | |||
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266 | pclow => 2, | |||
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267 | clk_freq => 25000, | |||
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268 | NB_CPU => 1, | |||
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269 | ENABLE_FPU => 1, | |||
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270 | FPU_NETLIST => 0, | |||
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271 | ENABLE_DSU => 1, | |||
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272 | ENABLE_AHB_UART => 1, | |||
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273 | ENABLE_APB_UART => 1, | |||
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274 | ENABLE_IRQMP => 1, | |||
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275 | ENABLE_GPT => 1, | |||
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276 | NB_AHB_MASTER => NB_AHB_MASTER, | |||
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277 | NB_AHB_SLAVE => NB_AHB_SLAVE, | |||
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278 | NB_APB_SLAVE => NB_APB_SLAVE) | |||
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279 | PORT MAP ( | |||
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280 | clk => clk_25, | |||
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281 | reset => reset, | |||
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282 | errorn => errorn, | |||
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283 | ahbrxd => TXD1, | |||
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284 | ahbtxd => RXD1, | |||
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285 | urxd1 => TXD2, | |||
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286 | utxd1 => RXD2, | |||
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287 | address => SRAM_A, | |||
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288 | data => SRAM_DQ, | |||
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289 | nSRAM_BE0 => SRAM_nBE(0), | |||
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290 | nSRAM_BE1 => SRAM_nBE(1), | |||
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291 | nSRAM_BE2 => SRAM_nBE(2), | |||
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292 | nSRAM_BE3 => SRAM_nBE(3), | |||
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293 | nSRAM_WE => SRAM_nWE, | |||
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294 | nSRAM_CE => SRAM_CE, | |||
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295 | nSRAM_OE => SRAM_nOE, | |||
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296 | ||||
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297 | apbi_ext => apbi_ext, | |||
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298 | apbo_ext => apbo_ext, | |||
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299 | ahbi_s_ext => ahbi_s_ext, | |||
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300 | ahbo_s_ext => ahbo_s_ext, | |||
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301 | ahbi_m_ext => ahbi_m_ext, | |||
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302 | ahbo_m_ext => ahbo_m_ext); | |||
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303 | ||||
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304 | ------------------------------------------------------------------------------- | |||
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305 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- | |||
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306 | ------------------------------------------------------------------------------- | |||
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307 | apb_lfr_time_management_1 : apb_lfr_time_management | |||
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308 | GENERIC MAP ( | |||
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309 | pindex => 6, | |||
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310 | paddr => 6, | |||
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311 | pmask => 16#fff#, | |||
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312 | pirq => 12, | |||
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313 | nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375 | |||
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314 | PORT MAP ( | |||
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315 | clk25MHz => clk_25, | |||
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316 | clk49_152MHz => clk_24, -- 49.152MHz/2 | |||
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317 | resetn => reset, | |||
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318 | grspw_tick => swno.tickout, | |||
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319 | apbi => apbi_ext, | |||
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320 | apbo => apbo_ext(6), | |||
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321 | coarse_time => coarse_time, | |||
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322 | fine_time => fine_time); | |||
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323 | ||||
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324 | ----------------------------------------------------------------------- | |||
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325 | --- SpaceWire -------------------------------------------------------- | |||
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326 | ----------------------------------------------------------------------- | |||
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327 | ||||
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328 | SPW_EN <= '1'; | |||
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329 | ||||
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330 | spw_clk <= clk_50_s; | |||
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331 | spw_rxtxclk <= spw_clk; | |||
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332 | spw_rxclkn <= NOT spw_rxtxclk; | |||
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333 | ||||
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334 | -- PADS for SPW1 | |||
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335 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) | |||
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336 | PORT MAP (SPW_NOM_DIN, dtmp(0)); | |||
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337 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) | |||
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338 | PORT MAP (SPW_NOM_SIN, stmp(0)); | |||
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339 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) | |||
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340 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); | |||
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341 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) | |||
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342 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); | |||
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343 | -- PADS FOR SPW2 | |||
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344 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |||
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345 | PORT MAP (SPW_RED_SIN, dtmp(1)); | |||
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346 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |||
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347 | PORT MAP (SPW_RED_DIN, stmp(1)); | |||
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348 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) | |||
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349 | PORT MAP (SPW_RED_DOUT, swno.d(1)); | |||
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350 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) | |||
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351 | PORT MAP (SPW_RED_SOUT, swno.s(1)); | |||
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352 | ||||
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353 | -- GRSPW PHY | |||
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354 | --spw1_input: if CFG_SPW_GRSPW = 1 generate | |||
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355 | spw_inputloop : FOR j IN 0 TO 1 GENERATE | |||
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356 | spw_phy0 : grspw_phy | |||
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357 | GENERIC MAP( | |||
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358 | tech => apa3e, | |||
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359 | rxclkbuftype => 1, | |||
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360 | scantest => 0) | |||
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361 | PORT MAP( | |||
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362 | rxrst => swno.rxrst, | |||
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363 | di => dtmp(j), | |||
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364 | si => stmp(j), | |||
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365 | rxclko => spw_rxclk(j), | |||
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366 | do => swni.d(j), | |||
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367 | ndo => swni.nd(j*5+4 DOWNTO j*5), | |||
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368 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); | |||
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369 | END GENERATE spw_inputloop; | |||
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370 | ||||
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371 | -- SPW core | |||
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372 | sw0 : grspwm GENERIC MAP( | |||
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373 | tech => apa3e, | |||
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374 | hindex => 1, | |||
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375 | pindex => 5, | |||
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376 | paddr => 5, | |||
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377 | pirq => 11, | |||
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378 | sysfreq => 25000, -- CPU_FREQ | |||
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379 | rmap => 1, | |||
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380 | rmapcrc => 1, | |||
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381 | fifosize1 => 16, | |||
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382 | fifosize2 => 16, | |||
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383 | rxclkbuftype => 1, | |||
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384 | rxunaligned => 0, | |||
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385 | rmapbufs => 4, | |||
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386 | ft => 0, | |||
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387 | netlist => 0, | |||
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388 | ports => 2, | |||
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389 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 | |||
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390 | memtech => apa3e, | |||
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391 | destkey => 2, | |||
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392 | spwcore => 1 | |||
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393 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 | |||
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394 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 | |||
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395 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 | |||
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396 | ) | |||
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397 | PORT MAP(reset, clk_25, spw_rxclk(0), | |||
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398 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, | |||
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399 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), | |||
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400 | swni, swno); | |||
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401 | ||||
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402 | swni.tickin <= '0'; | |||
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403 | swni.rmapen <= '1'; | |||
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404 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz | |||
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405 | swni.tickinraw <= '0'; | |||
|
406 | swni.timein <= (OTHERS => '0'); | |||
|
407 | swni.dcrstval <= (OTHERS => '0'); | |||
|
408 | swni.timerrstval <= (OTHERS => '0'); | |||
|
409 | ||||
|
410 | ------------------------------------------------------------------------------- | |||
|
411 | -- LFR ------------------------------------------------------------------------ | |||
|
412 | ------------------------------------------------------------------------------- | |||
|
413 | lpp_lfr_1 : lpp_lfr | |||
|
414 | GENERIC MAP ( | |||
|
415 | Mem_use => use_RAM, | |||
|
416 | nb_data_by_buffer_size => 32, | |||
|
417 | nb_word_by_buffer_size => 30, | |||
|
418 | nb_snapshot_param_size => 32, | |||
|
419 | delta_vector_size => 32, | |||
|
420 | delta_vector_size_f0_2 => 7, -- log2(96) | |||
|
421 | pindex => 15, | |||
|
422 | paddr => 15, | |||
|
423 | pmask => 16#fff#, | |||
|
424 | pirq_ms => 6, | |||
|
425 | pirq_wfp => 14, | |||
|
426 | hindex => 2, | |||
|
427 | top_lfr_version => X"000101") -- aa.bb.cc version | |||
|
428 | PORT MAP ( | |||
|
429 | clk => clk_25, | |||
|
430 | rstn => reset, | |||
|
431 | sample_B => sample(2 DOWNTO 0), | |||
|
432 | sample_E => sample(7 DOWNTO 3), | |||
|
433 | sample_val => sample_val, | |||
|
434 | apbi => apbi_ext, | |||
|
435 | apbo => apbo_ext(15), | |||
|
436 | ahbi => ahbi_m_ext, | |||
|
437 | ahbo => ahbo_m_ext(2), | |||
|
438 | coarse_time => coarse_time, | |||
|
439 | fine_time => fine_time, | |||
|
440 | data_shaping_BW => bias_fail_sw_sig); | |||
|
441 | ||||
|
442 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 | |||
|
443 | GENERIC MAP( | |||
|
444 | ChannelCount => 8, | |||
|
445 | SampleNbBits => 14, | |||
|
446 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 | |||
|
447 | ncycle_cnv => 250) -- 49 152 000 / 98304 /2 | |||
|
448 | PORT MAP ( | |||
|
449 | -- CONV | |||
|
450 | cnv_clk => clk_24, | |||
|
451 | cnv_rstn => reset, | |||
|
452 | cnv => ADC_nCS_sig, | |||
|
453 | -- DATA | |||
|
454 | clk => clk_25, | |||
|
455 | rstn => reset, | |||
|
456 | sck => ADC_CLK_sig, | |||
|
457 | sdo => ADC_SDO_sig, | |||
|
458 | -- SAMPLE | |||
|
459 | sample => sample, | |||
|
460 | sample_val => sample_val); | |||
|
461 | ||||
|
462 | IO10 <= ADC_SDO_sig(5); | |||
|
463 | IO9 <= ADC_SDO_sig(4); | |||
|
464 | IO8 <= ADC_SDO_sig(3); | |||
|
465 | ||||
|
466 | ADC_nCS <= ADC_nCS_sig; | |||
|
467 | ADC_CLK <= ADC_CLK_sig; | |||
|
468 | ADC_SDO_sig <= ADC_SDO; | |||
|
469 | ||||
|
470 | ---------------------------------------------------------------------- | |||
|
471 | --- GPIO ----------------------------------------------------------- | |||
|
472 | ---------------------------------------------------------------------- | |||
|
473 | ||||
|
474 | grgpio0 : grgpio | |||
|
475 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) | |||
|
476 | PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); | |||
|
477 | ||||
|
478 | pio_pad_0 : iopad | |||
|
479 | GENERIC MAP (tech => CFG_PADTECH) | |||
|
480 | PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); | |||
|
481 | pio_pad_1 : iopad | |||
|
482 | GENERIC MAP (tech => CFG_PADTECH) | |||
|
483 | PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); | |||
|
484 | pio_pad_2 : iopad | |||
|
485 | GENERIC MAP (tech => CFG_PADTECH) | |||
|
486 | PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); | |||
|
487 | pio_pad_3 : iopad | |||
|
488 | GENERIC MAP (tech => CFG_PADTECH) | |||
|
489 | PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); | |||
|
490 | pio_pad_4 : iopad | |||
|
491 | GENERIC MAP (tech => CFG_PADTECH) | |||
|
492 | PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); | |||
|
493 | pio_pad_5 : iopad | |||
|
494 | GENERIC MAP (tech => CFG_PADTECH) | |||
|
495 | PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); | |||
|
496 | pio_pad_6 : iopad | |||
|
497 | GENERIC MAP (tech => CFG_PADTECH) | |||
|
498 | PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); | |||
|
499 | pio_pad_7 : iopad | |||
|
500 | GENERIC MAP (tech => CFG_PADTECH) | |||
|
501 | PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); | |||
|
502 | ||||
|
503 | END beh; |
@@ -0,0 +1,46 | |||||
|
1 | VHDLIB=../.. | |||
|
2 | SCRIPTSDIR=$(VHDLIB)/scripts/ | |||
|
3 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) | |||
|
4 | TOP=MINI_LFR_top | |||
|
5 | BOARD=MINI-LFR | |||
|
6 | include $(VHDLIB)/boards/$(BOARD)/Makefile.inc | |||
|
7 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) | |||
|
8 | UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf | |||
|
9 | QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf | |||
|
10 | EFFORT=high | |||
|
11 | XSTOPT= | |||
|
12 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" | |||
|
13 | VHDLSYNFILES= MINI_LFR_top.vhd | |||
|
14 | ||||
|
15 | PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc | |||
|
16 | BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut | |||
|
17 | CLEAN=soft-clean | |||
|
18 | ||||
|
19 | TECHLIBS = proasic3e | |||
|
20 | ||||
|
21 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ | |||
|
22 | tmtc openchip hynix ihp gleichmann micron usbhc | |||
|
23 | ||||
|
24 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ | |||
|
25 | pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ | |||
|
26 | ./amba_lcd_16x2_ctrlr \ | |||
|
27 | ./general_purpose/lpp_AMR \ | |||
|
28 | ./general_purpose/lpp_balise \ | |||
|
29 | ./general_purpose/lpp_delay \ | |||
|
30 | ./lpp_bootloader \ | |||
|
31 | ./lpp_cna \ | |||
|
32 | ./lpp_uart \ | |||
|
33 | ./lpp_usb \ | |||
|
34 | ./lpp_sim/CY7C1061DV33 \ | |||
|
35 | ||||
|
36 | FILESKIP =i2cmst.vhd \ | |||
|
37 | APB_MULTI_DIODE.vhd \ | |||
|
38 | APB_SIMPLE_DIODE.vhd \ | |||
|
39 | Top_MatrixSpec.vhd \ | |||
|
40 | APB_FFT.vhd | |||
|
41 | ||||
|
42 | include $(GRLIB)/bin/Makefile | |||
|
43 | include $(GRLIB)/software/leon3/Makefile | |||
|
44 | ||||
|
45 | ################## project specific targets ########################## | |||
|
46 |
@@ -8,6 +8,8 vcom -quiet -93 -work lpp ../../../grl | |||||
8 |
|
8 | |||
9 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd |
|
9 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd | |
10 |
|
10 | |||
|
11 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd | |||
|
12 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd | |||
11 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_test.vhd |
|
13 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_test.vhd | |
12 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd |
|
14 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd | |
13 |
|
15 | |||
@@ -21,6 +23,6 vsim work.testbench | |||||
21 |
|
23 | |||
22 | log -r * |
|
24 | log -r * | |
23 |
|
25 | |||
24 |
do wave_ |
|
26 | do wave_ms.do | |
25 |
|
27 | |||
26 |
run |
|
28 | run 2 ms |
@@ -314,24 +314,24 BEGIN | |||||
314 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
|
314 | ahb0 : ahbctrl -- AHB arbiter/multiplexer | |
315 | GENERIC MAP (defmast => 0, split => 0, |
|
315 | GENERIC MAP (defmast => 0, split => 0, | |
316 | rrobin => 1, ioaddr => 16#FFF#, |
|
316 | rrobin => 1, ioaddr => 16#FFF#, | |
317 |
ioen => 0, nahbm => 2, nahbs => |
|
317 | ioen => 0, nahbm => 2, nahbs => 4) | |
318 | PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso); |
|
318 | PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso); | |
319 |
|
319 | |||
320 |
|
320 | |||
321 |
|
321 | |||
322 | --- AHB RAM ---------------------------------------------------------- |
|
322 | --- AHB RAM ---------------------------------------------------------- | |
323 |
|
|
323 | ahbram0 : ahbram | |
324 |
|
|
324 | GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0) | |
325 |
|
|
325 | PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0)); | |
326 |
|
|
326 | ahbram1 : ahbram | |
327 |
|
|
327 | GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0) | |
328 |
|
|
328 | PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1)); | |
329 |
|
|
329 | ahbram2 : ahbram | |
330 |
|
|
330 | GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0) | |
331 |
|
|
331 | PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2)); | |
332 |
|
|
332 | ahbram3 : ahbram | |
333 |
|
|
333 | GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0) | |
334 |
|
|
334 | PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3)); | |
335 |
|
335 | |||
336 | ----------------------------------------------------------------------------- |
|
336 | ----------------------------------------------------------------------------- | |
337 | ---------------------------------------------------------------------- |
|
337 | ---------------------------------------------------------------------- | |
@@ -501,7 +501,7 BEGIN | |||||
501 | ----------------------------------------------------------------------------- |
|
501 | ----------------------------------------------------------------------------- | |
502 | -- IRQ |
|
502 | -- IRQ | |
503 | ----------------------------------------------------------------------------- |
|
503 | ----------------------------------------------------------------------------- | |
504 | PROCESS |
|
504 | PROCESS (clk25MHz, rstn) | |
505 | BEGIN -- PROCESS |
|
505 | BEGIN -- PROCESS | |
506 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
506 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
507 |
|
507 |
@@ -17,6 +17,7 SYNC_FF.vhd | |||||
17 | Shifter.vhd |
|
17 | Shifter.vhd | |
18 | TwoComplementer.vhd |
|
18 | TwoComplementer.vhd | |
19 | Clock_Divider.vhd |
|
19 | Clock_Divider.vhd | |
|
20 | lpp_front_to_level.vhd | |||
20 | lpp_front_detection.vhd |
|
21 | lpp_front_detection.vhd | |
21 | lpp_front_positive_detection.vhd |
|
22 | lpp_front_positive_detection.vhd | |
22 | SYNC_VALID_BIT.vhd |
|
23 | SYNC_VALID_BIT.vhd |
@@ -40,7 +40,7 PACKAGE apb_devices_list IS | |||||
40 | CONSTANT LPP_CLKSETTING : amba_device_type := 16#20#; |
|
40 | CONSTANT LPP_CLKSETTING : amba_device_type := 16#20#; | |
41 |
|
41 | |||
42 | CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#; |
|
42 | CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#; | |
43 |
CONSTANT LPP_DEBUG_LFR |
|
43 | CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#; | |
44 |
|
44 | |||
45 | CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A2#; |
|
45 | CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A2#; | |
46 |
|
46 |
@@ -59,7 +59,7 ENTITY lpp_lfr IS | |||||
59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
61 | -- |
|
61 | -- | |
62 |
data_shaping_BW : OUT STD_LOGIC |
|
62 | data_shaping_BW : OUT STD_LOGIC; | |
63 | -- |
|
63 | -- | |
64 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
64 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
65 |
|
65 | |||
@@ -489,7 +489,7 BEGIN | |||||
489 | data_f3_data_out => data_f3_data_out, |
|
489 | data_f3_data_out => data_f3_data_out, | |
490 | data_f3_data_out_valid => data_f3_data_out_valid_s, |
|
490 | data_f3_data_out_valid => data_f3_data_out_valid_s, | |
491 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, |
|
491 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, | |
492 |
data_f3_data_out_ren => data_f3_data_out_ren |
|
492 | data_f3_data_out_ren => data_f3_data_out_ren , | |
493 |
|
493 | |||
494 | ------------------------------------------------------------------------- |
|
494 | ------------------------------------------------------------------------- | |
495 | observation_reg => observation_reg |
|
495 | observation_reg => observation_reg | |
@@ -605,8 +605,10 BEGIN | |||||
605 | dma_sel <= (OTHERS => '0'); |
|
605 | dma_sel <= (OTHERS => '0'); | |
606 | dma_send <= '0'; |
|
606 | dma_send <= '0'; | |
607 | dma_valid_burst <= '0'; |
|
607 | dma_valid_burst <= '0'; | |
|
608 | data_ms_done <= '0'; | |||
608 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
609 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
609 | IF run = '1' THEN |
|
610 | IF run = '1' THEN | |
|
611 | data_ms_done <= '0'; | |||
610 | IF dma_sel = "00000" OR dma_done = '1' THEN |
|
612 | IF dma_sel = "00000" OR dma_done = '1' THEN | |
611 | dma_sel <= dma_rr_grant; |
|
613 | dma_sel <= dma_rr_grant; | |
612 | IF dma_rr_grant(0) = '1' THEN |
|
614 | IF dma_rr_grant(0) = '1' THEN | |
@@ -639,6 +641,7 BEGIN | |||||
639 | dma_send <= '0'; |
|
641 | dma_send <= '0'; | |
640 | END IF; |
|
642 | END IF; | |
641 | ELSE |
|
643 | ELSE | |
|
644 | data_ms_done <= '0'; | |||
642 | dma_sel <= (OTHERS => '0'); |
|
645 | dma_sel <= (OTHERS => '0'); | |
643 | dma_send <= '0'; |
|
646 | dma_send <= '0'; | |
644 | dma_valid_burst <= '0'; |
|
647 | dma_valid_burst <= '0'; | |
@@ -717,6 +720,7 BEGIN | |||||
717 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) |
|
720 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) | |
718 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); |
|
721 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); | |
719 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); |
|
722 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); | |
|
723 | ||||
720 |
|
|
724 | ------------------------------------------------------------------------------- | |
721 | lpp_lfr_ms_1: lpp_lfr_ms |
|
725 | lpp_lfr_ms_1: lpp_lfr_ms | |
722 | GENERIC MAP ( |
|
726 | GENERIC MAP ( | |
@@ -725,6 +729,9 BEGIN | |||||
725 | clk => clk, |
|
729 | clk => clk, | |
726 | rstn => rstn, |
|
730 | rstn => rstn, | |
727 |
|
731 | |||
|
732 | coarse_time => coarse_time, | |||
|
733 | fine_time => fine_time, | |||
|
734 | ||||
728 | sample_f0_wen => sample_f0_wen, |
|
735 | sample_f0_wen => sample_f0_wen, | |
729 | sample_f0_wdata => sample_f0_wdata, |
|
736 | sample_f0_wdata => sample_f0_wdata, | |
730 | sample_f1_wen => sample_f1_wen, |
|
737 | sample_f1_wen => sample_f1_wen, |
@@ -37,6 +37,9 ENTITY lpp_lfr_ms IS | |||||
37 | --------------------------------------------------------------------------- |
|
37 | --------------------------------------------------------------------------- | |
38 | -- DATA INPUT |
|
38 | -- DATA INPUT | |
39 | --------------------------------------------------------------------------- |
|
39 | --------------------------------------------------------------------------- | |
|
40 | -- TIME | |||
|
41 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |||
|
42 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |||
40 | -- |
|
43 | -- | |
41 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
44 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
42 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
45 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
@@ -136,6 +139,9 ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |||||
136 | SIGNAL DMA_Read : STD_LOGIC; |
|
139 | SIGNAL DMA_Read : STD_LOGIC; | |
137 | SIGNAL DMA_ack : STD_LOGIC; |
|
140 | SIGNAL DMA_ack : STD_LOGIC; | |
138 |
|
141 | |||
|
142 | ----------------------------------------------------------------------------- | |||
|
143 | SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
144 | ||||
139 | BEGIN |
|
145 | BEGIN | |
140 |
|
146 | |||
141 | ----------------------------------------------------------------------------- |
|
147 | ----------------------------------------------------------------------------- | |
@@ -305,13 +311,16 BEGIN | |||||
305 | header_val => Head_Val, |
|
311 | header_val => Head_Val, | |
306 | header_ack => DMA_ack ); |
|
312 | header_ack => DMA_ack ); | |
307 | ----------------------------------------------------------------------------- |
|
313 | ----------------------------------------------------------------------------- | |
308 |
|
314 | data_time(31 DOWNTO 0) <= coarse_time; | ||
|
315 | data_time(47 DOWNTO 32) <= fine_time; | |||
309 |
|
316 | |||
310 | lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma |
|
317 | lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma | |
311 | PORT MAP ( |
|
318 | PORT MAP ( | |
312 | HCLK => clk, |
|
319 | HCLK => clk, | |
313 | HRESETn => rstn, |
|
320 | HRESETn => rstn, | |
314 |
|
321 | |||
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322 | data_time => data_time, | |||
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323 | ||||
315 | fifo_data => Head_Data, |
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324 | fifo_data => Head_Data, | |
316 | fifo_empty => Head_Empty, |
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325 | fifo_empty => Head_Empty, | |
317 | fifo_ren => DMA_Read, |
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326 | fifo_ren => DMA_Read, |
@@ -21,6 +21,10 PACKAGE lpp_lfr_pkg IS | |||||
21 | PORT ( |
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21 | PORT ( | |
22 | clk : IN STD_LOGIC; |
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22 | clk : IN STD_LOGIC; | |
23 | rstn : IN STD_LOGIC; |
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23 | rstn : IN STD_LOGIC; | |
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24 | ||||
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25 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |||
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26 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |||
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27 | ||||
24 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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28 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
25 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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29 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
26 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
30 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
@@ -60,6 +64,7 PACKAGE lpp_lfr_pkg IS | |||||
60 | PORT ( |
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64 | PORT ( | |
61 | HCLK : IN STD_ULOGIC; |
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65 | HCLK : IN STD_ULOGIC; | |
62 | HRESETn : IN STD_ULOGIC; |
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66 | HRESETn : IN STD_ULOGIC; | |
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67 | data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
63 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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68 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
64 | fifo_empty : IN STD_LOGIC; |
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69 | fifo_empty : IN STD_LOGIC; | |
65 | fifo_ren : OUT STD_LOGIC; |
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70 | fifo_ren : OUT STD_LOGIC; | |
@@ -144,7 +149,7 PACKAGE lpp_lfr_pkg IS | |||||
144 | ahbo : OUT AHB_Mst_Out_Type; |
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149 | ahbo : OUT AHB_Mst_Out_Type; | |
145 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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150 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
146 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
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151 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
147 | data_shaping_BW : OUT STD_LOGIC |
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152 | data_shaping_BW : OUT STD_LOGIC; | |
148 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
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153 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
149 | ); |
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154 | ); | |
150 | END COMPONENT; |
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155 | END COMPONENT; |
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