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1 | ------------------------------------------------------------------------------ | |||
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
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4 | -- | |||
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5 | -- This program is free software; you can redistribute it and/or modify | |||
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6 | -- it under the terms of the GNU General Public License as published by | |||
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7 | -- the Free Software Foundation; either version 3 of the License, or | |||
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8 | -- (at your option) any later version. | |||
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9 | -- | |||
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10 | -- This program is distributed in the hope that it will be useful, | |||
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
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13 | -- GNU General Public License for more details. | |||
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14 | -- | |||
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15 | -- You should have received a copy of the GNU General Public License | |||
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16 | -- along with this program; if not, write to the Free Software | |||
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
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18 | ------------------------------------------------------------------------------- | |||
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19 | -- Author : Jean-christophe Pellion | |||
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
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21 | ------------------------------------------------------------------------------- | |||
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22 | LIBRARY IEEE; | |||
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23 | USE IEEE.numeric_std.ALL; | |||
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24 | USE IEEE.std_logic_1164.ALL; | |||
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25 | LIBRARY grlib; | |||
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26 | USE grlib.amba.ALL; | |||
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27 | USE grlib.stdlib.ALL; | |||
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28 | LIBRARY techmap; | |||
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29 | USE techmap.gencomp.ALL; | |||
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30 | LIBRARY gaisler; | |||
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31 | USE gaisler.memctrl.ALL; | |||
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32 | USE gaisler.leon3.ALL; | |||
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33 | USE gaisler.uart.ALL; | |||
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34 | USE gaisler.misc.ALL; | |||
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35 | USE gaisler.spacewire.ALL; | |||
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36 | LIBRARY esa; | |||
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37 | USE esa.memoryctrl.ALL; | |||
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38 | LIBRARY lpp; | |||
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39 | USE lpp.lpp_memory.ALL; | |||
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40 | USE lpp.lpp_ad_conv.ALL; | |||
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41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib | |||
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42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker | |||
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43 | USE lpp.iir_filter.ALL; | |||
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44 | USE lpp.general_purpose.ALL; | |||
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45 | USE lpp.lpp_lfr_time_management.ALL; | |||
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46 | USE lpp.lpp_leon3_soc_pkg.ALL; | |||
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47 | ||||
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48 | ENTITY MINI_LFR_top IS | |||
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49 | ||||
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50 | PORT ( | |||
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51 | clk_50 : IN STD_LOGIC; | |||
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52 | clk_49 : IN STD_LOGIC; | |||
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53 | reset : IN STD_LOGIC; | |||
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54 | --BPs | |||
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55 | BP0 : IN STD_LOGIC; | |||
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56 | BP1 : IN STD_LOGIC; | |||
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57 | --LEDs | |||
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58 | LED0 : OUT STD_LOGIC; | |||
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59 | LED1 : OUT STD_LOGIC; | |||
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60 | LED2 : OUT STD_LOGIC; | |||
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61 | --UARTs | |||
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62 | TXD1 : IN STD_LOGIC; | |||
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63 | RXD1 : OUT STD_LOGIC; | |||
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64 | nCTS1 : OUT STD_LOGIC; | |||
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65 | nRTS1 : IN STD_LOGIC; | |||
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66 | ||||
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67 | TXD2 : IN STD_LOGIC; | |||
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68 | RXD2 : OUT STD_LOGIC; | |||
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69 | nCTS2 : OUT STD_LOGIC; | |||
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70 | nDTR2 : IN STD_LOGIC; | |||
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71 | nRTS2 : IN STD_LOGIC; | |||
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72 | nDCD2 : OUT STD_LOGIC; | |||
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73 | ||||
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74 | --EXT CONNECTOR | |||
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75 | IO0 : INOUT STD_LOGIC; | |||
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76 | IO1 : INOUT STD_LOGIC; | |||
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77 | IO2 : INOUT STD_LOGIC; | |||
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78 | IO3 : INOUT STD_LOGIC; | |||
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79 | IO4 : INOUT STD_LOGIC; | |||
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80 | IO5 : INOUT STD_LOGIC; | |||
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81 | IO6 : INOUT STD_LOGIC; | |||
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82 | IO7 : INOUT STD_LOGIC; | |||
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83 | IO8 : INOUT STD_LOGIC; | |||
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84 | IO9 : INOUT STD_LOGIC; | |||
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85 | IO10 : INOUT STD_LOGIC; | |||
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86 | IO11 : INOUT STD_LOGIC; | |||
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87 | ||||
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88 | --SPACE WIRE | |||
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89 | SPW_EN : OUT STD_LOGIC; -- 0 => off | |||
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90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK | |||
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91 | SPW_NOM_SIN : IN STD_LOGIC; | |||
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92 | SPW_NOM_DOUT : OUT STD_LOGIC; | |||
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93 | SPW_NOM_SOUT : OUT STD_LOGIC; | |||
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94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK | |||
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95 | SPW_RED_SIN : IN STD_LOGIC; | |||
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96 | SPW_RED_DOUT : OUT STD_LOGIC; | |||
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97 | SPW_RED_SOUT : OUT STD_LOGIC; | |||
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98 | -- MINI LFR ADC INPUTS | |||
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99 | ADC_nCS : OUT STD_LOGIC; | |||
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100 | ADC_CLK : OUT STD_LOGIC; | |||
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101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |||
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102 | ||||
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103 | -- SRAM | |||
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104 | SRAM_nWE : OUT STD_LOGIC; | |||
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105 | SRAM_CE : OUT STD_LOGIC; | |||
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106 | SRAM_nOE : OUT STD_LOGIC; | |||
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107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |||
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109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
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110 | ); | |||
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111 | ||||
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112 | END MINI_LFR_top; | |||
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113 | ||||
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114 | ||||
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115 | ARCHITECTURE beh OF MINI_LFR_top IS | |||
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116 | SIGNAL clk_50_s : STD_LOGIC := '0'; | |||
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117 | SIGNAL clk_25 : STD_LOGIC := '0'; | |||
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118 | SIGNAL clk_24 : STD_LOGIC := '0'; | |||
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119 | ----------------------------------------------------------------------------- | |||
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120 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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121 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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122 | -- | |||
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123 | SIGNAL errorn : STD_LOGIC; | |||
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124 | -- UART AHB --------------------------------------------------------------- | |||
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125 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data | |||
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126 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data | |||
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127 | ||||
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128 | -- UART APB --------------------------------------------------------------- | |||
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129 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data | |||
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130 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data | |||
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131 | -- | |||
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132 | SIGNAL I00_s : STD_LOGIC; | |||
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133 | ||||
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134 | -- CONSTANTS | |||
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135 | CONSTANT CFG_PADTECH : INTEGER := inferred; | |||
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136 | -- | |||
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137 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f | |||
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138 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; | |||
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139 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker | |||
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140 | ||||
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141 | SIGNAL apbi_ext : apb_slv_in_type; | |||
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142 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); | |||
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143 | SIGNAL ahbi_s_ext : ahb_slv_in_type; | |||
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144 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); | |||
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145 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |||
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146 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); | |||
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147 | ||||
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148 | -- Spacewire signals | |||
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149 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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150 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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151 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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152 | SIGNAL spw_rxtxclk : STD_ULOGIC; | |||
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153 | SIGNAL spw_rxclkn : STD_ULOGIC; | |||
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154 | SIGNAL spw_clk : STD_LOGIC; | |||
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155 | SIGNAL swni : grspw_in_type; | |||
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156 | SIGNAL swno : grspw_out_type; | |||
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157 | -- SIGNAL clkmn : STD_ULOGIC; | |||
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158 | -- SIGNAL txclk : STD_ULOGIC; | |||
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159 | ||||
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160 | --GPIO | |||
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161 | SIGNAL gpioi : gpio_in_type; | |||
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162 | SIGNAL gpioo : gpio_out_type; | |||
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163 | ||||
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164 | -- AD Converter ADS7886 | |||
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165 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |||
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166 | SIGNAL sample_val : STD_LOGIC; | |||
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167 | SIGNAL ADC_nCS_sig : STD_LOGIC; | |||
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168 | SIGNAL ADC_CLK_sig : STD_LOGIC; | |||
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169 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); | |||
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170 | ||||
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171 | SIGNAL bias_fail_sw_sig : STD_LOGIC; | |||
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172 | ||||
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173 | ----------------------------------------------------------------------------- | |||
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174 | ||||
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175 | BEGIN -- beh | |||
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176 | ||||
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177 | ----------------------------------------------------------------------------- | |||
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178 | -- CLK | |||
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179 | ----------------------------------------------------------------------------- | |||
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180 | ||||
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181 | PROCESS(clk_50) | |||
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182 | BEGIN | |||
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183 | IF clk_50'EVENT AND clk_50 = '1' THEN | |||
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184 | clk_50_s <= NOT clk_50_s; | |||
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185 | END IF; | |||
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186 | END PROCESS; | |||
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187 | ||||
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188 | PROCESS(clk_50_s) | |||
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189 | BEGIN | |||
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190 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN | |||
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191 | clk_25 <= NOT clk_25; | |||
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192 | END IF; | |||
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193 | END PROCESS; | |||
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194 | ||||
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195 | PROCESS(clk_49) | |||
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196 | BEGIN | |||
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197 | IF clk_49'EVENT AND clk_49 = '1' THEN | |||
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198 | clk_24 <= NOT clk_24; | |||
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199 | END IF; | |||
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200 | END PROCESS; | |||
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201 | ||||
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202 | ----------------------------------------------------------------------------- | |||
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203 | ||||
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204 | PROCESS (clk_25, reset) | |||
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205 | BEGIN -- PROCESS | |||
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206 | IF reset = '0' THEN -- asynchronous reset (active low) | |||
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207 | LED0 <= '0'; | |||
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208 | LED1 <= '0'; | |||
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209 | LED2 <= '0'; | |||
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210 | --IO1 <= '0'; | |||
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211 | --IO2 <= '1'; | |||
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212 | --IO3 <= '0'; | |||
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213 | --IO4 <= '0'; | |||
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214 | --IO5 <= '0'; | |||
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215 | --IO6 <= '0'; | |||
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216 | --IO7 <= '0'; | |||
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217 | --IO8 <= '0'; | |||
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218 | --IO9 <= '0'; | |||
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219 | --IO10 <= '0'; | |||
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220 | --IO11 <= '0'; | |||
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221 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |||
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222 | LED0 <= '0'; | |||
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223 | LED1 <= '1'; | |||
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224 | LED2 <= BP0; | |||
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225 | --IO1 <= '1'; | |||
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226 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; | |||
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227 | --IO3 <= ADC_SDO(0); | |||
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228 | --IO4 <= ADC_SDO(1); | |||
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229 | --IO5 <= ADC_SDO(2); | |||
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230 | --IO6 <= ADC_SDO(3); | |||
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231 | --IO7 <= ADC_SDO(4); | |||
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232 | --IO8 <= ADC_SDO(5); | |||
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233 | --IO9 <= ADC_SDO(6); | |||
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234 | --IO10 <= ADC_SDO(7); | |||
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235 | IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |||
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236 | END IF; | |||
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237 | END PROCESS; | |||
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238 | ||||
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239 | PROCESS (clk_24, reset) | |||
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240 | BEGIN -- PROCESS | |||
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241 | IF reset = '0' THEN -- asynchronous reset (active low) | |||
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242 | I00_s <= '0'; | |||
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243 | ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge | |||
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244 | I00_s <= NOT I00_s; | |||
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245 | END IF; | |||
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246 | END PROCESS; | |||
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247 | -- IO0 <= I00_s; | |||
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248 | ||||
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249 | --UARTs | |||
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250 | nCTS1 <= '1'; | |||
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251 | nCTS2 <= '1'; | |||
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252 | nDCD2 <= '1'; | |||
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253 | ||||
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254 | --EXT CONNECTOR | |||
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255 | ||||
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256 | --SPACE WIRE | |||
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257 | ||||
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258 | leon3_soc_1 : leon3_soc | |||
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259 | GENERIC MAP ( | |||
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260 | fabtech => apa3e, | |||
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261 | memtech => apa3e, | |||
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262 | padtech => inferred, | |||
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263 | clktech => inferred, | |||
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264 | disas => 0, | |||
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265 | dbguart => 0, | |||
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266 | pclow => 2, | |||
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267 | clk_freq => 25000, | |||
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268 | NB_CPU => 1, | |||
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269 | ENABLE_FPU => 1, | |||
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270 | FPU_NETLIST => 0, | |||
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271 | ENABLE_DSU => 1, | |||
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272 | ENABLE_AHB_UART => 1, | |||
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273 | ENABLE_APB_UART => 1, | |||
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274 | ENABLE_IRQMP => 1, | |||
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275 | ENABLE_GPT => 1, | |||
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276 | NB_AHB_MASTER => NB_AHB_MASTER, | |||
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277 | NB_AHB_SLAVE => NB_AHB_SLAVE, | |||
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278 | NB_APB_SLAVE => NB_APB_SLAVE) | |||
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279 | PORT MAP ( | |||
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280 | clk => clk_25, | |||
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281 | reset => reset, | |||
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282 | errorn => errorn, | |||
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283 | ahbrxd => TXD1, | |||
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284 | ahbtxd => RXD1, | |||
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285 | urxd1 => TXD2, | |||
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286 | utxd1 => RXD2, | |||
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287 | address => SRAM_A, | |||
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288 | data => SRAM_DQ, | |||
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289 | nSRAM_BE0 => SRAM_nBE(0), | |||
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290 | nSRAM_BE1 => SRAM_nBE(1), | |||
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291 | nSRAM_BE2 => SRAM_nBE(2), | |||
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292 | nSRAM_BE3 => SRAM_nBE(3), | |||
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293 | nSRAM_WE => SRAM_nWE, | |||
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294 | nSRAM_CE => SRAM_CE, | |||
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295 | nSRAM_OE => SRAM_nOE, | |||
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296 | ||||
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297 | apbi_ext => apbi_ext, | |||
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298 | apbo_ext => apbo_ext, | |||
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299 | ahbi_s_ext => ahbi_s_ext, | |||
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300 | ahbo_s_ext => ahbo_s_ext, | |||
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301 | ahbi_m_ext => ahbi_m_ext, | |||
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302 | ahbo_m_ext => ahbo_m_ext); | |||
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303 | ||||
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304 | ------------------------------------------------------------------------------- | |||
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305 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- | |||
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306 | ------------------------------------------------------------------------------- | |||
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307 | apb_lfr_time_management_1 : apb_lfr_time_management | |||
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308 | GENERIC MAP ( | |||
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309 | pindex => 6, | |||
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310 | paddr => 6, | |||
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311 | pmask => 16#fff#, | |||
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312 | pirq => 12, | |||
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313 | nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375 | |||
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314 | PORT MAP ( | |||
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315 | clk25MHz => clk_25, | |||
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316 | clk49_152MHz => clk_24, -- 49.152MHz/2 | |||
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317 | resetn => reset, | |||
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318 | grspw_tick => swno.tickout, | |||
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319 | apbi => apbi_ext, | |||
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320 | apbo => apbo_ext(6), | |||
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321 | coarse_time => coarse_time, | |||
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322 | fine_time => fine_time); | |||
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323 | ||||
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324 | ----------------------------------------------------------------------- | |||
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325 | --- SpaceWire -------------------------------------------------------- | |||
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326 | ----------------------------------------------------------------------- | |||
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327 | ||||
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328 | SPW_EN <= '1'; | |||
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329 | ||||
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330 | spw_clk <= clk_50_s; | |||
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331 | spw_rxtxclk <= spw_clk; | |||
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332 | spw_rxclkn <= NOT spw_rxtxclk; | |||
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333 | ||||
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334 | -- PADS for SPW1 | |||
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335 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) | |||
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336 | PORT MAP (SPW_NOM_DIN, dtmp(0)); | |||
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337 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) | |||
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338 | PORT MAP (SPW_NOM_SIN, stmp(0)); | |||
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339 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) | |||
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340 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); | |||
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341 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) | |||
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342 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); | |||
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343 | -- PADS FOR SPW2 | |||
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344 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |||
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345 | PORT MAP (SPW_RED_SIN, dtmp(1)); | |||
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346 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |||
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347 | PORT MAP (SPW_RED_DIN, stmp(1)); | |||
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348 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) | |||
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349 | PORT MAP (SPW_RED_DOUT, swno.d(1)); | |||
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350 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) | |||
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351 | PORT MAP (SPW_RED_SOUT, swno.s(1)); | |||
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352 | ||||
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353 | -- GRSPW PHY | |||
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354 | --spw1_input: if CFG_SPW_GRSPW = 1 generate | |||
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355 | spw_inputloop : FOR j IN 0 TO 1 GENERATE | |||
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356 | spw_phy0 : grspw_phy | |||
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357 | GENERIC MAP( | |||
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358 | tech => apa3e, | |||
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359 | rxclkbuftype => 1, | |||
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360 | scantest => 0) | |||
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361 | PORT MAP( | |||
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362 | rxrst => swno.rxrst, | |||
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363 | di => dtmp(j), | |||
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364 | si => stmp(j), | |||
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365 | rxclko => spw_rxclk(j), | |||
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366 | do => swni.d(j), | |||
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367 | ndo => swni.nd(j*5+4 DOWNTO j*5), | |||
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368 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); | |||
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369 | END GENERATE spw_inputloop; | |||
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370 | ||||
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371 | -- SPW core | |||
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372 | sw0 : grspwm GENERIC MAP( | |||
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373 | tech => apa3e, | |||
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374 | hindex => 1, | |||
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375 | pindex => 5, | |||
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376 | paddr => 5, | |||
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377 | pirq => 11, | |||
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378 | sysfreq => 25000, -- CPU_FREQ | |||
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379 | rmap => 1, | |||
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380 | rmapcrc => 1, | |||
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381 | fifosize1 => 16, | |||
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382 | fifosize2 => 16, | |||
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383 | rxclkbuftype => 1, | |||
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384 | rxunaligned => 0, | |||
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385 | rmapbufs => 4, | |||
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386 | ft => 0, | |||
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387 | netlist => 0, | |||
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388 | ports => 2, | |||
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389 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 | |||
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390 | memtech => apa3e, | |||
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391 | destkey => 2, | |||
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392 | spwcore => 1 | |||
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393 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 | |||
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394 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 | |||
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395 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 | |||
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396 | ) | |||
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397 | PORT MAP(reset, clk_25, spw_rxclk(0), | |||
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398 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, | |||
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399 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), | |||
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400 | swni, swno); | |||
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401 | ||||
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402 | swni.tickin <= '0'; | |||
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403 | swni.rmapen <= '1'; | |||
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404 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz | |||
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405 | swni.tickinraw <= '0'; | |||
|
406 | swni.timein <= (OTHERS => '0'); | |||
|
407 | swni.dcrstval <= (OTHERS => '0'); | |||
|
408 | swni.timerrstval <= (OTHERS => '0'); | |||
|
409 | ||||
|
410 | ------------------------------------------------------------------------------- | |||
|
411 | -- LFR ------------------------------------------------------------------------ | |||
|
412 | ------------------------------------------------------------------------------- | |||
|
413 | lpp_lfr_1 : lpp_lfr | |||
|
414 | GENERIC MAP ( | |||
|
415 | Mem_use => use_RAM, | |||
|
416 | nb_data_by_buffer_size => 32, | |||
|
417 | nb_word_by_buffer_size => 30, | |||
|
418 | nb_snapshot_param_size => 32, | |||
|
419 | delta_vector_size => 32, | |||
|
420 | delta_vector_size_f0_2 => 7, -- log2(96) | |||
|
421 | pindex => 15, | |||
|
422 | paddr => 15, | |||
|
423 | pmask => 16#fff#, | |||
|
424 | pirq_ms => 6, | |||
|
425 | pirq_wfp => 14, | |||
|
426 | hindex => 2, | |||
|
427 | top_lfr_version => X"000101") -- aa.bb.cc version | |||
|
428 | PORT MAP ( | |||
|
429 | clk => clk_25, | |||
|
430 | rstn => reset, | |||
|
431 | sample_B => sample(2 DOWNTO 0), | |||
|
432 | sample_E => sample(7 DOWNTO 3), | |||
|
433 | sample_val => sample_val, | |||
|
434 | apbi => apbi_ext, | |||
|
435 | apbo => apbo_ext(15), | |||
|
436 | ahbi => ahbi_m_ext, | |||
|
437 | ahbo => ahbo_m_ext(2), | |||
|
438 | coarse_time => coarse_time, | |||
|
439 | fine_time => fine_time, | |||
|
440 | data_shaping_BW => bias_fail_sw_sig); | |||
|
441 | ||||
|
442 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 | |||
|
443 | GENERIC MAP( | |||
|
444 | ChannelCount => 8, | |||
|
445 | SampleNbBits => 14, | |||
|
446 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 | |||
|
447 | ncycle_cnv => 250) -- 49 152 000 / 98304 /2 | |||
|
448 | PORT MAP ( | |||
|
449 | -- CONV | |||
|
450 | cnv_clk => clk_24, | |||
|
451 | cnv_rstn => reset, | |||
|
452 | cnv => ADC_nCS_sig, | |||
|
453 | -- DATA | |||
|
454 | clk => clk_25, | |||
|
455 | rstn => reset, | |||
|
456 | sck => ADC_CLK_sig, | |||
|
457 | sdo => ADC_SDO_sig, | |||
|
458 | -- SAMPLE | |||
|
459 | sample => sample, | |||
|
460 | sample_val => sample_val); | |||
|
461 | ||||
|
462 | IO10 <= ADC_SDO_sig(5); | |||
|
463 | IO9 <= ADC_SDO_sig(4); | |||
|
464 | IO8 <= ADC_SDO_sig(3); | |||
|
465 | ||||
|
466 | ADC_nCS <= ADC_nCS_sig; | |||
|
467 | ADC_CLK <= ADC_CLK_sig; | |||
|
468 | ADC_SDO_sig <= ADC_SDO; | |||
|
469 | ||||
|
470 | ---------------------------------------------------------------------- | |||
|
471 | --- GPIO ----------------------------------------------------------- | |||
|
472 | ---------------------------------------------------------------------- | |||
|
473 | ||||
|
474 | grgpio0 : grgpio | |||
|
475 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) | |||
|
476 | PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); | |||
|
477 | ||||
|
478 | pio_pad_0 : iopad | |||
|
479 | GENERIC MAP (tech => CFG_PADTECH) | |||
|
480 | PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); | |||
|
481 | pio_pad_1 : iopad | |||
|
482 | GENERIC MAP (tech => CFG_PADTECH) | |||
|
483 | PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); | |||
|
484 | pio_pad_2 : iopad | |||
|
485 | GENERIC MAP (tech => CFG_PADTECH) | |||
|
486 | PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); | |||
|
487 | pio_pad_3 : iopad | |||
|
488 | GENERIC MAP (tech => CFG_PADTECH) | |||
|
489 | PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); | |||
|
490 | pio_pad_4 : iopad | |||
|
491 | GENERIC MAP (tech => CFG_PADTECH) | |||
|
492 | PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); | |||
|
493 | pio_pad_5 : iopad | |||
|
494 | GENERIC MAP (tech => CFG_PADTECH) | |||
|
495 | PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); | |||
|
496 | pio_pad_6 : iopad | |||
|
497 | GENERIC MAP (tech => CFG_PADTECH) | |||
|
498 | PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); | |||
|
499 | pio_pad_7 : iopad | |||
|
500 | GENERIC MAP (tech => CFG_PADTECH) | |||
|
501 | PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); | |||
|
502 | ||||
|
503 | END beh; |
@@ -0,0 +1,46 | |||||
|
1 | VHDLIB=../.. | |||
|
2 | SCRIPTSDIR=$(VHDLIB)/scripts/ | |||
|
3 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) | |||
|
4 | TOP=MINI_LFR_top | |||
|
5 | BOARD=MINI-LFR | |||
|
6 | include $(VHDLIB)/boards/$(BOARD)/Makefile.inc | |||
|
7 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) | |||
|
8 | UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf | |||
|
9 | QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf | |||
|
10 | EFFORT=high | |||
|
11 | XSTOPT= | |||
|
12 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" | |||
|
13 | VHDLSYNFILES= MINI_LFR_top.vhd | |||
|
14 | ||||
|
15 | PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc | |||
|
16 | BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut | |||
|
17 | CLEAN=soft-clean | |||
|
18 | ||||
|
19 | TECHLIBS = proasic3e | |||
|
20 | ||||
|
21 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ | |||
|
22 | tmtc openchip hynix ihp gleichmann micron usbhc | |||
|
23 | ||||
|
24 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ | |||
|
25 | pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ | |||
|
26 | ./amba_lcd_16x2_ctrlr \ | |||
|
27 | ./general_purpose/lpp_AMR \ | |||
|
28 | ./general_purpose/lpp_balise \ | |||
|
29 | ./general_purpose/lpp_delay \ | |||
|
30 | ./lpp_bootloader \ | |||
|
31 | ./lpp_cna \ | |||
|
32 | ./lpp_uart \ | |||
|
33 | ./lpp_usb \ | |||
|
34 | ./lpp_sim/CY7C1061DV33 \ | |||
|
35 | ||||
|
36 | FILESKIP =i2cmst.vhd \ | |||
|
37 | APB_MULTI_DIODE.vhd \ | |||
|
38 | APB_SIMPLE_DIODE.vhd \ | |||
|
39 | Top_MatrixSpec.vhd \ | |||
|
40 | APB_FFT.vhd | |||
|
41 | ||||
|
42 | include $(GRLIB)/bin/Makefile | |||
|
43 | include $(GRLIB)/software/leon3/Makefile | |||
|
44 | ||||
|
45 | ################## project specific targets ########################## | |||
|
46 |
@@ -8,6 +8,8 vcom -quiet -93 -work lpp ../../../grl | |||||
8 |
|
8 | |||
9 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd |
|
9 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd | |
10 |
|
10 | |||
|
11 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd | |||
|
12 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd | |||
11 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_test.vhd |
|
13 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_test.vhd | |
12 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd |
|
14 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd | |
13 |
|
15 | |||
@@ -21,6 +23,6 vsim work.testbench | |||||
21 |
|
23 | |||
22 | log -r * |
|
24 | log -r * | |
23 |
|
25 | |||
24 |
do wave_ |
|
26 | do wave_ms.do | |
25 |
|
27 | |||
26 |
run |
|
28 | run 2 ms |
@@ -314,24 +314,24 BEGIN | |||||
314 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
|
314 | ahb0 : ahbctrl -- AHB arbiter/multiplexer | |
315 | GENERIC MAP (defmast => 0, split => 0, |
|
315 | GENERIC MAP (defmast => 0, split => 0, | |
316 | rrobin => 1, ioaddr => 16#FFF#, |
|
316 | rrobin => 1, ioaddr => 16#FFF#, | |
317 |
ioen => 0, nahbm => 2, nahbs => |
|
317 | ioen => 0, nahbm => 2, nahbs => 4) | |
318 | PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso); |
|
318 | PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso); | |
319 |
|
319 | |||
320 |
|
320 | |||
321 |
|
321 | |||
322 | --- AHB RAM ---------------------------------------------------------- |
|
322 | --- AHB RAM ---------------------------------------------------------- | |
323 |
|
|
323 | ahbram0 : ahbram | |
324 |
|
|
324 | GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0) | |
325 |
|
|
325 | PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0)); | |
326 |
|
|
326 | ahbram1 : ahbram | |
327 |
|
|
327 | GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0) | |
328 |
|
|
328 | PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1)); | |
329 |
|
|
329 | ahbram2 : ahbram | |
330 |
|
|
330 | GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0) | |
331 |
|
|
331 | PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2)); | |
332 |
|
|
332 | ahbram3 : ahbram | |
333 |
|
|
333 | GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0) | |
334 |
|
|
334 | PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3)); | |
335 |
|
335 | |||
336 | ----------------------------------------------------------------------------- |
|
336 | ----------------------------------------------------------------------------- | |
337 | ---------------------------------------------------------------------- |
|
337 | ---------------------------------------------------------------------- | |
@@ -501,7 +501,7 BEGIN | |||||
501 | ----------------------------------------------------------------------------- |
|
501 | ----------------------------------------------------------------------------- | |
502 | -- IRQ |
|
502 | -- IRQ | |
503 | ----------------------------------------------------------------------------- |
|
503 | ----------------------------------------------------------------------------- | |
504 | PROCESS |
|
504 | PROCESS (clk25MHz, rstn) | |
505 | BEGIN -- PROCESS |
|
505 | BEGIN -- PROCESS | |
506 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
506 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
507 |
|
507 |
@@ -17,6 +17,7 SYNC_FF.vhd | |||||
17 | Shifter.vhd |
|
17 | Shifter.vhd | |
18 | TwoComplementer.vhd |
|
18 | TwoComplementer.vhd | |
19 | Clock_Divider.vhd |
|
19 | Clock_Divider.vhd | |
|
20 | lpp_front_to_level.vhd | |||
20 | lpp_front_detection.vhd |
|
21 | lpp_front_detection.vhd | |
21 | lpp_front_positive_detection.vhd |
|
22 | lpp_front_positive_detection.vhd | |
22 | SYNC_VALID_BIT.vhd |
|
23 | SYNC_VALID_BIT.vhd |
@@ -40,7 +40,7 PACKAGE apb_devices_list IS | |||||
40 | CONSTANT LPP_CLKSETTING : amba_device_type := 16#20#; |
|
40 | CONSTANT LPP_CLKSETTING : amba_device_type := 16#20#; | |
41 |
|
41 | |||
42 | CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#; |
|
42 | CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#; | |
43 |
CONSTANT LPP_DEBUG_LFR |
|
43 | CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#; | |
44 |
|
44 | |||
45 | CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A2#; |
|
45 | CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A2#; | |
46 |
|
46 |
This diff has been collapsed as it changes many lines, (1531 lines changed) Show them Hide them | |||||
@@ -1,762 +1,769 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 | USE ieee.numeric_std.ALL; |
|
3 | USE ieee.numeric_std.ALL; | |
4 |
|
4 | |||
5 | LIBRARY lpp; |
|
5 | LIBRARY lpp; | |
6 | USE lpp.lpp_ad_conv.ALL; |
|
6 | USE lpp.lpp_ad_conv.ALL; | |
7 | USE lpp.iir_filter.ALL; |
|
7 | USE lpp.iir_filter.ALL; | |
8 | USE lpp.FILTERcfg.ALL; |
|
8 | USE lpp.FILTERcfg.ALL; | |
9 | USE lpp.lpp_memory.ALL; |
|
9 | USE lpp.lpp_memory.ALL; | |
10 | USE lpp.lpp_waveform_pkg.ALL; |
|
10 | USE lpp.lpp_waveform_pkg.ALL; | |
11 | USE lpp.lpp_dma_pkg.ALL; |
|
11 | USE lpp.lpp_dma_pkg.ALL; | |
12 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
12 | USE lpp.lpp_top_lfr_pkg.ALL; | |
13 | USE lpp.lpp_lfr_pkg.ALL; |
|
13 | USE lpp.lpp_lfr_pkg.ALL; | |
14 | USE lpp.general_purpose.ALL; |
|
14 | USE lpp.general_purpose.ALL; | |
15 |
|
15 | |||
16 | LIBRARY techmap; |
|
16 | LIBRARY techmap; | |
17 | USE techmap.gencomp.ALL; |
|
17 | USE techmap.gencomp.ALL; | |
18 |
|
18 | |||
19 | LIBRARY grlib; |
|
19 | LIBRARY grlib; | |
20 | USE grlib.amba.ALL; |
|
20 | USE grlib.amba.ALL; | |
21 | USE grlib.stdlib.ALL; |
|
21 | USE grlib.stdlib.ALL; | |
22 | USE grlib.devices.ALL; |
|
22 | USE grlib.devices.ALL; | |
23 | USE GRLIB.DMA2AHB_Package.ALL; |
|
23 | USE GRLIB.DMA2AHB_Package.ALL; | |
24 |
|
24 | |||
25 | ENTITY lpp_lfr IS |
|
25 | ENTITY lpp_lfr IS | |
26 | GENERIC ( |
|
26 | GENERIC ( | |
27 | Mem_use : INTEGER := use_RAM; |
|
27 | Mem_use : INTEGER := use_RAM; | |
28 | nb_data_by_buffer_size : INTEGER := 11; |
|
28 | nb_data_by_buffer_size : INTEGER := 11; | |
29 | nb_word_by_buffer_size : INTEGER := 11; |
|
29 | nb_word_by_buffer_size : INTEGER := 11; | |
30 | nb_snapshot_param_size : INTEGER := 11; |
|
30 | nb_snapshot_param_size : INTEGER := 11; | |
31 | delta_vector_size : INTEGER := 20; |
|
31 | delta_vector_size : INTEGER := 20; | |
32 | delta_vector_size_f0_2 : INTEGER := 7; |
|
32 | delta_vector_size_f0_2 : INTEGER := 7; | |
33 |
|
33 | |||
34 | pindex : INTEGER := 4; |
|
34 | pindex : INTEGER := 4; | |
35 | paddr : INTEGER := 4; |
|
35 | paddr : INTEGER := 4; | |
36 | pmask : INTEGER := 16#fff#; |
|
36 | pmask : INTEGER := 16#fff#; | |
37 | pirq_ms : INTEGER := 0; |
|
37 | pirq_ms : INTEGER := 0; | |
38 | pirq_wfp : INTEGER := 1; |
|
38 | pirq_wfp : INTEGER := 1; | |
39 |
|
39 | |||
40 | hindex : INTEGER := 2; |
|
40 | hindex : INTEGER := 2; | |
41 |
|
41 | |||
42 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0') |
|
42 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0') | |
43 |
|
43 | |||
44 | ); |
|
44 | ); | |
45 | PORT ( |
|
45 | PORT ( | |
46 | clk : IN STD_LOGIC; |
|
46 | clk : IN STD_LOGIC; | |
47 | rstn : IN STD_LOGIC; |
|
47 | rstn : IN STD_LOGIC; | |
48 | -- SAMPLE |
|
48 | -- SAMPLE | |
49 | sample_B : IN Samples14v(2 DOWNTO 0); |
|
49 | sample_B : IN Samples14v(2 DOWNTO 0); | |
50 | sample_E : IN Samples14v(4 DOWNTO 0); |
|
50 | sample_E : IN Samples14v(4 DOWNTO 0); | |
51 | sample_val : IN STD_LOGIC; |
|
51 | sample_val : IN STD_LOGIC; | |
52 | -- APB |
|
52 | -- APB | |
53 | apbi : IN apb_slv_in_type; |
|
53 | apbi : IN apb_slv_in_type; | |
54 | apbo : OUT apb_slv_out_type; |
|
54 | apbo : OUT apb_slv_out_type; | |
55 | -- AHB |
|
55 | -- AHB | |
56 | ahbi : IN AHB_Mst_In_Type; |
|
56 | ahbi : IN AHB_Mst_In_Type; | |
57 | ahbo : OUT AHB_Mst_Out_Type; |
|
57 | ahbo : OUT AHB_Mst_Out_Type; | |
58 | -- TIME |
|
58 | -- TIME | |
59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
61 | -- |
|
61 | -- | |
62 |
data_shaping_BW : OUT STD_LOGIC |
|
62 | data_shaping_BW : OUT STD_LOGIC; | |
63 | -- |
|
63 | -- | |
64 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
64 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
65 |
|
65 | |||
66 | --debug |
|
66 | --debug | |
67 | --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
67 | --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
68 | --debug_f0_data_valid : OUT STD_LOGIC; |
|
68 | --debug_f0_data_valid : OUT STD_LOGIC; | |
69 | --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
69 | --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
70 | --debug_f1_data_valid : OUT STD_LOGIC; |
|
70 | --debug_f1_data_valid : OUT STD_LOGIC; | |
71 | --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
71 | --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
72 | --debug_f2_data_valid : OUT STD_LOGIC; |
|
72 | --debug_f2_data_valid : OUT STD_LOGIC; | |
73 | --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
73 | --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
74 | --debug_f3_data_valid : OUT STD_LOGIC; |
|
74 | --debug_f3_data_valid : OUT STD_LOGIC; | |
75 |
|
75 | |||
76 | ---- debug FIFO_IN |
|
76 | ---- debug FIFO_IN | |
77 | --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
77 | --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
78 | --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; |
|
78 | --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; | |
79 | --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
79 | --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
80 | --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; |
|
80 | --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; | |
81 | --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
81 | --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
82 | --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; |
|
82 | --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; | |
83 | --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
83 | --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
84 | --debug_f3_data_fifo_in_valid : OUT STD_LOGIC; |
|
84 | --debug_f3_data_fifo_in_valid : OUT STD_LOGIC; | |
85 |
|
85 | |||
86 | ----debug FIFO OUT |
|
86 | ----debug FIFO OUT | |
87 | --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
87 | --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
88 | --debug_f0_data_fifo_out_valid : OUT STD_LOGIC; |
|
88 | --debug_f0_data_fifo_out_valid : OUT STD_LOGIC; | |
89 | --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
89 | --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
90 | --debug_f1_data_fifo_out_valid : OUT STD_LOGIC; |
|
90 | --debug_f1_data_fifo_out_valid : OUT STD_LOGIC; | |
91 | --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
92 | --debug_f2_data_fifo_out_valid : OUT STD_LOGIC; |
|
92 | --debug_f2_data_fifo_out_valid : OUT STD_LOGIC; | |
93 | --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
93 | --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
94 | --debug_f3_data_fifo_out_valid : OUT STD_LOGIC; |
|
94 | --debug_f3_data_fifo_out_valid : OUT STD_LOGIC; | |
95 |
|
95 | |||
96 | ----debug DMA IN |
|
96 | ----debug DMA IN | |
97 | --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
97 | --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
98 | --debug_f0_data_dma_in_valid : OUT STD_LOGIC; |
|
98 | --debug_f0_data_dma_in_valid : OUT STD_LOGIC; | |
99 | --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
99 | --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
100 | --debug_f1_data_dma_in_valid : OUT STD_LOGIC; |
|
100 | --debug_f1_data_dma_in_valid : OUT STD_LOGIC; | |
101 | --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
101 | --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
102 | --debug_f2_data_dma_in_valid : OUT STD_LOGIC; |
|
102 | --debug_f2_data_dma_in_valid : OUT STD_LOGIC; | |
103 | --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
103 | --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
104 | --debug_f3_data_dma_in_valid : OUT STD_LOGIC |
|
104 | --debug_f3_data_dma_in_valid : OUT STD_LOGIC | |
105 | ); |
|
105 | ); | |
106 | END lpp_lfr; |
|
106 | END lpp_lfr; | |
107 |
|
107 | |||
108 | ARCHITECTURE beh OF lpp_lfr IS |
|
108 | ARCHITECTURE beh OF lpp_lfr IS | |
109 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
|
109 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
110 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
|
110 | SIGNAL sample_s : Samples(7 DOWNTO 0); | |
111 | -- |
|
111 | -- | |
112 | SIGNAL data_shaping_SP0 : STD_LOGIC; |
|
112 | SIGNAL data_shaping_SP0 : STD_LOGIC; | |
113 | SIGNAL data_shaping_SP1 : STD_LOGIC; |
|
113 | SIGNAL data_shaping_SP1 : STD_LOGIC; | |
114 | SIGNAL data_shaping_R0 : STD_LOGIC; |
|
114 | SIGNAL data_shaping_R0 : STD_LOGIC; | |
115 | SIGNAL data_shaping_R1 : STD_LOGIC; |
|
115 | SIGNAL data_shaping_R1 : STD_LOGIC; | |
116 | -- |
|
116 | -- | |
117 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
117 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
118 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
118 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
119 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
119 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
120 | -- |
|
120 | -- | |
121 | SIGNAL sample_f0_val : STD_LOGIC; |
|
121 | SIGNAL sample_f0_val : STD_LOGIC; | |
122 | SIGNAL sample_f1_val : STD_LOGIC; |
|
122 | SIGNAL sample_f1_val : STD_LOGIC; | |
123 | SIGNAL sample_f2_val : STD_LOGIC; |
|
123 | SIGNAL sample_f2_val : STD_LOGIC; | |
124 | SIGNAL sample_f3_val : STD_LOGIC; |
|
124 | SIGNAL sample_f3_val : STD_LOGIC; | |
125 | -- |
|
125 | -- | |
126 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
126 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
127 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
127 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
128 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
128 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
129 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
129 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
130 | -- |
|
130 | -- | |
131 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
131 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
132 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
132 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
133 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
133 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
134 |
|
134 | |||
135 | -- SM |
|
135 | -- SM | |
136 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; |
|
136 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; | |
137 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; |
|
137 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; | |
138 | SIGNAL ready_matrix_f1 : STD_LOGIC; |
|
138 | SIGNAL ready_matrix_f1 : STD_LOGIC; | |
139 | SIGNAL ready_matrix_f2 : STD_LOGIC; |
|
139 | SIGNAL ready_matrix_f2 : STD_LOGIC; | |
140 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; |
|
140 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; | |
141 | SIGNAL error_bad_component_error : STD_LOGIC; |
|
141 | SIGNAL error_bad_component_error : STD_LOGIC; | |
142 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
142 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
143 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; |
|
143 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; | |
144 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; |
|
144 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; | |
145 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; |
|
145 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; | |
146 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; |
|
146 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; | |
147 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; |
|
147 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; | |
148 | SIGNAL status_error_bad_component_error : STD_LOGIC; |
|
148 | SIGNAL status_error_bad_component_error : STD_LOGIC; | |
149 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; |
|
149 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; | |
150 | SIGNAL config_active_interruption_onError : STD_LOGIC; |
|
150 | SIGNAL config_active_interruption_onError : STD_LOGIC; | |
151 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
151 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
152 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
152 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
153 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
153 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
154 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
154 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
155 |
|
155 | |||
156 | -- WFP |
|
156 | -- WFP | |
157 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
157 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
158 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
158 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
159 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
159 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
160 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
160 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
161 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
161 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
162 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
162 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
163 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
163 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
164 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
164 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
165 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
165 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
166 |
|
166 | |||
167 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
167 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
168 | SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
168 | SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
169 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
169 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
170 | SIGNAL enable_f0 : STD_LOGIC; |
|
170 | SIGNAL enable_f0 : STD_LOGIC; | |
171 | SIGNAL enable_f1 : STD_LOGIC; |
|
171 | SIGNAL enable_f1 : STD_LOGIC; | |
172 | SIGNAL enable_f2 : STD_LOGIC; |
|
172 | SIGNAL enable_f2 : STD_LOGIC; | |
173 | SIGNAL enable_f3 : STD_LOGIC; |
|
173 | SIGNAL enable_f3 : STD_LOGIC; | |
174 | SIGNAL burst_f0 : STD_LOGIC; |
|
174 | SIGNAL burst_f0 : STD_LOGIC; | |
175 | SIGNAL burst_f1 : STD_LOGIC; |
|
175 | SIGNAL burst_f1 : STD_LOGIC; | |
176 | SIGNAL burst_f2 : STD_LOGIC; |
|
176 | SIGNAL burst_f2 : STD_LOGIC; | |
177 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
177 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
178 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
178 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
179 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
179 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
180 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
180 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
181 |
|
181 | |||
182 | SIGNAL run : STD_LOGIC; |
|
182 | SIGNAL run : STD_LOGIC; | |
183 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
183 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
184 |
|
184 | |||
185 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
185 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
186 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
186 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
187 | SIGNAL data_f0_data_out_valid : STD_LOGIC; |
|
187 | SIGNAL data_f0_data_out_valid : STD_LOGIC; | |
188 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; |
|
188 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; | |
189 | SIGNAL data_f0_data_out_ren : STD_LOGIC; |
|
189 | SIGNAL data_f0_data_out_ren : STD_LOGIC; | |
190 | --f1 |
|
190 | --f1 | |
191 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
191 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
192 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
192 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
193 | SIGNAL data_f1_data_out_valid : STD_LOGIC; |
|
193 | SIGNAL data_f1_data_out_valid : STD_LOGIC; | |
194 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; |
|
194 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; | |
195 | SIGNAL data_f1_data_out_ren : STD_LOGIC; |
|
195 | SIGNAL data_f1_data_out_ren : STD_LOGIC; | |
196 | --f2 |
|
196 | --f2 | |
197 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
197 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
198 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
198 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
199 | SIGNAL data_f2_data_out_valid : STD_LOGIC; |
|
199 | SIGNAL data_f2_data_out_valid : STD_LOGIC; | |
200 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; |
|
200 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; | |
201 | SIGNAL data_f2_data_out_ren : STD_LOGIC; |
|
201 | SIGNAL data_f2_data_out_ren : STD_LOGIC; | |
202 | --f3 |
|
202 | --f3 | |
203 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
203 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
204 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
204 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
205 | SIGNAL data_f3_data_out_valid : STD_LOGIC; |
|
205 | SIGNAL data_f3_data_out_valid : STD_LOGIC; | |
206 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; |
|
206 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; | |
207 | SIGNAL data_f3_data_out_ren : STD_LOGIC; |
|
207 | SIGNAL data_f3_data_out_ren : STD_LOGIC; | |
208 |
|
208 | |||
209 | ----------------------------------------------------------------------------- |
|
209 | ----------------------------------------------------------------------------- | |
210 | -- |
|
210 | -- | |
211 | ----------------------------------------------------------------------------- |
|
211 | ----------------------------------------------------------------------------- | |
212 | SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
212 | SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
213 | SIGNAL data_f0_data_out_valid_s : STD_LOGIC; |
|
213 | SIGNAL data_f0_data_out_valid_s : STD_LOGIC; | |
214 | SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; |
|
214 | SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; | |
215 | --f1 |
|
215 | --f1 | |
216 | SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
216 | SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
217 | SIGNAL data_f1_data_out_valid_s : STD_LOGIC; |
|
217 | SIGNAL data_f1_data_out_valid_s : STD_LOGIC; | |
218 | SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; |
|
218 | SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; | |
219 | --f2 |
|
219 | --f2 | |
220 | SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
220 | SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
221 | SIGNAL data_f2_data_out_valid_s : STD_LOGIC; |
|
221 | SIGNAL data_f2_data_out_valid_s : STD_LOGIC; | |
222 | SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; |
|
222 | SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; | |
223 | --f3 |
|
223 | --f3 | |
224 | SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
224 | SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
225 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; |
|
225 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; | |
226 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; |
|
226 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; | |
227 |
|
227 | |||
228 | ----------------------------------------------------------------------------- |
|
228 | ----------------------------------------------------------------------------- | |
229 | -- DMA RR |
|
229 | -- DMA RR | |
230 | ----------------------------------------------------------------------------- |
|
230 | ----------------------------------------------------------------------------- | |
231 | SIGNAL dma_sel_valid : STD_LOGIC; |
|
231 | SIGNAL dma_sel_valid : STD_LOGIC; | |
232 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
232 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
233 | SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
233 | SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
234 | SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
234 | SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
235 | SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
235 | SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
236 |
|
236 | |||
237 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
237 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
238 | SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
238 | SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
239 |
|
239 | |||
240 | ----------------------------------------------------------------------------- |
|
240 | ----------------------------------------------------------------------------- | |
241 | -- DMA_REG |
|
241 | -- DMA_REG | |
242 | ----------------------------------------------------------------------------- |
|
242 | ----------------------------------------------------------------------------- | |
243 | SIGNAL ongoing_reg : STD_LOGIC; |
|
243 | SIGNAL ongoing_reg : STD_LOGIC; | |
244 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
244 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
245 | SIGNAL dma_send_reg : STD_LOGIC; |
|
245 | SIGNAL dma_send_reg : STD_LOGIC; | |
246 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
246 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
247 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
247 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
248 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
248 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
249 |
|
249 | |||
250 |
|
250 | |||
251 | ----------------------------------------------------------------------------- |
|
251 | ----------------------------------------------------------------------------- | |
252 | -- DMA |
|
252 | -- DMA | |
253 | ----------------------------------------------------------------------------- |
|
253 | ----------------------------------------------------------------------------- | |
254 | SIGNAL dma_send : STD_LOGIC; |
|
254 | SIGNAL dma_send : STD_LOGIC; | |
255 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
255 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
256 | SIGNAL dma_done : STD_LOGIC; |
|
256 | SIGNAL dma_done : STD_LOGIC; | |
257 | SIGNAL dma_ren : STD_LOGIC; |
|
257 | SIGNAL dma_ren : STD_LOGIC; | |
258 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
258 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
259 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
259 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
260 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
260 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
261 |
|
261 | |||
262 | ----------------------------------------------------------------------------- |
|
262 | ----------------------------------------------------------------------------- | |
263 | -- DEBUG |
|
263 | -- DEBUG | |
264 | ----------------------------------------------------------------------------- |
|
264 | ----------------------------------------------------------------------------- | |
265 | -- |
|
265 | -- | |
266 | SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
266 | SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
267 | SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
267 | SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
268 | SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
268 | SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
269 | SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
269 | SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
270 |
|
270 | |||
271 | SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
271 | SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
272 | SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
272 | SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
273 | SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
273 | SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
274 | SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
274 | SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
275 | SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
275 | SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
276 | SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
276 | SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
277 | SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
277 | SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
278 | SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
278 | SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
279 |
|
279 | |||
280 | ----------------------------------------------------------------------------- |
|
280 | ----------------------------------------------------------------------------- | |
281 | -- MS |
|
281 | -- MS | |
282 | ----------------------------------------------------------------------------- |
|
282 | ----------------------------------------------------------------------------- | |
283 |
|
283 | |||
284 | SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
284 | SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
285 | SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
285 | SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
286 | SIGNAL data_ms_valid : STD_LOGIC; |
|
286 | SIGNAL data_ms_valid : STD_LOGIC; | |
287 | SIGNAL data_ms_valid_burst : STD_LOGIC; |
|
287 | SIGNAL data_ms_valid_burst : STD_LOGIC; | |
288 | SIGNAL data_ms_ren : STD_LOGIC; |
|
288 | SIGNAL data_ms_ren : STD_LOGIC; | |
289 | SIGNAL data_ms_done : STD_LOGIC; |
|
289 | SIGNAL data_ms_done : STD_LOGIC; | |
290 |
|
290 | |||
291 | BEGIN |
|
291 | BEGIN | |
292 |
|
292 | |||
293 | sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); |
|
293 | sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); | |
294 | sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); |
|
294 | sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); | |
295 |
|
295 | |||
296 | all_channel : FOR i IN 7 DOWNTO 0 GENERATE |
|
296 | all_channel : FOR i IN 7 DOWNTO 0 GENERATE | |
297 | sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); |
|
297 | sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); | |
298 | END GENERATE all_channel; |
|
298 | END GENERATE all_channel; | |
299 |
|
299 | |||
300 | ----------------------------------------------------------------------------- |
|
300 | ----------------------------------------------------------------------------- | |
301 | lpp_lfr_filter_1 : lpp_lfr_filter |
|
301 | lpp_lfr_filter_1 : lpp_lfr_filter | |
302 | GENERIC MAP ( |
|
302 | GENERIC MAP ( | |
303 | Mem_use => Mem_use) |
|
303 | Mem_use => Mem_use) | |
304 | PORT MAP ( |
|
304 | PORT MAP ( | |
305 | sample => sample_s, |
|
305 | sample => sample_s, | |
306 | sample_val => sample_val, |
|
306 | sample_val => sample_val, | |
307 | clk => clk, |
|
307 | clk => clk, | |
308 | rstn => rstn, |
|
308 | rstn => rstn, | |
309 | data_shaping_SP0 => data_shaping_SP0, |
|
309 | data_shaping_SP0 => data_shaping_SP0, | |
310 | data_shaping_SP1 => data_shaping_SP1, |
|
310 | data_shaping_SP1 => data_shaping_SP1, | |
311 | data_shaping_R0 => data_shaping_R0, |
|
311 | data_shaping_R0 => data_shaping_R0, | |
312 | data_shaping_R1 => data_shaping_R1, |
|
312 | data_shaping_R1 => data_shaping_R1, | |
313 | sample_f0_val => sample_f0_val, |
|
313 | sample_f0_val => sample_f0_val, | |
314 | sample_f1_val => sample_f1_val, |
|
314 | sample_f1_val => sample_f1_val, | |
315 | sample_f2_val => sample_f2_val, |
|
315 | sample_f2_val => sample_f2_val, | |
316 | sample_f3_val => sample_f3_val, |
|
316 | sample_f3_val => sample_f3_val, | |
317 | sample_f0_wdata => sample_f0_data, |
|
317 | sample_f0_wdata => sample_f0_data, | |
318 | sample_f1_wdata => sample_f1_data, |
|
318 | sample_f1_wdata => sample_f1_data, | |
319 | sample_f2_wdata => sample_f2_data, |
|
319 | sample_f2_wdata => sample_f2_data, | |
320 | sample_f3_wdata => sample_f3_data); |
|
320 | sample_f3_wdata => sample_f3_data); | |
321 |
|
321 | |||
322 | ----------------------------------------------------------------------------- |
|
322 | ----------------------------------------------------------------------------- | |
323 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg |
|
323 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg | |
324 | GENERIC MAP ( |
|
324 | GENERIC MAP ( | |
325 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
325 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |
326 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
|
326 | nb_word_by_buffer_size => nb_word_by_buffer_size, | |
327 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
327 | nb_snapshot_param_size => nb_snapshot_param_size, | |
328 | delta_vector_size => delta_vector_size, |
|
328 | delta_vector_size => delta_vector_size, | |
329 | delta_vector_size_f0_2 => delta_vector_size_f0_2, |
|
329 | delta_vector_size_f0_2 => delta_vector_size_f0_2, | |
330 | pindex => pindex, |
|
330 | pindex => pindex, | |
331 | paddr => paddr, |
|
331 | paddr => paddr, | |
332 | pmask => pmask, |
|
332 | pmask => pmask, | |
333 | pirq_ms => pirq_ms, |
|
333 | pirq_ms => pirq_ms, | |
334 | pirq_wfp => pirq_wfp, |
|
334 | pirq_wfp => pirq_wfp, | |
335 | top_lfr_version => top_lfr_version) |
|
335 | top_lfr_version => top_lfr_version) | |
336 | PORT MAP ( |
|
336 | PORT MAP ( | |
337 | HCLK => clk, |
|
337 | HCLK => clk, | |
338 | HRESETn => rstn, |
|
338 | HRESETn => rstn, | |
339 | apbi => apbi, |
|
339 | apbi => apbi, | |
340 | apbo => apbo, |
|
340 | apbo => apbo, | |
341 | ready_matrix_f0_0 => ready_matrix_f0_0, |
|
341 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
342 | ready_matrix_f0_1 => ready_matrix_f0_1, |
|
342 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
343 | ready_matrix_f1 => ready_matrix_f1, |
|
343 | ready_matrix_f1 => ready_matrix_f1, | |
344 | ready_matrix_f2 => ready_matrix_f2, |
|
344 | ready_matrix_f2 => ready_matrix_f2, | |
345 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
345 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
346 | error_bad_component_error => error_bad_component_error, |
|
346 | error_bad_component_error => error_bad_component_error, | |
347 | debug_reg => debug_reg, |
|
347 | debug_reg => debug_reg, | |
348 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
|
348 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
349 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
349 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
350 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
350 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
351 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
351 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
352 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
352 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
353 | status_error_bad_component_error => status_error_bad_component_error, |
|
353 | status_error_bad_component_error => status_error_bad_component_error, | |
354 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
354 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
355 | config_active_interruption_onError => config_active_interruption_onError, |
|
355 | config_active_interruption_onError => config_active_interruption_onError, | |
356 | addr_matrix_f0_0 => addr_matrix_f0_0, |
|
356 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
357 | addr_matrix_f0_1 => addr_matrix_f0_1, |
|
357 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
358 | addr_matrix_f1 => addr_matrix_f1, |
|
358 | addr_matrix_f1 => addr_matrix_f1, | |
359 | addr_matrix_f2 => addr_matrix_f2, |
|
359 | addr_matrix_f2 => addr_matrix_f2, | |
360 | status_full => status_full, |
|
360 | status_full => status_full, | |
361 | status_full_ack => status_full_ack, |
|
361 | status_full_ack => status_full_ack, | |
362 | status_full_err => status_full_err, |
|
362 | status_full_err => status_full_err, | |
363 | status_new_err => status_new_err, |
|
363 | status_new_err => status_new_err, | |
364 | data_shaping_BW => data_shaping_BW, |
|
364 | data_shaping_BW => data_shaping_BW, | |
365 | data_shaping_SP0 => data_shaping_SP0, |
|
365 | data_shaping_SP0 => data_shaping_SP0, | |
366 | data_shaping_SP1 => data_shaping_SP1, |
|
366 | data_shaping_SP1 => data_shaping_SP1, | |
367 | data_shaping_R0 => data_shaping_R0, |
|
367 | data_shaping_R0 => data_shaping_R0, | |
368 | data_shaping_R1 => data_shaping_R1, |
|
368 | data_shaping_R1 => data_shaping_R1, | |
369 | delta_snapshot => delta_snapshot, |
|
369 | delta_snapshot => delta_snapshot, | |
370 | delta_f0 => delta_f0, |
|
370 | delta_f0 => delta_f0, | |
371 | delta_f0_2 => delta_f0_2, |
|
371 | delta_f0_2 => delta_f0_2, | |
372 | delta_f1 => delta_f1, |
|
372 | delta_f1 => delta_f1, | |
373 | delta_f2 => delta_f2, |
|
373 | delta_f2 => delta_f2, | |
374 | nb_data_by_buffer => nb_data_by_buffer, |
|
374 | nb_data_by_buffer => nb_data_by_buffer, | |
375 | nb_word_by_buffer => nb_word_by_buffer, |
|
375 | nb_word_by_buffer => nb_word_by_buffer, | |
376 | nb_snapshot_param => nb_snapshot_param, |
|
376 | nb_snapshot_param => nb_snapshot_param, | |
377 | enable_f0 => enable_f0, |
|
377 | enable_f0 => enable_f0, | |
378 | enable_f1 => enable_f1, |
|
378 | enable_f1 => enable_f1, | |
379 | enable_f2 => enable_f2, |
|
379 | enable_f2 => enable_f2, | |
380 | enable_f3 => enable_f3, |
|
380 | enable_f3 => enable_f3, | |
381 | burst_f0 => burst_f0, |
|
381 | burst_f0 => burst_f0, | |
382 | burst_f1 => burst_f1, |
|
382 | burst_f1 => burst_f1, | |
383 | burst_f2 => burst_f2, |
|
383 | burst_f2 => burst_f2, | |
384 | run => run, |
|
384 | run => run, | |
385 | addr_data_f0 => addr_data_f0, |
|
385 | addr_data_f0 => addr_data_f0, | |
386 | addr_data_f1 => addr_data_f1, |
|
386 | addr_data_f1 => addr_data_f1, | |
387 | addr_data_f2 => addr_data_f2, |
|
387 | addr_data_f2 => addr_data_f2, | |
388 | addr_data_f3 => addr_data_f3, |
|
388 | addr_data_f3 => addr_data_f3, | |
389 | start_date => start_date, |
|
389 | start_date => start_date, | |
390 | --------------------------------------------------------------------------- |
|
390 | --------------------------------------------------------------------------- | |
391 | debug_reg0 => debug_reg0, |
|
391 | debug_reg0 => debug_reg0, | |
392 | debug_reg1 => debug_reg1, |
|
392 | debug_reg1 => debug_reg1, | |
393 | debug_reg2 => debug_reg2, |
|
393 | debug_reg2 => debug_reg2, | |
394 | debug_reg3 => debug_reg3, |
|
394 | debug_reg3 => debug_reg3, | |
395 | debug_reg4 => debug_reg4, |
|
395 | debug_reg4 => debug_reg4, | |
396 | debug_reg5 => debug_reg5, |
|
396 | debug_reg5 => debug_reg5, | |
397 | debug_reg6 => debug_reg6, |
|
397 | debug_reg6 => debug_reg6, | |
398 | debug_reg7 => debug_reg7); |
|
398 | debug_reg7 => debug_reg7); | |
399 |
|
399 | |||
400 | debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0); |
|
400 | debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0); | |
401 | debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); |
|
401 | debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); | |
402 | debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2); |
|
402 | debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2); | |
403 | ----------------------------------------------------------------------------- |
|
403 | ----------------------------------------------------------------------------- | |
404 | --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug |
|
404 | --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug | |
405 | --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug |
|
405 | --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug | |
406 | --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug |
|
406 | --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug | |
407 | --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug |
|
407 | --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug | |
408 |
|
408 | |||
409 |
|
409 | |||
410 | ----------------------------------------------------------------------------- |
|
410 | ----------------------------------------------------------------------------- | |
411 | lpp_waveform_1 : lpp_waveform |
|
411 | lpp_waveform_1 : lpp_waveform | |
412 | GENERIC MAP ( |
|
412 | GENERIC MAP ( | |
413 | tech => inferred, |
|
413 | tech => inferred, | |
414 | data_size => 6*16, |
|
414 | data_size => 6*16, | |
415 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
415 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |
416 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
|
416 | nb_word_by_buffer_size => nb_word_by_buffer_size, | |
417 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
417 | nb_snapshot_param_size => nb_snapshot_param_size, | |
418 | delta_vector_size => delta_vector_size, |
|
418 | delta_vector_size => delta_vector_size, | |
419 | delta_vector_size_f0_2 => delta_vector_size_f0_2 |
|
419 | delta_vector_size_f0_2 => delta_vector_size_f0_2 | |
420 | ) |
|
420 | ) | |
421 | PORT MAP ( |
|
421 | PORT MAP ( | |
422 | clk => clk, |
|
422 | clk => clk, | |
423 | rstn => rstn, |
|
423 | rstn => rstn, | |
424 |
|
424 | |||
425 | reg_run => run, |
|
425 | reg_run => run, | |
426 | reg_start_date => start_date, |
|
426 | reg_start_date => start_date, | |
427 | reg_delta_snapshot => delta_snapshot, |
|
427 | reg_delta_snapshot => delta_snapshot, | |
428 | reg_delta_f0 => delta_f0, |
|
428 | reg_delta_f0 => delta_f0, | |
429 | reg_delta_f0_2 => delta_f0_2, |
|
429 | reg_delta_f0_2 => delta_f0_2, | |
430 | reg_delta_f1 => delta_f1, |
|
430 | reg_delta_f1 => delta_f1, | |
431 | reg_delta_f2 => delta_f2, |
|
431 | reg_delta_f2 => delta_f2, | |
432 |
|
432 | |||
433 | enable_f0 => enable_f0, |
|
433 | enable_f0 => enable_f0, | |
434 | enable_f1 => enable_f1, |
|
434 | enable_f1 => enable_f1, | |
435 | enable_f2 => enable_f2, |
|
435 | enable_f2 => enable_f2, | |
436 | enable_f3 => enable_f3, |
|
436 | enable_f3 => enable_f3, | |
437 | burst_f0 => burst_f0, |
|
437 | burst_f0 => burst_f0, | |
438 | burst_f1 => burst_f1, |
|
438 | burst_f1 => burst_f1, | |
439 | burst_f2 => burst_f2, |
|
439 | burst_f2 => burst_f2, | |
440 |
|
440 | |||
441 | nb_data_by_buffer => nb_data_by_buffer, |
|
441 | nb_data_by_buffer => nb_data_by_buffer, | |
442 | nb_word_by_buffer => nb_word_by_buffer, |
|
442 | nb_word_by_buffer => nb_word_by_buffer, | |
443 | nb_snapshot_param => nb_snapshot_param, |
|
443 | nb_snapshot_param => nb_snapshot_param, | |
444 | status_full => status_full, |
|
444 | status_full => status_full, | |
445 | status_full_ack => status_full_ack, |
|
445 | status_full_ack => status_full_ack, | |
446 | status_full_err => status_full_err, |
|
446 | status_full_err => status_full_err, | |
447 | status_new_err => status_new_err, |
|
447 | status_new_err => status_new_err, | |
448 |
|
448 | |||
449 | coarse_time => coarse_time, |
|
449 | coarse_time => coarse_time, | |
450 | fine_time => fine_time, |
|
450 | fine_time => fine_time, | |
451 |
|
451 | |||
452 | --f0 |
|
452 | --f0 | |
453 | addr_data_f0 => addr_data_f0, |
|
453 | addr_data_f0 => addr_data_f0, | |
454 | data_f0_in_valid => sample_f0_val, |
|
454 | data_f0_in_valid => sample_f0_val, | |
455 | data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug |
|
455 | data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug | |
456 | --f1 |
|
456 | --f1 | |
457 | addr_data_f1 => addr_data_f1, |
|
457 | addr_data_f1 => addr_data_f1, | |
458 | data_f1_in_valid => sample_f1_val, |
|
458 | data_f1_in_valid => sample_f1_val, | |
459 | data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug, |
|
459 | data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug, | |
460 | --f2 |
|
460 | --f2 | |
461 | addr_data_f2 => addr_data_f2, |
|
461 | addr_data_f2 => addr_data_f2, | |
462 | data_f2_in_valid => sample_f2_val, |
|
462 | data_f2_in_valid => sample_f2_val, | |
463 | data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug, |
|
463 | data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug, | |
464 | --f3 |
|
464 | --f3 | |
465 | addr_data_f3 => addr_data_f3, |
|
465 | addr_data_f3 => addr_data_f3, | |
466 | data_f3_in_valid => sample_f3_val, |
|
466 | data_f3_in_valid => sample_f3_val, | |
467 | data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug, |
|
467 | data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug, | |
468 | -- OUTPUT -- DMA interface |
|
468 | -- OUTPUT -- DMA interface | |
469 | --f0 |
|
469 | --f0 | |
470 | data_f0_addr_out => data_f0_addr_out_s, |
|
470 | data_f0_addr_out => data_f0_addr_out_s, | |
471 | data_f0_data_out => data_f0_data_out, |
|
471 | data_f0_data_out => data_f0_data_out, | |
472 | data_f0_data_out_valid => data_f0_data_out_valid_s, |
|
472 | data_f0_data_out_valid => data_f0_data_out_valid_s, | |
473 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s, |
|
473 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s, | |
474 | data_f0_data_out_ren => data_f0_data_out_ren, |
|
474 | data_f0_data_out_ren => data_f0_data_out_ren, | |
475 | --f1 |
|
475 | --f1 | |
476 | data_f1_addr_out => data_f1_addr_out_s, |
|
476 | data_f1_addr_out => data_f1_addr_out_s, | |
477 | data_f1_data_out => data_f1_data_out, |
|
477 | data_f1_data_out => data_f1_data_out, | |
478 | data_f1_data_out_valid => data_f1_data_out_valid_s, |
|
478 | data_f1_data_out_valid => data_f1_data_out_valid_s, | |
479 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s, |
|
479 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s, | |
480 | data_f1_data_out_ren => data_f1_data_out_ren, |
|
480 | data_f1_data_out_ren => data_f1_data_out_ren, | |
481 | --f2 |
|
481 | --f2 | |
482 | data_f2_addr_out => data_f2_addr_out_s, |
|
482 | data_f2_addr_out => data_f2_addr_out_s, | |
483 | data_f2_data_out => data_f2_data_out, |
|
483 | data_f2_data_out => data_f2_data_out, | |
484 | data_f2_data_out_valid => data_f2_data_out_valid_s, |
|
484 | data_f2_data_out_valid => data_f2_data_out_valid_s, | |
485 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s, |
|
485 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s, | |
486 | data_f2_data_out_ren => data_f2_data_out_ren, |
|
486 | data_f2_data_out_ren => data_f2_data_out_ren, | |
487 | --f3 |
|
487 | --f3 | |
488 | data_f3_addr_out => data_f3_addr_out_s, |
|
488 | data_f3_addr_out => data_f3_addr_out_s, | |
489 | data_f3_data_out => data_f3_data_out, |
|
489 | data_f3_data_out => data_f3_data_out, | |
490 | data_f3_data_out_valid => data_f3_data_out_valid_s, |
|
490 | data_f3_data_out_valid => data_f3_data_out_valid_s, | |
491 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, |
|
491 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, | |
492 |
data_f3_data_out_ren => data_f3_data_out_ren |
|
492 | data_f3_data_out_ren => data_f3_data_out_ren , | |
493 |
|
493 | |||
494 | ------------------------------------------------------------------------- |
|
494 | ------------------------------------------------------------------------- | |
495 | observation_reg => observation_reg |
|
495 | observation_reg => observation_reg | |
496 | ---- debug SNAPSHOT_OUT |
|
496 | ---- debug SNAPSHOT_OUT | |
497 | --debug_f0_data => debug_f0_data, |
|
497 | --debug_f0_data => debug_f0_data, | |
498 | --debug_f0_data_valid => debug_f0_data_valid , |
|
498 | --debug_f0_data_valid => debug_f0_data_valid , | |
499 | --debug_f1_data => debug_f1_data , |
|
499 | --debug_f1_data => debug_f1_data , | |
500 | --debug_f1_data_valid => debug_f1_data_valid, |
|
500 | --debug_f1_data_valid => debug_f1_data_valid, | |
501 | --debug_f2_data => debug_f2_data , |
|
501 | --debug_f2_data => debug_f2_data , | |
502 | --debug_f2_data_valid => debug_f2_data_valid , |
|
502 | --debug_f2_data_valid => debug_f2_data_valid , | |
503 | --debug_f3_data => debug_f3_data , |
|
503 | --debug_f3_data => debug_f3_data , | |
504 | --debug_f3_data_valid => debug_f3_data_valid, |
|
504 | --debug_f3_data_valid => debug_f3_data_valid, | |
505 |
|
505 | |||
506 | ---- debug FIFO_IN |
|
506 | ---- debug FIFO_IN | |
507 | --debug_f0_data_fifo_in => debug_f0_data_fifo_in , |
|
507 | --debug_f0_data_fifo_in => debug_f0_data_fifo_in , | |
508 | --debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid, |
|
508 | --debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid, | |
509 | --debug_f1_data_fifo_in => debug_f1_data_fifo_in , |
|
509 | --debug_f1_data_fifo_in => debug_f1_data_fifo_in , | |
510 | --debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid, |
|
510 | --debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid, | |
511 | --debug_f2_data_fifo_in => debug_f2_data_fifo_in , |
|
511 | --debug_f2_data_fifo_in => debug_f2_data_fifo_in , | |
512 | --debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid, |
|
512 | --debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid, | |
513 | --debug_f3_data_fifo_in => debug_f3_data_fifo_in , |
|
513 | --debug_f3_data_fifo_in => debug_f3_data_fifo_in , | |
514 | --debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid |
|
514 | --debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid | |
515 |
|
515 | |||
516 | ); |
|
516 | ); | |
517 |
|
517 | |||
518 |
|
518 | |||
519 | ----------------------------------------------------------------------------- |
|
519 | ----------------------------------------------------------------------------- | |
520 | -- DEBUG -- WFP OUT |
|
520 | -- DEBUG -- WFP OUT | |
521 | --debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren; |
|
521 | --debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren; | |
522 | --debug_f0_data_fifo_out <= data_f0_data_out; |
|
522 | --debug_f0_data_fifo_out <= data_f0_data_out; | |
523 | --debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren; |
|
523 | --debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren; | |
524 | --debug_f1_data_fifo_out <= data_f1_data_out; |
|
524 | --debug_f1_data_fifo_out <= data_f1_data_out; | |
525 | --debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren; |
|
525 | --debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren; | |
526 | --debug_f2_data_fifo_out <= data_f2_data_out; |
|
526 | --debug_f2_data_fifo_out <= data_f2_data_out; | |
527 | --debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren; |
|
527 | --debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren; | |
528 | --debug_f3_data_fifo_out <= data_f3_data_out; |
|
528 | --debug_f3_data_fifo_out <= data_f3_data_out; | |
529 | ----------------------------------------------------------------------------- |
|
529 | ----------------------------------------------------------------------------- | |
530 |
|
530 | |||
531 |
|
531 | |||
532 | ----------------------------------------------------------------------------- |
|
532 | ----------------------------------------------------------------------------- | |
533 | -- TEMP |
|
533 | -- TEMP | |
534 | ----------------------------------------------------------------------------- |
|
534 | ----------------------------------------------------------------------------- | |
535 |
|
535 | |||
536 | PROCESS (clk, rstn) |
|
536 | PROCESS (clk, rstn) | |
537 | BEGIN -- PROCESS |
|
537 | BEGIN -- PROCESS | |
538 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
538 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
539 | data_f0_data_out_valid <= '0'; |
|
539 | data_f0_data_out_valid <= '0'; | |
540 | data_f0_data_out_valid_burst <= '0'; |
|
540 | data_f0_data_out_valid_burst <= '0'; | |
541 | data_f1_data_out_valid <= '0'; |
|
541 | data_f1_data_out_valid <= '0'; | |
542 | data_f1_data_out_valid_burst <= '0'; |
|
542 | data_f1_data_out_valid_burst <= '0'; | |
543 | data_f2_data_out_valid <= '0'; |
|
543 | data_f2_data_out_valid <= '0'; | |
544 | data_f2_data_out_valid_burst <= '0'; |
|
544 | data_f2_data_out_valid_burst <= '0'; | |
545 | data_f3_data_out_valid <= '0'; |
|
545 | data_f3_data_out_valid <= '0'; | |
546 | data_f3_data_out_valid_burst <= '0'; |
|
546 | data_f3_data_out_valid_burst <= '0'; | |
547 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
547 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
548 | data_f0_data_out_valid <= data_f0_data_out_valid_s; |
|
548 | data_f0_data_out_valid <= data_f0_data_out_valid_s; | |
549 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; |
|
549 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; | |
550 | data_f1_data_out_valid <= data_f1_data_out_valid_s; |
|
550 | data_f1_data_out_valid <= data_f1_data_out_valid_s; | |
551 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; |
|
551 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; | |
552 | data_f2_data_out_valid <= data_f2_data_out_valid_s; |
|
552 | data_f2_data_out_valid <= data_f2_data_out_valid_s; | |
553 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; |
|
553 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; | |
554 | data_f3_data_out_valid <= data_f3_data_out_valid_s; |
|
554 | data_f3_data_out_valid <= data_f3_data_out_valid_s; | |
555 | data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; |
|
555 | data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; | |
556 | END IF; |
|
556 | END IF; | |
557 | END PROCESS; |
|
557 | END PROCESS; | |
558 |
|
558 | |||
559 | data_f0_addr_out <= data_f0_addr_out_s; |
|
559 | data_f0_addr_out <= data_f0_addr_out_s; | |
560 | data_f1_addr_out <= data_f1_addr_out_s; |
|
560 | data_f1_addr_out <= data_f1_addr_out_s; | |
561 | data_f2_addr_out <= data_f2_addr_out_s; |
|
561 | data_f2_addr_out <= data_f2_addr_out_s; | |
562 | data_f3_addr_out <= data_f3_addr_out_s; |
|
562 | data_f3_addr_out <= data_f3_addr_out_s; | |
563 |
|
563 | |||
564 | ----------------------------------------------------------------------------- |
|
564 | ----------------------------------------------------------------------------- | |
565 | -- RoundRobin Selection For DMA |
|
565 | -- RoundRobin Selection For DMA | |
566 | ----------------------------------------------------------------------------- |
|
566 | ----------------------------------------------------------------------------- | |
567 |
|
567 | |||
568 | dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; |
|
568 | dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; | |
569 | dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; |
|
569 | dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; | |
570 | dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; |
|
570 | dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; | |
571 | dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; |
|
571 | dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; | |
572 |
|
572 | |||
573 | RR_Arbiter_4_1 : RR_Arbiter_4 |
|
573 | RR_Arbiter_4_1 : RR_Arbiter_4 | |
574 | PORT MAP ( |
|
574 | PORT MAP ( | |
575 | clk => clk, |
|
575 | clk => clk, | |
576 | rstn => rstn, |
|
576 | rstn => rstn, | |
577 | in_valid => dma_rr_valid, |
|
577 | in_valid => dma_rr_valid, | |
578 | out_grant => dma_rr_grant_s); |
|
578 | out_grant => dma_rr_grant_s); | |
579 |
|
579 | |||
580 | dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst; |
|
580 | dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst; | |
581 | dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; |
|
581 | dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; | |
582 | dma_rr_valid_ms(2) <= '0'; |
|
582 | dma_rr_valid_ms(2) <= '0'; | |
583 | dma_rr_valid_ms(3) <= '0'; |
|
583 | dma_rr_valid_ms(3) <= '0'; | |
584 |
|
584 | |||
585 | RR_Arbiter_4_2 : RR_Arbiter_4 |
|
585 | RR_Arbiter_4_2 : RR_Arbiter_4 | |
586 | PORT MAP ( |
|
586 | PORT MAP ( | |
587 | clk => clk, |
|
587 | clk => clk, | |
588 | rstn => rstn, |
|
588 | rstn => rstn, | |
589 | in_valid => dma_rr_valid_ms, |
|
589 | in_valid => dma_rr_valid_ms, | |
590 | out_grant => dma_rr_grant_ms); |
|
590 | out_grant => dma_rr_grant_ms); | |
591 |
|
591 | |||
592 | dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; |
|
592 | dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; | |
593 |
|
593 | |||
594 |
|
594 | |||
595 | ----------------------------------------------------------------------------- |
|
595 | ----------------------------------------------------------------------------- | |
596 | -- in : dma_rr_grant |
|
596 | -- in : dma_rr_grant | |
597 | -- send |
|
597 | -- send | |
598 | -- out : dma_sel |
|
598 | -- out : dma_sel | |
599 | -- dma_valid_burst |
|
599 | -- dma_valid_burst | |
600 | -- dma_sel_valid |
|
600 | -- dma_sel_valid | |
601 | ----------------------------------------------------------------------------- |
|
601 | ----------------------------------------------------------------------------- | |
602 | PROCESS (clk, rstn) |
|
602 | PROCESS (clk, rstn) | |
603 | BEGIN -- PROCESS |
|
603 | BEGIN -- PROCESS | |
604 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
604 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
605 | dma_sel <= (OTHERS => '0'); |
|
605 | dma_sel <= (OTHERS => '0'); | |
606 | dma_send <= '0'; |
|
606 | dma_send <= '0'; | |
607 | dma_valid_burst <= '0'; |
|
607 | dma_valid_burst <= '0'; | |
608 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
608 | data_ms_done <= '0'; | |
609 | IF run = '1' THEN |
|
609 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
610 | IF dma_sel = "00000" OR dma_done = '1' THEN |
|
610 | IF run = '1' THEN | |
611 | dma_sel <= dma_rr_grant; |
|
611 | data_ms_done <= '0'; | |
612 |
|
|
612 | IF dma_sel = "00000" OR dma_done = '1' THEN | |
613 |
|
|
613 | dma_sel <= dma_rr_grant; | |
614 | dma_valid_burst <= data_f0_data_out_valid_burst; |
|
614 | IF dma_rr_grant(0) = '1' THEN | |
615 | dma_sel_valid <= data_f0_data_out_valid; |
|
615 | dma_send <= '1'; | |
616 | ELSIF dma_rr_grant(1) = '1' THEN |
|
616 | dma_valid_burst <= data_f0_data_out_valid_burst; | |
617 | dma_send <= '1'; |
|
617 | dma_sel_valid <= data_f0_data_out_valid; | |
618 | dma_valid_burst <= data_f1_data_out_valid_burst; |
|
618 | ELSIF dma_rr_grant(1) = '1' THEN | |
619 |
dma_se |
|
619 | dma_send <= '1'; | |
620 | ELSIF dma_rr_grant(2) = '1' THEN |
|
620 | dma_valid_burst <= data_f1_data_out_valid_burst; | |
621 |
dma_se |
|
621 | dma_sel_valid <= data_f1_data_out_valid; | |
622 | dma_valid_burst <= data_f2_data_out_valid_burst; |
|
622 | ELSIF dma_rr_grant(2) = '1' THEN | |
623 | dma_sel_valid <= data_f2_data_out_valid; |
|
623 | dma_send <= '1'; | |
624 | ELSIF dma_rr_grant(3) = '1' THEN |
|
624 | dma_valid_burst <= data_f2_data_out_valid_burst; | |
625 | dma_send <= '1'; |
|
625 | dma_sel_valid <= data_f2_data_out_valid; | |
626 | dma_valid_burst <= data_f3_data_out_valid_burst; |
|
626 | ELSIF dma_rr_grant(3) = '1' THEN | |
627 | dma_sel_valid <= data_f3_data_out_valid; |
|
627 | dma_send <= '1'; | |
628 | ELSIF dma_rr_grant(4) = '1' THEN |
|
628 | dma_valid_burst <= data_f3_data_out_valid_burst; | |
629 | dma_send <= '1'; |
|
629 | dma_sel_valid <= data_f3_data_out_valid; | |
630 | dma_valid_burst <= data_ms_valid_burst; |
|
630 | ELSIF dma_rr_grant(4) = '1' THEN | |
631 |
dma_se |
|
631 | dma_send <= '1'; | |
632 | END IF; |
|
632 | dma_valid_burst <= data_ms_valid_burst; | |
633 |
|
633 | dma_sel_valid <= data_ms_valid; | ||
634 | IF dma_sel(4) = '1' THEN |
|
634 | END IF; | |
635 | data_ms_done <= '1'; |
|
635 | ||
636 | END IF; |
|
636 | IF dma_sel(4) = '1' THEN | |
637 | ELSE |
|
637 | data_ms_done <= '1'; | |
638 | dma_sel <= dma_sel; |
|
638 | END IF; | |
639 | dma_send <= '0'; |
|
639 | ELSE | |
640 | END IF; |
|
640 | dma_sel <= dma_sel; | |
641 | ELSE |
|
641 | dma_send <= '0'; | |
642 | dma_sel <= (OTHERS => '0'); |
|
642 | END IF; | |
643 | dma_send <= '0'; |
|
643 | ELSE | |
644 |
d |
|
644 | data_ms_done <= '0'; | |
645 | END IF; |
|
645 | dma_sel <= (OTHERS => '0'); | |
646 | END IF; |
|
646 | dma_send <= '0'; | |
647 | END PROCESS; |
|
647 | dma_valid_burst <= '0'; | |
648 |
|
648 | END IF; | ||
649 |
|
649 | END IF; | ||
650 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE |
|
650 | END PROCESS; | |
651 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE |
|
651 | ||
652 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE |
|
652 | ||
653 |
|
|
653 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE | |
654 |
data_ |
|
654 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE | |
655 |
|
655 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE | ||
656 |
|
|
656 | data_f3_addr_out WHEN dma_sel(3) = '1' ELSE | |
657 | data_f1_data_out WHEN dma_sel(1) = '1' ELSE |
|
657 | data_ms_addr; | |
658 | data_f2_data_out WHEN dma_sel(2) = '1' ELSE |
|
658 | ||
659 |
|
|
659 | dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE | |
660 | data_ms_data; |
|
660 | data_f1_data_out WHEN dma_sel(1) = '1' ELSE | |
661 |
|
661 | data_f2_data_out WHEN dma_sel(2) = '1' ELSE | ||
662 |
data_f |
|
662 | data_f3_data_out WHEN dma_sel(3) = '1' ELSE | |
663 | data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; |
|
663 | data_ms_data; | |
664 | data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; |
|
664 | ||
665 |
|
|
665 | data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; | |
666 |
data_ |
|
666 | data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; | |
667 |
|
667 | data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; | ||
668 | dma_data_2 <= dma_data; |
|
668 | data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; | |
669 |
|
669 | data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1'; | ||
670 |
|
670 | |||
671 |
|
671 | dma_data_2 <= dma_data; | ||
672 |
|
672 | |||
673 |
|
673 | |||
674 | ----------------------------------------------------------------------------- |
|
674 | ||
675 | -- DEBUG -- DMA IN |
|
675 | ||
676 | --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; |
|
676 | ||
677 | --debug_f0_data_dma_in <= dma_data; |
|
677 | ----------------------------------------------------------------------------- | |
678 | --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; |
|
678 | -- DEBUG -- DMA IN | |
679 |
--debug_f |
|
679 | --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; | |
680 |
--debug_f |
|
680 | --debug_f0_data_dma_in <= dma_data; | |
681 |
--debug_f |
|
681 | --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; | |
682 |
--debug_f |
|
682 | --debug_f1_data_dma_in <= dma_data; | |
683 |
--debug_f |
|
683 | --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren; | |
684 | ----------------------------------------------------------------------------- |
|
684 | --debug_f2_data_dma_in <= dma_data; | |
685 |
|
685 | --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren; | ||
686 | ----------------------------------------------------------------------------- |
|
686 | --debug_f3_data_dma_in <= dma_data; | |
687 | -- DMA |
|
687 | ----------------------------------------------------------------------------- | |
688 | ----------------------------------------------------------------------------- |
|
688 | ||
689 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst |
|
689 | ----------------------------------------------------------------------------- | |
690 | GENERIC MAP ( |
|
690 | -- DMA | |
691 | tech => inferred, |
|
691 | ----------------------------------------------------------------------------- | |
692 | hindex => hindex) |
|
692 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst | |
693 |
|
|
693 | GENERIC MAP ( | |
694 | HCLK => clk, |
|
694 | tech => inferred, | |
695 | HRESETn => rstn, |
|
695 | hindex => hindex) | |
696 | run => run, |
|
696 | PORT MAP ( | |
697 | AHB_Master_In => ahbi, |
|
697 | HCLK => clk, | |
698 | AHB_Master_Out => ahbo, |
|
698 | HRESETn => rstn, | |
699 |
|
699 | run => run, | ||
700 | send => dma_send, |
|
700 | AHB_Master_In => ahbi, | |
701 | valid_burst => dma_valid_burst, |
|
701 | AHB_Master_Out => ahbo, | |
702 | done => dma_done, |
|
702 | ||
703 |
|
|
703 | send => dma_send, | |
704 |
|
|
704 | valid_burst => dma_valid_burst, | |
705 |
d |
|
705 | done => dma_done, | |
706 |
|
706 | ren => dma_ren, | ||
707 | ----------------------------------------------------------------------------- |
|
707 | address => dma_address, | |
708 | -- Matrix Spectral |
|
708 | data => dma_data_2); | |
709 | ----------------------------------------------------------------------------- |
|
709 | ||
710 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & |
|
710 | ----------------------------------------------------------------------------- | |
711 | NOT(sample_f0_val) & NOT(sample_f0_val) ; |
|
711 | -- Matrix Spectral | |
712 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & |
|
712 | ----------------------------------------------------------------------------- | |
713 | NOT(sample_f1_val) & NOT(sample_f1_val) ; |
|
713 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & | |
714 | sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & |
|
714 | NOT(sample_f0_val) & NOT(sample_f0_val) ; | |
715 | NOT(sample_f3_val) & NOT(sample_f3_val) ; |
|
715 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & | |
716 |
|
716 | NOT(sample_f1_val) & NOT(sample_f1_val) ; | ||
717 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) |
|
717 | sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & | |
718 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); |
|
718 | NOT(sample_f3_val) & NOT(sample_f3_val) ; | |
719 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); |
|
719 | ||
720 | ------------------------------------------------------------------------------- |
|
720 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) | |
721 | lpp_lfr_ms_1: lpp_lfr_ms |
|
721 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); | |
722 | GENERIC MAP ( |
|
722 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); | |
723 | Mem_use => Mem_use ) |
|
723 | ||
724 | PORT MAP ( |
|
724 | ------------------------------------------------------------------------------- | |
725 | clk => clk, |
|
725 | lpp_lfr_ms_1: lpp_lfr_ms | |
726 | rstn => rstn, |
|
726 | GENERIC MAP ( | |
727 |
|
727 | Mem_use => Mem_use ) | ||
728 | sample_f0_wen => sample_f0_wen, |
|
728 | PORT MAP ( | |
729 |
|
|
729 | clk => clk, | |
730 |
|
|
730 | rstn => rstn, | |
731 | sample_f1_wdata => sample_f1_wdata, |
|
731 | ||
732 | sample_f3_wen => sample_f3_wen, |
|
732 | coarse_time => coarse_time, | |
733 | sample_f3_wdata => sample_f3_wdata, |
|
733 | fine_time => fine_time, | |
734 |
|
734 | |||
735 |
|
|
735 | sample_f0_wen => sample_f0_wen, | |
736 |
|
|
736 | sample_f0_wdata => sample_f0_wdata, | |
737 |
|
|
737 | sample_f1_wen => sample_f1_wen, | |
738 | dma_valid_burst => data_ms_valid_burst, -- |
|
738 | sample_f1_wdata => sample_f1_wdata, | |
739 |
|
|
739 | sample_f3_wen => sample_f3_wen, | |
740 | dma_done => data_ms_done, -- |
|
740 | sample_f3_wdata => sample_f3_wdata, | |
741 |
|
741 | |||
742 | ready_matrix_f0_0 => ready_matrix_f0_0, |
|
742 | dma_addr => data_ms_addr, -- | |
743 | ready_matrix_f0_1 => ready_matrix_f0_1, |
|
743 | dma_data => data_ms_data, -- | |
744 |
|
|
744 | dma_valid => data_ms_valid, -- | |
745 |
|
|
745 | dma_valid_burst => data_ms_valid_burst, -- | |
746 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
746 | dma_ren => data_ms_ren, -- | |
747 | error_bad_component_error => error_bad_component_error, |
|
747 | dma_done => data_ms_done, -- | |
748 | debug_reg => debug_reg, |
|
748 | ||
749 |
|
|
749 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
750 |
|
|
750 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
751 |
|
|
751 | ready_matrix_f1 => ready_matrix_f1, | |
752 |
|
|
752 | ready_matrix_f2 => ready_matrix_f2, | |
753 |
|
|
753 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
754 |
|
|
754 | error_bad_component_error => error_bad_component_error, | |
755 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
755 | debug_reg => debug_reg, | |
756 | config_active_interruption_onError => config_active_interruption_onError, |
|
756 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
757 |
|
|
757 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
758 |
|
|
758 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
759 |
|
|
759 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
760 | addr_matrix_f2 => addr_matrix_f2); |
|
760 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
761 |
|
761 | status_error_bad_component_error => status_error_bad_component_error, | ||
762 | END beh; |
|
762 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
|
763 | config_active_interruption_onError => config_active_interruption_onError, | |||
|
764 | addr_matrix_f0_0 => addr_matrix_f0_0, | |||
|
765 | addr_matrix_f0_1 => addr_matrix_f0_1, | |||
|
766 | addr_matrix_f1 => addr_matrix_f1, | |||
|
767 | addr_matrix_f2 => addr_matrix_f2); | |||
|
768 | ||||
|
769 | END beh; |
@@ -37,6 +37,9 ENTITY lpp_lfr_ms IS | |||||
37 | --------------------------------------------------------------------------- |
|
37 | --------------------------------------------------------------------------- | |
38 | -- DATA INPUT |
|
38 | -- DATA INPUT | |
39 | --------------------------------------------------------------------------- |
|
39 | --------------------------------------------------------------------------- | |
|
40 | -- TIME | |||
|
41 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |||
|
42 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |||
40 | -- |
|
43 | -- | |
41 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
44 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
42 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
45 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
@@ -135,7 +138,10 ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |||||
135 | ----------------------------------------------------------------------------- |
|
138 | ----------------------------------------------------------------------------- | |
136 | SIGNAL DMA_Read : STD_LOGIC; |
|
139 | SIGNAL DMA_Read : STD_LOGIC; | |
137 | SIGNAL DMA_ack : STD_LOGIC; |
|
140 | SIGNAL DMA_ack : STD_LOGIC; | |
138 |
|
141 | |||
|
142 | ----------------------------------------------------------------------------- | |||
|
143 | SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
144 | ||||
139 | BEGIN |
|
145 | BEGIN | |
140 |
|
146 | |||
141 | ----------------------------------------------------------------------------- |
|
147 | ----------------------------------------------------------------------------- | |
@@ -305,13 +311,16 BEGIN | |||||
305 | header_val => Head_Val, |
|
311 | header_val => Head_Val, | |
306 | header_ack => DMA_ack ); |
|
312 | header_ack => DMA_ack ); | |
307 | ----------------------------------------------------------------------------- |
|
313 | ----------------------------------------------------------------------------- | |
308 |
|
314 | data_time(31 DOWNTO 0) <= coarse_time; | ||
|
315 | data_time(47 DOWNTO 32) <= fine_time; | |||
309 |
|
316 | |||
310 | lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma |
|
317 | lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma | |
311 | PORT MAP ( |
|
318 | PORT MAP ( | |
312 | HCLK => clk, |
|
319 | HCLK => clk, | |
313 | HRESETn => rstn, |
|
320 | HRESETn => rstn, | |
314 |
|
321 | |||
|
322 | data_time => data_time, | |||
|
323 | ||||
315 | fifo_data => Head_Data, |
|
324 | fifo_data => Head_Data, | |
316 | fifo_empty => Head_Empty, |
|
325 | fifo_empty => Head_Empty, | |
317 | fifo_ren => DMA_Read, |
|
326 | fifo_ren => DMA_Read, |
This diff has been collapsed as it changes many lines, (521 lines changed) Show them Hide them | |||||
@@ -1,258 +1,263 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 |
|
3 | |||
4 | LIBRARY grlib; |
|
4 | LIBRARY grlib; | |
5 | USE grlib.amba.ALL; |
|
5 | USE grlib.amba.ALL; | |
6 |
|
6 | |||
7 | LIBRARY lpp; |
|
7 | LIBRARY lpp; | |
8 | USE lpp.lpp_ad_conv.ALL; |
|
8 | USE lpp.lpp_ad_conv.ALL; | |
9 | USE lpp.iir_filter.ALL; |
|
9 | USE lpp.iir_filter.ALL; | |
10 | USE lpp.FILTERcfg.ALL; |
|
10 | USE lpp.FILTERcfg.ALL; | |
11 | USE lpp.lpp_memory.ALL; |
|
11 | USE lpp.lpp_memory.ALL; | |
12 | LIBRARY techmap; |
|
12 | LIBRARY techmap; | |
13 | USE techmap.gencomp.ALL; |
|
13 | USE techmap.gencomp.ALL; | |
14 |
|
14 | |||
15 | PACKAGE lpp_lfr_pkg IS |
|
15 | PACKAGE lpp_lfr_pkg IS | |
16 |
|
16 | |||
17 | COMPONENT lpp_lfr_ms |
|
17 | COMPONENT lpp_lfr_ms | |
18 | GENERIC ( |
|
18 | GENERIC ( | |
19 | Mem_use : INTEGER |
|
19 | Mem_use : INTEGER | |
20 | ); |
|
20 | ); | |
21 | PORT ( |
|
21 | PORT ( | |
22 | clk : IN STD_LOGIC; |
|
22 | clk : IN STD_LOGIC; | |
23 | rstn : IN STD_LOGIC; |
|
23 | rstn : IN STD_LOGIC; | |
24 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
24 | ||
25 |
|
|
25 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
26 |
|
|
26 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
27 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
27 | ||
28 |
sample_f |
|
28 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
29 |
sample_f |
|
29 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
30 |
|
30 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | ||
31 |
|
|
31 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
32 |
|
|
32 | sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
33 | dma_valid : OUT STD_LOGIC; |
|
33 | sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
34 | dma_valid_burst : OUT STD_LOGIC; |
|
34 | ||
35 |
dma_r |
|
35 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
36 |
dma_d |
|
36 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
37 |
|
37 | dma_valid : OUT STD_LOGIC; | ||
38 | ready_matrix_f0_0 : OUT STD_LOGIC; |
|
38 | dma_valid_burst : OUT STD_LOGIC; | |
39 |
|
|
39 | dma_ren : IN STD_LOGIC; | |
40 |
|
|
40 | dma_done : IN STD_LOGIC; | |
41 | ready_matrix_f2 : OUT STD_LOGIC; |
|
41 | ||
42 |
|
|
42 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
43 |
|
|
43 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
44 |
|
|
44 | ready_matrix_f1 : OUT STD_LOGIC; | |
45 |
|
|
45 | ready_matrix_f2 : OUT STD_LOGIC; | |
46 |
|
|
46 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
47 |
|
|
47 | error_bad_component_error : OUT STD_LOGIC; | |
48 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
48 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
49 |
status_ |
|
49 | status_ready_matrix_f0_0 : IN STD_LOGIC; | |
50 |
status_ |
|
50 | status_ready_matrix_f0_1 : IN STD_LOGIC; | |
51 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
51 | status_ready_matrix_f1 : IN STD_LOGIC; | |
52 | config_active_interruption_onError : IN STD_LOGIC; |
|
52 | status_ready_matrix_f2 : IN STD_LOGIC; | |
53 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
53 | status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
54 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
54 | status_error_bad_component_error : IN STD_LOGIC; | |
55 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
55 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
56 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
56 | config_active_interruption_onError : IN STD_LOGIC; | |
57 | END COMPONENT; |
|
57 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
58 |
|
58 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | ||
59 | COMPONENT lpp_lfr_ms_fsmdma |
|
59 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
60 | PORT ( |
|
60 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
61 | HCLK : IN STD_ULOGIC; |
|
61 | END COMPONENT; | |
62 | HRESETn : IN STD_ULOGIC; |
|
62 | ||
63 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
63 | COMPONENT lpp_lfr_ms_fsmdma | |
64 | fifo_empty : IN STD_LOGIC; |
|
64 | PORT ( | |
65 |
|
|
65 | HCLK : IN STD_ULOGIC; | |
66 |
|
|
66 | HRESETn : IN STD_ULOGIC; | |
67 |
|
|
67 | data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
68 |
|
|
68 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
69 |
|
|
69 | fifo_empty : IN STD_LOGIC; | |
70 |
|
|
70 | fifo_ren : OUT STD_LOGIC; | |
71 |
|
|
71 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
72 |
|
|
72 | header_val : IN STD_LOGIC; | |
73 |
|
|
73 | header_ack : OUT STD_LOGIC; | |
74 |
dma_ |
|
74 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
75 |
|
|
75 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
76 |
|
|
76 | dma_valid : OUT STD_LOGIC; | |
77 |
|
|
77 | dma_valid_burst : OUT STD_LOGIC; | |
78 |
|
|
78 | dma_ren : IN STD_LOGIC; | |
79 | error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
79 | dma_done : IN STD_LOGIC; | |
80 |
|
|
80 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
81 |
|
|
81 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
82 |
|
|
82 | ready_matrix_f1 : OUT STD_LOGIC; | |
83 |
|
|
83 | ready_matrix_f2 : OUT STD_LOGIC; | |
84 |
|
|
84 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
85 |
|
|
85 | error_bad_component_error : OUT STD_LOGIC; | |
86 | status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
86 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
87 |
status_ |
|
87 | status_ready_matrix_f0_0 : IN STD_LOGIC; | |
88 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
88 | status_ready_matrix_f0_1 : IN STD_LOGIC; | |
89 | config_active_interruption_onError : IN STD_LOGIC; |
|
89 | status_ready_matrix_f1 : IN STD_LOGIC; | |
90 |
|
|
90 | status_ready_matrix_f2 : IN STD_LOGIC; | |
91 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
92 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
92 | status_error_bad_component_error : IN STD_LOGIC; | |
93 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
93 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
94 | END COMPONENT; |
|
94 | config_active_interruption_onError : IN STD_LOGIC; | |
95 |
|
95 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | ||
96 |
|
96 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | ||
97 | COMPONENT lpp_lfr_filter |
|
97 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
98 | GENERIC ( |
|
98 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
99 | Mem_use : INTEGER); |
|
99 | END COMPONENT; | |
100 | PORT ( |
|
100 | ||
101 | sample : IN Samples(7 DOWNTO 0); |
|
101 | ||
102 | sample_val : IN STD_LOGIC; |
|
102 | COMPONENT lpp_lfr_filter | |
103 | clk : IN STD_LOGIC; |
|
103 | GENERIC ( | |
104 | rstn : IN STD_LOGIC; |
|
104 | Mem_use : INTEGER); | |
105 | data_shaping_SP0 : IN STD_LOGIC; |
|
105 | PORT ( | |
106 | data_shaping_SP1 : IN STD_LOGIC; |
|
106 | sample : IN Samples(7 DOWNTO 0); | |
107 |
|
|
107 | sample_val : IN STD_LOGIC; | |
108 |
|
|
108 | clk : IN STD_LOGIC; | |
109 |
|
|
109 | rstn : IN STD_LOGIC; | |
110 |
|
|
110 | data_shaping_SP0 : IN STD_LOGIC; | |
111 |
|
|
111 | data_shaping_SP1 : IN STD_LOGIC; | |
112 |
|
|
112 | data_shaping_R0 : IN STD_LOGIC; | |
113 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
113 | data_shaping_R1 : IN STD_LOGIC; | |
114 |
sample_f |
|
114 | sample_f0_val : OUT STD_LOGIC; | |
115 |
sample_f |
|
115 | sample_f1_val : OUT STD_LOGIC; | |
116 |
sample_f |
|
116 | sample_f2_val : OUT STD_LOGIC; | |
117 | END COMPONENT; |
|
117 | sample_f3_val : OUT STD_LOGIC; | |
118 |
|
118 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | ||
119 | COMPONENT lpp_lfr |
|
119 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
120 | GENERIC ( |
|
120 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
121 | Mem_use : INTEGER; |
|
121 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)); | |
122 | nb_data_by_buffer_size : INTEGER; |
|
122 | END COMPONENT; | |
123 | nb_word_by_buffer_size : INTEGER; |
|
123 | ||
124 | nb_snapshot_param_size : INTEGER; |
|
124 | COMPONENT lpp_lfr | |
125 | delta_vector_size : INTEGER; |
|
125 | GENERIC ( | |
126 | delta_vector_size_f0_2 : INTEGER; |
|
126 | Mem_use : INTEGER; | |
127 | pindex : INTEGER; |
|
127 | nb_data_by_buffer_size : INTEGER; | |
128 | paddr : INTEGER; |
|
128 | nb_word_by_buffer_size : INTEGER; | |
129 | pmask : INTEGER; |
|
129 | nb_snapshot_param_size : INTEGER; | |
130 | pirq_ms : INTEGER; |
|
130 | delta_vector_size : INTEGER; | |
131 | pirq_wfp : INTEGER; |
|
131 | delta_vector_size_f0_2 : INTEGER; | |
132 |
|
|
132 | pindex : INTEGER; | |
133 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) |
|
133 | paddr : INTEGER; | |
134 | ); |
|
134 | pmask : INTEGER; | |
135 | PORT ( |
|
135 | pirq_ms : INTEGER; | |
136 |
|
|
136 | pirq_wfp : INTEGER; | |
137 |
|
|
137 | hindex : INTEGER; | |
138 | sample_B : IN Samples14v(2 DOWNTO 0); |
|
138 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) | |
139 | sample_E : IN Samples14v(4 DOWNTO 0); |
|
139 | ); | |
140 | sample_val : IN STD_LOGIC; |
|
140 | PORT ( | |
141 |
|
|
141 | clk : IN STD_LOGIC; | |
142 | apbo : OUT apb_slv_out_type; |
|
142 | rstn : IN STD_LOGIC; | |
143 | ahbi : IN AHB_Mst_In_Type; |
|
143 | sample_B : IN Samples14v(2 DOWNTO 0); | |
144 | ahbo : OUT AHB_Mst_Out_Type; |
|
144 | sample_E : IN Samples14v(4 DOWNTO 0); | |
145 |
|
|
145 | sample_val : IN STD_LOGIC; | |
146 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
146 | apbi : IN apb_slv_in_type; | |
147 | data_shaping_BW : OUT STD_LOGIC |
|
147 | apbo : OUT apb_slv_out_type; | |
148 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
148 | ahbi : IN AHB_Mst_In_Type; | |
149 | ); |
|
149 | ahbo : OUT AHB_Mst_Out_Type; | |
150 | END COMPONENT; |
|
150 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
151 |
|
151 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | ||
152 | COMPONENT lpp_lfr_apbreg |
|
152 | data_shaping_BW : OUT STD_LOGIC; | |
153 | GENERIC ( |
|
153 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
154 | nb_data_by_buffer_size : INTEGER; |
|
154 | ); | |
155 | nb_word_by_buffer_size : INTEGER; |
|
155 | END COMPONENT; | |
156 | nb_snapshot_param_size : INTEGER; |
|
156 | ||
157 | delta_vector_size : INTEGER; |
|
157 | COMPONENT lpp_lfr_apbreg | |
158 | delta_vector_size_f0_2 : INTEGER; |
|
158 | GENERIC ( | |
159 | pindex : INTEGER; |
|
159 | nb_data_by_buffer_size : INTEGER; | |
160 | paddr : INTEGER; |
|
160 | nb_word_by_buffer_size : INTEGER; | |
161 | pmask : INTEGER; |
|
161 | nb_snapshot_param_size : INTEGER; | |
162 | pirq_ms : INTEGER; |
|
162 | delta_vector_size : INTEGER; | |
163 | pirq_wfp : INTEGER; |
|
163 | delta_vector_size_f0_2 : INTEGER; | |
164 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
164 | pindex : INTEGER; | |
165 | PORT ( |
|
165 | paddr : INTEGER; | |
166 |
|
|
166 | pmask : INTEGER; | |
167 | HRESETn : IN STD_ULOGIC; |
|
167 | pirq_ms : INTEGER; | |
168 | apbi : IN apb_slv_in_type; |
|
168 | pirq_wfp : INTEGER; | |
169 | apbo : OUT apb_slv_out_type; |
|
169 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
170 | ready_matrix_f0_0 : IN STD_LOGIC; |
|
170 | PORT ( | |
171 |
|
|
171 | HCLK : IN STD_ULOGIC; | |
172 |
|
|
172 | HRESETn : IN STD_ULOGIC; | |
173 |
|
|
173 | apbi : IN apb_slv_in_type; | |
174 | error_anticipating_empty_fifo : IN STD_LOGIC; |
|
174 | apbo : OUT apb_slv_out_type; | |
175 |
|
|
175 | ready_matrix_f0_0 : IN STD_LOGIC; | |
176 |
|
|
176 | ready_matrix_f0_1 : IN STD_LOGIC; | |
177 |
|
|
177 | ready_matrix_f1 : IN STD_LOGIC; | |
178 |
|
|
178 | ready_matrix_f2 : IN STD_LOGIC; | |
179 |
|
|
179 | error_anticipating_empty_fifo : IN STD_LOGIC; | |
180 |
|
|
180 | error_bad_component_error : IN STD_LOGIC; | |
181 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
181 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
182 |
status_ |
|
182 | status_ready_matrix_f0_0 : OUT STD_LOGIC; | |
183 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
183 | status_ready_matrix_f0_1 : OUT STD_LOGIC; | |
184 | config_active_interruption_onError : OUT STD_LOGIC; |
|
184 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
185 |
|
|
185 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
186 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
186 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; | |
187 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
187 | status_error_bad_component_error : OUT STD_LOGIC; | |
188 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
188 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
189 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
189 | config_active_interruption_onError : OUT STD_LOGIC; | |
190 |
|
|
190 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
191 |
|
|
191 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
192 |
|
|
192 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
193 |
|
|
193 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
194 |
|
|
194 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
195 |
|
|
195 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
196 |
|
|
196 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
197 |
|
|
197 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
198 |
d |
|
198 | data_shaping_BW : OUT STD_LOGIC; | |
199 |
d |
|
199 | data_shaping_SP0 : OUT STD_LOGIC; | |
200 |
d |
|
200 | data_shaping_SP1 : OUT STD_LOGIC; | |
201 |
d |
|
201 | data_shaping_R0 : OUT STD_LOGIC; | |
202 |
d |
|
202 | data_shaping_R1 : OUT STD_LOGIC; | |
203 |
|
|
203 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
204 |
|
|
204 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
205 |
|
|
205 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
206 |
|
|
206 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
207 |
|
|
207 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
208 | enable_f2 : OUT STD_LOGIC; |
|
208 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
209 | enable_f3 : OUT STD_LOGIC; |
|
209 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
210 | burst_f0 : OUT STD_LOGIC; |
|
210 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
211 |
|
|
211 | enable_f0 : OUT STD_LOGIC; | |
212 |
|
|
212 | enable_f1 : OUT STD_LOGIC; | |
213 |
|
|
213 | enable_f2 : OUT STD_LOGIC; | |
214 |
|
|
214 | enable_f3 : OUT STD_LOGIC; | |
215 |
|
|
215 | burst_f0 : OUT STD_LOGIC; | |
216 |
|
|
216 | burst_f1 : OUT STD_LOGIC; | |
217 |
|
|
217 | burst_f2 : OUT STD_LOGIC; | |
218 |
|
|
218 | run : OUT STD_LOGIC; | |
219 | --------------------------------------------------------------------------- |
|
219 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
220 |
|
|
220 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
221 |
|
|
221 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
222 |
|
|
222 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
223 |
|
|
223 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); | |
224 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
224 | --------------------------------------------------------------------------- | |
225 |
debug_reg |
|
225 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
226 |
debug_reg |
|
226 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
227 |
debug_reg |
|
227 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
228 | END COMPONENT; |
|
228 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
229 |
|
229 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | ||
230 | COMPONENT lpp_top_ms |
|
230 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
231 | GENERIC ( |
|
231 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
232 | Mem_use : INTEGER; |
|
232 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
233 | nb_burst_available_size : INTEGER; |
|
233 | END COMPONENT; | |
234 | nb_snapshot_param_size : INTEGER; |
|
234 | ||
235 | delta_snapshot_size : INTEGER; |
|
235 | COMPONENT lpp_top_ms | |
236 | delta_f2_f0_size : INTEGER; |
|
236 | GENERIC ( | |
237 |
|
|
237 | Mem_use : INTEGER; | |
238 | pindex : INTEGER; |
|
238 | nb_burst_available_size : INTEGER; | |
239 | paddr : INTEGER; |
|
239 | nb_snapshot_param_size : INTEGER; | |
240 | pmask : INTEGER; |
|
240 | delta_snapshot_size : INTEGER; | |
241 |
|
|
241 | delta_f2_f0_size : INTEGER; | |
242 |
|
|
242 | delta_f2_f1_size : INTEGER; | |
243 |
|
|
243 | pindex : INTEGER; | |
244 |
|
|
244 | paddr : INTEGER; | |
245 | PORT ( |
|
245 | pmask : INTEGER; | |
246 |
|
|
246 | pirq_ms : INTEGER; | |
247 |
|
|
247 | pirq_wfp : INTEGER; | |
248 | sample_B : IN Samples14v(2 DOWNTO 0); |
|
248 | hindex_wfp : INTEGER; | |
249 | sample_E : IN Samples14v(4 DOWNTO 0); |
|
249 | hindex_ms : INTEGER); | |
250 | sample_val : IN STD_LOGIC; |
|
250 | PORT ( | |
251 |
|
|
251 | clk : IN STD_LOGIC; | |
252 | apbo : OUT apb_slv_out_type; |
|
252 | rstn : IN STD_LOGIC; | |
253 | ahbi_ms : IN AHB_Mst_In_Type; |
|
253 | sample_B : IN Samples14v(2 DOWNTO 0); | |
254 | ahbo_ms : OUT AHB_Mst_Out_Type; |
|
254 | sample_E : IN Samples14v(4 DOWNTO 0); | |
255 | data_shaping_BW : OUT STD_LOGIC); |
|
255 | sample_val : IN STD_LOGIC; | |
256 | END COMPONENT; |
|
256 | apbi : IN apb_slv_in_type; | |
257 |
|
257 | apbo : OUT apb_slv_out_type; | ||
258 | END lpp_lfr_pkg; |
|
258 | ahbi_ms : IN AHB_Mst_In_Type; | |
|
259 | ahbo_ms : OUT AHB_Mst_Out_Type; | |||
|
260 | data_shaping_BW : OUT STD_LOGIC); | |||
|
261 | END COMPONENT; | |||
|
262 | ||||
|
263 | END lpp_lfr_pkg; |
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