@@ -0,0 +1,76 | |||||
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1 | LIBRARY ieee; | |||
|
2 | USE ieee.std_logic_1164.ALL; | |||
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3 | ||||
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4 | ||||
|
5 | LIBRARY lpp; | |||
|
6 | USE lpp.lpp_memory.ALL; | |||
|
7 | USE lpp.iir_filter.ALL; | |||
|
8 | USE lpp.spectral_matrix_package.ALL; | |||
|
9 | USE lpp.lpp_dma_pkg.ALL; | |||
|
10 | USE lpp.lpp_Header.ALL; | |||
|
11 | USE lpp.lpp_matrix.ALL; | |||
|
12 | USE lpp.lpp_matrix.ALL; | |||
|
13 | USE lpp.lpp_lfr_pkg.ALL; | |||
|
14 | USE lpp.lpp_fft.ALL; | |||
|
15 | USE lpp.fft_components.ALL; | |||
|
16 | ||||
|
17 | ENTITY lpp_lfr_ms_FFT IS | |||
|
18 | PORT ( | |||
|
19 | clk : IN STD_LOGIC; | |||
|
20 | rstn : IN STD_LOGIC; | |||
|
21 | -- IN | |||
|
22 | sample_valid : IN STD_LOGIC; | |||
|
23 | fft_read : IN STD_LOGIC; | |||
|
24 | sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
25 | sample_load : OUT STD_LOGIC; | |||
|
26 | ||||
|
27 | --OUT | |||
|
28 | fft_pong : OUT STD_LOGIC; | |||
|
29 | fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
30 | fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
31 | fft_data_valid : OUT STD_LOGIC; | |||
|
32 | fft_ready : OUT STD_LOGIC | |||
|
33 | ||||
|
34 | ); | |||
|
35 | END; | |||
|
36 | ||||
|
37 | ARCHITECTURE Behavioral OF lpp_lfr_ms_FFT IS | |||
|
38 | ||||
|
39 | BEGIN | |||
|
40 | ||||
|
41 | ----------------------------------------------------------------------------- | |||
|
42 | -- FFT | |||
|
43 | ----------------------------------------------------------------------------- | |||
|
44 | CoreFFT_1 : CoreFFT | |||
|
45 | GENERIC MAP ( | |||
|
46 | LOGPTS => gLOGPTS, | |||
|
47 | LOGLOGPTS => gLOGLOGPTS, | |||
|
48 | WSIZE => gWSIZE, | |||
|
49 | TWIDTH => gTWIDTH, | |||
|
50 | DWIDTH => gDWIDTH, | |||
|
51 | TDWIDTH => gTDWIDTH, | |||
|
52 | RND_MODE => gRND_MODE, | |||
|
53 | SCALE_MODE => gSCALE_MODE, | |||
|
54 | PTS => gPTS, | |||
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55 | HALFPTS => gHALFPTS, | |||
|
56 | inBuf_RWDLY => gInBuf_RWDLY) | |||
|
57 | PORT MAP ( | |||
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58 | clk => clk, | |||
|
59 | ifiStart => '0', -- '1' | |||
|
60 | ifiNreset => rstn, | |||
|
61 | ||||
|
62 | ifiD_valid => sample_valid, -- IN | |||
|
63 | ifiRead_y => fft_read, | |||
|
64 | ifiD_im => (OTHERS => '0'), -- IN | |||
|
65 | ifiD_re => sample_data, -- IN | |||
|
66 | ifoLoad => sample_load, -- IN | |||
|
67 | ||||
|
68 | ifoPong => fft_pong, | |||
|
69 | ifoY_im => fft_data_im, | |||
|
70 | ifoY_re => fft_data_re, | |||
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71 | ifoY_valid => fft_data_valid, | |||
|
72 | ifoY_rdy => fft_ready); | |||
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73 | ||||
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74 | ----------------------------------------------------------------------------- | |||
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75 | ||||
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76 | END Behavioral; |
@@ -1,587 +1,587 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------- |
|
21 | ------------------------------------------------------------------------------- | |
22 | LIBRARY IEEE; |
|
22 | LIBRARY IEEE; | |
23 | USE IEEE.numeric_std.ALL; |
|
23 | USE IEEE.numeric_std.ALL; | |
24 | USE IEEE.std_logic_1164.ALL; |
|
24 | USE IEEE.std_logic_1164.ALL; | |
25 | LIBRARY grlib; |
|
25 | LIBRARY grlib; | |
26 | USE grlib.amba.ALL; |
|
26 | USE grlib.amba.ALL; | |
27 | USE grlib.stdlib.ALL; |
|
27 | USE grlib.stdlib.ALL; | |
28 | LIBRARY techmap; |
|
28 | LIBRARY techmap; | |
29 | USE techmap.gencomp.ALL; |
|
29 | USE techmap.gencomp.ALL; | |
30 | LIBRARY gaisler; |
|
30 | LIBRARY gaisler; | |
31 | USE gaisler.memctrl.ALL; |
|
31 | USE gaisler.memctrl.ALL; | |
32 | USE gaisler.leon3.ALL; |
|
32 | USE gaisler.leon3.ALL; | |
33 | USE gaisler.uart.ALL; |
|
33 | USE gaisler.uart.ALL; | |
34 | USE gaisler.misc.ALL; |
|
34 | USE gaisler.misc.ALL; | |
35 | USE gaisler.spacewire.ALL; |
|
35 | USE gaisler.spacewire.ALL; | |
36 | LIBRARY esa; |
|
36 | LIBRARY esa; | |
37 | USE esa.memoryctrl.ALL; |
|
37 | USE esa.memoryctrl.ALL; | |
38 | LIBRARY lpp; |
|
38 | LIBRARY lpp; | |
39 | USE lpp.lpp_memory.ALL; |
|
39 | USE lpp.lpp_memory.ALL; | |
40 | USE lpp.lpp_ad_conv.ALL; |
|
40 | USE lpp.lpp_ad_conv.ALL; | |
41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
|
41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib | |
42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
|
42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker | |
43 | USE lpp.iir_filter.ALL; |
|
43 | USE lpp.iir_filter.ALL; | |
44 | USE lpp.general_purpose.ALL; |
|
44 | USE lpp.general_purpose.ALL; | |
45 | USE lpp.lpp_lfr_time_management.ALL; |
|
45 | USE lpp.lpp_lfr_time_management.ALL; | |
46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
|
46 | USE lpp.lpp_leon3_soc_pkg.ALL; | |
47 |
|
47 | |||
48 | ENTITY MINI_LFR_top IS |
|
48 | ENTITY MINI_LFR_top IS | |
49 |
|
49 | |||
50 | PORT ( |
|
50 | PORT ( | |
51 | clk_50 : IN STD_LOGIC; |
|
51 | clk_50 : IN STD_LOGIC; | |
52 | clk_49 : IN STD_LOGIC; |
|
52 | clk_49 : IN STD_LOGIC; | |
53 | reset : IN STD_LOGIC; |
|
53 | reset : IN STD_LOGIC; | |
54 | --BPs |
|
54 | --BPs | |
55 | BP0 : IN STD_LOGIC; |
|
55 | BP0 : IN STD_LOGIC; | |
56 | BP1 : IN STD_LOGIC; |
|
56 | BP1 : IN STD_LOGIC; | |
57 | --LEDs |
|
57 | --LEDs | |
58 | LED0 : OUT STD_LOGIC; |
|
58 | LED0 : OUT STD_LOGIC; | |
59 | LED1 : OUT STD_LOGIC; |
|
59 | LED1 : OUT STD_LOGIC; | |
60 | LED2 : OUT STD_LOGIC; |
|
60 | LED2 : OUT STD_LOGIC; | |
61 | --UARTs |
|
61 | --UARTs | |
62 | TXD1 : IN STD_LOGIC; |
|
62 | TXD1 : IN STD_LOGIC; | |
63 | RXD1 : OUT STD_LOGIC; |
|
63 | RXD1 : OUT STD_LOGIC; | |
64 | nCTS1 : OUT STD_LOGIC; |
|
64 | nCTS1 : OUT STD_LOGIC; | |
65 | nRTS1 : IN STD_LOGIC; |
|
65 | nRTS1 : IN STD_LOGIC; | |
66 |
|
66 | |||
67 | TXD2 : IN STD_LOGIC; |
|
67 | TXD2 : IN STD_LOGIC; | |
68 | RXD2 : OUT STD_LOGIC; |
|
68 | RXD2 : OUT STD_LOGIC; | |
69 | nCTS2 : OUT STD_LOGIC; |
|
69 | nCTS2 : OUT STD_LOGIC; | |
70 | nDTR2 : IN STD_LOGIC; |
|
70 | nDTR2 : IN STD_LOGIC; | |
71 | nRTS2 : IN STD_LOGIC; |
|
71 | nRTS2 : IN STD_LOGIC; | |
72 | nDCD2 : OUT STD_LOGIC; |
|
72 | nDCD2 : OUT STD_LOGIC; | |
73 |
|
73 | |||
74 | --EXT CONNECTOR |
|
74 | --EXT CONNECTOR | |
75 | IO0 : INOUT STD_LOGIC; |
|
75 | IO0 : INOUT STD_LOGIC; | |
76 | IO1 : INOUT STD_LOGIC; |
|
76 | IO1 : INOUT STD_LOGIC; | |
77 | IO2 : INOUT STD_LOGIC; |
|
77 | IO2 : INOUT STD_LOGIC; | |
78 | IO3 : INOUT STD_LOGIC; |
|
78 | IO3 : INOUT STD_LOGIC; | |
79 | IO4 : INOUT STD_LOGIC; |
|
79 | IO4 : INOUT STD_LOGIC; | |
80 | IO5 : INOUT STD_LOGIC; |
|
80 | IO5 : INOUT STD_LOGIC; | |
81 | IO6 : INOUT STD_LOGIC; |
|
81 | IO6 : INOUT STD_LOGIC; | |
82 | IO7 : INOUT STD_LOGIC; |
|
82 | IO7 : INOUT STD_LOGIC; | |
83 | IO8 : INOUT STD_LOGIC; |
|
83 | IO8 : INOUT STD_LOGIC; | |
84 | IO9 : INOUT STD_LOGIC; |
|
84 | IO9 : INOUT STD_LOGIC; | |
85 | IO10 : INOUT STD_LOGIC; |
|
85 | IO10 : INOUT STD_LOGIC; | |
86 | IO11 : INOUT STD_LOGIC; |
|
86 | IO11 : INOUT STD_LOGIC; | |
87 |
|
87 | |||
88 | --SPACE WIRE |
|
88 | --SPACE WIRE | |
89 | SPW_EN : OUT STD_LOGIC; -- 0 => off |
|
89 | SPW_EN : OUT STD_LOGIC; -- 0 => off | |
90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK |
|
90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK | |
91 | SPW_NOM_SIN : IN STD_LOGIC; |
|
91 | SPW_NOM_SIN : IN STD_LOGIC; | |
92 | SPW_NOM_DOUT : OUT STD_LOGIC; |
|
92 | SPW_NOM_DOUT : OUT STD_LOGIC; | |
93 | SPW_NOM_SOUT : OUT STD_LOGIC; |
|
93 | SPW_NOM_SOUT : OUT STD_LOGIC; | |
94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK |
|
94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK | |
95 | SPW_RED_SIN : IN STD_LOGIC; |
|
95 | SPW_RED_SIN : IN STD_LOGIC; | |
96 | SPW_RED_DOUT : OUT STD_LOGIC; |
|
96 | SPW_RED_DOUT : OUT STD_LOGIC; | |
97 | SPW_RED_SOUT : OUT STD_LOGIC; |
|
97 | SPW_RED_SOUT : OUT STD_LOGIC; | |
98 | -- MINI LFR ADC INPUTS |
|
98 | -- MINI LFR ADC INPUTS | |
99 | ADC_nCS : OUT STD_LOGIC; |
|
99 | ADC_nCS : OUT STD_LOGIC; | |
100 | ADC_CLK : OUT STD_LOGIC; |
|
100 | ADC_CLK : OUT STD_LOGIC; | |
101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
102 |
|
102 | |||
103 | -- SRAM |
|
103 | -- SRAM | |
104 | SRAM_nWE : OUT STD_LOGIC; |
|
104 | SRAM_nWE : OUT STD_LOGIC; | |
105 | SRAM_CE : OUT STD_LOGIC; |
|
105 | SRAM_CE : OUT STD_LOGIC; | |
106 | SRAM_nOE : OUT STD_LOGIC; |
|
106 | SRAM_nOE : OUT STD_LOGIC; | |
107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
|
108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |
109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
110 | ); |
|
110 | ); | |
111 |
|
111 | |||
112 | END MINI_LFR_top; |
|
112 | END MINI_LFR_top; | |
113 |
|
113 | |||
114 |
|
114 | |||
115 | ARCHITECTURE beh OF MINI_LFR_top IS |
|
115 | ARCHITECTURE beh OF MINI_LFR_top IS | |
116 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
|
116 | SIGNAL clk_50_s : STD_LOGIC := '0'; | |
117 | SIGNAL clk_25 : STD_LOGIC := '0'; |
|
117 | SIGNAL clk_25 : STD_LOGIC := '0'; | |
118 | SIGNAL clk_24 : STD_LOGIC := '0'; |
|
118 | SIGNAL clk_24 : STD_LOGIC := '0'; | |
119 | ----------------------------------------------------------------------------- |
|
119 | ----------------------------------------------------------------------------- | |
120 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
120 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
121 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
121 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
122 | -- |
|
122 | -- | |
123 | SIGNAL errorn : STD_LOGIC; |
|
123 | SIGNAL errorn : STD_LOGIC; | |
124 | -- UART AHB --------------------------------------------------------------- |
|
124 | -- UART AHB --------------------------------------------------------------- | |
125 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data |
|
125 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data | |
126 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data |
|
126 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data | |
127 |
|
127 | |||
128 | -- UART APB --------------------------------------------------------------- |
|
128 | -- UART APB --------------------------------------------------------------- | |
129 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data |
|
129 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data | |
130 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data |
|
130 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data | |
131 | -- |
|
131 | -- | |
132 | SIGNAL I00_s : STD_LOGIC; |
|
132 | SIGNAL I00_s : STD_LOGIC; | |
133 |
|
133 | |||
134 | -- CONSTANTS |
|
134 | -- CONSTANTS | |
135 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
|
135 | CONSTANT CFG_PADTECH : INTEGER := inferred; | |
136 | -- |
|
136 | -- | |
137 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
|
137 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f | |
138 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
|
138 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; | |
139 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
|
139 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker | |
140 |
|
140 | |||
141 | SIGNAL apbi_ext : apb_slv_in_type; |
|
141 | SIGNAL apbi_ext : apb_slv_in_type; | |
142 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
|
142 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); | |
143 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
|
143 | SIGNAL ahbi_s_ext : ahb_slv_in_type; | |
144 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); |
|
144 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); | |
145 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
|
145 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |
146 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); |
|
146 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); | |
147 |
|
147 | |||
148 | -- Spacewire signals |
|
148 | -- Spacewire signals | |
149 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
149 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
150 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
150 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
151 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
151 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
152 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
|
152 | SIGNAL spw_rxtxclk : STD_ULOGIC; | |
153 | SIGNAL spw_rxclkn : STD_ULOGIC; |
|
153 | SIGNAL spw_rxclkn : STD_ULOGIC; | |
154 | SIGNAL spw_clk : STD_LOGIC; |
|
154 | SIGNAL spw_clk : STD_LOGIC; | |
155 | SIGNAL swni : grspw_in_type; |
|
155 | SIGNAL swni : grspw_in_type; | |
156 | SIGNAL swno : grspw_out_type; |
|
156 | SIGNAL swno : grspw_out_type; | |
157 | -- SIGNAL clkmn : STD_ULOGIC; |
|
157 | -- SIGNAL clkmn : STD_ULOGIC; | |
158 | -- SIGNAL txclk : STD_ULOGIC; |
|
158 | -- SIGNAL txclk : STD_ULOGIC; | |
159 |
|
159 | |||
160 | --GPIO |
|
160 | --GPIO | |
161 | SIGNAL gpioi : gpio_in_type; |
|
161 | SIGNAL gpioi : gpio_in_type; | |
162 | SIGNAL gpioo : gpio_out_type; |
|
162 | SIGNAL gpioo : gpio_out_type; | |
163 |
|
163 | |||
164 | -- AD Converter ADS7886 |
|
164 | -- AD Converter ADS7886 | |
165 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
|
165 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
166 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
|
166 | SIGNAL sample_s : Samples(7 DOWNTO 0); | |
167 | SIGNAL sample_val : STD_LOGIC; |
|
167 | SIGNAL sample_val : STD_LOGIC; | |
168 | SIGNAL ADC_nCS_sig : STD_LOGIC; |
|
168 | SIGNAL ADC_nCS_sig : STD_LOGIC; | |
169 | SIGNAL ADC_CLK_sig : STD_LOGIC; |
|
169 | SIGNAL ADC_CLK_sig : STD_LOGIC; | |
170 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
170 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
171 |
|
171 | |||
172 | SIGNAL bias_fail_sw_sig : STD_LOGIC; |
|
172 | SIGNAL bias_fail_sw_sig : STD_LOGIC; | |
173 |
|
173 | |||
174 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
174 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
175 | ----------------------------------------------------------------------------- |
|
175 | ----------------------------------------------------------------------------- | |
176 |
|
176 | |||
177 | BEGIN -- beh |
|
177 | BEGIN -- beh | |
178 |
|
178 | |||
179 | ----------------------------------------------------------------------------- |
|
179 | ----------------------------------------------------------------------------- | |
180 | -- CLK |
|
180 | -- CLK | |
181 | ----------------------------------------------------------------------------- |
|
181 | ----------------------------------------------------------------------------- | |
182 |
|
182 | |||
183 | PROCESS(clk_50) |
|
183 | PROCESS(clk_50) | |
184 | BEGIN |
|
184 | BEGIN | |
185 | IF clk_50'EVENT AND clk_50 = '1' THEN |
|
185 | IF clk_50'EVENT AND clk_50 = '1' THEN | |
186 | clk_50_s <= NOT clk_50_s; |
|
186 | clk_50_s <= NOT clk_50_s; | |
187 | END IF; |
|
187 | END IF; | |
188 | END PROCESS; |
|
188 | END PROCESS; | |
189 |
|
189 | |||
190 | PROCESS(clk_50_s) |
|
190 | PROCESS(clk_50_s) | |
191 | BEGIN |
|
191 | BEGIN | |
192 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
|
192 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN | |
193 | clk_25 <= NOT clk_25; |
|
193 | clk_25 <= NOT clk_25; | |
194 | END IF; |
|
194 | END IF; | |
195 | END PROCESS; |
|
195 | END PROCESS; | |
196 |
|
196 | |||
197 | PROCESS(clk_49) |
|
197 | PROCESS(clk_49) | |
198 | BEGIN |
|
198 | BEGIN | |
199 | IF clk_49'EVENT AND clk_49 = '1' THEN |
|
199 | IF clk_49'EVENT AND clk_49 = '1' THEN | |
200 | clk_24 <= NOT clk_24; |
|
200 | clk_24 <= NOT clk_24; | |
201 | END IF; |
|
201 | END IF; | |
202 | END PROCESS; |
|
202 | END PROCESS; | |
203 |
|
203 | |||
204 | ----------------------------------------------------------------------------- |
|
204 | ----------------------------------------------------------------------------- | |
205 |
|
205 | |||
206 | PROCESS (clk_25, reset) |
|
206 | PROCESS (clk_25, reset) | |
207 | BEGIN -- PROCESS |
|
207 | BEGIN -- PROCESS | |
208 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
208 | IF reset = '0' THEN -- asynchronous reset (active low) | |
209 | LED0 <= '0'; |
|
209 | LED0 <= '0'; | |
210 | LED1 <= '0'; |
|
210 | LED1 <= '0'; | |
211 | LED2 <= '0'; |
|
211 | LED2 <= '0'; | |
212 | --IO1 <= '0'; |
|
212 | --IO1 <= '0'; | |
213 | --IO2 <= '1'; |
|
213 | --IO2 <= '1'; | |
214 | --IO3 <= '0'; |
|
214 | --IO3 <= '0'; | |
215 | --IO4 <= '0'; |
|
215 | --IO4 <= '0'; | |
216 | --IO5 <= '0'; |
|
216 | --IO5 <= '0'; | |
217 | --IO6 <= '0'; |
|
217 | --IO6 <= '0'; | |
218 | --IO7 <= '0'; |
|
218 | --IO7 <= '0'; | |
219 | --IO8 <= '0'; |
|
219 | --IO8 <= '0'; | |
220 | --IO9 <= '0'; |
|
220 | --IO9 <= '0'; | |
221 | --IO10 <= '0'; |
|
221 | --IO10 <= '0'; | |
222 | --IO11 <= '0'; |
|
222 | --IO11 <= '0'; | |
223 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
|
223 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |
224 | LED0 <= '0'; |
|
224 | LED0 <= '0'; | |
225 | LED1 <= '1'; |
|
225 | LED1 <= '1'; | |
226 | LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
|
226 | LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |
227 | --IO1 <= '1'; |
|
227 | --IO1 <= '1'; | |
228 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; |
|
228 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; | |
229 | --IO3 <= ADC_SDO(0); |
|
229 | --IO3 <= ADC_SDO(0); | |
230 | --IO4 <= ADC_SDO(1); |
|
230 | --IO4 <= ADC_SDO(1); | |
231 | --IO5 <= ADC_SDO(2); |
|
231 | --IO5 <= ADC_SDO(2); | |
232 | --IO6 <= ADC_SDO(3); |
|
232 | --IO6 <= ADC_SDO(3); | |
233 | --IO7 <= ADC_SDO(4); |
|
233 | --IO7 <= ADC_SDO(4); | |
234 | --IO8 <= ADC_SDO(5); |
|
234 | --IO8 <= ADC_SDO(5); | |
235 | --IO9 <= ADC_SDO(6); |
|
235 | --IO9 <= ADC_SDO(6); | |
236 | --IO10 <= ADC_SDO(7); |
|
236 | --IO10 <= ADC_SDO(7); | |
237 | --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
|
237 | --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |
238 | END IF; |
|
238 | END IF; | |
239 | END PROCESS; |
|
239 | END PROCESS; | |
240 |
|
240 | |||
241 | PROCESS (clk_24, reset) |
|
241 | PROCESS (clk_24, reset) | |
242 | BEGIN -- PROCESS |
|
242 | BEGIN -- PROCESS | |
243 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
243 | IF reset = '0' THEN -- asynchronous reset (active low) | |
244 | I00_s <= '0'; |
|
244 | I00_s <= '0'; | |
245 | ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge |
|
245 | ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge | |
246 | I00_s <= NOT I00_s ; |
|
246 | I00_s <= NOT I00_s ; | |
247 | END IF; |
|
247 | END IF; | |
248 | END PROCESS; |
|
248 | END PROCESS; | |
249 | -- IO0 <= I00_s; |
|
249 | -- IO0 <= I00_s; | |
250 |
|
250 | |||
251 | --UARTs |
|
251 | --UARTs | |
252 | nCTS1 <= '1'; |
|
252 | nCTS1 <= '1'; | |
253 | nCTS2 <= '1'; |
|
253 | nCTS2 <= '1'; | |
254 | nDCD2 <= '1'; |
|
254 | nDCD2 <= '1'; | |
255 |
|
255 | |||
256 | --EXT CONNECTOR |
|
256 | --EXT CONNECTOR | |
257 |
|
257 | |||
258 | --SPACE WIRE |
|
258 | --SPACE WIRE | |
259 |
|
259 | |||
260 | leon3_soc_1 : leon3_soc |
|
260 | leon3_soc_1 : leon3_soc | |
261 | GENERIC MAP ( |
|
261 | GENERIC MAP ( | |
262 | fabtech => apa3e, |
|
262 | fabtech => apa3e, | |
263 | memtech => apa3e, |
|
263 | memtech => apa3e, | |
264 | padtech => inferred, |
|
264 | padtech => inferred, | |
265 | clktech => inferred, |
|
265 | clktech => inferred, | |
266 | disas => 0, |
|
266 | disas => 0, | |
267 | dbguart => 0, |
|
267 | dbguart => 0, | |
268 | pclow => 2, |
|
268 | pclow => 2, | |
269 | clk_freq => 25000, |
|
269 | clk_freq => 25000, | |
270 | NB_CPU => 1, |
|
270 | NB_CPU => 1, | |
271 | ENABLE_FPU => 1, |
|
271 | ENABLE_FPU => 1, | |
272 | FPU_NETLIST => 0, |
|
272 | FPU_NETLIST => 0, | |
273 | ENABLE_DSU => 1, |
|
273 | ENABLE_DSU => 1, | |
274 | ENABLE_AHB_UART => 1, |
|
274 | ENABLE_AHB_UART => 1, | |
275 | ENABLE_APB_UART => 1, |
|
275 | ENABLE_APB_UART => 1, | |
276 | ENABLE_IRQMP => 1, |
|
276 | ENABLE_IRQMP => 1, | |
277 | ENABLE_GPT => 1, |
|
277 | ENABLE_GPT => 1, | |
278 | NB_AHB_MASTER => NB_AHB_MASTER, |
|
278 | NB_AHB_MASTER => NB_AHB_MASTER, | |
279 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
|
279 | NB_AHB_SLAVE => NB_AHB_SLAVE, | |
280 | NB_APB_SLAVE => NB_APB_SLAVE) |
|
280 | NB_APB_SLAVE => NB_APB_SLAVE) | |
281 | PORT MAP ( |
|
281 | PORT MAP ( | |
282 | clk => clk_25, |
|
282 | clk => clk_25, | |
283 | reset => reset, |
|
283 | reset => reset, | |
284 | errorn => errorn, |
|
284 | errorn => errorn, | |
285 | ahbrxd => TXD1, |
|
285 | ahbrxd => TXD1, | |
286 | ahbtxd => RXD1, |
|
286 | ahbtxd => RXD1, | |
287 | urxd1 => TXD2, |
|
287 | urxd1 => TXD2, | |
288 | utxd1 => RXD2, |
|
288 | utxd1 => RXD2, | |
289 | address => SRAM_A, |
|
289 | address => SRAM_A, | |
290 | data => SRAM_DQ, |
|
290 | data => SRAM_DQ, | |
291 | nSRAM_BE0 => SRAM_nBE(0), |
|
291 | nSRAM_BE0 => SRAM_nBE(0), | |
292 | nSRAM_BE1 => SRAM_nBE(1), |
|
292 | nSRAM_BE1 => SRAM_nBE(1), | |
293 | nSRAM_BE2 => SRAM_nBE(2), |
|
293 | nSRAM_BE2 => SRAM_nBE(2), | |
294 | nSRAM_BE3 => SRAM_nBE(3), |
|
294 | nSRAM_BE3 => SRAM_nBE(3), | |
295 | nSRAM_WE => SRAM_nWE, |
|
295 | nSRAM_WE => SRAM_nWE, | |
296 | nSRAM_CE => SRAM_CE, |
|
296 | nSRAM_CE => SRAM_CE, | |
297 | nSRAM_OE => SRAM_nOE, |
|
297 | nSRAM_OE => SRAM_nOE, | |
298 |
|
298 | |||
299 | apbi_ext => apbi_ext, |
|
299 | apbi_ext => apbi_ext, | |
300 | apbo_ext => apbo_ext, |
|
300 | apbo_ext => apbo_ext, | |
301 | ahbi_s_ext => ahbi_s_ext, |
|
301 | ahbi_s_ext => ahbi_s_ext, | |
302 | ahbo_s_ext => ahbo_s_ext, |
|
302 | ahbo_s_ext => ahbo_s_ext, | |
303 | ahbi_m_ext => ahbi_m_ext, |
|
303 | ahbi_m_ext => ahbi_m_ext, | |
304 | ahbo_m_ext => ahbo_m_ext); |
|
304 | ahbo_m_ext => ahbo_m_ext); | |
305 |
|
305 | |||
306 | ------------------------------------------------------------------------------- |
|
306 | ------------------------------------------------------------------------------- | |
307 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
|
307 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- | |
308 | ------------------------------------------------------------------------------- |
|
308 | ------------------------------------------------------------------------------- | |
309 | apb_lfr_time_management_1 : apb_lfr_time_management |
|
309 | apb_lfr_time_management_1 : apb_lfr_time_management | |
310 | GENERIC MAP ( |
|
310 | GENERIC MAP ( | |
311 | pindex => 6, |
|
311 | pindex => 6, | |
312 | paddr => 6, |
|
312 | paddr => 6, | |
313 | pmask => 16#fff#, |
|
313 | pmask => 16#fff#, | |
314 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 |
|
314 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 | |
315 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
|
315 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set | |
316 | PORT MAP ( |
|
316 | PORT MAP ( | |
317 | clk25MHz => clk_25, |
|
317 | clk25MHz => clk_25, | |
318 | clk24_576MHz => clk_24, -- 49.152MHz/2 |
|
318 | clk24_576MHz => clk_24, -- 49.152MHz/2 | |
319 | resetn => reset, |
|
319 | resetn => reset, | |
320 | grspw_tick => swno.tickout, |
|
320 | grspw_tick => swno.tickout, | |
321 | apbi => apbi_ext, |
|
321 | apbi => apbi_ext, | |
322 | apbo => apbo_ext(6), |
|
322 | apbo => apbo_ext(6), | |
323 | coarse_time => coarse_time, |
|
323 | coarse_time => coarse_time, | |
324 | fine_time => fine_time); |
|
324 | fine_time => fine_time); | |
325 |
|
325 | |||
326 | ----------------------------------------------------------------------- |
|
326 | ----------------------------------------------------------------------- | |
327 | --- SpaceWire -------------------------------------------------------- |
|
327 | --- SpaceWire -------------------------------------------------------- | |
328 | ----------------------------------------------------------------------- |
|
328 | ----------------------------------------------------------------------- | |
329 |
|
329 | |||
330 | SPW_EN <= '1'; |
|
330 | SPW_EN <= '1'; | |
331 |
|
331 | |||
332 | spw_clk <= clk_50_s; |
|
332 | spw_clk <= clk_50_s; | |
333 | spw_rxtxclk <= spw_clk; |
|
333 | spw_rxtxclk <= spw_clk; | |
334 | spw_rxclkn <= NOT spw_rxtxclk; |
|
334 | spw_rxclkn <= NOT spw_rxtxclk; | |
335 |
|
335 | |||
336 | -- PADS for SPW1 |
|
336 | -- PADS for SPW1 | |
337 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
|
337 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) | |
338 | PORT MAP (SPW_NOM_DIN, dtmp(0)); |
|
338 | PORT MAP (SPW_NOM_DIN, dtmp(0)); | |
339 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
|
339 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) | |
340 | PORT MAP (SPW_NOM_SIN, stmp(0)); |
|
340 | PORT MAP (SPW_NOM_SIN, stmp(0)); | |
341 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
341 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) | |
342 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); |
|
342 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); | |
343 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
343 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) | |
344 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); |
|
344 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); | |
345 | -- PADS FOR SPW2 |
|
345 | -- PADS FOR SPW2 | |
346 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
346 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
347 | PORT MAP (SPW_RED_SIN, dtmp(1)); |
|
347 | PORT MAP (SPW_RED_SIN, dtmp(1)); | |
348 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
348 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
349 | PORT MAP (SPW_RED_DIN, stmp(1)); |
|
349 | PORT MAP (SPW_RED_DIN, stmp(1)); | |
350 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
350 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) | |
351 | PORT MAP (SPW_RED_DOUT, swno.d(1)); |
|
351 | PORT MAP (SPW_RED_DOUT, swno.d(1)); | |
352 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
352 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) | |
353 | PORT MAP (SPW_RED_SOUT, swno.s(1)); |
|
353 | PORT MAP (SPW_RED_SOUT, swno.s(1)); | |
354 |
|
354 | |||
355 | -- GRSPW PHY |
|
355 | -- GRSPW PHY | |
356 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
|
356 | --spw1_input: if CFG_SPW_GRSPW = 1 generate | |
357 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
|
357 | spw_inputloop : FOR j IN 0 TO 1 GENERATE | |
358 | spw_phy0 : grspw_phy |
|
358 | spw_phy0 : grspw_phy | |
359 | GENERIC MAP( |
|
359 | GENERIC MAP( | |
360 | tech => apa3e, |
|
360 | tech => apa3e, | |
361 | rxclkbuftype => 1, |
|
361 | rxclkbuftype => 1, | |
362 | scantest => 0) |
|
362 | scantest => 0) | |
363 | PORT MAP( |
|
363 | PORT MAP( | |
364 | rxrst => swno.rxrst, |
|
364 | rxrst => swno.rxrst, | |
365 | di => dtmp(j), |
|
365 | di => dtmp(j), | |
366 | si => stmp(j), |
|
366 | si => stmp(j), | |
367 | rxclko => spw_rxclk(j), |
|
367 | rxclko => spw_rxclk(j), | |
368 | do => swni.d(j), |
|
368 | do => swni.d(j), | |
369 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
|
369 | ndo => swni.nd(j*5+4 DOWNTO j*5), | |
370 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
370 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); | |
371 | END GENERATE spw_inputloop; |
|
371 | END GENERATE spw_inputloop; | |
372 |
|
372 | |||
373 | -- SPW core |
|
373 | -- SPW core | |
374 | sw0 : grspwm GENERIC MAP( |
|
374 | sw0 : grspwm GENERIC MAP( | |
375 | tech => apa3e, |
|
375 | tech => apa3e, | |
376 | hindex => 1, |
|
376 | hindex => 1, | |
377 | pindex => 5, |
|
377 | pindex => 5, | |
378 | paddr => 5, |
|
378 | paddr => 5, | |
379 | pirq => 11, |
|
379 | pirq => 11, | |
380 | sysfreq => 25000, -- CPU_FREQ |
|
380 | sysfreq => 25000, -- CPU_FREQ | |
381 | rmap => 1, |
|
381 | rmap => 1, | |
382 | rmapcrc => 1, |
|
382 | rmapcrc => 1, | |
383 | fifosize1 => 16, |
|
383 | fifosize1 => 16, | |
384 | fifosize2 => 16, |
|
384 | fifosize2 => 16, | |
385 | rxclkbuftype => 1, |
|
385 | rxclkbuftype => 1, | |
386 | rxunaligned => 0, |
|
386 | rxunaligned => 0, | |
387 | rmapbufs => 4, |
|
387 | rmapbufs => 4, | |
388 | ft => 0, |
|
388 | ft => 0, | |
389 | netlist => 0, |
|
389 | netlist => 0, | |
390 | ports => 2, |
|
390 | ports => 2, | |
391 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
|
391 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 | |
392 | memtech => apa3e, |
|
392 | memtech => apa3e, | |
393 | destkey => 2, |
|
393 | destkey => 2, | |
394 | spwcore => 1 |
|
394 | spwcore => 1 | |
395 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
|
395 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 | |
396 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
|
396 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 | |
397 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
|
397 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 | |
398 | ) |
|
398 | ) | |
399 | PORT MAP(reset, clk_25, spw_rxclk(0), |
|
399 | PORT MAP(reset, clk_25, spw_rxclk(0), | |
400 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
|
400 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, | |
401 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
|
401 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), | |
402 | swni, swno); |
|
402 | swni, swno); | |
403 |
|
403 | |||
404 | swni.tickin <= '0'; |
|
404 | swni.tickin <= '0'; | |
405 | swni.rmapen <= '1'; |
|
405 | swni.rmapen <= '1'; | |
406 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz |
|
406 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz | |
407 | swni.tickinraw <= '0'; |
|
407 | swni.tickinraw <= '0'; | |
408 | swni.timein <= (OTHERS => '0'); |
|
408 | swni.timein <= (OTHERS => '0'); | |
409 | swni.dcrstval <= (OTHERS => '0'); |
|
409 | swni.dcrstval <= (OTHERS => '0'); | |
410 | swni.timerrstval <= (OTHERS => '0'); |
|
410 | swni.timerrstval <= (OTHERS => '0'); | |
411 |
|
411 | |||
412 | ------------------------------------------------------------------------------- |
|
412 | ------------------------------------------------------------------------------- | |
413 | -- LFR ------------------------------------------------------------------------ |
|
413 | -- LFR ------------------------------------------------------------------------ | |
414 | ------------------------------------------------------------------------------- |
|
414 | ------------------------------------------------------------------------------- | |
415 | lpp_lfr_1 : lpp_lfr |
|
415 | lpp_lfr_1 : lpp_lfr | |
416 | GENERIC MAP ( |
|
416 | GENERIC MAP ( | |
417 | Mem_use => use_RAM, |
|
417 | Mem_use => use_RAM, | |
418 | nb_data_by_buffer_size => 32, |
|
418 | nb_data_by_buffer_size => 32, | |
419 | nb_word_by_buffer_size => 30, |
|
419 | nb_word_by_buffer_size => 30, | |
420 | nb_snapshot_param_size => 32, |
|
420 | nb_snapshot_param_size => 32, | |
421 | delta_vector_size => 32, |
|
421 | delta_vector_size => 32, | |
422 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
422 | delta_vector_size_f0_2 => 7, -- log2(96) | |
423 | pindex => 15, |
|
423 | pindex => 15, | |
424 | paddr => 15, |
|
424 | paddr => 15, | |
425 | pmask => 16#fff#, |
|
425 | pmask => 16#fff#, | |
426 | pirq_ms => 6, |
|
426 | pirq_ms => 6, | |
427 | pirq_wfp => 14, |
|
427 | pirq_wfp => 14, | |
428 | hindex => 2, |
|
428 | hindex => 2, | |
429 |
top_lfr_version => X"00010 |
|
429 | top_lfr_version => X"00010C") -- aa.bb.cc version | |
430 | PORT MAP ( |
|
430 | PORT MAP ( | |
431 | clk => clk_25, |
|
431 | clk => clk_25, | |
432 | rstn => reset, |
|
432 | rstn => reset, | |
433 | sample_B => sample_s(2 DOWNTO 0), |
|
433 | sample_B => sample_s(2 DOWNTO 0), | |
434 | sample_E => sample_s(7 DOWNTO 3), |
|
434 | sample_E => sample_s(7 DOWNTO 3), | |
435 | sample_val => sample_val, |
|
435 | sample_val => sample_val, | |
436 | apbi => apbi_ext, |
|
436 | apbi => apbi_ext, | |
437 | apbo => apbo_ext(15), |
|
437 | apbo => apbo_ext(15), | |
438 | ahbi => ahbi_m_ext, |
|
438 | ahbi => ahbi_m_ext, | |
439 | ahbo => ahbo_m_ext(2), |
|
439 | ahbo => ahbo_m_ext(2), | |
440 | coarse_time => coarse_time, |
|
440 | coarse_time => coarse_time, | |
441 | fine_time => fine_time, |
|
441 | fine_time => fine_time, | |
442 | data_shaping_BW => bias_fail_sw_sig, |
|
442 | data_shaping_BW => bias_fail_sw_sig, | |
443 | observation_reg => observation_reg); |
|
443 | observation_reg => observation_reg); | |
444 |
|
444 | |||
445 | all_sample: FOR I IN 7 DOWNTO 0 GENERATE |
|
445 | all_sample: FOR I IN 7 DOWNTO 0 GENERATE | |
446 | sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; |
|
446 | sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; | |
447 | END GENERATE all_sample; |
|
447 | END GENERATE all_sample; | |
448 |
|
448 | |||
449 |
|
449 | |||
450 |
|
450 | |||
451 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 |
|
451 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 | |
452 | GENERIC MAP( |
|
452 | GENERIC MAP( | |
453 | ChannelCount => 8, |
|
453 | ChannelCount => 8, | |
454 | SampleNbBits => 14, |
|
454 | SampleNbBits => 14, | |
455 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 |
|
455 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 | |
456 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 |
|
456 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 | |
457 | PORT MAP ( |
|
457 | PORT MAP ( | |
458 | -- CONV |
|
458 | -- CONV | |
459 | cnv_clk => clk_24, |
|
459 | cnv_clk => clk_24, | |
460 | cnv_rstn => reset, |
|
460 | cnv_rstn => reset, | |
461 | cnv => ADC_nCS_sig, |
|
461 | cnv => ADC_nCS_sig, | |
462 | -- DATA |
|
462 | -- DATA | |
463 | clk => clk_25, |
|
463 | clk => clk_25, | |
464 | rstn => reset, |
|
464 | rstn => reset, | |
465 | sck => ADC_CLK_sig, |
|
465 | sck => ADC_CLK_sig, | |
466 | sdo => ADC_SDO_sig, |
|
466 | sdo => ADC_SDO_sig, | |
467 | -- SAMPLE |
|
467 | -- SAMPLE | |
468 | sample => sample, |
|
468 | sample => sample, | |
469 | sample_val => sample_val); |
|
469 | sample_val => sample_val); | |
470 |
|
470 | |||
471 | --IO10 <= ADC_SDO_sig(5); |
|
471 | --IO10 <= ADC_SDO_sig(5); | |
472 | --IO9 <= ADC_SDO_sig(4); |
|
472 | --IO9 <= ADC_SDO_sig(4); | |
473 | --IO8 <= ADC_SDO_sig(3); |
|
473 | --IO8 <= ADC_SDO_sig(3); | |
474 |
|
474 | |||
475 | ADC_nCS <= ADC_nCS_sig; |
|
475 | ADC_nCS <= ADC_nCS_sig; | |
476 | ADC_CLK <= ADC_CLK_sig; |
|
476 | ADC_CLK <= ADC_CLK_sig; | |
477 | ADC_SDO_sig <= ADC_SDO; |
|
477 | ADC_SDO_sig <= ADC_SDO; | |
478 |
|
478 | |||
479 | ---------------------------------------------------------------------- |
|
479 | ---------------------------------------------------------------------- | |
480 | --- GPIO ----------------------------------------------------------- |
|
480 | --- GPIO ----------------------------------------------------------- | |
481 | ---------------------------------------------------------------------- |
|
481 | ---------------------------------------------------------------------- | |
482 |
|
482 | |||
483 | grgpio0 : grgpio |
|
483 | grgpio0 : grgpio | |
484 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) |
|
484 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) | |
485 | PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); |
|
485 | PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); | |
486 |
|
486 | |||
487 | --pio_pad_0 : iopad |
|
487 | --pio_pad_0 : iopad | |
488 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
488 | -- GENERIC MAP (tech => CFG_PADTECH) | |
489 | -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); |
|
489 | -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); | |
490 | --pio_pad_1 : iopad |
|
490 | --pio_pad_1 : iopad | |
491 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
491 | -- GENERIC MAP (tech => CFG_PADTECH) | |
492 | -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); |
|
492 | -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); | |
493 | --pio_pad_2 : iopad |
|
493 | --pio_pad_2 : iopad | |
494 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
494 | -- GENERIC MAP (tech => CFG_PADTECH) | |
495 | -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); |
|
495 | -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); | |
496 | --pio_pad_3 : iopad |
|
496 | --pio_pad_3 : iopad | |
497 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
497 | -- GENERIC MAP (tech => CFG_PADTECH) | |
498 | -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); |
|
498 | -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); | |
499 | --pio_pad_4 : iopad |
|
499 | --pio_pad_4 : iopad | |
500 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
500 | -- GENERIC MAP (tech => CFG_PADTECH) | |
501 | -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); |
|
501 | -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); | |
502 | --pio_pad_5 : iopad |
|
502 | --pio_pad_5 : iopad | |
503 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
503 | -- GENERIC MAP (tech => CFG_PADTECH) | |
504 | -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); |
|
504 | -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); | |
505 | --pio_pad_6 : iopad |
|
505 | --pio_pad_6 : iopad | |
506 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
506 | -- GENERIC MAP (tech => CFG_PADTECH) | |
507 | -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); |
|
507 | -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); | |
508 | --pio_pad_7 : iopad |
|
508 | --pio_pad_7 : iopad | |
509 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
509 | -- GENERIC MAP (tech => CFG_PADTECH) | |
510 | -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); |
|
510 | -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); | |
511 |
|
511 | |||
512 | PROCESS (clk_25, reset) |
|
512 | PROCESS (clk_25, reset) | |
513 | BEGIN -- PROCESS |
|
513 | BEGIN -- PROCESS | |
514 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
514 | IF reset = '0' THEN -- asynchronous reset (active low) | |
515 | IO0 <= '0'; |
|
515 | IO0 <= '0'; | |
516 | IO1 <= '0'; |
|
516 | IO1 <= '0'; | |
517 | IO2 <= '0'; |
|
517 | IO2 <= '0'; | |
518 | IO3 <= '0'; |
|
518 | IO3 <= '0'; | |
519 | IO4 <= '0'; |
|
519 | IO4 <= '0'; | |
520 | IO5 <= '0'; |
|
520 | IO5 <= '0'; | |
521 | IO6 <= '0'; |
|
521 | IO6 <= '0'; | |
522 | IO7 <= '0'; |
|
522 | IO7 <= '0'; | |
523 | IO8 <= '0'; |
|
523 | IO8 <= '0'; | |
524 | IO9 <= '0'; |
|
524 | IO9 <= '0'; | |
525 | IO10 <= '0'; |
|
525 | IO10 <= '0'; | |
526 | IO11 <= '0'; |
|
526 | IO11 <= '0'; | |
527 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge |
|
527 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge | |
528 | CASE gpioo.dout(1 DOWNTO 0) IS |
|
528 | CASE gpioo.dout(1 DOWNTO 0) IS | |
529 | WHEN "00" => |
|
529 | WHEN "00" => | |
530 | IO0 <= observation_reg(0 ); |
|
530 | IO0 <= observation_reg(0 ); | |
531 | IO1 <= observation_reg(1 ); |
|
531 | IO1 <= observation_reg(1 ); | |
532 | IO2 <= observation_reg(2 ); |
|
532 | IO2 <= observation_reg(2 ); | |
533 | IO3 <= observation_reg(3 ); |
|
533 | IO3 <= observation_reg(3 ); | |
534 | IO4 <= observation_reg(4 ); |
|
534 | IO4 <= observation_reg(4 ); | |
535 | IO5 <= observation_reg(5 ); |
|
535 | IO5 <= observation_reg(5 ); | |
536 | IO6 <= observation_reg(6 ); |
|
536 | IO6 <= observation_reg(6 ); | |
537 | IO7 <= observation_reg(7 ); |
|
537 | IO7 <= observation_reg(7 ); | |
538 | IO8 <= observation_reg(8 ); |
|
538 | IO8 <= observation_reg(8 ); | |
539 | IO9 <= observation_reg(9 ); |
|
539 | IO9 <= observation_reg(9 ); | |
540 | IO10 <= observation_reg(10); |
|
540 | IO10 <= observation_reg(10); | |
541 | IO11 <= observation_reg(11); |
|
541 | IO11 <= observation_reg(11); | |
542 | WHEN "01" => |
|
542 | WHEN "01" => | |
543 | IO0 <= observation_reg(0 + 12); |
|
543 | IO0 <= observation_reg(0 + 12); | |
544 | IO1 <= observation_reg(1 + 12); |
|
544 | IO1 <= observation_reg(1 + 12); | |
545 | IO2 <= observation_reg(2 + 12); |
|
545 | IO2 <= observation_reg(2 + 12); | |
546 | IO3 <= observation_reg(3 + 12); |
|
546 | IO3 <= observation_reg(3 + 12); | |
547 | IO4 <= observation_reg(4 + 12); |
|
547 | IO4 <= observation_reg(4 + 12); | |
548 | IO5 <= observation_reg(5 + 12); |
|
548 | IO5 <= observation_reg(5 + 12); | |
549 | IO6 <= observation_reg(6 + 12); |
|
549 | IO6 <= observation_reg(6 + 12); | |
550 | IO7 <= observation_reg(7 + 12); |
|
550 | IO7 <= observation_reg(7 + 12); | |
551 | IO8 <= observation_reg(8 + 12); |
|
551 | IO8 <= observation_reg(8 + 12); | |
552 | IO9 <= observation_reg(9 + 12); |
|
552 | IO9 <= observation_reg(9 + 12); | |
553 | IO10 <= observation_reg(10 + 12); |
|
553 | IO10 <= observation_reg(10 + 12); | |
554 | IO11 <= observation_reg(11 + 12); |
|
554 | IO11 <= observation_reg(11 + 12); | |
555 | WHEN "10" => |
|
555 | WHEN "10" => | |
556 | IO0 <= observation_reg(0 + 12 + 12); |
|
556 | IO0 <= observation_reg(0 + 12 + 12); | |
557 | IO1 <= observation_reg(1 + 12 + 12); |
|
557 | IO1 <= observation_reg(1 + 12 + 12); | |
558 | IO2 <= observation_reg(2 + 12 + 12); |
|
558 | IO2 <= observation_reg(2 + 12 + 12); | |
559 | IO3 <= observation_reg(3 + 12 + 12); |
|
559 | IO3 <= observation_reg(3 + 12 + 12); | |
560 | IO4 <= observation_reg(4 + 12 + 12); |
|
560 | IO4 <= observation_reg(4 + 12 + 12); | |
561 | IO5 <= observation_reg(5 + 12 + 12); |
|
561 | IO5 <= observation_reg(5 + 12 + 12); | |
562 | IO6 <= observation_reg(6 + 12 + 12); |
|
562 | IO6 <= observation_reg(6 + 12 + 12); | |
563 | IO7 <= observation_reg(7 + 12 + 12); |
|
563 | IO7 <= observation_reg(7 + 12 + 12); | |
564 | IO8 <= '0'; |
|
564 | IO8 <= '0'; | |
565 | IO9 <= '0'; |
|
565 | IO9 <= '0'; | |
566 | IO10 <= '0'; |
|
566 | IO10 <= '0'; | |
567 | IO11 <= '0'; |
|
567 | IO11 <= '0'; | |
568 | WHEN "11" => |
|
568 | WHEN "11" => | |
569 | IO0 <= '0'; |
|
569 | IO0 <= '0'; | |
570 | IO1 <= '0'; |
|
570 | IO1 <= '0'; | |
571 | IO2 <= '0'; |
|
571 | IO2 <= '0'; | |
572 | IO3 <= '0'; |
|
572 | IO3 <= '0'; | |
573 | IO4 <= '0'; |
|
573 | IO4 <= '0'; | |
574 | IO5 <= '0'; |
|
574 | IO5 <= '0'; | |
575 | IO6 <= '0'; |
|
575 | IO6 <= '0'; | |
576 | IO7 <= '0'; |
|
576 | IO7 <= '0'; | |
577 | IO8 <= '0'; |
|
577 | IO8 <= '0'; | |
578 | IO9 <= '0'; |
|
578 | IO9 <= '0'; | |
579 | IO10 <= '0'; |
|
579 | IO10 <= '0'; | |
580 | IO11 <= '0'; |
|
580 | IO11 <= '0'; | |
581 | WHEN OTHERS => NULL; |
|
581 | WHEN OTHERS => NULL; | |
582 | END CASE; |
|
582 | END CASE; | |
583 |
|
583 | |||
584 | END IF; |
|
584 | END IF; | |
585 | END PROCESS; |
|
585 | END PROCESS; | |
586 |
|
586 | |||
587 | END beh; |
|
587 | END beh; |
This diff has been collapsed as it changes many lines, (1532 lines changed) Show them Hide them | |||||
@@ -1,762 +1,770 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 | USE ieee.numeric_std.ALL; |
|
3 | USE ieee.numeric_std.ALL; | |
4 |
|
4 | |||
5 | LIBRARY lpp; |
|
5 | LIBRARY lpp; | |
6 | USE lpp.lpp_ad_conv.ALL; |
|
6 | USE lpp.lpp_ad_conv.ALL; | |
7 | USE lpp.iir_filter.ALL; |
|
7 | USE lpp.iir_filter.ALL; | |
8 | USE lpp.FILTERcfg.ALL; |
|
8 | USE lpp.FILTERcfg.ALL; | |
9 | USE lpp.lpp_memory.ALL; |
|
9 | USE lpp.lpp_memory.ALL; | |
10 | USE lpp.lpp_waveform_pkg.ALL; |
|
10 | USE lpp.lpp_waveform_pkg.ALL; | |
11 | USE lpp.lpp_dma_pkg.ALL; |
|
11 | USE lpp.lpp_dma_pkg.ALL; | |
12 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
12 | USE lpp.lpp_top_lfr_pkg.ALL; | |
13 | USE lpp.lpp_lfr_pkg.ALL; |
|
13 | USE lpp.lpp_lfr_pkg.ALL; | |
14 | USE lpp.general_purpose.ALL; |
|
14 | USE lpp.general_purpose.ALL; | |
15 |
|
15 | |||
16 | LIBRARY techmap; |
|
16 | LIBRARY techmap; | |
17 | USE techmap.gencomp.ALL; |
|
17 | USE techmap.gencomp.ALL; | |
18 |
|
18 | |||
19 | LIBRARY grlib; |
|
19 | LIBRARY grlib; | |
20 | USE grlib.amba.ALL; |
|
20 | USE grlib.amba.ALL; | |
21 | USE grlib.stdlib.ALL; |
|
21 | USE grlib.stdlib.ALL; | |
22 | USE grlib.devices.ALL; |
|
22 | USE grlib.devices.ALL; | |
23 | USE GRLIB.DMA2AHB_Package.ALL; |
|
23 | USE GRLIB.DMA2AHB_Package.ALL; | |
24 |
|
24 | |||
25 | ENTITY lpp_lfr IS |
|
25 | ENTITY lpp_lfr IS | |
26 | GENERIC ( |
|
26 | GENERIC ( | |
27 | Mem_use : INTEGER := use_RAM; |
|
27 | Mem_use : INTEGER := use_RAM; | |
28 | nb_data_by_buffer_size : INTEGER := 11; |
|
28 | nb_data_by_buffer_size : INTEGER := 11; | |
29 | nb_word_by_buffer_size : INTEGER := 11; |
|
29 | nb_word_by_buffer_size : INTEGER := 11; | |
30 | nb_snapshot_param_size : INTEGER := 11; |
|
30 | nb_snapshot_param_size : INTEGER := 11; | |
31 | delta_vector_size : INTEGER := 20; |
|
31 | delta_vector_size : INTEGER := 20; | |
32 | delta_vector_size_f0_2 : INTEGER := 7; |
|
32 | delta_vector_size_f0_2 : INTEGER := 7; | |
33 |
|
33 | |||
34 | pindex : INTEGER := 4; |
|
34 | pindex : INTEGER := 4; | |
35 | paddr : INTEGER := 4; |
|
35 | paddr : INTEGER := 4; | |
36 | pmask : INTEGER := 16#fff#; |
|
36 | pmask : INTEGER := 16#fff#; | |
37 | pirq_ms : INTEGER := 0; |
|
37 | pirq_ms : INTEGER := 0; | |
38 | pirq_wfp : INTEGER := 1; |
|
38 | pirq_wfp : INTEGER := 1; | |
39 |
|
39 | |||
40 | hindex : INTEGER := 2; |
|
40 | hindex : INTEGER := 2; | |
41 |
|
41 | |||
42 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0') |
|
42 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0') | |
43 |
|
43 | |||
44 | ); |
|
44 | ); | |
45 | PORT ( |
|
45 | PORT ( | |
46 | clk : IN STD_LOGIC; |
|
46 | clk : IN STD_LOGIC; | |
47 | rstn : IN STD_LOGIC; |
|
47 | rstn : IN STD_LOGIC; | |
48 | -- SAMPLE |
|
48 | -- SAMPLE | |
49 | sample_B : IN Samples(2 DOWNTO 0); |
|
49 | sample_B : IN Samples(2 DOWNTO 0); | |
50 | sample_E : IN Samples(4 DOWNTO 0); |
|
50 | sample_E : IN Samples(4 DOWNTO 0); | |
51 | sample_val : IN STD_LOGIC; |
|
51 | sample_val : IN STD_LOGIC; | |
52 | -- APB |
|
52 | -- APB | |
53 | apbi : IN apb_slv_in_type; |
|
53 | apbi : IN apb_slv_in_type; | |
54 | apbo : OUT apb_slv_out_type; |
|
54 | apbo : OUT apb_slv_out_type; | |
55 | -- AHB |
|
55 | -- AHB | |
56 | ahbi : IN AHB_Mst_In_Type; |
|
56 | ahbi : IN AHB_Mst_In_Type; | |
57 | ahbo : OUT AHB_Mst_Out_Type; |
|
57 | ahbo : OUT AHB_Mst_Out_Type; | |
58 | -- TIME |
|
58 | -- TIME | |
59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
61 | -- |
|
61 | -- | |
62 | data_shaping_BW : OUT STD_LOGIC; |
|
62 | data_shaping_BW : OUT STD_LOGIC; | |
63 | -- |
|
63 | -- | |
64 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
64 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
65 |
|
65 | |||
66 | --debug |
|
66 | --debug | |
67 | --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
67 | --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
68 | --debug_f0_data_valid : OUT STD_LOGIC; |
|
68 | --debug_f0_data_valid : OUT STD_LOGIC; | |
69 | --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
69 | --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
70 | --debug_f1_data_valid : OUT STD_LOGIC; |
|
70 | --debug_f1_data_valid : OUT STD_LOGIC; | |
71 | --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
71 | --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
72 | --debug_f2_data_valid : OUT STD_LOGIC; |
|
72 | --debug_f2_data_valid : OUT STD_LOGIC; | |
73 | --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
73 | --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
74 | --debug_f3_data_valid : OUT STD_LOGIC; |
|
74 | --debug_f3_data_valid : OUT STD_LOGIC; | |
75 |
|
75 | |||
76 | ---- debug FIFO_IN |
|
76 | ---- debug FIFO_IN | |
77 | --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
77 | --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
78 | --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; |
|
78 | --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; | |
79 | --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
79 | --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
80 | --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; |
|
80 | --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; | |
81 | --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
81 | --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
82 | --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; |
|
82 | --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; | |
83 | --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
83 | --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
84 | --debug_f3_data_fifo_in_valid : OUT STD_LOGIC; |
|
84 | --debug_f3_data_fifo_in_valid : OUT STD_LOGIC; | |
85 |
|
85 | |||
86 | ----debug FIFO OUT |
|
86 | ----debug FIFO OUT | |
87 | --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
87 | --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
88 | --debug_f0_data_fifo_out_valid : OUT STD_LOGIC; |
|
88 | --debug_f0_data_fifo_out_valid : OUT STD_LOGIC; | |
89 | --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
89 | --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
90 | --debug_f1_data_fifo_out_valid : OUT STD_LOGIC; |
|
90 | --debug_f1_data_fifo_out_valid : OUT STD_LOGIC; | |
91 | --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
92 | --debug_f2_data_fifo_out_valid : OUT STD_LOGIC; |
|
92 | --debug_f2_data_fifo_out_valid : OUT STD_LOGIC; | |
93 | --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
93 | --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
94 | --debug_f3_data_fifo_out_valid : OUT STD_LOGIC; |
|
94 | --debug_f3_data_fifo_out_valid : OUT STD_LOGIC; | |
95 |
|
95 | |||
96 | ----debug DMA IN |
|
96 | ----debug DMA IN | |
97 | --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
97 | --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
98 | --debug_f0_data_dma_in_valid : OUT STD_LOGIC; |
|
98 | --debug_f0_data_dma_in_valid : OUT STD_LOGIC; | |
99 | --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
99 | --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
100 | --debug_f1_data_dma_in_valid : OUT STD_LOGIC; |
|
100 | --debug_f1_data_dma_in_valid : OUT STD_LOGIC; | |
101 | --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
101 | --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
102 | --debug_f2_data_dma_in_valid : OUT STD_LOGIC; |
|
102 | --debug_f2_data_dma_in_valid : OUT STD_LOGIC; | |
103 | --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
103 | --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
104 | --debug_f3_data_dma_in_valid : OUT STD_LOGIC |
|
104 | --debug_f3_data_dma_in_valid : OUT STD_LOGIC | |
105 | ); |
|
105 | ); | |
106 | END lpp_lfr; |
|
106 | END lpp_lfr; | |
107 |
|
107 | |||
108 | ARCHITECTURE beh OF lpp_lfr IS |
|
108 | ARCHITECTURE beh OF lpp_lfr IS | |
109 | --SIGNAL sample : Samples14v(7 DOWNTO 0); |
|
109 | --SIGNAL sample : Samples14v(7 DOWNTO 0); | |
110 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
|
110 | SIGNAL sample_s : Samples(7 DOWNTO 0); | |
111 | -- |
|
111 | -- | |
112 | SIGNAL data_shaping_SP0 : STD_LOGIC; |
|
112 | SIGNAL data_shaping_SP0 : STD_LOGIC; | |
113 | SIGNAL data_shaping_SP1 : STD_LOGIC; |
|
113 | SIGNAL data_shaping_SP1 : STD_LOGIC; | |
114 | SIGNAL data_shaping_R0 : STD_LOGIC; |
|
114 | SIGNAL data_shaping_R0 : STD_LOGIC; | |
115 | SIGNAL data_shaping_R1 : STD_LOGIC; |
|
115 | SIGNAL data_shaping_R1 : STD_LOGIC; | |
116 | -- |
|
116 | -- | |
117 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
117 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
118 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
118 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
119 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
119 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
120 | -- |
|
120 | -- | |
121 | SIGNAL sample_f0_val : STD_LOGIC; |
|
121 | SIGNAL sample_f0_val : STD_LOGIC; | |
122 | SIGNAL sample_f1_val : STD_LOGIC; |
|
122 | SIGNAL sample_f1_val : STD_LOGIC; | |
123 | SIGNAL sample_f2_val : STD_LOGIC; |
|
123 | SIGNAL sample_f2_val : STD_LOGIC; | |
124 | SIGNAL sample_f3_val : STD_LOGIC; |
|
124 | SIGNAL sample_f3_val : STD_LOGIC; | |
125 | -- |
|
125 | -- | |
126 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
126 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
127 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
127 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
128 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
128 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
129 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
129 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
130 | -- |
|
130 | -- | |
131 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
131 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
132 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
132 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
133 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
133 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
134 |
|
134 | |||
135 | -- SM |
|
135 | -- SM | |
136 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; |
|
136 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; | |
137 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; |
|
137 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; | |
138 | SIGNAL ready_matrix_f1 : STD_LOGIC; |
|
138 | SIGNAL ready_matrix_f1 : STD_LOGIC; | |
139 | SIGNAL ready_matrix_f2 : STD_LOGIC; |
|
139 | SIGNAL ready_matrix_f2 : STD_LOGIC; | |
140 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; |
|
140 | -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC; | |
141 | SIGNAL error_bad_component_error : STD_LOGIC; |
|
141 | SIGNAL error_bad_component_error : STD_LOGIC; | |
142 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
142 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
143 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; |
|
143 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; | |
144 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; |
|
144 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; | |
145 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; |
|
145 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; | |
146 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; |
|
146 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; | |
147 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; |
|
147 | -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; | |
148 | SIGNAL status_error_bad_component_error : STD_LOGIC; |
|
148 | -- SIGNAL status_error_bad_component_error : STD_LOGIC; | |
149 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; |
|
149 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; | |
150 | SIGNAL config_active_interruption_onError : STD_LOGIC; |
|
150 | SIGNAL config_active_interruption_onError : STD_LOGIC; | |
151 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
151 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
152 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
152 | -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
153 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
153 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
154 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
154 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
155 |
|
155 | |||
156 | -- WFP |
|
156 | -- WFP | |
157 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
157 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
158 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
158 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
159 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
159 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
160 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
160 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
161 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
161 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
162 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
162 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
163 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
163 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
164 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
164 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
165 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
165 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
166 |
|
166 | |||
167 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
167 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
168 | SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
168 | SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
169 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
169 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
170 | SIGNAL enable_f0 : STD_LOGIC; |
|
170 | SIGNAL enable_f0 : STD_LOGIC; | |
171 | SIGNAL enable_f1 : STD_LOGIC; |
|
171 | SIGNAL enable_f1 : STD_LOGIC; | |
172 | SIGNAL enable_f2 : STD_LOGIC; |
|
172 | SIGNAL enable_f2 : STD_LOGIC; | |
173 | SIGNAL enable_f3 : STD_LOGIC; |
|
173 | SIGNAL enable_f3 : STD_LOGIC; | |
174 | SIGNAL burst_f0 : STD_LOGIC; |
|
174 | SIGNAL burst_f0 : STD_LOGIC; | |
175 | SIGNAL burst_f1 : STD_LOGIC; |
|
175 | SIGNAL burst_f1 : STD_LOGIC; | |
176 | SIGNAL burst_f2 : STD_LOGIC; |
|
176 | SIGNAL burst_f2 : STD_LOGIC; | |
177 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
177 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
178 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
178 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
179 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
179 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
180 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
180 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
181 |
|
181 | |||
182 | SIGNAL run : STD_LOGIC; |
|
182 | SIGNAL run : STD_LOGIC; | |
183 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
183 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
184 |
|
184 | |||
185 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
185 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
186 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
186 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
187 | SIGNAL data_f0_data_out_valid : STD_LOGIC; |
|
187 | SIGNAL data_f0_data_out_valid : STD_LOGIC; | |
188 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; |
|
188 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; | |
189 | SIGNAL data_f0_data_out_ren : STD_LOGIC; |
|
189 | SIGNAL data_f0_data_out_ren : STD_LOGIC; | |
190 | --f1 |
|
190 | --f1 | |
191 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
191 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
192 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
192 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
193 | SIGNAL data_f1_data_out_valid : STD_LOGIC; |
|
193 | SIGNAL data_f1_data_out_valid : STD_LOGIC; | |
194 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; |
|
194 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; | |
195 | SIGNAL data_f1_data_out_ren : STD_LOGIC; |
|
195 | SIGNAL data_f1_data_out_ren : STD_LOGIC; | |
196 | --f2 |
|
196 | --f2 | |
197 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
197 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
198 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
198 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
199 | SIGNAL data_f2_data_out_valid : STD_LOGIC; |
|
199 | SIGNAL data_f2_data_out_valid : STD_LOGIC; | |
200 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; |
|
200 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; | |
201 | SIGNAL data_f2_data_out_ren : STD_LOGIC; |
|
201 | SIGNAL data_f2_data_out_ren : STD_LOGIC; | |
202 | --f3 |
|
202 | --f3 | |
203 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
203 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
204 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
204 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
205 | SIGNAL data_f3_data_out_valid : STD_LOGIC; |
|
205 | SIGNAL data_f3_data_out_valid : STD_LOGIC; | |
206 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; |
|
206 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; | |
207 | SIGNAL data_f3_data_out_ren : STD_LOGIC; |
|
207 | SIGNAL data_f3_data_out_ren : STD_LOGIC; | |
208 |
|
208 | |||
209 | ----------------------------------------------------------------------------- |
|
209 | ----------------------------------------------------------------------------- | |
210 | -- |
|
210 | -- | |
211 | ----------------------------------------------------------------------------- |
|
211 | ----------------------------------------------------------------------------- | |
212 | SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
212 | SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
213 | SIGNAL data_f0_data_out_valid_s : STD_LOGIC; |
|
213 | SIGNAL data_f0_data_out_valid_s : STD_LOGIC; | |
214 | SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; |
|
214 | SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; | |
215 | --f1 |
|
215 | --f1 | |
216 | SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
216 | SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
217 | SIGNAL data_f1_data_out_valid_s : STD_LOGIC; |
|
217 | SIGNAL data_f1_data_out_valid_s : STD_LOGIC; | |
218 | SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; |
|
218 | SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; | |
219 | --f2 |
|
219 | --f2 | |
220 | SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
220 | SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
221 | SIGNAL data_f2_data_out_valid_s : STD_LOGIC; |
|
221 | SIGNAL data_f2_data_out_valid_s : STD_LOGIC; | |
222 | SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; |
|
222 | SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; | |
223 | --f3 |
|
223 | --f3 | |
224 | SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
224 | SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
225 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; |
|
225 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; | |
226 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; |
|
226 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; | |
227 |
|
227 | |||
228 | ----------------------------------------------------------------------------- |
|
228 | ----------------------------------------------------------------------------- | |
229 | -- DMA RR |
|
229 | -- DMA RR | |
230 | ----------------------------------------------------------------------------- |
|
230 | ----------------------------------------------------------------------------- | |
231 | SIGNAL dma_sel_valid : STD_LOGIC; |
|
231 | SIGNAL dma_sel_valid : STD_LOGIC; | |
232 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
232 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
233 | SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
233 | SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
234 | SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
234 | SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
235 | SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
235 | SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
236 |
|
236 | |||
237 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
237 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
238 | SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
238 | SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
239 |
|
239 | |||
240 | ----------------------------------------------------------------------------- |
|
240 | ----------------------------------------------------------------------------- | |
241 | -- DMA_REG |
|
241 | -- DMA_REG | |
242 | ----------------------------------------------------------------------------- |
|
242 | ----------------------------------------------------------------------------- | |
243 | SIGNAL ongoing_reg : STD_LOGIC; |
|
243 | SIGNAL ongoing_reg : STD_LOGIC; | |
244 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
244 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
245 | SIGNAL dma_send_reg : STD_LOGIC; |
|
245 | SIGNAL dma_send_reg : STD_LOGIC; | |
246 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
246 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
247 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
247 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
248 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
248 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
249 |
|
249 | |||
250 |
|
250 | |||
251 | ----------------------------------------------------------------------------- |
|
251 | ----------------------------------------------------------------------------- | |
252 | -- DMA |
|
252 | -- DMA | |
253 | ----------------------------------------------------------------------------- |
|
253 | ----------------------------------------------------------------------------- | |
254 | SIGNAL dma_send : STD_LOGIC; |
|
254 | SIGNAL dma_send : STD_LOGIC; | |
255 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
255 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
256 | SIGNAL dma_done : STD_LOGIC; |
|
256 | SIGNAL dma_done : STD_LOGIC; | |
257 | SIGNAL dma_ren : STD_LOGIC; |
|
257 | SIGNAL dma_ren : STD_LOGIC; | |
258 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
258 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
259 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
259 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
260 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
260 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
261 |
|
261 | |||
262 | ----------------------------------------------------------------------------- |
|
262 | ----------------------------------------------------------------------------- | |
263 | -- DEBUG |
|
263 | -- DEBUG | |
264 | ----------------------------------------------------------------------------- |
|
264 | ----------------------------------------------------------------------------- | |
265 | -- |
|
265 | -- | |
266 | SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
266 | SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
267 | SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
267 | SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
268 | SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
268 | SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
269 | SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
269 | SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
270 |
|
270 | |||
271 | SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
271 | SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
272 | SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
272 | SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
273 | SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
273 | SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
274 | SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
274 | SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
275 | SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
275 | SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
276 | SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
276 | SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
277 | SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
277 | SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
278 | SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
278 | SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
279 |
|
279 | |||
280 | ----------------------------------------------------------------------------- |
|
280 | ----------------------------------------------------------------------------- | |
281 | -- MS |
|
281 | -- MS | |
282 | ----------------------------------------------------------------------------- |
|
282 | ----------------------------------------------------------------------------- | |
283 |
|
283 | |||
284 | SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
284 | SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
285 | SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
285 | SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
286 | SIGNAL data_ms_valid : STD_LOGIC; |
|
286 | SIGNAL data_ms_valid : STD_LOGIC; | |
287 | SIGNAL data_ms_valid_burst : STD_LOGIC; |
|
287 | SIGNAL data_ms_valid_burst : STD_LOGIC; | |
288 | SIGNAL data_ms_ren : STD_LOGIC; |
|
288 | SIGNAL data_ms_ren : STD_LOGIC; | |
289 | SIGNAL data_ms_done : STD_LOGIC; |
|
289 | SIGNAL data_ms_done : STD_LOGIC; | |
290 |
|
290 | |||
291 | SIGNAL run_ms : STD_LOGIC; |
|
291 | SIGNAL run_ms : STD_LOGIC; | |
292 | SIGNAL ms_softandhard_rstn : STD_LOGIC; |
|
292 | SIGNAL ms_softandhard_rstn : STD_LOGIC; | |
293 |
|
293 | |||
294 | SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
294 | SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
295 | SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
295 | -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
296 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
296 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
297 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
297 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
298 |
|
298 | |||
299 |
|
299 | |||
300 | BEGIN |
|
300 | SIGNAL error_buffer_full : STD_LOGIC; | |
301 |
|
301 | SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); | ||
302 | sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); |
|
302 | ||
303 | sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); |
|
303 | BEGIN | |
304 |
|
304 | |||
305 | --all_channel : FOR i IN 7 DOWNTO 0 GENERATE |
|
305 | sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); | |
306 | -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); |
|
306 | sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); | |
307 | --END GENERATE all_channel; |
|
307 | ||
308 |
|
308 | --all_channel : FOR i IN 7 DOWNTO 0 GENERATE | ||
309 | ----------------------------------------------------------------------------- |
|
309 | -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); | |
310 | lpp_lfr_filter_1 : lpp_lfr_filter |
|
310 | --END GENERATE all_channel; | |
311 | GENERIC MAP ( |
|
311 | ||
312 | Mem_use => Mem_use) |
|
312 | ----------------------------------------------------------------------------- | |
313 | PORT MAP ( |
|
313 | lpp_lfr_filter_1 : lpp_lfr_filter | |
314 | sample => sample_s, |
|
314 | GENERIC MAP ( | |
315 | sample_val => sample_val, |
|
315 | Mem_use => Mem_use) | |
316 | clk => clk, |
|
316 | PORT MAP ( | |
317 |
|
|
317 | sample => sample_s, | |
318 | data_shaping_SP0 => data_shaping_SP0, |
|
318 | sample_val => sample_val, | |
319 | data_shaping_SP1 => data_shaping_SP1, |
|
319 | clk => clk, | |
320 | data_shaping_R0 => data_shaping_R0, |
|
320 | rstn => rstn, | |
321 |
data_shaping_ |
|
321 | data_shaping_SP0 => data_shaping_SP0, | |
322 | sample_f0_val => sample_f0_val, |
|
322 | data_shaping_SP1 => data_shaping_SP1, | |
323 | sample_f1_val => sample_f1_val, |
|
323 | data_shaping_R0 => data_shaping_R0, | |
324 | sample_f2_val => sample_f2_val, |
|
324 | data_shaping_R1 => data_shaping_R1, | |
325 |
sample_f |
|
325 | sample_f0_val => sample_f0_val, | |
326 |
sample_f |
|
326 | sample_f1_val => sample_f1_val, | |
327 |
sample_f |
|
327 | sample_f2_val => sample_f2_val, | |
328 |
sample_f |
|
328 | sample_f3_val => sample_f3_val, | |
329 |
sample_f |
|
329 | sample_f0_wdata => sample_f0_data, | |
330 |
|
330 | sample_f1_wdata => sample_f1_data, | ||
331 | ----------------------------------------------------------------------------- |
|
331 | sample_f2_wdata => sample_f2_data, | |
332 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg |
|
332 | sample_f3_wdata => sample_f3_data); | |
333 | GENERIC MAP ( |
|
333 | ||
334 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
334 | ----------------------------------------------------------------------------- | |
335 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
|
335 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg | |
336 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
336 | GENERIC MAP ( | |
337 |
|
|
337 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |
338 | delta_vector_size_f0_2 => delta_vector_size_f0_2, |
|
338 | nb_word_by_buffer_size => nb_word_by_buffer_size, | |
339 | pindex => pindex, |
|
339 | nb_snapshot_param_size => nb_snapshot_param_size, | |
340 | paddr => paddr, |
|
340 | delta_vector_size => delta_vector_size, | |
341 | pmask => pmask, |
|
341 | delta_vector_size_f0_2 => delta_vector_size_f0_2, | |
342 |
pi |
|
342 | pindex => pindex, | |
343 |
p |
|
343 | paddr => paddr, | |
344 | top_lfr_version => top_lfr_version) |
|
344 | pmask => pmask, | |
345 | PORT MAP ( |
|
345 | pirq_ms => pirq_ms, | |
346 | HCLK => clk, |
|
346 | pirq_wfp => pirq_wfp, | |
347 | HRESETn => rstn, |
|
347 | top_lfr_version => top_lfr_version) | |
348 | apbi => apbi, |
|
348 | PORT MAP ( | |
349 |
|
|
349 | HCLK => clk, | |
350 |
|
350 | HRESETn => rstn, | ||
351 | run_ms => run_ms, |
|
351 | apbi => apbi, | |
352 |
|
352 | apbo => apbo, | ||
353 | ready_matrix_f0_0 => ready_matrix_f0_0, |
|
353 | ||
354 | ready_matrix_f0_1 => ready_matrix_f0_1, |
|
354 | run_ms => run_ms, | |
355 | ready_matrix_f1 => ready_matrix_f1, |
|
355 | ||
356 |
ready_matrix_f |
|
356 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
357 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
357 | -- ready_matrix_f0_1 => ready_matrix_f0_1, | |
358 | error_bad_component_error => error_bad_component_error, |
|
358 | ready_matrix_f1 => ready_matrix_f1, | |
359 |
|
|
359 | ready_matrix_f2 => ready_matrix_f2, | |
360 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
|
360 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
361 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
361 | error_bad_component_error => error_bad_component_error, | |
362 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
362 | error_buffer_full => error_buffer_full, -- TODO | |
363 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
363 | error_input_fifo_write => error_input_fifo_write, -- TODO | |
364 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
364 | debug_reg => debug_reg, | |
365 | status_error_bad_component_error => status_error_bad_component_error, |
|
365 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
366 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
366 | -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
367 | config_active_interruption_onError => config_active_interruption_onError, |
|
367 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
368 |
|
368 | status_ready_matrix_f2 => status_ready_matrix_f2, | ||
369 | matrix_time_f0_0 => matrix_time_f0_0, |
|
369 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
370 | matrix_time_f0_1 => matrix_time_f0_1, |
|
370 | -- status_error_bad_component_error => status_error_bad_component_error, | |
371 | matrix_time_f1 => matrix_time_f1, |
|
371 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
372 | matrix_time_f2 => matrix_time_f2, |
|
372 | config_active_interruption_onError => config_active_interruption_onError, | |
373 |
|
373 | |||
374 |
|
|
374 | matrix_time_f0_0 => matrix_time_f0_0, | |
375 |
|
|
375 | -- matrix_time_f0_1 => matrix_time_f0_1, | |
376 |
|
|
376 | matrix_time_f1 => matrix_time_f1, | |
377 |
|
|
377 | matrix_time_f2 => matrix_time_f2, | |
378 | status_full => status_full, |
|
378 | ||
379 | status_full_ack => status_full_ack, |
|
379 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
380 | status_full_err => status_full_err, |
|
380 | -- addr_matrix_f0_1 => addr_matrix_f0_1, | |
381 | status_new_err => status_new_err, |
|
381 | addr_matrix_f1 => addr_matrix_f1, | |
382 | data_shaping_BW => data_shaping_BW, |
|
382 | addr_matrix_f2 => addr_matrix_f2, | |
383 | data_shaping_SP0 => data_shaping_SP0, |
|
383 | ------------------------------------------------------------------------- | |
384 | data_shaping_SP1 => data_shaping_SP1, |
|
384 | status_full => status_full, | |
385 | data_shaping_R0 => data_shaping_R0, |
|
385 | status_full_ack => status_full_ack, | |
386 | data_shaping_R1 => data_shaping_R1, |
|
386 | status_full_err => status_full_err, | |
387 | delta_snapshot => delta_snapshot, |
|
387 | status_new_err => status_new_err, | |
388 | delta_f0 => delta_f0, |
|
388 | data_shaping_BW => data_shaping_BW, | |
389 | delta_f0_2 => delta_f0_2, |
|
389 | data_shaping_SP0 => data_shaping_SP0, | |
390 | delta_f1 => delta_f1, |
|
390 | data_shaping_SP1 => data_shaping_SP1, | |
391 | delta_f2 => delta_f2, |
|
391 | data_shaping_R0 => data_shaping_R0, | |
392 | nb_data_by_buffer => nb_data_by_buffer, |
|
392 | data_shaping_R1 => data_shaping_R1, | |
393 | nb_word_by_buffer => nb_word_by_buffer, |
|
393 | delta_snapshot => delta_snapshot, | |
394 | nb_snapshot_param => nb_snapshot_param, |
|
394 | delta_f0 => delta_f0, | |
395 |
|
|
395 | delta_f0_2 => delta_f0_2, | |
396 |
|
|
396 | delta_f1 => delta_f1, | |
397 |
|
|
397 | delta_f2 => delta_f2, | |
398 | enable_f3 => enable_f3, |
|
398 | nb_data_by_buffer => nb_data_by_buffer, | |
399 | burst_f0 => burst_f0, |
|
399 | nb_word_by_buffer => nb_word_by_buffer, | |
400 | burst_f1 => burst_f1, |
|
400 | nb_snapshot_param => nb_snapshot_param, | |
401 |
|
|
401 | enable_f0 => enable_f0, | |
402 |
|
|
402 | enable_f1 => enable_f1, | |
403 | addr_data_f0 => addr_data_f0, |
|
403 | enable_f2 => enable_f2, | |
404 | addr_data_f1 => addr_data_f1, |
|
404 | enable_f3 => enable_f3, | |
405 |
|
|
405 | burst_f0 => burst_f0, | |
406 |
|
|
406 | burst_f1 => burst_f1, | |
407 |
|
|
407 | burst_f2 => burst_f2, | |
408 | --------------------------------------------------------------------------- |
|
408 | run => run, | |
409 | debug_reg0 => debug_reg0, |
|
409 | addr_data_f0 => addr_data_f0, | |
410 | debug_reg1 => debug_reg1, |
|
410 | addr_data_f1 => addr_data_f1, | |
411 | debug_reg2 => debug_reg2, |
|
411 | addr_data_f2 => addr_data_f2, | |
412 | debug_reg3 => debug_reg3, |
|
412 | addr_data_f3 => addr_data_f3, | |
413 | debug_reg4 => debug_reg4, |
|
413 | start_date => start_date, | |
414 | debug_reg5 => debug_reg5, |
|
414 | --------------------------------------------------------------------------- | |
415 |
debug_reg |
|
415 | debug_reg0 => debug_reg0, | |
416 |
debug_reg |
|
416 | debug_reg1 => debug_reg1, | |
417 |
|
417 | debug_reg2 => debug_reg2, | ||
418 | debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0); |
|
418 | debug_reg3 => debug_reg3, | |
419 | debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); |
|
419 | debug_reg4 => debug_reg4, | |
420 | debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2); |
|
420 | debug_reg5 => debug_reg5, | |
421 | ----------------------------------------------------------------------------- |
|
421 | debug_reg6 => debug_reg6, | |
422 | --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug |
|
422 | debug_reg7 => debug_reg7); | |
423 | --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug |
|
423 | ||
424 | --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug |
|
424 | debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0); | |
425 | --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug |
|
425 | debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); | |
426 |
|
426 | debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2); | ||
427 |
|
427 | ----------------------------------------------------------------------------- | ||
428 | ----------------------------------------------------------------------------- |
|
428 | --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug | |
429 | lpp_waveform_1 : lpp_waveform |
|
429 | --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug | |
430 | GENERIC MAP ( |
|
430 | --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug | |
431 | tech => inferred, |
|
431 | --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug | |
432 | data_size => 6*16, |
|
432 | ||
433 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
433 | ||
434 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
|
434 | ----------------------------------------------------------------------------- | |
435 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
435 | lpp_waveform_1 : lpp_waveform | |
436 | delta_vector_size => delta_vector_size, |
|
436 | GENERIC MAP ( | |
437 | delta_vector_size_f0_2 => delta_vector_size_f0_2 |
|
437 | tech => inferred, | |
438 | ) |
|
438 | data_size => 6*16, | |
439 | PORT MAP ( |
|
439 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |
440 | clk => clk, |
|
440 | nb_word_by_buffer_size => nb_word_by_buffer_size, | |
441 | rstn => rstn, |
|
441 | nb_snapshot_param_size => nb_snapshot_param_size, | |
442 |
|
442 | delta_vector_size => delta_vector_size, | ||
443 | reg_run => run, |
|
443 | delta_vector_size_f0_2 => delta_vector_size_f0_2 | |
444 | reg_start_date => start_date, |
|
444 | ) | |
445 | reg_delta_snapshot => delta_snapshot, |
|
445 | PORT MAP ( | |
446 | reg_delta_f0 => delta_f0, |
|
446 | clk => clk, | |
447 | reg_delta_f0_2 => delta_f0_2, |
|
447 | rstn => rstn, | |
448 | reg_delta_f1 => delta_f1, |
|
448 | ||
449 |
reg_ |
|
449 | reg_run => run, | |
450 |
|
450 | reg_start_date => start_date, | ||
451 | enable_f0 => enable_f0, |
|
451 | reg_delta_snapshot => delta_snapshot, | |
452 | enable_f1 => enable_f1, |
|
452 | reg_delta_f0 => delta_f0, | |
453 |
|
|
453 | reg_delta_f0_2 => delta_f0_2, | |
454 | enable_f3 => enable_f3, |
|
454 | reg_delta_f1 => delta_f1, | |
455 | burst_f0 => burst_f0, |
|
455 | reg_delta_f2 => delta_f2, | |
456 | burst_f1 => burst_f1, |
|
456 | ||
457 | burst_f2 => burst_f2, |
|
457 | enable_f0 => enable_f0, | |
458 |
|
458 | enable_f1 => enable_f1, | ||
459 | nb_data_by_buffer => nb_data_by_buffer, |
|
459 | enable_f2 => enable_f2, | |
460 | nb_word_by_buffer => nb_word_by_buffer, |
|
460 | enable_f3 => enable_f3, | |
461 | nb_snapshot_param => nb_snapshot_param, |
|
461 | burst_f0 => burst_f0, | |
462 | status_full => status_full, |
|
462 | burst_f1 => burst_f1, | |
463 | status_full_ack => status_full_ack, |
|
463 | burst_f2 => burst_f2, | |
464 | status_full_err => status_full_err, |
|
464 | ||
465 | status_new_err => status_new_err, |
|
465 | nb_data_by_buffer => nb_data_by_buffer, | |
466 |
|
466 | nb_word_by_buffer => nb_word_by_buffer, | ||
467 | coarse_time => coarse_time, |
|
467 | nb_snapshot_param => nb_snapshot_param, | |
468 | fine_time => fine_time, |
|
468 | status_full => status_full, | |
469 |
|
469 | status_full_ack => status_full_ack, | ||
470 | --f0 |
|
470 | status_full_err => status_full_err, | |
471 | addr_data_f0 => addr_data_f0, |
|
471 | status_new_err => status_new_err, | |
472 | data_f0_in_valid => sample_f0_val, |
|
472 | ||
473 | data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug |
|
473 | coarse_time => coarse_time, | |
474 | --f1 |
|
474 | fine_time => fine_time, | |
475 | addr_data_f1 => addr_data_f1, |
|
475 | ||
476 | data_f1_in_valid => sample_f1_val, |
|
476 | --f0 | |
477 | data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug, |
|
477 | addr_data_f0 => addr_data_f0, | |
478 | --f2 |
|
478 | data_f0_in_valid => sample_f0_val, | |
479 | addr_data_f2 => addr_data_f2, |
|
479 | data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug | |
480 | data_f2_in_valid => sample_f2_val, |
|
480 | --f1 | |
481 | data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug, |
|
481 | addr_data_f1 => addr_data_f1, | |
482 | --f3 |
|
482 | data_f1_in_valid => sample_f1_val, | |
483 | addr_data_f3 => addr_data_f3, |
|
483 | data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug, | |
484 | data_f3_in_valid => sample_f3_val, |
|
484 | --f2 | |
485 | data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug, |
|
485 | addr_data_f2 => addr_data_f2, | |
486 | -- OUTPUT -- DMA interface |
|
486 | data_f2_in_valid => sample_f2_val, | |
487 | --f0 |
|
487 | data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug, | |
488 | data_f0_addr_out => data_f0_addr_out_s, |
|
488 | --f3 | |
489 |
|
|
489 | addr_data_f3 => addr_data_f3, | |
490 |
data_f |
|
490 | data_f3_in_valid => sample_f3_val, | |
491 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s, |
|
491 | data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug, | |
492 | data_f0_data_out_ren => data_f0_data_out_ren, |
|
492 | -- OUTPUT -- DMA interface | |
493 |
--f |
|
493 | --f0 | |
494 |
data_f |
|
494 | data_f0_addr_out => data_f0_addr_out_s, | |
495 |
data_f |
|
495 | data_f0_data_out => data_f0_data_out, | |
496 |
data_f |
|
496 | data_f0_data_out_valid => data_f0_data_out_valid_s, | |
497 |
data_f |
|
497 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s, | |
498 |
data_f |
|
498 | data_f0_data_out_ren => data_f0_data_out_ren, | |
499 |
--f |
|
499 | --f1 | |
500 |
data_f |
|
500 | data_f1_addr_out => data_f1_addr_out_s, | |
501 |
data_f |
|
501 | data_f1_data_out => data_f1_data_out, | |
502 |
data_f |
|
502 | data_f1_data_out_valid => data_f1_data_out_valid_s, | |
503 |
data_f |
|
503 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s, | |
504 |
data_f |
|
504 | data_f1_data_out_ren => data_f1_data_out_ren, | |
505 |
--f |
|
505 | --f2 | |
506 |
data_f |
|
506 | data_f2_addr_out => data_f2_addr_out_s, | |
507 |
data_f |
|
507 | data_f2_data_out => data_f2_data_out, | |
508 |
data_f |
|
508 | data_f2_data_out_valid => data_f2_data_out_valid_s, | |
509 |
data_f |
|
509 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s, | |
510 |
data_f |
|
510 | data_f2_data_out_ren => data_f2_data_out_ren, | |
511 |
|
511 | --f3 | ||
512 | ------------------------------------------------------------------------- |
|
512 | data_f3_addr_out => data_f3_addr_out_s, | |
513 | observation_reg => OPEN |
|
513 | data_f3_data_out => data_f3_data_out, | |
514 |
|
514 | data_f3_data_out_valid => data_f3_data_out_valid_s, | ||
515 | ); |
|
515 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, | |
516 |
|
516 | data_f3_data_out_ren => data_f3_data_out_ren , | ||
517 |
|
517 | |||
518 |
|
|
518 | ------------------------------------------------------------------------- | |
519 | -- TEMP |
|
519 | observation_reg => OPEN | |
520 | ----------------------------------------------------------------------------- |
|
520 | ||
521 |
|
521 | ); | ||
522 | PROCESS (clk, rstn) |
|
522 | ||
523 | BEGIN -- PROCESS |
|
523 | ||
524 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
524 | ----------------------------------------------------------------------------- | |
525 | data_f0_data_out_valid <= '0'; |
|
525 | -- TEMP | |
526 | data_f0_data_out_valid_burst <= '0'; |
|
526 | ----------------------------------------------------------------------------- | |
527 | data_f1_data_out_valid <= '0'; |
|
527 | ||
528 | data_f1_data_out_valid_burst <= '0'; |
|
528 | PROCESS (clk, rstn) | |
529 | data_f2_data_out_valid <= '0'; |
|
529 | BEGIN -- PROCESS | |
530 | data_f2_data_out_valid_burst <= '0'; |
|
530 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
531 |
data_f |
|
531 | data_f0_data_out_valid <= '0'; | |
532 |
data_f |
|
532 | data_f0_data_out_valid_burst <= '0'; | |
533 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
533 | data_f1_data_out_valid <= '0'; | |
534 | data_f0_data_out_valid <= data_f0_data_out_valid_s; |
|
534 | data_f1_data_out_valid_burst <= '0'; | |
535 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; |
|
535 | data_f2_data_out_valid <= '0'; | |
536 | data_f1_data_out_valid <= data_f1_data_out_valid_s; |
|
536 | data_f2_data_out_valid_burst <= '0'; | |
537 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; |
|
537 | data_f3_data_out_valid <= '0'; | |
538 | data_f2_data_out_valid <= data_f2_data_out_valid_s; |
|
538 | data_f3_data_out_valid_burst <= '0'; | |
539 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; |
|
539 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
540 |
data_f |
|
540 | data_f0_data_out_valid <= data_f0_data_out_valid_s; | |
541 |
data_f |
|
541 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; | |
542 | END IF; |
|
542 | data_f1_data_out_valid <= data_f1_data_out_valid_s; | |
543 | END PROCESS; |
|
543 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; | |
544 |
|
544 | data_f2_data_out_valid <= data_f2_data_out_valid_s; | ||
545 |
data_f |
|
545 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; | |
546 |
data_f |
|
546 | data_f3_data_out_valid <= data_f3_data_out_valid_s; | |
547 |
data_f |
|
547 | data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; | |
548 | data_f3_addr_out <= data_f3_addr_out_s; |
|
548 | END IF; | |
549 |
|
549 | END PROCESS; | ||
550 | ----------------------------------------------------------------------------- |
|
550 | ||
551 | -- RoundRobin Selection For DMA |
|
551 | data_f0_addr_out <= data_f0_addr_out_s; | |
552 | ----------------------------------------------------------------------------- |
|
552 | data_f1_addr_out <= data_f1_addr_out_s; | |
553 |
|
553 | data_f2_addr_out <= data_f2_addr_out_s; | ||
554 | dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; |
|
554 | data_f3_addr_out <= data_f3_addr_out_s; | |
555 | dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; |
|
555 | ||
556 | dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; |
|
556 | ----------------------------------------------------------------------------- | |
557 | dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; |
|
557 | -- RoundRobin Selection For DMA | |
558 |
|
558 | ----------------------------------------------------------------------------- | ||
559 | RR_Arbiter_4_1 : RR_Arbiter_4 |
|
559 | ||
560 | PORT MAP ( |
|
560 | dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; | |
561 | clk => clk, |
|
561 | dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; | |
562 | rstn => rstn, |
|
562 | dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; | |
563 | in_valid => dma_rr_valid, |
|
563 | dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; | |
564 | out_grant => dma_rr_grant_s); |
|
564 | ||
565 |
|
565 | RR_Arbiter_4_1 : RR_Arbiter_4 | ||
566 | dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst; |
|
566 | PORT MAP ( | |
567 | dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; |
|
567 | clk => clk, | |
568 | dma_rr_valid_ms(2) <= '0'; |
|
568 | rstn => rstn, | |
569 | dma_rr_valid_ms(3) <= '0'; |
|
569 | in_valid => dma_rr_valid, | |
570 |
|
570 | out_grant => dma_rr_grant_s); | ||
571 | RR_Arbiter_4_2 : RR_Arbiter_4 |
|
571 | ||
572 | PORT MAP ( |
|
572 | dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst; | |
573 | clk => clk, |
|
573 | dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; | |
574 | rstn => rstn, |
|
574 | dma_rr_valid_ms(2) <= '0'; | |
575 | in_valid => dma_rr_valid_ms, |
|
575 | dma_rr_valid_ms(3) <= '0'; | |
576 | out_grant => dma_rr_grant_ms); |
|
576 | ||
577 |
|
577 | RR_Arbiter_4_2 : RR_Arbiter_4 | ||
578 | dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; |
|
578 | PORT MAP ( | |
579 |
|
579 | clk => clk, | ||
580 |
|
580 | rstn => rstn, | ||
581 | ----------------------------------------------------------------------------- |
|
581 | in_valid => dma_rr_valid_ms, | |
582 | -- in : dma_rr_grant |
|
582 | out_grant => dma_rr_grant_ms); | |
583 | -- send |
|
583 | ||
584 | -- out : dma_sel |
|
584 | dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; | |
585 | -- dma_valid_burst |
|
585 | ||
586 | -- dma_sel_valid |
|
586 | ||
587 | ----------------------------------------------------------------------------- |
|
587 | ----------------------------------------------------------------------------- | |
588 | PROCESS (clk, rstn) |
|
588 | -- in : dma_rr_grant | |
589 | BEGIN -- PROCESS |
|
589 | -- send | |
590 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
590 | -- out : dma_sel | |
591 | dma_sel <= (OTHERS => '0'); |
|
591 | -- dma_valid_burst | |
592 | dma_send <= '0'; |
|
592 | -- dma_sel_valid | |
593 | dma_valid_burst <= '0'; |
|
593 | ----------------------------------------------------------------------------- | |
594 | data_ms_done <= '0'; |
|
594 | PROCESS (clk, rstn) | |
595 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
595 | BEGIN -- PROCESS | |
596 | IF run = '1' THEN |
|
596 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
597 | data_ms_done <= '0'; |
|
597 | dma_sel <= (OTHERS => '0'); | |
598 | IF dma_sel = "00000" OR dma_done = '1' THEN |
|
598 | dma_send <= '0'; | |
599 | dma_sel <= dma_rr_grant; |
|
599 | dma_valid_burst <= '0'; | |
600 | IF dma_rr_grant(0) = '1' THEN |
|
600 | data_ms_done <= '0'; | |
601 | dma_send <= '1'; |
|
601 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
602 | dma_valid_burst <= data_f0_data_out_valid_burst; |
|
602 | IF run = '1' THEN | |
603 | dma_sel_valid <= data_f0_data_out_valid; |
|
603 | data_ms_done <= '0'; | |
604 |
|
|
604 | IF dma_sel = "00000" OR dma_done = '1' THEN | |
605 |
|
|
605 | dma_sel <= dma_rr_grant; | |
606 | dma_valid_burst <= data_f1_data_out_valid_burst; |
|
606 | IF dma_rr_grant(0) = '1' THEN | |
607 |
dma_se |
|
607 | dma_send <= '1'; | |
608 | ELSIF dma_rr_grant(2) = '1' THEN |
|
608 | dma_valid_burst <= data_f0_data_out_valid_burst; | |
609 | dma_send <= '1'; |
|
609 | dma_sel_valid <= data_f0_data_out_valid; | |
610 | dma_valid_burst <= data_f2_data_out_valid_burst; |
|
610 | ELSIF dma_rr_grant(1) = '1' THEN | |
611 | dma_sel_valid <= data_f2_data_out_valid; |
|
611 | dma_send <= '1'; | |
612 | ELSIF dma_rr_grant(3) = '1' THEN |
|
612 | dma_valid_burst <= data_f1_data_out_valid_burst; | |
613 |
dma_se |
|
613 | dma_sel_valid <= data_f1_data_out_valid; | |
614 | dma_valid_burst <= data_f3_data_out_valid_burst; |
|
614 | ELSIF dma_rr_grant(2) = '1' THEN | |
615 | dma_sel_valid <= data_f3_data_out_valid; |
|
615 | dma_send <= '1'; | |
616 | ELSIF dma_rr_grant(4) = '1' THEN |
|
616 | dma_valid_burst <= data_f2_data_out_valid_burst; | |
617 | dma_send <= '1'; |
|
617 | dma_sel_valid <= data_f2_data_out_valid; | |
618 | dma_valid_burst <= data_ms_valid_burst; |
|
618 | ELSIF dma_rr_grant(3) = '1' THEN | |
619 |
dma_se |
|
619 | dma_send <= '1'; | |
620 | END IF; |
|
620 | dma_valid_burst <= data_f3_data_out_valid_burst; | |
621 |
|
621 | dma_sel_valid <= data_f3_data_out_valid; | ||
622 |
IF dma_ |
|
622 | ELSIF dma_rr_grant(4) = '1' THEN | |
623 |
d |
|
623 | dma_send <= '1'; | |
624 | END IF; |
|
624 | dma_valid_burst <= data_ms_valid_burst; | |
625 | ELSE |
|
625 | dma_sel_valid <= data_ms_valid; | |
626 | dma_sel <= dma_sel; |
|
626 | END IF; | |
627 | dma_send <= '0'; |
|
627 | ||
628 | END IF; |
|
628 | IF dma_sel(4) = '1' THEN | |
629 | ELSE |
|
629 | data_ms_done <= '1'; | |
630 | data_ms_done <= '0'; |
|
630 | END IF; | |
631 | dma_sel <= (OTHERS => '0'); |
|
631 | ELSE | |
632 |
dma_se |
|
632 | dma_sel <= dma_sel; | |
633 |
|
|
633 | dma_send <= '0'; | |
634 | END IF; |
|
634 | END IF; | |
635 | END IF; |
|
635 | ELSE | |
636 | END PROCESS; |
|
636 | data_ms_done <= '0'; | |
637 |
|
637 | dma_sel <= (OTHERS => '0'); | ||
638 |
|
638 | dma_send <= '0'; | ||
639 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE |
|
639 | dma_valid_burst <= '0'; | |
640 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE |
|
640 | END IF; | |
641 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE |
|
641 | END IF; | |
642 | data_f3_addr_out WHEN dma_sel(3) = '1' ELSE |
|
642 | END PROCESS; | |
643 | data_ms_addr; |
|
643 | ||
644 |
|
644 | |||
645 |
dma_ |
|
645 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE | |
646 |
data_f1_ |
|
646 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE | |
647 |
data_f2_ |
|
647 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE | |
648 |
data_f3_ |
|
648 | data_f3_addr_out WHEN dma_sel(3) = '1' ELSE | |
649 |
data_ms_ |
|
649 | data_ms_addr; | |
650 |
|
650 | |||
651 |
d |
|
651 | dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE | |
652 |
data_f1_data_out |
|
652 | data_f1_data_out WHEN dma_sel(1) = '1' ELSE | |
653 |
data_f2_data_out |
|
653 | data_f2_data_out WHEN dma_sel(2) = '1' ELSE | |
654 |
data_f3_data_out |
|
654 | data_f3_data_out WHEN dma_sel(3) = '1' ELSE | |
655 | data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1'; |
|
655 | data_ms_data; | |
656 |
|
656 | |||
657 | dma_data_2 <= dma_data; |
|
657 | data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; | |
658 |
|
658 | data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; | ||
659 |
|
659 | data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; | ||
660 |
|
660 | data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; | ||
661 |
|
661 | data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1'; | ||
662 |
|
662 | |||
663 | ----------------------------------------------------------------------------- |
|
663 | dma_data_2 <= dma_data; | |
664 | -- DEBUG -- DMA IN |
|
664 | ||
665 | --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; |
|
665 | ||
666 | --debug_f0_data_dma_in <= dma_data; |
|
666 | ||
667 | --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; |
|
667 | ||
668 | --debug_f1_data_dma_in <= dma_data; |
|
668 | ||
669 | --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren; |
|
669 | ----------------------------------------------------------------------------- | |
670 | --debug_f2_data_dma_in <= dma_data; |
|
670 | -- DEBUG -- DMA IN | |
671 |
--debug_f |
|
671 | --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; | |
672 |
--debug_f |
|
672 | --debug_f0_data_dma_in <= dma_data; | |
673 | ----------------------------------------------------------------------------- |
|
673 | --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; | |
674 |
|
674 | --debug_f1_data_dma_in <= dma_data; | ||
675 | ----------------------------------------------------------------------------- |
|
675 | --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren; | |
676 | -- DMA |
|
676 | --debug_f2_data_dma_in <= dma_data; | |
677 | ----------------------------------------------------------------------------- |
|
677 | --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren; | |
678 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst |
|
678 | --debug_f3_data_dma_in <= dma_data; | |
679 | GENERIC MAP ( |
|
679 | ----------------------------------------------------------------------------- | |
680 | tech => inferred, |
|
680 | ||
681 | hindex => hindex) |
|
681 | ----------------------------------------------------------------------------- | |
682 | PORT MAP ( |
|
682 | -- DMA | |
683 | HCLK => clk, |
|
683 | ----------------------------------------------------------------------------- | |
684 | HRESETn => rstn, |
|
684 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst | |
685 | run => run, |
|
685 | GENERIC MAP ( | |
686 | AHB_Master_In => ahbi, |
|
686 | tech => inferred, | |
687 | AHB_Master_Out => ahbo, |
|
687 | hindex => hindex) | |
688 |
|
688 | PORT MAP ( | ||
689 |
|
|
689 | HCLK => clk, | |
690 | valid_burst => dma_valid_burst, |
|
690 | HRESETn => rstn, | |
691 |
|
|
691 | run => run, | |
692 | ren => dma_ren, |
|
692 | AHB_Master_In => ahbi, | |
693 | address => dma_address, |
|
693 | AHB_Master_Out => ahbo, | |
694 | data => dma_data_2); |
|
694 | ||
695 |
|
695 | send => dma_send, | ||
696 | ----------------------------------------------------------------------------- |
|
696 | valid_burst => dma_valid_burst, | |
697 | -- Matrix Spectral |
|
697 | done => dma_done, | |
698 | ----------------------------------------------------------------------------- |
|
698 | ren => dma_ren, | |
699 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & |
|
699 | address => dma_address, | |
700 | NOT(sample_f0_val) & NOT(sample_f0_val); |
|
700 | data => dma_data_2); | |
701 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & |
|
701 | ||
702 | NOT(sample_f1_val) & NOT(sample_f1_val); |
|
702 | ----------------------------------------------------------------------------- | |
703 | sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & |
|
703 | -- Matrix Spectral | |
704 | NOT(sample_f3_val) & NOT(sample_f3_val); |
|
704 | ----------------------------------------------------------------------------- | |
705 |
|
705 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & | ||
706 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) |
|
706 | NOT(sample_f0_val) & NOT(sample_f0_val); | |
707 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); |
|
707 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & | |
708 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); |
|
708 | NOT(sample_f1_val) & NOT(sample_f1_val); | |
709 |
|
709 | sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & | ||
710 | ------------------------------------------------------------------------------- |
|
710 | NOT(sample_f3_val) & NOT(sample_f3_val); | |
711 |
|
711 | |||
712 | ms_softandhard_rstn <= rstn AND run_ms AND run; |
|
712 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) | |
713 |
|
713 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); | ||
714 | ----------------------------------------------------------------------------- |
|
714 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); | |
715 | lpp_lfr_ms_1 : lpp_lfr_ms |
|
715 | ||
716 | GENERIC MAP ( |
|
716 | ------------------------------------------------------------------------------- | |
717 | Mem_use => Mem_use) |
|
717 | ||
718 | PORT MAP ( |
|
718 | ms_softandhard_rstn <= rstn AND run_ms AND run; | |
719 | clk => clk, |
|
719 | ||
720 | rstn => ms_softandhard_rstn, --rstn, |
|
720 | ----------------------------------------------------------------------------- | |
721 |
|
721 | lpp_lfr_ms_1 : lpp_lfr_ms | ||
722 | coarse_time => coarse_time, |
|
722 | GENERIC MAP ( | |
723 | fine_time => fine_time, |
|
723 | Mem_use => Mem_use) | |
724 |
|
724 | PORT MAP ( | ||
725 | sample_f0_wen => sample_f0_wen, |
|
725 | clk => clk, | |
726 | sample_f0_wdata => sample_f0_wdata, |
|
726 | rstn => ms_softandhard_rstn, --rstn, | |
727 | sample_f1_wen => sample_f1_wen, |
|
727 | ||
728 | sample_f1_wdata => sample_f1_wdata, |
|
728 | coarse_time => coarse_time, | |
729 | sample_f2_wen => sample_f3_wen, -- TODO verify that it's the good data |
|
729 | fine_time => fine_time, | |
730 | sample_f2_wdata => sample_f3_wdata,-- TODO verify that it's the good data |
|
730 | ||
731 |
|
731 | sample_f0_wen => sample_f0_wen, | ||
732 | dma_addr => data_ms_addr, -- |
|
732 | sample_f0_wdata => sample_f0_wdata, | |
733 | dma_data => data_ms_data, -- |
|
733 | sample_f1_wen => sample_f1_wen, | |
734 | dma_valid => data_ms_valid, -- |
|
734 | sample_f1_wdata => sample_f1_wdata, | |
735 | dma_valid_burst => data_ms_valid_burst, -- |
|
735 | sample_f2_wen => sample_f3_wen, -- TODO verify that it's the good data | |
736 | dma_ren => data_ms_ren, -- |
|
736 | sample_f2_wdata => sample_f3_wdata,-- TODO verify that it's the good data | |
737 | dma_done => data_ms_done, -- |
|
737 | ||
738 |
|
738 | dma_addr => data_ms_addr, -- | ||
739 | ready_matrix_f0 => ready_matrix_f0_0,-- TODO rename |
|
739 | dma_data => data_ms_data, -- | |
740 | ready_matrix_f1 => ready_matrix_f1, |
|
740 | dma_valid => data_ms_valid, -- | |
741 | ready_matrix_f2 => ready_matrix_f2, |
|
741 | dma_valid_burst => data_ms_valid_burst, -- | |
742 | --error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
742 | dma_ren => data_ms_ren, -- | |
743 | error_bad_component_error => error_bad_component_error, |
|
743 | dma_done => data_ms_done, -- | |
744 | error_buffer_full => OPEN, -- TODO |
|
744 | ||
745 | error_input_fifo_write => OPEN, -- TODO |
|
745 | ready_matrix_f0 => ready_matrix_f0_0,-- TODO rename | |
746 |
|
|
746 | ready_matrix_f1 => ready_matrix_f1, | |
747 |
|
|
747 | ready_matrix_f2 => ready_matrix_f2, | |
748 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
748 | --error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
749 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
749 | error_bad_component_error => error_bad_component_error, | |
750 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,-- TODO |
|
750 | error_buffer_full => error_buffer_full, -- TODO | |
751 | -- status_error_bad_component_error => status_error_bad_component_error,-- TODO |
|
751 | error_input_fifo_write => error_input_fifo_write, -- TODO | |
752 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
752 | ||
753 | config_active_interruption_onError => config_active_interruption_onError, |
|
753 | debug_reg => observation_reg, | |
754 | addr_matrix_f0 => addr_matrix_f0_0,-- TODO rename |
|
754 | ||
755 |
|
|
755 | status_ready_matrix_f0 => status_ready_matrix_f0_0,-- TODO rename | |
756 |
|
|
756 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
757 |
|
757 | status_ready_matrix_f2 => status_ready_matrix_f2, | ||
758 | matrix_time_f0 => matrix_time_f0_0,-- TODO rename |
|
758 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,-- TODO | |
759 | matrix_time_f1 => matrix_time_f1, |
|
759 | -- status_error_bad_component_error => status_error_bad_component_error,-- TODO | |
760 | matrix_time_f2 => matrix_time_f2); |
|
760 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
761 |
|
761 | config_active_interruption_onError => config_active_interruption_onError, | ||
762 | END beh; |
|
762 | addr_matrix_f0 => addr_matrix_f0_0,-- TODO rename | |
|
763 | addr_matrix_f1 => addr_matrix_f1, | |||
|
764 | addr_matrix_f2 => addr_matrix_f2, | |||
|
765 | ||||
|
766 | matrix_time_f0 => matrix_time_f0_0,-- TODO rename | |||
|
767 | matrix_time_f1 => matrix_time_f1, | |||
|
768 | matrix_time_f2 => matrix_time_f2); | |||
|
769 | ||||
|
770 | END beh; No newline at end of file |
@@ -1,544 +1,569 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | -- jean-christophe.pellion@easii-ic.com |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
22 | ---------------------------------------------------------------------------- |
|
22 | ---------------------------------------------------------------------------- | |
23 | LIBRARY ieee; |
|
23 | LIBRARY ieee; | |
24 | USE ieee.std_logic_1164.ALL; |
|
24 | USE ieee.std_logic_1164.ALL; | |
25 | USE ieee.numeric_std.ALL; |
|
25 | USE ieee.numeric_std.ALL; | |
26 | LIBRARY grlib; |
|
26 | LIBRARY grlib; | |
27 | USE grlib.amba.ALL; |
|
27 | USE grlib.amba.ALL; | |
28 | USE grlib.stdlib.ALL; |
|
28 | USE grlib.stdlib.ALL; | |
29 | USE grlib.devices.ALL; |
|
29 | USE grlib.devices.ALL; | |
30 | LIBRARY lpp; |
|
30 | LIBRARY lpp; | |
31 | USE lpp.lpp_amba.ALL; |
|
31 | USE lpp.lpp_amba.ALL; | |
32 | USE lpp.apb_devices_list.ALL; |
|
32 | USE lpp.apb_devices_list.ALL; | |
33 | USE lpp.lpp_memory.ALL; |
|
33 | USE lpp.lpp_memory.ALL; | |
34 | LIBRARY techmap; |
|
34 | LIBRARY techmap; | |
35 | USE techmap.gencomp.ALL; |
|
35 | USE techmap.gencomp.ALL; | |
36 |
|
36 | |||
37 | ENTITY lpp_lfr_apbreg IS |
|
37 | ENTITY lpp_lfr_apbreg IS | |
38 | GENERIC ( |
|
38 | GENERIC ( | |
39 | nb_data_by_buffer_size : INTEGER := 11; |
|
39 | nb_data_by_buffer_size : INTEGER := 11; | |
40 | nb_word_by_buffer_size : INTEGER := 11; |
|
40 | nb_word_by_buffer_size : INTEGER := 11; | |
41 | nb_snapshot_param_size : INTEGER := 11; |
|
41 | nb_snapshot_param_size : INTEGER := 11; | |
42 | delta_vector_size : INTEGER := 20; |
|
42 | delta_vector_size : INTEGER := 20; | |
43 | delta_vector_size_f0_2 : INTEGER := 3; |
|
43 | delta_vector_size_f0_2 : INTEGER := 3; | |
44 |
|
44 | |||
45 | pindex : INTEGER := 4; |
|
45 | pindex : INTEGER := 4; | |
46 | paddr : INTEGER := 4; |
|
46 | paddr : INTEGER := 4; | |
47 | pmask : INTEGER := 16#fff#; |
|
47 | pmask : INTEGER := 16#fff#; | |
48 | pirq_ms : INTEGER := 0; |
|
48 | pirq_ms : INTEGER := 0; | |
49 | pirq_wfp : INTEGER := 1; |
|
49 | pirq_wfp : INTEGER := 1; | |
50 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000"); |
|
50 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000"); | |
51 | PORT ( |
|
51 | PORT ( | |
52 | -- AMBA AHB system signals |
|
52 | -- AMBA AHB system signals | |
53 | HCLK : IN STD_ULOGIC; |
|
53 | HCLK : IN STD_ULOGIC; | |
54 | HRESETn : IN STD_ULOGIC; |
|
54 | HRESETn : IN STD_ULOGIC; | |
55 |
|
55 | |||
56 | -- AMBA APB Slave Interface |
|
56 | -- AMBA APB Slave Interface | |
57 | apbi : IN apb_slv_in_type; |
|
57 | apbi : IN apb_slv_in_type; | |
58 | apbo : OUT apb_slv_out_type; |
|
58 | apbo : OUT apb_slv_out_type; | |
59 |
|
59 | |||
60 | --------------------------------------------------------------------------- |
|
60 | --------------------------------------------------------------------------- | |
61 | -- Spectral Matrix Reg |
|
61 | -- Spectral Matrix Reg | |
62 | run_ms : OUT STD_LOGIC; |
|
62 | run_ms : OUT STD_LOGIC; | |
63 | -- IN |
|
63 | -- IN | |
64 | ready_matrix_f0_0 : IN STD_LOGIC; |
|
64 | ready_matrix_f0_0 : IN STD_LOGIC; | |
65 | ready_matrix_f0_1 : IN STD_LOGIC; |
|
|||
66 | ready_matrix_f1 : IN STD_LOGIC; |
|
65 | ready_matrix_f1 : IN STD_LOGIC; | |
67 | ready_matrix_f2 : IN STD_LOGIC; |
|
66 | ready_matrix_f2 : IN STD_LOGIC; | |
68 | error_anticipating_empty_fifo : IN STD_LOGIC; |
|
67 | ||
69 | error_bad_component_error : IN STD_LOGIC; |
|
68 | error_bad_component_error : IN STD_LOGIC; | |
|
69 | error_buffer_full : in STD_LOGIC; -- TODO | |||
|
70 | error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO | |||
|
71 | ||||
70 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
72 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
71 |
|
73 | |||
72 | -- OUT |
|
74 | -- OUT | |
73 | status_ready_matrix_f0_0 : OUT STD_LOGIC; |
|
75 | status_ready_matrix_f0_0 : OUT STD_LOGIC; | |
74 | status_ready_matrix_f0_1 : OUT STD_LOGIC; |
|
|||
75 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
76 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
76 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
77 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
77 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
|||
78 | status_error_bad_component_error : OUT STD_LOGIC; |
|
|||
79 |
|
78 | |||
80 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
79 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
81 | config_active_interruption_onError : OUT STD_LOGIC; |
|
80 | config_active_interruption_onError : OUT STD_LOGIC; | |
82 |
|
81 | |||
83 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
82 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
84 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
83 | -- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
85 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
84 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
86 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
85 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
87 |
|
86 | |||
88 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
87 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
89 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
88 | -- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
90 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
89 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
91 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
90 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
92 |
|
91 | |||
93 | --------------------------------------------------------------------------- |
|
92 | --------------------------------------------------------------------------- | |
94 | --------------------------------------------------------------------------- |
|
93 | --------------------------------------------------------------------------- | |
95 | -- WaveForm picker Reg |
|
94 | -- WaveForm picker Reg | |
96 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
95 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
97 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
96 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
98 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
97 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
99 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
98 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
100 |
|
99 | |||
101 | -- OUT |
|
100 | -- OUT | |
102 | data_shaping_BW : OUT STD_LOGIC; |
|
101 | data_shaping_BW : OUT STD_LOGIC; | |
103 | data_shaping_SP0 : OUT STD_LOGIC; |
|
102 | data_shaping_SP0 : OUT STD_LOGIC; | |
104 | data_shaping_SP1 : OUT STD_LOGIC; |
|
103 | data_shaping_SP1 : OUT STD_LOGIC; | |
105 | data_shaping_R0 : OUT STD_LOGIC; |
|
104 | data_shaping_R0 : OUT STD_LOGIC; | |
106 | data_shaping_R1 : OUT STD_LOGIC; |
|
105 | data_shaping_R1 : OUT STD_LOGIC; | |
107 |
|
106 | |||
108 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
107 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
109 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
108 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
110 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
109 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
111 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
110 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
112 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
111 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
113 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
112 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
114 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
113 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
115 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
114 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
116 |
|
115 | |||
117 | enable_f0 : OUT STD_LOGIC; |
|
116 | enable_f0 : OUT STD_LOGIC; | |
118 | enable_f1 : OUT STD_LOGIC; |
|
117 | enable_f1 : OUT STD_LOGIC; | |
119 | enable_f2 : OUT STD_LOGIC; |
|
118 | enable_f2 : OUT STD_LOGIC; | |
120 | enable_f3 : OUT STD_LOGIC; |
|
119 | enable_f3 : OUT STD_LOGIC; | |
121 |
|
120 | |||
122 | burst_f0 : OUT STD_LOGIC; |
|
121 | burst_f0 : OUT STD_LOGIC; | |
123 | burst_f1 : OUT STD_LOGIC; |
|
122 | burst_f1 : OUT STD_LOGIC; | |
124 | burst_f2 : OUT STD_LOGIC; |
|
123 | burst_f2 : OUT STD_LOGIC; | |
125 |
|
124 | |||
126 | run : OUT STD_LOGIC; |
|
125 | run : OUT STD_LOGIC; | |
127 |
|
126 | |||
128 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
127 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
129 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
128 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
130 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
129 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
131 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
130 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
132 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
131 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); | |
133 | --------------------------------------------------------------------------- |
|
132 | --------------------------------------------------------------------------- | |
134 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
133 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
135 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
134 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
136 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
135 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
137 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
136 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
138 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
137 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
139 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
138 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
140 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
139 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
141 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
140 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
142 |
|
141 | |||
143 | --------------------------------------------------------------------------- |
|
142 | --------------------------------------------------------------------------- | |
144 | ); |
|
143 | ); | |
145 |
|
144 | |||
146 | END lpp_lfr_apbreg; |
|
145 | END lpp_lfr_apbreg; | |
147 |
|
146 | |||
148 | ARCHITECTURE beh OF lpp_lfr_apbreg IS |
|
147 | ARCHITECTURE beh OF lpp_lfr_apbreg IS | |
149 |
|
148 | |||
150 | CONSTANT REVISION : INTEGER := 1; |
|
149 | CONSTANT REVISION : INTEGER := 1; | |
151 |
|
150 | |||
152 | CONSTANT pconfig : apb_config_type := ( |
|
151 | CONSTANT pconfig : apb_config_type := ( | |
153 | 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp), |
|
152 | 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp), | |
154 | 1 => apb_iobar(paddr, pmask)); |
|
153 | 1 => apb_iobar(paddr, pmask)); | |
155 |
|
154 | |||
156 | TYPE lpp_SpectralMatrix_regs IS RECORD |
|
155 | TYPE lpp_SpectralMatrix_regs IS RECORD | |
157 | config_active_interruption_onNewMatrix : STD_LOGIC; |
|
156 | config_active_interruption_onNewMatrix : STD_LOGIC; | |
158 | config_active_interruption_onError : STD_LOGIC; |
|
157 | config_active_interruption_onError : STD_LOGIC; | |
159 | config_ms_run : STD_LOGIC; |
|
158 | config_ms_run : STD_LOGIC; | |
160 | status_ready_matrix_f0_0 : STD_LOGIC; |
|
159 | status_ready_matrix_f0_0 : STD_LOGIC; | |
161 | status_ready_matrix_f0_1 : STD_LOGIC; |
|
160 | -- status_ready_matrix_f0_1 : STD_LOGIC; | |
162 | status_ready_matrix_f1 : STD_LOGIC; |
|
161 | status_ready_matrix_f1 : STD_LOGIC; | |
163 | status_ready_matrix_f2 : STD_LOGIC; |
|
162 | status_ready_matrix_f2 : STD_LOGIC; | |
164 | status_error_anticipating_empty_fifo : STD_LOGIC; |
|
163 | -- status_error_anticipating_empty_fifo : STD_LOGIC; | |
165 | status_error_bad_component_error : STD_LOGIC; |
|
164 | status_error_bad_component_error : STD_LOGIC; | |
|
165 | status_error_buffer_full : STD_LOGIC; -- TODO | |||
|
166 | status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO | |||
166 | addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
167 | addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
167 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
168 | -- addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
168 | addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
169 | addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
169 | addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
170 | addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
170 |
|
171 | |||
171 | coarse_time_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
172 | coarse_time_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
172 | coarse_time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
173 | -- coarse_time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
173 | coarse_time_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
174 | coarse_time_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
174 | coarse_time_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
175 | coarse_time_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
175 |
|
176 | |||
176 | -- fine_time_f0_0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
177 | -- fine_time_f0_0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
177 | -- fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
178 | -- fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
178 | -- fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
179 | -- fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
179 | -- fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
180 | -- fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
180 | END RECORD; |
|
181 | END RECORD; | |
181 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; |
|
182 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; | |
182 |
|
183 | |||
183 | TYPE lpp_WaveformPicker_regs IS RECORD |
|
184 | TYPE lpp_WaveformPicker_regs IS RECORD | |
184 | status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
185 | status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
185 | status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
186 | status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
186 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
187 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
187 | data_shaping_BW : STD_LOGIC; |
|
188 | data_shaping_BW : STD_LOGIC; | |
188 | data_shaping_SP0 : STD_LOGIC; |
|
189 | data_shaping_SP0 : STD_LOGIC; | |
189 | data_shaping_SP1 : STD_LOGIC; |
|
190 | data_shaping_SP1 : STD_LOGIC; | |
190 | data_shaping_R0 : STD_LOGIC; |
|
191 | data_shaping_R0 : STD_LOGIC; | |
191 | data_shaping_R1 : STD_LOGIC; |
|
192 | data_shaping_R1 : STD_LOGIC; | |
192 | delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
193 | delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
193 | delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
194 | delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
194 | delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
195 | delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
195 | delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
196 | delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
196 | delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
197 | delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
197 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
198 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
198 | nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
199 | nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
199 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
200 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
200 | enable_f0 : STD_LOGIC; |
|
201 | enable_f0 : STD_LOGIC; | |
201 | enable_f1 : STD_LOGIC; |
|
202 | enable_f1 : STD_LOGIC; | |
202 | enable_f2 : STD_LOGIC; |
|
203 | enable_f2 : STD_LOGIC; | |
203 | enable_f3 : STD_LOGIC; |
|
204 | enable_f3 : STD_LOGIC; | |
204 | burst_f0 : STD_LOGIC; |
|
205 | burst_f0 : STD_LOGIC; | |
205 | burst_f1 : STD_LOGIC; |
|
206 | burst_f1 : STD_LOGIC; | |
206 | burst_f2 : STD_LOGIC; |
|
207 | burst_f2 : STD_LOGIC; | |
207 | run : STD_LOGIC; |
|
208 | run : STD_LOGIC; | |
208 | addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
209 | addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
209 | addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
210 | addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
210 | addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
211 | addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
211 | addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
212 | addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
212 | start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
213 | start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
213 | END RECORD; |
|
214 | END RECORD; | |
214 | SIGNAL reg_wp : lpp_WaveformPicker_regs; |
|
215 | SIGNAL reg_wp : lpp_WaveformPicker_regs; | |
215 |
|
216 | |||
216 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
217 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
217 |
|
218 | |||
218 | ----------------------------------------------------------------------------- |
|
219 | ----------------------------------------------------------------------------- | |
219 | -- IRQ |
|
220 | -- IRQ | |
220 | ----------------------------------------------------------------------------- |
|
221 | ----------------------------------------------------------------------------- | |
221 | CONSTANT IRQ_WFP_SIZE : INTEGER := 12; |
|
222 | CONSTANT IRQ_WFP_SIZE : INTEGER := 12; | |
222 | SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
223 | SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
223 | SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
224 | SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
224 | SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
225 | SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
225 | SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
226 | SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
226 | SIGNAL ored_irq_wfp : STD_LOGIC; |
|
227 | SIGNAL ored_irq_wfp : STD_LOGIC; | |
227 |
|
228 | |||
228 | BEGIN -- beh |
|
229 | BEGIN -- beh | |
229 |
|
230 | |||
230 | status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0; |
|
231 | status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0; | |
231 | status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1; |
|
232 | -- status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1; | |
232 | status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; |
|
233 | status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; | |
233 | status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; |
|
234 | status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; | |
234 | status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; |
|
235 | -- status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; | |
235 | status_error_bad_component_error <= reg_sp.status_error_bad_component_error; |
|
236 | -- status_error_bad_component_error <= reg_sp.status_error_bad_component_error; | |
236 |
|
237 | |||
237 | config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; |
|
238 | config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; | |
238 | config_active_interruption_onError <= reg_sp.config_active_interruption_onError; |
|
239 | config_active_interruption_onError <= reg_sp.config_active_interruption_onError; | |
239 | addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; |
|
240 | addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; | |
240 | addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; |
|
241 | -- addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; | |
241 | addr_matrix_f1 <= reg_sp.addr_matrix_f1; |
|
242 | addr_matrix_f1 <= reg_sp.addr_matrix_f1; | |
242 | addr_matrix_f2 <= reg_sp.addr_matrix_f2; |
|
243 | addr_matrix_f2 <= reg_sp.addr_matrix_f2; | |
243 |
|
244 | |||
244 |
|
245 | |||
245 | data_shaping_BW <= NOT reg_wp.data_shaping_BW; |
|
246 | data_shaping_BW <= NOT reg_wp.data_shaping_BW; | |
246 | data_shaping_SP0 <= reg_wp.data_shaping_SP0; |
|
247 | data_shaping_SP0 <= reg_wp.data_shaping_SP0; | |
247 | data_shaping_SP1 <= reg_wp.data_shaping_SP1; |
|
248 | data_shaping_SP1 <= reg_wp.data_shaping_SP1; | |
248 | data_shaping_R0 <= reg_wp.data_shaping_R0; |
|
249 | data_shaping_R0 <= reg_wp.data_shaping_R0; | |
249 | data_shaping_R1 <= reg_wp.data_shaping_R1; |
|
250 | data_shaping_R1 <= reg_wp.data_shaping_R1; | |
250 |
|
251 | |||
251 | delta_snapshot <= reg_wp.delta_snapshot; |
|
252 | delta_snapshot <= reg_wp.delta_snapshot; | |
252 | delta_f0 <= reg_wp.delta_f0; |
|
253 | delta_f0 <= reg_wp.delta_f0; | |
253 | delta_f0_2 <= reg_wp.delta_f0_2; |
|
254 | delta_f0_2 <= reg_wp.delta_f0_2; | |
254 | delta_f1 <= reg_wp.delta_f1; |
|
255 | delta_f1 <= reg_wp.delta_f1; | |
255 | delta_f2 <= reg_wp.delta_f2; |
|
256 | delta_f2 <= reg_wp.delta_f2; | |
256 | nb_data_by_buffer <= reg_wp.nb_data_by_buffer; |
|
257 | nb_data_by_buffer <= reg_wp.nb_data_by_buffer; | |
257 | nb_word_by_buffer <= reg_wp.nb_word_by_buffer; |
|
258 | nb_word_by_buffer <= reg_wp.nb_word_by_buffer; | |
258 | nb_snapshot_param <= reg_wp.nb_snapshot_param; |
|
259 | nb_snapshot_param <= reg_wp.nb_snapshot_param; | |
259 |
|
260 | |||
260 | enable_f0 <= reg_wp.enable_f0; |
|
261 | enable_f0 <= reg_wp.enable_f0; | |
261 | enable_f1 <= reg_wp.enable_f1; |
|
262 | enable_f1 <= reg_wp.enable_f1; | |
262 | enable_f2 <= reg_wp.enable_f2; |
|
263 | enable_f2 <= reg_wp.enable_f2; | |
263 | enable_f3 <= reg_wp.enable_f3; |
|
264 | enable_f3 <= reg_wp.enable_f3; | |
264 |
|
265 | |||
265 | burst_f0 <= reg_wp.burst_f0; |
|
266 | burst_f0 <= reg_wp.burst_f0; | |
266 | burst_f1 <= reg_wp.burst_f1; |
|
267 | burst_f1 <= reg_wp.burst_f1; | |
267 | burst_f2 <= reg_wp.burst_f2; |
|
268 | burst_f2 <= reg_wp.burst_f2; | |
268 |
|
269 | |||
269 | run <= reg_wp.run; |
|
270 | run <= reg_wp.run; | |
270 |
|
271 | |||
271 | addr_data_f0 <= reg_wp.addr_data_f0; |
|
272 | addr_data_f0 <= reg_wp.addr_data_f0; | |
272 | addr_data_f1 <= reg_wp.addr_data_f1; |
|
273 | addr_data_f1 <= reg_wp.addr_data_f1; | |
273 | addr_data_f2 <= reg_wp.addr_data_f2; |
|
274 | addr_data_f2 <= reg_wp.addr_data_f2; | |
274 | addr_data_f3 <= reg_wp.addr_data_f3; |
|
275 | addr_data_f3 <= reg_wp.addr_data_f3; | |
275 |
|
276 | |||
276 | start_date <= reg_wp.start_date; |
|
277 | start_date <= reg_wp.start_date; | |
277 |
|
278 | |||
278 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) |
|
279 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) | |
279 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); |
|
280 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); | |
280 | BEGIN -- PROCESS lpp_dma_top |
|
281 | BEGIN -- PROCESS lpp_dma_top | |
281 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
282 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
282 | reg_sp.config_active_interruption_onNewMatrix <= '0'; |
|
283 | reg_sp.config_active_interruption_onNewMatrix <= '0'; | |
283 | reg_sp.config_active_interruption_onError <= '0'; |
|
284 | reg_sp.config_active_interruption_onError <= '0'; | |
284 | reg_sp.config_ms_run <= '1'; |
|
285 | reg_sp.config_ms_run <= '1'; | |
285 | reg_sp.status_ready_matrix_f0_0 <= '0'; |
|
286 | reg_sp.status_ready_matrix_f0_0 <= '0'; | |
286 | reg_sp.status_ready_matrix_f0_1 <= '0'; |
|
287 | -- reg_sp.status_ready_matrix_f0_1 <= '0'; | |
287 | reg_sp.status_ready_matrix_f1 <= '0'; |
|
288 | reg_sp.status_ready_matrix_f1 <= '0'; | |
288 | reg_sp.status_ready_matrix_f2 <= '0'; |
|
289 | reg_sp.status_ready_matrix_f2 <= '0'; | |
289 | reg_sp.status_error_anticipating_empty_fifo <= '0'; |
|
290 | -- reg_sp.status_error_anticipating_empty_fifo <= '0'; | |
290 | reg_sp.status_error_bad_component_error <= '0'; |
|
291 | reg_sp.status_error_bad_component_error <= '0'; | |
|
292 | reg_sp.status_error_buffer_full <= '0'; | |||
|
293 | reg_sp.status_error_input_fifo_write <= (OTHERS => '0'); | |||
|
294 | ||||
291 |
|
|
295 | reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); | |
292 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); |
|
296 | -- reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); | |
293 | reg_sp.addr_matrix_f1 <= (OTHERS => '0'); |
|
297 | reg_sp.addr_matrix_f1 <= (OTHERS => '0'); | |
294 | reg_sp.addr_matrix_f2 <= (OTHERS => '0'); |
|
298 | reg_sp.addr_matrix_f2 <= (OTHERS => '0'); | |
295 |
|
299 | |||
296 | reg_sp.coarse_time_f0_0 <= (OTHERS => '0'); |
|
300 | reg_sp.coarse_time_f0_0 <= (OTHERS => '0'); | |
297 | reg_sp.coarse_time_f0_1 <= (OTHERS => '0'); |
|
301 | -- reg_sp.coarse_time_f0_1 <= (OTHERS => '0'); | |
298 | reg_sp.coarse_time_f1 <= (OTHERS => '0'); |
|
302 | reg_sp.coarse_time_f1 <= (OTHERS => '0'); | |
299 | reg_sp.coarse_time_f2 <= (OTHERS => '0'); |
|
303 | reg_sp.coarse_time_f2 <= (OTHERS => '0'); | |
300 | --reg_sp.fine_time_f0_0 <= (OTHERS => '0'); |
|
304 | --reg_sp.fine_time_f0_0 <= (OTHERS => '0'); | |
301 | --reg_sp.fine_time_f0_1 <= (OTHERS => '0'); |
|
305 | --reg_sp.fine_time_f0_1 <= (OTHERS => '0'); | |
302 | --reg_sp.fine_time_f1 <= (OTHERS => '0'); |
|
306 | --reg_sp.fine_time_f1 <= (OTHERS => '0'); | |
303 | --reg_sp.fine_time_f2 <= (OTHERS => '0'); |
|
307 | --reg_sp.fine_time_f2 <= (OTHERS => '0'); | |
304 |
|
308 | |||
305 | prdata <= (OTHERS => '0'); |
|
309 | prdata <= (OTHERS => '0'); | |
306 |
|
310 | |||
307 | apbo.pirq <= (OTHERS => '0'); |
|
311 | apbo.pirq <= (OTHERS => '0'); | |
308 |
|
312 | |||
309 | status_full_ack <= (OTHERS => '0'); |
|
313 | status_full_ack <= (OTHERS => '0'); | |
310 |
|
314 | |||
311 | reg_wp.data_shaping_BW <= '0'; |
|
315 | reg_wp.data_shaping_BW <= '0'; | |
312 | reg_wp.data_shaping_SP0 <= '0'; |
|
316 | reg_wp.data_shaping_SP0 <= '0'; | |
313 | reg_wp.data_shaping_SP1 <= '0'; |
|
317 | reg_wp.data_shaping_SP1 <= '0'; | |
314 | reg_wp.data_shaping_R0 <= '0'; |
|
318 | reg_wp.data_shaping_R0 <= '0'; | |
315 | reg_wp.data_shaping_R1 <= '0'; |
|
319 | reg_wp.data_shaping_R1 <= '0'; | |
316 | reg_wp.enable_f0 <= '0'; |
|
320 | reg_wp.enable_f0 <= '0'; | |
317 | reg_wp.enable_f1 <= '0'; |
|
321 | reg_wp.enable_f1 <= '0'; | |
318 | reg_wp.enable_f2 <= '0'; |
|
322 | reg_wp.enable_f2 <= '0'; | |
319 | reg_wp.enable_f3 <= '0'; |
|
323 | reg_wp.enable_f3 <= '0'; | |
320 | reg_wp.burst_f0 <= '0'; |
|
324 | reg_wp.burst_f0 <= '0'; | |
321 | reg_wp.burst_f1 <= '0'; |
|
325 | reg_wp.burst_f1 <= '0'; | |
322 | reg_wp.burst_f2 <= '0'; |
|
326 | reg_wp.burst_f2 <= '0'; | |
323 | reg_wp.run <= '0'; |
|
327 | reg_wp.run <= '0'; | |
324 | reg_wp.addr_data_f0 <= (OTHERS => '0'); |
|
328 | reg_wp.addr_data_f0 <= (OTHERS => '0'); | |
325 | reg_wp.addr_data_f1 <= (OTHERS => '0'); |
|
329 | reg_wp.addr_data_f1 <= (OTHERS => '0'); | |
326 | reg_wp.addr_data_f2 <= (OTHERS => '0'); |
|
330 | reg_wp.addr_data_f2 <= (OTHERS => '0'); | |
327 | reg_wp.addr_data_f3 <= (OTHERS => '0'); |
|
331 | reg_wp.addr_data_f3 <= (OTHERS => '0'); | |
328 | reg_wp.status_full <= (OTHERS => '0'); |
|
332 | reg_wp.status_full <= (OTHERS => '0'); | |
329 | reg_wp.status_full_err <= (OTHERS => '0'); |
|
333 | reg_wp.status_full_err <= (OTHERS => '0'); | |
330 | reg_wp.status_new_err <= (OTHERS => '0'); |
|
334 | reg_wp.status_new_err <= (OTHERS => '0'); | |
331 | reg_wp.delta_snapshot <= (OTHERS => '0'); |
|
335 | reg_wp.delta_snapshot <= (OTHERS => '0'); | |
332 | reg_wp.delta_f0 <= (OTHERS => '0'); |
|
336 | reg_wp.delta_f0 <= (OTHERS => '0'); | |
333 | reg_wp.delta_f0_2 <= (OTHERS => '0'); |
|
337 | reg_wp.delta_f0_2 <= (OTHERS => '0'); | |
334 | reg_wp.delta_f1 <= (OTHERS => '0'); |
|
338 | reg_wp.delta_f1 <= (OTHERS => '0'); | |
335 | reg_wp.delta_f2 <= (OTHERS => '0'); |
|
339 | reg_wp.delta_f2 <= (OTHERS => '0'); | |
336 | reg_wp.nb_data_by_buffer <= (OTHERS => '0'); |
|
340 | reg_wp.nb_data_by_buffer <= (OTHERS => '0'); | |
337 | reg_wp.nb_snapshot_param <= (OTHERS => '0'); |
|
341 | reg_wp.nb_snapshot_param <= (OTHERS => '0'); | |
338 | reg_wp.start_date <= (OTHERS => '0'); |
|
342 | reg_wp.start_date <= (OTHERS => '0'); | |
339 |
|
343 | |||
340 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
344 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
341 |
|
345 | |||
342 | reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0); |
|
346 | reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0); | |
343 | reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0); |
|
347 | -- reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0); | |
344 | reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0); |
|
348 | reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0); | |
345 | reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0); |
|
349 | reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0); | |
346 |
|
350 | |||
347 | --reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0); |
|
351 | --reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0); | |
348 | --reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0); |
|
352 | --reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0); | |
349 | --reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0); |
|
353 | --reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0); | |
350 | --reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0); |
|
354 | --reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0); | |
351 |
|
355 | |||
352 | status_full_ack <= (OTHERS => '0'); |
|
356 | status_full_ack <= (OTHERS => '0'); | |
353 |
|
357 | |||
354 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; |
|
358 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; | |
355 | reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1; |
|
359 | -- reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1; | |
356 | reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1; |
|
360 | reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1; | |
357 | reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; |
|
361 | reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; | |
358 |
|
362 | |||
359 | reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; |
|
363 | -- reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; | |
360 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; |
|
364 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; | |
|
365 | ||||
|
366 | reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full; | |||
|
367 | reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0); | |||
|
368 | reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1); | |||
|
369 | reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2); | |||
|
370 | ||||
|
371 | ||||
|
372 | ||||
361 |
|
|
373 | all_status: FOR I IN 3 DOWNTO 0 LOOP | |
362 | --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; |
|
374 | --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; | |
363 | --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; |
|
375 | --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; | |
364 | --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; |
|
376 | --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; | |
365 | reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; |
|
377 | reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; | |
366 | reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run; |
|
378 | reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run; | |
367 | reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ; |
|
379 | reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ; | |
368 | END LOOP all_status; |
|
380 | END LOOP all_status; | |
369 |
|
381 | |||
370 | paddr := "000000"; |
|
382 | paddr := "000000"; | |
371 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); |
|
383 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); | |
372 | prdata <= (OTHERS => '0'); |
|
384 | prdata <= (OTHERS => '0'); | |
373 | IF apbi.psel(pindex) = '1' THEN |
|
385 | IF apbi.psel(pindex) = '1' THEN | |
374 | -- APB DMA READ -- |
|
386 | -- APB DMA READ -- | |
375 | CASE paddr(7 DOWNTO 2) IS |
|
387 | CASE paddr(7 DOWNTO 2) IS | |
376 | -- |
|
388 | -- | |
377 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; |
|
389 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; | |
378 | prdata(1) <= reg_sp.config_active_interruption_onError; |
|
390 | prdata(1) <= reg_sp.config_active_interruption_onError; | |
379 | prdata(2) <= reg_sp.config_ms_run; |
|
391 | prdata(2) <= reg_sp.config_ms_run; | |
380 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; |
|
392 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; | |
381 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; |
|
393 | -- prdata(1) <= reg_sp.status_ready_matrix_f0_1; | |
382 | prdata(2) <= reg_sp.status_ready_matrix_f1; |
|
394 | prdata(2) <= reg_sp.status_ready_matrix_f1; | |
383 | prdata(3) <= reg_sp.status_ready_matrix_f2; |
|
395 | prdata(3) <= reg_sp.status_ready_matrix_f2; | |
384 | prdata(4) <= reg_sp.status_error_anticipating_empty_fifo; |
|
396 | -- prdata(4) <= reg_sp.status_error_anticipating_empty_fifo; | |
385 | prdata(5) <= reg_sp.status_error_bad_component_error; |
|
397 | prdata(5) <= reg_sp.status_error_bad_component_error; | |
|
398 | prdata(6) <= reg_sp.status_error_buffer_full; | |||
|
399 | prdata(7) <= reg_sp.status_error_input_fifo_write(0); | |||
|
400 | prdata(8) <= reg_sp.status_error_input_fifo_write(1); | |||
|
401 | prdata(9) <= reg_sp.status_error_input_fifo_write(2); | |||
386 |
|
|
402 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; | |
387 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; |
|
403 | -- WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; | |
388 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1; |
|
404 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1; | |
389 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; |
|
405 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; | |
390 |
|
406 | |||
391 | WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0; |
|
407 | WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0; | |
392 | WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1; |
|
408 | -- WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1; | |
393 | WHEN "001000" => prdata <= reg_sp.coarse_time_f1; |
|
409 | WHEN "001000" => prdata <= reg_sp.coarse_time_f1; | |
394 | WHEN "001001" => prdata <= reg_sp.coarse_time_f2; |
|
410 | WHEN "001001" => prdata <= reg_sp.coarse_time_f2; | |
395 | WHEN "001010" => prdata(15 downto 0) <= matrix_time_f0_0(15 DOWNTO 0);--reg_sp.fine_time_f0_0; |
|
411 | WHEN "001010" => prdata(15 downto 0) <= matrix_time_f0_0(15 DOWNTO 0);--reg_sp.fine_time_f0_0; | |
396 | WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1; |
|
412 | -- WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1; | |
397 | WHEN "001100" => prdata(15 downto 0) <= matrix_time_f1 (15 DOWNTO 0);--reg_sp.fine_time_f1; |
|
413 | WHEN "001100" => prdata(15 downto 0) <= matrix_time_f1 (15 DOWNTO 0);--reg_sp.fine_time_f1; | |
398 | WHEN "001101" => prdata(15 downto 0) <= matrix_time_f2 (15 DOWNTO 0);--reg_sp.fine_time_f2; |
|
414 | WHEN "001101" => prdata(15 downto 0) <= matrix_time_f2 (15 DOWNTO 0);--reg_sp.fine_time_f2; | |
399 |
|
415 | |||
400 | WHEN "001111" => prdata <= debug_reg; |
|
416 | WHEN "001111" => prdata <= debug_reg; | |
401 | --------------------------------------------------------------------- |
|
417 | --------------------------------------------------------------------- | |
402 | WHEN "010000" => prdata(0) <= reg_wp.data_shaping_BW; |
|
418 | WHEN "010000" => prdata(0) <= reg_wp.data_shaping_BW; | |
403 | prdata(1) <= reg_wp.data_shaping_SP0; |
|
419 | prdata(1) <= reg_wp.data_shaping_SP0; | |
404 | prdata(2) <= reg_wp.data_shaping_SP1; |
|
420 | prdata(2) <= reg_wp.data_shaping_SP1; | |
405 | prdata(3) <= reg_wp.data_shaping_R0; |
|
421 | prdata(3) <= reg_wp.data_shaping_R0; | |
406 | prdata(4) <= reg_wp.data_shaping_R1; |
|
422 | prdata(4) <= reg_wp.data_shaping_R1; | |
407 | WHEN "010001" => prdata(0) <= reg_wp.enable_f0; |
|
423 | WHEN "010001" => prdata(0) <= reg_wp.enable_f0; | |
408 | prdata(1) <= reg_wp.enable_f1; |
|
424 | prdata(1) <= reg_wp.enable_f1; | |
409 | prdata(2) <= reg_wp.enable_f2; |
|
425 | prdata(2) <= reg_wp.enable_f2; | |
410 | prdata(3) <= reg_wp.enable_f3; |
|
426 | prdata(3) <= reg_wp.enable_f3; | |
411 | prdata(4) <= reg_wp.burst_f0; |
|
427 | prdata(4) <= reg_wp.burst_f0; | |
412 | prdata(5) <= reg_wp.burst_f1; |
|
428 | prdata(5) <= reg_wp.burst_f1; | |
413 | prdata(6) <= reg_wp.burst_f2; |
|
429 | prdata(6) <= reg_wp.burst_f2; | |
414 | prdata(7) <= reg_wp.run; |
|
430 | prdata(7) <= reg_wp.run; | |
415 | WHEN "010010" => prdata <= reg_wp.addr_data_f0; |
|
431 | WHEN "010010" => prdata <= reg_wp.addr_data_f0; | |
416 | WHEN "010011" => prdata <= reg_wp.addr_data_f1; |
|
432 | WHEN "010011" => prdata <= reg_wp.addr_data_f1; | |
417 | WHEN "010100" => prdata <= reg_wp.addr_data_f2; |
|
433 | WHEN "010100" => prdata <= reg_wp.addr_data_f2; | |
418 | WHEN "010101" => prdata <= reg_wp.addr_data_f3; |
|
434 | WHEN "010101" => prdata <= reg_wp.addr_data_f3; | |
419 | WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; |
|
435 | WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; | |
420 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; |
|
436 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; | |
421 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; |
|
437 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; | |
422 | WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; |
|
438 | WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; | |
423 | WHEN "011000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; |
|
439 | WHEN "011000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; | |
424 | WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; |
|
440 | WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; | |
425 | WHEN "011010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; |
|
441 | WHEN "011010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; | |
426 | WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; |
|
442 | WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; | |
427 | WHEN "011100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; |
|
443 | WHEN "011100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; | |
428 | WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; |
|
444 | WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; | |
429 | WHEN "011110" => prdata(30 DOWNTO 0) <= reg_wp.start_date; |
|
445 | WHEN "011110" => prdata(30 DOWNTO 0) <= reg_wp.start_date; | |
430 | WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; |
|
446 | WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; | |
431 | ---------------------------------------------------- |
|
447 | ---------------------------------------------------- | |
432 | WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0); |
|
448 | WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0); | |
433 | WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0); |
|
449 | WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0); | |
434 | WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0); |
|
450 | WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0); | |
435 | WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0); |
|
451 | WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0); | |
436 | WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0); |
|
452 | WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0); | |
437 | WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0); |
|
453 | WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0); | |
438 | WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0); |
|
454 | WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0); | |
439 | WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0); |
|
455 | WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0); | |
440 | ---------------------------------------------------- |
|
456 | ---------------------------------------------------- | |
441 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); |
|
457 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); | |
442 | WHEN OTHERS => NULL; |
|
458 | WHEN OTHERS => NULL; | |
443 |
|
459 | |||
444 | END CASE; |
|
460 | END CASE; | |
445 | IF (apbi.pwrite AND apbi.penable) = '1' THEN |
|
461 | IF (apbi.pwrite AND apbi.penable) = '1' THEN | |
446 | -- APB DMA WRITE -- |
|
462 | -- APB DMA WRITE -- | |
447 | CASE paddr(7 DOWNTO 2) IS |
|
463 | CASE paddr(7 DOWNTO 2) IS | |
448 | -- |
|
464 | -- | |
449 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); |
|
465 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); | |
450 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); |
|
466 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); | |
451 | reg_sp.config_ms_run <= apbi.pwdata(2); |
|
467 | reg_sp.config_ms_run <= apbi.pwdata(2); | |
452 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); |
|
468 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); | |
453 | reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); |
|
469 | -- reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); | |
454 | reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); |
|
470 | reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); | |
455 | reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3); |
|
471 | reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3); | |
456 | reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4); |
|
472 | -- reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4); | |
457 | reg_sp.status_error_bad_component_error <= apbi.pwdata(5); |
|
473 | reg_sp.status_error_bad_component_error <= apbi.pwdata(5); | |
|
474 | reg_sp.status_error_buffer_full <= apbi.pwdata(6); | |||
|
475 | reg_sp.status_error_input_fifo_write(0) <= apbi.pwdata(7); | |||
|
476 | reg_sp.status_error_input_fifo_write(1) <= apbi.pwdata(8); | |||
|
477 | reg_sp.status_error_input_fifo_write(2) <= apbi.pwdata(9); | |||
458 |
|
|
478 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; | |
459 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; |
|
479 | -- WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |
460 | WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; |
|
480 | WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; | |
461 | WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; |
|
481 | WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; | |
462 | -- |
|
482 | -- | |
463 | WHEN "010000" => reg_wp.data_shaping_BW <= apbi.pwdata(0); |
|
483 | WHEN "010000" => reg_wp.data_shaping_BW <= apbi.pwdata(0); | |
464 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); |
|
484 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); | |
465 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); |
|
485 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); | |
466 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); |
|
486 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); | |
467 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); |
|
487 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); | |
468 | WHEN "010001" => reg_wp.enable_f0 <= apbi.pwdata(0); |
|
488 | WHEN "010001" => reg_wp.enable_f0 <= apbi.pwdata(0); | |
469 | reg_wp.enable_f1 <= apbi.pwdata(1); |
|
489 | reg_wp.enable_f1 <= apbi.pwdata(1); | |
470 | reg_wp.enable_f2 <= apbi.pwdata(2); |
|
490 | reg_wp.enable_f2 <= apbi.pwdata(2); | |
471 | reg_wp.enable_f3 <= apbi.pwdata(3); |
|
491 | reg_wp.enable_f3 <= apbi.pwdata(3); | |
472 | reg_wp.burst_f0 <= apbi.pwdata(4); |
|
492 | reg_wp.burst_f0 <= apbi.pwdata(4); | |
473 | reg_wp.burst_f1 <= apbi.pwdata(5); |
|
493 | reg_wp.burst_f1 <= apbi.pwdata(5); | |
474 | reg_wp.burst_f2 <= apbi.pwdata(6); |
|
494 | reg_wp.burst_f2 <= apbi.pwdata(6); | |
475 | reg_wp.run <= apbi.pwdata(7); |
|
495 | reg_wp.run <= apbi.pwdata(7); | |
476 | WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata; |
|
496 | WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata; | |
477 | WHEN "010011" => reg_wp.addr_data_f1 <= apbi.pwdata; |
|
497 | WHEN "010011" => reg_wp.addr_data_f1 <= apbi.pwdata; | |
478 | WHEN "010100" => reg_wp.addr_data_f2 <= apbi.pwdata; |
|
498 | WHEN "010100" => reg_wp.addr_data_f2 <= apbi.pwdata; | |
479 | WHEN "010101" => reg_wp.addr_data_f3 <= apbi.pwdata; |
|
499 | WHEN "010101" => reg_wp.addr_data_f3 <= apbi.pwdata; | |
480 | WHEN "010110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); |
|
500 | WHEN "010110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); | |
481 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); |
|
501 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); | |
482 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); |
|
502 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); | |
483 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); |
|
503 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); | |
484 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); |
|
504 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); | |
485 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); |
|
505 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); | |
486 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); |
|
506 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); | |
487 | WHEN "010111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); |
|
507 | WHEN "010111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
488 | WHEN "011000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); |
|
508 | WHEN "011000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
489 | WHEN "011001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); |
|
509 | WHEN "011001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); | |
490 | WHEN "011010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); |
|
510 | WHEN "011010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
491 | WHEN "011011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); |
|
511 | WHEN "011011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
492 | WHEN "011100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); |
|
512 | WHEN "011100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); | |
493 | WHEN "011101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); |
|
513 | WHEN "011101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); | |
494 | WHEN "011110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); |
|
514 | WHEN "011110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); | |
495 | WHEN "011111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); |
|
515 | WHEN "011111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); | |
496 | -- |
|
516 | -- | |
497 | WHEN OTHERS => NULL; |
|
517 | WHEN OTHERS => NULL; | |
498 | END CASE; |
|
518 | END CASE; | |
499 | END IF; |
|
519 | END IF; | |
500 | END IF; |
|
520 | END IF; | |
501 |
|
521 | |||
502 | apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR |
|
522 | apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR | |
503 | ready_matrix_f0_1 OR |
|
523 | -- ready_matrix_f0_1 OR | |
504 | ready_matrix_f1 OR |
|
524 | ready_matrix_f1 OR | |
505 | ready_matrix_f2) |
|
525 | ready_matrix_f2) | |
506 | ) |
|
526 | ) | |
507 | OR |
|
527 | OR | |
508 |
(reg_sp.config_active_interruption_onError AND ( |
|
528 | (reg_sp.config_active_interruption_onError AND ( | |
509 | error_bad_component_error) |
|
529 | --error_anticipating_empty_fifo OR | |
|
530 | error_bad_component_error | |||
|
531 | OR error_buffer_full | |||
|
532 | OR error_input_fifo_write(0) | |||
|
533 | OR error_input_fifo_write(1) | |||
|
534 | OR error_input_fifo_write(2)) | |||
510 | )); |
|
535 | )); | |
511 |
|
536 | |||
512 | apbo.pirq(pirq_wfp) <= ored_irq_wfp; |
|
537 | apbo.pirq(pirq_wfp) <= ored_irq_wfp; | |
513 |
|
538 | |||
514 | END IF; |
|
539 | END IF; | |
515 | END PROCESS lpp_lfr_apbreg; |
|
540 | END PROCESS lpp_lfr_apbreg; | |
516 |
|
541 | |||
517 | apbo.pindex <= pindex; |
|
542 | apbo.pindex <= pindex; | |
518 | apbo.pconfig <= pconfig; |
|
543 | apbo.pconfig <= pconfig; | |
519 | apbo.prdata <= prdata; |
|
544 | apbo.prdata <= prdata; | |
520 |
|
545 | |||
521 | ----------------------------------------------------------------------------- |
|
546 | ----------------------------------------------------------------------------- | |
522 | -- IRQ |
|
547 | -- IRQ | |
523 | ----------------------------------------------------------------------------- |
|
548 | ----------------------------------------------------------------------------- | |
524 | irq_wfp_reg_s <= status_full & status_full_err & status_new_err; |
|
549 | irq_wfp_reg_s <= status_full & status_full_err & status_new_err; | |
525 |
|
550 | |||
526 | PROCESS (HCLK, HRESETn) |
|
551 | PROCESS (HCLK, HRESETn) | |
527 | BEGIN -- PROCESS |
|
552 | BEGIN -- PROCESS | |
528 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
553 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
529 | irq_wfp_reg <= (OTHERS => '0'); |
|
554 | irq_wfp_reg <= (OTHERS => '0'); | |
530 | ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge |
|
555 | ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge | |
531 | irq_wfp_reg <= irq_wfp_reg_s; |
|
556 | irq_wfp_reg <= irq_wfp_reg_s; | |
532 | END IF; |
|
557 | END IF; | |
533 | END PROCESS; |
|
558 | END PROCESS; | |
534 |
|
559 | |||
535 | all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE |
|
560 | all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE | |
536 | irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I); |
|
561 | irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I); | |
537 | END GENERATE all_irq_wfp; |
|
562 | END GENERATE all_irq_wfp; | |
538 |
|
563 | |||
539 | irq_wfp_ZERO <= (OTHERS => '0'); |
|
564 | irq_wfp_ZERO <= (OTHERS => '0'); | |
540 | ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; |
|
565 | ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; | |
541 |
|
566 | |||
542 | run_ms <= reg_sp.config_ms_run; |
|
567 | run_ms <= reg_sp.config_ms_run; | |
543 |
|
568 | |||
544 | END beh; No newline at end of file |
|
569 | END beh; |
This diff has been collapsed as it changes many lines, (616 lines changed) Show them Hide them | |||||
@@ -1,1067 +1,943 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 |
|
3 | |||
4 |
|
4 | |||
5 | LIBRARY lpp; |
|
5 | LIBRARY lpp; | |
6 | USE lpp.lpp_memory.ALL; |
|
6 | USE lpp.lpp_memory.ALL; | |
7 | USE lpp.iir_filter.ALL; |
|
7 | USE lpp.iir_filter.ALL; | |
8 | USE lpp.spectral_matrix_package.ALL; |
|
8 | USE lpp.spectral_matrix_package.ALL; | |
9 | USE lpp.lpp_dma_pkg.ALL; |
|
9 | USE lpp.lpp_dma_pkg.ALL; | |
10 | USE lpp.lpp_Header.ALL; |
|
10 | USE lpp.lpp_Header.ALL; | |
11 | USE lpp.lpp_matrix.ALL; |
|
11 | USE lpp.lpp_matrix.ALL; | |
12 | USE lpp.lpp_matrix.ALL; |
|
12 | USE lpp.lpp_matrix.ALL; | |
13 | USE lpp.lpp_lfr_pkg.ALL; |
|
13 | USE lpp.lpp_lfr_pkg.ALL; | |
14 | USE lpp.lpp_fft.ALL; |
|
14 | USE lpp.lpp_fft.ALL; | |
15 | USE lpp.fft_components.ALL; |
|
15 | USE lpp.fft_components.ALL; | |
16 |
|
16 | |||
17 | ENTITY lpp_lfr_ms IS |
|
17 | ENTITY lpp_lfr_ms IS | |
18 | GENERIC ( |
|
18 | GENERIC ( | |
19 | Mem_use : INTEGER := use_RAM |
|
19 | Mem_use : INTEGER := use_RAM | |
20 | ); |
|
20 | ); | |
21 | PORT ( |
|
21 | PORT ( | |
22 | clk : IN STD_LOGIC; |
|
22 | clk : IN STD_LOGIC; | |
23 | rstn : IN STD_LOGIC; |
|
23 | rstn : IN STD_LOGIC; | |
24 |
|
24 | |||
25 | --------------------------------------------------------------------------- |
|
25 | --------------------------------------------------------------------------- | |
26 | -- DATA INPUT |
|
26 | -- DATA INPUT | |
27 | --------------------------------------------------------------------------- |
|
27 | --------------------------------------------------------------------------- | |
28 | -- TIME |
|
28 | -- TIME | |
29 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
29 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
30 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
30 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
31 | -- |
|
31 | -- | |
32 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
32 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
33 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
33 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
34 | -- |
|
34 | -- | |
35 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
35 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
36 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
36 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
37 | -- |
|
37 | -- | |
38 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
38 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
39 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
39 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
40 |
|
40 | |||
41 | --------------------------------------------------------------------------- |
|
41 | --------------------------------------------------------------------------- | |
42 | -- DMA |
|
42 | -- DMA | |
43 | --------------------------------------------------------------------------- |
|
43 | --------------------------------------------------------------------------- | |
44 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
44 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
45 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
45 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
46 | dma_valid : OUT STD_LOGIC; |
|
46 | dma_valid : OUT STD_LOGIC; | |
47 | dma_valid_burst : OUT STD_LOGIC; |
|
47 | dma_valid_burst : OUT STD_LOGIC; | |
48 | dma_ren : IN STD_LOGIC; |
|
48 | dma_ren : IN STD_LOGIC; | |
49 | dma_done : IN STD_LOGIC; |
|
49 | dma_done : IN STD_LOGIC; | |
50 |
|
50 | |||
51 | -- Reg out |
|
51 | -- Reg out | |
52 |
ready_matrix_f0 |
|
52 | ready_matrix_f0 : OUT STD_LOGIC; | |
53 |
|
|
53 | ready_matrix_f1 : OUT STD_LOGIC; | |
54 |
ready_matrix_f |
|
54 | ready_matrix_f2 : OUT STD_LOGIC; | |
55 | ready_matrix_f2 : OUT STD_LOGIC; |
|
55 | error_bad_component_error : OUT STD_LOGIC; | |
56 |
|
|
56 | error_buffer_full : OUT STD_LOGIC; | |
57 | error_bad_component_error : OUT STD_LOGIC; |
|
57 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
58 | error_buffer_full : OUT STD_LOGIC; |
|
58 | ||
59 |
|
|
59 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
60 |
|
||||
61 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
62 |
|
60 | |||
63 | -- Reg In |
|
61 | -- Reg In | |
64 |
status_ready_matrix_f0 |
|
62 | status_ready_matrix_f0 : IN STD_LOGIC; | |
65 |
|
|
63 | status_ready_matrix_f1 : IN STD_LOGIC; | |
66 |
status_ready_matrix_f |
|
64 | status_ready_matrix_f2 : IN STD_LOGIC; | |
67 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
|||
68 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
|||
69 | -- status_error_bad_component_error : IN STD_LOGIC; |
|
|||
70 | -- status_error_buffer_full : IN STD_LOGIC; |
|
|||
71 |
|
65 | |||
72 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
66 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
73 | config_active_interruption_onError : IN STD_LOGIC; |
|
67 | config_active_interruption_onError : IN STD_LOGIC; | |
74 | -- addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
75 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
68 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
76 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
69 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
77 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
70 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
78 |
|
71 | |||
79 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
72 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
80 |
|
|
73 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
81 |
matrix_time_f |
|
74 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
82 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
|||
83 |
|
75 | |||
84 | ); |
|
76 | ); | |
85 | END; |
|
77 | END; | |
86 |
|
78 | |||
87 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS |
|
79 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |
88 |
|
80 | |||
89 | SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
81 | SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
90 | SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
82 | SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
91 | SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
83 | SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
92 | SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
84 | SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
93 | SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
85 | SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
94 |
|
86 | |||
95 | SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
87 | SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
96 | SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
88 | SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
97 | SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
89 | SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
98 | SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
90 | SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
99 | SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
91 | SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
100 |
|
92 | |||
101 | SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
93 | SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
102 | SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
94 | SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
103 | SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
95 | SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
104 | SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
96 | SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
105 |
|
97 | |||
106 | SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
98 | SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
107 |
|
99 | |||
108 | SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
100 | SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
109 | SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
101 | SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
110 | SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
102 | SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
111 | SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
103 | SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
112 |
|
104 | |||
113 | SIGNAL error_wen_f0 : STD_LOGIC; |
|
105 | SIGNAL error_wen_f0 : STD_LOGIC; | |
114 | SIGNAL error_wen_f1 : STD_LOGIC; |
|
106 | SIGNAL error_wen_f1 : STD_LOGIC; | |
115 | SIGNAL error_wen_f2 : STD_LOGIC; |
|
107 | SIGNAL error_wen_f2 : STD_LOGIC; | |
116 |
|
108 | |||
117 | SIGNAL one_sample_f1_full : STD_LOGIC; |
|
109 | SIGNAL one_sample_f1_full : STD_LOGIC; | |
118 | SIGNAL one_sample_f1_wen : STD_LOGIC; |
|
110 | SIGNAL one_sample_f1_wen : STD_LOGIC; | |
119 | SIGNAL one_sample_f2_full : STD_LOGIC; |
|
111 | SIGNAL one_sample_f2_full : STD_LOGIC; | |
120 | SIGNAL one_sample_f2_wen : STD_LOGIC; |
|
112 | SIGNAL one_sample_f2_wen : STD_LOGIC; | |
121 |
|
113 | |||
122 | ----------------------------------------------------------------------------- |
|
114 | ----------------------------------------------------------------------------- | |
123 | -- FSM / SWITCH SELECT CHANNEL |
|
115 | -- FSM / SWITCH SELECT CHANNEL | |
124 | ----------------------------------------------------------------------------- |
|
116 | ----------------------------------------------------------------------------- | |
125 | TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2); |
|
117 | TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2); | |
126 | SIGNAL state_fsm_select_channel : fsm_select_channel; |
|
118 | SIGNAL state_fsm_select_channel : fsm_select_channel; | |
127 | SIGNAL pre_state_fsm_select_channel : fsm_select_channel; |
|
119 | SIGNAL pre_state_fsm_select_channel : fsm_select_channel; | |
128 |
|
120 | |||
129 | SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
121 | SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
130 | SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
122 | SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
131 | SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
123 | SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
132 | SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
124 | SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
133 |
|
125 | |||
134 | ----------------------------------------------------------------------------- |
|
126 | ----------------------------------------------------------------------------- | |
135 | -- FSM LOAD FFT |
|
127 | -- FSM LOAD FFT | |
136 | ----------------------------------------------------------------------------- |
|
128 | ----------------------------------------------------------------------------- | |
137 | TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5); |
|
129 | TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5); | |
138 | SIGNAL state_fsm_load_FFT : fsm_load_FFT; |
|
130 | SIGNAL state_fsm_load_FFT : fsm_load_FFT; | |
139 | SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; |
|
131 | SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; | |
140 |
|
132 | |||
141 | SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
133 | SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
142 | SIGNAL sample_load : STD_LOGIC; |
|
134 | SIGNAL sample_load : STD_LOGIC; | |
143 | SIGNAL sample_valid : STD_LOGIC; |
|
135 | SIGNAL sample_valid : STD_LOGIC; | |
144 | SIGNAL sample_valid_r : STD_LOGIC; |
|
136 | SIGNAL sample_valid_r : STD_LOGIC; | |
145 | SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
137 | SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
146 |
|
138 | |||
147 |
|
139 | |||
148 | ----------------------------------------------------------------------------- |
|
140 | ----------------------------------------------------------------------------- | |
149 | -- FFT |
|
141 | -- FFT | |
150 | ----------------------------------------------------------------------------- |
|
142 | ----------------------------------------------------------------------------- | |
151 | SIGNAL fft_read : STD_LOGIC; |
|
143 | SIGNAL fft_read : STD_LOGIC; | |
152 | SIGNAL fft_pong : STD_LOGIC; |
|
144 | SIGNAL fft_pong : STD_LOGIC; | |
153 | SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
145 | SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
154 | SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
146 | SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
155 | SIGNAL fft_data_valid : STD_LOGIC; |
|
147 | SIGNAL fft_data_valid : STD_LOGIC; | |
156 | SIGNAL fft_ready : STD_LOGIC; |
|
148 | SIGNAL fft_ready : STD_LOGIC; | |
157 | ----------------------------------------------------------------------------- |
|
149 | ----------------------------------------------------------------------------- | |
158 | -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
150 | -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
159 | ----------------------------------------------------------------------------- |
|
151 | ----------------------------------------------------------------------------- | |
160 | TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT); |
|
152 | TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT); | |
161 | SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory; |
|
153 | SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory; | |
162 | SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
154 | SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
163 | SIGNAL current_fifo_empty : STD_LOGIC; |
|
155 | SIGNAL current_fifo_empty : STD_LOGIC; | |
164 | SIGNAL current_fifo_locked : STD_LOGIC; |
|
156 | SIGNAL current_fifo_locked : STD_LOGIC; | |
165 | SIGNAL current_fifo_full : STD_LOGIC; |
|
157 | SIGNAL current_fifo_full : STD_LOGIC; | |
166 | SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
158 | SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
167 |
|
159 | |||
168 | ----------------------------------------------------------------------------- |
|
160 | ----------------------------------------------------------------------------- | |
169 |
SIGNAL MEM_IN_SM_ReUse |
|
161 | SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
170 |
SIGNAL MEM_IN_SM_wen |
|
162 | SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
171 |
SIGNAL MEM_IN_SM_wen_s |
|
163 | SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
172 |
SIGNAL MEM_IN_SM_ren |
|
164 | SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
173 |
SIGNAL MEM_IN_SM_wData |
|
165 | SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); | |
174 |
SIGNAL MEM_IN_SM_rData |
|
166 | SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); | |
175 |
SIGNAL MEM_IN_SM_Full |
|
167 | SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
176 |
SIGNAL MEM_IN_SM_Empty |
|
168 | SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
177 | ----------------------------------------------------------------------------- |
|
169 | ----------------------------------------------------------------------------- | |
178 | SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); |
|
170 | SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); | |
179 | SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
171 | SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
180 | SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
172 | SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
181 |
|
173 | |||
182 | SIGNAL SM_correlation_start : STD_LOGIC; |
|
174 | SIGNAL SM_correlation_start : STD_LOGIC; | |
183 | SIGNAL SM_correlation_auto : STD_LOGIC; |
|
175 | SIGNAL SM_correlation_auto : STD_LOGIC; | |
184 | SIGNAL SM_correlation_done : STD_LOGIC; |
|
176 | SIGNAL SM_correlation_done : STD_LOGIC; | |
185 | SIGNAL SM_correlation_done_reg1 : STD_LOGIC; |
|
177 | SIGNAL SM_correlation_done_reg1 : STD_LOGIC; | |
186 | SIGNAL SM_correlation_done_reg2 : STD_LOGIC; |
|
178 | SIGNAL SM_correlation_done_reg2 : STD_LOGIC; | |
187 | SIGNAL SM_correlation_done_reg3 : STD_LOGIC; |
|
179 | SIGNAL SM_correlation_done_reg3 : STD_LOGIC; | |
188 | SIGNAL SM_correlation_begin : STD_LOGIC; |
|
180 | SIGNAL SM_correlation_begin : STD_LOGIC; | |
189 |
|
||||
190 | -- SIGNAL temp_ongoing : STD_LOGIC; |
|
|||
191 | -- SIGNAL temp_auto : STD_LOGIC; |
|
|||
192 |
|
181 | |||
193 |
SIGNAL MEM_OUT_SM_Full_s |
|
182 | SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC; | |
194 |
SIGNAL MEM_OUT_SM_Data_in_s |
|
183 | SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
195 |
SIGNAL MEM_OUT_SM_Write_s |
|
184 | SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC; | |
196 |
|
185 | |||
197 |
SIGNAL |
|
186 | SIGNAL current_matrix_write : STD_LOGIC; | |
198 |
SIGNAL |
|
187 | SIGNAL current_matrix_wait_empty : STD_LOGIC; | |
199 |
|
||||
200 | --SIGNAL MEM_OUT_SM_BURST_available : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|||
201 |
|
||||
202 | ----------------------------------------------------------------------------- |
|
188 | ----------------------------------------------------------------------------- | |
203 |
SIGNAL |
|
189 | SIGNAL fifo_0_ready : STD_LOGIC; | |
204 |
SIGNAL |
|
190 | SIGNAL fifo_1_ready : STD_LOGIC; | |
205 |
SIGNAL |
|
191 | SIGNAL fifo_ongoing : STD_LOGIC; | |
206 |
|
192 | |||
207 | SIGNAL FSM_DMA_fifo_ren : STD_LOGIC; |
|
193 | SIGNAL FSM_DMA_fifo_ren : STD_LOGIC; | |
208 | SIGNAL FSM_DMA_fifo_empty : STD_LOGIC; |
|
194 | SIGNAL FSM_DMA_fifo_empty : STD_LOGIC; | |
209 | SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
195 | SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
210 | SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
196 | SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
211 |
|
||||
212 | ----------------------------------------------------------------------------- |
|
197 | ----------------------------------------------------------------------------- | |
213 | -- SIGNAL HEAD_SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
|||
214 | --SIGNAL HEAD_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|||
215 | --SIGNAL HEAD_SM_Wen : STD_LOGIC; |
|
|||
216 | --SIGNAL HEAD_Valid : STD_LOGIC; |
|
|||
217 | --SIGNAL HEAD_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
218 | --SIGNAL HEAD_Empty : STD_LOGIC; |
|
|||
219 | --SIGNAL HEAD_Read : STD_LOGIC; |
|
|||
220 | ----------------------------------------------------------------------------- |
|
|||
221 | -- SIGNAL MEM_OUT_SM_ReUse : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|||
222 | SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
198 | SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
223 | SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
199 | SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
224 | SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
200 | SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
225 | SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
201 | SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
226 | SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
202 | SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
227 | SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
203 | SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
228 | ----------------------------------------------------------------------------- |
|
|||
229 | --SIGNAL DMA_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
230 | --SIGNAL DMA_Header_Val : STD_LOGIC; |
|
|||
231 | --SIGNAL DMA_Header_Ack : STD_LOGIC; |
|
|||
232 |
|
204 | |||
233 | ----------------------------------------------------------------------------- |
|
205 | ----------------------------------------------------------------------------- | |
234 | -- TIME REG & INFOs |
|
206 | -- TIME REG & INFOs | |
235 | ----------------------------------------------------------------------------- |
|
207 | ----------------------------------------------------------------------------- | |
236 | SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
208 | SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
237 |
|
209 | |||
238 | SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
210 | SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
239 | SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
211 | SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
240 | SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
212 | SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
241 | SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
213 | SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
242 |
|
214 | |||
243 | SIGNAL time_update_f0_A : STD_LOGIC; |
|
215 | SIGNAL time_update_f0_A : STD_LOGIC; | |
244 | SIGNAL time_update_f0_B : STD_LOGIC; |
|
216 | SIGNAL time_update_f0_B : STD_LOGIC; | |
245 | SIGNAL time_update_f1 : STD_LOGIC; |
|
217 | SIGNAL time_update_f1 : STD_LOGIC; | |
246 | SIGNAL time_update_f2 : STD_LOGIC; |
|
218 | SIGNAL time_update_f2 : STD_LOGIC; | |
247 | -- |
|
219 | -- | |
248 | SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
220 | SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0); | |
249 | SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
221 | SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0); | |
250 | SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
222 | SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
251 |
|
223 | |||
252 | SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
224 | SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
253 | SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
225 | SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
254 | -- SIGNAL status_component_fifo_0_new : STD_LOGIC; |
|
|||
255 | -- SIGNAL status_component_fifo_1_new : STD_LOGIC; |
|
|||
256 | SIGNAL status_component_fifo_0_end : STD_LOGIC; |
|
226 | SIGNAL status_component_fifo_0_end : STD_LOGIC; | |
257 | SIGNAL status_component_fifo_1_end : STD_LOGIC; |
|
227 | SIGNAL status_component_fifo_1_end : STD_LOGIC; | |
258 |
|
||||
259 | SIGNAL dma_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|||
260 | ----------------------------------------------------------------------------- |
|
228 | ----------------------------------------------------------------------------- | |
261 |
|
229 | |||
262 | BEGIN |
|
230 | BEGIN | |
263 |
|
231 | |||
264 |
|
232 | |||
265 |
error_input_fifo_write <= |
|
233 | error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0; | |
266 |
|
234 | |||
267 |
|
235 | |||
268 | switch_f0_inst : spectral_matrix_switch_f0 |
|
236 | switch_f0_inst : spectral_matrix_switch_f0 | |
269 | PORT MAP ( |
|
237 | PORT MAP ( | |
270 | clk => clk, |
|
238 | clk => clk, | |
271 | rstn => rstn, |
|
239 | rstn => rstn, | |
272 |
|
240 | |||
273 | sample_wen => sample_f0_wen, |
|
241 | sample_wen => sample_f0_wen, | |
274 |
|
242 | |||
275 | fifo_A_empty => sample_f0_A_empty, |
|
243 | fifo_A_empty => sample_f0_A_empty, | |
276 | fifo_A_full => sample_f0_A_full, |
|
244 | fifo_A_full => sample_f0_A_full, | |
277 | fifo_A_wen => sample_f0_A_wen, |
|
245 | fifo_A_wen => sample_f0_A_wen, | |
278 |
|
246 | |||
279 | fifo_B_empty => sample_f0_B_empty, |
|
247 | fifo_B_empty => sample_f0_B_empty, | |
280 | fifo_B_full => sample_f0_B_full, |
|
248 | fifo_B_full => sample_f0_B_full, | |
281 | fifo_B_wen => sample_f0_B_wen, |
|
249 | fifo_B_wen => sample_f0_B_wen, | |
282 |
|
250 | |||
283 | error_wen => error_wen_f0); -- TODO |
|
251 | error_wen => error_wen_f0); -- TODO | |
284 |
|
252 | |||
285 | ----------------------------------------------------------------------------- |
|
253 | ----------------------------------------------------------------------------- | |
286 | -- FIFO IN |
|
254 | -- FIFO IN | |
287 | ----------------------------------------------------------------------------- |
|
255 | ----------------------------------------------------------------------------- | |
288 | lppFIFOxN_f0_a : lppFIFOxN |
|
256 | lppFIFOxN_f0_a : lppFIFOxN | |
289 | GENERIC MAP ( |
|
257 | GENERIC MAP ( | |
290 |
tech |
|
258 | tech => 0, | |
291 |
Mem_use |
|
259 | Mem_use => Mem_use, | |
292 |
Data_sz |
|
260 | Data_sz => 16, | |
293 |
Addr_sz |
|
261 | Addr_sz => 8, | |
294 |
FifoCnt |
|
262 | FifoCnt => 5) | |
295 | PORT MAP ( |
|
263 | PORT MAP ( | |
296 |
clk |
|
264 | clk => clk, | |
297 |
rstn |
|
265 | rstn => rstn, | |
298 |
|
266 | |||
299 | ReUse => (OTHERS => '0'), |
|
267 | ReUse => (OTHERS => '0'), | |
300 |
|
268 | |||
301 |
wen |
|
269 | wen => sample_f0_A_wen, | |
302 |
wdata |
|
270 | wdata => sample_f0_wdata, | |
303 |
|
271 | |||
304 |
ren |
|
272 | ren => sample_f0_A_ren, | |
305 |
rdata |
|
273 | rdata => sample_f0_A_rdata, | |
306 |
|
274 | |||
307 |
empty => sample_f0_A_empty, |
|
275 | empty => sample_f0_A_empty, | |
308 |
full => sample_f0_A_full, |
|
276 | full => sample_f0_A_full, | |
309 | almost_full => OPEN); |
|
277 | almost_full => OPEN); | |
310 |
|
278 | |||
311 | lppFIFOxN_f0_b : lppFIFOxN |
|
279 | lppFIFOxN_f0_b : lppFIFOxN | |
312 | GENERIC MAP ( |
|
280 | GENERIC MAP ( | |
313 |
tech |
|
281 | tech => 0, | |
314 |
Mem_use |
|
282 | Mem_use => Mem_use, | |
315 |
Data_sz |
|
283 | Data_sz => 16, | |
316 |
Addr_sz |
|
284 | Addr_sz => 8, | |
317 |
FifoCnt |
|
285 | FifoCnt => 5) | |
318 | PORT MAP ( |
|
286 | PORT MAP ( | |
319 |
clk |
|
287 | clk => clk, | |
320 |
rstn |
|
288 | rstn => rstn, | |
321 |
|
289 | |||
322 | ReUse => (OTHERS => '0'), |
|
290 | ReUse => (OTHERS => '0'), | |
323 |
|
291 | |||
324 |
wen => sample_f0_B_wen, |
|
292 | wen => sample_f0_B_wen, | |
325 |
wdata => sample_f0_wdata, |
|
293 | wdata => sample_f0_wdata, | |
326 |
ren => sample_f0_B_ren, |
|
294 | ren => sample_f0_B_ren, | |
327 |
rdata => sample_f0_B_rdata, |
|
295 | rdata => sample_f0_B_rdata, | |
328 |
empty => sample_f0_B_empty, |
|
296 | empty => sample_f0_B_empty, | |
329 |
full => sample_f0_B_full, |
|
297 | full => sample_f0_B_full, | |
330 | almost_full => OPEN); |
|
298 | almost_full => OPEN); | |
331 |
|
299 | |||
332 | lppFIFOxN_f1 : lppFIFOxN |
|
300 | lppFIFOxN_f1 : lppFIFOxN | |
333 | GENERIC MAP ( |
|
301 | GENERIC MAP ( | |
334 |
tech |
|
302 | tech => 0, | |
335 |
Mem_use |
|
303 | Mem_use => Mem_use, | |
336 |
Data_sz |
|
304 | Data_sz => 16, | |
337 |
Addr_sz |
|
305 | Addr_sz => 8, | |
338 |
FifoCnt |
|
306 | FifoCnt => 5) | |
339 | PORT MAP ( |
|
307 | PORT MAP ( | |
340 |
clk |
|
308 | clk => clk, | |
341 |
rstn |
|
309 | rstn => rstn, | |
342 |
|
310 | |||
343 | ReUse => (OTHERS => '0'), |
|
311 | ReUse => (OTHERS => '0'), | |
344 |
|
312 | |||
345 |
wen => sample_f1_wen, |
|
313 | wen => sample_f1_wen, | |
346 |
wdata => sample_f1_wdata, |
|
314 | wdata => sample_f1_wdata, | |
347 |
ren => sample_f1_ren, |
|
315 | ren => sample_f1_ren, | |
348 |
rdata => sample_f1_rdata, |
|
316 | rdata => sample_f1_rdata, | |
349 |
empty => sample_f1_empty, |
|
317 | empty => sample_f1_empty, | |
350 |
full => sample_f1_full, |
|
318 | full => sample_f1_full, | |
351 | almost_full => sample_f1_almost_full); |
|
319 | almost_full => sample_f1_almost_full); | |
352 |
|
320 | |||
353 |
|
321 | |||
354 | one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1'; |
|
322 | one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1'; | |
355 |
|
323 | |||
356 | PROCESS (clk, rstn) |
|
324 | PROCESS (clk, rstn) | |
357 | BEGIN -- PROCESS |
|
325 | BEGIN -- PROCESS | |
358 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
326 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
359 | one_sample_f1_full <= '0'; |
|
327 | one_sample_f1_full <= '0'; | |
360 | error_wen_f1 <= '0'; |
|
328 | error_wen_f1 <= '0'; | |
361 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
329 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
362 | IF sample_f1_full = "00000" THEN |
|
330 | IF sample_f1_full = "00000" THEN | |
363 | one_sample_f1_full <= '0'; |
|
331 | one_sample_f1_full <= '0'; | |
364 | ELSE |
|
332 | ELSE | |
365 | one_sample_f1_full <= '1'; |
|
333 | one_sample_f1_full <= '1'; | |
366 | END IF; |
|
334 | END IF; | |
367 | error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full; |
|
335 | error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full; | |
368 | END IF; |
|
336 | END IF; | |
369 | END PROCESS; |
|
337 | END PROCESS; | |
370 |
|
338 | |||
371 |
|
339 | |||
372 | lppFIFOxN_f2 : lppFIFOxN |
|
340 | lppFIFOxN_f2 : lppFIFOxN | |
373 | GENERIC MAP ( |
|
341 | GENERIC MAP ( | |
374 |
tech |
|
342 | tech => 0, | |
375 |
Mem_use |
|
343 | Mem_use => Mem_use, | |
376 |
Data_sz |
|
344 | Data_sz => 16, | |
377 |
Addr_sz |
|
345 | Addr_sz => 8, | |
378 |
FifoCnt |
|
346 | FifoCnt => 5) | |
379 | PORT MAP ( |
|
347 | PORT MAP ( | |
380 |
clk |
|
348 | clk => clk, | |
381 |
rstn |
|
349 | rstn => rstn, | |
382 |
|
350 | |||
383 | ReUse => (OTHERS => '0'), |
|
351 | ReUse => (OTHERS => '0'), | |
384 |
|
352 | |||
385 |
wen => sample_f2_wen, |
|
353 | wen => sample_f2_wen, | |
386 |
wdata => sample_f2_wdata, |
|
354 | wdata => sample_f2_wdata, | |
387 |
ren => sample_f2_ren, |
|
355 | ren => sample_f2_ren, | |
388 |
rdata => sample_f2_rdata, |
|
356 | rdata => sample_f2_rdata, | |
389 |
empty => sample_f2_empty, |
|
357 | empty => sample_f2_empty, | |
390 |
full => sample_f2_full, |
|
358 | full => sample_f2_full, | |
391 | almost_full => OPEN); |
|
359 | almost_full => OPEN); | |
392 |
|
360 | |||
393 |
|
361 | |||
394 | one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1'; |
|
362 | one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1'; | |
395 |
|
363 | |||
396 | PROCESS (clk, rstn) |
|
364 | PROCESS (clk, rstn) | |
397 | BEGIN -- PROCESS |
|
365 | BEGIN -- PROCESS | |
398 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
366 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
399 | one_sample_f2_full <= '0'; |
|
367 | one_sample_f2_full <= '0'; | |
400 | error_wen_f2 <= '0'; |
|
368 | error_wen_f2 <= '0'; | |
401 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
369 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
402 | IF sample_f2_full = "00000" THEN |
|
370 | IF sample_f2_full = "00000" THEN | |
403 | one_sample_f2_full <= '0'; |
|
371 | one_sample_f2_full <= '0'; | |
404 | ELSE |
|
372 | ELSE | |
405 | one_sample_f2_full <= '1'; |
|
373 | one_sample_f2_full <= '1'; | |
406 | END IF; |
|
374 | END IF; | |
407 | error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full; |
|
375 | error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full; | |
408 | END IF; |
|
376 | END IF; | |
409 | END PROCESS; |
|
377 | END PROCESS; | |
410 |
|
378 | |||
411 | ----------------------------------------------------------------------------- |
|
379 | ----------------------------------------------------------------------------- | |
412 | -- FSM SELECT CHANNEL |
|
380 | -- FSM SELECT CHANNEL | |
413 | ----------------------------------------------------------------------------- |
|
381 | ----------------------------------------------------------------------------- | |
414 | PROCESS (clk, rstn) |
|
382 | PROCESS (clk, rstn) | |
415 | BEGIN |
|
383 | BEGIN | |
416 | IF rstn = '0' THEN |
|
384 | IF rstn = '0' THEN | |
417 | state_fsm_select_channel <= IDLE; |
|
385 | state_fsm_select_channel <= IDLE; | |
418 | ELSIF clk'EVENT AND clk = '1' THEN |
|
386 | ELSIF clk'EVENT AND clk = '1' THEN | |
419 | CASE state_fsm_select_channel IS |
|
387 | CASE state_fsm_select_channel IS | |
420 | WHEN IDLE => |
|
388 | WHEN IDLE => | |
421 | IF sample_f1_full = "11111" THEN |
|
389 | IF sample_f1_full = "11111" THEN | |
422 | state_fsm_select_channel <= SWITCH_F1; |
|
390 | state_fsm_select_channel <= SWITCH_F1; | |
423 | ELSIF sample_f1_almost_full = "00000" THEN |
|
391 | ELSIF sample_f1_almost_full = "00000" THEN | |
424 | IF sample_f0_A_full = "11111" THEN |
|
392 | IF sample_f0_A_full = "11111" THEN | |
425 | state_fsm_select_channel <= SWITCH_F0_A; |
|
393 | state_fsm_select_channel <= SWITCH_F0_A; | |
426 | ELSIF sample_f0_B_full = "11111" THEN |
|
394 | ELSIF sample_f0_B_full = "11111" THEN | |
427 | state_fsm_select_channel <= SWITCH_F0_B; |
|
395 | state_fsm_select_channel <= SWITCH_F0_B; | |
428 | ELSIF sample_f2_full = "11111" THEN |
|
396 | ELSIF sample_f2_full = "11111" THEN | |
429 | state_fsm_select_channel <= SWITCH_F2; |
|
397 | state_fsm_select_channel <= SWITCH_F2; | |
430 | END IF; |
|
398 | END IF; | |
431 | END IF; |
|
399 | END IF; | |
432 |
|
400 | |||
433 | WHEN SWITCH_F0_A => |
|
401 | WHEN SWITCH_F0_A => | |
434 | IF sample_f0_A_empty = "11111" THEN |
|
402 | IF sample_f0_A_empty = "11111" THEN | |
435 | state_fsm_select_channel <= IDLE; |
|
403 | state_fsm_select_channel <= IDLE; | |
436 | END IF; |
|
404 | END IF; | |
437 | WHEN SWITCH_F0_B => |
|
405 | WHEN SWITCH_F0_B => | |
438 | IF sample_f0_B_empty = "11111" THEN |
|
406 | IF sample_f0_B_empty = "11111" THEN | |
439 | state_fsm_select_channel <= IDLE; |
|
407 | state_fsm_select_channel <= IDLE; | |
440 | END IF; |
|
408 | END IF; | |
441 | WHEN SWITCH_F1 => |
|
409 | WHEN SWITCH_F1 => | |
442 | IF sample_f1_empty = "11111" THEN |
|
410 | IF sample_f1_empty = "11111" THEN | |
443 | state_fsm_select_channel <= IDLE; |
|
411 | state_fsm_select_channel <= IDLE; | |
444 | END IF; |
|
412 | END IF; | |
445 | WHEN SWITCH_F2 => |
|
413 | WHEN SWITCH_F2 => | |
446 | IF sample_f2_empty = "11111" THEN |
|
414 | IF sample_f2_empty = "11111" THEN | |
447 | state_fsm_select_channel <= IDLE; |
|
415 | state_fsm_select_channel <= IDLE; | |
448 | END IF; |
|
416 | END IF; | |
449 | WHEN OTHERS => NULL; |
|
417 | WHEN OTHERS => NULL; | |
450 | END CASE; |
|
418 | END CASE; | |
451 |
|
419 | |||
452 | END IF; |
|
420 | END IF; | |
453 | END PROCESS; |
|
421 | END PROCESS; | |
454 |
|
422 | |||
455 | PROCESS (clk, rstn) |
|
423 | PROCESS (clk, rstn) | |
456 | BEGIN |
|
424 | BEGIN | |
457 | IF rstn = '0' THEN |
|
425 | IF rstn = '0' THEN | |
458 | pre_state_fsm_select_channel <= IDLE; |
|
426 | pre_state_fsm_select_channel <= IDLE; | |
459 | ELSIF clk'EVENT AND clk = '1' THEN |
|
427 | ELSIF clk'EVENT AND clk = '1' THEN | |
460 | pre_state_fsm_select_channel <= state_fsm_select_channel; |
|
428 | pre_state_fsm_select_channel <= state_fsm_select_channel; | |
461 | END IF; |
|
429 | END IF; | |
462 | END PROCESS; |
|
430 | END PROCESS; | |
463 |
|
431 | |||
464 |
|
432 | |||
465 | ----------------------------------------------------------------------------- |
|
433 | ----------------------------------------------------------------------------- | |
466 | -- SWITCH SELECT CHANNEL |
|
434 | -- SWITCH SELECT CHANNEL | |
467 | ----------------------------------------------------------------------------- |
|
435 | ----------------------------------------------------------------------------- | |
468 | sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
436 | sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE | |
469 | sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
437 | sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE | |
470 | sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
438 | sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE | |
471 | sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
439 | sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE | |
472 | (OTHERS => '1'); |
|
440 | (OTHERS => '1'); | |
473 |
|
441 | |||
474 | sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
442 | sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE | |
475 | sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
443 | sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE | |
476 | sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
444 | sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE | |
477 | sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
445 | sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE | |
478 | (OTHERS => '0'); |
|
446 | (OTHERS => '0'); | |
479 |
|
447 | |||
480 | sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE |
|
448 | sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE | |
481 | sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE |
|
449 | sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE | |
482 | sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE |
|
450 | sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE | |
483 | sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
451 | sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE | |
484 |
|
452 | |||
485 |
|
453 | |||
486 | sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1'); |
|
454 | sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1'); | |
487 | sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1'); |
|
455 | sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1'); | |
488 | sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1'); |
|
456 | sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1'); | |
489 | sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1'); |
|
457 | sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1'); | |
490 |
|
458 | |||
491 |
|
459 | |||
492 | status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
460 | status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE | |
493 | time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
461 | time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE | |
494 | time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
462 | time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE | |
495 | time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2 |
|
463 | time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2 | |
496 |
|
464 | |||
497 | ----------------------------------------------------------------------------- |
|
465 | ----------------------------------------------------------------------------- | |
498 | -- FSM LOAD FFT |
|
466 | -- FSM LOAD FFT | |
499 | ----------------------------------------------------------------------------- |
|
467 | ----------------------------------------------------------------------------- | |
500 |
|
468 | |||
501 | sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1'); |
|
469 | sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1'); | |
502 |
|
470 | |||
503 | PROCESS (clk, rstn) |
|
471 | PROCESS (clk, rstn) | |
504 | BEGIN |
|
472 | BEGIN | |
505 | IF rstn = '0' THEN |
|
473 | IF rstn = '0' THEN | |
506 | sample_ren_s <= (OTHERS => '1'); |
|
474 | sample_ren_s <= (OTHERS => '1'); | |
507 | state_fsm_load_FFT <= IDLE; |
|
475 | state_fsm_load_FFT <= IDLE; | |
508 | status_MS_input <= (OTHERS => '0'); |
|
476 | status_MS_input <= (OTHERS => '0'); | |
509 | --next_state_fsm_load_FFT <= IDLE; |
|
477 | --next_state_fsm_load_FFT <= IDLE; | |
510 | --sample_valid <= '0'; |
|
478 | --sample_valid <= '0'; | |
511 | ELSIF clk'EVENT AND clk = '1' THEN |
|
479 | ELSIF clk'EVENT AND clk = '1' THEN | |
512 | CASE state_fsm_load_FFT IS |
|
480 | CASE state_fsm_load_FFT IS | |
513 | WHEN IDLE => |
|
481 | WHEN IDLE => | |
514 | --sample_valid <= '0'; |
|
482 | --sample_valid <= '0'; | |
515 | sample_ren_s <= (OTHERS => '1'); |
|
483 | sample_ren_s <= (OTHERS => '1'); | |
516 | IF sample_full = "11111" AND sample_load = '1' THEN |
|
484 | IF sample_full = "11111" AND sample_load = '1' THEN | |
517 | state_fsm_load_FFT <= FIFO_1; |
|
485 | state_fsm_load_FFT <= FIFO_1; | |
518 | status_MS_input <= status_channel; |
|
486 | status_MS_input <= status_channel; | |
519 | END IF; |
|
487 | END IF; | |
520 |
|
488 | |||
521 | WHEN FIFO_1 => |
|
489 | WHEN FIFO_1 => | |
522 | sample_ren_s <= "1111" & NOT(sample_load); |
|
490 | sample_ren_s <= "1111" & NOT(sample_load); | |
523 | IF sample_empty(0) = '1' THEN |
|
491 | IF sample_empty(0) = '1' THEN | |
524 | sample_ren_s <= (OTHERS => '1'); |
|
492 | sample_ren_s <= (OTHERS => '1'); | |
525 | state_fsm_load_FFT <= FIFO_2; |
|
493 | state_fsm_load_FFT <= FIFO_2; | |
526 | END IF; |
|
494 | END IF; | |
527 |
|
495 | |||
528 | WHEN FIFO_2 => |
|
496 | WHEN FIFO_2 => | |
529 | sample_ren_s <= "111" & NOT(sample_load) & '1'; |
|
497 | sample_ren_s <= "111" & NOT(sample_load) & '1'; | |
530 | IF sample_empty(1) = '1' THEN |
|
498 | IF sample_empty(1) = '1' THEN | |
531 | sample_ren_s <= (OTHERS => '1'); |
|
499 | sample_ren_s <= (OTHERS => '1'); | |
532 | state_fsm_load_FFT <= FIFO_3; |
|
500 | state_fsm_load_FFT <= FIFO_3; | |
533 | END IF; |
|
501 | END IF; | |
534 |
|
502 | |||
535 | WHEN FIFO_3 => |
|
503 | WHEN FIFO_3 => | |
536 | sample_ren_s <= "11" & NOT(sample_load) & "11"; |
|
504 | sample_ren_s <= "11" & NOT(sample_load) & "11"; | |
537 | IF sample_empty(2) = '1' THEN |
|
505 | IF sample_empty(2) = '1' THEN | |
538 | sample_ren_s <= (OTHERS => '1'); |
|
506 | sample_ren_s <= (OTHERS => '1'); | |
539 | state_fsm_load_FFT <= FIFO_4; |
|
507 | state_fsm_load_FFT <= FIFO_4; | |
540 | END IF; |
|
508 | END IF; | |
541 |
|
509 | |||
542 | WHEN FIFO_4 => |
|
510 | WHEN FIFO_4 => | |
543 | sample_ren_s <= '1' & NOT(sample_load) & "111"; |
|
511 | sample_ren_s <= '1' & NOT(sample_load) & "111"; | |
544 | IF sample_empty(3) = '1' THEN |
|
512 | IF sample_empty(3) = '1' THEN | |
545 | sample_ren_s <= (OTHERS => '1'); |
|
513 | sample_ren_s <= (OTHERS => '1'); | |
546 | state_fsm_load_FFT <= FIFO_5; |
|
514 | state_fsm_load_FFT <= FIFO_5; | |
547 | END IF; |
|
515 | END IF; | |
548 |
|
516 | |||
549 | WHEN FIFO_5 => |
|
517 | WHEN FIFO_5 => | |
550 | sample_ren_s <= NOT(sample_load) & "1111"; |
|
518 | sample_ren_s <= NOT(sample_load) & "1111"; | |
551 | IF sample_empty(4) = '1' THEN |
|
519 | IF sample_empty(4) = '1' THEN | |
552 | sample_ren_s <= (OTHERS => '1'); |
|
520 | sample_ren_s <= (OTHERS => '1'); | |
553 | state_fsm_load_FFT <= IDLE; |
|
521 | state_fsm_load_FFT <= IDLE; | |
554 | END IF; |
|
522 | END IF; | |
555 | WHEN OTHERS => NULL; |
|
523 | WHEN OTHERS => NULL; | |
556 | END CASE; |
|
524 | END CASE; | |
557 | END IF; |
|
525 | END IF; | |
558 | END PROCESS; |
|
526 | END PROCESS; | |
559 |
|
527 | |||
560 | PROCESS (clk, rstn) |
|
528 | PROCESS (clk, rstn) | |
561 | BEGIN |
|
529 | BEGIN | |
562 | IF rstn = '0' THEN |
|
530 | IF rstn = '0' THEN | |
563 | sample_valid_r <= '0'; |
|
531 | sample_valid_r <= '0'; | |
564 | next_state_fsm_load_FFT <= IDLE; |
|
532 | next_state_fsm_load_FFT <= IDLE; | |
565 | ELSIF clk'EVENT AND clk = '1' THEN |
|
533 | ELSIF clk'EVENT AND clk = '1' THEN | |
566 | next_state_fsm_load_FFT <= state_fsm_load_FFT; |
|
534 | next_state_fsm_load_FFT <= state_fsm_load_FFT; | |
567 | IF sample_ren_s = "11111" THEN |
|
535 | IF sample_ren_s = "11111" THEN | |
568 | sample_valid_r <= '0'; |
|
536 | sample_valid_r <= '0'; | |
569 | ELSE |
|
537 | ELSE | |
570 | sample_valid_r <= '1'; |
|
538 | sample_valid_r <= '1'; | |
571 | END IF; |
|
539 | END IF; | |
572 | END IF; |
|
540 | END IF; | |
573 | END PROCESS; |
|
541 | END PROCESS; | |
574 |
|
542 | |||
575 | sample_valid <= sample_valid_r AND sample_load; |
|
543 | sample_valid <= sample_valid_r AND sample_load; | |
576 |
|
544 | |||
577 | sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE |
|
545 | sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE | |
578 | sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE |
|
546 | sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE | |
579 | sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE |
|
547 | sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE | |
580 | sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE |
|
548 | sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE | |
581 | sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE |
|
549 | sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE | |
582 |
|
550 | |||
583 | ----------------------------------------------------------------------------- |
|
551 | ----------------------------------------------------------------------------- | |
584 | -- FFT |
|
552 | -- FFT | |
585 | ----------------------------------------------------------------------------- |
|
553 | ----------------------------------------------------------------------------- | |
586 | lpp_lfr_ms_FFT_1: lpp_lfr_ms_FFT |
|
554 | lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT | |
587 | PORT MAP ( |
|
555 | PORT MAP ( | |
588 | clk => clk, |
|
556 | clk => clk, | |
589 | rstn => rstn, |
|
557 | rstn => rstn, | |
590 | sample_valid => sample_valid, |
|
558 | sample_valid => sample_valid, | |
591 | fft_read => fft_read, |
|
559 | fft_read => fft_read, | |
592 | sample_data => sample_data, |
|
560 | sample_data => sample_data, | |
593 | sample_load => sample_load, |
|
561 | sample_load => sample_load, | |
594 | fft_pong => fft_pong, |
|
562 | fft_pong => fft_pong, | |
595 | fft_data_im => fft_data_im, |
|
563 | fft_data_im => fft_data_im, | |
596 | fft_data_re => fft_data_re, |
|
564 | fft_data_re => fft_data_re, | |
597 | fft_data_valid => fft_data_valid, |
|
565 | fft_data_valid => fft_data_valid, | |
598 | fft_ready => fft_ready); |
|
566 | fft_ready => fft_ready); | |
599 |
|
567 | |||
600 | ----------------------------------------------------------------------------- |
|
568 | ----------------------------------------------------------------------------- | |
601 | -- in fft_data_im & fft_data_re |
|
|||
602 | -- in fft_data_valid |
|
|||
603 | -- in fft_ready |
|
|||
604 | -- out fft_read |
|
|||
605 | PROCESS (clk, rstn) |
|
569 | PROCESS (clk, rstn) | |
606 | BEGIN |
|
570 | BEGIN | |
607 | IF rstn = '0' THEN |
|
571 | IF rstn = '0' THEN | |
608 | state_fsm_load_MS_memory <= IDLE; |
|
572 | state_fsm_load_MS_memory <= IDLE; | |
609 | current_fifo_load <= "00001"; |
|
573 | current_fifo_load <= "00001"; | |
610 |
ELSIF clk' |
|
574 | ELSIF clk'EVENT AND clk = '1' THEN | |
611 | CASE state_fsm_load_MS_memory IS |
|
575 | CASE state_fsm_load_MS_memory IS | |
612 | WHEN IDLE => |
|
576 | WHEN IDLE => | |
613 | IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN |
|
577 | IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN | |
614 | state_fsm_load_MS_memory <= LOAD_FIFO; |
|
578 | state_fsm_load_MS_memory <= LOAD_FIFO; | |
615 | END IF; |
|
579 | END IF; | |
616 | WHEN LOAD_FIFO => |
|
580 | WHEN LOAD_FIFO => | |
617 | IF current_fifo_full = '1' THEN |
|
581 | IF current_fifo_full = '1' THEN | |
618 | state_fsm_load_MS_memory <= TRASH_FFT; |
|
582 | state_fsm_load_MS_memory <= TRASH_FFT; | |
619 | END IF; |
|
583 | END IF; | |
620 | WHEN TRASH_FFT => |
|
584 | WHEN TRASH_FFT => | |
621 | IF fft_ready = '0' THEN |
|
585 | IF fft_ready = '0' THEN | |
622 | state_fsm_load_MS_memory <= IDLE; |
|
586 | state_fsm_load_MS_memory <= IDLE; | |
623 | current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4); |
|
587 | current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4); | |
624 |
END IF; |
|
588 | END IF; | |
625 | WHEN OTHERS => NULL; |
|
589 | WHEN OTHERS => NULL; | |
626 | END CASE; |
|
590 | END CASE; | |
627 |
|
591 | |||
628 | END IF; |
|
592 | END IF; | |
629 | END PROCESS; |
|
593 | END PROCESS; | |
630 |
|
594 | |||
631 | current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE |
|
595 | current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE | |
632 | MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE |
|
596 | MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE | |
633 | MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE |
|
597 | MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE | |
634 | MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE |
|
598 | MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE | |
635 | MEM_IN_SM_Empty(4);-- WHEN current_fifo_load(3) = '1' ELSE |
|
599 | MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE | |
636 |
|
600 | |||
637 |
current_fifo_full |
|
601 | current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE | |
638 |
|
|
602 | MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE | |
639 |
|
|
603 | MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE | |
640 |
|
|
604 | MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE | |
641 |
|
|
605 | MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE | |
642 |
|
606 | |||
643 | current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE |
|
607 | current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE | |
644 | MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE |
|
608 | MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE | |
645 | MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE |
|
609 | MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE | |
646 | MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE |
|
610 | MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE | |
647 | MEM_IN_SM_locked(4);-- WHEN current_fifo_load(3) = '1' ELSE |
|
611 | MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE | |
648 |
|
612 | |||
649 | fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1'; |
|
613 | fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1'; | |
650 |
|
614 | |||
651 | all_fifo: FOR I IN 4 DOWNTO 0 GENERATE |
|
615 | all_fifo : FOR I IN 4 DOWNTO 0 GENERATE | |
652 |
|
|
616 | MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1' | |
653 |
|
|
617 | AND state_fsm_load_MS_memory = LOAD_FIFO | |
654 |
|
|
618 | AND current_fifo_load(I) = '1' | |
655 | ELSE '1'; |
|
619 | ELSE '1'; | |
656 | END GENERATE all_fifo; |
|
620 | END GENERATE all_fifo; | |
657 |
|
621 | |||
658 | PROCESS (clk, rstn) |
|
622 | PROCESS (clk, rstn) | |
659 | BEGIN |
|
623 | BEGIN | |
660 | IF rstn = '0' THEN |
|
624 | IF rstn = '0' THEN | |
661 | MEM_IN_SM_wen <= (OTHERS => '1'); |
|
625 | MEM_IN_SM_wen <= (OTHERS => '1'); | |
662 |
ELSIF clk' |
|
626 | ELSIF clk'EVENT AND clk = '1' THEN | |
663 |
MEM_IN_SM_wen <= MEM_IN_SM_wen_s; |
|
627 | MEM_IN_SM_wen <= MEM_IN_SM_wen_s; | |
664 | END IF; |
|
628 | END IF; | |
665 | END PROCESS; |
|
629 | END PROCESS; | |
666 |
|
630 | |||
667 | MEM_IN_SM_wData <= (fft_data_im & fft_data_re) & |
|
631 | MEM_IN_SM_wData <= (fft_data_im & fft_data_re) & | |
668 | (fft_data_im & fft_data_re) & |
|
632 | (fft_data_im & fft_data_re) & | |
669 | (fft_data_im & fft_data_re) & |
|
633 | (fft_data_im & fft_data_re) & | |
670 | (fft_data_im & fft_data_re) & |
|
634 | (fft_data_im & fft_data_re) & | |
671 | (fft_data_im & fft_data_re); |
|
635 | (fft_data_im & fft_data_re); | |
672 |
|
||||
673 |
|
636 | |||
674 | -- out SM_MEM_IN_wData |
|
|||
675 | -- out SM_MEM_IN_wen |
|
|||
676 | -- out SM_MEM_IN_Full |
|
|||
677 |
|
||||
678 | -- out SM_MEM_IN_locked |
|
|||
679 | ----------------------------------------------------------------------------- |
|
|||
680 | ----------------------------------------------------------------------------- |
|
|||
681 | ----------------------------------------------------------------------------- |
|
|||
682 | ----------------------------------------------------------------------------- |
|
|||
683 | --Linker_FFT_1 : Linker_FFT |
|
|||
684 | -- GENERIC MAP ( |
|
|||
685 | -- Data_sz => 16, |
|
|||
686 | -- NbData => 256) |
|
|||
687 | -- PORT MAP ( |
|
|||
688 | -- clk => clk, |
|
|||
689 | -- rstn => rstn, |
|
|||
690 |
|
||||
691 | -- Ready => fft_ready, |
|
|||
692 | -- Valid => fft_data_valid, |
|
|||
693 |
|
||||
694 | -- Full => MEM_IN_SM_Full, |
|
|||
695 |
|
||||
696 | -- Data_re => fft_data_re, |
|
|||
697 | -- Data_im => fft_data_im, |
|
|||
698 | -- Read => fft_read, |
|
|||
699 |
|
||||
700 | -- Write => MEM_IN_SM_wen, |
|
|||
701 | -- ReUse => fft_linker_ReUse, |
|
|||
702 | -- DATA => MEM_IN_SM_wData); |
|
|||
703 |
|
||||
704 | ----------------------------------------------------------------------------- |
|
637 | ----------------------------------------------------------------------------- | |
705 | Mem_In_SpectralMatrix : lppFIFOxN |
|
638 | Mem_In_SpectralMatrix : lppFIFOxN | |
706 | GENERIC MAP ( |
|
639 | GENERIC MAP ( | |
707 |
tech |
|
640 | tech => 0, | |
708 |
Mem_use |
|
641 | Mem_use => Mem_use, | |
709 |
Data_sz |
|
642 | Data_sz => 32, --16, | |
710 |
Addr_sz |
|
643 | Addr_sz => 7, --8 | |
711 |
FifoCnt |
|
644 | FifoCnt => 5) | |
712 | PORT MAP ( |
|
645 | PORT MAP ( | |
713 | clk => clk, |
|
646 | clk => clk, | |
714 | rstn => rstn, |
|
647 | rstn => rstn, | |
715 |
|
648 | |||
716 | ReUse => MEM_IN_SM_ReUse, |
|
649 | ReUse => MEM_IN_SM_ReUse, | |
717 |
|
650 | |||
718 | wen => MEM_IN_SM_wen, |
|
651 | wen => MEM_IN_SM_wen, | |
719 | wdata => MEM_IN_SM_wData, |
|
652 | wdata => MEM_IN_SM_wData, | |
720 |
|
653 | |||
721 | ren => MEM_IN_SM_ren, |
|
654 | ren => MEM_IN_SM_ren, | |
722 | rdata => MEM_IN_SM_rData, |
|
655 | rdata => MEM_IN_SM_rData, | |
723 | full => MEM_IN_SM_Full, |
|
656 | full => MEM_IN_SM_Full, | |
724 |
empty => MEM_IN_SM_Empty, |
|
657 | empty => MEM_IN_SM_Empty, | |
725 | almost_full => OPEN); |
|
658 | almost_full => OPEN); | |
726 |
|
659 | |||
727 |
|
||||
728 | --all_lock: FOR I IN 4 DOWNTO 0 GENERATE |
|
|||
729 | -- PROCESS (clk, rstn) |
|
|||
730 | -- BEGIN |
|
|||
731 | -- IF rstn = '0' THEN |
|
|||
732 | -- MEM_IN_SM_locked(I) <= '0'; |
|
|||
733 | -- ELSIF clk'event AND clk = '1' THEN |
|
|||
734 | -- MEM_IN_SM_locked(I) <= MEM_IN_SM_Full(I) OR MEM_IN_SM_locked(I); -- TODO |
|
|||
735 | -- END IF; |
|
|||
736 | -- END PROCESS; |
|
|||
737 | --END GENERATE all_lock; |
|
|||
738 |
|
||||
739 | ----------------------------------------------------------------------------- |
|
660 | ----------------------------------------------------------------------------- | |
740 | MS_control_1: MS_control |
|
661 | MS_control_1 : MS_control | |
741 | PORT MAP ( |
|
662 | PORT MAP ( | |
742 |
clk |
|
663 | clk => clk, | |
743 |
rstn |
|
664 | rstn => rstn, | |
744 |
|
665 | |||
745 | current_status_ms => status_MS_input, |
|
666 | current_status_ms => status_MS_input, | |
746 |
|
667 | |||
747 |
fifo_in_lock |
|
668 | fifo_in_lock => MEM_IN_SM_locked, | |
748 |
fifo_in_data |
|
669 | fifo_in_data => MEM_IN_SM_rdata, | |
749 |
fifo_in_full |
|
670 | fifo_in_full => MEM_IN_SM_Full, | |
750 |
fifo_in_empty |
|
671 | fifo_in_empty => MEM_IN_SM_Empty, | |
751 |
fifo_in_ren |
|
672 | fifo_in_ren => MEM_IN_SM_ren, | |
752 |
fifo_in_reuse |
|
673 | fifo_in_reuse => MEM_IN_SM_ReUse, | |
753 |
|
674 | |||
754 |
fifo_out_data |
|
675 | fifo_out_data => SM_in_data, | |
755 |
fifo_out_ren |
|
676 | fifo_out_ren => SM_in_ren, | |
756 |
fifo_out_empty |
|
677 | fifo_out_empty => SM_in_empty, | |
757 |
|
678 | |||
758 | current_status_component => status_component, |
|
679 | current_status_component => status_component, | |
759 |
|
680 | |||
760 | correlation_start => SM_correlation_start, |
|
681 | correlation_start => SM_correlation_start, | |
761 | correlation_auto => SM_correlation_auto, |
|
682 | correlation_auto => SM_correlation_auto, | |
762 | correlation_done => SM_correlation_done); |
|
683 | correlation_done => SM_correlation_done); | |
763 |
|
684 | |||
764 |
|
685 | |||
765 | MS_calculation_1: MS_calculation |
|
686 | MS_calculation_1 : MS_calculation | |
766 | PORT MAP ( |
|
687 | PORT MAP ( | |
767 |
clk |
|
688 | clk => clk, | |
768 |
rstn |
|
689 | rstn => rstn, | |
769 |
|
690 | |||
770 |
fifo_in_data |
|
691 | fifo_in_data => SM_in_data, | |
771 |
fifo_in_ren |
|
692 | fifo_in_ren => SM_in_ren, | |
772 |
fifo_in_empty |
|
693 | fifo_in_empty => SM_in_empty, | |
773 |
|
694 | |||
774 |
fifo_out_data |
|
695 | fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO | |
775 |
fifo_out_wen |
|
696 | fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO | |
776 |
fifo_out_full |
|
697 | fifo_out_full => MEM_OUT_SM_Full_s, -- TODO | |
777 |
|
698 | |||
778 | correlation_start => SM_correlation_start, |
|
699 | correlation_start => SM_correlation_start, | |
779 | correlation_auto => SM_correlation_auto, |
|
700 | correlation_auto => SM_correlation_auto, | |
780 | correlation_begin => SM_correlation_begin, |
|
701 | correlation_begin => SM_correlation_begin, | |
781 | correlation_done => SM_correlation_done); |
|
702 | correlation_done => SM_correlation_done); | |
782 |
|
703 | |||
783 | ----------------------------------------------------------------------------- |
|
704 | ----------------------------------------------------------------------------- | |
784 | PROCESS (clk, rstn) |
|
705 | PROCESS (clk, rstn) | |
785 | BEGIN -- PROCESS |
|
706 | BEGIN -- PROCESS | |
786 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
707 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
787 | current_matrix_write <= '0'; |
|
708 | current_matrix_write <= '0'; | |
788 | current_matrix_wait_empty <= '1'; |
|
709 | current_matrix_wait_empty <= '1'; | |
789 | status_component_fifo_0 <= (OTHERS => '0'); |
|
710 | status_component_fifo_0 <= (OTHERS => '0'); | |
790 | status_component_fifo_1 <= (OTHERS => '0'); |
|
711 | status_component_fifo_1 <= (OTHERS => '0'); | |
791 | -- status_component_fifo_0_new <= '0'; |
|
|||
792 | -- status_component_fifo_1_new <= '0'; |
|
|||
793 | status_component_fifo_0_end <= '0'; |
|
712 | status_component_fifo_0_end <= '0'; | |
794 | status_component_fifo_1_end <= '0'; |
|
713 | status_component_fifo_1_end <= '0'; | |
795 | SM_correlation_done_reg1 <= '0'; |
|
714 | SM_correlation_done_reg1 <= '0'; | |
796 | SM_correlation_done_reg2 <= '0'; |
|
715 | SM_correlation_done_reg2 <= '0'; | |
797 | SM_correlation_done_reg3 <= '0'; |
|
716 | SM_correlation_done_reg3 <= '0'; | |
798 |
|
717 | |||
799 |
ELSIF clk' |
|
718 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
800 | SM_correlation_done_reg1 <= SM_correlation_done; |
|
719 | SM_correlation_done_reg1 <= SM_correlation_done; | |
801 | SM_correlation_done_reg2 <= SM_correlation_done_reg1; |
|
720 | SM_correlation_done_reg2 <= SM_correlation_done_reg1; | |
802 | SM_correlation_done_reg3 <= SM_correlation_done_reg2; |
|
721 | SM_correlation_done_reg3 <= SM_correlation_done_reg2; | |
803 |
|
||||
804 | -- status_component_fifo_0_new <= '0'; |
|
|||
805 | -- status_component_fifo_1_new <= '0'; |
|
|||
806 | status_component_fifo_0_end <= '0'; |
|
722 | status_component_fifo_0_end <= '0'; | |
807 | status_component_fifo_1_end <= '0'; |
|
723 | status_component_fifo_1_end <= '0'; | |
808 |
|
||||
809 |
|
||||
810 |
|
||||
811 | IF SM_correlation_begin = '1' THEN |
|
724 | IF SM_correlation_begin = '1' THEN | |
812 | IF current_matrix_write = '0' THEN |
|
725 | IF current_matrix_write = '0' THEN | |
813 |
|
|
726 | status_component_fifo_0 <= status_component; | |
814 | status_component_fifo_0 <= status_component; |
|
|||
815 | ELSE |
|
727 | ELSE | |
816 |
|
|
728 | status_component_fifo_1 <= status_component; | |
817 | status_component_fifo_1 <= status_component; |
|
|||
818 | END IF; |
|
729 | END IF; | |
819 | END IF; |
|
730 | END IF; | |
820 |
|
731 | |||
821 | IF SM_correlation_done_reg3 = '1' THEN |
|
732 | IF SM_correlation_done_reg3 = '1' THEN | |
822 | IF current_matrix_write = '0' THEN |
|
733 | IF current_matrix_write = '0' THEN | |
823 |
status_component_fifo_0_end |
|
734 | status_component_fifo_0_end <= '1'; | |
824 | ELSE |
|
735 | ELSE | |
825 |
status_component_fifo_1_end |
|
736 | status_component_fifo_1_end <= '1'; | |
826 | END IF; |
|
737 | END IF; | |
827 | current_matrix_wait_empty <= '1'; |
|
738 | current_matrix_wait_empty <= '1'; | |
828 | current_matrix_write <= NOT current_matrix_write; |
|
739 | current_matrix_write <= NOT current_matrix_write; | |
829 | END IF; |
|
740 | END IF; | |
830 |
|
741 | |||
831 | IF current_matrix_wait_empty <= '1' THEN |
|
742 | IF current_matrix_wait_empty <= '1' THEN | |
832 | IF current_matrix_write = '0' THEN |
|
743 | IF current_matrix_write = '0' THEN | |
833 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0); |
|
744 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0); | |
834 | ELSE |
|
745 | ELSE | |
835 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1); |
|
746 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1); | |
836 | END IF; |
|
747 | END IF; | |
837 | END IF; |
|
748 | END IF; | |
838 |
|
749 | |||
839 | END IF; |
|
750 | END IF; | |
840 | END PROCESS; |
|
751 | END PROCESS; | |
841 |
|
752 | |||
842 |
MEM_OUT_SM_Full_s <= '1' |
|
753 | MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE | |
843 | '1' WHEN SM_correlation_done_reg1 = '1' ELSE |
|
754 | '1' WHEN SM_correlation_done_reg1 = '1' ELSE | |
844 | '1' WHEN SM_correlation_done_reg2 = '1' ELSE |
|
755 | '1' WHEN SM_correlation_done_reg2 = '1' ELSE | |
845 | '1' WHEN SM_correlation_done_reg3 = '1' ELSE |
|
756 | '1' WHEN SM_correlation_done_reg3 = '1' ELSE | |
846 | '1' WHEN current_matrix_wait_empty = '1' ELSE |
|
757 | '1' WHEN current_matrix_wait_empty = '1' ELSE | |
847 | MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE |
|
758 | MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE | |
848 | MEM_OUT_SM_Full(1); |
|
759 | MEM_OUT_SM_Full(1); | |
849 |
|
760 | |||
850 | MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1'; |
|
761 | MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1'; | |
851 | MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1'; |
|
762 | MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1'; | |
852 |
|
763 | |||
853 |
MEM_OUT_SM_Data_in |
|
764 | MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s; | |
854 | ----------------------------------------------------------------------------- |
|
765 | ----------------------------------------------------------------------------- | |
855 |
|
766 | |||
856 | Mem_Out_SpectralMatrix : lppFIFOxN |
|
767 | Mem_Out_SpectralMatrix : lppFIFOxN | |
857 | GENERIC MAP ( |
|
768 | GENERIC MAP ( | |
858 |
tech |
|
769 | tech => 0, | |
859 |
Mem_use |
|
770 | Mem_use => Mem_use, | |
860 |
Data_sz |
|
771 | Data_sz => 32, | |
861 |
Addr_sz |
|
772 | Addr_sz => 8, | |
862 |
FifoCnt |
|
773 | FifoCnt => 2) | |
863 | PORT MAP ( |
|
774 | PORT MAP ( | |
864 | clk => clk, |
|
775 | clk => clk, | |
865 | rstn => rstn, |
|
776 | rstn => rstn, | |
866 |
|
777 | |||
867 | ReUse => (OTHERS => '0'), |
|
778 | ReUse => (OTHERS => '0'), | |
868 |
|
779 | |||
869 | wen => MEM_OUT_SM_Write, |
|
780 | wen => MEM_OUT_SM_Write, | |
870 | wdata => MEM_OUT_SM_Data_in, |
|
781 | wdata => MEM_OUT_SM_Data_in, | |
871 |
|
782 | |||
872 | ren => MEM_OUT_SM_Read, |
|
783 | ren => MEM_OUT_SM_Read, | |
873 | rdata => MEM_OUT_SM_Data_out, |
|
784 | rdata => MEM_OUT_SM_Data_out, | |
874 |
|
785 | |||
875 | full => MEM_OUT_SM_Full, |
|
786 | full => MEM_OUT_SM_Full, | |
876 | empty => MEM_OUT_SM_Empty, |
|
787 | empty => MEM_OUT_SM_Empty, | |
877 | almost_full => OPEN); |
|
788 | almost_full => OPEN); | |
878 |
|
789 | |||
879 | ----------------------------------------------------------------------------- |
|
790 | ----------------------------------------------------------------------------- | |
880 | -- MEM_OUT_SM_Read <= "00"; |
|
791 | -- MEM_OUT_SM_Read <= "00"; | |
881 | PROCESS (clk, rstn) |
|
792 | PROCESS (clk, rstn) | |
882 |
BEGIN |
|
793 | BEGIN | |
883 |
IF rstn = '0' THEN |
|
794 | IF rstn = '0' THEN | |
884 | fifo_0_ready <= '0'; |
|
795 | fifo_0_ready <= '0'; | |
885 | fifo_1_ready <= '0'; |
|
796 | fifo_1_ready <= '0'; | |
886 | fifo_ongoing <= '0'; |
|
797 | fifo_ongoing <= '0'; | |
887 |
ELSIF clk' |
|
798 | ELSIF clk'EVENT AND clk = '1' THEN | |
888 | IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN |
|
799 | IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN | |
889 |
fifo_ongoing <= '1'; |
|
800 | fifo_ongoing <= '1'; | |
890 | fifo_0_ready <= '0'; |
|
801 | fifo_0_ready <= '0'; | |
891 | ELSIF status_component_fifo_0_end = '1' THEN |
|
802 | ELSIF status_component_fifo_0_end = '1' THEN | |
892 |
fifo_0_ready <= '1'; |
|
803 | fifo_0_ready <= '1'; | |
893 | END IF; |
|
804 | END IF; | |
894 |
|
805 | |||
895 | IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN |
|
806 | IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN | |
896 | fifo_ongoing <= '0'; |
|
807 | fifo_ongoing <= '0'; | |
897 | fifo_1_ready <= '0'; |
|
808 | fifo_1_ready <= '0'; | |
898 | ELSIF status_component_fifo_1_end = '1' THEN |
|
809 | ELSIF status_component_fifo_1_end = '1' THEN | |
899 |
fifo_1_ready <= '1'; |
|
810 | fifo_1_ready <= '1'; | |
900 | END IF; |
|
811 | END IF; | |
901 |
|
812 | |||
902 | END IF; |
|
813 | END IF; | |
903 | END PROCESS; |
|
814 | END PROCESS; | |
904 |
|
815 | |||
905 | MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE |
|
816 | MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE | |
906 | '1' WHEN fifo_0_ready = '0' ELSE |
|
817 | '1' WHEN fifo_0_ready = '0' ELSE | |
907 | FSM_DMA_fifo_ren; |
|
818 | FSM_DMA_fifo_ren; | |
908 |
|
819 | |||
909 | MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE |
|
820 | MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE | |
910 | '1' WHEN fifo_1_ready = '0' ELSE |
|
821 | '1' WHEN fifo_1_ready = '0' ELSE | |
911 | FSM_DMA_fifo_ren; |
|
822 | FSM_DMA_fifo_ren; | |
912 |
|
823 | |||
913 |
FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) |
|
824 | FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE | |
914 |
MEM_OUT_SM_Empty(1) |
|
825 | MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE | |
915 | '1'; |
|
826 | '1'; | |
916 |
|
827 | |||
917 |
FSM_DMA_fifo_status <= |
|
828 | FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE | |
918 |
|
|
829 | status_component_fifo_1; | |
919 |
|
830 | |||
920 |
FSM_DMA_fifo_data |
|
831 | FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE | |
921 |
|
|
832 | MEM_OUT_SM_Data_out(63 DOWNTO 32); | |
922 |
|
833 | |||
923 | ----------------------------------------------------------------------------- |
|
834 | ----------------------------------------------------------------------------- | |
924 | lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma |
|
835 | lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma | |
925 | PORT MAP ( |
|
836 | PORT MAP ( | |
926 | HCLK => clk, |
|
837 | HCLK => clk, | |
927 | HRESETn => rstn, |
|
838 | HRESETn => rstn, | |
928 |
|
839 | |||
929 |
fifo_matrix_type => FSM_DMA_fifo_status( |
|
840 | fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), | |
930 |
fifo_matrix_component => FSM_DMA_fifo_status( |
|
841 | fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), | |
931 | fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), |
|
842 | fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), | |
932 | fifo_data => FSM_DMA_fifo_data, |
|
843 | fifo_data => FSM_DMA_fifo_data, | |
933 | fifo_empty => FSM_DMA_fifo_empty, |
|
844 | fifo_empty => FSM_DMA_fifo_empty, | |
934 | fifo_ren => FSM_DMA_fifo_ren, |
|
845 | fifo_ren => FSM_DMA_fifo_ren, | |
935 |
|
||||
936 | ---- FIFO IN |
|
|||
937 | --data_time => dma_time, |
|
|||
938 |
|
||||
939 | --fifo_data => HEAD_Data, |
|
|||
940 | --fifo_empty => HEAD_Empty, |
|
|||
941 | --fifo_ren => HEAD_Read, |
|
|||
942 |
|
||||
943 | --header => DMA_Header, |
|
|||
944 | --header_val => DMA_Header_Val, |
|
|||
945 | --header_ack => DMA_Header_Ack, |
|
|||
946 |
|
846 | |||
947 | dma_addr => dma_addr, |
|
847 | dma_addr => dma_addr, | |
948 | dma_data => dma_data, |
|
848 | dma_data => dma_data, | |
949 | dma_valid => dma_valid, |
|
849 | dma_valid => dma_valid, | |
950 | dma_valid_burst => dma_valid_burst, |
|
850 | dma_valid_burst => dma_valid_burst, | |
951 | dma_ren => dma_ren, |
|
851 | dma_ren => dma_ren, | |
952 | dma_done => dma_done, |
|
852 | dma_done => dma_done, | |
953 |
|
853 | |||
954 |
ready_matrix_f0 |
|
854 | ready_matrix_f0 => ready_matrix_f0, | |
955 |
|
|
855 | ready_matrix_f1 => ready_matrix_f1, | |
956 |
ready_matrix_f |
|
856 | ready_matrix_f2 => ready_matrix_f2, | |
957 | ready_matrix_f2 => ready_matrix_f2, |
|
857 | ||
958 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
858 | error_bad_component_error => error_bad_component_error, | |
959 | error_bad_component_error => error_bad_component_error, |
|
859 | error_buffer_full => error_buffer_full, | |
960 | error_buffer_full => error_buffer_full, |
|
860 | ||
961 |
debug_reg |
|
861 | debug_reg => debug_reg, | |
962 |
status_ready_matrix_f0 |
|
862 | status_ready_matrix_f0 => status_ready_matrix_f0, | |
963 |
|
|
863 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
964 |
status_ready_matrix_f |
|
864 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
965 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
865 | ||
966 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
|||
967 | -- status_error_bad_component_error => status_error_bad_component_error, |
|
|||
968 | -- status_error_buffer_full => status_error_buffer_full, |
|
|||
969 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
866 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
970 | config_active_interruption_onError => config_active_interruption_onError, |
|
867 | config_active_interruption_onError => config_active_interruption_onError, | |
971 | addr_matrix_f0 => addr_matrix_f0, |
|
868 | ||
972 |
|
|
869 | addr_matrix_f0 => addr_matrix_f0, | |
973 |
addr_matrix_f1 |
|
870 | addr_matrix_f1 => addr_matrix_f1, | |
974 |
addr_matrix_f2 |
|
871 | addr_matrix_f2 => addr_matrix_f2, | |
975 |
|
872 | |||
976 | matrix_time_f0 => matrix_time_f0, |
|
873 | matrix_time_f0 => matrix_time_f0, | |
977 |
|
|
874 | matrix_time_f1 => matrix_time_f1, | |
978 |
matrix_time_f |
|
875 | matrix_time_f2 => matrix_time_f2 | |
979 | matrix_time_f2 => matrix_time_f2 |
|
|||
980 | ); |
|
876 | ); | |
981 | ----------------------------------------------------------------------------- |
|
877 | ----------------------------------------------------------------------------- | |
982 |
|
878 | |||
983 |
|
879 | |||
984 |
|
880 | |||
985 |
|
881 | |||
986 |
|
882 | |||
987 |
|
||||
988 |
|
||||
989 |
|
||||
990 |
|
||||
991 |
|
||||
992 |
|
||||
993 | ----------------------------------------------------------------------------- |
|
|||
994 | ----------------------------------------------------------------------------- |
|
|||
995 | ----------------------------------------------------------------------------- |
|
|||
996 | ----------------------------------------------------------------------------- |
|
|||
997 | ----------------------------------------------------------------------------- |
|
|||
998 | ----------------------------------------------------------------------------- |
|
|||
999 |
|
||||
1000 |
|
||||
1001 |
|
||||
1002 |
|
||||
1003 |
|
||||
1004 |
|
||||
1005 | ----------------------------------------------------------------------------- |
|
883 | ----------------------------------------------------------------------------- | |
1006 | -- TIME MANAGMENT |
|
884 | -- TIME MANAGMENT | |
1007 | ----------------------------------------------------------------------------- |
|
885 | ----------------------------------------------------------------------------- | |
1008 | all_time <= coarse_time & fine_time; |
|
886 | all_time <= coarse_time & fine_time; | |
1009 | -- |
|
887 | -- | |
1010 | time_update_f0_A <= '0' WHEN sample_f0_A_wen = "11111" ELSE |
|
888 | time_update_f0_A <= '0' WHEN sample_f0_A_wen = "11111" ELSE | |
1011 | '1' WHEN sample_f0_A_empty = "11111" ELSE |
|
889 | '1' WHEN sample_f0_A_empty = "11111" ELSE | |
1012 | '0'; |
|
890 | '0'; | |
1013 |
|
891 | |||
1014 | s_m_t_m_f0_A : spectral_matrix_time_managment |
|
892 | s_m_t_m_f0_A : spectral_matrix_time_managment | |
1015 | PORT MAP ( |
|
893 | PORT MAP ( | |
1016 | clk => clk, |
|
894 | clk => clk, | |
1017 | rstn => rstn, |
|
895 | rstn => rstn, | |
1018 | time_in => all_time, |
|
896 | time_in => all_time, | |
1019 | update_1 => time_update_f0_A, |
|
897 | update_1 => time_update_f0_A, | |
1020 | time_out => time_reg_f0_A); |
|
898 | time_out => time_reg_f0_A); | |
1021 |
|
899 | |||
1022 | -- |
|
900 | -- | |
1023 | time_update_f0_B <= '0' WHEN sample_f0_B_wen = "11111" ELSE |
|
901 | time_update_f0_B <= '0' WHEN sample_f0_B_wen = "11111" ELSE | |
1024 | '1' WHEN sample_f0_B_empty = "11111" ELSE |
|
902 | '1' WHEN sample_f0_B_empty = "11111" ELSE | |
1025 | '0'; |
|
903 | '0'; | |
1026 |
|
904 | |||
1027 | s_m_t_m_f0_B : spectral_matrix_time_managment |
|
905 | s_m_t_m_f0_B : spectral_matrix_time_managment | |
1028 | PORT MAP ( |
|
906 | PORT MAP ( | |
1029 | clk => clk, |
|
907 | clk => clk, | |
1030 | rstn => rstn, |
|
908 | rstn => rstn, | |
1031 | time_in => all_time, |
|
909 | time_in => all_time, | |
1032 | update_1 => time_update_f0_B, |
|
910 | update_1 => time_update_f0_B, | |
1033 | time_out => time_reg_f0_B); |
|
911 | time_out => time_reg_f0_B); | |
1034 |
|
912 | |||
1035 | -- |
|
913 | -- | |
1036 | time_update_f1 <= '0' WHEN sample_f1_wen = "11111" ELSE |
|
914 | time_update_f1 <= '0' WHEN sample_f1_wen = "11111" ELSE | |
1037 | '1' WHEN sample_f1_empty = "11111" ELSE |
|
915 | '1' WHEN sample_f1_empty = "11111" ELSE | |
1038 | '0'; |
|
916 | '0'; | |
1039 |
|
917 | |||
1040 | s_m_t_m_f1 : spectral_matrix_time_managment |
|
918 | s_m_t_m_f1 : spectral_matrix_time_managment | |
1041 | PORT MAP ( |
|
919 | PORT MAP ( | |
1042 | clk => clk, |
|
920 | clk => clk, | |
1043 | rstn => rstn, |
|
921 | rstn => rstn, | |
1044 | time_in => all_time, |
|
922 | time_in => all_time, | |
1045 | update_1 => time_update_f1, |
|
923 | update_1 => time_update_f1, | |
1046 | time_out => time_reg_f1); |
|
924 | time_out => time_reg_f1); | |
1047 |
|
925 | |||
1048 | -- |
|
926 | -- | |
1049 | time_update_f2 <= '0' WHEN sample_f2_wen = "11111" ELSE |
|
927 | time_update_f2 <= '0' WHEN sample_f2_wen = "11111" ELSE | |
1050 | '1' WHEN sample_f2_empty = "11111" ELSE |
|
928 | '1' WHEN sample_f2_empty = "11111" ELSE | |
1051 | '0'; |
|
929 | '0'; | |
1052 |
|
930 | |||
1053 | s_m_t_m_f2 : spectral_matrix_time_managment |
|
931 | s_m_t_m_f2 : spectral_matrix_time_managment | |
1054 | PORT MAP ( |
|
932 | PORT MAP ( | |
1055 | clk => clk, |
|
933 | clk => clk, | |
1056 | rstn => rstn, |
|
934 | rstn => rstn, | |
1057 | time_in => all_time, |
|
935 | time_in => all_time, | |
1058 | update_1 => time_update_f2, |
|
936 | update_1 => time_update_f2, | |
1059 | time_out => time_reg_f2); |
|
937 | time_out => time_reg_f2); | |
1060 |
|
938 | |||
1061 | ----------------------------------------------------------------------------- |
|
939 | ----------------------------------------------------------------------------- | |
1062 | dma_time <= (OTHERS => '0'); -- TODO |
|
|||
1063 | ----------------------------------------------------------------------------- |
|
|||
1064 |
|
940 | |||
1065 |
|
941 | |||
1066 |
|
942 | |||
1067 | END Behavioral; |
|
943 | END Behavioral; |
@@ -1,296 +1,295 | |||||
1 |
|
1 | |||
2 | ------------------------------------------------------------------------------ |
|
2 | ------------------------------------------------------------------------------ | |
3 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | -- This file is a part of the LPP VHDL IP LIBRARY | |
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
5 | -- |
|
5 | -- | |
6 | -- This program is free software; you can redistribute it and/or modify |
|
6 | -- This program is free software; you can redistribute it and/or modify | |
7 | -- it under the terms of the GNU General Public License as published by |
|
7 | -- it under the terms of the GNU General Public License as published by | |
8 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | -- the Free Software Foundation; either version 3 of the License, or | |
9 | -- (at your option) any later version. |
|
9 | -- (at your option) any later version. | |
10 | -- |
|
10 | -- | |
11 | -- This program is distributed in the hope that it will be useful, |
|
11 | -- This program is distributed in the hope that it will be useful, | |
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | -- GNU General Public License for more details. |
|
14 | -- GNU General Public License for more details. | |
15 | -- |
|
15 | -- | |
16 | -- You should have received a copy of the GNU General Public License |
|
16 | -- You should have received a copy of the GNU General Public License | |
17 | -- along with this program; if not, write to the Free Software |
|
17 | -- along with this program; if not, write to the Free Software | |
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | ------------------------------------------------------------------------------- |
|
19 | ------------------------------------------------------------------------------- | |
20 | -- Author : Jean-christophe Pellion |
|
20 | -- Author : Jean-christophe Pellion | |
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
22 | -- jean-christophe.pellion@easii-ic.com |
|
22 | -- jean-christophe.pellion@easii-ic.com | |
23 | ------------------------------------------------------------------------------- |
|
23 | ------------------------------------------------------------------------------- | |
24 | LIBRARY ieee; |
|
24 | LIBRARY ieee; | |
25 | USE ieee.std_logic_1164.ALL; |
|
25 | USE ieee.std_logic_1164.ALL; | |
26 | USE ieee.numeric_std.ALL; |
|
26 | USE ieee.numeric_std.ALL; | |
27 | LIBRARY grlib; |
|
27 | LIBRARY grlib; | |
28 | USE grlib.amba.ALL; |
|
28 | USE grlib.amba.ALL; | |
29 | USE grlib.stdlib.ALL; |
|
29 | USE grlib.stdlib.ALL; | |
30 | USE grlib.devices.ALL; |
|
30 | USE grlib.devices.ALL; | |
31 | USE GRLIB.DMA2AHB_Package.ALL; |
|
31 | USE GRLIB.DMA2AHB_Package.ALL; | |
32 | LIBRARY lpp; |
|
32 | LIBRARY lpp; | |
33 | USE lpp.lpp_amba.ALL; |
|
33 | USE lpp.lpp_amba.ALL; | |
34 | USE lpp.apb_devices_list.ALL; |
|
34 | USE lpp.apb_devices_list.ALL; | |
35 | USE lpp.lpp_memory.ALL; |
|
35 | USE lpp.lpp_memory.ALL; | |
36 | USE lpp.lpp_dma_pkg.ALL; |
|
36 | USE lpp.lpp_dma_pkg.ALL; | |
37 | LIBRARY techmap; |
|
37 | LIBRARY techmap; | |
38 | USE techmap.gencomp.ALL; |
|
38 | USE techmap.gencomp.ALL; | |
39 |
|
39 | |||
40 |
|
40 | |||
41 | ENTITY lpp_lfr_ms_fsmdma IS |
|
41 | ENTITY lpp_lfr_ms_fsmdma IS | |
42 | PORT ( |
|
42 | PORT ( | |
43 | -- AMBA AHB system signals |
|
43 | -- AMBA AHB system signals | |
44 | HCLK : IN STD_ULOGIC; |
|
44 | HCLK : IN STD_ULOGIC; | |
45 | HRESETn : IN STD_ULOGIC; |
|
45 | HRESETn : IN STD_ULOGIC; | |
46 |
|
46 | |||
47 | --------------------------------------------------------------------------- |
|
47 | --------------------------------------------------------------------------- | |
48 | -- FIFO - IN |
|
48 | -- FIFO - IN | |
49 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
49 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
50 | fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
50 | fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
51 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
51 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
52 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
52 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
53 | fifo_empty : IN STD_LOGIC; |
|
53 | fifo_empty : IN STD_LOGIC; | |
54 | fifo_ren : OUT STD_LOGIC; |
|
54 | fifo_ren : OUT STD_LOGIC; | |
55 |
|
55 | |||
56 | --------------------------------------------------------------------------- |
|
56 | --------------------------------------------------------------------------- | |
57 | -- DMA - OUT |
|
57 | -- DMA - OUT | |
58 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
58 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
59 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
59 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
60 | dma_valid : OUT STD_LOGIC; |
|
60 | dma_valid : OUT STD_LOGIC; | |
61 | dma_valid_burst : OUT STD_LOGIC; |
|
61 | dma_valid_burst : OUT STD_LOGIC; | |
62 | dma_ren : IN STD_LOGIC; |
|
62 | dma_ren : IN STD_LOGIC; | |
63 | dma_done : IN STD_LOGIC; |
|
63 | dma_done : IN STD_LOGIC; | |
64 |
|
64 | |||
65 | --------------------------------------------------------------------------- |
|
65 | --------------------------------------------------------------------------- | |
66 | -- Reg out |
|
66 | -- Reg out | |
67 | ready_matrix_f0 : OUT STD_LOGIC; |
|
67 | ready_matrix_f0 : OUT STD_LOGIC; | |
68 | -- ready_matrix_f0_1 : OUT STD_LOGIC; |
|
|||
69 | ready_matrix_f1 : OUT STD_LOGIC; |
|
68 | ready_matrix_f1 : OUT STD_LOGIC; | |
70 | ready_matrix_f2 : OUT STD_LOGIC; |
|
69 | ready_matrix_f2 : OUT STD_LOGIC; | |
71 | --error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
70 | ||
72 |
|
|
71 | error_bad_component_error : OUT STD_LOGIC; | |
73 | error_buffer_full : OUT STD_LOGIC; |
|
72 | error_buffer_full : OUT STD_LOGIC; | |
74 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
73 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
75 |
|
74 | |||
76 | -- Reg In |
|
75 | -- Reg In | |
77 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
76 | status_ready_matrix_f0 : IN STD_LOGIC; | |
78 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
|||
79 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
77 | status_ready_matrix_f1 : IN STD_LOGIC; | |
80 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
78 | status_ready_matrix_f2 : IN STD_LOGIC; | |
81 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
|||
82 | -- status_error_bad_component_error : IN STD_LOGIC; |
|
|||
83 | -- status_error_buffer_full : IN STD_LOGIC; |
|
|||
84 |
|
79 | |||
85 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
80 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
86 | config_active_interruption_onError : IN STD_LOGIC; |
|
81 | config_active_interruption_onError : IN STD_LOGIC; | |
87 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
82 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
88 | --s addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
89 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
83 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
90 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
84 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
91 |
|
85 | |||
92 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
86 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
93 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|||
94 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
87 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
95 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
88 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
96 |
|
89 | |||
97 | ); |
|
90 | ); | |
98 | END; |
|
91 | END; | |
99 |
|
92 | |||
100 | ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS |
|
93 | ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS | |
101 | ----------------------------------------------------------------------------- |
|
94 | ----------------------------------------------------------------------------- | |
102 | TYPE state_DMAWriteBurst IS (IDLE, |
|
95 | TYPE state_DMAWriteBurst IS (IDLE, | |
103 | CHECK_COMPONENT_TYPE, |
|
96 | CHECK_COMPONENT_TYPE, | |
104 | WRITE_COARSE_TIME, |
|
97 | WRITE_COARSE_TIME, | |
105 | WRITE_FINE_TIME, |
|
98 | WRITE_FINE_TIME, | |
106 | TRASH_FIFO, |
|
99 | TRASH_FIFO, | |
107 | SEND_DATA, |
|
100 | SEND_DATA, | |
108 | WAIT_DATA_ACK |
|
101 | WAIT_DATA_ACK | |
109 | ); |
|
102 | ); | |
110 | SIGNAL state : state_DMAWriteBurst; |
|
103 | SIGNAL state : state_DMAWriteBurst; | |
111 |
|
104 | |||
112 | SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
105 | SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
113 | SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
106 | SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
114 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
107 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
115 | SIGNAL header_check_ok : STD_LOGIC; |
|
108 | SIGNAL header_check_ok : STD_LOGIC; | |
116 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
109 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
117 | -- SIGNAL send_matrix : STD_LOGIC; |
|
|||
118 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
110 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
119 | ----------------------------------------------------------------------------- |
|
111 | ----------------------------------------------------------------------------- | |
120 | ----------------------------------------------------------------------------- |
|
112 | ----------------------------------------------------------------------------- | |
121 |
|
113 | |||
122 | SIGNAL component_send : STD_LOGIC; |
|
114 | SIGNAL component_send : STD_LOGIC; | |
123 | SIGNAL component_send_ok : STD_LOGIC; |
|
115 | SIGNAL component_send_ok : STD_LOGIC; | |
124 | -- SIGNAL component_send_ko : STD_LOGIC; |
|
|||
125 | ----------------------------------------------------------------------------- |
|
116 | ----------------------------------------------------------------------------- | |
126 | SIGNAL fifo_ren_trash : STD_LOGIC; |
|
117 | SIGNAL fifo_ren_trash : STD_LOGIC; | |
127 | -- SIGNAL component_fifo_ren : STD_LOGIC; |
|
|||
128 |
|
118 | |||
129 | ----------------------------------------------------------------------------- |
|
119 | ----------------------------------------------------------------------------- | |
130 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
120 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
131 | ----------------------------------------------------------------------------- |
|
121 | ----------------------------------------------------------------------------- | |
132 | SIGNAL log_empty_fifo : STD_LOGIC; |
|
122 | SIGNAL log_empty_fifo : STD_LOGIC; | |
133 | ----------------------------------------------------------------------------- |
|
123 | ----------------------------------------------------------------------------- | |
134 | --SIGNAL header_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
135 | --SIGNAL header_reg_val : STD_LOGIC; |
|
|||
136 | --SIGNAL header_reg_ack : STD_LOGIC; |
|
|||
137 | -- SIGNAL header_error : STD_LOGIC; |
|
|||
138 |
|
124 | |||
139 | SIGNAL matrix_buffer_ready : STD_LOGIC; |
|
125 | SIGNAL matrix_buffer_ready : STD_LOGIC; | |
140 | BEGIN |
|
126 | BEGIN | |
141 |
|
127 | |||
142 | debug_reg <= debug_reg_s; |
|
128 | debug_reg <= debug_reg_s; | |
143 |
|
129 | |||
144 |
|
130 | |||
145 | matrix_buffer_ready <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0 = '0' ELSE |
|
131 | matrix_buffer_ready <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0 = '0' ELSE | |
146 | --'1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE |
|
|||
147 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f1 = '0' ELSE |
|
132 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f1 = '0' ELSE | |
148 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f2 = '0' ELSE |
|
133 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f2 = '0' ELSE | |
149 | '0'; |
|
134 | '0'; | |
150 |
|
135 | |||
151 | header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111" |
|
136 | header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111" | |
152 | '1' WHEN component_type = "0000" ELSE --AND component_type_pre = "0000" ELSE |
|
137 | '1' WHEN component_type = "0000" ELSE --AND component_type_pre = "0000" ELSE | |
153 | '1' WHEN component_type = component_type_pre + "0001" ELSE |
|
138 | '1' WHEN component_type = component_type_pre + "0001" ELSE | |
154 | '0'; |
|
139 | '0'; | |
155 |
|
140 | |||
156 | address_matrix <= addr_matrix_f0 WHEN matrix_type = "00" ELSE |
|
141 | address_matrix <= addr_matrix_f0 WHEN matrix_type = "00" ELSE | |
157 | --addr_matrix_f0_1 WHEN matrix_type = "01" ELSE |
|
|||
158 | addr_matrix_f1 WHEN matrix_type = "01" ELSE |
|
142 | addr_matrix_f1 WHEN matrix_type = "01" ELSE | |
159 | addr_matrix_f2 WHEN matrix_type = "10" ELSE |
|
143 | addr_matrix_f2 WHEN matrix_type = "10" ELSE | |
160 | (OTHERS => '0'); |
|
144 | (OTHERS => '0'); | |
161 |
|
145 | |||
162 |
debug_reg_s(31 DOWNTO |
|
146 | debug_reg_s(31 DOWNTO 15) <= (OTHERS => '0'); | |
163 | ----------------------------------------------------------------------------- |
|
147 | ----------------------------------------------------------------------------- | |
164 | -- DMA control |
|
148 | -- DMA control | |
165 | ----------------------------------------------------------------------------- |
|
149 | ----------------------------------------------------------------------------- | |
166 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) |
|
150 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) | |
167 | BEGIN |
|
151 | BEGIN | |
168 | IF HRESETn = '0' THEN |
|
152 | IF HRESETn = '0' THEN | |
169 | matrix_type <= (OTHERS => '0'); |
|
153 | matrix_type <= (OTHERS => '0'); | |
170 | component_type <= (OTHERS => '0'); |
|
154 | component_type <= (OTHERS => '0'); | |
171 | state <= IDLE; |
|
155 | state <= IDLE; | |
172 | ready_matrix_f0 <= '0'; |
|
156 | ready_matrix_f0 <= '0'; | |
173 | -- ready_matrix_f0_1 <= '0'; |
|
|||
174 | ready_matrix_f1 <= '0'; |
|
157 | ready_matrix_f1 <= '0'; | |
175 | ready_matrix_f2 <= '0'; |
|
158 | ready_matrix_f2 <= '0'; | |
176 | -- error_anticipating_empty_fifo <= '0'; |
|
|||
177 | error_bad_component_error <= '0'; |
|
159 | error_bad_component_error <= '0'; | |
178 | error_buffer_full <= '0'; -- TODO |
|
160 | error_buffer_full <= '0'; -- TODO | |
179 | component_type_pre <= "0000"; |
|
161 | component_type_pre <= "0000"; | |
180 | fifo_ren_trash <= '1'; |
|
162 | fifo_ren_trash <= '1'; | |
181 | component_send <= '0'; |
|
163 | component_send <= '0'; | |
182 | address <= (OTHERS => '0'); |
|
164 | address <= (OTHERS => '0'); | |
183 |
|
165 | |||
184 | debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0'); |
|
166 | debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0'); | |
|
167 | debug_reg_s(5 DOWNTO 3) <= (OTHERS => '0'); | |||
|
168 | debug_reg_s(8 DOWNTO 6) <= (OTHERS => '0'); | |||
|
169 | debug_reg_s(10 DOWNTO 9) <= (OTHERS => '0'); | |||
|
170 | debug_reg_s(14 DOWNTO 11) <= (OTHERS => '0'); | |||
185 |
|
171 | |||
186 | log_empty_fifo <= '0'; |
|
172 | log_empty_fifo <= '0'; | |
187 |
|
173 | |||
188 | matrix_time_f0 <= (OTHERS => '0'); |
|
174 | matrix_time_f0 <= (OTHERS => '0'); | |
189 | matrix_time_f1 <= (OTHERS => '0'); |
|
175 | matrix_time_f1 <= (OTHERS => '0'); | |
190 | matrix_time_f2 <= (OTHERS => '0'); |
|
176 | matrix_time_f2 <= (OTHERS => '0'); | |
191 |
|
177 | |||
192 |
ELSIF HCLK'EVENT AND HCLK = '1' THEN |
|
178 | ELSIF HCLK'EVENT AND HCLK = '1' THEN | |
|
179 | -- | |||
|
180 | debug_reg_s(3) <= status_ready_matrix_f0; | |||
|
181 | debug_reg_s(4) <= status_ready_matrix_f0; | |||
|
182 | debug_reg_s(5) <= status_ready_matrix_f0; | |||
|
183 | debug_reg_s(6) <= '0'; | |||
|
184 | debug_reg_s(7) <= '0'; | |||
|
185 | debug_reg_s(8) <= '0'; | |||
|
186 | debug_reg_s(10 DOWNTO 9) <= matrix_type; | |||
|
187 | debug_reg_s(14 DOWNTO 11) <= component_type; | |||
|
188 | ||||
|
189 | -- | |||
|
190 | ||||
|
191 | ||||
193 |
|
192 | |||
194 | ready_matrix_f0 <= '0'; |
|
193 | ready_matrix_f0 <= '0'; | |
195 | -- ready_matrix_f0_1 <= '0'; |
|
|||
196 | ready_matrix_f1 <= '0'; |
|
194 | ready_matrix_f1 <= '0'; | |
197 | ready_matrix_f2 <= '0'; |
|
195 | ready_matrix_f2 <= '0'; | |
198 | error_bad_component_error <= '0'; |
|
196 | error_bad_component_error <= '0'; | |
199 | error_buffer_full <= '0'; |
|
197 | error_buffer_full <= '0'; | |
200 |
|
198 | |||
201 | CASE state IS |
|
199 | CASE state IS | |
202 | WHEN IDLE => |
|
200 | WHEN IDLE => | |
203 | debug_reg_s(2 DOWNTO 0) <= "000"; |
|
201 | debug_reg_s(2 DOWNTO 0) <= "000"; | |
204 | IF fifo_empty = '0' THEN |
|
202 | IF fifo_empty = '0' THEN | |
205 | state <= CHECK_COMPONENT_TYPE; |
|
203 | state <= CHECK_COMPONENT_TYPE; | |
206 | matrix_type <= fifo_matrix_type; |
|
204 | matrix_type <= fifo_matrix_type; | |
207 | component_type <= fifo_matrix_component; |
|
205 | component_type <= fifo_matrix_component; | |
208 | component_type_pre <= component_type; |
|
206 | component_type_pre <= component_type; | |
209 | END IF; |
|
207 | END IF; | |
210 |
|
208 | |||
211 | log_empty_fifo <= '0'; |
|
209 | log_empty_fifo <= '0'; | |
212 |
|
210 | |||
213 | WHEN CHECK_COMPONENT_TYPE => |
|
211 | WHEN CHECK_COMPONENT_TYPE => | |
214 | debug_reg_s(2 DOWNTO 0) <= "001"; |
|
212 | debug_reg_s(2 DOWNTO 0) <= "001"; | |
215 |
|
213 | |||
216 | IF header_check_ok = '1' AND matrix_buffer_ready = '1'THEN |
|
214 | IF header_check_ok = '1' AND matrix_buffer_ready = '1'THEN | |
217 | IF component_type = "0000" THEN |
|
215 | IF component_type = "0000" THEN | |
218 | address <= address_matrix; |
|
216 | address <= address_matrix; | |
219 | CASE matrix_type IS |
|
217 | CASE matrix_type IS | |
220 | WHEN "00" => matrix_time_f0 <= fifo_matrix_time; |
|
218 | WHEN "00" => matrix_time_f0 <= fifo_matrix_time; | |
221 | WHEN "01" => matrix_time_f1 <= fifo_matrix_time; |
|
219 | WHEN "01" => matrix_time_f1 <= fifo_matrix_time; | |
222 | WHEN "10" => matrix_time_f2 <= fifo_matrix_time; |
|
220 | WHEN "10" => matrix_time_f2 <= fifo_matrix_time; | |
223 | WHEN OTHERS => NULL; |
|
221 | WHEN OTHERS => NULL; | |
224 | END CASE; |
|
222 | END CASE; | |
225 | component_send <= '1'; |
|
223 | component_send <= '1'; | |
226 | END IF; |
|
224 | END IF; | |
227 | state <= SEND_DATA; |
|
225 | state <= SEND_DATA; | |
228 | -- |
|
226 | -- | |
229 | ELSE |
|
227 | ELSE | |
230 | error_bad_component_error <= NOT header_check_ok; |
|
228 | error_bad_component_error <= NOT header_check_ok; | |
231 | error_buffer_full <= NOT matrix_buffer_ready; -- TODO |
|
229 | error_buffer_full <= NOT matrix_buffer_ready; -- TODO | |
232 | component_type_pre <= "0000"; |
|
230 | component_type_pre <= "0000"; | |
233 | state <= TRASH_FIFO; |
|
231 | state <= TRASH_FIFO; | |
234 | END IF; |
|
232 | END IF; | |
235 |
|
233 | |||
236 | WHEN TRASH_FIFO => |
|
234 | WHEN TRASH_FIFO => | |
237 | debug_reg_s(2 DOWNTO 0) <= "100"; |
|
235 | debug_reg_s(2 DOWNTO 0) <= "100"; | |
238 |
|
236 | |||
239 | error_bad_component_error <= '0'; |
|
237 | error_bad_component_error <= '0'; | |
240 | -- error_anticipating_empty_fifo <= '0'; |
|
|||
241 | IF fifo_empty = '1' THEN |
|
238 | IF fifo_empty = '1' THEN | |
242 | state <= IDLE; |
|
239 | state <= IDLE; | |
243 | fifo_ren_trash <= '1'; |
|
240 | fifo_ren_trash <= '1'; | |
244 | ELSE |
|
241 | ELSE | |
245 | fifo_ren_trash <= '0'; |
|
242 | fifo_ren_trash <= '0'; | |
246 | END IF; |
|
243 | END IF; | |
247 |
|
244 | |||
248 | WHEN SEND_DATA => |
|
245 | WHEN SEND_DATA => | |
249 |
debug_reg_s(2 DOWNTO 0) <= " |
|
246 | debug_reg_s(2 DOWNTO 0) <= "010"; | |
250 |
|
247 | |||
251 | IF fifo_empty = '1' OR log_empty_fifo = '1' THEN |
|
248 | IF fifo_empty = '1' OR log_empty_fifo = '1' THEN | |
252 | state <= IDLE; |
|
249 | state <= IDLE; | |
253 | IF component_type = "1110" THEN |
|
250 | IF component_type = "1110" THEN | |
254 | CASE matrix_type IS |
|
251 | CASE matrix_type IS | |
255 |
WHEN "00" => |
|
252 | WHEN "00" => | |
256 |
|
|
253 | ready_matrix_f0 <= '1'; | |
257 |
|
|
254 | debug_reg_s(6) <= '1'; | |
|
255 | WHEN "01" => | |||
|
256 | ready_matrix_f1 <= '1'; | |||
|
257 | debug_reg_s(7) <= '1'; | |||
|
258 | WHEN "10" => | |||
|
259 | ready_matrix_f2 <= '1'; | |||
|
260 | debug_reg_s(8) <= '1'; | |||
258 | WHEN OTHERS => NULL; |
|
261 | WHEN OTHERS => NULL; | |
259 | END CASE; |
|
262 | END CASE; | |
260 | END IF; |
|
263 | END IF; | |
261 | ELSE |
|
264 | ELSE | |
262 | component_send <= '1'; |
|
265 | component_send <= '1'; | |
263 | address <= address; |
|
266 | address <= address; | |
264 | state <= WAIT_DATA_ACK; |
|
267 | state <= WAIT_DATA_ACK; | |
265 | END IF; |
|
268 | END IF; | |
266 |
|
269 | |||
267 | WHEN WAIT_DATA_ACK => |
|
270 | WHEN WAIT_DATA_ACK => | |
268 | log_empty_fifo <= fifo_empty OR log_empty_fifo; |
|
271 | log_empty_fifo <= fifo_empty OR log_empty_fifo; | |
269 |
|
272 | |||
270 |
debug_reg_s(2 DOWNTO 0) <= "11 |
|
273 | debug_reg_s(2 DOWNTO 0) <= "011"; | |
271 |
|
274 | |||
272 | component_send <= '0'; |
|
275 | component_send <= '0'; | |
273 | IF component_send_ok = '1' THEN |
|
276 | IF component_send_ok = '1' THEN | |
274 | address <= address + 64; |
|
277 | address <= address + 64; | |
275 | state <= SEND_DATA; |
|
278 | state <= SEND_DATA; | |
276 | -- ELSIF component_send_ko = '1' THEN |
|
|||
277 | -- error_anticipating_empty_fifo <= '0'; |
|
|||
278 | -- state <= TRASH_FIFO; |
|
|||
279 | END IF; |
|
279 | END IF; | |
280 |
|
280 | |||
281 | WHEN OTHERS => NULL; |
|
281 | WHEN OTHERS => NULL; | |
282 | END CASE; |
|
282 | END CASE; | |
283 |
|
283 | |||
284 | END IF; |
|
284 | END IF; | |
285 | END PROCESS DMAWriteFSM_p; |
|
285 | END PROCESS DMAWriteFSM_p; | |
286 |
|
286 | |||
287 | dma_valid_burst <= component_send; |
|
287 | dma_valid_burst <= component_send; | |
288 | dma_valid <= '0'; |
|
288 | dma_valid <= '0'; | |
289 | dma_data <= fifo_data; |
|
289 | dma_data <= fifo_data; | |
290 | dma_addr <= address; |
|
290 | dma_addr <= address; | |
291 | fifo_ren <= dma_ren AND fifo_ren_trash; |
|
291 | fifo_ren <= dma_ren AND fifo_ren_trash; | |
292 |
|
292 | |||
293 | component_send_ok <= dma_done; |
|
293 | component_send_ok <= dma_done; | |
294 | -- component_send_ko <= '0'; |
|
|||
295 |
|
294 | |||
296 | END Behavioral; |
|
295 | END Behavioral; |
@@ -1,401 +1,395 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 |
|
3 | |||
4 | LIBRARY grlib; |
|
4 | LIBRARY grlib; | |
5 | USE grlib.amba.ALL; |
|
5 | USE grlib.amba.ALL; | |
6 |
|
6 | |||
7 | LIBRARY lpp; |
|
7 | LIBRARY lpp; | |
8 | USE lpp.lpp_ad_conv.ALL; |
|
8 | USE lpp.lpp_ad_conv.ALL; | |
9 | USE lpp.iir_filter.ALL; |
|
9 | USE lpp.iir_filter.ALL; | |
10 | USE lpp.FILTERcfg.ALL; |
|
10 | USE lpp.FILTERcfg.ALL; | |
11 | USE lpp.lpp_memory.ALL; |
|
11 | USE lpp.lpp_memory.ALL; | |
12 | LIBRARY techmap; |
|
12 | LIBRARY techmap; | |
13 | USE techmap.gencomp.ALL; |
|
13 | USE techmap.gencomp.ALL; | |
14 |
|
14 | |||
15 | PACKAGE lpp_lfr_pkg IS |
|
15 | PACKAGE lpp_lfr_pkg IS | |
16 | ----------------------------------------------------------------------------- |
|
16 | ----------------------------------------------------------------------------- | |
17 | -- TEMP |
|
17 | -- TEMP | |
18 | ----------------------------------------------------------------------------- |
|
18 | ----------------------------------------------------------------------------- | |
19 | COMPONENT lpp_lfr_ms_test |
|
19 | COMPONENT lpp_lfr_ms_test | |
20 | GENERIC ( |
|
20 | GENERIC ( | |
21 | Mem_use : INTEGER); |
|
21 | Mem_use : INTEGER); | |
22 | PORT ( |
|
22 | PORT ( | |
23 | clk : IN STD_LOGIC; |
|
23 | clk : IN STD_LOGIC; | |
24 | rstn : IN STD_LOGIC; |
|
24 | rstn : IN STD_LOGIC; | |
25 |
|
25 | |||
26 | -- TIME |
|
26 | -- TIME | |
27 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
27 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
28 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
28 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
29 | -- |
|
29 | -- | |
30 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
30 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
31 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
31 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
32 | -- |
|
32 | -- | |
33 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
33 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
34 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
34 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
35 | -- |
|
35 | -- | |
36 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
36 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
37 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
37 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
38 |
|
38 | |||
39 |
|
39 | |||
40 |
|
40 | |||
41 | --------------------------------------------------------------------------- |
|
41 | --------------------------------------------------------------------------- | |
42 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
42 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
43 |
|
43 | |||
44 | -- |
|
44 | -- | |
45 | --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
45 | --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
46 | --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
46 | --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
47 | --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
47 | --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
48 | --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
48 | --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
49 |
|
49 | |||
50 | --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
50 | --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0); | |
51 |
|
51 | |||
52 | -- IN |
|
52 | -- IN | |
53 | MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
53 | MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
54 |
|
54 | |||
55 | ----------------------------------------------------------------------------- |
|
55 | ----------------------------------------------------------------------------- | |
56 |
|
56 | |||
57 | status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
57 | status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); | |
58 | SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); |
|
58 | SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); | |
59 | SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
59 | SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
60 | SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
60 | SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
61 |
|
61 | |||
62 | SM_correlation_start : OUT STD_LOGIC; |
|
62 | SM_correlation_start : OUT STD_LOGIC; | |
63 | SM_correlation_auto : OUT STD_LOGIC; |
|
63 | SM_correlation_auto : OUT STD_LOGIC; | |
64 | SM_correlation_done : IN STD_LOGIC |
|
64 | SM_correlation_done : IN STD_LOGIC | |
65 | ); |
|
65 | ); | |
66 | END COMPONENT; |
|
66 | END COMPONENT; | |
67 |
|
67 | |||
68 |
|
68 | |||
69 | ----------------------------------------------------------------------------- |
|
69 | ----------------------------------------------------------------------------- | |
70 | COMPONENT lpp_lfr_ms |
|
70 | COMPONENT lpp_lfr_ms | |
71 | GENERIC ( |
|
71 | GENERIC ( | |
72 | Mem_use : INTEGER |
|
72 | Mem_use : INTEGER | |
73 | ); |
|
73 | ); | |
74 | PORT ( |
|
74 | PORT ( | |
75 | clk : IN STD_LOGIC; |
|
75 | clk : IN STD_LOGIC; | |
76 | rstn : IN STD_LOGIC; |
|
76 | rstn : IN STD_LOGIC; | |
77 |
|
77 | |||
78 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
78 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
79 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
79 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
80 |
|
80 | |||
81 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
81 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
82 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
82 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
83 |
|
83 | |||
84 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
84 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
85 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
85 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
86 |
|
86 | |||
87 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
87 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
88 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
88 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
89 |
|
89 | |||
90 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
90 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
91 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
92 | dma_valid : OUT STD_LOGIC; |
|
92 | dma_valid : OUT STD_LOGIC; | |
93 | dma_valid_burst : OUT STD_LOGIC; |
|
93 | dma_valid_burst : OUT STD_LOGIC; | |
94 | dma_ren : IN STD_LOGIC; |
|
94 | dma_ren : IN STD_LOGIC; | |
95 | dma_done : IN STD_LOGIC; |
|
95 | dma_done : IN STD_LOGIC; | |
96 |
|
96 | |||
97 | ready_matrix_f0 : OUT STD_LOGIC; |
|
97 | ready_matrix_f0 : OUT STD_LOGIC; | |
98 | -- ready_matrix_f0_1 : OUT STD_LOGIC; |
|
98 | -- ready_matrix_f0_1 : OUT STD_LOGIC; | |
99 | ready_matrix_f1 : OUT STD_LOGIC; |
|
99 | ready_matrix_f1 : OUT STD_LOGIC; | |
100 | ready_matrix_f2 : OUT STD_LOGIC; |
|
100 | ready_matrix_f2 : OUT STD_LOGIC; | |
101 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
101 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; | |
102 | error_bad_component_error : OUT STD_LOGIC; |
|
102 | error_bad_component_error : OUT STD_LOGIC; | |
103 | error_buffer_full : OUT STD_LOGIC; |
|
103 | error_buffer_full : OUT STD_LOGIC; | |
104 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
104 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
105 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
105 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
106 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
106 | status_ready_matrix_f0 : IN STD_LOGIC; | |
107 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
107 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; | |
108 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
108 | status_ready_matrix_f1 : IN STD_LOGIC; | |
109 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
109 | status_ready_matrix_f2 : IN STD_LOGIC; | |
110 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
110 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
111 | -- status_error_bad_component_error : IN STD_LOGIC; |
|
111 | -- status_error_bad_component_error : IN STD_LOGIC; | |
112 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
112 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
113 | config_active_interruption_onError : IN STD_LOGIC; |
|
113 | config_active_interruption_onError : IN STD_LOGIC; | |
114 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
114 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
115 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
115 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
116 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
116 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
117 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
117 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
118 |
|
118 | |||
119 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
119 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
120 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
120 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
121 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
121 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
122 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); |
|
122 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); | |
123 | END COMPONENT; |
|
123 | END COMPONENT; | |
124 |
|
124 | |||
125 | COMPONENT lpp_lfr_ms_fsmdma |
|
125 | COMPONENT lpp_lfr_ms_fsmdma | |
126 | PORT ( |
|
126 | PORT ( | |
127 | HCLK : IN STD_ULOGIC; |
|
127 | HCLK : IN STD_ULOGIC; | |
128 | HRESETn : IN STD_ULOGIC; |
|
128 | HRESETn : IN STD_ULOGIC; | |
129 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
129 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
130 | fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
130 | fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
131 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
131 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
132 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
132 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
133 | fifo_empty : IN STD_LOGIC; |
|
133 | fifo_empty : IN STD_LOGIC; | |
134 | fifo_ren : OUT STD_LOGIC; |
|
134 | fifo_ren : OUT STD_LOGIC; | |
135 | --data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
135 | --data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
136 | --fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
136 | --fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
137 | --fifo_empty : IN STD_LOGIC; |
|
137 | --fifo_empty : IN STD_LOGIC; | |
138 | --fifo_ren : OUT STD_LOGIC; |
|
138 | --fifo_ren : OUT STD_LOGIC; | |
139 | --header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
139 | --header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
140 | --header_val : IN STD_LOGIC; |
|
140 | --header_val : IN STD_LOGIC; | |
141 | --header_ack : OUT STD_LOGIC; |
|
141 | --header_ack : OUT STD_LOGIC; | |
142 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
142 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
143 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
143 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
144 | dma_valid : OUT STD_LOGIC; |
|
144 | dma_valid : OUT STD_LOGIC; | |
145 | dma_valid_burst : OUT STD_LOGIC; |
|
145 | dma_valid_burst : OUT STD_LOGIC; | |
146 | dma_ren : IN STD_LOGIC; |
|
146 | dma_ren : IN STD_LOGIC; | |
147 | dma_done : IN STD_LOGIC; |
|
147 | dma_done : IN STD_LOGIC; | |
148 | ready_matrix_f0 : OUT STD_LOGIC; |
|
148 | ready_matrix_f0 : OUT STD_LOGIC; | |
149 | -- ready_matrix_f0_1 : OUT STD_LOGIC; |
|
149 | -- ready_matrix_f0_1 : OUT STD_LOGIC; | |
150 | ready_matrix_f1 : OUT STD_LOGIC; |
|
150 | ready_matrix_f1 : OUT STD_LOGIC; | |
151 | ready_matrix_f2 : OUT STD_LOGIC; |
|
151 | ready_matrix_f2 : OUT STD_LOGIC; | |
152 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
152 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; | |
153 | error_bad_component_error : OUT STD_LOGIC; |
|
153 | error_bad_component_error : OUT STD_LOGIC; | |
154 | error_buffer_full : OUT STD_LOGIC; |
|
154 | error_buffer_full : OUT STD_LOGIC; | |
155 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
155 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
156 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
156 | status_ready_matrix_f0 : IN STD_LOGIC; | |
157 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
157 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; | |
158 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
158 | status_ready_matrix_f1 : IN STD_LOGIC; | |
159 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
159 | status_ready_matrix_f2 : IN STD_LOGIC; | |
160 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
160 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
161 | -- status_error_bad_component_error : IN STD_LOGIC; |
|
161 | -- status_error_bad_component_error : IN STD_LOGIC; | |
162 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
162 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
163 | config_active_interruption_onError : IN STD_LOGIC; |
|
163 | config_active_interruption_onError : IN STD_LOGIC; | |
164 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
164 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
165 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
165 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
166 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
166 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
167 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
167 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
168 |
|
168 | |||
169 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
169 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
170 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
170 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
171 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
171 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
172 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
172 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
173 | ); |
|
173 | ); | |
174 | END COMPONENT; |
|
174 | END COMPONENT; | |
175 |
|
175 | |||
176 | COMPONENT lpp_lfr_ms_FFT |
|
176 | COMPONENT lpp_lfr_ms_FFT | |
177 | PORT ( |
|
177 | PORT ( | |
178 | clk : IN STD_LOGIC; |
|
178 | clk : IN STD_LOGIC; | |
179 | rstn : IN STD_LOGIC; |
|
179 | rstn : IN STD_LOGIC; | |
180 | sample_valid : IN STD_LOGIC; |
|
180 | sample_valid : IN STD_LOGIC; | |
181 | fft_read : IN STD_LOGIC; |
|
181 | fft_read : IN STD_LOGIC; | |
182 | sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
182 | sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
183 | sample_load : OUT STD_LOGIC; |
|
183 | sample_load : OUT STD_LOGIC; | |
184 | fft_pong : OUT STD_LOGIC; |
|
184 | fft_pong : OUT STD_LOGIC; | |
185 | fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
185 | fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |
186 | fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
186 | fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |
187 | fft_data_valid : OUT STD_LOGIC; |
|
187 | fft_data_valid : OUT STD_LOGIC; | |
188 | fft_ready : OUT STD_LOGIC); |
|
188 | fft_ready : OUT STD_LOGIC); | |
189 | END COMPONENT; |
|
189 | END COMPONENT; | |
190 |
|
190 | |||
191 | COMPONENT lpp_lfr_filter |
|
191 | COMPONENT lpp_lfr_filter | |
192 | GENERIC ( |
|
192 | GENERIC ( | |
193 | Mem_use : INTEGER); |
|
193 | Mem_use : INTEGER); | |
194 | PORT ( |
|
194 | PORT ( | |
195 | sample : IN Samples(7 DOWNTO 0); |
|
195 | sample : IN Samples(7 DOWNTO 0); | |
196 | sample_val : IN STD_LOGIC; |
|
196 | sample_val : IN STD_LOGIC; | |
197 | clk : IN STD_LOGIC; |
|
197 | clk : IN STD_LOGIC; | |
198 | rstn : IN STD_LOGIC; |
|
198 | rstn : IN STD_LOGIC; | |
199 | data_shaping_SP0 : IN STD_LOGIC; |
|
199 | data_shaping_SP0 : IN STD_LOGIC; | |
200 | data_shaping_SP1 : IN STD_LOGIC; |
|
200 | data_shaping_SP1 : IN STD_LOGIC; | |
201 | data_shaping_R0 : IN STD_LOGIC; |
|
201 | data_shaping_R0 : IN STD_LOGIC; | |
202 | data_shaping_R1 : IN STD_LOGIC; |
|
202 | data_shaping_R1 : IN STD_LOGIC; | |
203 | sample_f0_val : OUT STD_LOGIC; |
|
203 | sample_f0_val : OUT STD_LOGIC; | |
204 | sample_f1_val : OUT STD_LOGIC; |
|
204 | sample_f1_val : OUT STD_LOGIC; | |
205 | sample_f2_val : OUT STD_LOGIC; |
|
205 | sample_f2_val : OUT STD_LOGIC; | |
206 | sample_f3_val : OUT STD_LOGIC; |
|
206 | sample_f3_val : OUT STD_LOGIC; | |
207 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
207 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
208 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
208 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
209 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
209 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
210 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)); |
|
210 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)); | |
211 | END COMPONENT; |
|
211 | END COMPONENT; | |
212 |
|
212 | |||
213 | COMPONENT lpp_lfr |
|
213 | COMPONENT lpp_lfr | |
214 | GENERIC ( |
|
214 | GENERIC ( | |
215 | Mem_use : INTEGER; |
|
215 | Mem_use : INTEGER; | |
216 | nb_data_by_buffer_size : INTEGER; |
|
216 | nb_data_by_buffer_size : INTEGER; | |
217 | nb_word_by_buffer_size : INTEGER; |
|
217 | nb_word_by_buffer_size : INTEGER; | |
218 | nb_snapshot_param_size : INTEGER; |
|
218 | nb_snapshot_param_size : INTEGER; | |
219 | delta_vector_size : INTEGER; |
|
219 | delta_vector_size : INTEGER; | |
220 | delta_vector_size_f0_2 : INTEGER; |
|
220 | delta_vector_size_f0_2 : INTEGER; | |
221 | pindex : INTEGER; |
|
221 | pindex : INTEGER; | |
222 | paddr : INTEGER; |
|
222 | paddr : INTEGER; | |
223 | pmask : INTEGER; |
|
223 | pmask : INTEGER; | |
224 | pirq_ms : INTEGER; |
|
224 | pirq_ms : INTEGER; | |
225 | pirq_wfp : INTEGER; |
|
225 | pirq_wfp : INTEGER; | |
226 | hindex : INTEGER; |
|
226 | hindex : INTEGER; | |
227 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) |
|
227 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) | |
228 | ); |
|
228 | ); | |
229 | PORT ( |
|
229 | PORT ( | |
230 | clk : IN STD_LOGIC; |
|
230 | clk : IN STD_LOGIC; | |
231 | rstn : IN STD_LOGIC; |
|
231 | rstn : IN STD_LOGIC; | |
232 | sample_B : IN Samples(2 DOWNTO 0); |
|
232 | sample_B : IN Samples(2 DOWNTO 0); | |
233 | sample_E : IN Samples(4 DOWNTO 0); |
|
233 | sample_E : IN Samples(4 DOWNTO 0); | |
234 | sample_val : IN STD_LOGIC; |
|
234 | sample_val : IN STD_LOGIC; | |
235 | apbi : IN apb_slv_in_type; |
|
235 | apbi : IN apb_slv_in_type; | |
236 | apbo : OUT apb_slv_out_type; |
|
236 | apbo : OUT apb_slv_out_type; | |
237 | ahbi : IN AHB_Mst_In_Type; |
|
237 | ahbi : IN AHB_Mst_In_Type; | |
238 | ahbo : OUT AHB_Mst_Out_Type; |
|
238 | ahbo : OUT AHB_Mst_Out_Type; | |
239 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
239 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
240 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
240 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
241 | data_shaping_BW : OUT STD_LOGIC; |
|
241 | data_shaping_BW : OUT STD_LOGIC; | |
242 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
242 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
243 | ); |
|
243 | ); | |
244 | END COMPONENT; |
|
244 | END COMPONENT; | |
245 |
|
245 | |||
246 | ----------------------------------------------------------------------------- |
|
246 | ----------------------------------------------------------------------------- | |
247 | -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System) |
|
247 | -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System) | |
248 | ----------------------------------------------------------------------------- |
|
248 | ----------------------------------------------------------------------------- | |
249 | COMPONENT lpp_lfr_WFP_nMS |
|
249 | COMPONENT lpp_lfr_WFP_nMS | |
250 | GENERIC ( |
|
250 | GENERIC ( | |
251 | Mem_use : INTEGER; |
|
251 | Mem_use : INTEGER; | |
252 | nb_data_by_buffer_size : INTEGER; |
|
252 | nb_data_by_buffer_size : INTEGER; | |
253 | nb_word_by_buffer_size : INTEGER; |
|
253 | nb_word_by_buffer_size : INTEGER; | |
254 | nb_snapshot_param_size : INTEGER; |
|
254 | nb_snapshot_param_size : INTEGER; | |
255 | delta_vector_size : INTEGER; |
|
255 | delta_vector_size : INTEGER; | |
256 | delta_vector_size_f0_2 : INTEGER; |
|
256 | delta_vector_size_f0_2 : INTEGER; | |
257 | pindex : INTEGER; |
|
257 | pindex : INTEGER; | |
258 | paddr : INTEGER; |
|
258 | paddr : INTEGER; | |
259 | pmask : INTEGER; |
|
259 | pmask : INTEGER; | |
260 | pirq_ms : INTEGER; |
|
260 | pirq_ms : INTEGER; | |
261 | pirq_wfp : INTEGER; |
|
261 | pirq_wfp : INTEGER; | |
262 | hindex : INTEGER; |
|
262 | hindex : INTEGER; | |
263 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
263 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
264 | PORT ( |
|
264 | PORT ( | |
265 | clk : IN STD_LOGIC; |
|
265 | clk : IN STD_LOGIC; | |
266 | rstn : IN STD_LOGIC; |
|
266 | rstn : IN STD_LOGIC; | |
267 | sample_B : IN Samples(2 DOWNTO 0); |
|
267 | sample_B : IN Samples(2 DOWNTO 0); | |
268 | sample_E : IN Samples(4 DOWNTO 0); |
|
268 | sample_E : IN Samples(4 DOWNTO 0); | |
269 | sample_val : IN STD_LOGIC; |
|
269 | sample_val : IN STD_LOGIC; | |
270 | apbi : IN apb_slv_in_type; |
|
270 | apbi : IN apb_slv_in_type; | |
271 | apbo : OUT apb_slv_out_type; |
|
271 | apbo : OUT apb_slv_out_type; | |
272 | ahbi : IN AHB_Mst_In_Type; |
|
272 | ahbi : IN AHB_Mst_In_Type; | |
273 | ahbo : OUT AHB_Mst_Out_Type; |
|
273 | ahbo : OUT AHB_Mst_Out_Type; | |
274 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
274 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
275 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
275 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
276 | data_shaping_BW : OUT STD_LOGIC; |
|
276 | data_shaping_BW : OUT STD_LOGIC; | |
277 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
277 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
278 | END COMPONENT; |
|
278 | END COMPONENT; | |
279 | ----------------------------------------------------------------------------- |
|
279 | ----------------------------------------------------------------------------- | |
280 |
|
||||
281 |
|
||||
282 | COMPONENT lpp_lfr_apbreg |
|
280 | COMPONENT lpp_lfr_apbreg | |
283 | GENERIC ( |
|
281 | GENERIC ( | |
284 | nb_data_by_buffer_size : INTEGER; |
|
282 | nb_data_by_buffer_size : INTEGER; | |
285 | nb_word_by_buffer_size : INTEGER; |
|
283 | nb_word_by_buffer_size : INTEGER; | |
286 | nb_snapshot_param_size : INTEGER; |
|
284 | nb_snapshot_param_size : INTEGER; | |
287 | delta_vector_size : INTEGER; |
|
285 | delta_vector_size : INTEGER; | |
288 | delta_vector_size_f0_2 : INTEGER; |
|
286 | delta_vector_size_f0_2 : INTEGER; | |
289 | pindex : INTEGER; |
|
287 | pindex : INTEGER; | |
290 | paddr : INTEGER; |
|
288 | paddr : INTEGER; | |
291 | pmask : INTEGER; |
|
289 | pmask : INTEGER; | |
292 | pirq_ms : INTEGER; |
|
290 | pirq_ms : INTEGER; | |
293 | pirq_wfp : INTEGER; |
|
291 | pirq_wfp : INTEGER; | |
294 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
292 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
295 | PORT ( |
|
293 | PORT ( | |
296 | HCLK : IN STD_ULOGIC; |
|
294 | HCLK : IN STD_ULOGIC; | |
297 | HRESETn : IN STD_ULOGIC; |
|
295 | HRESETn : IN STD_ULOGIC; | |
298 | apbi : IN apb_slv_in_type; |
|
296 | apbi : IN apb_slv_in_type; | |
299 | apbo : OUT apb_slv_out_type; |
|
297 | apbo : OUT apb_slv_out_type; | |
300 | run_ms : OUT STD_LOGIC; |
|
298 | run_ms : OUT STD_LOGIC; | |
301 | ready_matrix_f0_0 : IN STD_LOGIC; |
|
299 | ready_matrix_f0_0 : IN STD_LOGIC; | |
302 | ready_matrix_f0_1 : IN STD_LOGIC; |
|
|||
303 | ready_matrix_f1 : IN STD_LOGIC; |
|
300 | ready_matrix_f1 : IN STD_LOGIC; | |
304 | ready_matrix_f2 : IN STD_LOGIC; |
|
301 | ready_matrix_f2 : IN STD_LOGIC; | |
305 | error_anticipating_empty_fifo : IN STD_LOGIC; |
|
|||
306 | error_bad_component_error : IN STD_LOGIC; |
|
302 | error_bad_component_error : IN STD_LOGIC; | |
|
303 | error_buffer_full : in STD_LOGIC; | |||
|
304 | error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0); | |||
307 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
305 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
308 | status_ready_matrix_f0_0 : OUT STD_LOGIC; |
|
306 | status_ready_matrix_f0_0 : OUT STD_LOGIC; | |
309 | status_ready_matrix_f0_1 : OUT STD_LOGIC; |
|
|||
310 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
307 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
311 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
308 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
312 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
|||
313 | status_error_bad_component_error : OUT STD_LOGIC; |
|
|||
314 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
309 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
315 | config_active_interruption_onError : OUT STD_LOGIC; |
|
310 | config_active_interruption_onError : OUT STD_LOGIC; | |
316 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
311 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
317 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
312 | -- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
318 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
313 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
319 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
314 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
320 |
|
315 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | ||
321 |
matrix_time_f0_ |
|
316 | -- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
322 |
matrix_time_f |
|
317 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
323 |
matrix_time_f |
|
318 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
324 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|||
325 |
|
||||
326 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
319 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
327 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
320 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
328 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
321 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
329 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
322 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
330 | data_shaping_BW : OUT STD_LOGIC; |
|
323 | data_shaping_BW : OUT STD_LOGIC; | |
331 | data_shaping_SP0 : OUT STD_LOGIC; |
|
324 | data_shaping_SP0 : OUT STD_LOGIC; | |
332 | data_shaping_SP1 : OUT STD_LOGIC; |
|
325 | data_shaping_SP1 : OUT STD_LOGIC; | |
333 | data_shaping_R0 : OUT STD_LOGIC; |
|
326 | data_shaping_R0 : OUT STD_LOGIC; | |
334 | data_shaping_R1 : OUT STD_LOGIC; |
|
327 | data_shaping_R1 : OUT STD_LOGIC; | |
335 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
328 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
336 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
329 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
337 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
330 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
338 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
331 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
339 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
332 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
340 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
333 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
341 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
334 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
342 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
335 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
343 | enable_f0 : OUT STD_LOGIC; |
|
336 | enable_f0 : OUT STD_LOGIC; | |
344 | enable_f1 : OUT STD_LOGIC; |
|
337 | enable_f1 : OUT STD_LOGIC; | |
345 | enable_f2 : OUT STD_LOGIC; |
|
338 | enable_f2 : OUT STD_LOGIC; | |
346 | enable_f3 : OUT STD_LOGIC; |
|
339 | enable_f3 : OUT STD_LOGIC; | |
347 | burst_f0 : OUT STD_LOGIC; |
|
340 | burst_f0 : OUT STD_LOGIC; | |
348 | burst_f1 : OUT STD_LOGIC; |
|
341 | burst_f1 : OUT STD_LOGIC; | |
349 | burst_f2 : OUT STD_LOGIC; |
|
342 | burst_f2 : OUT STD_LOGIC; | |
350 | run : OUT STD_LOGIC; |
|
343 | run : OUT STD_LOGIC; | |
351 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
344 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
352 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
345 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
353 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
346 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
354 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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347 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
355 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); |
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348 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); | |
356 | --------------------------------------------------------------------------- |
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|||
357 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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349 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
358 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
350 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
359 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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351 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
360 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
352 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
361 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
353 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
362 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
354 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
363 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
355 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
364 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
356 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
365 | END COMPONENT; |
|
357 | END COMPONENT; | |
|
358 | ||||
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359 | ||||
366 |
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360 | ||
367 |
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361 | COMPONENT lpp_top_ms | |
368 | GENERIC ( |
|
362 | GENERIC ( | |
369 | Mem_use : INTEGER; |
|
363 | Mem_use : INTEGER; | |
370 | nb_burst_available_size : INTEGER; |
|
364 | nb_burst_available_size : INTEGER; | |
371 | nb_snapshot_param_size : INTEGER; |
|
365 | nb_snapshot_param_size : INTEGER; | |
372 | delta_snapshot_size : INTEGER; |
|
366 | delta_snapshot_size : INTEGER; | |
373 | delta_f2_f0_size : INTEGER; |
|
367 | delta_f2_f0_size : INTEGER; | |
374 | delta_f2_f1_size : INTEGER; |
|
368 | delta_f2_f1_size : INTEGER; | |
375 | pindex : INTEGER; |
|
369 | pindex : INTEGER; | |
376 | paddr : INTEGER; |
|
370 | paddr : INTEGER; | |
377 | pmask : INTEGER; |
|
371 | pmask : INTEGER; | |
378 | pirq_ms : INTEGER; |
|
372 | pirq_ms : INTEGER; | |
379 | pirq_wfp : INTEGER; |
|
373 | pirq_wfp : INTEGER; | |
380 | hindex_wfp : INTEGER; |
|
374 | hindex_wfp : INTEGER; | |
381 | hindex_ms : INTEGER); |
|
375 | hindex_ms : INTEGER); | |
382 | PORT ( |
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376 | PORT ( | |
383 | clk : IN STD_LOGIC; |
|
377 | clk : IN STD_LOGIC; | |
384 | rstn : IN STD_LOGIC; |
|
378 | rstn : IN STD_LOGIC; | |
385 | sample_B : IN Samples14v(2 DOWNTO 0); |
|
379 | sample_B : IN Samples14v(2 DOWNTO 0); | |
386 | sample_E : IN Samples14v(4 DOWNTO 0); |
|
380 | sample_E : IN Samples14v(4 DOWNTO 0); | |
387 | sample_val : IN STD_LOGIC; |
|
381 | sample_val : IN STD_LOGIC; | |
388 | apbi : IN apb_slv_in_type; |
|
382 | apbi : IN apb_slv_in_type; | |
389 | apbo : OUT apb_slv_out_type; |
|
383 | apbo : OUT apb_slv_out_type; | |
390 | ahbi_ms : IN AHB_Mst_In_Type; |
|
384 | ahbi_ms : IN AHB_Mst_In_Type; | |
391 | ahbo_ms : OUT AHB_Mst_Out_Type; |
|
385 | ahbo_ms : OUT AHB_Mst_Out_Type; | |
392 | data_shaping_BW : OUT STD_LOGIC; |
|
386 | data_shaping_BW : OUT STD_LOGIC; | |
393 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
387 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
394 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
388 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
395 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
389 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
396 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
390 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) | |
397 |
|
391 | |||
398 | ); |
|
392 | ); | |
399 | END COMPONENT; |
|
393 | END COMPONENT; | |
400 |
|
394 | |||
401 | END lpp_lfr_pkg; |
|
395 | END lpp_lfr_pkg; |
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