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Sync
Jeandet Alexis -
r253:d746d794fb8a alexis
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1 library IEEE;
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
2 use IEEE.STD_LOGIC_1164.ALL;
3 use IEEE.NUMERIC_STD.ALL;
3 use IEEE.NUMERIC_STD.ALL;
4 library lpp;
4 library lpp;
5 use lpp.lpp_ad_conv.all;
5 use lpp.lpp_ad_conv.all;
6 use lpp.lpp_amba.all;
6 use lpp.lpp_amba.all;
7 use lpp.apb_devices_list.all;
7 use lpp.apb_devices_list.all;
8 use lpp.general_purpose.all;
8 use lpp.general_purpose.all;
9 use lpp.Rocket_PCM_Encoder.all;
9 use lpp.Rocket_PCM_Encoder.all;
10
10
11 use work.config.all;
11 use work.config.all;
12
12
13
13
14 entity DC_ACQ_TOP is
14 entity DC_ACQ_TOP is
15 generic(
15 generic(
16 WordSize : integer := 8;
16 WordSize : integer := 8;
17 WordCnt : integer := 144;
17 WordCnt : integer := 144;
18 MinFCount : integer := 64;
18 MinFCount : integer := 64;
19 EnableSR : integer := 1;
19 EnableSR : integer := 1;
20 CstDATA : integer := 0;
20 CstDATA : integer := 0;
21 FakeADC : integer := 0;
21 FakeADC : integer := 0;
22 CDS : integer := 0
22 CDS : integer := 0
23 );
23 );
24 port(
24 port(
25
25
26 reset : in std_logic;
26 reset : in std_logic;
27 clk : in std_logic;
27 clk : in std_logic;
28 SyncSig : in STD_LOGIC;
28 SyncSig : in STD_LOGIC;
29 minorF : in std_logic;
29 minorF : in std_logic;
30 majorF : in std_logic;
30 majorF : in std_logic;
31 sclk : in std_logic;
31 sclk : in std_logic;
32 WordClk : in std_logic;
32 WordClk : in std_logic;
33
33
34 DC_ADC_Sclk : out std_logic;
34 DC_ADC_Sclk : out std_logic;
35 DC_ADC_IN : in std_logic_vector(1 downto 0);
35 DC_ADC_IN : in std_logic_vector(1 downto 0);
36 DC_ADC_ClkDiv : out std_logic;
36 DC_ADC_ClkDiv : out std_logic;
37 DC_ADC_FSynch : out std_logic;
37 DC_ADC_FSynch : out std_logic;
38 SET_RESET0 : out std_logic;
38 SET_RESET0 : out std_logic;
39 SET_RESET1 : out std_logic;
39 SET_RESET1 : out std_logic;
40
40
41 AMR1X : out std_logic_vector(23 downto 0);
41 AMR1X : out std_logic_vector(23 downto 0);
42 AMR1Y : out std_logic_vector(23 downto 0);
42 AMR1Y : out std_logic_vector(23 downto 0);
43 AMR1Z : out std_logic_vector(23 downto 0);
43 AMR1Z : out std_logic_vector(23 downto 0);
44
44
45 AMR2X : out std_logic_vector(23 downto 0);
45 AMR2X : out std_logic_vector(23 downto 0);
46 AMR2Y : out std_logic_vector(23 downto 0);
46 AMR2Y : out std_logic_vector(23 downto 0);
47 AMR2Z : out std_logic_vector(23 downto 0);
47 AMR2Z : out std_logic_vector(23 downto 0);
48
48
49 AMR3X : out std_logic_vector(23 downto 0);
49 AMR3X : out std_logic_vector(23 downto 0);
50 AMR3Y : out std_logic_vector(23 downto 0);
50 AMR3Y : out std_logic_vector(23 downto 0);
51 AMR3Z : out std_logic_vector(23 downto 0);
51 AMR3Z : out std_logic_vector(23 downto 0);
52
52
53 AMR4X : out std_logic_vector(23 downto 0);
53 AMR4X : out std_logic_vector(23 downto 0);
54 AMR4Y : out std_logic_vector(23 downto 0);
54 AMR4Y : out std_logic_vector(23 downto 0);
55 AMR4Z : out std_logic_vector(23 downto 0);
55 AMR4Z : out std_logic_vector(23 downto 0);
56
56
57 Temp1 : out std_logic_vector(23 downto 0);
57 Temp1 : out std_logic_vector(23 downto 0);
58 Temp2 : out std_logic_vector(23 downto 0);
58 Temp2 : out std_logic_vector(23 downto 0);
59 Temp3 : out std_logic_vector(23 downto 0);
59 Temp3 : out std_logic_vector(23 downto 0);
60 Temp4 : out std_logic_vector(23 downto 0)
60 Temp4 : out std_logic_vector(23 downto 0)
61 );
61 );
62 end DC_ACQ_TOP;
62 end DC_ACQ_TOP;
63
63
64 architecture Behavioral of DC_ACQ_TOP is
64 architecture Behavioral of DC_ACQ_TOP is
65
65
66 signal DC_ADC_SmplClk : std_logic;
66 signal DC_ADC_SmplClk : std_logic;
67 signal LF_ADC_SmplClk : std_logic;
67 signal LF_ADC_SmplClk : std_logic;
68 signal SET_RESET0_sig : std_logic;
68 signal SET_RESET0_sig : std_logic;
69 signal SET_RESET1_sig : std_logic;
69 signal SET_RESET1_sig : std_logic;
70 signal SET_RESET_counter : integer range 0 to 31:=0;
70 signal SET_RESET_counter : integer range 0 to 31:=0;
71
71
72 signal AMR1X_Sync : std_logic_vector(23 downto 0);
72 signal AMR1X_Sync : std_logic_vector(23 downto 0);
73 signal AMR1Y_Sync : std_logic_vector(23 downto 0);
73 signal AMR1Y_Sync : std_logic_vector(23 downto 0);
74 signal AMR1Z_Sync : std_logic_vector(23 downto 0);
74 signal AMR1Z_Sync : std_logic_vector(23 downto 0);
75
75
76 signal AMR2X_Sync : std_logic_vector(23 downto 0);
76 signal AMR2X_Sync : std_logic_vector(23 downto 0);
77 signal AMR2Y_Sync : std_logic_vector(23 downto 0);
77 signal AMR2Y_Sync : std_logic_vector(23 downto 0);
78 signal AMR2Z_Sync : std_logic_vector(23 downto 0);
78 signal AMR2Z_Sync : std_logic_vector(23 downto 0);
79
79
80 signal AMR3X_Sync : std_logic_vector(23 downto 0);
80 signal AMR3X_Sync : std_logic_vector(23 downto 0);
81 signal AMR3Y_Sync : std_logic_vector(23 downto 0);
81 signal AMR3Y_Sync : std_logic_vector(23 downto 0);
82 signal AMR3Z_Sync : std_logic_vector(23 downto 0);
82 signal AMR3Z_Sync : std_logic_vector(23 downto 0);
83
83
84 signal AMR4X_Sync : std_logic_vector(23 downto 0);
84 signal AMR4X_Sync : std_logic_vector(23 downto 0);
85 signal AMR4Y_Sync : std_logic_vector(23 downto 0);
85 signal AMR4Y_Sync : std_logic_vector(23 downto 0);
86 signal AMR4Z_Sync : std_logic_vector(23 downto 0);
86 signal AMR4Z_Sync : std_logic_vector(23 downto 0);
87
87
88 signal Temp1_Sync : std_logic_vector(23 downto 0);
88 signal Temp1_Sync : std_logic_vector(23 downto 0);
89 signal Temp2_Sync : std_logic_vector(23 downto 0);
89 signal Temp2_Sync : std_logic_vector(23 downto 0);
90 signal Temp3_Sync : std_logic_vector(23 downto 0);
90 signal Temp3_Sync : std_logic_vector(23 downto 0);
91 signal Temp4_Sync : std_logic_vector(23 downto 0);
91 signal Temp4_Sync : std_logic_vector(23 downto 0);
92
92
93 begin
93 begin
94
94
95 ------------------------------------------------------------------
95 ------------------------------------------------------------------
96 --
96 --
97 -- DC sampling clock generation
97 -- DC sampling clock generation
98 --
98 --
99 ------------------------------------------------------------------
99 ------------------------------------------------------------------
100
100
101
101
102 DC_SMPL_CLK0 : entity work.LF_SMPL_CLK
102 DC_SMPL_CLK0 : entity work.LF_SMPL_CLK
103 --generic map(36)
103 --generic map(36)
104 generic map(288)
104 generic map(288)
105 port map(
105 port map(
106 reset => reset,
106 reset => reset,
107 wclk => WordClk,
107 wclk => WordClk,
108 SMPL_CLK => DC_ADC_SmplClk
108 SMPL_CLK => DC_ADC_SmplClk
109 );
109 );
110 ------------------------------------------------------------------
110 ------------------------------------------------------------------
111
111
112
112
113
113
114
114
115 ------------------------------------------------------------------
115 ------------------------------------------------------------------
116 --
116 --
117 -- DC ADC
117 -- DC ADC
118 --
118 --
119 ------------------------------------------------------------------
119 ------------------------------------------------------------------
120 ADC1: IF CstDATA /= 1 GENERATE
120 ADC1: IF CstDATA /= 1 GENERATE
121 ADC : IF FakeADC /=1 GENERATE
121 ADC : IF FakeADC /=1 GENERATE
122
122
123 DC_ADC0 : DUAL_ADS1278_DRIVER
123 DC_ADC0 : DUAL_ADS1278_DRIVER
124 port map(
124 port map(
125 Clk => clk,
125 Clk => clk,
126 reset => reset,
126 reset => reset,
127 SpiClk => DC_ADC_Sclk,
127 SpiClk => DC_ADC_Sclk,
128 DIN => DC_ADC_IN,
128 DIN => DC_ADC_IN,
129 SmplClk => DC_ADC_SmplClk,
129 SmplClk => DC_ADC_SmplClk,
130 OUT00 => AMR1X_Sync,
130 OUT00 => AMR1X_Sync,
131 OUT01 => AMR1Y_Sync,
131 OUT01 => AMR1Y_Sync,
132 OUT02 => AMR1Z_Sync,
132 OUT02 => AMR1Z_Sync,
133 OUT03 => AMR2X_Sync,
133 OUT03 => AMR2X_Sync,
134 OUT04 => AMR2Y_Sync,
134 OUT04 => AMR2Y_Sync,
135 OUT05 => AMR2Z_Sync,
135 OUT05 => AMR2Z_Sync,
136 OUT06 => Temp1_Sync,
136 OUT06 => Temp1_Sync,
137 OUT07 => Temp2_Sync,
137 OUT07 => Temp2_Sync,
138 OUT10 => AMR3X_Sync,
138 OUT10 => AMR3X_Sync,
139 OUT11 => AMR3Y_Sync,
139 OUT11 => AMR3Y_Sync,
140 OUT12 => AMR3Z_Sync,
140 OUT12 => AMR3Z_Sync,
141 OUT13 => AMR4X_Sync,
141 OUT13 => AMR4X_Sync,
142 OUT14 => AMR4Y_Sync,
142 OUT14 => AMR4Y_Sync,
143 OUT15 => AMR4Z_Sync,
143 OUT15 => AMR4Z_Sync,
144 OUT16 => Temp3_Sync,
144 OUT16 => Temp3_Sync,
145 OUT17 => Temp4_Sync,
145 OUT17 => Temp4_Sync,
146 FSynch => DC_ADC_FSynch
146 FSynch => DC_ADC_FSynch
147 );
147 );
148 END GENERATE;
148 END GENERATE;
149
149
150 NOADC: IF FakeADC=1 GENERATE
150 NOADC: IF FakeADC=1 GENERATE
151
151
152 DC_ADC0 : entity work.FAKE_DUAL_ADS1278_DRIVER
152 DC_ADC0 : entity work.FAKE_DUAL_ADS1278_DRIVER
153 port map(
153 port map(
154 Clk => clk,
154 Clk => clk,
155 reset => reset,
155 reset => reset,
156 SpiClk => DC_ADC_Sclk,
156 SpiClk => DC_ADC_Sclk,
157 DIN => DC_ADC_IN,
157 DIN => DC_ADC_IN,
158 SmplClk => DC_ADC_SmplClk,
158 SmplClk => DC_ADC_SmplClk,
159 OUT00 => AMR1X_Sync,
159 OUT00 => AMR1X_Sync,
160 OUT01 => AMR1Y_Sync,
160 OUT01 => AMR1Y_Sync,
161 OUT02 => AMR1Z_Sync,
161 OUT02 => AMR1Z_Sync,
162 OUT03 => AMR2X_Sync,
162 OUT03 => AMR2X_Sync,
163 OUT04 => AMR2Y_Sync,
163 OUT04 => AMR2Y_Sync,
164 OUT05 => AMR2Z_Sync,
164 OUT05 => AMR2Z_Sync,
165 OUT06 => Temp1_Sync,
165 OUT06 => Temp1_Sync,
166 OUT07 => Temp2_Sync,
166 OUT07 => Temp2_Sync,
167 OUT10 => AMR3X_Sync,
167 OUT10 => AMR3X_Sync,
168 OUT11 => AMR3Y_Sync,
168 OUT11 => AMR3Y_Sync,
169 OUT12 => AMR3Z_Sync,
169 OUT12 => AMR3Z_Sync,
170 OUT13 => AMR4X_Sync,
170 OUT13 => AMR4X_Sync,
171 OUT14 => AMR4Y_Sync,
171 OUT14 => AMR4Y_Sync,
172 OUT15 => AMR4Z_Sync,
172 OUT15 => AMR4Z_Sync,
173 OUT16 => Temp3_Sync,
173 OUT16 => Temp3_Sync,
174 OUT17 => Temp4_Sync,
174 OUT17 => Temp4_Sync,
175 FSynch => DC_ADC_FSynch
175 FSynch => DC_ADC_FSynch
176 );
176 );
177 END GENERATE;
177 END GENERATE;
178
178
179 END GENERATE;
179 END GENERATE;
180 ------------------------------------------------------------------
180 ------------------------------------------------------------------
181
181
182 NOADC: IF CstDATA = 1 GENERATE
182 NOADC: IF CstDATA = 1 GENERATE
183
183
184 AMR1X_Sync <= AMR1Xcst;
184 AMR1X_Sync <= AMR1Xcst;
185 AMR1Y_Sync <= AMR1Ycst;
185 AMR1Y_Sync <= AMR1Ycst;
186 AMR1Z_Sync <= AMR1Zcst;
186 AMR1Z_Sync <= AMR1Zcst;
187 AMR2X_Sync <= AMR2Xcst;
187 AMR2X_Sync <= AMR2Xcst;
188 AMR2Y_Sync <= AMR2Ycst;
188 AMR2Y_Sync <= AMR2Ycst;
189 AMR2Z_Sync <= AMR2Zcst;
189 AMR2Z_Sync <= AMR2Zcst;
190 Temp1_Sync <= Temp1cst;
190 Temp1_Sync <= Temp1cst;
191 Temp2_Sync <= Temp2cst;
191 Temp2_Sync <= Temp2cst;
192 AMR3X_Sync <= AMR3Xcst;
192 AMR3X_Sync <= AMR3Xcst;
193 AMR3Y_Sync <= AMR3Ycst;
193 AMR3Y_Sync <= AMR3Ycst;
194 AMR3Z_Sync <= AMR3Zcst;
194 AMR3Z_Sync <= AMR3Zcst;
195 AMR4X_Sync <= AMR4Xcst;
195 AMR4X_Sync <= AMR4Xcst;
196 AMR4Y_Sync <= AMR4Ycst;
196 AMR4Y_Sync <= AMR4Ycst;
197 AMR4Z_Sync <= AMR4Zcst;
197 AMR4Z_Sync <= AMR4Zcst;
198 Temp3_Sync <= Temp3cst;
198 Temp3_Sync <= Temp3cst;
199 Temp4_Sync <= Temp4cst;
199 Temp4_Sync <= Temp4cst;
200
200
201
201
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203
203
204
204
205 END GENERATE;
205 END GENERATE;
206
206
207
207
208
208
209
209
210 ------------------------------------------------------------------
210 ------------------------------------------------------------------
211 --
211 --
212 -- SET/RESET GEN
212 -- SET/RESET GEN
213 --
213 --
214 ------------------------------------------------------------------
214 ------------------------------------------------------------------
215
215
216 SR: IF EnableSR /=0 GENERATE
216 SR: IF EnableSR /=0 GENERATE
217 process(reset,DC_ADC_SmplClk)
217 process(reset,DC_ADC_SmplClk)
218 begin
218 begin
219 if reset = '0' then
219 if reset = '0' then
220 SET_RESET0_sig <= '0';
220 SET_RESET0_sig <= '0';
221 elsif DC_ADC_SmplClk'event and DC_ADC_SmplClk = '0' then
221 elsif DC_ADC_SmplClk'event and DC_ADC_SmplClk = '0' then
222 if(SET_RESET_counter = 31) then
222 if(SET_RESET_counter = 31) then
223 SET_RESET0_sig <= not SET_RESET0_sig;
223 SET_RESET0_sig <= not SET_RESET0_sig;
224 SET_RESET_counter <= 0;
224 SET_RESET_counter <= 0;
225 else
225 else
226 SET_RESET_counter <= SET_RESET_counter +1;
226 SET_RESET_counter <= SET_RESET_counter +1;
227 end if;
227 end if;
228 end if;
228 end if;
229 end process;
229 end process;
230
230
231 END GENERATE;
231 END GENERATE;
232 NOSR: IF EnableSR=0 GENERATE
232 NOSR: IF EnableSR=0 GENERATE
233 SET_RESET0_sig <= '0';
233 SET_RESET0_sig <= '0';
234 END GENERATE;
234 END GENERATE;
235
235
236 SET_RESET1_sig <= SET_RESET0_sig;
236 SET_RESET1_sig <= SET_RESET0_sig;
237 SET_RESET0 <= SET_RESET0_sig;
237 SET_RESET0 <= SET_RESET0_sig;
238 SET_RESET1 <= SET_RESET1_sig;
238 SET_RESET1 <= SET_RESET1_sig;
239 ------------------------------------------------------------------
239 ------------------------------------------------------------------
240 ------------------------------------------------------------------
240 ------------------------------------------------------------------
241
241
242
242
243 ------------------------------------------------------------------
243 ------------------------------------------------------------------
244 --
244 --
245 -- Cross domain clock synchronisation
245 -- Cross domain clock synchronisation
246 --
246 --
247 ------------------------------------------------------------------
247 ------------------------------------------------------------------
248
248
249 IF CDS =1 GENERATE
249 CDS0: IF CDS =1 GENERATE
250
250
251 AMR1Xsync: entity work.Fast2SlowSync
251 AMR1Xsync: entity work.Fast2SlowSync
252 generic map(N => 24)
252 generic map(N => 24)
253 port map( AMR1X_Sync,clk,sclk,SyncSig,AMR1X);
253 port map( AMR1X_Sync,clk,sclk,SyncSig,AMR1X);
254 AMR1Ysync: entity work.Fast2SlowSync
254 AMR1Ysync: entity work.Fast2SlowSync
255 generic map(N => 24)
255 generic map(N => 24)
256 port map( AMR1Y_Sync,clk,sclk,SyncSig,AMR1Y);
256 port map( AMR1Y_Sync,clk,sclk,SyncSig,AMR1Y);
257 AMR1Zsync: entity work.Fast2SlowSync
257 AMR1Zsync: entity work.Fast2SlowSync
258 generic map(N => 24)
258 generic map(N => 24)
259 port map( AMR1Z_Sync,clk,sclk,SyncSig,AMR1Z);
259 port map( AMR1Z_Sync,clk,sclk,SyncSig,AMR1Z);
260
260
261 AMR2Xsync: entity work.Fast2SlowSync
261 AMR2Xsync: entity work.Fast2SlowSync
262 generic map(N => 24)
262 generic map(N => 24)
263 port map( AMR2X_Sync,clk,sclk,SyncSig,AMR2X);
263 port map( AMR2X_Sync,clk,sclk,SyncSig,AMR2X);
264 AMR2Ysync: entity work.Fast2SlowSync
264 AMR2Ysync: entity work.Fast2SlowSync
265 generic map(N => 24)
265 generic map(N => 24)
266 port map( AMR2Y_Sync,clk,sclk,SyncSig,AMR2Y);
266 port map( AMR2Y_Sync,clk,sclk,SyncSig,AMR2Y);
267 AMR2Zsync: entity work.Fast2SlowSync
267 AMR2Zsync: entity work.Fast2SlowSync
268 generic map(N => 24)
268 generic map(N => 24)
269 port map( AMR2Z_Sync,clk,sclk,SyncSig,AMR2Z);
269 port map( AMR2Z_Sync,clk,sclk,SyncSig,AMR2Z);
270
270
271 AMR3Xsync: entity work.Fast2SlowSync
271 AMR3Xsync: entity work.Fast2SlowSync
272 generic map(N => 24)
272 generic map(N => 24)
273 port map( AMR3X_Sync,clk,sclk,SyncSig,AMR3X);
273 port map( AMR3X_Sync,clk,sclk,SyncSig,AMR3X);
274 AMR3Ysync: entity work.Fast2SlowSync
274 AMR3Ysync: entity work.Fast2SlowSync
275 generic map(N => 24)
275 generic map(N => 24)
276 port map( AMR3Y_Sync,clk,sclk,SyncSig,AMR3Y);
276 port map( AMR3Y_Sync,clk,sclk,SyncSig,AMR3Y);
277 AMR3Zsync: entity work.Fast2SlowSync
277 AMR3Zsync: entity work.Fast2SlowSync
278 generic map(N => 24)
278 generic map(N => 24)
279 port map( AMR3Z_Sync,clk,sclk,SyncSig,AMR3Z);
279 port map( AMR3Z_Sync,clk,sclk,SyncSig,AMR3Z);
280
280
281
281
282 AMR4Xsync: entity work.Fast2SlowSync
282 AMR4Xsync: entity work.Fast2SlowSync
283 generic map(N => 24)
283 generic map(N => 24)
284 port map( AMR4X_Sync,clk,sclk,SyncSig,AMR4X);
284 port map( AMR4X_Sync,clk,sclk,SyncSig,AMR4X);
285 AMR4Ysync: entity work.Fast2SlowSync
285 AMR4Ysync: entity work.Fast2SlowSync
286 generic map(N => 24)
286 generic map(N => 24)
287 port map( AMR4Y_Sync,clk,sclk,SyncSig,AMR4Y);
287 port map( AMR4Y_Sync,clk,sclk,SyncSig,AMR4Y);
288 AMR4Zsync: entity work.Fast2SlowSync
288 AMR4Zsync: entity work.Fast2SlowSync
289 generic map(N => 24)
289 generic map(N => 24)
290 port map( AMR4Z_Sync,clk,sclk,SyncSig,AMR4Z);
290 port map( AMR4Z_Sync,clk,sclk,SyncSig,AMR4Z);
291
291
292
292
293 TEMP1sync: entity work.Fast2SlowSync
293 TEMP1sync: entity work.Fast2SlowSync
294 generic map(N => 24)
294 generic map(N => 24)
295 port map( TEMP1_Sync,clk,sclk,SyncSig,TEMP1);
295 port map( TEMP1_Sync,clk,sclk,SyncSig,TEMP1);
296 TEMP2sync: entity work.Fast2SlowSync
296 TEMP2sync: entity work.Fast2SlowSync
297 generic map(N => 24)
297 generic map(N => 24)
298 port map( TEMP2_Sync,clk,sclk,SyncSig,TEMP2);
298 port map( TEMP2_Sync,clk,sclk,SyncSig,TEMP2);
299 TEMP3sync: entity work.Fast2SlowSync
299 TEMP3sync: entity work.Fast2SlowSync
300 generic map(N => 24)
300 generic map(N => 24)
301 port map( TEMP3_Sync,clk,sclk,SyncSig,TEMP3);
301 port map( TEMP3_Sync,clk,sclk,SyncSig,TEMP3);
302 TEMP4sync: entity work.Fast2SlowSync
302 TEMP4sync: entity work.Fast2SlowSync
303 generic map(N => 24)
303 generic map(N => 24)
304 port map( TEMP4_Sync,clk,sclk,SyncSig,TEMP4);
304 port map( TEMP4_Sync,clk,sclk,SyncSig,TEMP4);
305
305
306 END GENERATE;
306 END GENERATE;
307
307
308 IF CDS /= 1 GENERATE
308 IF CDS /= 1 GENERATE
309
309
310
310
311 AMR1X_Sync <= AMR1X;
311 AMR1X_Sync <= AMR1X;
312 AMR1Y_Sync <= AMR1Y;
312 AMR1Y_Sync <= AMR1Y;
313 AMR1Z_Sync <= AMR1Z;
313 AMR1Z_Sync <= AMR1Z;
314 AMR2X_Sync <= AMR2X;
314 AMR2X_Sync <= AMR2X;
315 AMR2Y_Sync <= AMR2Y;
315 AMR2Y_Sync <= AMR2Y;
316 AMR2Z_Sync <= AMR2Z;
316 AMR2Z_Sync <= AMR2Z;
317 Temp1_Sync <= Temp1;
317 Temp1_Sync <= Temp1;
318 Temp2_Sync <= Temp2;
318 Temp2_Sync <= Temp2;
319 AMR3X_Sync <= AMR3X;
319 AMR3X_Sync <= AMR3X;
320 AMR3Y_Sync <= AMR3Y;
320 AMR3Y_Sync <= AMR3Y;
321 AMR3Z_Sync <= AMR3Z;
321 AMR3Z_Sync <= AMR3Z;
322 AMR4X_Sync <= AMR4X;
322 AMR4X_Sync <= AMR4X;
323 AMR4Y_Sync <= AMR4Y;
323 AMR4Y_Sync <= AMR4Y;
324 AMR4Z_Sync <= AMR4Z;
324 AMR4Z_Sync <= AMR4Z;
325 Temp3_Sync <= Temp3;
325 Temp3_Sync <= Temp3;
326 Temp4_Sync <= Temp4;
326 Temp4_Sync <= Temp4;
327
327
328 END GENERATE;
328 END GENERATE;
329 ------------------------------------------------------------------
329 ------------------------------------------------------------------
330
330
331
331
332 end Behavioral;
332 end Behavioral;
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