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add RTAX post layout constraint
pellion -
r628:d5fcc754829e simu_with_Leon3
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Thu Jun 04 11:49:44 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_pad_25/U0:Y }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_1:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_1_0:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_1:Y }
28
29
30 ######## Generated Clock Constraints ########
31
32
33
34 ######## Clock Source Latency Constraints #########
35
36
37
38 ######## Input Delay Constraints ########
39
40 set_input_delay -max 10.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
41
42 set_input_delay -max 10.000 -clock { clk_25:Q } [get_ports { ADC_data }]
43
44
45
46 ######## Output Delay Constraints ########
47
48 set_max_delay 25.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
49 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
50 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
51 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
52
53 set_max_delay 25.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
54 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
55 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
56 address[7] address[8] address[9] }]
57
58 set_max_delay 25.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W nSRAM_G nSRAM_MBE}]
59
60 set_max_delay 25.000 -from [get_clocks {clk_25:Q}] -to [get_ports { ADC_OEB_bar_CH ADC_OEB_bar_HK }]
61
62 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { DAC_SCK DAC_SDO DAC_SYNC }]
63
64
65 ######## Delay Constraints ########
66
67 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
68 [get_clocks {spw_inputloop.0.spw_phy0/rxclki_1_0:Y}]
69
70 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to \
71 [get_clocks {spw_inputloop.1.spw_phy0/rxclki_1_0:Y}]
72
73
74 ######## Delay Constraints ########
75
76
77
78 ######## Multicycle Constraints ########
79
80
81
82 ######## False Path Constraints ########
83
84
85
86 ######## Output load Constraints ########
87
88
89
90 ######## Disable Timing Constraints #########
91
92
93
94 ######## Clock Uncertainty Constraints #########
95
96
97
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