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MINI LFR - WFP&MS - 0.1.7...
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r332:d5b2e267f44d (MINI-LFR) WFP_MS-0-1-7 JC
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_val : STD_LOGIC;
166 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL ADC_nCS_sig : STD_LOGIC;
167 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_CLK_sig : STD_LOGIC;
168 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
169 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170
170
171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172
172
173 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 -----------------------------------------------------------------------------
174 -----------------------------------------------------------------------------
175
175
176 BEGIN -- beh
176 BEGIN -- beh
177
177
178 -----------------------------------------------------------------------------
178 -----------------------------------------------------------------------------
179 -- CLK
179 -- CLK
180 -----------------------------------------------------------------------------
180 -----------------------------------------------------------------------------
181
181
182 PROCESS(clk_50)
182 PROCESS(clk_50)
183 BEGIN
183 BEGIN
184 IF clk_50'EVENT AND clk_50 = '1' THEN
184 IF clk_50'EVENT AND clk_50 = '1' THEN
185 clk_50_s <= NOT clk_50_s;
185 clk_50_s <= NOT clk_50_s;
186 END IF;
186 END IF;
187 END PROCESS;
187 END PROCESS;
188
188
189 PROCESS(clk_50_s)
189 PROCESS(clk_50_s)
190 BEGIN
190 BEGIN
191 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
191 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
192 clk_25 <= NOT clk_25;
192 clk_25 <= NOT clk_25;
193 END IF;
193 END IF;
194 END PROCESS;
194 END PROCESS;
195
195
196 PROCESS(clk_49)
196 PROCESS(clk_49)
197 BEGIN
197 BEGIN
198 IF clk_49'EVENT AND clk_49 = '1' THEN
198 IF clk_49'EVENT AND clk_49 = '1' THEN
199 clk_24 <= NOT clk_24;
199 clk_24 <= NOT clk_24;
200 END IF;
200 END IF;
201 END PROCESS;
201 END PROCESS;
202
202
203 -----------------------------------------------------------------------------
203 -----------------------------------------------------------------------------
204
204
205 PROCESS (clk_25, reset)
205 PROCESS (clk_25, reset)
206 BEGIN -- PROCESS
206 BEGIN -- PROCESS
207 IF reset = '0' THEN -- asynchronous reset (active low)
207 IF reset = '0' THEN -- asynchronous reset (active low)
208 LED0 <= '0';
208 LED0 <= '0';
209 LED1 <= '0';
209 LED1 <= '0';
210 LED2 <= '0';
210 LED2 <= '0';
211 --IO1 <= '0';
211 --IO1 <= '0';
212 --IO2 <= '1';
212 --IO2 <= '1';
213 --IO3 <= '0';
213 --IO3 <= '0';
214 --IO4 <= '0';
214 --IO4 <= '0';
215 --IO5 <= '0';
215 --IO5 <= '0';
216 --IO6 <= '0';
216 --IO6 <= '0';
217 --IO7 <= '0';
217 --IO7 <= '0';
218 --IO8 <= '0';
218 --IO8 <= '0';
219 --IO9 <= '0';
219 --IO9 <= '0';
220 --IO10 <= '0';
220 --IO10 <= '0';
221 --IO11 <= '0';
221 --IO11 <= '0';
222 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
222 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
223 LED0 <= '0';
223 LED0 <= '0';
224 LED1 <= '1';
224 LED1 <= '1';
225 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
225 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
226 --IO1 <= '1';
226 --IO1 <= '1';
227 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
227 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
228 --IO3 <= ADC_SDO(0);
228 --IO3 <= ADC_SDO(0);
229 --IO4 <= ADC_SDO(1);
229 --IO4 <= ADC_SDO(1);
230 --IO5 <= ADC_SDO(2);
230 --IO5 <= ADC_SDO(2);
231 --IO6 <= ADC_SDO(3);
231 --IO6 <= ADC_SDO(3);
232 --IO7 <= ADC_SDO(4);
232 --IO7 <= ADC_SDO(4);
233 --IO8 <= ADC_SDO(5);
233 --IO8 <= ADC_SDO(5);
234 --IO9 <= ADC_SDO(6);
234 --IO9 <= ADC_SDO(6);
235 --IO10 <= ADC_SDO(7);
235 --IO10 <= ADC_SDO(7);
236 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
236 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
237 END IF;
237 END IF;
238 END PROCESS;
238 END PROCESS;
239
239
240 PROCESS (clk_24, reset)
240 PROCESS (clk_24, reset)
241 BEGIN -- PROCESS
241 BEGIN -- PROCESS
242 IF reset = '0' THEN -- asynchronous reset (active low)
242 IF reset = '0' THEN -- asynchronous reset (active low)
243 I00_s <= '0';
243 I00_s <= '0';
244 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
244 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
245 I00_s <= NOT I00_s ;
245 I00_s <= NOT I00_s ;
246 END IF;
246 END IF;
247 END PROCESS;
247 END PROCESS;
248 -- IO0 <= I00_s;
248 -- IO0 <= I00_s;
249
249
250 --UARTs
250 --UARTs
251 nCTS1 <= '1';
251 nCTS1 <= '1';
252 nCTS2 <= '1';
252 nCTS2 <= '1';
253 nDCD2 <= '1';
253 nDCD2 <= '1';
254
254
255 --EXT CONNECTOR
255 --EXT CONNECTOR
256
256
257 --SPACE WIRE
257 --SPACE WIRE
258
258
259 leon3_soc_1 : leon3_soc
259 leon3_soc_1 : leon3_soc
260 GENERIC MAP (
260 GENERIC MAP (
261 fabtech => apa3e,
261 fabtech => apa3e,
262 memtech => apa3e,
262 memtech => apa3e,
263 padtech => inferred,
263 padtech => inferred,
264 clktech => inferred,
264 clktech => inferred,
265 disas => 0,
265 disas => 0,
266 dbguart => 0,
266 dbguart => 0,
267 pclow => 2,
267 pclow => 2,
268 clk_freq => 25000,
268 clk_freq => 25000,
269 NB_CPU => 1,
269 NB_CPU => 1,
270 ENABLE_FPU => 1,
270 ENABLE_FPU => 1,
271 FPU_NETLIST => 0,
271 FPU_NETLIST => 0,
272 ENABLE_DSU => 1,
272 ENABLE_DSU => 1,
273 ENABLE_AHB_UART => 1,
273 ENABLE_AHB_UART => 1,
274 ENABLE_APB_UART => 1,
274 ENABLE_APB_UART => 1,
275 ENABLE_IRQMP => 1,
275 ENABLE_IRQMP => 1,
276 ENABLE_GPT => 1,
276 ENABLE_GPT => 1,
277 NB_AHB_MASTER => NB_AHB_MASTER,
277 NB_AHB_MASTER => NB_AHB_MASTER,
278 NB_AHB_SLAVE => NB_AHB_SLAVE,
278 NB_AHB_SLAVE => NB_AHB_SLAVE,
279 NB_APB_SLAVE => NB_APB_SLAVE)
279 NB_APB_SLAVE => NB_APB_SLAVE)
280 PORT MAP (
280 PORT MAP (
281 clk => clk_25,
281 clk => clk_25,
282 reset => reset,
282 reset => reset,
283 errorn => errorn,
283 errorn => errorn,
284 ahbrxd => TXD1,
284 ahbrxd => TXD1,
285 ahbtxd => RXD1,
285 ahbtxd => RXD1,
286 urxd1 => TXD2,
286 urxd1 => TXD2,
287 utxd1 => RXD2,
287 utxd1 => RXD2,
288 address => SRAM_A,
288 address => SRAM_A,
289 data => SRAM_DQ,
289 data => SRAM_DQ,
290 nSRAM_BE0 => SRAM_nBE(0),
290 nSRAM_BE0 => SRAM_nBE(0),
291 nSRAM_BE1 => SRAM_nBE(1),
291 nSRAM_BE1 => SRAM_nBE(1),
292 nSRAM_BE2 => SRAM_nBE(2),
292 nSRAM_BE2 => SRAM_nBE(2),
293 nSRAM_BE3 => SRAM_nBE(3),
293 nSRAM_BE3 => SRAM_nBE(3),
294 nSRAM_WE => SRAM_nWE,
294 nSRAM_WE => SRAM_nWE,
295 nSRAM_CE => SRAM_CE,
295 nSRAM_CE => SRAM_CE,
296 nSRAM_OE => SRAM_nOE,
296 nSRAM_OE => SRAM_nOE,
297
297
298 apbi_ext => apbi_ext,
298 apbi_ext => apbi_ext,
299 apbo_ext => apbo_ext,
299 apbo_ext => apbo_ext,
300 ahbi_s_ext => ahbi_s_ext,
300 ahbi_s_ext => ahbi_s_ext,
301 ahbo_s_ext => ahbo_s_ext,
301 ahbo_s_ext => ahbo_s_ext,
302 ahbi_m_ext => ahbi_m_ext,
302 ahbi_m_ext => ahbi_m_ext,
303 ahbo_m_ext => ahbo_m_ext);
303 ahbo_m_ext => ahbo_m_ext);
304
304
305 -------------------------------------------------------------------------------
305 -------------------------------------------------------------------------------
306 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
306 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
307 -------------------------------------------------------------------------------
307 -------------------------------------------------------------------------------
308 apb_lfr_time_management_1 : apb_lfr_time_management
308 apb_lfr_time_management_1 : apb_lfr_time_management
309 GENERIC MAP (
309 GENERIC MAP (
310 pindex => 6,
310 pindex => 6,
311 paddr => 6,
311 paddr => 6,
312 pmask => 16#fff#,
312 pmask => 16#fff#,
313 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
313 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
314 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
314 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
315 PORT MAP (
315 PORT MAP (
316 clk25MHz => clk_25,
316 clk25MHz => clk_25,
317 clk24_576MHz => clk_24, -- 49.152MHz/2
317 clk24_576MHz => clk_24, -- 49.152MHz/2
318 resetn => reset,
318 resetn => reset,
319 grspw_tick => swno.tickout,
319 grspw_tick => swno.tickout,
320 apbi => apbi_ext,
320 apbi => apbi_ext,
321 apbo => apbo_ext(6),
321 apbo => apbo_ext(6),
322 coarse_time => coarse_time,
322 coarse_time => coarse_time,
323 fine_time => fine_time);
323 fine_time => fine_time);
324
324
325 -----------------------------------------------------------------------
325 -----------------------------------------------------------------------
326 --- SpaceWire --------------------------------------------------------
326 --- SpaceWire --------------------------------------------------------
327 -----------------------------------------------------------------------
327 -----------------------------------------------------------------------
328
328
329 SPW_EN <= '1';
329 SPW_EN <= '1';
330
330
331 spw_clk <= clk_50_s;
331 spw_clk <= clk_50_s;
332 spw_rxtxclk <= spw_clk;
332 spw_rxtxclk <= spw_clk;
333 spw_rxclkn <= NOT spw_rxtxclk;
333 spw_rxclkn <= NOT spw_rxtxclk;
334
334
335 -- PADS for SPW1
335 -- PADS for SPW1
336 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
336 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
337 PORT MAP (SPW_NOM_DIN, dtmp(0));
337 PORT MAP (SPW_NOM_DIN, dtmp(0));
338 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
338 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
339 PORT MAP (SPW_NOM_SIN, stmp(0));
339 PORT MAP (SPW_NOM_SIN, stmp(0));
340 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
340 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
341 PORT MAP (SPW_NOM_DOUT, swno.d(0));
341 PORT MAP (SPW_NOM_DOUT, swno.d(0));
342 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
342 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
343 PORT MAP (SPW_NOM_SOUT, swno.s(0));
343 PORT MAP (SPW_NOM_SOUT, swno.s(0));
344 -- PADS FOR SPW2
344 -- PADS FOR SPW2
345 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
345 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
346 PORT MAP (SPW_RED_SIN, dtmp(1));
346 PORT MAP (SPW_RED_SIN, dtmp(1));
347 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
347 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
348 PORT MAP (SPW_RED_DIN, stmp(1));
348 PORT MAP (SPW_RED_DIN, stmp(1));
349 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
349 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
350 PORT MAP (SPW_RED_DOUT, swno.d(1));
350 PORT MAP (SPW_RED_DOUT, swno.d(1));
351 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
351 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
352 PORT MAP (SPW_RED_SOUT, swno.s(1));
352 PORT MAP (SPW_RED_SOUT, swno.s(1));
353
353
354 -- GRSPW PHY
354 -- GRSPW PHY
355 --spw1_input: if CFG_SPW_GRSPW = 1 generate
355 --spw1_input: if CFG_SPW_GRSPW = 1 generate
356 spw_inputloop : FOR j IN 0 TO 1 GENERATE
356 spw_inputloop : FOR j IN 0 TO 1 GENERATE
357 spw_phy0 : grspw_phy
357 spw_phy0 : grspw_phy
358 GENERIC MAP(
358 GENERIC MAP(
359 tech => apa3e,
359 tech => apa3e,
360 rxclkbuftype => 1,
360 rxclkbuftype => 1,
361 scantest => 0)
361 scantest => 0)
362 PORT MAP(
362 PORT MAP(
363 rxrst => swno.rxrst,
363 rxrst => swno.rxrst,
364 di => dtmp(j),
364 di => dtmp(j),
365 si => stmp(j),
365 si => stmp(j),
366 rxclko => spw_rxclk(j),
366 rxclko => spw_rxclk(j),
367 do => swni.d(j),
367 do => swni.d(j),
368 ndo => swni.nd(j*5+4 DOWNTO j*5),
368 ndo => swni.nd(j*5+4 DOWNTO j*5),
369 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
369 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
370 END GENERATE spw_inputloop;
370 END GENERATE spw_inputloop;
371
371
372 -- SPW core
372 -- SPW core
373 sw0 : grspwm GENERIC MAP(
373 sw0 : grspwm GENERIC MAP(
374 tech => apa3e,
374 tech => apa3e,
375 hindex => 1,
375 hindex => 1,
376 pindex => 5,
376 pindex => 5,
377 paddr => 5,
377 paddr => 5,
378 pirq => 11,
378 pirq => 11,
379 sysfreq => 25000, -- CPU_FREQ
379 sysfreq => 25000, -- CPU_FREQ
380 rmap => 1,
380 rmap => 1,
381 rmapcrc => 1,
381 rmapcrc => 1,
382 fifosize1 => 16,
382 fifosize1 => 16,
383 fifosize2 => 16,
383 fifosize2 => 16,
384 rxclkbuftype => 1,
384 rxclkbuftype => 1,
385 rxunaligned => 0,
385 rxunaligned => 0,
386 rmapbufs => 4,
386 rmapbufs => 4,
387 ft => 0,
387 ft => 0,
388 netlist => 0,
388 netlist => 0,
389 ports => 2,
389 ports => 2,
390 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
390 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
391 memtech => apa3e,
391 memtech => apa3e,
392 destkey => 2,
392 destkey => 2,
393 spwcore => 1
393 spwcore => 1
394 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
394 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
395 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
395 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
396 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
396 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
397 )
397 )
398 PORT MAP(reset, clk_25, spw_rxclk(0),
398 PORT MAP(reset, clk_25, spw_rxclk(0),
399 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
399 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
400 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
400 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
401 swni, swno);
401 swni, swno);
402
402
403 swni.tickin <= '0';
403 swni.tickin <= '0';
404 swni.rmapen <= '1';
404 swni.rmapen <= '1';
405 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
405 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
406 swni.tickinraw <= '0';
406 swni.tickinraw <= '0';
407 swni.timein <= (OTHERS => '0');
407 swni.timein <= (OTHERS => '0');
408 swni.dcrstval <= (OTHERS => '0');
408 swni.dcrstval <= (OTHERS => '0');
409 swni.timerrstval <= (OTHERS => '0');
409 swni.timerrstval <= (OTHERS => '0');
410
410
411 -------------------------------------------------------------------------------
411 -------------------------------------------------------------------------------
412 -- LFR ------------------------------------------------------------------------
412 -- LFR ------------------------------------------------------------------------
413 -------------------------------------------------------------------------------
413 -------------------------------------------------------------------------------
414 lpp_lfr_1 : lpp_lfr
414 lpp_lfr_1 : lpp_lfr
415 GENERIC MAP (
415 GENERIC MAP (
416 Mem_use => use_RAM,
416 Mem_use => use_RAM,
417 nb_data_by_buffer_size => 32,
417 nb_data_by_buffer_size => 32,
418 nb_word_by_buffer_size => 30,
418 nb_word_by_buffer_size => 30,
419 nb_snapshot_param_size => 32,
419 nb_snapshot_param_size => 32,
420 delta_vector_size => 32,
420 delta_vector_size => 32,
421 delta_vector_size_f0_2 => 7, -- log2(96)
421 delta_vector_size_f0_2 => 7, -- log2(96)
422 pindex => 15,
422 pindex => 15,
423 paddr => 15,
423 paddr => 15,
424 pmask => 16#fff#,
424 pmask => 16#fff#,
425 pirq_ms => 6,
425 pirq_ms => 6,
426 pirq_wfp => 14,
426 pirq_wfp => 14,
427 hindex => 2,
427 hindex => 2,
428 top_lfr_version => X"000106") -- aa.bb.cc version
428 top_lfr_version => X"000107") -- aa.bb.cc version
429 PORT MAP (
429 PORT MAP (
430 clk => clk_25,
430 clk => clk_25,
431 rstn => reset,
431 rstn => reset,
432 sample_B => sample(2 DOWNTO 0),
432 sample_B => sample(2 DOWNTO 0),
433 sample_E => sample(7 DOWNTO 3),
433 sample_E => sample(7 DOWNTO 3),
434 sample_val => sample_val,
434 sample_val => sample_val,
435 apbi => apbi_ext,
435 apbi => apbi_ext,
436 apbo => apbo_ext(15),
436 apbo => apbo_ext(15),
437 ahbi => ahbi_m_ext,
437 ahbi => ahbi_m_ext,
438 ahbo => ahbo_m_ext(2),
438 ahbo => ahbo_m_ext(2),
439 coarse_time => coarse_time,
439 coarse_time => coarse_time,
440 fine_time => fine_time,
440 fine_time => fine_time,
441 data_shaping_BW => bias_fail_sw_sig,
441 data_shaping_BW => bias_fail_sw_sig,
442 observation_reg => observation_reg);
442 observation_reg => observation_reg);
443
443
444 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
444 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
445 GENERIC MAP(
445 GENERIC MAP(
446 ChannelCount => 8,
446 ChannelCount => 8,
447 SampleNbBits => 14,
447 SampleNbBits => 14,
448 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
448 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
449 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
449 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
450 PORT MAP (
450 PORT MAP (
451 -- CONV
451 -- CONV
452 cnv_clk => clk_24,
452 cnv_clk => clk_24,
453 cnv_rstn => reset,
453 cnv_rstn => reset,
454 cnv => ADC_nCS_sig,
454 cnv => ADC_nCS_sig,
455 -- DATA
455 -- DATA
456 clk => clk_25,
456 clk => clk_25,
457 rstn => reset,
457 rstn => reset,
458 sck => ADC_CLK_sig,
458 sck => ADC_CLK_sig,
459 sdo => ADC_SDO_sig,
459 sdo => ADC_SDO_sig,
460 -- SAMPLE
460 -- SAMPLE
461 sample => sample,
461 sample => sample,
462 sample_val => sample_val);
462 sample_val => sample_val);
463
463
464 --IO10 <= ADC_SDO_sig(5);
464 --IO10 <= ADC_SDO_sig(5);
465 --IO9 <= ADC_SDO_sig(4);
465 --IO9 <= ADC_SDO_sig(4);
466 --IO8 <= ADC_SDO_sig(3);
466 --IO8 <= ADC_SDO_sig(3);
467
467
468 ADC_nCS <= ADC_nCS_sig;
468 ADC_nCS <= ADC_nCS_sig;
469 ADC_CLK <= ADC_CLK_sig;
469 ADC_CLK <= ADC_CLK_sig;
470 ADC_SDO_sig <= ADC_SDO;
470 ADC_SDO_sig <= ADC_SDO;
471
471
472 ----------------------------------------------------------------------
472 ----------------------------------------------------------------------
473 --- GPIO -----------------------------------------------------------
473 --- GPIO -----------------------------------------------------------
474 ----------------------------------------------------------------------
474 ----------------------------------------------------------------------
475
475
476 grgpio0 : grgpio
476 grgpio0 : grgpio
477 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
477 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
478 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
478 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
479
479
480 --pio_pad_0 : iopad
480 --pio_pad_0 : iopad
481 -- GENERIC MAP (tech => CFG_PADTECH)
481 -- GENERIC MAP (tech => CFG_PADTECH)
482 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
482 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
483 --pio_pad_1 : iopad
483 --pio_pad_1 : iopad
484 -- GENERIC MAP (tech => CFG_PADTECH)
484 -- GENERIC MAP (tech => CFG_PADTECH)
485 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
485 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
486 --pio_pad_2 : iopad
486 --pio_pad_2 : iopad
487 -- GENERIC MAP (tech => CFG_PADTECH)
487 -- GENERIC MAP (tech => CFG_PADTECH)
488 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
488 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
489 --pio_pad_3 : iopad
489 --pio_pad_3 : iopad
490 -- GENERIC MAP (tech => CFG_PADTECH)
490 -- GENERIC MAP (tech => CFG_PADTECH)
491 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
491 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
492 --pio_pad_4 : iopad
492 --pio_pad_4 : iopad
493 -- GENERIC MAP (tech => CFG_PADTECH)
493 -- GENERIC MAP (tech => CFG_PADTECH)
494 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
494 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
495 --pio_pad_5 : iopad
495 --pio_pad_5 : iopad
496 -- GENERIC MAP (tech => CFG_PADTECH)
496 -- GENERIC MAP (tech => CFG_PADTECH)
497 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
497 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
498 --pio_pad_6 : iopad
498 --pio_pad_6 : iopad
499 -- GENERIC MAP (tech => CFG_PADTECH)
499 -- GENERIC MAP (tech => CFG_PADTECH)
500 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
500 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
501 --pio_pad_7 : iopad
501 --pio_pad_7 : iopad
502 -- GENERIC MAP (tech => CFG_PADTECH)
502 -- GENERIC MAP (tech => CFG_PADTECH)
503 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
503 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
504
504
505 PROCESS (clk_25, reset)
505 PROCESS (clk_25, reset)
506 BEGIN -- PROCESS
506 BEGIN -- PROCESS
507 IF reset = '0' THEN -- asynchronous reset (active low)
507 IF reset = '0' THEN -- asynchronous reset (active low)
508 IO0 <= '0';
508 IO0 <= '0';
509 IO1 <= '0';
509 IO1 <= '0';
510 IO2 <= '0';
510 IO2 <= '0';
511 IO3 <= '0';
511 IO3 <= '0';
512 IO4 <= '0';
512 IO4 <= '0';
513 IO5 <= '0';
513 IO5 <= '0';
514 IO6 <= '0';
514 IO6 <= '0';
515 IO7 <= '0';
515 IO7 <= '0';
516 IO8 <= '0';
516 IO8 <= '0';
517 IO9 <= '0';
517 IO9 <= '0';
518 IO10 <= '0';
518 IO10 <= '0';
519 IO11 <= '0';
519 IO11 <= '0';
520 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
520 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
521 CASE gpioo.dout(1 DOWNTO 0) IS
521 CASE gpioo.dout(1 DOWNTO 0) IS
522 WHEN "00" =>
522 WHEN "00" =>
523 IO0 <= observation_reg(0 );
523 IO0 <= observation_reg(0 );
524 IO1 <= observation_reg(1 );
524 IO1 <= observation_reg(1 );
525 IO2 <= observation_reg(2 );
525 IO2 <= observation_reg(2 );
526 IO3 <= observation_reg(3 );
526 IO3 <= observation_reg(3 );
527 IO4 <= observation_reg(4 );
527 IO4 <= observation_reg(4 );
528 IO5 <= observation_reg(5 );
528 IO5 <= observation_reg(5 );
529 IO6 <= observation_reg(6 );
529 IO6 <= observation_reg(6 );
530 IO7 <= observation_reg(7 );
530 IO7 <= observation_reg(7 );
531 IO8 <= observation_reg(8 );
531 IO8 <= observation_reg(8 );
532 IO9 <= observation_reg(9 );
532 IO9 <= observation_reg(9 );
533 IO10 <= observation_reg(10);
533 IO10 <= observation_reg(10);
534 IO11 <= observation_reg(11);
534 IO11 <= observation_reg(11);
535 WHEN "01" =>
535 WHEN "01" =>
536 IO0 <= observation_reg(0 + 12);
536 IO0 <= observation_reg(0 + 12);
537 IO1 <= observation_reg(1 + 12);
537 IO1 <= observation_reg(1 + 12);
538 IO2 <= observation_reg(2 + 12);
538 IO2 <= observation_reg(2 + 12);
539 IO3 <= observation_reg(3 + 12);
539 IO3 <= observation_reg(3 + 12);
540 IO4 <= observation_reg(4 + 12);
540 IO4 <= observation_reg(4 + 12);
541 IO5 <= observation_reg(5 + 12);
541 IO5 <= observation_reg(5 + 12);
542 IO6 <= observation_reg(6 + 12);
542 IO6 <= observation_reg(6 + 12);
543 IO7 <= observation_reg(7 + 12);
543 IO7 <= observation_reg(7 + 12);
544 IO8 <= observation_reg(8 + 12);
544 IO8 <= observation_reg(8 + 12);
545 IO9 <= observation_reg(9 + 12);
545 IO9 <= observation_reg(9 + 12);
546 IO10 <= observation_reg(10 + 12);
546 IO10 <= observation_reg(10 + 12);
547 IO11 <= observation_reg(11 + 12);
547 IO11 <= observation_reg(11 + 12);
548 WHEN "10" =>
548 WHEN "10" =>
549 IO0 <= observation_reg(0 + 12 + 12);
549 IO0 <= observation_reg(0 + 12 + 12);
550 IO1 <= observation_reg(1 + 12 + 12);
550 IO1 <= observation_reg(1 + 12 + 12);
551 IO2 <= observation_reg(2 + 12 + 12);
551 IO2 <= observation_reg(2 + 12 + 12);
552 IO3 <= observation_reg(3 + 12 + 12);
552 IO3 <= observation_reg(3 + 12 + 12);
553 IO4 <= observation_reg(4 + 12 + 12);
553 IO4 <= observation_reg(4 + 12 + 12);
554 IO5 <= observation_reg(5 + 12 + 12);
554 IO5 <= observation_reg(5 + 12 + 12);
555 IO6 <= observation_reg(6 + 12 + 12);
555 IO6 <= observation_reg(6 + 12 + 12);
556 IO7 <= observation_reg(7 + 12 + 12);
556 IO7 <= observation_reg(7 + 12 + 12);
557 IO8 <= '0';
557 IO8 <= '0';
558 IO9 <= '0';
558 IO9 <= '0';
559 IO10 <= '0';
559 IO10 <= '0';
560 IO11 <= '0';
560 IO11 <= '0';
561 WHEN "11" =>
561 WHEN "11" =>
562 IO0 <= '0';
562 IO0 <= '0';
563 IO1 <= '0';
563 IO1 <= '0';
564 IO2 <= '0';
564 IO2 <= '0';
565 IO3 <= '0';
565 IO3 <= '0';
566 IO4 <= '0';
566 IO4 <= '0';
567 IO5 <= '0';
567 IO5 <= '0';
568 IO6 <= '0';
568 IO6 <= '0';
569 IO7 <= '0';
569 IO7 <= '0';
570 IO8 <= '0';
570 IO8 <= '0';
571 IO9 <= '0';
571 IO9 <= '0';
572 IO10 <= '0';
572 IO10 <= '0';
573 IO11 <= '0';
573 IO11 <= '0';
574 WHEN OTHERS => NULL;
574 WHEN OTHERS => NULL;
575 END CASE;
575 END CASE;
576
576
577 END IF;
577 END IF;
578 END PROCESS;
578 END PROCESS;
579
579
580 END beh; No newline at end of file
580 END beh;
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@@ -1,254 +1,292
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22
22
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE IEEE.NUMERIC_STD.ALL;
25 USE IEEE.NUMERIC_STD.ALL;
26
26
27 LIBRARY grlib;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
30 USE grlib.devices.ALL;
31
31
32 LIBRARY lpp;
32 LIBRARY lpp;
33 USE lpp.lpp_lfr_time_management.ALL;
33 USE lpp.lpp_lfr_time_management.ALL;
34
34
35 ENTITY TB IS
35 ENTITY TB IS
36
36
37 PORT (
37 PORT (
38 SIM_OK : OUT STD_LOGIC
38 SIM_OK : OUT STD_LOGIC
39 );
39 );
40
40
41 END TB;
41 END TB;
42
42
43
43
44 ARCHITECTURE beh OF TB IS
44 ARCHITECTURE beh OF TB IS
45
45
46 SIGNAL clk25MHz : STD_LOGIC := '0';
46 SIGNAL clk25MHz : STD_LOGIC := '0';
47 SIGNAL clk24_576MHz : STD_LOGIC := '0';
47 SIGNAL clk24_576MHz : STD_LOGIC := '0';
48 SIGNAL resetn : STD_LOGIC;
48 SIGNAL resetn : STD_LOGIC;
49 SIGNAL grspw_tick : STD_LOGIC;
49 SIGNAL grspw_tick : STD_LOGIC;
50 SIGNAL apbi : apb_slv_in_type;
50 SIGNAL apbi : apb_slv_in_type;
51 SIGNAL apbo : apb_slv_out_type;
51 SIGNAL apbo : apb_slv_out_type;
52 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
52 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
53 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
53 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
54
54
55 SIGNAL TB_string : STRING(1 TO 8):= "12345678";
55 SIGNAL TB_string : STRING(1 TO 8):= "12345678";
56
56
57 SIGNAL coarse_time_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
57 SIGNAL coarse_time_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
58 SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
58 SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
59 SIGNAL global_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
59 SIGNAL global_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
60 SIGNAL global_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
60 SIGNAL global_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
61 SIGNAL tick_ongoing : STD_LOGIC;
61 SIGNAL tick_ongoing : STD_LOGIC;
62
62
63 SIGNAL ASSERTION_1 : STD_LOGIC;
63 SIGNAL ASSERTION_1 : STD_LOGIC;
64 SIGNAL ASSERTION_2 : STD_LOGIC;
64 SIGNAL ASSERTION_2 : STD_LOGIC;
65 SIGNAL ASSERTION_3 : STD_LOGIC;
65 SIGNAL ASSERTION_3 : STD_LOGIC;
66
66
67 BEGIN -- beh
67 BEGIN -- beh
68
68
69 apb_lfr_time_management_1: apb_lfr_time_management
69 apb_lfr_time_management_1: apb_lfr_time_management
70 GENERIC MAP (
70 GENERIC MAP (
71 pindex => 0,
71 pindex => 0,
72 paddr => 0,
72 paddr => 0,
73 pmask => 16#fff#,
73 pmask => 16#fff#,
74 FIRST_DIVISION => 20,
74 FIRST_DIVISION => 20,
75 NB_SECOND_DESYNC => 4)
75 NB_SECOND_DESYNC => 4)
76 PORT MAP (
76 PORT MAP (
77 clk25MHz => clk25MHz,
77 clk25MHz => clk25MHz,
78 clk24_576MHz => clk24_576MHz,
78 clk24_576MHz => clk24_576MHz,
79 resetn => resetn,
79 resetn => resetn,
80 grspw_tick => grspw_tick,
80 grspw_tick => grspw_tick,
81 apbi => apbi,
81 apbi => apbi,
82 apbo => apbo,
82 apbo => apbo,
83 coarse_time => coarse_time,
83 coarse_time => coarse_time,
84 fine_time => fine_time);
84 fine_time => fine_time);
85
85
86 clk25MHz <= NOT clk25MHz AFTER 20000 ps;
86 clk25MHz <= NOT clk25MHz AFTER 20000 ps;
87 clk24_576MHz <= NOT clk24_576MHz AFTER 20345 ps;
87 clk24_576MHz <= NOT clk24_576MHz AFTER 20345 ps;
88
88
89
89
90
90
91
91
92 PROCESS
92 PROCESS
93 BEGIN -- PROCESS
93 BEGIN -- PROCESS
94 WAIT UNTIL clk25MHz = '1';
94 WAIT UNTIL clk25MHz = '1';
95 TB_string <= "RESET ";
95 TB_string <= "RESET ";
96
96
97 resetn <= '0';
97 resetn <= '0';
98
98
99 apbi.psel(0) <= '0';
99 apbi.psel(0) <= '0';
100 apbi.pwrite <= '0';
100 apbi.pwrite <= '0';
101 apbi.penable <= '0';
101 apbi.penable <= '0';
102 apbi.paddr <= (OTHERS => '0');
102 apbi.paddr <= (OTHERS => '0');
103 apbi.pwdata <= (OTHERS => '0');
103 apbi.pwdata <= (OTHERS => '0');
104 grspw_tick <= '0';
104 grspw_tick <= '0';
105 WAIT UNTIL clk25MHz = '1';
105 WAIT UNTIL clk25MHz = '1';
106 WAIT UNTIL clk25MHz = '1';
106 WAIT UNTIL clk25MHz = '1';
107 resetn <= '1';
107 resetn <= '1';
108 WAIT FOR 60 ms;
108 WAIT FOR 60 ms;
109 ---------------------------------------------------------------------------
109 ---------------------------------------------------------------------------
110 -- DESYNC TO SYNC
110 -- DESYNC TO SYNC
111 ---------------------------------------------------------------------------
111 ---------------------------------------------------------------------------
112 WAIT UNTIL clk25MHz = '1';
112 WAIT UNTIL clk25MHz = '1';
113 TB_string <= "TICK 1 ";
113 TB_string <= "TICK 1 ";
114 grspw_tick <= '1';------------------------------------------------------1
114 grspw_tick <= '1';------------------------------------------------------1
115 WAIT UNTIL clk25MHz = '1';
115 WAIT UNTIL clk25MHz = '1';
116 grspw_tick <= '0';
116 grspw_tick <= '0';
117 WAIT FOR 53333 us;
117 WAIT FOR 53333 us;
118 WAIT UNTIL clk25MHz = '1';
118 WAIT UNTIL clk25MHz = '1';
119 TB_string <= "TICK 2 ";
119 TB_string <= "TICK 2 ";
120 grspw_tick <= '1';------------------------------------------------------2
120 grspw_tick <= '1';------------------------------------------------------2
121 WAIT UNTIL clk25MHz = '1';
121 WAIT UNTIL clk25MHz = '1';
122 grspw_tick <= '0';
122 grspw_tick <= '0';
123 WAIT FOR 56000 us;
123 WAIT FOR 56000 us;
124 WAIT UNTIL clk25MHz = '1';
124 WAIT UNTIL clk25MHz = '1';
125 TB_string <= "TICK 3 ";
125 TB_string <= "TICK 3 ";
126 grspw_tick <= '1';------------------------------------------------------3
126 grspw_tick <= '1';------------------------------------------------------3
127 WAIT UNTIL clk25MHz = '1';
127 WAIT UNTIL clk25MHz = '1';
128 grspw_tick <= '0';
128 grspw_tick <= '0';
129 WAIT FOR 200 ms;
129 WAIT FOR 200 ms;
130 WAIT UNTIL clk25MHz = '1';
130 WAIT UNTIL clk25MHz = '1';
131 TB_string <= "CT new ";
131 TB_string <= "CT new ";
132 -- WRITE NEW COARSE_TIME
132 -- WRITE NEW COARSE_TIME
133 apbi.psel(0) <= '1';
133 apbi.psel(0) <= '1';
134 apbi.pwrite <= '1';
134 apbi.pwrite <= '1';
135 apbi.penable <= '1';
135 apbi.penable <= '1';
136 apbi.paddr <= X"00000004";
136 apbi.paddr <= X"00000004";
137 apbi.pwdata <= X"00001234";
137 apbi.pwdata <= X"00001234";
138 WAIT UNTIL clk25MHz = '1';
138 WAIT UNTIL clk25MHz = '1';
139 apbi.psel(0) <= '0';
139 apbi.psel(0) <= '0';
140 apbi.pwrite <= '0';
140 apbi.pwrite <= '0';
141 apbi.penable <= '0';
141 apbi.penable <= '0';
142 apbi.paddr <= (OTHERS => '0');
142 apbi.paddr <= (OTHERS => '0');
143 apbi.pwdata <= (OTHERS => '0');
143 apbi.pwdata <= (OTHERS => '0');
144 WAIT UNTIL clk25MHz = '1';
144 WAIT UNTIL clk25MHz = '1';
145
145
146 WAIT FOR 10 ms;
146 WAIT FOR 10 ms;
147 WAIT UNTIL clk25MHz = '1';
147 WAIT UNTIL clk25MHz = '1';
148 TB_string <= "TICK 4 ";
148 TB_string <= "TICK 4 ";
149 grspw_tick <= '1';------------------------------------------------------3
149 grspw_tick <= '1';------------------------------------------------------3
150 WAIT UNTIL clk25MHz = '1';
150 WAIT UNTIL clk25MHz = '1';
151 grspw_tick <= '0';
151 grspw_tick <= '0';
152
152
153
153 WAIT FOR 250 ms;
154
154 TB_string <= "READ 1 ";
155
155 apbi.psel(0) <= '1';
156 WAIT FOR 750 ms;
156 apbi.pwrite <= '0';
157 apbi.penable <= '1';
158 apbi.paddr <= X"00000008";
159 WAIT UNTIL clk25MHz = '1';
160 apbi.psel(0) <= '0';
161 apbi.pwrite <= '0';
162 apbi.penable <= '0';
163 apbi.paddr <= (OTHERS => '0');
164 WAIT UNTIL clk25MHz = '1';
165 WAIT FOR 250 ms;
166 TB_string <= "READ 2 ";
167 apbi.psel(0) <= '1';
168 apbi.pwrite <= '0';
169 apbi.penable <= '1';
170 apbi.paddr <= X"00000008";
171 WAIT UNTIL clk25MHz = '1';
172 apbi.psel(0) <= '0';
173 apbi.pwrite <= '0';
174 apbi.penable <= '0';
175 apbi.paddr <= (OTHERS => '0');
176 WAIT UNTIL clk25MHz = '1';
177 WAIT FOR 250 ms;
178 TB_string <= "READ 3 ";
179 apbi.psel(0) <= '1';
180 apbi.pwrite <= '0';
181 apbi.penable <= '1';
182 apbi.paddr <= X"00000008";
183 WAIT UNTIL clk25MHz = '1';
184 apbi.psel(0) <= '0';
185 apbi.pwrite <= '0';
186 apbi.penable <= '0';
187 apbi.paddr <= (OTHERS => '0');
188 WAIT UNTIL clk25MHz = '1';
189
190
157
191
158 REPORT "*** END simulation ***" SEVERITY failure;
192 REPORT "*** END simulation ***" SEVERITY failure;
159 WAIT;
193 WAIT;
160
194
161 END PROCESS;
195 END PROCESS;
162
196
163
197
198 -----------------------------------------------------------------------------
199 --
200 -----------------------------------------------------------------------------
201
164 global_time <= coarse_time & fine_time;
202 global_time <= coarse_time & fine_time;
165
203
166 PROCESS (clk25MHz, resetn)
204 PROCESS (clk25MHz, resetn)
167 BEGIN -- PROCESS
205 BEGIN -- PROCESS
168 IF resetn = '0' THEN -- asynchronous reset (active low)
206 IF resetn = '0' THEN -- asynchronous reset (active low)
169 coarse_time_reg <= (OTHERS => '0');
207 coarse_time_reg <= (OTHERS => '0');
170 fine_time_reg <= (OTHERS => '0');
208 fine_time_reg <= (OTHERS => '0');
171 global_time_reg <= (OTHERS => '0');
209 global_time_reg <= (OTHERS => '0');
172 tick_ongoing <= '0';
210 tick_ongoing <= '0';
173 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
211 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
174 global_time_reg <= global_time;
212 global_time_reg <= global_time;
175 coarse_time_reg <= coarse_time;
213 coarse_time_reg <= coarse_time;
176 fine_time_reg <= fine_time;
214 fine_time_reg <= fine_time;
177 IF grspw_tick ='1' THEN
215 IF grspw_tick ='1' THEN
178 tick_ongoing <= '1';
216 tick_ongoing <= '1';
179 ELSIF tick_ongoing = '1' THEN
217 ELSIF tick_ongoing = '1' THEN
180 IF (fine_time_reg /= fine_time) OR (coarse_time_reg /= coarse_time) THEN
218 IF (fine_time_reg /= fine_time) OR (coarse_time_reg /= coarse_time) THEN
181 tick_ongoing <= '0';
219 tick_ongoing <= '0';
182 END IF;
220 END IF;
183 END IF;
221 END IF;
184
222
185 END IF;
223 END IF;
186 END PROCESS;
224 END PROCESS;
187
225
188 -----------------------------------------------------------------------------
226 -----------------------------------------------------------------------------
189 -- ASSERTION 1 :
227 -- ASSERTION 1 :
190 -- Coarse_time "changed" => FINE_TIME = 0
228 -- Coarse_time "changed" => FINE_TIME = 0
191 -- False after a TRANSITION !
229 -- False after a TRANSITION !
192 -----------------------------------------------------------------------------
230 -----------------------------------------------------------------------------
193 PROCESS (clk25MHz, resetn)
231 PROCESS (clk25MHz, resetn)
194 BEGIN -- PROCESS
232 BEGIN -- PROCESS
195 IF resetn = '0' THEN -- asynchronous reset (active low)
233 IF resetn = '0' THEN -- asynchronous reset (active low)
196 ASSERTION_1 <= '1';
234 ASSERTION_1 <= '1';
197 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
235 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
198 IF coarse_time /= coarse_time_reg THEN
236 IF coarse_time /= coarse_time_reg THEN
199 IF fine_time /= X"0000" THEN
237 IF fine_time /= X"0000" THEN
200 IF fine_time /= X"0041" THEN
238 IF fine_time /= X"0041" THEN
201 ASSERTION_1 <= '0';
239 ASSERTION_1 <= '0';
202 ELSE
240 ELSE
203 ASSERTION_1 <= 'U';
241 ASSERTION_1 <= 'U';
204 END IF;
242 END IF;
205 ELSE
243 ELSE
206 ASSERTION_1 <= '1';
244 ASSERTION_1 <= '1';
207 END IF;
245 END IF;
208 END IF;
246 END IF;
209 END IF;
247 END IF;
210 END PROCESS;
248 END PROCESS;
211
249
212 -----------------------------------------------------------------------------
250 -----------------------------------------------------------------------------
213 -- ASSERTION 2 :
251 -- ASSERTION 2 :
214 -- tick => next(FINE_TIME) = 0
252 -- tick => next(FINE_TIME) = 0
215 -----------------------------------------------------------------------------
253 -----------------------------------------------------------------------------
216 PROCESS (clk25MHz, resetn)
254 PROCESS (clk25MHz, resetn)
217 BEGIN -- PROCESS
255 BEGIN -- PROCESS
218 IF resetn = '0' THEN -- asynchronous reset (active low)
256 IF resetn = '0' THEN -- asynchronous reset (active low)
219 ASSERTION_2 <= '1';
257 ASSERTION_2 <= '1';
220 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
258 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
221 IF tick_ongoing = '1' THEN
259 IF tick_ongoing = '1' THEN
222 IF fine_time_reg /= fine_time OR coarse_time_reg /= coarse_time THEN
260 IF fine_time_reg /= fine_time OR coarse_time_reg /= coarse_time THEN
223 IF fine_time /= X"0000" THEN
261 IF fine_time /= X"0000" THEN
224 ASSERTION_2 <= '0';
262 ASSERTION_2 <= '0';
225 END IF;
263 END IF;
226 END IF;
264 END IF;
227 END IF;
265 END IF;
228 END IF;
266 END IF;
229 END PROCESS;
267 END PROCESS;
230
268
231 -----------------------------------------------------------------------------
269 -----------------------------------------------------------------------------
232 -- ASSERTION 3 :
270 -- ASSERTION 3 :
233 -- next(TIME) > TIME
271 -- next(TIME) > TIME
234 -- false if resynchro, or new coarse_time
272 -- false if resynchro, or new coarse_time
235 -----------------------------------------------------------------------------
273 -----------------------------------------------------------------------------
236 PROCESS (clk25MHz, resetn)
274 PROCESS (clk25MHz, resetn)
237 BEGIN -- PROCESS
275 BEGIN -- PROCESS
238 IF resetn = '0' THEN -- asynchronous reset (active low)
276 IF resetn = '0' THEN -- asynchronous reset (active low)
239 ASSERTION_3 <= '1';
277 ASSERTION_3 <= '1';
240 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
278 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
241 ASSERTION_3 <= '1';
279 ASSERTION_3 <= '1';
242 IF global_time_reg(46 DOWNTO 0) > global_time(46 DOWNTO 0) THEN
280 IF global_time_reg(46 DOWNTO 0) > global_time(46 DOWNTO 0) THEN
243 IF global_time(47) = '0' AND global_time_reg(47) = '1' THEN
281 IF global_time(47) = '0' AND global_time_reg(47) = '1' THEN
244 ASSERTION_3 <= 'U'; -- RESYNCHRO ....
282 ASSERTION_3 <= 'U'; -- RESYNCHRO ....
245 ELSE
283 ELSE
246 ASSERTION_3 <= '0';
284 ASSERTION_3 <= '0';
247 END IF;
285 END IF;
248 END IF;
286 END IF;
249 END IF;
287 END IF;
250 END PROCESS;
288 END PROCESS;
251
289
252
290
253 END beh;
291 END beh;
254
292
Show file before | Show file after | Hide comments
@@ -1,31 +1,34
1 onerror {resume}
1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate /tb/tb_string
3 add wave -noupdate /tb/tb_string
4 add wave -noupdate /tb/assertion_1
4 add wave -noupdate /tb/assertion_1
5 add wave -noupdate /tb/assertion_2
5 add wave -noupdate /tb/assertion_2
6 add wave -noupdate /tb/assertion_3
6 add wave -noupdate /tb/assertion_3
7 add wave -noupdate /tb/apb_lfr_time_management_1/lfr_time_management_1/state
7 add wave -noupdate /tb/apb_lfr_time_management_1/lfr_time_management_1/state
8 add wave -noupdate -format Analog-Step -height 74 -max 66000.0 -radix hexadecimal /tb/apb_lfr_time_management_1/lfr_time_management_1/fine_time
8 add wave -noupdate -format Analog-Step -height 74 -max 66000.0 -radix hexadecimal /tb/apb_lfr_time_management_1/lfr_time_management_1/fine_time
9 add wave -noupdate /tb/apb_lfr_time_management_1/lfr_time_management_1/coarse_time_new
9 add wave -noupdate /tb/apb_lfr_time_management_1/lfr_time_management_1/coarse_time_new
10 add wave -noupdate -radix hexadecimal /tb/apb_lfr_time_management_1/lfr_time_management_1/coarse_time
10 add wave -noupdate -radix hexadecimal /tb/apb_lfr_time_management_1/lfr_time_management_1/coarse_time
11 add wave -noupdate /tb/apb_lfr_time_management_1/grspw_tick
11 add wave -noupdate /tb/apb_lfr_time_management_1/grspw_tick
12 add wave -noupdate -group OUTPUT /tb/apb_lfr_time_management_1/fine_time
12 add wave -noupdate -group OUTPUT /tb/apb_lfr_time_management_1/fine_time
13 add wave -noupdate -group OUTPUT /tb/apb_lfr_time_management_1/coarse_time
13 add wave -noupdate -group OUTPUT /tb/apb_lfr_time_management_1/coarse_time
14 add wave -noupdate /tb/apb_lfr_time_management_1/lfr_time_management_1/fine_time_new
14 add wave -noupdate /tb/apb_lfr_time_management_1/lfr_time_management_1/fine_time_new
15 add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/apbi.psel {-radix hexadecimal} /tb/apbi.psel(0) {-radix hexadecimal} /tb/apbi.psel(1) {-radix hexadecimal} /tb/apbi.psel(2) {-radix hexadecimal} /tb/apbi.psel(3) {-radix hexadecimal} /tb/apbi.psel(4) {-radix hexadecimal} /tb/apbi.psel(5) {-radix hexadecimal} /tb/apbi.psel(6) {-radix hexadecimal} /tb/apbi.psel(7) {-radix hexadecimal} /tb/apbi.psel(8) {-radix hexadecimal} /tb/apbi.psel(9) {-radix hexadecimal} /tb/apbi.psel(10) {-radix hexadecimal} /tb/apbi.psel(11) {-radix hexadecimal} /tb/apbi.psel(12) {-radix hexadecimal} /tb/apbi.psel(13) {-radix hexadecimal} /tb/apbi.psel(14) {-radix hexadecimal} /tb/apbi.psel(15) {-radix hexadecimal} /tb/apbi.penable {-radix hexadecimal} /tb/apbi.paddr {-radix hexadecimal} /tb/apbi.pwrite {-radix hexadecimal} /tb/apbi.pwdata {-radix hexadecimal} /tb/apbi.pirq {-radix hexadecimal} /tb/apbi.testen {-radix hexadecimal} /tb/apbi.testrst {-radix hexadecimal} /tb/apbi.scanen {-radix hexadecimal} /tb/apbi.testoen {-radix hexadecimal} /tb/apbi.testin {-radix hexadecimal}} /tb/apbi
16 add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/apbo.prdata {-radix hexadecimal} /tb/apbo.pirq {-radix hexadecimal} /tb/apbo.pconfig {-radix hexadecimal} /tb/apbo.pindex {-radix hexadecimal}} /tb/apbo
17 add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/apb_lfr_time_management_1/r.ctrl {-radix hexadecimal} /tb/apb_lfr_time_management_1/r.coarse_time_load {-radix hexadecimal} /tb/apb_lfr_time_management_1/r.coarse_time {-radix hexadecimal} /tb/apb_lfr_time_management_1/r.fine_time {-radix hexadecimal}} /tb/apb_lfr_time_management_1/r
15 TreeUpdate [SetDefaultTree]
18 TreeUpdate [SetDefaultTree]
16 WaveRestoreCursors {{FT 1} {15279095 ps} 1} {{FT 1 + 1s} {1000012719095 ps} 1} {{Cursor 3} {369333380000 ps} 0} {TRANSITION {169333245705 ps} 1}
19 WaveRestoreCursors {{FT 1} {15279095 ps} 1} {{FT 1 + 1s} {1000012719095 ps} 1} {{Cursor 3} {750199620000 ps} 0} {TRANSITION {169333245705 ps} 1}
17 configure wave -namecolwidth 512
20 configure wave -namecolwidth 512
18 configure wave -valuecolwidth 139
21 configure wave -valuecolwidth 139
19 configure wave -justifyvalue left
22 configure wave -justifyvalue left
20 configure wave -signalnamewidth 0
23 configure wave -signalnamewidth 0
21 configure wave -snapdistance 10
24 configure wave -snapdistance 10
22 configure wave -datasetprefix 0
25 configure wave -datasetprefix 0
23 configure wave -rowmargin 4
26 configure wave -rowmargin 4
24 configure wave -childrowmargin 2
27 configure wave -childrowmargin 2
25 configure wave -gridoffset 0
28 configure wave -gridoffset 0
26 configure wave -gridperiod 1
29 configure wave -gridperiod 1
27 configure wave -griddelta 40
30 configure wave -griddelta 40
28 configure wave -timeline 0
31 configure wave -timeline 0
29 configure wave -timelineunits ps
32 configure wave -timelineunits ps
30 update
33 update
31 WaveRestoreZoom {0 ps} {243152392641 ps}
34 WaveRestoreZoom {0 ps} {1185800469 ns}
Show file before | Show file after | Hide comments
@@ -1,274 +1,276
1 ----------------------------------------------------------------------------------
1 ----------------------------------------------------------------------------------
2 -- Company:
2 -- Company:
3 -- Engineer:
3 -- Engineer:
4 --
4 --
5 -- Create Date: 11:17:05 07/02/2012
5 -- Create Date: 11:17:05 07/02/2012
6 -- Design Name:
6 -- Design Name:
7 -- Module Name: apb_lfr_time_management - Behavioral
7 -- Module Name: apb_lfr_time_management - Behavioral
8 -- Project Name:
8 -- Project Name:
9 -- Target Devices:
9 -- Target Devices:
10 -- Tool versions:
10 -- Tool versions:
11 -- Description:
11 -- Description:
12 --
12 --
13 -- Dependencies:
13 -- Dependencies:
14 --
14 --
15 -- Revision:
15 -- Revision:
16 -- Revision 0.01 - File Created
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 USE grlib.devices.ALL;
26 USE grlib.devices.ALL;
27 LIBRARY lpp;
27 LIBRARY lpp;
28 USE lpp.apb_devices_list.ALL;
28 USE lpp.apb_devices_list.ALL;
29 USE lpp.general_purpose.ALL;
29 USE lpp.general_purpose.ALL;
30 USE lpp.lpp_lfr_time_management.ALL;
30 USE lpp.lpp_lfr_time_management.ALL;
31
31
32 ENTITY apb_lfr_time_management IS
32 ENTITY apb_lfr_time_management IS
33
33
34 GENERIC(
34 GENERIC(
35 pindex : INTEGER := 0; --! APB slave index
35 pindex : INTEGER := 0; --! APB slave index
36 paddr : INTEGER := 0; --! ADDR field of the APB BAR
36 paddr : INTEGER := 0; --! ADDR field of the APB BAR
37 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
38 FIRST_DIVISION : INTEGER := 374;
38 FIRST_DIVISION : INTEGER := 374;
39 NB_SECOND_DESYNC : INTEGER := 60
39 NB_SECOND_DESYNC : INTEGER := 60
40 );
40 );
41
41
42 PORT (
42 PORT (
43 clk25MHz : IN STD_LOGIC; --! Clock
43 clk25MHz : IN STD_LOGIC; --! Clock
44 clk24_576MHz : IN STD_LOGIC; --! secondary clock
44 clk24_576MHz : IN STD_LOGIC; --! secondary clock
45 resetn : IN STD_LOGIC; --! Reset
45 resetn : IN STD_LOGIC; --! Reset
46
46
47 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
47 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
48
48
49 apbi : IN apb_slv_in_type; --! APB slave input signals
49 apbi : IN apb_slv_in_type; --! APB slave input signals
50 apbo : OUT apb_slv_out_type; --! APB slave output signals
50 apbo : OUT apb_slv_out_type; --! APB slave output signals
51
51
52 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
52 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
53 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
53 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
54 );
54 );
55
55
56 END apb_lfr_time_management;
56 END apb_lfr_time_management;
57
57
58 ARCHITECTURE Behavioral OF apb_lfr_time_management IS
58 ARCHITECTURE Behavioral OF apb_lfr_time_management IS
59
59
60 CONSTANT REVISION : INTEGER := 1;
60 CONSTANT REVISION : INTEGER := 1;
61 CONSTANT pconfig : apb_config_type := (
61 CONSTANT pconfig : apb_config_type := (
62 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, 0),
62 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, 0),
63 1 => apb_iobar(paddr, pmask)
63 1 => apb_iobar(paddr, pmask)
64 );
64 );
65
65
66 TYPE apb_lfr_time_management_Reg IS RECORD
66 TYPE apb_lfr_time_management_Reg IS RECORD
67 ctrl : STD_LOGIC;
67 ctrl : STD_LOGIC;
68 coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
68 coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
69 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
69 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
70 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
70 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
71 END RECORD;
71 END RECORD;
72 SIGNAL r : apb_lfr_time_management_Reg;
72 SIGNAL r : apb_lfr_time_management_Reg;
73
73
74 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
74 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
75 SIGNAL force_tick : STD_LOGIC;
75 SIGNAL force_tick : STD_LOGIC;
76 SIGNAL previous_force_tick : STD_LOGIC;
76 SIGNAL previous_force_tick : STD_LOGIC;
77 SIGNAL soft_tick : STD_LOGIC;
77 SIGNAL soft_tick : STD_LOGIC;
78
78
79 SIGNAL coarsetime_reg_updated : STD_LOGIC;
79 SIGNAL coarsetime_reg_updated : STD_LOGIC;
80 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
80 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
81
81
82 --SIGNAL coarse_time_new : STD_LOGIC;
82 --SIGNAL coarse_time_new : STD_LOGIC;
83 SIGNAL coarse_time_new_49 : STD_LOGIC;
83 SIGNAL coarse_time_new_49 : STD_LOGIC;
84 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
84 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
86
86
87 --SIGNAL fine_time_new : STD_LOGIC;
87 --SIGNAL fine_time_new : STD_LOGIC;
88 --SIGNAL fine_time_new_temp : STD_LOGIC;
88 --SIGNAL fine_time_new_temp : STD_LOGIC;
89 SIGNAL fine_time_new_49 : STD_LOGIC;
89 SIGNAL fine_time_new_49 : STD_LOGIC;
90 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
90 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
91 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
91 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
92 SIGNAL tick : STD_LOGIC;
92 SIGNAL tick : STD_LOGIC;
93 SIGNAL new_timecode : STD_LOGIC;
93 SIGNAL new_timecode : STD_LOGIC;
94 SIGNAL new_coarsetime : STD_LOGIC;
94 SIGNAL new_coarsetime : STD_LOGIC;
95
95
96 SIGNAL time_new_49 : STD_LOGIC;
96 SIGNAL time_new_49 : STD_LOGIC;
97 SIGNAL time_new : STD_LOGIC;
97 SIGNAL time_new : STD_LOGIC;
98
98
99 BEGIN
99 BEGIN
100
100
101 PROCESS(resetn, clk25MHz)
101 PROCESS(resetn, clk25MHz)
102 BEGIN
102 BEGIN
103
103
104 IF resetn = '0' THEN
104 IF resetn = '0' THEN
105 Rdata <= (OTHERS => '0');
105 Rdata <= (OTHERS => '0');
106 r.coarse_time_load <= x"80000000";
106 r.coarse_time_load <= x"80000000";
107 r.ctrl <= '0';
107 r.ctrl <= '0';
108 force_tick <= '0';
108 force_tick <= '0';
109 previous_force_tick <= '0';
109 previous_force_tick <= '0';
110 soft_tick <= '0';
110 soft_tick <= '0';
111
111
112 coarsetime_reg_updated <= '0';
112 coarsetime_reg_updated <= '0';
113
113
114 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
114 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
115 coarsetime_reg_updated <= '0';
115 coarsetime_reg_updated <= '0';
116
116
117 force_tick <= r.ctrl;
117 force_tick <= r.ctrl;
118 previous_force_tick <= force_tick;
118 previous_force_tick <= force_tick;
119 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
119 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
120 soft_tick <= '1';
120 soft_tick <= '1';
121 ELSE
121 ELSE
122 soft_tick <= '0';
122 soft_tick <= '0';
123 END IF;
123 END IF;
124
124
125 --APB Write OP
125 --APB Write OP
126 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
126 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
127 CASE apbi.paddr(7 DOWNTO 2) IS
127 CASE apbi.paddr(7 DOWNTO 2) IS
128 WHEN "000000" =>
128 WHEN "000000" =>
129 r.ctrl <= apbi.pwdata(0);
129 r.ctrl <= apbi.pwdata(0);
130 WHEN "000001" =>
130 WHEN "000001" =>
131 r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0);
131 r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0);
132 coarsetime_reg_updated <= '1';
132 coarsetime_reg_updated <= '1';
133 WHEN OTHERS =>
133 WHEN OTHERS =>
134 NULL;
134 END CASE;
135 END CASE;
135 ELSIF r.ctrl = '1' THEN
136 ELSIF r.ctrl = '1' THEN
136 r.ctrl <= '0';
137 r.ctrl <= '0';
137 END IF;
138 END IF;
138
139
139 --APB READ OP
140 --APB READ OP
140 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
141 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
141 CASE apbi.paddr(7 DOWNTO 2) IS
142 CASE apbi.paddr(7 DOWNTO 2) IS
142 WHEN "000000" =>
143 WHEN "000000" =>
143 Rdata(0) <= r.ctrl;
144 Rdata(0) <= r.ctrl;
145 Rdata(31 DOWNTO 1) <= (others => '0');
144 WHEN "000001" =>
146 WHEN "000001" =>
145 Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0);
147 Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0);
146 WHEN "000010" =>
148 WHEN "000010" =>
147 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
149 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
148 WHEN "000011" =>
150 WHEN "000011" =>
149 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
151 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
150 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
152 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
151 WHEN OTHERS =>
153 WHEN OTHERS =>
152 Rdata(31 DOWNTO 0) <= x"00000000";
154 Rdata(31 DOWNTO 0) <= (others => '0');
153 END CASE;
155 END CASE;
154 END IF;
156 END IF;
155
157
156 END IF;
158 END IF;
157 END PROCESS;
159 END PROCESS;
158
160
159 apbo.prdata <= Rdata;
161 apbo.prdata <= Rdata;
160 apbo.pconfig <= pconfig;
162 apbo.pconfig <= pconfig;
161 apbo.pindex <= pindex;
163 apbo.pindex <= pindex;
162
164
163 -----------------------------------------------------------------------------
165 -----------------------------------------------------------------------------
164 -- IN
166 -- IN
165 coarse_time <= r.coarse_time;
167 coarse_time <= r.coarse_time;
166 fine_time <= r.fine_time;
168 fine_time <= r.fine_time;
167 coarsetime_reg <= r.coarse_time_load;
169 coarsetime_reg <= r.coarse_time_load;
168 -----------------------------------------------------------------------------
170 -----------------------------------------------------------------------------
169
171
170 -----------------------------------------------------------------------------
172 -----------------------------------------------------------------------------
171 -- OUT
173 -- OUT
172 r.coarse_time <= coarse_time_s;
174 r.coarse_time <= coarse_time_s;
173 r.fine_time <= fine_time_s;
175 r.fine_time <= fine_time_s;
174 -----------------------------------------------------------------------------
176 -----------------------------------------------------------------------------
175
177
176 -----------------------------------------------------------------------------
178 -----------------------------------------------------------------------------
177 tick <= grspw_tick OR soft_tick;
179 tick <= grspw_tick OR soft_tick;
178
180
179 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
181 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
180 GENERIC MAP (
182 GENERIC MAP (
181 NB_FF_OF_SYNC => 2)
183 NB_FF_OF_SYNC => 2)
182 PORT MAP (
184 PORT MAP (
183 clk_in => clk25MHz,
185 clk_in => clk25MHz,
184 clk_out => clk24_576MHz,
186 clk_out => clk24_576MHz,
185 rstn => resetn,
187 rstn => resetn,
186 sin => tick,
188 sin => tick,
187 sout => new_timecode);
189 sout => new_timecode);
188
190
189 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
191 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
190 GENERIC MAP (
192 GENERIC MAP (
191 NB_FF_OF_SYNC => 2)
193 NB_FF_OF_SYNC => 2)
192 PORT MAP (
194 PORT MAP (
193 clk_in => clk25MHz,
195 clk_in => clk25MHz,
194 clk_out => clk24_576MHz,
196 clk_out => clk24_576MHz,
195 rstn => resetn,
197 rstn => resetn,
196 sin => coarsetime_reg_updated,
198 sin => coarsetime_reg_updated,
197 sout => new_coarsetime);
199 sout => new_coarsetime);
198 ----------------------------------------------------------------------------
200 ----------------------------------------------------------------------------
199
201
200 -----------------------------------------------------------------------------
202 -----------------------------------------------------------------------------
201 --SYNC_FF_1 : SYNC_FF
203 --SYNC_FF_1 : SYNC_FF
202 -- GENERIC MAP (
204 -- GENERIC MAP (
203 -- NB_FF_OF_SYNC => 2)
205 -- NB_FF_OF_SYNC => 2)
204 -- PORT MAP (
206 -- PORT MAP (
205 -- clk => clk25MHz,
207 -- clk => clk25MHz,
206 -- rstn => resetn,
208 -- rstn => resetn,
207 -- A => fine_time_new_49,
209 -- A => fine_time_new_49,
208 -- A_sync => fine_time_new_temp);
210 -- A_sync => fine_time_new_temp);
209
211
210 --lpp_front_detection_1 : lpp_front_detection
212 --lpp_front_detection_1 : lpp_front_detection
211 -- PORT MAP (
213 -- PORT MAP (
212 -- clk => clk25MHz,
214 -- clk => clk25MHz,
213 -- rstn => resetn,
215 -- rstn => resetn,
214 -- sin => fine_time_new_temp,
216 -- sin => fine_time_new_temp,
215 -- sout => fine_time_new);
217 -- sout => fine_time_new);
216
218
217 --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
219 --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
218 -- GENERIC MAP (
220 -- GENERIC MAP (
219 -- NB_FF_OF_SYNC => 2)
221 -- NB_FF_OF_SYNC => 2)
220 -- PORT MAP (
222 -- PORT MAP (
221 -- clk_in => clk24_576MHz,
223 -- clk_in => clk24_576MHz,
222 -- clk_out => clk25MHz,
224 -- clk_out => clk25MHz,
223 -- rstn => resetn,
225 -- rstn => resetn,
224 -- sin => coarse_time_new_49,
226 -- sin => coarse_time_new_49,
225 -- sout => coarse_time_new);
227 -- sout => coarse_time_new);
226
228
227 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
229 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
228
230
229 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
231 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
230 GENERIC MAP (
232 GENERIC MAP (
231 NB_FF_OF_SYNC => 2)
233 NB_FF_OF_SYNC => 2)
232 PORT MAP (
234 PORT MAP (
233 clk_in => clk24_576MHz,
235 clk_in => clk24_576MHz,
234 clk_out => clk25MHz,
236 clk_out => clk25MHz,
235 rstn => resetn,
237 rstn => resetn,
236 sin => time_new_49,
238 sin => time_new_49,
237 sout => time_new);
239 sout => time_new);
238
240
239
241
240
242
241 PROCESS (clk25MHz, resetn)
243 PROCESS (clk25MHz, resetn)
242 BEGIN -- PROCESS
244 BEGIN -- PROCESS
243 IF resetn = '0' THEN -- asynchronous reset (active low)
245 IF resetn = '0' THEN -- asynchronous reset (active low)
244 fine_time_s <= (OTHERS => '0');
246 fine_time_s <= (OTHERS => '0');
245 coarse_time_s <= (OTHERS => '0');
247 coarse_time_s <= (OTHERS => '0');
246 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
248 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
247 IF time_new = '1' THEN
249 IF time_new = '1' THEN
248 fine_time_s <= fine_time_49;
250 fine_time_s <= fine_time_49;
249 coarse_time_s <= coarse_time_49;
251 coarse_time_s <= coarse_time_49;
250 END IF;
252 END IF;
251 END IF;
253 END IF;
252 END PROCESS;
254 END PROCESS;
253
255
254 -----------------------------------------------------------------------------
256 -----------------------------------------------------------------------------
255 -- LFR_TIME_MANAGMENT
257 -- LFR_TIME_MANAGMENT
256 -----------------------------------------------------------------------------
258 -----------------------------------------------------------------------------
257 lfr_time_management_1 : lfr_time_management
259 lfr_time_management_1 : lfr_time_management
258 GENERIC MAP (
260 GENERIC MAP (
259 FIRST_DIVISION => FIRST_DIVISION,
261 FIRST_DIVISION => FIRST_DIVISION,
260 NB_SECOND_DESYNC => NB_SECOND_DESYNC)
262 NB_SECOND_DESYNC => NB_SECOND_DESYNC)
261 PORT MAP (
263 PORT MAP (
262 clk => clk24_576MHz,
264 clk => clk24_576MHz,
263 rstn => resetn,
265 rstn => resetn,
264
266
265 tick => new_timecode,
267 tick => new_timecode,
266 new_coarsetime => new_coarsetime,
268 new_coarsetime => new_coarsetime,
267 coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
269 coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
268
270
269 fine_time => fine_time_49,
271 fine_time => fine_time_49,
270 fine_time_new => fine_time_new_49,
272 fine_time_new => fine_time_new_49,
271 coarse_time => coarse_time_49,
273 coarse_time => coarse_time_49,
272 coarse_time_new => coarse_time_new_49);
274 coarse_time_new => coarse_time_new_49);
273
275
274 END Behavioral;
276 END Behavioral; No newline at end of file
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1
1
2 ------------------------------------------------------------------------------
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
5 --
6 -- This program is free software; you can redistribute it and/or modify
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
9 -- (at your option) any later version.
10 --
10 --
11 -- This program is distributed in the hope that it will be useful,
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
14 -- GNU General Public License for more details.
15 --
15 --
16 -- You should have received a copy of the GNU General Public License
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
24 -- 1.0 - initial version
25 -------------------------------------------------------------------------------
25 -------------------------------------------------------------------------------
26 LIBRARY ieee;
26 LIBRARY ieee;
27 USE ieee.std_logic_1164.ALL;
27 USE ieee.std_logic_1164.ALL;
28 USE ieee.numeric_std.ALL;
28 USE ieee.numeric_std.ALL;
29 LIBRARY grlib;
29 LIBRARY grlib;
30 USE grlib.amba.ALL;
30 USE grlib.amba.ALL;
31 USE grlib.stdlib.ALL;
31 USE grlib.stdlib.ALL;
32 USE grlib.devices.ALL;
32 USE grlib.devices.ALL;
33 USE GRLIB.DMA2AHB_Package.ALL;
33 USE GRLIB.DMA2AHB_Package.ALL;
34 LIBRARY lpp;
34 LIBRARY lpp;
35 USE lpp.lpp_amba.ALL;
35 USE lpp.lpp_amba.ALL;
36 USE lpp.apb_devices_list.ALL;
36 USE lpp.apb_devices_list.ALL;
37 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_dma_pkg.ALL;
38 USE lpp.lpp_dma_pkg.ALL;
39 LIBRARY techmap;
39 LIBRARY techmap;
40 USE techmap.gencomp.ALL;
40 USE techmap.gencomp.ALL;
41
41
42
42
43 ENTITY lpp_lfr_ms_fsmdma IS
43 ENTITY lpp_lfr_ms_fsmdma IS
44 PORT (
44 PORT (
45 -- AMBA AHB system signals
45 -- AMBA AHB system signals
46 HCLK : IN STD_ULOGIC;
46 HCLK : IN STD_ULOGIC;
47 HRESETn : IN STD_ULOGIC;
47 HRESETn : IN STD_ULOGIC;
48
48
49 --TIME
49 --TIME
50 data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
50 data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
51
51
52 -- fifo interface
52 -- fifo interface
53 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
54 fifo_empty : IN STD_LOGIC;
54 fifo_empty : IN STD_LOGIC;
55 fifo_ren : OUT STD_LOGIC;
55 fifo_ren : OUT STD_LOGIC;
56
56
57 -- header
57 -- header
58 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
59 header_val : IN STD_LOGIC;
59 header_val : IN STD_LOGIC;
60 header_ack : OUT STD_LOGIC;
60 header_ack : OUT STD_LOGIC;
61
61
62 -- DMA
62 -- DMA
63 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
65 dma_valid : OUT STD_LOGIC;
65 dma_valid : OUT STD_LOGIC;
66 dma_valid_burst : OUT STD_LOGIC;
66 dma_valid_burst : OUT STD_LOGIC;
67 dma_ren : IN STD_LOGIC;
67 dma_ren : IN STD_LOGIC;
68 dma_done : IN STD_LOGIC;
68 dma_done : IN STD_LOGIC;
69
69
70 -- Reg out
70 -- Reg out
71 ready_matrix_f0_0 : OUT STD_LOGIC;
71 ready_matrix_f0_0 : OUT STD_LOGIC;
72 ready_matrix_f0_1 : OUT STD_LOGIC;
72 ready_matrix_f0_1 : OUT STD_LOGIC;
73 ready_matrix_f1 : OUT STD_LOGIC;
73 ready_matrix_f1 : OUT STD_LOGIC;
74 ready_matrix_f2 : OUT STD_LOGIC;
74 ready_matrix_f2 : OUT STD_LOGIC;
75 error_anticipating_empty_fifo : OUT STD_LOGIC;
75 error_anticipating_empty_fifo : OUT STD_LOGIC;
76 error_bad_component_error : OUT STD_LOGIC;
76 error_bad_component_error : OUT STD_LOGIC;
77 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
77 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78
78
79 -- Reg In
79 -- Reg In
80 status_ready_matrix_f0_0 : IN STD_LOGIC;
80 status_ready_matrix_f0_0 : IN STD_LOGIC;
81 status_ready_matrix_f0_1 : IN STD_LOGIC;
81 status_ready_matrix_f0_1 : IN STD_LOGIC;
82 status_ready_matrix_f1 : IN STD_LOGIC;
82 status_ready_matrix_f1 : IN STD_LOGIC;
83 status_ready_matrix_f2 : IN STD_LOGIC;
83 status_ready_matrix_f2 : IN STD_LOGIC;
84 status_error_anticipating_empty_fifo : IN STD_LOGIC;
84 status_error_anticipating_empty_fifo : IN STD_LOGIC;
85 status_error_bad_component_error : IN STD_LOGIC;
85 status_error_bad_component_error : IN STD_LOGIC;
86
86
87 config_active_interruption_onNewMatrix : IN STD_LOGIC;
87 config_active_interruption_onNewMatrix : IN STD_LOGIC;
88 config_active_interruption_onError : IN STD_LOGIC;
88 config_active_interruption_onError : IN STD_LOGIC;
89 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
93
93
94 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
94 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
95 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
95 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
96 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
96 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
97 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
97 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
98
98
99 );
99 );
100 END;
100 END;
101
101
102 ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
102 ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
103 -----------------------------------------------------------------------------
103 -----------------------------------------------------------------------------
104 -- SIGNAL DMAIn : DMA_In_Type;
104 -- SIGNAL DMAIn : DMA_In_Type;
105 -- SIGNAL header_dmai : DMA_In_Type;
105 -- SIGNAL header_dmai : DMA_In_Type;
106 -- SIGNAL component_dmai : DMA_In_Type;
106 -- SIGNAL component_dmai : DMA_In_Type;
107 -- SIGNAL DMAOut : DMA_OUt_Type;
107 -- SIGNAL DMAOut : DMA_OUt_Type;
108 -----------------------------------------------------------------------------
108 -----------------------------------------------------------------------------
109
109
110 -----------------------------------------------------------------------------
110 -----------------------------------------------------------------------------
111 -----------------------------------------------------------------------------
111 -----------------------------------------------------------------------------
112 TYPE state_DMAWriteBurst IS (IDLE,
112 TYPE state_DMAWriteBurst IS (IDLE,
113 CHECK_COMPONENT_TYPE,
113 CHECK_COMPONENT_TYPE,
114 WRITE_COARSE_TIME,
114 WRITE_COARSE_TIME,
115 WRITE_FINE_TIME,
115 WRITE_FINE_TIME,
116 TRASH_FIFO,
116 TRASH_FIFO,
117 SEND_DATA,
117 SEND_DATA,
118 WAIT_DATA_ACK
118 WAIT_DATA_ACK
119 );
119 );
120 SIGNAL state : state_DMAWriteBurst; -- := IDLE;
120 SIGNAL state : state_DMAWriteBurst; -- := IDLE;
121
121
122 -- SIGNAL nbSend : INTEGER;
122 -- SIGNAL nbSend : INTEGER;
123 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
123 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
124 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
124 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
125 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
125 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
126 SIGNAL header_check_ok : STD_LOGIC;
126 SIGNAL header_check_ok : STD_LOGIC;
127 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
127 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
128 SIGNAL send_matrix : STD_LOGIC;
128 SIGNAL send_matrix : STD_LOGIC;
129 -- SIGNAL request : STD_LOGIC;
129 -- SIGNAL request : STD_LOGIC;
130 -- SIGNAL remaining_data_request : INTEGER;
130 -- SIGNAL remaining_data_request : INTEGER;
131 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
132 -----------------------------------------------------------------------------
132 -----------------------------------------------------------------------------
133 -----------------------------------------------------------------------------
133 -----------------------------------------------------------------------------
134 SIGNAL header_select : STD_LOGIC;
134 SIGNAL header_select : STD_LOGIC;
135
135
136 SIGNAL header_send : STD_LOGIC;
136 SIGNAL header_send : STD_LOGIC;
137 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
137 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
138 SIGNAL header_send_ok : STD_LOGIC;
138 SIGNAL header_send_ok : STD_LOGIC;
139 SIGNAL header_send_ko : STD_LOGIC;
139 SIGNAL header_send_ko : STD_LOGIC;
140
140
141 SIGNAL component_send : STD_LOGIC;
141 SIGNAL component_send : STD_LOGIC;
142 SIGNAL component_send_ok : STD_LOGIC;
142 SIGNAL component_send_ok : STD_LOGIC;
143 SIGNAL component_send_ko : STD_LOGIC;
143 SIGNAL component_send_ko : STD_LOGIC;
144 -----------------------------------------------------------------------------
144 -----------------------------------------------------------------------------
145 SIGNAL fifo_ren_trash : STD_LOGIC;
145 SIGNAL fifo_ren_trash : STD_LOGIC;
146 SIGNAL component_fifo_ren : STD_LOGIC;
146 SIGNAL component_fifo_ren : STD_LOGIC;
147
147
148 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
149 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
149 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
150 SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
151
151
152 -----------------------------------------------------------------------------
152 -----------------------------------------------------------------------------
153 SIGNAL log_empty_fifo : STD_LOGIC;
153 SIGNAL log_empty_fifo : STD_LOGIC;
154
154 -----------------------------------------------------------------------------
155 BEGIN
155 SIGNAL header_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
156
156 SIGNAL header_reg_val : STD_LOGIC;
157 debug_reg <= debug_reg_s;
157 SIGNAL header_reg_ack : STD_LOGIC;
158
158 SIGNAL header_error : STD_LOGIC;
159
159
160 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
160 BEGIN
161 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
161
162 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
162 debug_reg <= debug_reg_s;
163 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
163
164 '0';
164
165
165 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
166 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
166 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
167 '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE
167 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
168 '1' WHEN component_type = component_type_pre + "0001" ELSE
168 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
169 '0';
169 '0';
170
170
171 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
171 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
172 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
172 '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE
173 addr_matrix_f1 WHEN matrix_type = "10" ELSE
173 '1' WHEN component_type = component_type_pre + "0001" ELSE
174 addr_matrix_f2 WHEN matrix_type = "11" ELSE
174 '0';
175 (OTHERS => '0');
175
176
176 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
177 -----------------------------------------------------------------------------
177 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
178 -- DMA control
178 addr_matrix_f1 WHEN matrix_type = "10" ELSE
179 -----------------------------------------------------------------------------
179 addr_matrix_f2 WHEN matrix_type = "11" ELSE
180 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
180 (OTHERS => '0');
181 BEGIN -- PROCESS DMAWriteBurst_p
181
182 IF HRESETn = '0' THEN -- asynchronous reset (active low)
182 -----------------------------------------------------------------------------
183 matrix_type <= (OTHERS => '0');
183 -- DMA control
184 component_type <= (OTHERS => '0');
184 -----------------------------------------------------------------------------
185 state <= IDLE;
185 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
186 header_ack <= '0';
186 BEGIN -- PROCESS DMAWriteBurst_p
187 ready_matrix_f0_0 <= '0';
187 IF HRESETn = '0' THEN -- asynchronous reset (active low)
188 ready_matrix_f0_1 <= '0';
188 matrix_type <= (OTHERS => '0');
189 ready_matrix_f1 <= '0';
189 component_type <= (OTHERS => '0');
190 ready_matrix_f2 <= '0';
190 state <= IDLE;
191 error_anticipating_empty_fifo <= '0';
191 -- header_ack <= '0';
192 error_bad_component_error <= '0';
192 ready_matrix_f0_0 <= '0';
193 component_type_pre <= "0000";
193 ready_matrix_f0_1 <= '0';
194 fifo_ren_trash <= '1';
194 ready_matrix_f1 <= '0';
195 component_send <= '0';
195 ready_matrix_f2 <= '0';
196 address <= (OTHERS => '0');
196 error_anticipating_empty_fifo <= '0';
197 header_select <= '0';
197 error_bad_component_error <= '0';
198 header_send <= '0';
198 component_type_pre <= "0000";
199 header_data <= (OTHERS => '0');
199 fifo_ren_trash <= '1';
200 fine_time_reg <= (OTHERS => '0');
200 component_send <= '0';
201
201 address <= (OTHERS => '0');
202 debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0');
202 header_select <= '0';
203
203 header_send <= '0';
204 log_empty_fifo <= '0';
204 header_data <= (OTHERS => '0');
205
205 fine_time_reg <= (OTHERS => '0');
206 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
206
207 debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0');
207 debug_reg_s( 2 DOWNTO 0) <= (OTHERS => '0');
208
208 debug_reg_s(31 DOWNTO 4) <= (OTHERS => '0');
209 CASE state IS
209
210 WHEN IDLE =>
210 log_empty_fifo <= '0';
211 debug_reg_s(2 DOWNTO 0) <= "000";
211
212
212 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
213 matrix_type <= header(1 DOWNTO 0);
213 debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0');
214 --component_type <= header(5 DOWNTO 2);
214 header_reg_ack <= '0';
215
215
216 ready_matrix_f0_0 <= '0';
216 CASE state IS
217 ready_matrix_f0_1 <= '0';
217 WHEN IDLE =>
218 ready_matrix_f1 <= '0';
218 debug_reg_s(2 DOWNTO 0) <= "000";
219 ready_matrix_f2 <= '0';
219
220 error_bad_component_error <= '0';
220 matrix_type <= header(1 DOWNTO 0);
221 header_select <= '1';
221 --component_type <= header(5 DOWNTO 2);
222 IF header_val = '1' THEN
222
223 header_ack <= '1';
223 ready_matrix_f0_0 <= '0';
224 END IF;
224 ready_matrix_f0_1 <= '0';
225 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
225 ready_matrix_f1 <= '0';
226 debug_reg_s(5 DOWNTO 4) <= header(1 DOWNTO 0);
226 ready_matrix_f2 <= '0';
227 debug_reg_s(9 DOWNTO 6) <= header(5 DOWNTO 2);
227 error_bad_component_error <= '0';
228
228 header_select <= '1';
229 matrix_type <= header(1 DOWNTO 0);
229
230 component_type <= header(5 DOWNTO 2);
230 IF header_reg_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
231 component_type_pre <= component_type;
231 header_reg_ack <= '1';
232 state <= CHECK_COMPONENT_TYPE;
232 debug_reg_s(5 DOWNTO 4) <= header_reg(1 DOWNTO 0);
233 END IF;
233 debug_reg_s(9 DOWNTO 6) <= header_reg(5 DOWNTO 2);
234 log_empty_fifo <= '0';
234
235
235 matrix_type <= header_reg(1 DOWNTO 0);
236 WHEN CHECK_COMPONENT_TYPE =>
236 component_type <= header_reg(5 DOWNTO 2);
237 debug_reg_s(2 DOWNTO 0) <= "001";
237 component_type_pre <= component_type;
238 header_ack <= '0';
238 state <= CHECK_COMPONENT_TYPE;
239
239 END IF;
240 IF header_check_ok = '1' THEN
240 log_empty_fifo <= '0';
241 header_send <= '0';
241
242 --
242 WHEN CHECK_COMPONENT_TYPE =>
243 IF component_type = "0000" THEN
243 debug_reg_s(2 DOWNTO 0) <= "001";
244 address <= address_matrix;
244 --header_ack <= '0';
245 CASE matrix_type IS
245
246 WHEN "00" => matrix_time_f0_0 <= data_time;
246 IF header_check_ok = '1' THEN
247 WHEN "01" => matrix_time_f0_1 <= data_time;
247 header_send <= '0';
248 WHEN "10" => matrix_time_f1 <= data_time;
248 --
249 WHEN "11" => matrix_time_f2 <= data_time ;
249 IF component_type = "0000" THEN
250 WHEN OTHERS => NULL;
250 address <= address_matrix;
251 END CASE;
251 CASE matrix_type IS
252
252 WHEN "00" => matrix_time_f0_0 <= data_time;
253 header_data <= data_time(31 DOWNTO 0);
253 WHEN "01" => matrix_time_f0_1 <= data_time;
254 fine_time_reg <= data_time(47 DOWNTO 32);
254 WHEN "10" => matrix_time_f1 <= data_time;
255 --state <= WRITE_COARSE_TIME;
255 WHEN "11" => matrix_time_f2 <= data_time ;
256 --header_send <= '1';
256 WHEN OTHERS => NULL;
257 state <= SEND_DATA;
257 END CASE;
258 header_send <= '0';
258
259 component_send <= '1';
259 header_data <= data_time(31 DOWNTO 0);
260 header_select <= '0';
260 fine_time_reg <= data_time(47 DOWNTO 32);
261 ELSE
261 --state <= WRITE_COARSE_TIME;
262 state <= SEND_DATA;
262 --header_send <= '1';
263 END IF;
263 state <= SEND_DATA;
264 --
264 header_send <= '0';
265 ELSE
265 component_send <= '1';
266 error_bad_component_error <= '1';
266 header_select <= '0';
267 component_type_pre <= "0000";
267 ELSE
268 state <= TRASH_FIFO;
268 state <= SEND_DATA;
269 END IF;
269 END IF;
270
270 --
271 --WHEN WRITE_COARSE_TIME =>
271 ELSE
272 -- debug_reg_s(2 DOWNTO 0) <= "010";
272 error_bad_component_error <= '1';
273
273 component_type_pre <= "0000";
274 -- header_ack <= '0';
274 state <= TRASH_FIFO;
275
275 END IF;
276 -- IF dma_ren = '0' THEN
276
277 -- header_send <= '0';
277 --WHEN WRITE_COARSE_TIME =>
278 -- ELSE
278 -- debug_reg_s(2 DOWNTO 0) <= "010";
279 -- header_send <= header_send;
279
280 -- END IF;
280 -- header_ack <= '0';
281
281
282
282 -- IF dma_ren = '0' THEN
283 -- IF header_send_ko = '1' THEN
283 -- header_send <= '0';
284 -- header_send <= '0';
284 -- ELSE
285 -- state <= TRASH_FIFO;
285 -- header_send <= header_send;
286 -- error_anticipating_empty_fifo <= '1';
286 -- END IF;
287 -- -- TODO : error sending header
287
288 -- ELSIF header_send_ok = '1' THEN
288
289 -- header_send <= '1';
289 -- IF header_send_ko = '1' THEN
290 -- header_select <= '1';
290 -- header_send <= '0';
291 -- header_data(15 DOWNTO 0) <= fine_time_reg;
291 -- state <= TRASH_FIFO;
292 -- header_data(31 DOWNTO 16) <= (OTHERS => '0');
292 -- error_anticipating_empty_fifo <= '1';
293 -- state <= WRITE_FINE_TIME;
293 -- -- TODO : error sending header
294 -- address <= address + 4;
294 -- ELSIF header_send_ok = '1' THEN
295 -- END IF;
295 -- header_send <= '1';
296
296 -- header_select <= '1';
297
297 -- header_data(15 DOWNTO 0) <= fine_time_reg;
298 --WHEN WRITE_FINE_TIME =>
298 -- header_data(31 DOWNTO 16) <= (OTHERS => '0');
299 -- debug_reg_s(2 DOWNTO 0) <= "011";
299 -- state <= WRITE_FINE_TIME;
300
300 -- address <= address + 4;
301 -- header_ack <= '0';
301 -- END IF;
302
302
303 -- IF dma_ren = '0' THEN
303
304 -- header_send <= '0';
304 --WHEN WRITE_FINE_TIME =>
305 -- ELSE
305 -- debug_reg_s(2 DOWNTO 0) <= "011";
306 -- header_send <= header_send;
306
307 -- END IF;
307 -- header_ack <= '0';
308
308
309 -- IF header_send_ko = '1' THEN
309 -- IF dma_ren = '0' THEN
310 -- header_send <= '0';
310 -- header_send <= '0';
311 -- state <= TRASH_FIFO;
311 -- ELSE
312 -- error_anticipating_empty_fifo <= '1';
312 -- header_send <= header_send;
313 -- -- TODO : error sending header
313 -- END IF;
314 -- ELSIF header_send_ok = '1' THEN
314
315 -- header_send <= '0';
315 -- IF header_send_ko = '1' THEN
316 -- header_select <= '0';
316 -- header_send <= '0';
317 -- state <= SEND_DATA;
317 -- state <= TRASH_FIFO;
318 -- address <= address + 4;
318 -- error_anticipating_empty_fifo <= '1';
319 -- END IF;
319 -- -- TODO : error sending header
320
320 -- ELSIF header_send_ok = '1' THEN
321 WHEN TRASH_FIFO =>
321 -- header_send <= '0';
322 debug_reg_s(2 DOWNTO 0) <= "100";
322 -- header_select <= '0';
323
323 -- state <= SEND_DATA;
324 header_ack <= '0';
324 -- address <= address + 4;
325 error_bad_component_error <= '0';
325 -- END IF;
326 error_anticipating_empty_fifo <= '0';
326
327 IF fifo_empty = '1' THEN
327 WHEN TRASH_FIFO =>
328 state <= IDLE;
328 debug_reg_s(2 DOWNTO 0) <= "100";
329 fifo_ren_trash <= '1';
329
330 ELSE
330 -- header_ack <= '0';
331 fifo_ren_trash <= '0';
331 error_bad_component_error <= '0';
332 END IF;
332 error_anticipating_empty_fifo <= '0';
333
333 IF fifo_empty = '1' THEN
334 WHEN SEND_DATA =>
334 state <= IDLE;
335 header_ack <= '0';
335 fifo_ren_trash <= '1';
336 debug_reg_s(2 DOWNTO 0) <= "101";
336 ELSE
337
337 fifo_ren_trash <= '0';
338 IF fifo_empty = '1' OR log_empty_fifo = '1' THEN
338 END IF;
339 state <= IDLE;
339
340 IF component_type = "1110" THEN --"1110" -- JC
340 WHEN SEND_DATA =>
341 CASE matrix_type IS
341 -- header_ack <= '0';
342 WHEN "00" => ready_matrix_f0_0 <= '1';
342 debug_reg_s(2 DOWNTO 0) <= "101";
343 WHEN "01" => ready_matrix_f0_1 <= '1';
343
344 WHEN "10" => ready_matrix_f1 <= '1';
344 IF fifo_empty = '1' OR log_empty_fifo = '1' THEN
345 WHEN "11" => ready_matrix_f2 <= '1';
345 state <= IDLE;
346 WHEN OTHERS => NULL;
346 IF component_type = "1110" THEN --"1110" -- JC
347 END CASE;
347 CASE matrix_type IS
348
348 WHEN "00" => ready_matrix_f0_0 <= '1';
349 END IF;
349 WHEN "01" => ready_matrix_f0_1 <= '1';
350 ELSE
350 WHEN "10" => ready_matrix_f1 <= '1';
351 component_send <= '1';
351 WHEN "11" => ready_matrix_f2 <= '1';
352 address <= address;
352 WHEN OTHERS => NULL;
353 state <= WAIT_DATA_ACK;
353 END CASE;
354 END IF;
354
355
355 END IF;
356 WHEN WAIT_DATA_ACK =>
356 ELSE
357 log_empty_fifo <= fifo_empty OR log_empty_fifo;
357 component_send <= '1';
358
358 address <= address;
359 debug_reg_s(2 DOWNTO 0) <= "110";
359 state <= WAIT_DATA_ACK;
360
360 END IF;
361 component_send <= '0';
361
362 IF component_send_ok = '1' THEN
362 WHEN WAIT_DATA_ACK =>
363 address <= address + 64;
363 log_empty_fifo <= fifo_empty OR log_empty_fifo;
364 state <= SEND_DATA;
364
365 ELSIF component_send_ko = '1' THEN
365 debug_reg_s(2 DOWNTO 0) <= "110";
366 error_anticipating_empty_fifo <= '0';
366
367 state <= TRASH_FIFO;
367 component_send <= '0';
368 END IF;
368 IF component_send_ok = '1' THEN
369
369 address <= address + 64;
370
370 state <= SEND_DATA;
371 --WHEN CHECK_LENGTH =>
371 ELSIF component_send_ko = '1' THEN
372 -- component_send <= '0';
372 error_anticipating_empty_fifo <= '0';
373 -- debug_reg_s(2 DOWNTO 0) <= "111";
373 state <= TRASH_FIFO;
374 -- state <= IDLE;
374 END IF;
375
375
376 WHEN OTHERS => NULL;
376
377 END CASE;
377 --WHEN CHECK_LENGTH =>
378
378 -- component_send <= '0';
379 END IF;
379 -- debug_reg_s(2 DOWNTO 0) <= "111";
380 END PROCESS DMAWriteFSM_p;
380 -- state <= IDLE;
381
381
382 dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send;
382 WHEN OTHERS => NULL;
383 dma_valid <= header_send WHEN header_select = '1' ELSE '0';
383 END CASE;
384 dma_data <= header_data WHEN header_select = '1' ELSE fifo_data;
384
385 dma_addr <= address;
385 END IF;
386 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren;
386 END PROCESS DMAWriteFSM_p;
387
387
388 component_send_ok <= '0' WHEN header_select = '1' ELSE dma_done;
388 dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send;
389 component_send_ko <= '0';
389 dma_valid <= header_send WHEN header_select = '1' ELSE '0';
390
390 dma_data <= header_data WHEN header_select = '1' ELSE fifo_data;
391 header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done;
391 dma_addr <= address;
392 header_send_ko <= '0';
392 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren;
393
393
394 END Behavioral;
394 component_send_ok <= '0' WHEN header_select = '1' ELSE dma_done;
395 component_send_ko <= '0';
396
397 header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done;
398 header_send_ko <= '0';
399
400
401 -----------------------------------------------------------------------------
402 -- FSM HEADER ACK
403 -----------------------------------------------------------------------------
404 PROCESS (HCLK, HRESETn)
405 BEGIN -- PROCESS
406 IF HRESETn = '0' THEN -- asynchronous reset (active low)
407 header_ack <= '0';
408 header_reg <= (OTHERS => '0');
409 header_reg_val <= '0';
410 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
411 header_ack <= '0';
412
413 IF header_val = '1' THEN
414 header_ack <= '1';
415 header_reg <= header;
416 END IF;
417
418 IF header_val = '1' THEN
419 header_reg_val <= '1';
420 ELSIF header_reg_ack = '1' THEN
421 header_reg_val <= '0';
422 END IF;
423
424 header_error <= header_val AND header_reg_val AND (NOT Header_reg_ack);
425
426 END IF;
427 END PROCESS;
428
429 debug_reg_s(3) <= header_error;
430
431 END Behavioral; No newline at end of file
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