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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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--
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-- This program is free software; you can redistribute it and/or modify
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful,
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- jean-christophe.pellion@easii-ic.com
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-- jean-christophe.pellion@easii-ic.com
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- 1.0 - initial version
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-- 1.0 - initial version
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY grlib;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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USE grlib.devices.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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LIBRARY lpp;
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LIBRARY lpp;
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USE lpp.lpp_amba.ALL;
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USE lpp.lpp_amba.ALL;
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USE lpp.apb_devices_list.ALL;
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USE lpp.apb_devices_list.ALL;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_dma_pkg.ALL;
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USE lpp.lpp_dma_pkg.ALL;
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LIBRARY techmap;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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USE techmap.gencomp.ALL;
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ENTITY lpp_lfr_ms_fsmdma IS
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ENTITY lpp_lfr_ms_fsmdma IS
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PORT (
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PORT (
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-- AMBA AHB system signals
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-- AMBA AHB system signals
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HCLK : IN STD_ULOGIC;
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HCLK : IN STD_ULOGIC;
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HRESETn : IN STD_ULOGIC;
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HRESETn : IN STD_ULOGIC;
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--TIME
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--TIME
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data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
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data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
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-- fifo interface
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-- fifo interface
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fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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fifo_empty : IN STD_LOGIC;
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fifo_empty : IN STD_LOGIC;
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fifo_ren : OUT STD_LOGIC;
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fifo_ren : OUT STD_LOGIC;
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-- header
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-- header
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header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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header_val : IN STD_LOGIC;
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header_val : IN STD_LOGIC;
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header_ack : OUT STD_LOGIC;
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header_ack : OUT STD_LOGIC;
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-- DMA
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-- DMA
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dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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dma_valid : OUT STD_LOGIC;
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dma_valid : OUT STD_LOGIC;
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dma_valid_burst : OUT STD_LOGIC;
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dma_valid_burst : OUT STD_LOGIC;
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dma_ren : IN STD_LOGIC;
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dma_ren : IN STD_LOGIC;
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dma_done : IN STD_LOGIC;
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dma_done : IN STD_LOGIC;
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-- Reg out
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-- Reg out
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ready_matrix_f0_0 : OUT STD_LOGIC;
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ready_matrix_f0_0 : OUT STD_LOGIC;
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ready_matrix_f0_1 : OUT STD_LOGIC;
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ready_matrix_f0_1 : OUT STD_LOGIC;
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ready_matrix_f1 : OUT STD_LOGIC;
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ready_matrix_f1 : OUT STD_LOGIC;
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ready_matrix_f2 : OUT STD_LOGIC;
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ready_matrix_f2 : OUT STD_LOGIC;
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error_anticipating_empty_fifo : OUT STD_LOGIC;
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error_anticipating_empty_fifo : OUT STD_LOGIC;
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error_bad_component_error : OUT STD_LOGIC;
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error_bad_component_error : OUT STD_LOGIC;
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debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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-- Reg In
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-- Reg In
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status_ready_matrix_f0_0 : IN STD_LOGIC;
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status_ready_matrix_f0_0 : IN STD_LOGIC;
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status_ready_matrix_f0_1 : IN STD_LOGIC;
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status_ready_matrix_f0_1 : IN STD_LOGIC;
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status_ready_matrix_f1 : IN STD_LOGIC;
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status_ready_matrix_f1 : IN STD_LOGIC;
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status_ready_matrix_f2 : IN STD_LOGIC;
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status_ready_matrix_f2 : IN STD_LOGIC;
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status_error_anticipating_empty_fifo : IN STD_LOGIC;
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status_error_anticipating_empty_fifo : IN STD_LOGIC;
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status_error_bad_component_error : IN STD_LOGIC;
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status_error_bad_component_error : IN STD_LOGIC;
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config_active_interruption_onNewMatrix : IN STD_LOGIC;
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config_active_interruption_onNewMatrix : IN STD_LOGIC;
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config_active_interruption_onError : IN STD_LOGIC;
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config_active_interruption_onError : IN STD_LOGIC;
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addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
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matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
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matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
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matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
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matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
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matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
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matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
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matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
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);
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);
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END;
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END;
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ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
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ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- SIGNAL DMAIn : DMA_In_Type;
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-- SIGNAL DMAIn : DMA_In_Type;
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-- SIGNAL header_dmai : DMA_In_Type;
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-- SIGNAL header_dmai : DMA_In_Type;
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-- SIGNAL component_dmai : DMA_In_Type;
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-- SIGNAL component_dmai : DMA_In_Type;
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-- SIGNAL DMAOut : DMA_OUt_Type;
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-- SIGNAL DMAOut : DMA_OUt_Type;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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TYPE state_DMAWriteBurst IS (IDLE,
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TYPE state_DMAWriteBurst IS (IDLE,
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CHECK_COMPONENT_TYPE,
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CHECK_COMPONENT_TYPE,
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WRITE_COARSE_TIME,
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WRITE_COARSE_TIME,
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WRITE_FINE_TIME,
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WRITE_FINE_TIME,
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TRASH_FIFO,
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TRASH_FIFO,
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SEND_DATA,
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SEND_DATA,
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WAIT_DATA_ACK
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WAIT_DATA_ACK
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);
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);
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SIGNAL state : state_DMAWriteBurst; -- := IDLE;
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SIGNAL state : state_DMAWriteBurst; -- := IDLE;
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-- SIGNAL nbSend : INTEGER;
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-- SIGNAL nbSend : INTEGER;
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SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL header_check_ok : STD_LOGIC;
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SIGNAL header_check_ok : STD_LOGIC;
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SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL send_matrix : STD_LOGIC;
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SIGNAL send_matrix : STD_LOGIC;
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-- SIGNAL request : STD_LOGIC;
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-- SIGNAL request : STD_LOGIC;
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-- SIGNAL remaining_data_request : INTEGER;
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-- SIGNAL remaining_data_request : INTEGER;
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SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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SIGNAL header_select : STD_LOGIC;
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SIGNAL header_select : STD_LOGIC;
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SIGNAL header_send : STD_LOGIC;
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SIGNAL header_send : STD_LOGIC;
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SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL header_send_ok : STD_LOGIC;
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SIGNAL header_send_ok : STD_LOGIC;
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SIGNAL header_send_ko : STD_LOGIC;
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SIGNAL header_send_ko : STD_LOGIC;
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SIGNAL component_send : STD_LOGIC;
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SIGNAL component_send : STD_LOGIC;
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SIGNAL component_send_ok : STD_LOGIC;
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SIGNAL component_send_ok : STD_LOGIC;
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SIGNAL component_send_ko : STD_LOGIC;
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SIGNAL component_send_ko : STD_LOGIC;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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SIGNAL fifo_ren_trash : STD_LOGIC;
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SIGNAL fifo_ren_trash : STD_LOGIC;
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SIGNAL component_fifo_ren : STD_LOGIC;
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SIGNAL component_fifo_ren : STD_LOGIC;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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SIGNAL log_empty_fifo : STD_LOGIC;
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SIGNAL log_empty_fifo : STD_LOGIC;
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-----------------------------------------------------------------------------
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BEGIN
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SIGNAL header_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
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156
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SIGNAL header_reg_val : STD_LOGIC;
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157
|
debug_reg <= debug_reg_s;
|
|
157
|
SIGNAL header_reg_ack : STD_LOGIC;
|
|
|
158
|
|
|
158
|
SIGNAL header_error : STD_LOGIC;
|
|
|
159
|
|
|
159
|
|
|
|
160
|
send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
|
|
160
|
BEGIN
|
|
|
161
|
'1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
|
|
161
|
|
|
|
162
|
'1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
|
|
162
|
debug_reg <= debug_reg_s;
|
|
|
163
|
'1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
|
|
163
|
|
|
|
164
|
'0';
|
|
164
|
|
|
|
165
|
|
|
165
|
send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
|
|
|
166
|
header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
|
|
166
|
'1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
|
|
|
167
|
'1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE
|
|
167
|
'1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
|
|
|
168
|
'1' WHEN component_type = component_type_pre + "0001" ELSE
|
|
168
|
'1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
|
|
|
169
|
'0';
|
|
169
|
'0';
|
|
|
170
|
|
|
170
|
|
|
|
171
|
address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
|
|
171
|
header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
|
|
|
172
|
addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
|
|
172
|
'1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE
|
|
|
173
|
addr_matrix_f1 WHEN matrix_type = "10" ELSE
|
|
173
|
'1' WHEN component_type = component_type_pre + "0001" ELSE
|
|
|
174
|
addr_matrix_f2 WHEN matrix_type = "11" ELSE
|
|
174
|
'0';
|
|
|
175
|
(OTHERS => '0');
|
|
175
|
|
|
|
176
|
|
|
176
|
address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
|
|
|
177
|
-----------------------------------------------------------------------------
|
|
177
|
addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
|
|
|
178
|
-- DMA control
|
|
178
|
addr_matrix_f1 WHEN matrix_type = "10" ELSE
|
|
|
179
|
-----------------------------------------------------------------------------
|
|
179
|
addr_matrix_f2 WHEN matrix_type = "11" ELSE
|
|
|
180
|
DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
|
|
180
|
(OTHERS => '0');
|
|
|
181
|
BEGIN -- PROCESS DMAWriteBurst_p
|
|
181
|
|
|
|
182
|
IF HRESETn = '0' THEN -- asynchronous reset (active low)
|
|
182
|
-----------------------------------------------------------------------------
|
|
|
183
|
matrix_type <= (OTHERS => '0');
|
|
183
|
-- DMA control
|
|
|
184
|
component_type <= (OTHERS => '0');
|
|
184
|
-----------------------------------------------------------------------------
|
|
|
185
|
state <= IDLE;
|
|
185
|
DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
|
|
|
186
|
header_ack <= '0';
|
|
186
|
BEGIN -- PROCESS DMAWriteBurst_p
|
|
|
187
|
ready_matrix_f0_0 <= '0';
|
|
187
|
IF HRESETn = '0' THEN -- asynchronous reset (active low)
|
|
|
188
|
ready_matrix_f0_1 <= '0';
|
|
188
|
matrix_type <= (OTHERS => '0');
|
|
|
189
|
ready_matrix_f1 <= '0';
|
|
189
|
component_type <= (OTHERS => '0');
|
|
|
190
|
ready_matrix_f2 <= '0';
|
|
190
|
state <= IDLE;
|
|
|
191
|
error_anticipating_empty_fifo <= '0';
|
|
191
|
-- header_ack <= '0';
|
|
|
192
|
error_bad_component_error <= '0';
|
|
192
|
ready_matrix_f0_0 <= '0';
|
|
|
193
|
component_type_pre <= "0000";
|
|
193
|
ready_matrix_f0_1 <= '0';
|
|
|
194
|
fifo_ren_trash <= '1';
|
|
194
|
ready_matrix_f1 <= '0';
|
|
|
195
|
component_send <= '0';
|
|
195
|
ready_matrix_f2 <= '0';
|
|
|
196
|
address <= (OTHERS => '0');
|
|
196
|
error_anticipating_empty_fifo <= '0';
|
|
|
197
|
header_select <= '0';
|
|
197
|
error_bad_component_error <= '0';
|
|
|
198
|
header_send <= '0';
|
|
198
|
component_type_pre <= "0000";
|
|
|
199
|
header_data <= (OTHERS => '0');
|
|
199
|
fifo_ren_trash <= '1';
|
|
|
200
|
fine_time_reg <= (OTHERS => '0');
|
|
200
|
component_send <= '0';
|
|
|
201
|
|
|
201
|
address <= (OTHERS => '0');
|
|
|
202
|
debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0');
|
|
202
|
header_select <= '0';
|
|
|
203
|
|
|
203
|
header_send <= '0';
|
|
|
204
|
log_empty_fifo <= '0';
|
|
204
|
header_data <= (OTHERS => '0');
|
|
|
205
|
|
|
205
|
fine_time_reg <= (OTHERS => '0');
|
|
|
206
|
ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
|
|
206
|
|
|
|
207
|
debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0');
|
|
207
|
debug_reg_s( 2 DOWNTO 0) <= (OTHERS => '0');
|
|
|
208
|
|
|
208
|
debug_reg_s(31 DOWNTO 4) <= (OTHERS => '0');
|
|
|
209
|
CASE state IS
|
|
209
|
|
|
|
210
|
WHEN IDLE =>
|
|
210
|
log_empty_fifo <= '0';
|
|
|
211
|
debug_reg_s(2 DOWNTO 0) <= "000";
|
|
211
|
|
|
|
212
|
|
|
212
|
ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
|
|
|
213
|
matrix_type <= header(1 DOWNTO 0);
|
|
213
|
debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0');
|
|
|
214
|
--component_type <= header(5 DOWNTO 2);
|
|
214
|
header_reg_ack <= '0';
|
|
|
215
|
|
|
215
|
|
|
|
216
|
ready_matrix_f0_0 <= '0';
|
|
216
|
CASE state IS
|
|
|
217
|
ready_matrix_f0_1 <= '0';
|
|
217
|
WHEN IDLE =>
|
|
|
218
|
ready_matrix_f1 <= '0';
|
|
218
|
debug_reg_s(2 DOWNTO 0) <= "000";
|
|
|
219
|
ready_matrix_f2 <= '0';
|
|
219
|
|
|
|
220
|
error_bad_component_error <= '0';
|
|
220
|
matrix_type <= header(1 DOWNTO 0);
|
|
|
221
|
header_select <= '1';
|
|
221
|
--component_type <= header(5 DOWNTO 2);
|
|
|
222
|
IF header_val = '1' THEN
|
|
222
|
|
|
|
223
|
header_ack <= '1';
|
|
223
|
ready_matrix_f0_0 <= '0';
|
|
|
224
|
END IF;
|
|
224
|
ready_matrix_f0_1 <= '0';
|
|
|
225
|
IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
|
|
225
|
ready_matrix_f1 <= '0';
|
|
|
226
|
debug_reg_s(5 DOWNTO 4) <= header(1 DOWNTO 0);
|
|
226
|
ready_matrix_f2 <= '0';
|
|
|
227
|
debug_reg_s(9 DOWNTO 6) <= header(5 DOWNTO 2);
|
|
227
|
error_bad_component_error <= '0';
|
|
|
228
|
|
|
228
|
header_select <= '1';
|
|
|
229
|
matrix_type <= header(1 DOWNTO 0);
|
|
229
|
|
|
|
230
|
component_type <= header(5 DOWNTO 2);
|
|
230
|
IF header_reg_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
|
|
|
231
|
component_type_pre <= component_type;
|
|
231
|
header_reg_ack <= '1';
|
|
|
232
|
state <= CHECK_COMPONENT_TYPE;
|
|
232
|
debug_reg_s(5 DOWNTO 4) <= header_reg(1 DOWNTO 0);
|
|
|
233
|
END IF;
|
|
233
|
debug_reg_s(9 DOWNTO 6) <= header_reg(5 DOWNTO 2);
|
|
|
234
|
log_empty_fifo <= '0';
|
|
234
|
|
|
|
235
|
|
|
235
|
matrix_type <= header_reg(1 DOWNTO 0);
|
|
|
236
|
WHEN CHECK_COMPONENT_TYPE =>
|
|
236
|
component_type <= header_reg(5 DOWNTO 2);
|
|
|
237
|
debug_reg_s(2 DOWNTO 0) <= "001";
|
|
237
|
component_type_pre <= component_type;
|
|
|
238
|
header_ack <= '0';
|
|
238
|
state <= CHECK_COMPONENT_TYPE;
|
|
|
239
|
|
|
239
|
END IF;
|
|
|
240
|
IF header_check_ok = '1' THEN
|
|
240
|
log_empty_fifo <= '0';
|
|
|
241
|
header_send <= '0';
|
|
241
|
|
|
|
242
|
--
|
|
242
|
WHEN CHECK_COMPONENT_TYPE =>
|
|
|
243
|
IF component_type = "0000" THEN
|
|
243
|
debug_reg_s(2 DOWNTO 0) <= "001";
|
|
|
244
|
address <= address_matrix;
|
|
244
|
--header_ack <= '0';
|
|
|
245
|
CASE matrix_type IS
|
|
245
|
|
|
|
246
|
WHEN "00" => matrix_time_f0_0 <= data_time;
|
|
246
|
IF header_check_ok = '1' THEN
|
|
|
247
|
WHEN "01" => matrix_time_f0_1 <= data_time;
|
|
247
|
header_send <= '0';
|
|
|
248
|
WHEN "10" => matrix_time_f1 <= data_time;
|
|
248
|
--
|
|
|
249
|
WHEN "11" => matrix_time_f2 <= data_time ;
|
|
249
|
IF component_type = "0000" THEN
|
|
|
250
|
WHEN OTHERS => NULL;
|
|
250
|
address <= address_matrix;
|
|
|
251
|
END CASE;
|
|
251
|
CASE matrix_type IS
|
|
|
252
|
|
|
252
|
WHEN "00" => matrix_time_f0_0 <= data_time;
|
|
|
253
|
header_data <= data_time(31 DOWNTO 0);
|
|
253
|
WHEN "01" => matrix_time_f0_1 <= data_time;
|
|
|
254
|
fine_time_reg <= data_time(47 DOWNTO 32);
|
|
254
|
WHEN "10" => matrix_time_f1 <= data_time;
|
|
|
255
|
--state <= WRITE_COARSE_TIME;
|
|
255
|
WHEN "11" => matrix_time_f2 <= data_time ;
|
|
|
256
|
--header_send <= '1';
|
|
256
|
WHEN OTHERS => NULL;
|
|
|
257
|
state <= SEND_DATA;
|
|
257
|
END CASE;
|
|
|
258
|
header_send <= '0';
|
|
258
|
|
|
|
259
|
component_send <= '1';
|
|
259
|
header_data <= data_time(31 DOWNTO 0);
|
|
|
260
|
header_select <= '0';
|
|
260
|
fine_time_reg <= data_time(47 DOWNTO 32);
|
|
|
261
|
ELSE
|
|
261
|
--state <= WRITE_COARSE_TIME;
|
|
|
262
|
state <= SEND_DATA;
|
|
262
|
--header_send <= '1';
|
|
|
263
|
END IF;
|
|
263
|
state <= SEND_DATA;
|
|
|
264
|
--
|
|
264
|
header_send <= '0';
|
|
|
265
|
ELSE
|
|
265
|
component_send <= '1';
|
|
|
266
|
error_bad_component_error <= '1';
|
|
266
|
header_select <= '0';
|
|
|
267
|
component_type_pre <= "0000";
|
|
267
|
ELSE
|
|
|
268
|
state <= TRASH_FIFO;
|
|
268
|
state <= SEND_DATA;
|
|
|
269
|
END IF;
|
|
269
|
END IF;
|
|
|
270
|
|
|
270
|
--
|
|
|
271
|
--WHEN WRITE_COARSE_TIME =>
|
|
271
|
ELSE
|
|
|
272
|
-- debug_reg_s(2 DOWNTO 0) <= "010";
|
|
272
|
error_bad_component_error <= '1';
|
|
|
273
|
|
|
273
|
component_type_pre <= "0000";
|
|
|
274
|
-- header_ack <= '0';
|
|
274
|
state <= TRASH_FIFO;
|
|
|
275
|
|
|
275
|
END IF;
|
|
|
276
|
-- IF dma_ren = '0' THEN
|
|
276
|
|
|
|
277
|
-- header_send <= '0';
|
|
277
|
--WHEN WRITE_COARSE_TIME =>
|
|
|
278
|
-- ELSE
|
|
278
|
-- debug_reg_s(2 DOWNTO 0) <= "010";
|
|
|
279
|
-- header_send <= header_send;
|
|
279
|
|
|
|
280
|
-- END IF;
|
|
280
|
-- header_ack <= '0';
|
|
|
281
|
|
|
281
|
|
|
|
282
|
|
|
282
|
-- IF dma_ren = '0' THEN
|
|
|
283
|
-- IF header_send_ko = '1' THEN
|
|
283
|
-- header_send <= '0';
|
|
|
284
|
-- header_send <= '0';
|
|
284
|
-- ELSE
|
|
|
285
|
-- state <= TRASH_FIFO;
|
|
285
|
-- header_send <= header_send;
|
|
|
286
|
-- error_anticipating_empty_fifo <= '1';
|
|
286
|
-- END IF;
|
|
|
287
|
-- -- TODO : error sending header
|
|
287
|
|
|
|
288
|
-- ELSIF header_send_ok = '1' THEN
|
|
288
|
|
|
|
289
|
-- header_send <= '1';
|
|
289
|
-- IF header_send_ko = '1' THEN
|
|
|
290
|
-- header_select <= '1';
|
|
290
|
-- header_send <= '0';
|
|
|
291
|
-- header_data(15 DOWNTO 0) <= fine_time_reg;
|
|
291
|
-- state <= TRASH_FIFO;
|
|
|
292
|
-- header_data(31 DOWNTO 16) <= (OTHERS => '0');
|
|
292
|
-- error_anticipating_empty_fifo <= '1';
|
|
|
293
|
-- state <= WRITE_FINE_TIME;
|
|
293
|
-- -- TODO : error sending header
|
|
|
294
|
-- address <= address + 4;
|
|
294
|
-- ELSIF header_send_ok = '1' THEN
|
|
|
295
|
-- END IF;
|
|
295
|
-- header_send <= '1';
|
|
|
296
|
|
|
296
|
-- header_select <= '1';
|
|
|
297
|
|
|
297
|
-- header_data(15 DOWNTO 0) <= fine_time_reg;
|
|
|
298
|
--WHEN WRITE_FINE_TIME =>
|
|
298
|
-- header_data(31 DOWNTO 16) <= (OTHERS => '0');
|
|
|
299
|
-- debug_reg_s(2 DOWNTO 0) <= "011";
|
|
299
|
-- state <= WRITE_FINE_TIME;
|
|
|
300
|
|
|
300
|
-- address <= address + 4;
|
|
|
301
|
-- header_ack <= '0';
|
|
301
|
-- END IF;
|
|
|
302
|
|
|
302
|
|
|
|
303
|
-- IF dma_ren = '0' THEN
|
|
303
|
|
|
|
304
|
-- header_send <= '0';
|
|
304
|
--WHEN WRITE_FINE_TIME =>
|
|
|
305
|
-- ELSE
|
|
305
|
-- debug_reg_s(2 DOWNTO 0) <= "011";
|
|
|
306
|
-- header_send <= header_send;
|
|
306
|
|
|
|
307
|
-- END IF;
|
|
307
|
-- header_ack <= '0';
|
|
|
308
|
|
|
308
|
|
|
|
309
|
-- IF header_send_ko = '1' THEN
|
|
309
|
-- IF dma_ren = '0' THEN
|
|
|
310
|
-- header_send <= '0';
|
|
310
|
-- header_send <= '0';
|
|
|
311
|
-- state <= TRASH_FIFO;
|
|
311
|
-- ELSE
|
|
|
312
|
-- error_anticipating_empty_fifo <= '1';
|
|
312
|
-- header_send <= header_send;
|
|
|
313
|
-- -- TODO : error sending header
|
|
313
|
-- END IF;
|
|
|
314
|
-- ELSIF header_send_ok = '1' THEN
|
|
314
|
|
|
|
315
|
-- header_send <= '0';
|
|
315
|
-- IF header_send_ko = '1' THEN
|
|
|
316
|
-- header_select <= '0';
|
|
316
|
-- header_send <= '0';
|
|
|
317
|
-- state <= SEND_DATA;
|
|
317
|
-- state <= TRASH_FIFO;
|
|
|
318
|
-- address <= address + 4;
|
|
318
|
-- error_anticipating_empty_fifo <= '1';
|
|
|
319
|
-- END IF;
|
|
319
|
-- -- TODO : error sending header
|
|
|
320
|
|
|
320
|
-- ELSIF header_send_ok = '1' THEN
|
|
|
321
|
WHEN TRASH_FIFO =>
|
|
321
|
-- header_send <= '0';
|
|
|
322
|
debug_reg_s(2 DOWNTO 0) <= "100";
|
|
322
|
-- header_select <= '0';
|
|
|
323
|
|
|
323
|
-- state <= SEND_DATA;
|
|
|
324
|
header_ack <= '0';
|
|
324
|
-- address <= address + 4;
|
|
|
325
|
error_bad_component_error <= '0';
|
|
325
|
-- END IF;
|
|
|
326
|
error_anticipating_empty_fifo <= '0';
|
|
326
|
|
|
|
327
|
IF fifo_empty = '1' THEN
|
|
327
|
WHEN TRASH_FIFO =>
|
|
|
328
|
state <= IDLE;
|
|
328
|
debug_reg_s(2 DOWNTO 0) <= "100";
|
|
|
329
|
fifo_ren_trash <= '1';
|
|
329
|
|
|
|
330
|
ELSE
|
|
330
|
-- header_ack <= '0';
|
|
|
331
|
fifo_ren_trash <= '0';
|
|
331
|
error_bad_component_error <= '0';
|
|
|
332
|
END IF;
|
|
332
|
error_anticipating_empty_fifo <= '0';
|
|
|
333
|
|
|
333
|
IF fifo_empty = '1' THEN
|
|
|
334
|
WHEN SEND_DATA =>
|
|
334
|
state <= IDLE;
|
|
|
335
|
header_ack <= '0';
|
|
335
|
fifo_ren_trash <= '1';
|
|
|
336
|
debug_reg_s(2 DOWNTO 0) <= "101";
|
|
336
|
ELSE
|
|
|
337
|
|
|
337
|
fifo_ren_trash <= '0';
|
|
|
338
|
IF fifo_empty = '1' OR log_empty_fifo = '1' THEN
|
|
338
|
END IF;
|
|
|
339
|
state <= IDLE;
|
|
339
|
|
|
|
340
|
IF component_type = "1110" THEN --"1110" -- JC
|
|
340
|
WHEN SEND_DATA =>
|
|
|
341
|
CASE matrix_type IS
|
|
341
|
-- header_ack <= '0';
|
|
|
342
|
WHEN "00" => ready_matrix_f0_0 <= '1';
|
|
342
|
debug_reg_s(2 DOWNTO 0) <= "101";
|
|
|
343
|
WHEN "01" => ready_matrix_f0_1 <= '1';
|
|
343
|
|
|
|
344
|
WHEN "10" => ready_matrix_f1 <= '1';
|
|
344
|
IF fifo_empty = '1' OR log_empty_fifo = '1' THEN
|
|
|
345
|
WHEN "11" => ready_matrix_f2 <= '1';
|
|
345
|
state <= IDLE;
|
|
|
346
|
WHEN OTHERS => NULL;
|
|
346
|
IF component_type = "1110" THEN --"1110" -- JC
|
|
|
347
|
END CASE;
|
|
347
|
CASE matrix_type IS
|
|
|
348
|
|
|
348
|
WHEN "00" => ready_matrix_f0_0 <= '1';
|
|
|
349
|
END IF;
|
|
349
|
WHEN "01" => ready_matrix_f0_1 <= '1';
|
|
|
350
|
ELSE
|
|
350
|
WHEN "10" => ready_matrix_f1 <= '1';
|
|
|
351
|
component_send <= '1';
|
|
351
|
WHEN "11" => ready_matrix_f2 <= '1';
|
|
|
352
|
address <= address;
|
|
352
|
WHEN OTHERS => NULL;
|
|
|
353
|
state <= WAIT_DATA_ACK;
|
|
353
|
END CASE;
|
|
|
354
|
END IF;
|
|
354
|
|
|
|
355
|
|
|
355
|
END IF;
|
|
|
356
|
WHEN WAIT_DATA_ACK =>
|
|
356
|
ELSE
|
|
|
357
|
log_empty_fifo <= fifo_empty OR log_empty_fifo;
|
|
357
|
component_send <= '1';
|
|
|
358
|
|
|
358
|
address <= address;
|
|
|
359
|
debug_reg_s(2 DOWNTO 0) <= "110";
|
|
359
|
state <= WAIT_DATA_ACK;
|
|
|
360
|
|
|
360
|
END IF;
|
|
|
361
|
component_send <= '0';
|
|
361
|
|
|
|
362
|
IF component_send_ok = '1' THEN
|
|
362
|
WHEN WAIT_DATA_ACK =>
|
|
|
363
|
address <= address + 64;
|
|
363
|
log_empty_fifo <= fifo_empty OR log_empty_fifo;
|
|
|
364
|
state <= SEND_DATA;
|
|
364
|
|
|
|
365
|
ELSIF component_send_ko = '1' THEN
|
|
365
|
debug_reg_s(2 DOWNTO 0) <= "110";
|
|
|
366
|
error_anticipating_empty_fifo <= '0';
|
|
366
|
|
|
|
367
|
state <= TRASH_FIFO;
|
|
367
|
component_send <= '0';
|
|
|
368
|
END IF;
|
|
368
|
IF component_send_ok = '1' THEN
|
|
|
369
|
|
|
369
|
address <= address + 64;
|
|
|
370
|
|
|
370
|
state <= SEND_DATA;
|
|
|
371
|
--WHEN CHECK_LENGTH =>
|
|
371
|
ELSIF component_send_ko = '1' THEN
|
|
|
372
|
-- component_send <= '0';
|
|
372
|
error_anticipating_empty_fifo <= '0';
|
|
|
373
|
-- debug_reg_s(2 DOWNTO 0) <= "111";
|
|
373
|
state <= TRASH_FIFO;
|
|
|
374
|
-- state <= IDLE;
|
|
374
|
END IF;
|
|
|
375
|
|
|
375
|
|
|
|
376
|
WHEN OTHERS => NULL;
|
|
376
|
|
|
|
377
|
END CASE;
|
|
377
|
--WHEN CHECK_LENGTH =>
|
|
|
378
|
|
|
378
|
-- component_send <= '0';
|
|
|
379
|
END IF;
|
|
379
|
-- debug_reg_s(2 DOWNTO 0) <= "111";
|
|
|
380
|
END PROCESS DMAWriteFSM_p;
|
|
380
|
-- state <= IDLE;
|
|
|
381
|
|
|
381
|
|
|
|
382
|
dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send;
|
|
382
|
WHEN OTHERS => NULL;
|
|
|
383
|
dma_valid <= header_send WHEN header_select = '1' ELSE '0';
|
|
383
|
END CASE;
|
|
|
384
|
dma_data <= header_data WHEN header_select = '1' ELSE fifo_data;
|
|
384
|
|
|
|
385
|
dma_addr <= address;
|
|
385
|
END IF;
|
|
|
386
|
fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren;
|
|
386
|
END PROCESS DMAWriteFSM_p;
|
|
|
387
|
|
|
387
|
|
|
|
388
|
component_send_ok <= '0' WHEN header_select = '1' ELSE dma_done;
|
|
388
|
dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send;
|
|
|
389
|
component_send_ko <= '0';
|
|
389
|
dma_valid <= header_send WHEN header_select = '1' ELSE '0';
|
|
|
390
|
|
|
390
|
dma_data <= header_data WHEN header_select = '1' ELSE fifo_data;
|
|
|
391
|
header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done;
|
|
391
|
dma_addr <= address;
|
|
|
392
|
header_send_ko <= '0';
|
|
392
|
fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren;
|
|
|
393
|
|
|
393
|
|
|
|
394
|
END Behavioral;
|
|
394
|
component_send_ok <= '0' WHEN header_select = '1' ELSE dma_done;
|
|
|
|
|
|
395
|
component_send_ko <= '0';
|
|
|
|
|
|
396
|
|
|
|
|
|
|
397
|
header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done;
|
|
|
|
|
|
398
|
header_send_ko <= '0';
|
|
|
|
|
|
399
|
|
|
|
|
|
|
400
|
|
|
|
|
|
|
401
|
-----------------------------------------------------------------------------
|
|
|
|
|
|
402
|
-- FSM HEADER ACK
|
|
|
|
|
|
403
|
-----------------------------------------------------------------------------
|
|
|
|
|
|
404
|
PROCESS (HCLK, HRESETn)
|
|
|
|
|
|
405
|
BEGIN -- PROCESS
|
|
|
|
|
|
406
|
IF HRESETn = '0' THEN -- asynchronous reset (active low)
|
|
|
|
|
|
407
|
header_ack <= '0';
|
|
|
|
|
|
408
|
header_reg <= (OTHERS => '0');
|
|
|
|
|
|
409
|
header_reg_val <= '0';
|
|
|
|
|
|
410
|
ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
|
|
|
|
|
|
411
|
header_ack <= '0';
|
|
|
|
|
|
412
|
|
|
|
|
|
|
413
|
IF header_val = '1' THEN
|
|
|
|
|
|
414
|
header_ack <= '1';
|
|
|
|
|
|
415
|
header_reg <= header;
|
|
|
|
|
|
416
|
END IF;
|
|
|
|
|
|
417
|
|
|
|
|
|
|
418
|
IF header_val = '1' THEN
|
|
|
|
|
|
419
|
header_reg_val <= '1';
|
|
|
|
|
|
420
|
ELSIF header_reg_ack = '1' THEN
|
|
|
|
|
|
421
|
header_reg_val <= '0';
|
|
|
|
|
|
422
|
END IF;
|
|
|
|
|
|
423
|
|
|
|
|
|
|
424
|
header_error <= header_val AND header_reg_val AND (NOT Header_reg_ack);
|
|
|
|
|
|
425
|
|
|
|
|
|
|
426
|
END IF;
|
|
|
|
|
|
427
|
END PROCESS;
|
|
|
|
|
|
428
|
|
|
|
|
|
|
429
|
debug_reg_s(3) <= header_error;
|
|
|
|
|
|
430
|
|
|
|
|
|
|
431
|
END Behavioral;
No newline at end of file
|
