@@ -499,7 +499,7 BEGIN | |||||
499 | pirq_ms => 6, |
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499 | pirq_ms => 6, | |
500 | pirq_wfp => 14, |
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500 | pirq_wfp => 14, | |
501 | hindex => 2, |
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501 | hindex => 2, | |
502 |
top_lfr_version => X"0000000 |
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502 | top_lfr_version => X"00000009") | |
503 | PORT MAP ( |
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503 | PORT MAP ( | |
504 | clk => clkm, |
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504 | clk => clkm, | |
505 | rstn => rstn, |
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505 | rstn => rstn, |
@@ -140,6 +140,8 ARCHITECTURE beh OF MINI_LFR_top IS | |||||
140 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none); |
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140 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none); | |
141 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
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141 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |
142 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none); |
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142 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none); | |
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143 | -- | |||
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144 | SIGNAL IO_s : STD_LOGIC_VECTOR(11 DOWNTO 0); | |||
143 |
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145 | |||
144 | BEGIN -- beh |
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146 | BEGIN -- beh | |
145 |
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147 | |||
@@ -176,7 +178,10 BEGIN -- beh | |||||
176 | IO5 <= '0'; |
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178 | IO5 <= '0'; | |
177 | IO6 <= '0'; |
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179 | IO6 <= '0'; | |
178 | IO7 <= '0'; |
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180 | IO7 <= '0'; | |
179 |
IO8 <= ' |
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181 | IO8 <= '0'; | |
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182 | IO9 <= '0'; | |||
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183 | IO10 <= '0'; | |||
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184 | IO11 <= '0'; | |||
180 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge |
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185 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge | |
181 | LED0 <= '0'; |
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186 | LED0 <= '0'; | |
182 | LED1 <= '1'; |
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187 | LED1 <= '1'; | |
@@ -188,7 +193,10 BEGIN -- beh | |||||
188 | IO5 <= ADC_SDO(3) OR ADC_SDO(4); |
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193 | IO5 <= ADC_SDO(3) OR ADC_SDO(4); | |
189 | IO6 <= ADC_SDO(5) OR ADC_SDO(6) OR ADC_SDO(7); |
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194 | IO6 <= ADC_SDO(5) OR ADC_SDO(6) OR ADC_SDO(7); | |
190 | IO7 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
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195 | IO7 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |
191 |
IO8 <= |
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196 | IO8 <= IO_s(8); | |
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197 | IO9 <= IO_s(9); | |||
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198 | IO10 <= IO_s(10); | |||
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199 | IO11 <= IO_s(11); | |||
192 | END IF; |
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200 | END IF; | |
193 | END PROCESS; |
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201 | END PROCESS; | |
194 |
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202 | |||
@@ -234,9 +242,10 BEGIN -- beh | |||||
234 | ahbmo => ahbo_m_ext(1), |
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242 | ahbmo => ahbo_m_ext(1), | |
235 | apbi => apbi_ext, |
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243 | apbi => apbi_ext, | |
236 | apbo => apbo_ext(5), |
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244 | apbo => apbo_ext(5), | |
237 | out_ren => IO11, |
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245 | out_ren => IO_s(11), | |
238 | out_send => IO10, |
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246 | out_send => IO_s(10), | |
239 | out_done => IO9 |
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247 | out_done => IO_s(9), | |
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248 | out_dmaout_okay => IO_s(8) | |||
240 | ); |
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249 | ); | |
241 |
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250 | |||
242 | ----------------------------------------------------------------------------- |
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251 | ----------------------------------------------------------------------------- |
@@ -63,7 +63,8 ENTITY lpp_debug_dma_singleOrBurst IS | |||||
63 | -- observation SIGNAL |
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63 | -- observation SIGNAL | |
64 | out_ren : OUT STD_LOGIC; |
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64 | out_ren : OUT STD_LOGIC; | |
65 | out_send : OUT STD_LOGIC; |
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65 | out_send : OUT STD_LOGIC; | |
66 |
out_done : OUT STD_LOGIC |
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66 | out_done : OUT STD_LOGIC; | |
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67 | out_dmaout_okay : OUT STD_LOGIC | |||
67 | ); |
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68 | ); | |
68 | END; |
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69 | END; | |
69 |
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70 | |||
@@ -117,7 +118,8 BEGIN | |||||
117 | done => done, -- out |
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118 | done => done, -- out | |
118 | ren => ren, -- out |
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119 | ren => ren, -- out | |
119 | address => address, |
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120 | address => address, | |
120 |
data => data |
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121 | data => data, | |
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122 | debug_dmaout_okay => out_dmaout_okay); | |||
121 |
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123 | |||
122 |
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124 | |||
123 | run <= reg.run; |
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125 | run <= reg.run; |
@@ -43,7 +43,9 PACKAGE lpp_debug_lfr_pkg IS | |||||
43 | apbo : OUT apb_slv_out_type; |
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43 | apbo : OUT apb_slv_out_type; | |
44 | out_ren : OUT STD_LOGIC; |
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44 | out_ren : OUT STD_LOGIC; | |
45 | out_send : OUT STD_LOGIC; |
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45 | out_send : OUT STD_LOGIC; | |
46 |
out_done : OUT STD_LOGIC |
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46 | out_done : OUT STD_LOGIC; | |
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47 | out_dmaout_okay : OUT STD_LOGIC | |||
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48 | ); | |||
47 | END COMPONENT; |
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49 | END COMPONENT; | |
48 |
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50 | |||
49 | END; |
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51 | END; |
@@ -213,7 +213,8 PACKAGE lpp_dma_pkg IS | |||||
213 | done : OUT STD_LOGIC; |
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213 | done : OUT STD_LOGIC; | |
214 | ren : OUT STD_LOGIC; |
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214 | ren : OUT STD_LOGIC; | |
215 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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215 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
216 |
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
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216 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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217 | debug_dmaout_okay : OUT STD_LOGIC); | |||
217 | END COMPONENT; |
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218 | END COMPONENT; | |
218 |
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219 | |||
219 | END; |
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220 | END; |
@@ -54,6 +54,7 ENTITY lpp_dma_send_16word IS | |||||
54 | -- |
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54 | -- | |
55 | send_ok : OUT STD_LOGIC; |
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55 | send_ok : OUT STD_LOGIC; | |
56 | send_ko : OUT STD_LOGIC |
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56 | send_ko : OUT STD_LOGIC | |
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57 | ||||
57 |
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58 | ); | |
58 | END lpp_dma_send_16word; |
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59 | END lpp_dma_send_16word; | |
59 |
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60 | |||
@@ -167,8 +168,14 BEGIN -- beh | |||||
167 |
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168 | |||
168 | DMAIn.Data <= data; |
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169 | DMAIn.Data <= data; | |
169 |
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170 | |||
170 |
ren <= '0' WHEN DMAOut.OKAY = '1' |
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171 | ren <= '0' WHEN DMAOut.OKAY = '1' ELSE --AND (state = SEND_DATA OR state = WAIT_LAST_READY) ELSE | |
171 | '1'; |
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172 | '1'; | |
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173 | ||||
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174 | -- \/ JC - 11/12/2013 \/ | |||
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175 | --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE | |||
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176 | -- '1'; | |||
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177 | -- /\ JC - 11/12/2013 /\ | |||
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178 | ||||
172 | -- \/ JC - 10/12/2013 \/ |
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179 | -- \/ JC - 10/12/2013 \/ | |
173 | --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE |
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180 | --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE | |
174 | -- '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE |
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181 | -- '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE |
@@ -62,7 +62,10 ENTITY lpp_dma_singleOrBurst IS | |||||
62 | done : OUT STD_LOGIC; |
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62 | done : OUT STD_LOGIC; | |
63 | ren : OUT STD_LOGIC; |
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63 | ren : OUT STD_LOGIC; | |
64 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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64 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
65 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
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65 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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66 | -- | |||
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67 | debug_dmaout_okay : OUT STD_LOGIC | |||
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68 | ||||
66 |
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69 | ); | |
67 | END; |
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70 | END; | |
68 |
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71 | |||
@@ -94,6 +97,9 ARCHITECTURE Behavioral OF lpp_dma_singl | |||||
94 | SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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97 | SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
95 | BEGIN |
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98 | BEGIN | |
96 |
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99 | |||
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100 | debug_dmaout_okay <= DMAOut.OKAY; | |||
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101 | ||||
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102 | ||||
97 |
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103 | ----------------------------------------------------------------------------- | |
98 | -- DMA to AHB interface |
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104 | -- DMA to AHB interface | |
99 | DMA2AHB_1 : DMA2AHB |
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105 | DMA2AHB_1 : DMA2AHB | |
@@ -132,7 +138,10 BEGIN | |||||
132 |
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138 | |||
133 | --ren <= burst_ren WHEN valid_burst = '1' ELSE |
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139 | --ren <= burst_ren WHEN valid_burst = '1' ELSE | |
134 | -- NOT single_send_ok; |
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140 | -- NOT single_send_ok; | |
135 | ren <= burst_ren AND single_ren; |
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141 | --ren <= burst_ren AND single_ren; | |
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142 | ||||
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143 | ren <= '0' WHEN DMAOut.OKAY = '1' ELSE | |||
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144 | '1'; | |||
136 |
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145 | |||
137 | ----------------------------------------------------------------------------- |
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146 | ----------------------------------------------------------------------------- | |
138 | -- SEND 1 word by DMA |
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147 | -- SEND 1 word by DMA |
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