@@ -1,544 +1,544 | |||||
1 | ----------------------------------------------------------------------------- |
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1 | ----------------------------------------------------------------------------- | |
2 | -- LEON3 Demonstration design |
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2 | -- LEON3 Demonstration design | |
3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research |
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3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research | |
4 | -- |
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4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
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5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
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6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 2 of the License, or |
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7 | -- the Free Software Foundation; either version 2 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
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9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
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10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
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13 | -- GNU General Public License for more details. | |
14 | -- |
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14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
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15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
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16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
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18 | ------------------------------------------------------------------------------ | |
19 |
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19 | |||
20 |
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20 | |||
21 | LIBRARY ieee; |
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21 | LIBRARY ieee; | |
22 | USE ieee.std_logic_1164.ALL; |
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22 | USE ieee.std_logic_1164.ALL; | |
23 | LIBRARY grlib; |
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23 | LIBRARY grlib; | |
24 | USE grlib.amba.ALL; |
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24 | USE grlib.amba.ALL; | |
25 | USE grlib.stdlib.ALL; |
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25 | USE grlib.stdlib.ALL; | |
26 | LIBRARY techmap; |
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26 | LIBRARY techmap; | |
27 | USE techmap.gencomp.ALL; |
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27 | USE techmap.gencomp.ALL; | |
28 | LIBRARY gaisler; |
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28 | LIBRARY gaisler; | |
29 | USE gaisler.memctrl.ALL; |
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29 | USE gaisler.memctrl.ALL; | |
30 | USE gaisler.leon3.ALL; |
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30 | USE gaisler.leon3.ALL; | |
31 | USE gaisler.uart.ALL; |
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31 | USE gaisler.uart.ALL; | |
32 | USE gaisler.misc.ALL; |
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32 | USE gaisler.misc.ALL; | |
33 | USE gaisler.spacewire.ALL; -- PLE |
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33 | USE gaisler.spacewire.ALL; -- PLE | |
34 | LIBRARY esa; |
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34 | LIBRARY esa; | |
35 | USE esa.memoryctrl.ALL; |
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35 | USE esa.memoryctrl.ALL; | |
36 | USE work.config.ALL; |
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36 | USE work.config.ALL; | |
37 | LIBRARY lpp; |
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37 | LIBRARY lpp; | |
38 | USE lpp.lpp_memory.ALL; |
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38 | USE lpp.lpp_memory.ALL; | |
39 | USE lpp.lpp_ad_conv.ALL; |
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39 | USE lpp.lpp_ad_conv.ALL; | |
40 | USE lpp.lpp_lfr_pkg.ALL; |
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40 | USE lpp.lpp_lfr_pkg.ALL; | |
41 | USE lpp.iir_filter.ALL; |
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41 | USE lpp.iir_filter.ALL; | |
42 | USE lpp.general_purpose.ALL; |
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42 | USE lpp.general_purpose.ALL; | |
43 | USE lpp.lpp_lfr_time_management.ALL; |
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43 | USE lpp.lpp_lfr_time_management.ALL; | |
44 |
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44 | |||
45 | ENTITY leon3mp IS |
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45 | ENTITY leon3mp IS | |
46 | GENERIC ( |
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46 | GENERIC ( | |
47 | fabtech : INTEGER := CFG_FABTECH; |
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47 | fabtech : INTEGER := CFG_FABTECH; | |
48 | memtech : INTEGER := CFG_MEMTECH; |
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48 | memtech : INTEGER := CFG_MEMTECH; | |
49 | padtech : INTEGER := CFG_PADTECH; |
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49 | padtech : INTEGER := CFG_PADTECH; | |
50 | clktech : INTEGER := CFG_CLKTECH; |
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50 | clktech : INTEGER := CFG_CLKTECH; | |
51 | disas : INTEGER := CFG_DISAS; -- Enable disassembly to console |
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51 | disas : INTEGER := CFG_DISAS; -- Enable disassembly to console | |
52 | dbguart : INTEGER := CFG_DUART; -- Print UART on console |
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52 | dbguart : INTEGER := CFG_DUART; -- Print UART on console | |
53 | pclow : INTEGER := CFG_PCLOW |
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53 | pclow : INTEGER := CFG_PCLOW | |
54 | ); |
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54 | ); | |
55 | PORT ( |
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55 | PORT ( | |
56 | clk100MHz : IN STD_ULOGIC; |
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56 | clk100MHz : IN STD_ULOGIC; | |
57 | clk49_152MHz : IN STD_ULOGIC; |
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57 | clk49_152MHz : IN STD_ULOGIC; | |
58 | reset : IN STD_ULOGIC; |
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58 | reset : IN STD_ULOGIC; | |
59 |
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59 | |||
60 | errorn : OUT STD_ULOGIC; |
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60 | errorn : OUT STD_ULOGIC; | |
61 |
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61 | |||
62 | -- UART AHB --------------------------------------------------------------- |
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62 | -- UART AHB --------------------------------------------------------------- | |
63 | ahbrxd : IN STD_ULOGIC; -- DSU rx data |
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63 | ahbrxd : IN STD_ULOGIC; -- DSU rx data | |
64 | ahbtxd : OUT STD_ULOGIC; -- DSU tx data |
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64 | ahbtxd : OUT STD_ULOGIC; -- DSU tx data | |
65 |
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65 | |||
66 | -- UART APB --------------------------------------------------------------- |
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66 | -- UART APB --------------------------------------------------------------- | |
67 | urxd1 : IN STD_ULOGIC; -- UART1 rx data |
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67 | urxd1 : IN STD_ULOGIC; -- UART1 rx data | |
68 | utxd1 : OUT STD_ULOGIC; -- UART1 tx data |
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68 | utxd1 : OUT STD_ULOGIC; -- UART1 tx data | |
69 |
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69 | |||
70 | -- RAM -------------------------------------------------------------------- |
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70 | -- RAM -------------------------------------------------------------------- | |
71 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
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71 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |
72 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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72 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
73 | nSRAM_BE0 : OUT STD_LOGIC; |
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73 | nSRAM_BE0 : OUT STD_LOGIC; | |
74 | nSRAM_BE1 : OUT STD_LOGIC; |
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74 | nSRAM_BE1 : OUT STD_LOGIC; | |
75 | nSRAM_BE2 : OUT STD_LOGIC; |
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75 | nSRAM_BE2 : OUT STD_LOGIC; | |
76 | nSRAM_BE3 : OUT STD_LOGIC; |
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76 | nSRAM_BE3 : OUT STD_LOGIC; | |
77 | nSRAM_WE : OUT STD_LOGIC; |
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77 | nSRAM_WE : OUT STD_LOGIC; | |
78 | nSRAM_CE : OUT STD_LOGIC; |
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78 | nSRAM_CE : OUT STD_LOGIC; | |
79 | nSRAM_OE : OUT STD_LOGIC; |
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79 | nSRAM_OE : OUT STD_LOGIC; | |
80 |
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80 | |||
81 | -- SPW -------------------------------------------------------------------- |
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81 | -- SPW -------------------------------------------------------------------- | |
82 | spw1_din : IN STD_LOGIC; -- PLE |
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82 | spw1_din : IN STD_LOGIC; -- PLE | |
83 | spw1_sin : IN STD_LOGIC; -- PLE |
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83 | spw1_sin : IN STD_LOGIC; -- PLE | |
84 | spw1_dout : OUT STD_LOGIC; -- PLE |
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84 | spw1_dout : OUT STD_LOGIC; -- PLE | |
85 | spw1_sout : OUT STD_LOGIC; -- PLE |
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85 | spw1_sout : OUT STD_LOGIC; -- PLE | |
86 |
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86 | |||
87 | spw2_din : IN STD_LOGIC; -- JCPE --TODO |
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87 | spw2_din : IN STD_LOGIC; -- JCPE --TODO | |
88 | spw2_sin : IN STD_LOGIC; -- JCPE --TODO |
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88 | spw2_sin : IN STD_LOGIC; -- JCPE --TODO | |
89 | spw2_dout : OUT STD_LOGIC; -- JCPE --TODO |
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89 | spw2_dout : OUT STD_LOGIC; -- JCPE --TODO | |
90 | spw2_sout : OUT STD_LOGIC; -- JCPE --TODO |
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90 | spw2_sout : OUT STD_LOGIC; -- JCPE --TODO | |
91 |
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91 | |||
92 | -- ADC -------------------------------------------------------------------- |
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92 | -- ADC -------------------------------------------------------------------- | |
93 | bias_fail_sw : OUT STD_LOGIC; |
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93 | bias_fail_sw : OUT STD_LOGIC; | |
94 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
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94 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); | |
95 | ADC_smpclk : OUT STD_LOGIC; |
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95 | ADC_smpclk : OUT STD_LOGIC; | |
96 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); |
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96 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); | |
97 |
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97 | |||
98 | --------------------------------------------------------------------------- |
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98 | --------------------------------------------------------------------------- | |
99 | led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) |
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99 | led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) | |
100 | ); |
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100 | ); | |
101 | END; |
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101 | END; | |
102 |
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102 | |||
103 | ARCHITECTURE Behavioral OF leon3mp IS |
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103 | ARCHITECTURE Behavioral OF leon3mp IS | |
104 |
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104 | |||
105 | --constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ |
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105 | --constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ | |
106 | -- CFG_GRETH+CFG_AHB_JTAG; |
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106 | -- CFG_GRETH+CFG_AHB_JTAG; | |
107 | CONSTANT maxahbmsp : INTEGER := CFG_NCPU+ |
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107 | CONSTANT maxahbmsp : INTEGER := CFG_NCPU+ | |
108 | CFG_AHB_UART |
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108 | CFG_AHB_UART | |
109 | +2; |
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109 | +2; | |
110 | -- 1 is for the SpaceWire module grspw, which is a master |
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110 | -- 1 is for the SpaceWire module grspw, which is a master | |
111 | -- 1 is for the LFR |
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111 | -- 1 is for the LFR | |
112 |
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112 | |||
113 | CONSTANT maxahbm : INTEGER := maxahbmsp; |
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113 | CONSTANT maxahbm : INTEGER := maxahbmsp; | |
114 |
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114 | |||
115 | --Clk & Rst gοΏ½nοΏ½ |
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115 | --Clk & Rst gοΏ½nοΏ½ | |
116 | SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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116 | SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
117 | SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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117 | SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
118 | SIGNAL resetnl : STD_ULOGIC; |
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118 | SIGNAL resetnl : STD_ULOGIC; | |
119 | SIGNAL clk2x : STD_ULOGIC; |
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119 | SIGNAL clk2x : STD_ULOGIC; | |
120 | SIGNAL lclk2x : STD_ULOGIC; |
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120 | SIGNAL lclk2x : STD_ULOGIC; | |
121 | SIGNAL lclk25MHz : STD_ULOGIC; |
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121 | SIGNAL lclk25MHz : STD_ULOGIC; | |
122 | SIGNAL lclk50MHz : STD_ULOGIC; |
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122 | SIGNAL lclk50MHz : STD_ULOGIC; | |
123 | SIGNAL lclk100MHz : STD_ULOGIC; |
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123 | SIGNAL lclk100MHz : STD_ULOGIC; | |
124 | SIGNAL clkm : STD_ULOGIC; |
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124 | SIGNAL clkm : STD_ULOGIC; | |
125 | SIGNAL rstn : STD_ULOGIC; |
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125 | SIGNAL rstn : STD_ULOGIC; | |
126 | SIGNAL rstraw : STD_ULOGIC; |
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126 | SIGNAL rstraw : STD_ULOGIC; | |
127 | SIGNAL pciclk : STD_ULOGIC; |
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127 | SIGNAL pciclk : STD_ULOGIC; | |
128 | SIGNAL sdclkl : STD_ULOGIC; |
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128 | SIGNAL sdclkl : STD_ULOGIC; | |
129 | SIGNAL cgi : clkgen_in_type; |
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129 | SIGNAL cgi : clkgen_in_type; | |
130 | SIGNAL cgo : clkgen_out_type; |
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130 | SIGNAL cgo : clkgen_out_type; | |
131 | --- AHB / APB |
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131 | --- AHB / APB | |
132 | SIGNAL apbi : apb_slv_in_type; |
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132 | SIGNAL apbi : apb_slv_in_type; | |
133 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); |
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133 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); | |
134 | SIGNAL ahbsi : ahb_slv_in_type; |
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134 | SIGNAL ahbsi : ahb_slv_in_type; | |
135 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); |
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135 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); | |
136 | SIGNAL ahbmi : ahb_mst_in_type; |
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136 | SIGNAL ahbmi : ahb_mst_in_type; | |
137 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); |
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137 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); | |
138 | --UART |
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138 | --UART | |
139 | SIGNAL ahbuarti : uart_in_type; |
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139 | SIGNAL ahbuarti : uart_in_type; | |
140 | SIGNAL ahbuarto : uart_out_type; |
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140 | SIGNAL ahbuarto : uart_out_type; | |
141 | SIGNAL apbuarti : uart_in_type; |
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141 | SIGNAL apbuarti : uart_in_type; | |
142 | SIGNAL apbuarto : uart_out_type; |
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142 | SIGNAL apbuarto : uart_out_type; | |
143 | --MEM CTRLR |
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143 | --MEM CTRLR | |
144 | SIGNAL memi : memory_in_type; |
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144 | SIGNAL memi : memory_in_type; | |
145 | SIGNAL memo : memory_out_type; |
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145 | SIGNAL memo : memory_out_type; | |
146 | SIGNAL wpo : wprot_out_type; |
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146 | SIGNAL wpo : wprot_out_type; | |
147 | SIGNAL sdo : sdram_out_type; |
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147 | SIGNAL sdo : sdram_out_type; | |
148 | SIGNAL ramcs : STD_ULOGIC; |
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148 | SIGNAL ramcs : STD_ULOGIC; | |
149 | --IRQ |
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149 | --IRQ | |
150 | SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); |
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150 | SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); | |
151 | SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); |
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151 | SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); | |
152 | --Timer |
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152 | --Timer | |
153 | SIGNAL gpti : gptimer_in_type; |
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153 | SIGNAL gpti : gptimer_in_type; | |
154 | SIGNAL gpto : gptimer_out_type; |
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154 | SIGNAL gpto : gptimer_out_type; | |
155 | --GPIO |
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155 | --GPIO | |
156 | SIGNAL gpioi : gpio_in_type; |
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156 | SIGNAL gpioi : gpio_in_type; | |
157 | SIGNAL gpioo : gpio_out_type; |
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157 | SIGNAL gpioo : gpio_out_type; | |
158 | --DSU |
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158 | --DSU | |
159 | SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); |
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159 | SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); | |
160 | SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); |
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160 | SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); | |
161 | SIGNAL dsui : dsu_in_type; |
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161 | SIGNAL dsui : dsu_in_type; | |
162 | SIGNAL dsuo : dsu_out_type; |
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162 | SIGNAL dsuo : dsu_out_type; | |
163 |
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163 | |||
164 | --------------------------------------------------------------------- |
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164 | --------------------------------------------------------------------- | |
165 | --- AJOUT TEST ------------------------Signaux---------------------- |
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165 | --- AJOUT TEST ------------------------Signaux---------------------- | |
166 | --------------------------------------------------------------------- |
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166 | --------------------------------------------------------------------- | |
167 |
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167 | |||
168 | --------------------------------------------------------------------- |
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168 | --------------------------------------------------------------------- | |
169 | CONSTANT IOAEN : INTEGER := CFG_CAN; |
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169 | CONSTANT IOAEN : INTEGER := CFG_CAN; | |
170 | CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz |
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170 | CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz | |
171 |
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171 | |||
172 | -- time management signal |
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172 | -- time management signal | |
173 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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173 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
174 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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174 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
175 |
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175 | |||
176 | -- Spacewire signals |
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176 | -- Spacewire signals | |
177 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE |
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177 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE | |
178 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE |
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178 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE | |
179 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE |
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179 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE | |
180 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
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180 | SIGNAL spw_rxtxclk : STD_ULOGIC; | |
181 | SIGNAL spw_rxclkn : STD_ULOGIC; |
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181 | SIGNAL spw_rxclkn : STD_ULOGIC; | |
182 | SIGNAL spw_clk : STD_LOGIC; |
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182 | SIGNAL spw_clk : STD_LOGIC; | |
183 | SIGNAL swni : grspw_in_type; -- PLE |
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183 | SIGNAL swni : grspw_in_type; -- PLE | |
184 | SIGNAL swno : grspw_out_type; -- PLE |
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184 | SIGNAL swno : grspw_out_type; -- PLE | |
185 | SIGNAL clkmn : STD_ULOGIC; -- PLE |
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185 | SIGNAL clkmn : STD_ULOGIC; -- PLE | |
186 | SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14 |
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186 | SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14 | |
187 |
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187 | |||
188 | -- AD Converter RHF1401 |
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188 | -- AD Converter RHF1401 | |
189 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
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189 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
190 | SIGNAL sample_val : STD_LOGIC; |
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190 | SIGNAL sample_val : STD_LOGIC; | |
191 | ----------------------------------------------------------------------------- |
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191 | ----------------------------------------------------------------------------- | |
192 | SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0); |
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192 | SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
193 | ----------------------------------------------------------------------------- |
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193 | ----------------------------------------------------------------------------- | |
194 | SIGNAL debug_f0_data : STD_LOGIC_VECTOR(95 DOWNTO 0); |
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194 | SIGNAL debug_f0_data : STD_LOGIC_VECTOR(95 DOWNTO 0); | |
195 | SIGNAL debug_f0_data_valid : STD_LOGIC; |
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195 | SIGNAL debug_f0_data_valid : STD_LOGIC; | |
196 | SIGNAL debug_f1_data : STD_LOGIC_VECTOR(95 DOWNTO 0); |
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196 | SIGNAL debug_f1_data : STD_LOGIC_VECTOR(95 DOWNTO 0); | |
197 | SIGNAL debug_f1_data_valid : STD_LOGIC; |
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197 | SIGNAL debug_f1_data_valid : STD_LOGIC; | |
198 | SIGNAL debug_f2_data : STD_LOGIC_VECTOR(95 DOWNTO 0); |
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198 | SIGNAL debug_f2_data : STD_LOGIC_VECTOR(95 DOWNTO 0); | |
199 | SIGNAL debug_f2_data_valid : STD_LOGIC; |
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199 | SIGNAL debug_f2_data_valid : STD_LOGIC; | |
200 | SIGNAL debug_f3_data : STD_LOGIC_VECTOR(95 DOWNTO 0); |
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200 | SIGNAL debug_f3_data : STD_LOGIC_VECTOR(95 DOWNTO 0); | |
201 | SIGNAL debug_f3_data_valid : STD_LOGIC; |
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201 | SIGNAL debug_f3_data_valid : STD_LOGIC; | |
202 |
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202 | |||
203 | BEGIN |
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203 | BEGIN | |
204 |
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204 | |||
205 |
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205 | |||
206 | ---------------------------------------------------------------------- |
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206 | ---------------------------------------------------------------------- | |
207 | --- Reset and Clock generation ------------------------------------- |
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207 | --- Reset and Clock generation ------------------------------------- | |
208 | ---------------------------------------------------------------------- |
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208 | ---------------------------------------------------------------------- | |
209 |
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209 | |||
210 | vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0'); |
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210 | vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0'); | |
211 | cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; |
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211 | cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; | |
212 |
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212 | |||
213 | rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); |
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213 | rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); | |
214 |
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214 | |||
215 |
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215 | |||
216 | clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz); |
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216 | clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz); | |
217 |
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217 | |||
218 | clkgen0 : clkgen -- clock generator |
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218 | clkgen0 : clkgen -- clock generator | |
219 | GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, |
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219 | GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, | |
220 | CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) |
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220 | CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) | |
221 | PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); |
|
221 | PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); | |
222 |
|
222 | |||
223 | PROCESS(lclk100MHz) |
|
223 | PROCESS(lclk100MHz) | |
224 | BEGIN |
|
224 | BEGIN | |
225 | IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN |
|
225 | IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN | |
226 | lclk50MHz <= NOT lclk50MHz; |
|
226 | lclk50MHz <= NOT lclk50MHz; | |
227 | END IF; |
|
227 | END IF; | |
228 | END PROCESS; |
|
228 | END PROCESS; | |
229 |
|
229 | |||
230 | PROCESS(lclk50MHz) |
|
230 | PROCESS(lclk50MHz) | |
231 | BEGIN |
|
231 | BEGIN | |
232 | IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN |
|
232 | IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN | |
233 | lclk25MHz <= NOT lclk25MHz; |
|
233 | lclk25MHz <= NOT lclk25MHz; | |
234 | END IF; |
|
234 | END IF; | |
235 | END PROCESS; |
|
235 | END PROCESS; | |
236 |
|
236 | |||
237 | lclk2x <= lclk50MHz; |
|
237 | lclk2x <= lclk50MHz; | |
238 | spw_clk <= lclk50MHz; |
|
238 | spw_clk <= lclk50MHz; | |
239 |
|
239 | |||
240 | ---------------------------------------------------------------------- |
|
240 | ---------------------------------------------------------------------- | |
241 | --- LEON3 processor / DSU / IRQ ------------------------------------ |
|
241 | --- LEON3 processor / DSU / IRQ ------------------------------------ | |
242 | ---------------------------------------------------------------------- |
|
242 | ---------------------------------------------------------------------- | |
243 |
|
243 | |||
244 | l3 : IF CFG_LEON3 = 1 GENERATE |
|
244 | l3 : IF CFG_LEON3 = 1 GENERATE | |
245 | cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE |
|
245 | cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE | |
246 | u0 : leon3s -- LEON3 processor |
|
246 | u0 : leon3s -- LEON3 processor | |
247 | GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, |
|
247 | GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, | |
248 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, |
|
248 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, | |
249 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, |
|
249 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, | |
250 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, |
|
250 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, | |
251 | CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, |
|
251 | CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, | |
252 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) |
|
252 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) | |
253 | PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, |
|
253 | PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, | |
254 | irqi(i), irqo(i), dbgi(i), dbgo(i)); |
|
254 | irqi(i), irqo(i), dbgi(i), dbgo(i)); | |
255 | END GENERATE; |
|
255 | END GENERATE; | |
256 | errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); |
|
256 | errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); | |
257 |
|
257 | |||
258 | dsugen : IF CFG_DSU = 1 GENERATE |
|
258 | dsugen : IF CFG_DSU = 1 GENERATE | |
259 | dsu0 : dsu3 -- LEON3 Debug Support Unit |
|
259 | dsu0 : dsu3 -- LEON3 Debug Support Unit | |
260 | GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, |
|
260 | GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, | |
261 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) |
|
261 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) | |
262 | PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); |
|
262 | PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); | |
263 | dsui.enable <= '1'; |
|
263 | dsui.enable <= '1'; | |
264 | dsui.break <= '0'; |
|
264 | dsui.break <= '0'; | |
265 | led(2) <= dsuo.active; |
|
265 | led(2) <= dsuo.active; | |
266 | END GENERATE; |
|
266 | END GENERATE; | |
267 | END GENERATE; |
|
267 | END GENERATE; | |
268 |
|
268 | |||
269 | nodsu : IF CFG_DSU = 0 GENERATE |
|
269 | nodsu : IF CFG_DSU = 0 GENERATE | |
270 | ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; |
|
270 | ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; | |
271 | END GENERATE; |
|
271 | END GENERATE; | |
272 |
|
272 | |||
273 | irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE |
|
273 | irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE | |
274 | irqctrl0 : irqmp -- interrupt controller |
|
274 | irqctrl0 : irqmp -- interrupt controller | |
275 | GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) |
|
275 | GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) | |
276 | PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); |
|
276 | PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); | |
277 | END GENERATE; |
|
277 | END GENERATE; | |
278 | irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE |
|
278 | irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE | |
279 | x : FOR i IN 0 TO CFG_NCPU-1 GENERATE |
|
279 | x : FOR i IN 0 TO CFG_NCPU-1 GENERATE | |
280 | irqi(i).irl <= "0000"; |
|
280 | irqi(i).irl <= "0000"; | |
281 | END GENERATE; |
|
281 | END GENERATE; | |
282 | apbo(2) <= apb_none; |
|
282 | apbo(2) <= apb_none; | |
283 | END GENERATE; |
|
283 | END GENERATE; | |
284 |
|
284 | |||
285 | ---------------------------------------------------------------------- |
|
285 | ---------------------------------------------------------------------- | |
286 | --- Memory controllers --------------------------------------------- |
|
286 | --- Memory controllers --------------------------------------------- | |
287 | ---------------------------------------------------------------------- |
|
287 | ---------------------------------------------------------------------- | |
288 | memctrlr : mctrl GENERIC MAP ( |
|
288 | memctrlr : mctrl GENERIC MAP ( | |
289 | hindex => 0, |
|
289 | hindex => 0, | |
290 | pindex => 0, |
|
290 | pindex => 0, | |
291 | paddr => 0, |
|
291 | paddr => 0, | |
292 | srbanks => 1 |
|
292 | srbanks => 1 | |
293 | ) |
|
293 | ) | |
294 | PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); |
|
294 | PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); | |
295 |
|
295 | |||
296 | memi.brdyn <= '1'; |
|
296 | memi.brdyn <= '1'; | |
297 | memi.bexcn <= '1'; |
|
297 | memi.bexcn <= '1'; | |
298 | memi.writen <= '1'; |
|
298 | memi.writen <= '1'; | |
299 | memi.wrn <= "1111"; |
|
299 | memi.wrn <= "1111"; | |
300 | memi.bwidth <= "10"; |
|
300 | memi.bwidth <= "10"; | |
301 |
|
301 | |||
302 | bdr : FOR i IN 0 TO 3 GENERATE |
|
302 | bdr : FOR i IN 0 TO 3 GENERATE | |
303 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) |
|
303 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) | |
304 | PORT MAP ( |
|
304 | PORT MAP ( | |
305 | data(31-i*8 DOWNTO 24-i*8), |
|
305 | data(31-i*8 DOWNTO 24-i*8), | |
306 | memo.data(31-i*8 DOWNTO 24-i*8), |
|
306 | memo.data(31-i*8 DOWNTO 24-i*8), | |
307 | memo.bdrive(i), |
|
307 | memo.bdrive(i), | |
308 | memi.data(31-i*8 DOWNTO 24-i*8)); |
|
308 | memi.data(31-i*8 DOWNTO 24-i*8)); | |
309 | END GENERATE; |
|
309 | END GENERATE; | |
310 |
|
310 | |||
311 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) |
|
311 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) | |
312 | PORT MAP (address, memo.address(21 DOWNTO 2)); |
|
312 | PORT MAP (address, memo.address(21 DOWNTO 2)); | |
313 |
|
313 | |||
314 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0))); |
|
314 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0))); | |
315 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); |
|
315 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); | |
316 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); |
|
316 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); | |
317 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); |
|
317 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); | |
318 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); |
|
318 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); | |
319 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); |
|
319 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); | |
320 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); |
|
320 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); | |
321 |
|
321 | |||
322 | ---------------------------------------------------------------------- |
|
322 | ---------------------------------------------------------------------- | |
323 | --- AHB CONTROLLER ------------------------------------------------- |
|
323 | --- AHB CONTROLLER ------------------------------------------------- | |
324 | ---------------------------------------------------------------------- |
|
324 | ---------------------------------------------------------------------- | |
325 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
|
325 | ahb0 : ahbctrl -- AHB arbiter/multiplexer | |
326 | GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, |
|
326 | GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, | |
327 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, |
|
327 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, | |
328 | ioen => IOAEN, nahbm => maxahbm, nahbs => 8) |
|
328 | ioen => IOAEN, nahbm => maxahbm, nahbs => 8) | |
329 | PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); |
|
329 | PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); | |
330 |
|
330 | |||
331 | ---------------------------------------------------------------------- |
|
331 | ---------------------------------------------------------------------- | |
332 | --- AHB UART ------------------------------------------------------- |
|
332 | --- AHB UART ------------------------------------------------------- | |
333 | ---------------------------------------------------------------------- |
|
333 | ---------------------------------------------------------------------- | |
334 | dcomgen : IF CFG_AHB_UART = 1 GENERATE |
|
334 | dcomgen : IF CFG_AHB_UART = 1 GENERATE | |
335 | dcom0 : ahbuart |
|
335 | dcom0 : ahbuart | |
336 | GENERIC MAP (hindex => 3, pindex => 4, paddr => 4) |
|
336 | GENERIC MAP (hindex => 3, pindex => 4, paddr => 4) | |
337 | PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3)); |
|
337 | PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3)); | |
338 | dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); |
|
338 | dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); | |
339 | dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); |
|
339 | dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); | |
340 | led(0) <= NOT ahbuarti.rxd; |
|
340 | led(0) <= NOT ahbuarti.rxd; | |
341 | led(1) <= NOT ahbuarto.txd; |
|
341 | led(1) <= NOT ahbuarto.txd; | |
342 | END GENERATE; |
|
342 | END GENERATE; | |
343 | nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; |
|
343 | nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; | |
344 |
|
344 | |||
345 | ---------------------------------------------------------------------- |
|
345 | ---------------------------------------------------------------------- | |
346 | --- APB Bridge ----------------------------------------------------- |
|
346 | --- APB Bridge ----------------------------------------------------- | |
347 | ---------------------------------------------------------------------- |
|
347 | ---------------------------------------------------------------------- | |
348 | apb0 : apbctrl -- AHB/APB bridge |
|
348 | apb0 : apbctrl -- AHB/APB bridge | |
349 | GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) |
|
349 | GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) | |
350 | PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); |
|
350 | PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); | |
351 |
|
351 | |||
352 | ---------------------------------------------------------------------- |
|
352 | ---------------------------------------------------------------------- | |
353 | --- GPT Timer ------------------------------------------------------ |
|
353 | --- GPT Timer ------------------------------------------------------ | |
354 | ---------------------------------------------------------------------- |
|
354 | ---------------------------------------------------------------------- | |
355 | gpt : IF CFG_GPT_ENABLE /= 0 GENERATE |
|
355 | gpt : IF CFG_GPT_ENABLE /= 0 GENERATE | |
356 | timer0 : gptimer -- timer unit |
|
356 | timer0 : gptimer -- timer unit | |
357 | GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, |
|
357 | GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, | |
358 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, |
|
358 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, | |
359 | nbits => CFG_GPT_TW) |
|
359 | nbits => CFG_GPT_TW) | |
360 | PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); |
|
360 | PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); | |
361 | gpti.dhalt <= dsuo.tstop; |
|
361 | gpti.dhalt <= dsuo.tstop; | |
362 | gpti.extclk <= '0'; |
|
362 | gpti.extclk <= '0'; | |
363 | END GENERATE; |
|
363 | END GENERATE; | |
364 | notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; |
|
364 | notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; | |
365 |
|
365 | |||
366 |
|
366 | |||
367 | ---------------------------------------------------------------------- |
|
367 | ---------------------------------------------------------------------- | |
368 | --- APB UART ------------------------------------------------------- |
|
368 | --- APB UART ------------------------------------------------------- | |
369 | ---------------------------------------------------------------------- |
|
369 | ---------------------------------------------------------------------- | |
370 | ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE |
|
370 | ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE | |
371 | uart1 : apbuart -- UART 1 |
|
371 | uart1 : apbuart -- UART 1 | |
372 | GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, |
|
372 | GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, | |
373 | fifosize => CFG_UART1_FIFO) |
|
373 | fifosize => CFG_UART1_FIFO) | |
374 | PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); |
|
374 | PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); | |
375 | apbuarti.rxd <= urxd1; |
|
375 | apbuarti.rxd <= urxd1; | |
376 | apbuarti.extclk <= '0'; |
|
376 | apbuarti.extclk <= '0'; | |
377 | utxd1 <= apbuarto.txd; |
|
377 | utxd1 <= apbuarto.txd; | |
378 | apbuarti.ctsn <= '0'; |
|
378 | apbuarti.ctsn <= '0'; | |
379 | END GENERATE; |
|
379 | END GENERATE; | |
380 | noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; |
|
380 | noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; | |
381 |
|
381 | |||
382 | ------------------------------------------------------------------------------- |
|
382 | ------------------------------------------------------------------------------- | |
383 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
|
383 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- | |
384 | ------------------------------------------------------------------------------- |
|
384 | ------------------------------------------------------------------------------- | |
385 | apb_lfr_time_management_1: apb_lfr_time_management |
|
385 | apb_lfr_time_management_1: apb_lfr_time_management | |
386 | GENERIC MAP ( |
|
386 | GENERIC MAP ( | |
387 | pindex => 6, |
|
387 | pindex => 6, | |
388 | paddr => 6, |
|
388 | paddr => 6, | |
389 | pmask => 16#fff#, |
|
389 | pmask => 16#fff#, | |
390 | pirq => 12) |
|
390 | pirq => 12) | |
391 | PORT MAP ( |
|
391 | PORT MAP ( | |
392 | clk25MHz => clkm, |
|
392 | clk25MHz => clkm, | |
393 | clk49_152MHz => clk49_152MHz, |
|
393 | clk49_152MHz => clk49_152MHz, | |
394 | resetn => rstn, |
|
394 | resetn => rstn, | |
395 | grspw_tick => swno.tickout, |
|
395 | grspw_tick => swno.tickout, | |
396 | apbi => apbi, |
|
396 | apbi => apbi, | |
397 | apbo => apbo(6), |
|
397 | apbo => apbo(6), | |
398 | coarse_time => coarse_time, |
|
398 | coarse_time => coarse_time, | |
399 | fine_time => fine_time); |
|
399 | fine_time => fine_time); | |
400 |
|
400 | |||
401 | ----------------------------------------------------------------------- |
|
401 | ----------------------------------------------------------------------- | |
402 | --- SpaceWire -------------------------------------------------------- |
|
402 | --- SpaceWire -------------------------------------------------------- | |
403 | ----------------------------------------------------------------------- |
|
403 | ----------------------------------------------------------------------- | |
404 |
|
404 | |||
405 | spw_rxtxclk <= spw_clk; |
|
405 | spw_rxtxclk <= spw_clk; | |
406 | spw_rxclkn <= NOT spw_rxtxclk; |
|
406 | spw_rxclkn <= NOT spw_rxtxclk; | |
407 |
|
407 | |||
408 | -- PADS for SPW1 |
|
408 | -- PADS for SPW1 | |
409 | spw1_rxd_pad : inpad GENERIC MAP (tech => padtech) |
|
409 | spw1_rxd_pad : inpad GENERIC MAP (tech => padtech) | |
410 | PORT MAP (spw1_din, dtmp(0)); |
|
410 | PORT MAP (spw1_din, dtmp(0)); | |
411 | spw1_rxs_pad : inpad GENERIC MAP (tech => padtech) |
|
411 | spw1_rxs_pad : inpad GENERIC MAP (tech => padtech) | |
412 | PORT MAP (spw1_sin, stmp(0)); |
|
412 | PORT MAP (spw1_sin, stmp(0)); | |
413 | spw1_txd_pad : outpad GENERIC MAP (tech => padtech) |
|
413 | spw1_txd_pad : outpad GENERIC MAP (tech => padtech) | |
414 | PORT MAP (spw1_dout, swno.d(0)); |
|
414 | PORT MAP (spw1_dout, swno.d(0)); | |
415 | spw1_txs_pad : outpad GENERIC MAP (tech => padtech) |
|
415 | spw1_txs_pad : outpad GENERIC MAP (tech => padtech) | |
416 | PORT MAP (spw1_sout, swno.s(0)); |
|
416 | PORT MAP (spw1_sout, swno.s(0)); | |
417 | -- PADS FOR SPW2 |
|
417 | -- PADS FOR SPW2 | |
418 | spw2_rxd_pad : inpad GENERIC MAP (tech => padtech) |
|
418 | spw2_rxd_pad : inpad GENERIC MAP (tech => padtech) | |
419 | PORT MAP (spw2_din, dtmp(1)); |
|
419 | PORT MAP (spw2_din, dtmp(1)); | |
420 | spw2_rxs_pad : inpad GENERIC MAP (tech => padtech) |
|
420 | spw2_rxs_pad : inpad GENERIC MAP (tech => padtech) | |
421 | PORT MAP (spw2_sin, stmp(1)); |
|
421 | PORT MAP (spw2_sin, stmp(1)); | |
422 | spw2_txd_pad : outpad GENERIC MAP (tech => padtech) |
|
422 | spw2_txd_pad : outpad GENERIC MAP (tech => padtech) | |
423 | PORT MAP (spw2_dout, swno.d(1)); |
|
423 | PORT MAP (spw2_dout, swno.d(1)); | |
424 | spw2_txs_pad : outpad GENERIC MAP (tech => padtech) |
|
424 | spw2_txs_pad : outpad GENERIC MAP (tech => padtech) | |
425 | PORT MAP (spw2_sout, swno.s(1)); |
|
425 | PORT MAP (spw2_sout, swno.s(1)); | |
426 |
|
426 | |||
427 | -- GRSPW PHY |
|
427 | -- GRSPW PHY | |
428 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
|
428 | --spw1_input: if CFG_SPW_GRSPW = 1 generate | |
429 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
|
429 | spw_inputloop : FOR j IN 0 TO 1 GENERATE | |
430 | spw_phy0 : grspw_phy |
|
430 | spw_phy0 : grspw_phy | |
431 | GENERIC MAP( |
|
431 | GENERIC MAP( | |
432 | tech => fabtech, |
|
432 | tech => fabtech, | |
433 | rxclkbuftype => 1, |
|
433 | rxclkbuftype => 1, | |
434 | scantest => 0) |
|
434 | scantest => 0) | |
435 | PORT MAP( |
|
435 | PORT MAP( | |
436 | rxrst => swno.rxrst, |
|
436 | rxrst => swno.rxrst, | |
437 | di => dtmp(j), |
|
437 | di => dtmp(j), | |
438 | si => stmp(j), |
|
438 | si => stmp(j), | |
439 | rxclko => spw_rxclk(j), |
|
439 | rxclko => spw_rxclk(j), | |
440 | do => swni.d(j), |
|
440 | do => swni.d(j), | |
441 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
|
441 | ndo => swni.nd(j*5+4 DOWNTO j*5), | |
442 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
442 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); | |
443 | END GENERATE spw_inputloop; |
|
443 | END GENERATE spw_inputloop; | |
444 |
|
444 | |||
445 | -- SPW core |
|
445 | -- SPW core | |
446 | sw0 : grspwm |
|
446 | sw0 : grspwm | |
447 | GENERIC MAP( |
|
447 | GENERIC MAP( | |
448 | tech => apa3e, |
|
448 | tech => apa3e, | |
449 | hindex => 1, |
|
449 | hindex => 1, | |
450 | pindex => 5, |
|
450 | pindex => 5, | |
451 | paddr => 5, |
|
451 | paddr => 5, | |
452 | pirq => 11, |
|
452 | pirq => 11, | |
453 | sysfreq => 25000, -- CPU_FREQ |
|
453 | sysfreq => 25000, -- CPU_FREQ | |
454 | rmap => 1, |
|
454 | rmap => 1, | |
455 | rmapcrc => 1, |
|
455 | rmapcrc => 1, | |
456 | fifosize1 => 16, |
|
456 | fifosize1 => 16, | |
457 | fifosize2 => 16, |
|
457 | fifosize2 => 16, | |
458 | rxclkbuftype => 1, |
|
458 | rxclkbuftype => 1, | |
459 | rxunaligned => 0, |
|
459 | rxunaligned => 0, | |
460 | rmapbufs => 4, |
|
460 | rmapbufs => 4, | |
461 | ft => 0, |
|
461 | ft => 0, | |
462 | netlist => 0, |
|
462 | netlist => 0, | |
463 | ports => 2, |
|
463 | ports => 2, | |
464 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
|
464 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 | |
465 | memtech => apa3e, |
|
465 | memtech => apa3e, | |
466 | destkey => 2, |
|
466 | destkey => 2, | |
467 | spwcore => 1 |
|
467 | spwcore => 1 | |
468 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
|
468 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 | |
469 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
|
469 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 | |
470 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
|
470 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 | |
471 | ) |
|
471 | ) | |
472 | PORT MAP(rstn, clkm, spw_rxclk(0), |
|
472 | PORT MAP(rstn, clkm, spw_rxclk(0), | |
473 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
|
473 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, | |
474 | ahbmi, ahbmo(1), apbi, apbo(5), |
|
474 | ahbmi, ahbmo(1), apbi, apbo(5), | |
475 | swni, swno); |
|
475 | swni, swno); | |
476 |
|
476 | |||
477 | swni.tickin <= '0'; |
|
477 | swni.tickin <= '0'; | |
478 | swni.rmapen <= '1'; |
|
478 | swni.rmapen <= '1'; | |
479 | swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz |
|
479 | swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz | |
480 | swni.tickinraw <= '0'; |
|
480 | swni.tickinraw <= '0'; | |
481 | swni.timein <= (OTHERS => '0'); |
|
481 | swni.timein <= (OTHERS => '0'); | |
482 | swni.dcrstval <= (OTHERS => '0'); |
|
482 | swni.dcrstval <= (OTHERS => '0'); | |
483 | swni.timerrstval <= (OTHERS => '0'); |
|
483 | swni.timerrstval <= (OTHERS => '0'); | |
484 |
|
484 | |||
485 | ------------------------------------------------------------------------------- |
|
485 | ------------------------------------------------------------------------------- | |
486 | -- LFR |
|
486 | -- LFR | |
487 | ------------------------------------------------------------------------------- |
|
487 | ------------------------------------------------------------------------------- | |
488 | lpp_lfr_1 : lpp_lfr |
|
488 | lpp_lfr_1 : lpp_lfr | |
489 | GENERIC MAP ( |
|
489 | GENERIC MAP ( | |
490 | Mem_use => use_RAM, |
|
490 | Mem_use => use_RAM, | |
491 | nb_data_by_buffer_size => 32, |
|
491 | nb_data_by_buffer_size => 32, | |
492 | nb_word_by_buffer_size => 30, |
|
492 | nb_word_by_buffer_size => 30, | |
493 | nb_snapshot_param_size => 32, |
|
493 | nb_snapshot_param_size => 32, | |
494 | delta_vector_size => 32, |
|
494 | delta_vector_size => 32, | |
495 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
495 | delta_vector_size_f0_2 => 7, -- log2(96) | |
496 | pindex => 15, |
|
496 | pindex => 15, | |
497 | paddr => 15, |
|
497 | paddr => 15, | |
498 | pmask => 16#fff#, |
|
498 | pmask => 16#fff#, | |
499 | pirq_ms => 6, |
|
499 | pirq_ms => 6, | |
500 | pirq_wfp => 14, |
|
500 | pirq_wfp => 14, | |
501 | hindex => 2, |
|
501 | hindex => 2, | |
502 |
top_lfr_version => X"0000000 |
|
502 | top_lfr_version => X"00000009") | |
503 | PORT MAP ( |
|
503 | PORT MAP ( | |
504 | clk => clkm, |
|
504 | clk => clkm, | |
505 | rstn => rstn, |
|
505 | rstn => rstn, | |
506 | sample_B => sample(2 DOWNTO 0), |
|
506 | sample_B => sample(2 DOWNTO 0), | |
507 | sample_E => sample(7 DOWNTO 3), |
|
507 | sample_E => sample(7 DOWNTO 3), | |
508 | sample_val => sample_val, |
|
508 | sample_val => sample_val, | |
509 | apbi => apbi, |
|
509 | apbi => apbi, | |
510 | apbo => apbo(15), |
|
510 | apbo => apbo(15), | |
511 | ahbi => ahbmi, |
|
511 | ahbi => ahbmi, | |
512 | ahbo => ahbmo(2), |
|
512 | ahbo => ahbmo(2), | |
513 | coarse_time => coarse_time, |
|
513 | coarse_time => coarse_time, | |
514 | fine_time => fine_time, |
|
514 | fine_time => fine_time, | |
515 | data_shaping_BW => bias_fail_sw, |
|
515 | data_shaping_BW => bias_fail_sw, | |
516 |
|
516 | |||
517 | ------------------------------------------------------------------------- |
|
517 | ------------------------------------------------------------------------- | |
518 | debug_f0_data => debug_f0_data , |
|
518 | debug_f0_data => debug_f0_data , | |
519 | debug_f0_data_valid => debug_f0_data_valid, |
|
519 | debug_f0_data_valid => debug_f0_data_valid, | |
520 | debug_f1_data => debug_f1_data , |
|
520 | debug_f1_data => debug_f1_data , | |
521 | debug_f1_data_valid => debug_f1_data_valid, |
|
521 | debug_f1_data_valid => debug_f1_data_valid, | |
522 | debug_f2_data => debug_f2_data , |
|
522 | debug_f2_data => debug_f2_data , | |
523 | debug_f2_data_valid => debug_f2_data_valid, |
|
523 | debug_f2_data_valid => debug_f2_data_valid, | |
524 | debug_f3_data => debug_f3_data , |
|
524 | debug_f3_data => debug_f3_data , | |
525 | debug_f3_data_valid => debug_f3_data_valid |
|
525 | debug_f3_data_valid => debug_f3_data_valid | |
526 | ); |
|
526 | ); | |
527 |
|
527 | |||
528 | top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 |
|
528 | top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 | |
529 | GENERIC MAP ( |
|
529 | GENERIC MAP ( | |
530 | ChanelCount => 8, |
|
530 | ChanelCount => 8, | |
531 | ncycle_cnv_high => 79, |
|
531 | ncycle_cnv_high => 79, | |
532 | ncycle_cnv => 500) |
|
532 | ncycle_cnv => 500) | |
533 | PORT MAP ( |
|
533 | PORT MAP ( | |
534 | cnv_clk => clk49_152MHz, |
|
534 | cnv_clk => clk49_152MHz, | |
535 | cnv_rstn => rstn, |
|
535 | cnv_rstn => rstn, | |
536 | cnv => ADC_smpclk, |
|
536 | cnv => ADC_smpclk, | |
537 | clk => clkm, |
|
537 | clk => clkm, | |
538 | rstn => rstn, |
|
538 | rstn => rstn, | |
539 | ADC_data => ADC_data, |
|
539 | ADC_data => ADC_data, | |
540 | ADC_nOE => ADC_OEB_bar_CH, |
|
540 | ADC_nOE => ADC_OEB_bar_CH, | |
541 | sample => sample, |
|
541 | sample => sample, | |
542 | sample_val => sample_val); |
|
542 | sample_val => sample_val); | |
543 |
|
543 | |||
544 | END Behavioral; |
|
544 | END Behavioral; |
@@ -1,290 +1,299 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------- |
|
21 | ------------------------------------------------------------------------------- | |
22 | LIBRARY IEEE; |
|
22 | LIBRARY IEEE; | |
23 | USE IEEE.numeric_std.ALL; |
|
23 | USE IEEE.numeric_std.ALL; | |
24 | USE IEEE.std_logic_1164.ALL; |
|
24 | USE IEEE.std_logic_1164.ALL; | |
25 | LIBRARY grlib; |
|
25 | LIBRARY grlib; | |
26 | USE grlib.amba.ALL; |
|
26 | USE grlib.amba.ALL; | |
27 | USE grlib.stdlib.ALL; |
|
27 | USE grlib.stdlib.ALL; | |
28 | LIBRARY techmap; |
|
28 | LIBRARY techmap; | |
29 | USE techmap.gencomp.ALL; |
|
29 | USE techmap.gencomp.ALL; | |
30 | LIBRARY gaisler; |
|
30 | LIBRARY gaisler; | |
31 | USE gaisler.memctrl.ALL; |
|
31 | USE gaisler.memctrl.ALL; | |
32 | USE gaisler.leon3.ALL; |
|
32 | USE gaisler.leon3.ALL; | |
33 | USE gaisler.uart.ALL; |
|
33 | USE gaisler.uart.ALL; | |
34 | USE gaisler.misc.ALL; |
|
34 | USE gaisler.misc.ALL; | |
35 | USE gaisler.spacewire.ALL; -- PLE |
|
35 | USE gaisler.spacewire.ALL; -- PLE | |
36 | LIBRARY esa; |
|
36 | LIBRARY esa; | |
37 | USE esa.memoryctrl.ALL; |
|
37 | USE esa.memoryctrl.ALL; | |
38 | LIBRARY lpp; |
|
38 | LIBRARY lpp; | |
39 | USE lpp.lpp_memory.ALL; |
|
39 | USE lpp.lpp_memory.ALL; | |
40 | USE lpp.lpp_ad_conv.ALL; |
|
40 | USE lpp.lpp_ad_conv.ALL; | |
41 | USE lpp.lpp_lfr_pkg.ALL; |
|
41 | USE lpp.lpp_lfr_pkg.ALL; | |
42 | USE lpp.iir_filter.ALL; |
|
42 | USE lpp.iir_filter.ALL; | |
43 | USE lpp.general_purpose.ALL; |
|
43 | USE lpp.general_purpose.ALL; | |
44 | USE lpp.lpp_lfr_time_management.ALL; |
|
44 | USE lpp.lpp_lfr_time_management.ALL; | |
45 | USE lpp.lpp_leon3_soc_pkg.ALL; |
|
45 | USE lpp.lpp_leon3_soc_pkg.ALL; | |
46 | USE lpp.lpp_debug_lfr_pkg.ALL; |
|
46 | USE lpp.lpp_debug_lfr_pkg.ALL; | |
47 |
|
47 | |||
48 | ENTITY MINI_LFR_top IS |
|
48 | ENTITY MINI_LFR_top IS | |
49 |
|
49 | |||
50 | PORT ( |
|
50 | PORT ( | |
51 | clk_50 : IN STD_LOGIC; |
|
51 | clk_50 : IN STD_LOGIC; | |
52 | clk_49 : IN STD_LOGIC; |
|
52 | clk_49 : IN STD_LOGIC; | |
53 | reset : IN STD_LOGIC; |
|
53 | reset : IN STD_LOGIC; | |
54 | --BPs |
|
54 | --BPs | |
55 | BP0 : IN STD_LOGIC; |
|
55 | BP0 : IN STD_LOGIC; | |
56 | BP1 : IN STD_LOGIC; |
|
56 | BP1 : IN STD_LOGIC; | |
57 | --LEDs |
|
57 | --LEDs | |
58 | LED0 : OUT STD_LOGIC; |
|
58 | LED0 : OUT STD_LOGIC; | |
59 | LED1 : OUT STD_LOGIC; |
|
59 | LED1 : OUT STD_LOGIC; | |
60 | LED2 : OUT STD_LOGIC; |
|
60 | LED2 : OUT STD_LOGIC; | |
61 | --UARTs |
|
61 | --UARTs | |
62 | TXD1 : IN STD_LOGIC; |
|
62 | TXD1 : IN STD_LOGIC; | |
63 | RXD1 : OUT STD_LOGIC; |
|
63 | RXD1 : OUT STD_LOGIC; | |
64 | nCTS1 : OUT STD_LOGIC; |
|
64 | nCTS1 : OUT STD_LOGIC; | |
65 | nRTS1 : IN STD_LOGIC; |
|
65 | nRTS1 : IN STD_LOGIC; | |
66 |
|
66 | |||
67 | TXD2 : IN STD_LOGIC; |
|
67 | TXD2 : IN STD_LOGIC; | |
68 | RXD2 : OUT STD_LOGIC; |
|
68 | RXD2 : OUT STD_LOGIC; | |
69 | nCTS2 : OUT STD_LOGIC; |
|
69 | nCTS2 : OUT STD_LOGIC; | |
70 | nDTR2 : IN STD_LOGIC; |
|
70 | nDTR2 : IN STD_LOGIC; | |
71 | nRTS2 : IN STD_LOGIC; |
|
71 | nRTS2 : IN STD_LOGIC; | |
72 | nDCD2 : OUT STD_LOGIC; |
|
72 | nDCD2 : OUT STD_LOGIC; | |
73 |
|
73 | |||
74 | --EXT CONNECTOR |
|
74 | --EXT CONNECTOR | |
75 | IO0 : INOUT STD_LOGIC; |
|
75 | IO0 : INOUT STD_LOGIC; | |
76 | IO1 : INOUT STD_LOGIC; |
|
76 | IO1 : INOUT STD_LOGIC; | |
77 | IO2 : INOUT STD_LOGIC; |
|
77 | IO2 : INOUT STD_LOGIC; | |
78 | IO3 : INOUT STD_LOGIC; |
|
78 | IO3 : INOUT STD_LOGIC; | |
79 | IO4 : INOUT STD_LOGIC; |
|
79 | IO4 : INOUT STD_LOGIC; | |
80 | IO5 : INOUT STD_LOGIC; |
|
80 | IO5 : INOUT STD_LOGIC; | |
81 | IO6 : INOUT STD_LOGIC; |
|
81 | IO6 : INOUT STD_LOGIC; | |
82 | IO7 : INOUT STD_LOGIC; |
|
82 | IO7 : INOUT STD_LOGIC; | |
83 | IO8 : INOUT STD_LOGIC; |
|
83 | IO8 : INOUT STD_LOGIC; | |
84 | IO9 : INOUT STD_LOGIC; |
|
84 | IO9 : INOUT STD_LOGIC; | |
85 | IO10 : INOUT STD_LOGIC; |
|
85 | IO10 : INOUT STD_LOGIC; | |
86 | IO11 : INOUT STD_LOGIC; |
|
86 | IO11 : INOUT STD_LOGIC; | |
87 |
|
87 | |||
88 | --SPACE WIRE |
|
88 | --SPACE WIRE | |
89 | SPW_EN : OUT STD_LOGIC; -- 0 => off |
|
89 | SPW_EN : OUT STD_LOGIC; -- 0 => off | |
90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK |
|
90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK | |
91 | SPW_NOM_SIN : IN STD_LOGIC; |
|
91 | SPW_NOM_SIN : IN STD_LOGIC; | |
92 | SPW_NOM_DOUT : OUT STD_LOGIC; |
|
92 | SPW_NOM_DOUT : OUT STD_LOGIC; | |
93 | SPW_NOM_SOUT : OUT STD_LOGIC; |
|
93 | SPW_NOM_SOUT : OUT STD_LOGIC; | |
94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK |
|
94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK | |
95 | SPW_RED_SIN : IN STD_LOGIC; |
|
95 | SPW_RED_SIN : IN STD_LOGIC; | |
96 | SPW_RED_DOUT : OUT STD_LOGIC; |
|
96 | SPW_RED_DOUT : OUT STD_LOGIC; | |
97 | SPW_RED_SOUT : OUT STD_LOGIC; |
|
97 | SPW_RED_SOUT : OUT STD_LOGIC; | |
98 | -- MINI LFR ADC INPUTS |
|
98 | -- MINI LFR ADC INPUTS | |
99 | ADC_nCS : OUT STD_LOGIC; |
|
99 | ADC_nCS : OUT STD_LOGIC; | |
100 | ADC_CLK : OUT STD_LOGIC; |
|
100 | ADC_CLK : OUT STD_LOGIC; | |
101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
102 |
|
102 | |||
103 | -- SRAM |
|
103 | -- SRAM | |
104 | SRAM_nWE : OUT STD_LOGIC; |
|
104 | SRAM_nWE : OUT STD_LOGIC; | |
105 | SRAM_CE : OUT STD_LOGIC; |
|
105 | SRAM_CE : OUT STD_LOGIC; | |
106 | SRAM_nOE : OUT STD_LOGIC; |
|
106 | SRAM_nOE : OUT STD_LOGIC; | |
107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
|
108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |
109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
110 | ); |
|
110 | ); | |
111 |
|
111 | |||
112 | END MINI_LFR_top; |
|
112 | END MINI_LFR_top; | |
113 |
|
113 | |||
114 |
|
114 | |||
115 | ARCHITECTURE beh OF MINI_LFR_top IS |
|
115 | ARCHITECTURE beh OF MINI_LFR_top IS | |
116 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
|
116 | SIGNAL clk_50_s : STD_LOGIC := '0'; | |
117 | SIGNAL clk_25 : STD_LOGIC := '0'; |
|
117 | SIGNAL clk_25 : STD_LOGIC := '0'; | |
118 | ----------------------------------------------------------------------------- |
|
118 | ----------------------------------------------------------------------------- | |
119 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
119 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
120 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
120 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
121 | -- |
|
121 | -- | |
122 | SIGNAL errorn : STD_LOGIC; |
|
122 | SIGNAL errorn : STD_LOGIC; | |
123 | -- UART AHB --------------------------------------------------------------- |
|
123 | -- UART AHB --------------------------------------------------------------- | |
124 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data |
|
124 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data | |
125 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data |
|
125 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data | |
126 |
|
126 | |||
127 | -- UART APB --------------------------------------------------------------- |
|
127 | -- UART APB --------------------------------------------------------------- | |
128 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data |
|
128 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data | |
129 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data |
|
129 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data | |
130 | -- |
|
130 | -- | |
131 | SIGNAL I00_s : STD_LOGIC; |
|
131 | SIGNAL I00_s : STD_LOGIC; | |
132 | -- |
|
132 | -- | |
133 | CONSTANT NB_APB_SLAVE : INTEGER := 1; |
|
133 | CONSTANT NB_APB_SLAVE : INTEGER := 1; | |
134 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
|
134 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; | |
135 | CONSTANT NB_AHB_MASTER : INTEGER := 1; |
|
135 | CONSTANT NB_AHB_MASTER : INTEGER := 1; | |
136 |
|
136 | |||
137 | SIGNAL apbi_ext : apb_slv_in_type; |
|
137 | SIGNAL apbi_ext : apb_slv_in_type; | |
138 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5):= (OTHERS => apb_none); |
|
138 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5):= (OTHERS => apb_none); | |
139 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
|
139 | SIGNAL ahbi_s_ext : ahb_slv_in_type; | |
140 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none); |
|
140 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none); | |
141 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
|
141 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |
142 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none); |
|
142 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none); | |
|
143 | -- | |||
|
144 | SIGNAL IO_s : STD_LOGIC_VECTOR(11 DOWNTO 0); | |||
143 |
|
145 | |||
144 | BEGIN -- beh |
|
146 | BEGIN -- beh | |
145 |
|
147 | |||
146 | ----------------------------------------------------------------------------- |
|
148 | ----------------------------------------------------------------------------- | |
147 | -- CLK |
|
149 | -- CLK | |
148 | ----------------------------------------------------------------------------- |
|
150 | ----------------------------------------------------------------------------- | |
149 |
|
151 | |||
150 | PROCESS(clk_50) |
|
152 | PROCESS(clk_50) | |
151 | BEGIN |
|
153 | BEGIN | |
152 | IF clk_50'EVENT AND clk_50 = '1' THEN |
|
154 | IF clk_50'EVENT AND clk_50 = '1' THEN | |
153 | clk_50_s <= NOT clk_50_s; |
|
155 | clk_50_s <= NOT clk_50_s; | |
154 | END IF; |
|
156 | END IF; | |
155 | END PROCESS; |
|
157 | END PROCESS; | |
156 |
|
158 | |||
157 | PROCESS(clk_50_s) |
|
159 | PROCESS(clk_50_s) | |
158 | BEGIN |
|
160 | BEGIN | |
159 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
|
161 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN | |
160 | clk_25 <= NOT clk_25; |
|
162 | clk_25 <= NOT clk_25; | |
161 | END IF; |
|
163 | END IF; | |
162 | END PROCESS; |
|
164 | END PROCESS; | |
163 |
|
165 | |||
164 | ----------------------------------------------------------------------------- |
|
166 | ----------------------------------------------------------------------------- | |
165 |
|
167 | |||
166 | PROCESS (clk_25, reset) |
|
168 | PROCESS (clk_25, reset) | |
167 | BEGIN -- PROCESS |
|
169 | BEGIN -- PROCESS | |
168 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
170 | IF reset = '0' THEN -- asynchronous reset (active low) | |
169 | LED0 <= '0'; |
|
171 | LED0 <= '0'; | |
170 | LED1 <= '0'; |
|
172 | LED1 <= '0'; | |
171 | LED2 <= '0'; |
|
173 | LED2 <= '0'; | |
172 | IO1 <= '0'; |
|
174 | IO1 <= '0'; | |
173 | IO2 <= '1'; |
|
175 | IO2 <= '1'; | |
174 | IO3 <= '0'; |
|
176 | IO3 <= '0'; | |
175 | IO4 <= '0'; |
|
177 | IO4 <= '0'; | |
176 | IO5 <= '0'; |
|
178 | IO5 <= '0'; | |
177 | IO6 <= '0'; |
|
179 | IO6 <= '0'; | |
178 | IO7 <= '0'; |
|
180 | IO7 <= '0'; | |
179 |
IO8 <= ' |
|
181 | IO8 <= '0'; | |
|
182 | IO9 <= '0'; | |||
|
183 | IO10 <= '0'; | |||
|
184 | IO11 <= '0'; | |||
180 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge |
|
185 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge | |
181 | LED0 <= '0'; |
|
186 | LED0 <= '0'; | |
182 | LED1 <= '1'; |
|
187 | LED1 <= '1'; | |
183 | LED2 <= BP0; |
|
188 | LED2 <= BP0; | |
184 | IO1 <= '1'; |
|
189 | IO1 <= '1'; | |
185 | IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; |
|
190 | IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; | |
186 | IO3 <= ADC_SDO(0) OR ADC_SDO(1); |
|
191 | IO3 <= ADC_SDO(0) OR ADC_SDO(1); | |
187 | IO4 <= ADC_SDO(2) OR ADC_SDO(1); |
|
192 | IO4 <= ADC_SDO(2) OR ADC_SDO(1); | |
188 | IO5 <= ADC_SDO(3) OR ADC_SDO(4); |
|
193 | IO5 <= ADC_SDO(3) OR ADC_SDO(4); | |
189 | IO6 <= ADC_SDO(5) OR ADC_SDO(6) OR ADC_SDO(7); |
|
194 | IO6 <= ADC_SDO(5) OR ADC_SDO(6) OR ADC_SDO(7); | |
190 | IO7 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
|
195 | IO7 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |
191 |
IO8 <= |
|
196 | IO8 <= IO_s(8); | |
|
197 | IO9 <= IO_s(9); | |||
|
198 | IO10 <= IO_s(10); | |||
|
199 | IO11 <= IO_s(11); | |||
192 | END IF; |
|
200 | END IF; | |
193 | END PROCESS; |
|
201 | END PROCESS; | |
194 |
|
202 | |||
195 | PROCESS (clk_49, reset) |
|
203 | PROCESS (clk_49, reset) | |
196 | BEGIN -- PROCESS |
|
204 | BEGIN -- PROCESS | |
197 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
205 | IF reset = '0' THEN -- asynchronous reset (active low) | |
198 | I00_s <= '0'; |
|
206 | I00_s <= '0'; | |
199 | ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge |
|
207 | ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge | |
200 | I00_s <= NOT I00_s; |
|
208 | I00_s <= NOT I00_s; | |
201 | END IF; |
|
209 | END IF; | |
202 | END PROCESS; |
|
210 | END PROCESS; | |
203 | IO0 <= I00_s; |
|
211 | IO0 <= I00_s; | |
204 |
|
212 | |||
205 | --UARTs |
|
213 | --UARTs | |
206 | nCTS1 <= '1'; |
|
214 | nCTS1 <= '1'; | |
207 | nCTS2 <= '1'; |
|
215 | nCTS2 <= '1'; | |
208 | nDCD2 <= '1'; |
|
216 | nDCD2 <= '1'; | |
209 |
|
217 | |||
210 | --SPACE WIRE |
|
218 | --SPACE WIRE | |
211 | SPW_EN <= '0'; -- 0 => off |
|
219 | SPW_EN <= '0'; -- 0 => off | |
212 |
|
220 | |||
213 | SPW_NOM_DOUT <= '0'; |
|
221 | SPW_NOM_DOUT <= '0'; | |
214 | SPW_NOM_SOUT <= '0'; |
|
222 | SPW_NOM_SOUT <= '0'; | |
215 | SPW_RED_DOUT <= '0'; |
|
223 | SPW_RED_DOUT <= '0'; | |
216 | SPW_RED_SOUT <= '0'; |
|
224 | SPW_RED_SOUT <= '0'; | |
217 |
|
225 | |||
218 | ADC_nCS <= '0'; |
|
226 | ADC_nCS <= '0'; | |
219 | ADC_CLK <= '0'; |
|
227 | ADC_CLK <= '0'; | |
220 |
|
228 | |||
221 |
|
229 | |||
222 | ----------------------------------------------------------------------------- |
|
230 | ----------------------------------------------------------------------------- | |
223 | lpp_debug_dma_singleOrBurst_1: lpp_debug_dma_singleOrBurst |
|
231 | lpp_debug_dma_singleOrBurst_1: lpp_debug_dma_singleOrBurst | |
224 | GENERIC MAP ( |
|
232 | GENERIC MAP ( | |
225 | tech => apa3e, |
|
233 | tech => apa3e, | |
226 | hindex => 1, |
|
234 | hindex => 1, | |
227 | pindex => 5, |
|
235 | pindex => 5, | |
228 | paddr => 5, |
|
236 | paddr => 5, | |
229 | pmask => 16#fff#) |
|
237 | pmask => 16#fff#) | |
230 | PORT MAP ( |
|
238 | PORT MAP ( | |
231 | HCLK => clk_25, |
|
239 | HCLK => clk_25, | |
232 | HRESETn => reset , |
|
240 | HRESETn => reset , | |
233 | ahbmi => ahbi_m_ext , |
|
241 | ahbmi => ahbi_m_ext , | |
234 | ahbmo => ahbo_m_ext(1), |
|
242 | ahbmo => ahbo_m_ext(1), | |
235 | apbi => apbi_ext, |
|
243 | apbi => apbi_ext, | |
236 | apbo => apbo_ext(5), |
|
244 | apbo => apbo_ext(5), | |
237 | out_ren => IO11, |
|
245 | out_ren => IO_s(11), | |
238 | out_send => IO10, |
|
246 | out_send => IO_s(10), | |
239 | out_done => IO9 |
|
247 | out_done => IO_s(9), | |
|
248 | out_dmaout_okay => IO_s(8) | |||
240 | ); |
|
249 | ); | |
241 |
|
250 | |||
242 | ----------------------------------------------------------------------------- |
|
251 | ----------------------------------------------------------------------------- | |
243 |
|
252 | |||
244 | leon3_soc_1: leon3_soc |
|
253 | leon3_soc_1: leon3_soc | |
245 | GENERIC MAP ( |
|
254 | GENERIC MAP ( | |
246 | fabtech => apa3e, |
|
255 | fabtech => apa3e, | |
247 | memtech => apa3e, |
|
256 | memtech => apa3e, | |
248 | padtech => inferred, |
|
257 | padtech => inferred, | |
249 | clktech => inferred, |
|
258 | clktech => inferred, | |
250 | disas => 0, |
|
259 | disas => 0, | |
251 | dbguart => 0, |
|
260 | dbguart => 0, | |
252 | pclow => 2, |
|
261 | pclow => 2, | |
253 | clk_freq => 25000, |
|
262 | clk_freq => 25000, | |
254 | NB_CPU => 1, |
|
263 | NB_CPU => 1, | |
255 | ENABLE_FPU => 0, |
|
264 | ENABLE_FPU => 0, | |
256 | FPU_NETLIST => 0, |
|
265 | FPU_NETLIST => 0, | |
257 | ENABLE_DSU => 1, |
|
266 | ENABLE_DSU => 1, | |
258 | ENABLE_AHB_UART => 1, |
|
267 | ENABLE_AHB_UART => 1, | |
259 | ENABLE_APB_UART => 1, |
|
268 | ENABLE_APB_UART => 1, | |
260 | ENABLE_IRQMP => 1, |
|
269 | ENABLE_IRQMP => 1, | |
261 | ENABLE_GPT => 1, |
|
270 | ENABLE_GPT => 1, | |
262 | NB_AHB_MASTER => NB_AHB_MASTER, |
|
271 | NB_AHB_MASTER => NB_AHB_MASTER, | |
263 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
|
272 | NB_AHB_SLAVE => NB_AHB_SLAVE, | |
264 | NB_APB_SLAVE => NB_APB_SLAVE) |
|
273 | NB_APB_SLAVE => NB_APB_SLAVE) | |
265 | PORT MAP ( |
|
274 | PORT MAP ( | |
266 | clk => clk_25, |
|
275 | clk => clk_25, | |
267 | reset => reset, |
|
276 | reset => reset, | |
268 | errorn => errorn, |
|
277 | errorn => errorn, | |
269 | ahbrxd => TXD1, |
|
278 | ahbrxd => TXD1, | |
270 | ahbtxd => RXD1, |
|
279 | ahbtxd => RXD1, | |
271 | urxd1 => TXD2, |
|
280 | urxd1 => TXD2, | |
272 | utxd1 => RXD2, |
|
281 | utxd1 => RXD2, | |
273 | address => SRAM_A, |
|
282 | address => SRAM_A, | |
274 | data => SRAM_DQ, |
|
283 | data => SRAM_DQ, | |
275 | nSRAM_BE0 => SRAM_nBE(0), |
|
284 | nSRAM_BE0 => SRAM_nBE(0), | |
276 | nSRAM_BE1 => SRAM_nBE(1), |
|
285 | nSRAM_BE1 => SRAM_nBE(1), | |
277 | nSRAM_BE2 => SRAM_nBE(2), |
|
286 | nSRAM_BE2 => SRAM_nBE(2), | |
278 | nSRAM_BE3 => SRAM_nBE(3), |
|
287 | nSRAM_BE3 => SRAM_nBE(3), | |
279 | nSRAM_WE => SRAM_nWE, |
|
288 | nSRAM_WE => SRAM_nWE, | |
280 | nSRAM_CE => SRAM_CE, |
|
289 | nSRAM_CE => SRAM_CE, | |
281 | nSRAM_OE => SRAM_nOE, |
|
290 | nSRAM_OE => SRAM_nOE, | |
282 |
|
291 | |||
283 | apbi_ext => apbi_ext, |
|
292 | apbi_ext => apbi_ext, | |
284 | apbo_ext => apbo_ext, |
|
293 | apbo_ext => apbo_ext, | |
285 | ahbi_s_ext => ahbi_s_ext, |
|
294 | ahbi_s_ext => ahbi_s_ext, | |
286 | ahbo_s_ext => ahbo_s_ext, |
|
295 | ahbo_s_ext => ahbo_s_ext, | |
287 | ahbi_m_ext => ahbi_m_ext, |
|
296 | ahbi_m_ext => ahbi_m_ext, | |
288 | ahbo_m_ext => ahbo_m_ext); |
|
297 | ahbo_m_ext => ahbo_m_ext); | |
289 |
|
298 | |||
290 | END beh; |
|
299 | END beh; |
@@ -1,199 +1,201 | |||||
1 |
|
1 | |||
2 | ------------------------------------------------------------------------------ |
|
2 | ------------------------------------------------------------------------------ | |
3 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | -- This file is a part of the LPP VHDL IP LIBRARY | |
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
5 | -- |
|
5 | -- | |
6 | -- This program is free software; you can redistribute it and/or modify |
|
6 | -- This program is free software; you can redistribute it and/or modify | |
7 | -- it under the terms of the GNU General Public License as published by |
|
7 | -- it under the terms of the GNU General Public License as published by | |
8 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | -- the Free Software Foundation; either version 3 of the License, or | |
9 | -- (at your option) any later version. |
|
9 | -- (at your option) any later version. | |
10 | -- |
|
10 | -- | |
11 | -- This program is distributed in the hope that it will be useful, |
|
11 | -- This program is distributed in the hope that it will be useful, | |
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | -- GNU General Public License for more details. |
|
14 | -- GNU General Public License for more details. | |
15 | -- |
|
15 | -- | |
16 | -- You should have received a copy of the GNU General Public License |
|
16 | -- You should have received a copy of the GNU General Public License | |
17 | -- along with this program; if not, write to the Free Software |
|
17 | -- along with this program; if not, write to the Free Software | |
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | ------------------------------------------------------------------------------- |
|
19 | ------------------------------------------------------------------------------- | |
20 | -- Author : Jean-christophe Pellion |
|
20 | -- Author : Jean-christophe Pellion | |
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
22 | -- jean-christophe.pellion@easii-ic.com |
|
22 | -- jean-christophe.pellion@easii-ic.com | |
23 | ------------------------------------------------------------------------------- |
|
23 | ------------------------------------------------------------------------------- | |
24 | -- 1.0 - initial version |
|
24 | -- 1.0 - initial version | |
25 | -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) |
|
25 | -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) | |
26 | ------------------------------------------------------------------------------- |
|
26 | ------------------------------------------------------------------------------- | |
27 | LIBRARY ieee; |
|
27 | LIBRARY ieee; | |
28 | USE ieee.std_logic_1164.ALL; |
|
28 | USE ieee.std_logic_1164.ALL; | |
29 | USE ieee.numeric_std.ALL; |
|
29 | USE ieee.numeric_std.ALL; | |
30 | LIBRARY grlib; |
|
30 | LIBRARY grlib; | |
31 | USE grlib.amba.ALL; |
|
31 | USE grlib.amba.ALL; | |
32 | USE grlib.stdlib.ALL; |
|
32 | USE grlib.stdlib.ALL; | |
33 | USE grlib.devices.ALL; |
|
33 | USE grlib.devices.ALL; | |
34 | USE GRLIB.DMA2AHB_Package.ALL; |
|
34 | USE GRLIB.DMA2AHB_Package.ALL; | |
35 | LIBRARY lpp; |
|
35 | LIBRARY lpp; | |
36 | USE lpp.lpp_amba.ALL; |
|
36 | USE lpp.lpp_amba.ALL; | |
37 | USE lpp.apb_devices_list.ALL; |
|
37 | USE lpp.apb_devices_list.ALL; | |
38 | USE lpp.lpp_memory.ALL; |
|
38 | USE lpp.lpp_memory.ALL; | |
39 | USE lpp.lpp_dma_pkg.ALL; |
|
39 | USE lpp.lpp_dma_pkg.ALL; | |
40 | USE lpp.lpp_waveform_pkg.ALL; |
|
40 | USE lpp.lpp_waveform_pkg.ALL; | |
41 | LIBRARY techmap; |
|
41 | LIBRARY techmap; | |
42 | USE techmap.gencomp.ALL; |
|
42 | USE techmap.gencomp.ALL; | |
43 |
|
43 | |||
44 |
|
44 | |||
45 | ENTITY lpp_debug_dma_singleOrBurst IS |
|
45 | ENTITY lpp_debug_dma_singleOrBurst IS | |
46 | GENERIC ( |
|
46 | GENERIC ( | |
47 | tech : INTEGER := inferred; |
|
47 | tech : INTEGER := inferred; | |
48 | hindex : INTEGER := 2; |
|
48 | hindex : INTEGER := 2; | |
49 | pindex : INTEGER := 4; |
|
49 | pindex : INTEGER := 4; | |
50 | paddr : INTEGER := 4; |
|
50 | paddr : INTEGER := 4; | |
51 | pmask : INTEGER := 16#fff# |
|
51 | pmask : INTEGER := 16#fff# | |
52 | ); |
|
52 | ); | |
53 | PORT ( |
|
53 | PORT ( | |
54 | -- AMBA AHB system signals |
|
54 | -- AMBA AHB system signals | |
55 | HCLK : IN STD_ULOGIC; |
|
55 | HCLK : IN STD_ULOGIC; | |
56 | HRESETn : IN STD_ULOGIC; |
|
56 | HRESETn : IN STD_ULOGIC; | |
57 | -- AMBA AHB Master Interface |
|
57 | -- AMBA AHB Master Interface | |
58 | ahbmi : IN AHB_Mst_In_Type; |
|
58 | ahbmi : IN AHB_Mst_In_Type; | |
59 | ahbmo : OUT AHB_Mst_Out_Type; |
|
59 | ahbmo : OUT AHB_Mst_Out_Type; | |
60 | -- AMBA AHB Master Interface |
|
60 | -- AMBA AHB Master Interface | |
61 | apbi : IN apb_slv_in_type; |
|
61 | apbi : IN apb_slv_in_type; | |
62 | apbo : OUT apb_slv_out_type; |
|
62 | apbo : OUT apb_slv_out_type; | |
63 | -- observation SIGNAL |
|
63 | -- observation SIGNAL | |
64 | out_ren : OUT STD_LOGIC; |
|
64 | out_ren : OUT STD_LOGIC; | |
65 | out_send : OUT STD_LOGIC; |
|
65 | out_send : OUT STD_LOGIC; | |
66 |
out_done : OUT STD_LOGIC |
|
66 | out_done : OUT STD_LOGIC; | |
|
67 | out_dmaout_okay : OUT STD_LOGIC | |||
67 | ); |
|
68 | ); | |
68 | END; |
|
69 | END; | |
69 |
|
70 | |||
70 | ARCHITECTURE Behavioral OF lpp_debug_dma_singleOrBurst IS |
|
71 | ARCHITECTURE Behavioral OF lpp_debug_dma_singleOrBurst IS | |
71 | SIGNAL run : STD_LOGIC; |
|
72 | SIGNAL run : STD_LOGIC; | |
72 | SIGNAL send : STD_LOGIC; |
|
73 | SIGNAL send : STD_LOGIC; | |
73 | SIGNAL valid_burst : STD_LOGIC; |
|
74 | SIGNAL valid_burst : STD_LOGIC; | |
74 | SIGNAL done : STD_LOGIC; |
|
75 | SIGNAL done : STD_LOGIC; | |
75 | SIGNAL ren : STD_LOGIC; |
|
76 | SIGNAL ren : STD_LOGIC; | |
76 | SIGNAL address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
77 | SIGNAL address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
77 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
78 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
78 | -- |
|
79 | -- | |
79 |
|
80 | |||
80 | CONSTANT REVISION : INTEGER := 1; |
|
81 | CONSTANT REVISION : INTEGER := 1; | |
81 |
|
82 | |||
82 | CONSTANT pconfig : apb_config_type := ( |
|
83 | CONSTANT pconfig : apb_config_type := ( | |
83 | 0 => ahb_device_reg (VENDOR_LPP, LPP_DEBUG_DMA, 2, REVISION, 0), |
|
84 | 0 => ahb_device_reg (VENDOR_LPP, LPP_DEBUG_DMA, 2, REVISION, 0), | |
84 | 1 => apb_iobar(paddr, pmask)); |
|
85 | 1 => apb_iobar(paddr, pmask)); | |
85 |
|
86 | |||
86 | TYPE lpp_debug_dma_regs IS RECORD |
|
87 | TYPE lpp_debug_dma_regs IS RECORD | |
87 | run : STD_LOGIC; |
|
88 | run : STD_LOGIC; | |
88 | send : STD_LOGIC; |
|
89 | send : STD_LOGIC; | |
89 | valid_burst : STD_LOGIC; |
|
90 | valid_burst : STD_LOGIC; | |
90 | done : STD_LOGIC; |
|
91 | done : STD_LOGIC; | |
91 | ren : STD_LOGIC; |
|
92 | ren : STD_LOGIC; | |
92 | addr : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
93 | addr : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
93 | data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
94 | data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
94 | nb_ren : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
95 | nb_ren : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
95 | END RECORD; |
|
96 | END RECORD; | |
96 | SIGNAL reg : lpp_debug_dma_regs; |
|
97 | SIGNAL reg : lpp_debug_dma_regs; | |
97 |
|
98 | |||
98 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
99 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
99 |
|
100 | |||
100 | BEGIN |
|
101 | BEGIN | |
101 | out_ren <= ren; |
|
102 | out_ren <= ren; | |
102 | out_send <= send; |
|
103 | out_send <= send; | |
103 | out_done <= done; |
|
104 | out_done <= done; | |
104 |
|
105 | |||
105 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst |
|
106 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst | |
106 | GENERIC MAP ( |
|
107 | GENERIC MAP ( | |
107 | tech => tech, |
|
108 | tech => tech, | |
108 | hindex => hindex) |
|
109 | hindex => hindex) | |
109 | PORT MAP ( |
|
110 | PORT MAP ( | |
110 | HCLK => HCLK, |
|
111 | HCLK => HCLK, | |
111 | HRESETn => HRESETn, |
|
112 | HRESETn => HRESETn, | |
112 | run => run, -- |
|
113 | run => run, -- | |
113 | AHB_Master_In => ahbmi, |
|
114 | AHB_Master_In => ahbmi, | |
114 | AHB_Master_Out => ahbmo, |
|
115 | AHB_Master_Out => ahbmo, | |
115 | send => send, -- |
|
116 | send => send, -- | |
116 | valid_burst => valid_burst, -- |
|
117 | valid_burst => valid_burst, -- | |
117 | done => done, -- out |
|
118 | done => done, -- out | |
118 | ren => ren, -- out |
|
119 | ren => ren, -- out | |
119 | address => address, |
|
120 | address => address, | |
120 |
data => data |
|
121 | data => data, | |
|
122 | debug_dmaout_okay => out_dmaout_okay); | |||
121 |
|
123 | |||
122 |
|
124 | |||
123 | run <= reg.run; |
|
125 | run <= reg.run; | |
124 | valid_burst <= reg.valid_burst; |
|
126 | valid_burst <= reg.valid_burst; | |
125 | send <= reg.send; |
|
127 | send <= reg.send; | |
126 | address <= reg.addr; |
|
128 | address <= reg.addr; | |
127 | data <= reg.data; |
|
129 | data <= reg.data; | |
128 |
|
130 | |||
129 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) |
|
131 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) | |
130 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); |
|
132 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); | |
131 | BEGIN -- PROCESS lpp_dma_top |
|
133 | BEGIN -- PROCESS lpp_dma_top | |
132 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
134 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
133 | reg.run <= '0'; |
|
135 | reg.run <= '0'; | |
134 | reg.send <= '0'; |
|
136 | reg.send <= '0'; | |
135 | reg.valid_burst <= '0'; |
|
137 | reg.valid_burst <= '0'; | |
136 | reg.done <= '0'; |
|
138 | reg.done <= '0'; | |
137 | reg.ren <= '0'; |
|
139 | reg.ren <= '0'; | |
138 | reg.addr <= (OTHERS => '0'); |
|
140 | reg.addr <= (OTHERS => '0'); | |
139 | reg.data <= (OTHERS => '0'); |
|
141 | reg.data <= (OTHERS => '0'); | |
140 | reg.nb_ren <= (OTHERS => '0'); |
|
142 | reg.nb_ren <= (OTHERS => '0'); | |
141 |
|
143 | |||
142 | apbo.pirq <= (OTHERS => '0'); |
|
144 | apbo.pirq <= (OTHERS => '0'); | |
143 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
145 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
144 | paddr := "000000"; |
|
146 | paddr := "000000"; | |
145 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); |
|
147 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); | |
146 | prdata <= (OTHERS => '0'); |
|
148 | prdata <= (OTHERS => '0'); | |
147 | ------------------------------------ |
|
149 | ------------------------------------ | |
148 | reg.send <= '0'; |
|
150 | reg.send <= '0'; | |
149 | IF done = '1' THEN |
|
151 | IF done = '1' THEN | |
150 | reg.done <= '1'; |
|
152 | reg.done <= '1'; | |
151 | END IF; |
|
153 | END IF; | |
152 | IF ren = '0' THEN |
|
154 | IF ren = '0' THEN | |
153 | reg.ren <= '1'; |
|
155 | reg.ren <= '1'; | |
154 | reg.nb_ren <= STD_LOGIC_VECTOR(UNSIGNED(reg.nb_ren) + 1); |
|
156 | reg.nb_ren <= STD_LOGIC_VECTOR(UNSIGNED(reg.nb_ren) + 1); | |
155 | END IF; |
|
157 | END IF; | |
156 | ------------------------------------ |
|
158 | ------------------------------------ | |
157 |
|
159 | |||
158 | IF apbi.psel(pindex) = '1' THEN |
|
160 | IF apbi.psel(pindex) = '1' THEN | |
159 | -- APB DMA READ -- |
|
161 | -- APB DMA READ -- | |
160 | CASE paddr(7 DOWNTO 2) IS |
|
162 | CASE paddr(7 DOWNTO 2) IS | |
161 | -- |
|
163 | -- | |
162 | WHEN "000000" => prdata(0) <= reg.run; |
|
164 | WHEN "000000" => prdata(0) <= reg.run; | |
163 | prdata(1) <= reg.send; |
|
165 | prdata(1) <= reg.send; | |
164 | prdata(2) <= reg.valid_burst; |
|
166 | prdata(2) <= reg.valid_burst; | |
165 | prdata(3) <= reg.done; |
|
167 | prdata(3) <= reg.done; | |
166 | prdata(4) <= reg.ren; |
|
168 | prdata(4) <= reg.ren; | |
167 | WHEN "000001" => prdata <= reg.addr; |
|
169 | WHEN "000001" => prdata <= reg.addr; | |
168 | WHEN "000010" => prdata <= reg.data; |
|
170 | WHEN "000010" => prdata <= reg.data; | |
169 | WHEN "000011" => prdata <= reg.nb_ren; |
|
171 | WHEN "000011" => prdata <= reg.nb_ren; | |
170 |
|
172 | |||
171 | WHEN OTHERS => NULL; |
|
173 | WHEN OTHERS => NULL; | |
172 | END CASE; |
|
174 | END CASE; | |
173 | IF (apbi.pwrite AND apbi.penable) = '1' THEN |
|
175 | IF (apbi.pwrite AND apbi.penable) = '1' THEN | |
174 | -- APB DMA WRITE -- |
|
176 | -- APB DMA WRITE -- | |
175 | CASE paddr(7 DOWNTO 2) IS |
|
177 | CASE paddr(7 DOWNTO 2) IS | |
176 | -- |
|
178 | -- | |
177 | WHEN "000000" => reg.run <= apbi.pwdata(0); |
|
179 | WHEN "000000" => reg.run <= apbi.pwdata(0); | |
178 | reg.send <= apbi.pwdata(1); |
|
180 | reg.send <= apbi.pwdata(1); | |
179 | reg.valid_burst <= apbi.pwdata(2); |
|
181 | reg.valid_burst <= apbi.pwdata(2); | |
180 | reg.done <= apbi.pwdata(3); |
|
182 | reg.done <= apbi.pwdata(3); | |
181 | reg.ren <= apbi.pwdata(4); |
|
183 | reg.ren <= apbi.pwdata(4); | |
182 | WHEN "000001" => reg.addr <= apbi.pwdata; |
|
184 | WHEN "000001" => reg.addr <= apbi.pwdata; | |
183 | WHEN "000010" => reg.data <= apbi.pwdata; |
|
185 | WHEN "000010" => reg.data <= apbi.pwdata; | |
184 | --WHEN "000011" => reg.nb_ren <= apbi.pwdata; |
|
186 | --WHEN "000011" => reg.nb_ren <= apbi.pwdata; | |
185 | WHEN OTHERS => NULL; |
|
187 | WHEN OTHERS => NULL; | |
186 | END CASE; |
|
188 | END CASE; | |
187 | END IF; |
|
189 | END IF; | |
188 | END IF; |
|
190 | END IF; | |
189 |
|
191 | |||
190 | END IF; |
|
192 | END IF; | |
191 | END PROCESS lpp_lfr_apbreg; |
|
193 | END PROCESS lpp_lfr_apbreg; | |
192 |
|
194 | |||
193 | apbo.pindex <= pindex; |
|
195 | apbo.pindex <= pindex; | |
194 | apbo.pconfig <= pconfig; |
|
196 | apbo.pconfig <= pconfig; | |
195 | apbo.prdata <= prdata; |
|
197 | apbo.prdata <= prdata; | |
196 |
|
198 | |||
197 |
|
199 | |||
198 |
|
200 | |||
199 | END Behavioral; |
|
201 | END Behavioral; |
@@ -1,49 +1,51 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | -- jean-christophe.pellion@easii-ic.com |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
22 | ---------------------------------------------------------------------------- |
|
22 | ---------------------------------------------------------------------------- | |
23 | LIBRARY ieee; |
|
23 | LIBRARY ieee; | |
24 | USE ieee.std_logic_1164.ALL; |
|
24 | USE ieee.std_logic_1164.ALL; | |
25 | LIBRARY grlib; |
|
25 | LIBRARY grlib; | |
26 | USE grlib.amba.ALL; |
|
26 | USE grlib.amba.ALL; | |
27 |
|
27 | |||
28 | PACKAGE lpp_debug_lfr_pkg IS |
|
28 | PACKAGE lpp_debug_lfr_pkg IS | |
29 |
|
29 | |||
30 | COMPONENT lpp_debug_dma_singleOrBurst |
|
30 | COMPONENT lpp_debug_dma_singleOrBurst | |
31 | GENERIC ( |
|
31 | GENERIC ( | |
32 | tech : INTEGER; |
|
32 | tech : INTEGER; | |
33 | hindex : INTEGER; |
|
33 | hindex : INTEGER; | |
34 | pindex : INTEGER; |
|
34 | pindex : INTEGER; | |
35 | paddr : INTEGER; |
|
35 | paddr : INTEGER; | |
36 | pmask : INTEGER); |
|
36 | pmask : INTEGER); | |
37 | PORT ( |
|
37 | PORT ( | |
38 | HCLK : IN STD_ULOGIC; |
|
38 | HCLK : IN STD_ULOGIC; | |
39 | HRESETn : IN STD_ULOGIC; |
|
39 | HRESETn : IN STD_ULOGIC; | |
40 | ahbmi : IN AHB_Mst_In_Type; |
|
40 | ahbmi : IN AHB_Mst_In_Type; | |
41 | ahbmo : OUT AHB_Mst_Out_Type; |
|
41 | ahbmo : OUT AHB_Mst_Out_Type; | |
42 | apbi : IN apb_slv_in_type; |
|
42 | apbi : IN apb_slv_in_type; | |
43 | apbo : OUT apb_slv_out_type; |
|
43 | apbo : OUT apb_slv_out_type; | |
44 | out_ren : OUT STD_LOGIC; |
|
44 | out_ren : OUT STD_LOGIC; | |
45 | out_send : OUT STD_LOGIC; |
|
45 | out_send : OUT STD_LOGIC; | |
46 |
out_done : OUT STD_LOGIC |
|
46 | out_done : OUT STD_LOGIC; | |
|
47 | out_dmaout_okay : OUT STD_LOGIC | |||
|
48 | ); | |||
47 | END COMPONENT; |
|
49 | END COMPONENT; | |
48 |
|
50 | |||
49 | END; |
|
51 | END; |
@@ -1,219 +1,220 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | -- jean-christophe.pellion@easii-ic.com |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
22 | ---------------------------------------------------------------------------- |
|
22 | ---------------------------------------------------------------------------- | |
23 | LIBRARY ieee; |
|
23 | LIBRARY ieee; | |
24 | USE ieee.std_logic_1164.ALL; |
|
24 | USE ieee.std_logic_1164.ALL; | |
25 | LIBRARY grlib; |
|
25 | LIBRARY grlib; | |
26 | USE grlib.amba.ALL; |
|
26 | USE grlib.amba.ALL; | |
27 | USE std.textio.ALL; |
|
27 | USE std.textio.ALL; | |
28 | LIBRARY grlib; |
|
28 | LIBRARY grlib; | |
29 | USE grlib.amba.ALL; |
|
29 | USE grlib.amba.ALL; | |
30 | USE grlib.stdlib.ALL; |
|
30 | USE grlib.stdlib.ALL; | |
31 | USE GRLIB.DMA2AHB_Package.ALL; |
|
31 | USE GRLIB.DMA2AHB_Package.ALL; | |
32 | LIBRARY techmap; |
|
32 | LIBRARY techmap; | |
33 | USE techmap.gencomp.ALL; |
|
33 | USE techmap.gencomp.ALL; | |
34 | LIBRARY lpp; |
|
34 | LIBRARY lpp; | |
35 | USE lpp.lpp_amba.ALL; |
|
35 | USE lpp.lpp_amba.ALL; | |
36 | USE lpp.apb_devices_list.ALL; |
|
36 | USE lpp.apb_devices_list.ALL; | |
37 | USE lpp.lpp_memory.ALL; |
|
37 | USE lpp.lpp_memory.ALL; | |
38 |
|
38 | |||
39 | PACKAGE lpp_dma_pkg IS |
|
39 | PACKAGE lpp_dma_pkg IS | |
40 |
|
40 | |||
41 | COMPONENT lpp_dma |
|
41 | COMPONENT lpp_dma | |
42 | GENERIC ( |
|
42 | GENERIC ( | |
43 | tech : INTEGER; |
|
43 | tech : INTEGER; | |
44 | hindex : INTEGER; |
|
44 | hindex : INTEGER; | |
45 | pindex : INTEGER; |
|
45 | pindex : INTEGER; | |
46 | paddr : INTEGER; |
|
46 | paddr : INTEGER; | |
47 | pmask : INTEGER; |
|
47 | pmask : INTEGER; | |
48 | pirq : INTEGER); |
|
48 | pirq : INTEGER); | |
49 | PORT ( |
|
49 | PORT ( | |
50 | HCLK : IN STD_ULOGIC; |
|
50 | HCLK : IN STD_ULOGIC; | |
51 | HRESETn : IN STD_ULOGIC; |
|
51 | HRESETn : IN STD_ULOGIC; | |
52 | apbi : IN apb_slv_in_type; |
|
52 | apbi : IN apb_slv_in_type; | |
53 | apbo : OUT apb_slv_out_type; |
|
53 | apbo : OUT apb_slv_out_type; | |
54 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
54 | AHB_Master_In : IN AHB_Mst_In_Type; | |
55 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
55 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
56 | -- fifo interface |
|
56 | -- fifo interface | |
57 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
57 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
58 | fifo_empty : IN STD_LOGIC; |
|
58 | fifo_empty : IN STD_LOGIC; | |
59 | fifo_ren : OUT STD_LOGIC; |
|
59 | fifo_ren : OUT STD_LOGIC; | |
60 | -- header |
|
60 | -- header | |
61 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
61 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
62 | header_val : IN STD_LOGIC; |
|
62 | header_val : IN STD_LOGIC; | |
63 | header_ack : OUT STD_LOGIC); |
|
63 | header_ack : OUT STD_LOGIC); | |
64 | END COMPONENT; |
|
64 | END COMPONENT; | |
65 |
|
65 | |||
66 | COMPONENT fifo_test_dma |
|
66 | COMPONENT fifo_test_dma | |
67 | GENERIC ( |
|
67 | GENERIC ( | |
68 | tech : INTEGER; |
|
68 | tech : INTEGER; | |
69 | pindex : INTEGER; |
|
69 | pindex : INTEGER; | |
70 | paddr : INTEGER; |
|
70 | paddr : INTEGER; | |
71 | pmask : INTEGER); |
|
71 | pmask : INTEGER); | |
72 | PORT ( |
|
72 | PORT ( | |
73 | HCLK : IN STD_ULOGIC; |
|
73 | HCLK : IN STD_ULOGIC; | |
74 | HRESETn : IN STD_ULOGIC; |
|
74 | HRESETn : IN STD_ULOGIC; | |
75 | apbi : IN apb_slv_in_type; |
|
75 | apbi : IN apb_slv_in_type; | |
76 | apbo : OUT apb_slv_out_type; |
|
76 | apbo : OUT apb_slv_out_type; | |
77 | -- fifo interface |
|
77 | -- fifo interface | |
78 | fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
78 | fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
79 | fifo_empty : OUT STD_LOGIC; |
|
79 | fifo_empty : OUT STD_LOGIC; | |
80 | fifo_ren : IN STD_LOGIC; |
|
80 | fifo_ren : IN STD_LOGIC; | |
81 | -- header |
|
81 | -- header | |
82 | header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
82 | header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
83 | header_val : OUT STD_LOGIC; |
|
83 | header_val : OUT STD_LOGIC; | |
84 | header_ack : IN STD_LOGIC |
|
84 | header_ack : IN STD_LOGIC | |
85 | ); |
|
85 | ); | |
86 | END COMPONENT; |
|
86 | END COMPONENT; | |
87 |
|
87 | |||
88 | COMPONENT lpp_dma_apbreg |
|
88 | COMPONENT lpp_dma_apbreg | |
89 | GENERIC ( |
|
89 | GENERIC ( | |
90 | pindex : INTEGER; |
|
90 | pindex : INTEGER; | |
91 | paddr : INTEGER; |
|
91 | paddr : INTEGER; | |
92 | pmask : INTEGER; |
|
92 | pmask : INTEGER; | |
93 | pirq : INTEGER); |
|
93 | pirq : INTEGER); | |
94 | PORT ( |
|
94 | PORT ( | |
95 | HCLK : IN STD_ULOGIC; |
|
95 | HCLK : IN STD_ULOGIC; | |
96 | HRESETn : IN STD_ULOGIC; |
|
96 | HRESETn : IN STD_ULOGIC; | |
97 | apbi : IN apb_slv_in_type; |
|
97 | apbi : IN apb_slv_in_type; | |
98 | apbo : OUT apb_slv_out_type; |
|
98 | apbo : OUT apb_slv_out_type; | |
99 | -- IN |
|
99 | -- IN | |
100 | ready_matrix_f0_0 : IN STD_LOGIC; |
|
100 | ready_matrix_f0_0 : IN STD_LOGIC; | |
101 | ready_matrix_f0_1 : IN STD_LOGIC; |
|
101 | ready_matrix_f0_1 : IN STD_LOGIC; | |
102 | ready_matrix_f1 : IN STD_LOGIC; |
|
102 | ready_matrix_f1 : IN STD_LOGIC; | |
103 | ready_matrix_f2 : IN STD_LOGIC; |
|
103 | ready_matrix_f2 : IN STD_LOGIC; | |
104 | error_anticipating_empty_fifo : IN STD_LOGIC; |
|
104 | error_anticipating_empty_fifo : IN STD_LOGIC; | |
105 | error_bad_component_error : IN STD_LOGIC; |
|
105 | error_bad_component_error : IN STD_LOGIC; | |
106 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
106 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
107 |
|
107 | |||
108 | -- OUT |
|
108 | -- OUT | |
109 | status_ready_matrix_f0_0 : OUT STD_LOGIC; |
|
109 | status_ready_matrix_f0_0 : OUT STD_LOGIC; | |
110 | status_ready_matrix_f0_1 : OUT STD_LOGIC; |
|
110 | status_ready_matrix_f0_1 : OUT STD_LOGIC; | |
111 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
111 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
112 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
112 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
113 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
113 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; | |
114 | status_error_bad_component_error : OUT STD_LOGIC; |
|
114 | status_error_bad_component_error : OUT STD_LOGIC; | |
115 |
|
115 | |||
116 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
116 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
117 | config_active_interruption_onError : OUT STD_LOGIC; |
|
117 | config_active_interruption_onError : OUT STD_LOGIC; | |
118 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
118 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
119 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
119 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
120 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
120 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
121 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
121 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
122 | ); |
|
122 | ); | |
123 | END COMPONENT; |
|
123 | END COMPONENT; | |
124 |
|
124 | |||
125 | COMPONENT lpp_dma_send_1word |
|
125 | COMPONENT lpp_dma_send_1word | |
126 | PORT ( |
|
126 | PORT ( | |
127 | HCLK : IN STD_ULOGIC; |
|
127 | HCLK : IN STD_ULOGIC; | |
128 | HRESETn : IN STD_ULOGIC; |
|
128 | HRESETn : IN STD_ULOGIC; | |
129 | DMAIn : OUT DMA_In_Type; |
|
129 | DMAIn : OUT DMA_In_Type; | |
130 | DMAOut : IN DMA_OUt_Type; |
|
130 | DMAOut : IN DMA_OUt_Type; | |
131 | send : IN STD_LOGIC; |
|
131 | send : IN STD_LOGIC; | |
132 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
132 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
133 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
133 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
134 | ren : OUT STD_LOGIC; |
|
134 | ren : OUT STD_LOGIC; | |
135 | send_ok : OUT STD_LOGIC; |
|
135 | send_ok : OUT STD_LOGIC; | |
136 | send_ko : OUT STD_LOGIC); |
|
136 | send_ko : OUT STD_LOGIC); | |
137 | END COMPONENT; |
|
137 | END COMPONENT; | |
138 |
|
138 | |||
139 | COMPONENT lpp_dma_send_16word |
|
139 | COMPONENT lpp_dma_send_16word | |
140 | PORT ( |
|
140 | PORT ( | |
141 | HCLK : IN STD_ULOGIC; |
|
141 | HCLK : IN STD_ULOGIC; | |
142 | HRESETn : IN STD_ULOGIC; |
|
142 | HRESETn : IN STD_ULOGIC; | |
143 | DMAIn : OUT DMA_In_Type; |
|
143 | DMAIn : OUT DMA_In_Type; | |
144 | DMAOut : IN DMA_OUt_Type; |
|
144 | DMAOut : IN DMA_OUt_Type; | |
145 | send : IN STD_LOGIC; |
|
145 | send : IN STD_LOGIC; | |
146 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
146 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
147 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
147 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
148 | ren : OUT STD_LOGIC; |
|
148 | ren : OUT STD_LOGIC; | |
149 | send_ok : OUT STD_LOGIC; |
|
149 | send_ok : OUT STD_LOGIC; | |
150 | send_ko : OUT STD_LOGIC); |
|
150 | send_ko : OUT STD_LOGIC); | |
151 | END COMPONENT; |
|
151 | END COMPONENT; | |
152 |
|
152 | |||
153 | COMPONENT fifo_latency_correction |
|
153 | COMPONENT fifo_latency_correction | |
154 | PORT ( |
|
154 | PORT ( | |
155 | HCLK : IN STD_ULOGIC; |
|
155 | HCLK : IN STD_ULOGIC; | |
156 | HRESETn : IN STD_ULOGIC; |
|
156 | HRESETn : IN STD_ULOGIC; | |
157 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
157 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
158 | fifo_empty : IN STD_LOGIC; |
|
158 | fifo_empty : IN STD_LOGIC; | |
159 | fifo_ren : OUT STD_LOGIC; |
|
159 | fifo_ren : OUT STD_LOGIC; | |
160 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
160 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
161 | dma_empty : OUT STD_LOGIC; |
|
161 | dma_empty : OUT STD_LOGIC; | |
162 | dma_ren : IN STD_LOGIC); |
|
162 | dma_ren : IN STD_LOGIC); | |
163 | END COMPONENT; |
|
163 | END COMPONENT; | |
164 |
|
164 | |||
165 | COMPONENT lpp_dma_ip |
|
165 | COMPONENT lpp_dma_ip | |
166 | GENERIC ( |
|
166 | GENERIC ( | |
167 | tech : INTEGER; |
|
167 | tech : INTEGER; | |
168 | hindex : INTEGER); |
|
168 | hindex : INTEGER); | |
169 | PORT ( |
|
169 | PORT ( | |
170 | HCLK : IN STD_ULOGIC; |
|
170 | HCLK : IN STD_ULOGIC; | |
171 | HRESETn : IN STD_ULOGIC; |
|
171 | HRESETn : IN STD_ULOGIC; | |
172 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
172 | AHB_Master_In : IN AHB_Mst_In_Type; | |
173 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
173 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
174 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
174 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
175 | fifo_empty : IN STD_LOGIC; |
|
175 | fifo_empty : IN STD_LOGIC; | |
176 | fifo_ren : OUT STD_LOGIC; |
|
176 | fifo_ren : OUT STD_LOGIC; | |
177 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
177 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
178 | header_val : IN STD_LOGIC; |
|
178 | header_val : IN STD_LOGIC; | |
179 | header_ack : OUT STD_LOGIC; |
|
179 | header_ack : OUT STD_LOGIC; | |
180 | ready_matrix_f0_0 : OUT STD_LOGIC; |
|
180 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
181 | ready_matrix_f0_1 : OUT STD_LOGIC; |
|
181 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
182 | ready_matrix_f1 : OUT STD_LOGIC; |
|
182 | ready_matrix_f1 : OUT STD_LOGIC; | |
183 | ready_matrix_f2 : OUT STD_LOGIC; |
|
183 | ready_matrix_f2 : OUT STD_LOGIC; | |
184 | error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
184 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
185 | error_bad_component_error : OUT STD_LOGIC; |
|
185 | error_bad_component_error : OUT STD_LOGIC; | |
186 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
186 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
187 | status_ready_matrix_f0_0 : IN STD_LOGIC; |
|
187 | status_ready_matrix_f0_0 : IN STD_LOGIC; | |
188 | status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
188 | status_ready_matrix_f0_1 : IN STD_LOGIC; | |
189 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
189 | status_ready_matrix_f1 : IN STD_LOGIC; | |
190 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
190 | status_ready_matrix_f2 : IN STD_LOGIC; | |
191 | status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
191 | status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
192 | status_error_bad_component_error : IN STD_LOGIC; |
|
192 | status_error_bad_component_error : IN STD_LOGIC; | |
193 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
193 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
194 | config_active_interruption_onError : IN STD_LOGIC; |
|
194 | config_active_interruption_onError : IN STD_LOGIC; | |
195 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
195 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
196 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
196 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
197 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
197 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
198 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
198 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
199 | END COMPONENT; |
|
199 | END COMPONENT; | |
200 |
|
200 | |||
201 | COMPONENT lpp_dma_singleOrBurst |
|
201 | COMPONENT lpp_dma_singleOrBurst | |
202 | GENERIC ( |
|
202 | GENERIC ( | |
203 | tech : INTEGER; |
|
203 | tech : INTEGER; | |
204 | hindex : INTEGER); |
|
204 | hindex : INTEGER); | |
205 | PORT ( |
|
205 | PORT ( | |
206 | HCLK : IN STD_ULOGIC; |
|
206 | HCLK : IN STD_ULOGIC; | |
207 | HRESETn : IN STD_ULOGIC; |
|
207 | HRESETn : IN STD_ULOGIC; | |
208 | run : IN STD_LOGIC; |
|
208 | run : IN STD_LOGIC; | |
209 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
209 | AHB_Master_In : IN AHB_Mst_In_Type; | |
210 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
210 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
211 | send : IN STD_LOGIC; |
|
211 | send : IN STD_LOGIC; | |
212 | valid_burst : IN STD_LOGIC; |
|
212 | valid_burst : IN STD_LOGIC; | |
213 | done : OUT STD_LOGIC; |
|
213 | done : OUT STD_LOGIC; | |
214 | ren : OUT STD_LOGIC; |
|
214 | ren : OUT STD_LOGIC; | |
215 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
215 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
216 |
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
216 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
217 | debug_dmaout_okay : OUT STD_LOGIC); | |||
217 | END COMPONENT; |
|
218 | END COMPONENT; | |
218 |
|
219 | |||
219 | END; |
|
220 | END; |
@@ -1,183 +1,190 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | -- jean-christophe.pellion@easii-ic.com |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
22 | ---------------------------------------------------------------------------- |
|
22 | ---------------------------------------------------------------------------- | |
23 |
|
23 | |||
24 | LIBRARY ieee; |
|
24 | LIBRARY ieee; | |
25 | USE ieee.std_logic_1164.ALL; |
|
25 | USE ieee.std_logic_1164.ALL; | |
26 | USE ieee.numeric_std.ALL; |
|
26 | USE ieee.numeric_std.ALL; | |
27 | LIBRARY grlib; |
|
27 | LIBRARY grlib; | |
28 | USE grlib.amba.ALL; |
|
28 | USE grlib.amba.ALL; | |
29 | USE grlib.stdlib.ALL; |
|
29 | USE grlib.stdlib.ALL; | |
30 | USE grlib.devices.ALL; |
|
30 | USE grlib.devices.ALL; | |
31 | USE GRLIB.DMA2AHB_Package.ALL; |
|
31 | USE GRLIB.DMA2AHB_Package.ALL; | |
32 | LIBRARY lpp; |
|
32 | LIBRARY lpp; | |
33 | USE lpp.lpp_amba.ALL; |
|
33 | USE lpp.lpp_amba.ALL; | |
34 | USE lpp.apb_devices_list.ALL; |
|
34 | USE lpp.apb_devices_list.ALL; | |
35 | USE lpp.lpp_memory.ALL; |
|
35 | USE lpp.lpp_memory.ALL; | |
36 | LIBRARY techmap; |
|
36 | LIBRARY techmap; | |
37 | USE techmap.gencomp.ALL; |
|
37 | USE techmap.gencomp.ALL; | |
38 |
|
38 | |||
39 | ENTITY lpp_dma_send_16word IS |
|
39 | ENTITY lpp_dma_send_16word IS | |
40 | PORT ( |
|
40 | PORT ( | |
41 | -- AMBA AHB system signals |
|
41 | -- AMBA AHB system signals | |
42 | HCLK : IN STD_ULOGIC; |
|
42 | HCLK : IN STD_ULOGIC; | |
43 | HRESETn : IN STD_ULOGIC; |
|
43 | HRESETn : IN STD_ULOGIC; | |
44 |
|
44 | |||
45 | -- DMA |
|
45 | -- DMA | |
46 | DMAIn : OUT DMA_In_Type; |
|
46 | DMAIn : OUT DMA_In_Type; | |
47 | DMAOut : IN DMA_OUt_Type; |
|
47 | DMAOut : IN DMA_OUt_Type; | |
48 |
|
48 | |||
49 | -- |
|
49 | -- | |
50 | send : IN STD_LOGIC; |
|
50 | send : IN STD_LOGIC; | |
51 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
51 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
52 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
52 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
53 | ren : OUT STD_LOGIC; |
|
53 | ren : OUT STD_LOGIC; | |
54 | -- |
|
54 | -- | |
55 | send_ok : OUT STD_LOGIC; |
|
55 | send_ok : OUT STD_LOGIC; | |
56 | send_ko : OUT STD_LOGIC |
|
56 | send_ko : OUT STD_LOGIC | |
|
57 | ||||
57 |
|
|
58 | ); | |
58 | END lpp_dma_send_16word; |
|
59 | END lpp_dma_send_16word; | |
59 |
|
60 | |||
60 | ARCHITECTURE beh OF lpp_dma_send_16word IS |
|
61 | ARCHITECTURE beh OF lpp_dma_send_16word IS | |
61 |
|
62 | |||
62 | TYPE state_fsm_send_16word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1, WAIT_LAST_READY); |
|
63 | TYPE state_fsm_send_16word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1, WAIT_LAST_READY); | |
63 | SIGNAL state : state_fsm_send_16word; |
|
64 | SIGNAL state : state_fsm_send_16word; | |
64 |
|
65 | |||
65 | SIGNAL data_counter : INTEGER; |
|
66 | SIGNAL data_counter : INTEGER; | |
66 | SIGNAL grant_counter : INTEGER; |
|
67 | SIGNAL grant_counter : INTEGER; | |
67 |
|
68 | |||
68 | BEGIN -- beh |
|
69 | BEGIN -- beh | |
69 |
|
70 | |||
70 | DMAIn.Beat <= HINCR16; |
|
71 | DMAIn.Beat <= HINCR16; | |
71 | DMAIn.Size <= HSIZE32; |
|
72 | DMAIn.Size <= HSIZE32; | |
72 |
|
73 | |||
73 | PROCESS (HCLK, HRESETn) |
|
74 | PROCESS (HCLK, HRESETn) | |
74 | BEGIN -- PROCESS |
|
75 | BEGIN -- PROCESS | |
75 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
76 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
76 | state <= IDLE; |
|
77 | state <= IDLE; | |
77 | send_ok <= '0'; |
|
78 | send_ok <= '0'; | |
78 | send_ko <= '0'; |
|
79 | send_ko <= '0'; | |
79 |
|
80 | |||
80 | DMAIn.Reset <= '1'; |
|
81 | DMAIn.Reset <= '1'; | |
81 | DMAIn.Address <= (OTHERS => '0'); |
|
82 | DMAIn.Address <= (OTHERS => '0'); | |
82 | DMAIn.Request <= '0'; |
|
83 | DMAIn.Request <= '0'; | |
83 | DMAIn.Store <= '0'; |
|
84 | DMAIn.Store <= '0'; | |
84 | DMAIn.Burst <= '1'; |
|
85 | DMAIn.Burst <= '1'; | |
85 | DMAIn.Lock <= '0'; |
|
86 | DMAIn.Lock <= '0'; | |
86 | data_counter <= 0; |
|
87 | data_counter <= 0; | |
87 | grant_counter <= 0; |
|
88 | grant_counter <= 0; | |
88 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
89 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
89 |
|
90 | |||
90 | DMAIn.Reset <= '0'; |
|
91 | DMAIn.Reset <= '0'; | |
91 |
|
92 | |||
92 | CASE state IS |
|
93 | CASE state IS | |
93 | WHEN IDLE => |
|
94 | WHEN IDLE => | |
94 | DMAIn.Store <= '1'; |
|
95 | DMAIn.Store <= '1'; | |
95 | DMAIn.Request <= '0'; |
|
96 | DMAIn.Request <= '0'; | |
96 | send_ok <= '0'; |
|
97 | send_ok <= '0'; | |
97 | send_ko <= '0'; |
|
98 | send_ko <= '0'; | |
98 | DMAIn.Address <= address; |
|
99 | DMAIn.Address <= address; | |
99 | data_counter <= 0; |
|
100 | data_counter <= 0; | |
100 | DMAIn.Lock <= '0'; -- FIX test |
|
101 | DMAIn.Lock <= '0'; -- FIX test | |
101 | IF send = '1' THEN |
|
102 | IF send = '1' THEN | |
102 | state <= REQUEST_BUS; |
|
103 | state <= REQUEST_BUS; | |
103 | DMAIn.Request <= '1'; |
|
104 | DMAIn.Request <= '1'; | |
104 | DMAIn.Lock <= '1'; -- FIX test |
|
105 | DMAIn.Lock <= '1'; -- FIX test | |
105 | DMAIn.Store <= '1'; |
|
106 | DMAIn.Store <= '1'; | |
106 | END IF; |
|
107 | END IF; | |
107 | WHEN REQUEST_BUS => |
|
108 | WHEN REQUEST_BUS => | |
108 | IF DMAOut.Grant = '1' THEN |
|
109 | IF DMAOut.Grant = '1' THEN | |
109 | data_counter <= 1; |
|
110 | data_counter <= 1; | |
110 | grant_counter <= 1; |
|
111 | grant_counter <= 1; | |
111 | state <= SEND_DATA; |
|
112 | state <= SEND_DATA; | |
112 | END IF; |
|
113 | END IF; | |
113 | WHEN SEND_DATA => |
|
114 | WHEN SEND_DATA => | |
114 |
|
115 | |||
115 | IF DMAOut.Fault = '1' THEN |
|
116 | IF DMAOut.Fault = '1' THEN | |
116 | DMAIn.Reset <= '0'; |
|
117 | DMAIn.Reset <= '0'; | |
117 | DMAIn.Address <= (OTHERS => '0'); |
|
118 | DMAIn.Address <= (OTHERS => '0'); | |
118 | DMAIn.Request <= '0'; |
|
119 | DMAIn.Request <= '0'; | |
119 | DMAIn.Store <= '0'; |
|
120 | DMAIn.Store <= '0'; | |
120 | DMAIn.Burst <= '0'; |
|
121 | DMAIn.Burst <= '0'; | |
121 | state <= ERROR0; |
|
122 | state <= ERROR0; | |
122 | ELSE |
|
123 | ELSE | |
123 |
|
124 | |||
124 | IF DMAOut.Grant = '1' THEN |
|
125 | IF DMAOut.Grant = '1' THEN | |
125 | IF grant_counter = 15 THEN |
|
126 | IF grant_counter = 15 THEN | |
126 | DMAIn.Reset <= '0'; |
|
127 | DMAIn.Reset <= '0'; | |
127 | DMAIn.Request <= '0'; |
|
128 | DMAIn.Request <= '0'; | |
128 | DMAIn.Store <= '0'; |
|
129 | DMAIn.Store <= '0'; | |
129 | DMAIn.Burst <= '0'; |
|
130 | DMAIn.Burst <= '0'; | |
130 | ELSE |
|
131 | ELSE | |
131 | grant_counter <= grant_counter+1; |
|
132 | grant_counter <= grant_counter+1; | |
132 | END IF; |
|
133 | END IF; | |
133 | END IF; |
|
134 | END IF; | |
134 |
|
135 | |||
135 | IF DMAOut.OKAY = '1' THEN |
|
136 | IF DMAOut.OKAY = '1' THEN | |
136 | IF data_counter = 15 THEN |
|
137 | IF data_counter = 15 THEN | |
137 | DMAIn.Address <= (OTHERS => '0'); |
|
138 | DMAIn.Address <= (OTHERS => '0'); | |
138 | state <= WAIT_LAST_READY; |
|
139 | state <= WAIT_LAST_READY; | |
139 | ELSE |
|
140 | ELSE | |
140 | data_counter <= data_counter + 1; |
|
141 | data_counter <= data_counter + 1; | |
141 | END IF; |
|
142 | END IF; | |
142 | END IF; |
|
143 | END IF; | |
143 | END IF; |
|
144 | END IF; | |
144 |
|
145 | |||
145 |
|
146 | |||
146 | WHEN WAIT_LAST_READY => |
|
147 | WHEN WAIT_LAST_READY => | |
147 | IF DMAOut.Ready = '1' THEN |
|
148 | IF DMAOut.Ready = '1' THEN | |
148 | IF grant_counter = 15 THEN |
|
149 | IF grant_counter = 15 THEN | |
149 | state <= IDLE; |
|
150 | state <= IDLE; | |
150 | send_ok <= '1'; |
|
151 | send_ok <= '1'; | |
151 | send_ko <= '0'; |
|
152 | send_ko <= '0'; | |
152 | ELSE |
|
153 | ELSE | |
153 | state <= ERROR0; |
|
154 | state <= ERROR0; | |
154 | END IF; |
|
155 | END IF; | |
155 | END IF; |
|
156 | END IF; | |
156 |
|
157 | |||
157 | WHEN ERROR0 => |
|
158 | WHEN ERROR0 => | |
158 | state <= ERROR1; |
|
159 | state <= ERROR1; | |
159 | WHEN ERROR1 => |
|
160 | WHEN ERROR1 => | |
160 | send_ok <= '0'; |
|
161 | send_ok <= '0'; | |
161 | send_ko <= '1'; |
|
162 | send_ko <= '1'; | |
162 | state <= IDLE; |
|
163 | state <= IDLE; | |
163 | WHEN OTHERS => NULL; |
|
164 | WHEN OTHERS => NULL; | |
164 | END CASE; |
|
165 | END CASE; | |
165 | END IF; |
|
166 | END IF; | |
166 | END PROCESS; |
|
167 | END PROCESS; | |
167 |
|
168 | |||
168 | DMAIn.Data <= data; |
|
169 | DMAIn.Data <= data; | |
169 |
|
170 | |||
170 |
ren <= '0' WHEN DMAOut.OKAY = '1' |
|
171 | ren <= '0' WHEN DMAOut.OKAY = '1' ELSE --AND (state = SEND_DATA OR state = WAIT_LAST_READY) ELSE | |
171 | '1'; |
|
172 | '1'; | |
|
173 | ||||
|
174 | -- \/ JC - 11/12/2013 \/ | |||
|
175 | --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE | |||
|
176 | -- '1'; | |||
|
177 | -- /\ JC - 11/12/2013 /\ | |||
|
178 | ||||
172 | -- \/ JC - 10/12/2013 \/ |
|
179 | -- \/ JC - 10/12/2013 \/ | |
173 | --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE |
|
180 | --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE | |
174 | -- '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE |
|
181 | -- '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE | |
175 | -- '1'; |
|
182 | -- '1'; | |
176 | -- /\ JC - 10/12/2013 /\ |
|
183 | -- /\ JC - 10/12/2013 /\ | |
177 |
|
184 | |||
178 | -- \/ JC - 09/12/2013 \/ |
|
185 | -- \/ JC - 09/12/2013 \/ | |
179 | --ren <= '0' WHEN state = SEND_DATA ELSE |
|
186 | --ren <= '0' WHEN state = SEND_DATA ELSE | |
180 | -- '1'; |
|
187 | -- '1'; | |
181 | -- /\ JC - 09/12/2013 /\ |
|
188 | -- /\ JC - 09/12/2013 /\ | |
182 |
|
189 | |||
183 | END beh; |
|
190 | END beh; |
@@ -1,176 +1,185 | |||||
1 |
|
1 | |||
2 | ------------------------------------------------------------------------------ |
|
2 | ------------------------------------------------------------------------------ | |
3 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | -- This file is a part of the LPP VHDL IP LIBRARY | |
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
5 | -- |
|
5 | -- | |
6 | -- This program is free software; you can redistribute it and/or modify |
|
6 | -- This program is free software; you can redistribute it and/or modify | |
7 | -- it under the terms of the GNU General Public License as published by |
|
7 | -- it under the terms of the GNU General Public License as published by | |
8 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | -- the Free Software Foundation; either version 3 of the License, or | |
9 | -- (at your option) any later version. |
|
9 | -- (at your option) any later version. | |
10 | -- |
|
10 | -- | |
11 | -- This program is distributed in the hope that it will be useful, |
|
11 | -- This program is distributed in the hope that it will be useful, | |
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | -- GNU General Public License for more details. |
|
14 | -- GNU General Public License for more details. | |
15 | -- |
|
15 | -- | |
16 | -- You should have received a copy of the GNU General Public License |
|
16 | -- You should have received a copy of the GNU General Public License | |
17 | -- along with this program; if not, write to the Free Software |
|
17 | -- along with this program; if not, write to the Free Software | |
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | ------------------------------------------------------------------------------- |
|
19 | ------------------------------------------------------------------------------- | |
20 | -- Author : Jean-christophe Pellion |
|
20 | -- Author : Jean-christophe Pellion | |
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
22 | -- jean-christophe.pellion@easii-ic.com |
|
22 | -- jean-christophe.pellion@easii-ic.com | |
23 | ------------------------------------------------------------------------------- |
|
23 | ------------------------------------------------------------------------------- | |
24 | -- 1.0 - initial version |
|
24 | -- 1.0 - initial version | |
25 | -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) |
|
25 | -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) | |
26 | ------------------------------------------------------------------------------- |
|
26 | ------------------------------------------------------------------------------- | |
27 | LIBRARY ieee; |
|
27 | LIBRARY ieee; | |
28 | USE ieee.std_logic_1164.ALL; |
|
28 | USE ieee.std_logic_1164.ALL; | |
29 | USE ieee.numeric_std.ALL; |
|
29 | USE ieee.numeric_std.ALL; | |
30 | LIBRARY grlib; |
|
30 | LIBRARY grlib; | |
31 | USE grlib.amba.ALL; |
|
31 | USE grlib.amba.ALL; | |
32 | USE grlib.stdlib.ALL; |
|
32 | USE grlib.stdlib.ALL; | |
33 | USE grlib.devices.ALL; |
|
33 | USE grlib.devices.ALL; | |
34 | USE GRLIB.DMA2AHB_Package.ALL; |
|
34 | USE GRLIB.DMA2AHB_Package.ALL; | |
35 | LIBRARY lpp; |
|
35 | LIBRARY lpp; | |
36 | USE lpp.lpp_amba.ALL; |
|
36 | USE lpp.lpp_amba.ALL; | |
37 | USE lpp.apb_devices_list.ALL; |
|
37 | USE lpp.apb_devices_list.ALL; | |
38 | USE lpp.lpp_memory.ALL; |
|
38 | USE lpp.lpp_memory.ALL; | |
39 | USE lpp.lpp_dma_pkg.ALL; |
|
39 | USE lpp.lpp_dma_pkg.ALL; | |
40 | USE lpp.lpp_waveform_pkg.ALL; |
|
40 | USE lpp.lpp_waveform_pkg.ALL; | |
41 | LIBRARY techmap; |
|
41 | LIBRARY techmap; | |
42 | USE techmap.gencomp.ALL; |
|
42 | USE techmap.gencomp.ALL; | |
43 |
|
43 | |||
44 |
|
44 | |||
45 | ENTITY lpp_dma_singleOrBurst IS |
|
45 | ENTITY lpp_dma_singleOrBurst IS | |
46 | GENERIC ( |
|
46 | GENERIC ( | |
47 | tech : INTEGER := inferred; |
|
47 | tech : INTEGER := inferred; | |
48 | hindex : INTEGER := 2 |
|
48 | hindex : INTEGER := 2 | |
49 | ); |
|
49 | ); | |
50 | PORT ( |
|
50 | PORT ( | |
51 | -- AMBA AHB system signals |
|
51 | -- AMBA AHB system signals | |
52 | HCLK : IN STD_ULOGIC; |
|
52 | HCLK : IN STD_ULOGIC; | |
53 | HRESETn : IN STD_ULOGIC; |
|
53 | HRESETn : IN STD_ULOGIC; | |
54 | -- |
|
54 | -- | |
55 | run : IN STD_LOGIC; |
|
55 | run : IN STD_LOGIC; | |
56 | -- AMBA AHB Master Interface |
|
56 | -- AMBA AHB Master Interface | |
57 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
57 | AHB_Master_In : IN AHB_Mst_In_Type; | |
58 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
58 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
59 | -- |
|
59 | -- | |
60 | send : IN STD_LOGIC; |
|
60 | send : IN STD_LOGIC; | |
61 | valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
61 | valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
62 | done : OUT STD_LOGIC; |
|
62 | done : OUT STD_LOGIC; | |
63 | ren : OUT STD_LOGIC; |
|
63 | ren : OUT STD_LOGIC; | |
64 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
64 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
65 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
65 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
66 | -- | |||
|
67 | debug_dmaout_okay : OUT STD_LOGIC | |||
|
68 | ||||
66 |
|
|
69 | ); | |
67 | END; |
|
70 | END; | |
68 |
|
71 | |||
69 | ARCHITECTURE Behavioral OF lpp_dma_singleOrBurst IS |
|
72 | ARCHITECTURE Behavioral OF lpp_dma_singleOrBurst IS | |
70 | ----------------------------------------------------------------------------- |
|
73 | ----------------------------------------------------------------------------- | |
71 | SIGNAL DMAIn : DMA_In_Type; |
|
74 | SIGNAL DMAIn : DMA_In_Type; | |
72 | SIGNAL DMAOut : DMA_OUt_Type; |
|
75 | SIGNAL DMAOut : DMA_OUt_Type; | |
73 | ----------------------------------------------------------------------------- |
|
76 | ----------------------------------------------------------------------------- | |
74 | ----------------------------------------------------------------------------- |
|
77 | ----------------------------------------------------------------------------- | |
75 | -- CONTROL |
|
78 | -- CONTROL | |
76 | SIGNAL single_send : STD_LOGIC; |
|
79 | SIGNAL single_send : STD_LOGIC; | |
77 | SIGNAL burst_send : STD_LOGIC; |
|
80 | SIGNAL burst_send : STD_LOGIC; | |
78 |
|
81 | |||
79 | ----------------------------------------------------------------------------- |
|
82 | ----------------------------------------------------------------------------- | |
80 | -- SEND SINGLE MODULE |
|
83 | -- SEND SINGLE MODULE | |
81 | SIGNAL single_dmai : DMA_In_Type; |
|
84 | SIGNAL single_dmai : DMA_In_Type; | |
82 |
|
85 | |||
83 | SIGNAL single_send_ok : STD_LOGIC; |
|
86 | SIGNAL single_send_ok : STD_LOGIC; | |
84 | SIGNAL single_send_ko : STD_LOGIC; |
|
87 | SIGNAL single_send_ko : STD_LOGIC; | |
85 | SIGNAL single_ren : STD_LOGIC; |
|
88 | SIGNAL single_ren : STD_LOGIC; | |
86 | ----------------------------------------------------------------------------- |
|
89 | ----------------------------------------------------------------------------- | |
87 | -- SEND SINGLE MODULE |
|
90 | -- SEND SINGLE MODULE | |
88 | SIGNAL burst_dmai : DMA_In_Type; |
|
91 | SIGNAL burst_dmai : DMA_In_Type; | |
89 |
|
92 | |||
90 | SIGNAL burst_send_ok : STD_LOGIC; |
|
93 | SIGNAL burst_send_ok : STD_LOGIC; | |
91 | SIGNAL burst_send_ko : STD_LOGIC; |
|
94 | SIGNAL burst_send_ko : STD_LOGIC; | |
92 | SIGNAL burst_ren : STD_LOGIC; |
|
95 | SIGNAL burst_ren : STD_LOGIC; | |
93 | ----------------------------------------------------------------------------- |
|
96 | ----------------------------------------------------------------------------- | |
94 | SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
97 | SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
95 | BEGIN |
|
98 | BEGIN | |
96 |
|
99 | |||
|
100 | debug_dmaout_okay <= DMAOut.OKAY; | |||
|
101 | ||||
|
102 | ||||
97 |
|
|
103 | ----------------------------------------------------------------------------- | |
98 | -- DMA to AHB interface |
|
104 | -- DMA to AHB interface | |
99 | DMA2AHB_1 : DMA2AHB |
|
105 | DMA2AHB_1 : DMA2AHB | |
100 | GENERIC MAP ( |
|
106 | GENERIC MAP ( | |
101 | hindex => hindex, |
|
107 | hindex => hindex, | |
102 | vendorid => VENDOR_LPP, |
|
108 | vendorid => VENDOR_LPP, | |
103 | deviceid => 10, |
|
109 | deviceid => 10, | |
104 | version => 0, |
|
110 | version => 0, | |
105 | syncrst => 1, |
|
111 | syncrst => 1, | |
106 | boundary => 1) -- FIX 11/01/2013 |
|
112 | boundary => 1) -- FIX 11/01/2013 | |
107 | PORT MAP ( |
|
113 | PORT MAP ( | |
108 | HCLK => HCLK, |
|
114 | HCLK => HCLK, | |
109 | HRESETn => HRESETn, |
|
115 | HRESETn => HRESETn, | |
110 | DMAIn => DMAIn, |
|
116 | DMAIn => DMAIn, | |
111 | DMAOut => DMAOut, |
|
117 | DMAOut => DMAOut, | |
112 |
|
118 | |||
113 | AHBIn => AHB_Master_In, |
|
119 | AHBIn => AHB_Master_In, | |
114 | AHBOut => AHB_Master_Out); |
|
120 | AHBOut => AHB_Master_Out); | |
115 | ----------------------------------------------------------------------------- |
|
121 | ----------------------------------------------------------------------------- | |
116 |
|
122 | |||
117 | ----------------------------------------------------------------------------- |
|
123 | ----------------------------------------------------------------------------- | |
118 | ----------------------------------------------------------------------------- |
|
124 | ----------------------------------------------------------------------------- | |
119 | -- LE PROBLEME EST LA !!!!! |
|
125 | -- LE PROBLEME EST LA !!!!! | |
120 | ----------------------------------------------------------------------------- |
|
126 | ----------------------------------------------------------------------------- | |
121 | ----------------------------------------------------------------------------- |
|
127 | ----------------------------------------------------------------------------- | |
122 | -- C'est le signal valid_burst qui n'est pas assez long. |
|
128 | -- C'est le signal valid_burst qui n'est pas assez long. | |
123 | ----------------------------------------------------------------------------- |
|
129 | ----------------------------------------------------------------------------- | |
124 | single_send <= send WHEN valid_burst = '0' ELSE '0'; |
|
130 | single_send <= send WHEN valid_burst = '0' ELSE '0'; | |
125 | burst_send <= send WHEN valid_burst = '1' ELSE '0'; |
|
131 | burst_send <= send WHEN valid_burst = '1' ELSE '0'; | |
126 | DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai; |
|
132 | DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai; | |
127 |
|
133 | |||
128 | -- TODO : verifier |
|
134 | -- TODO : verifier | |
129 | done <= single_send_ok OR single_send_ko OR burst_send_ok OR burst_send_ko; |
|
135 | done <= single_send_ok OR single_send_ko OR burst_send_ok OR burst_send_ko; | |
130 | --done <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE |
|
136 | --done <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE | |
131 | -- burst_send_ok OR burst_send_ko; |
|
137 | -- burst_send_ok OR burst_send_ko; | |
132 |
|
138 | |||
133 | --ren <= burst_ren WHEN valid_burst = '1' ELSE |
|
139 | --ren <= burst_ren WHEN valid_burst = '1' ELSE | |
134 | -- NOT single_send_ok; |
|
140 | -- NOT single_send_ok; | |
135 | ren <= burst_ren AND single_ren; |
|
141 | --ren <= burst_ren AND single_ren; | |
|
142 | ||||
|
143 | ren <= '0' WHEN DMAOut.OKAY = '1' ELSE | |||
|
144 | '1'; | |||
136 |
|
145 | |||
137 | ----------------------------------------------------------------------------- |
|
146 | ----------------------------------------------------------------------------- | |
138 | -- SEND 1 word by DMA |
|
147 | -- SEND 1 word by DMA | |
139 | ----------------------------------------------------------------------------- |
|
148 | ----------------------------------------------------------------------------- | |
140 | lpp_dma_send_1word_1 : lpp_dma_send_1word |
|
149 | lpp_dma_send_1word_1 : lpp_dma_send_1word | |
141 | PORT MAP ( |
|
150 | PORT MAP ( | |
142 | HCLK => HCLK, |
|
151 | HCLK => HCLK, | |
143 | HRESETn => HRESETn, |
|
152 | HRESETn => HRESETn, | |
144 | DMAIn => single_dmai, |
|
153 | DMAIn => single_dmai, | |
145 | DMAOut => DMAOut, |
|
154 | DMAOut => DMAOut, | |
146 |
|
155 | |||
147 | send => single_send, |
|
156 | send => single_send, | |
148 | address => address, |
|
157 | address => address, | |
149 | data => data_2_halfword, |
|
158 | data => data_2_halfword, | |
150 | ren => single_ren, |
|
159 | ren => single_ren, | |
151 |
|
160 | |||
152 | send_ok => single_send_ok, -- TODO |
|
161 | send_ok => single_send_ok, -- TODO | |
153 | send_ko => single_send_ko -- TODO |
|
162 | send_ko => single_send_ko -- TODO | |
154 | ); |
|
163 | ); | |
155 |
|
164 | |||
156 | ----------------------------------------------------------------------------- |
|
165 | ----------------------------------------------------------------------------- | |
157 | -- SEND 16 word by DMA (in burst mode) |
|
166 | -- SEND 16 word by DMA (in burst mode) | |
158 | ----------------------------------------------------------------------------- |
|
167 | ----------------------------------------------------------------------------- | |
159 | data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16); |
|
168 | data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16); | |
160 |
|
169 | |||
161 | lpp_dma_send_16word_1 : lpp_dma_send_16word |
|
170 | lpp_dma_send_16word_1 : lpp_dma_send_16word | |
162 | PORT MAP ( |
|
171 | PORT MAP ( | |
163 | HCLK => HCLK, |
|
172 | HCLK => HCLK, | |
164 | HRESETn => HRESETn, |
|
173 | HRESETn => HRESETn, | |
165 | DMAIn => burst_dmai, |
|
174 | DMAIn => burst_dmai, | |
166 | DMAOut => DMAOut, |
|
175 | DMAOut => DMAOut, | |
167 |
|
176 | |||
168 | send => burst_send, |
|
177 | send => burst_send, | |
169 | address => address, |
|
178 | address => address, | |
170 | data => data_2_halfword, |
|
179 | data => data_2_halfword, | |
171 | ren => burst_ren, |
|
180 | ren => burst_ren, | |
172 |
|
181 | |||
173 | send_ok => burst_send_ok, |
|
182 | send_ok => burst_send_ok, | |
174 | send_ko => burst_send_ko); |
|
183 | send_ko => burst_send_ko); | |
175 |
|
184 | |||
176 | END Behavioral; |
|
185 | END Behavioral; |
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