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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
31 USE lpp.lpp_amba.ALL;
32 USE lpp.apb_devices_list.ALL;
33 USE lpp.lpp_memory.ALL;
34 LIBRARY techmap;
35 USE techmap.gencomp.ALL;
36
37 ENTITY lpp_top_apbreg IS
38 GENERIC (
39 pindex : INTEGER := 4;
40 paddr : INTEGER := 4;
41 pmask : INTEGER := 16#fff#;
42 pirq : INTEGER := 0);
43 PORT (
44 -- AMBA AHB system signals
45 HCLK : IN STD_ULOGIC;
46 HRESETn : IN STD_ULOGIC;
47
48 -- AMBA APB Slave Interface
49 apbi : IN apb_slv_in_type;
50 apbo : OUT apb_slv_out_type;
51
52 -- IN
53 ready_matrix_f0_0 : IN STD_LOGIC;
54 ready_matrix_f0_1 : IN STD_LOGIC;
55 ready_matrix_f1 : IN STD_LOGIC;
56 ready_matrix_f2 : IN STD_LOGIC;
57 error_anticipating_empty_fifo : IN STD_LOGIC;
58 error_bad_component_error : IN STD_LOGIC;
59 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60
61 -- OUT
62 status_ready_matrix_f0_0 : OUT STD_LOGIC;
63 status_ready_matrix_f0_1 : OUT STD_LOGIC;
64 status_ready_matrix_f1 : OUT STD_LOGIC;
65 status_ready_matrix_f2 : OUT STD_LOGIC;
66 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
67 status_error_bad_component_error : OUT STD_LOGIC;
68
69 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
70 config_active_interruption_onError : OUT STD_LOGIC;
71 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
74 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
75 );
76
77 END lpp_top_apbreg;
78
79 ARCHITECTURE beh OF lpp_top_apbreg IS
80
81 CONSTANT REVISION : INTEGER := 1;
82
83 CONSTANT pconfig : apb_config_type := (
84 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 0, REVISION, pirq),
85 1 => apb_iobar(paddr, pmask));
86
87 TYPE lpp_dma_regs IS RECORD
88 config_active_interruption_onNewMatrix : STD_LOGIC;
89 config_active_interruption_onError : STD_LOGIC;
90 status_ready_matrix_f0_0 : STD_LOGIC;
91 status_ready_matrix_f0_1 : STD_LOGIC;
92 status_ready_matrix_f1 : STD_LOGIC;
93 status_ready_matrix_f2 : STD_LOGIC;
94 status_error_anticipating_empty_fifo : STD_LOGIC;
95 status_error_bad_component_error : STD_LOGIC;
96 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
100 END RECORD;
101
102 SIGNAL reg : lpp_dma_regs;
103
104 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
105
106 BEGIN -- beh
107
108 status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0;
109 status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1;
110 status_ready_matrix_f1 <= reg.status_ready_matrix_f1;
111 status_ready_matrix_f2 <= reg.status_ready_matrix_f2;
112 status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo;
113 status_error_bad_component_error <= reg.status_error_bad_component_error;
114
115 config_active_interruption_onNewMatrix <= reg.config_active_interruption_onNewMatrix;
116 config_active_interruption_onError <= reg.config_active_interruption_onError;
117 addr_matrix_f0_0 <= reg.addr_matrix_f0_0;
118 addr_matrix_f0_1 <= reg.addr_matrix_f0_1;
119 addr_matrix_f1 <= reg.addr_matrix_f1;
120 addr_matrix_f2 <= reg.addr_matrix_f2;
121
122 lpp_top_apbreg : PROCESS (HCLK, HRESETn)
123 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
124 BEGIN -- PROCESS lpp_dma_top
125 IF HRESETn = '0' THEN -- asynchronous reset (active low)
126 reg.config_active_interruption_onNewMatrix <= '0';
127 reg.config_active_interruption_onError <= '0';
128 reg.status_ready_matrix_f0_0 <= '0';
129 reg.status_ready_matrix_f0_1 <= '0';
130 reg.status_ready_matrix_f1 <= '0';
131 reg.status_ready_matrix_f2 <= '0';
132 reg.status_error_anticipating_empty_fifo <= '0';
133 reg.status_error_bad_component_error <= '0';
134 reg.addr_matrix_f0_0 <= (OTHERS => '0');
135 reg.addr_matrix_f0_1 <= (OTHERS => '0');
136 reg.addr_matrix_f1 <= (OTHERS => '0');
137 reg.addr_matrix_f2 <= (OTHERS => '0');
138 prdata <= (OTHERS => '0');
139 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
140
141 reg.status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
142 reg.status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
143 reg.status_ready_matrix_f1 <= reg.status_ready_matrix_f1 OR ready_matrix_f1;
144 reg.status_ready_matrix_f2 <= reg.status_ready_matrix_f2 OR ready_matrix_f2;
145
146 reg.status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
147 reg.status_error_bad_component_error <= reg.status_error_bad_component_error OR error_bad_component_error;
148
149 paddr := "000000";
150 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
151 prdata <= (OTHERS => '0');
152 IF apbi.psel(pindex) = '1' THEN
153 -- APB DMA READ --
154 CASE paddr(7 DOWNTO 2) IS
155 WHEN "000000" => prdata(0) <= reg.config_active_interruption_onNewMatrix;
156 prdata(1) <= reg.config_active_interruption_onError;
157 WHEN "000001" => prdata(0) <= reg.status_ready_matrix_f0_0;
158 prdata(1) <= reg.status_ready_matrix_f0_1;
159 prdata(2) <= reg.status_ready_matrix_f1;
160 prdata(3) <= reg.status_ready_matrix_f2;
161 prdata(4) <= reg.status_error_anticipating_empty_fifo;
162 prdata(5) <= reg.status_error_bad_component_error;
163 WHEN "000010" => prdata <= reg.addr_matrix_f0_0;
164 WHEN "000011" => prdata <= reg.addr_matrix_f0_1;
165 WHEN "000100" => prdata <= reg.addr_matrix_f1;
166 WHEN "000101" => prdata <= reg.addr_matrix_f2;
167 WHEN "000110" => prdata <= debug_reg;
168 WHEN OTHERS => NULL;
169 END CASE;
170 IF (apbi.pwrite AND apbi.penable) = '1' THEN
171 -- APB DMA WRITE --
172 CASE paddr(7 DOWNTO 2) IS
173 WHEN "000000" => reg.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
174 reg.config_active_interruption_onError <= apbi.pwdata(1);
175 WHEN "000001" => reg.status_ready_matrix_f0_0 <= apbi.pwdata(0);
176 reg.status_ready_matrix_f0_1 <= apbi.pwdata(1);
177 reg.status_ready_matrix_f1 <= apbi.pwdata(2);
178 reg.status_ready_matrix_f2 <= apbi.pwdata(3);
179 reg.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
180 reg.status_error_bad_component_error <= apbi.pwdata(5);
181 WHEN "000010" => reg.addr_matrix_f0_0 <= apbi.pwdata;
182 WHEN "000011" => reg.addr_matrix_f0_1 <= apbi.pwdata;
183 WHEN "000100" => reg.addr_matrix_f1 <= apbi.pwdata;
184 WHEN "000101" => reg.addr_matrix_f2 <= apbi.pwdata;
185 WHEN OTHERS => NULL;
186 END CASE;
187 END IF;
188 END IF;
189 END IF;
190 END PROCESS lpp_top_apbreg;
191
192 apbo.pirq <= (OTHERS => '0');
193 apbo.pindex <= pindex;
194 apbo.pconfig <= pconfig;
195 apbo.prdata <= prdata;
196
197
198 END beh;
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 LIBRARY grlib;
4 USE grlib.amba.ALL;
5 USE grlib.stdlib.ALL;
6 USE grlib.devices.ALL;
7 USE GRLIB.DMA2AHB_Package.ALL;
8 LIBRARY lpp;
9 USE lpp.lpp_ad_conv.ALL;
10 USE lpp.iir_filter.ALL;
11 USE lpp.FILTERcfg.ALL;
12 USE lpp.lpp_memory.ALL;
13 USE lpp.lpp_top_lfr_pkg.ALL;
14 USE lpp.lpp_dma_pkg.ALL;
15 LIBRARY techmap;
16 USE techmap.gencomp.ALL;
17
18 ENTITY lpp_top_lfr IS
19 GENERIC(
20 tech : INTEGER := 0;
21 hindex_SpectralMatrix : INTEGER := 2;
22 pindex : INTEGER := 4;
23 paddr : INTEGER := 4;
24 pmask : INTEGER := 16#fff#;
25 pirq : INTEGER := 0
26 );
27 PORT (
28 -- ADS7886
29 cnv_run : IN STD_LOGIC;
30 cnv : OUT STD_LOGIC;
31 sck : OUT STD_LOGIC;
32 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
33 --
34 cnv_clk : IN STD_LOGIC; -- 49 MHz
35 cnv_rstn : IN STD_LOGIC;
36 --
37 clk : IN STD_LOGIC; -- 25 MHz
38 rstn : IN STD_LOGIC;
39 --
40 apbi : IN apb_slv_in_type;
41 apbo : OUT apb_slv_out_type;
42
43 -- AMBA AHB Master Interface
44 AHB_DMA_SpectralMatrix_In : IN AHB_Mst_In_Type;
45 AHB_DMA_SpectralMatrix_Out : OUT AHB_Mst_Out_Type
46 );
47 END lpp_top_lfr;
48
49 ARCHITECTURE tb OF lpp_top_lfr IS
50
51 -----------------------------------------------------------------------------
52 -- f0
53 SIGNAL sample_f0_0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
54 SIGNAL sample_f0_1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
55 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
56 --
57 SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
58 SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
59 SIGNAL sample_f0_0_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
60 SIGNAL sample_f0_0_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
61 --
62 SIGNAL sample_f0_1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
63 SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
64 SIGNAL sample_f0_1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
65 SIGNAL sample_f0_1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
66 -----------------------------------------------------------------------------
67 -- f1
68 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
69 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
70 --
71 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
72 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
73 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
74 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
75 -----------------------------------------------------------------------------
76 -- f2
77 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
78 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
79 -----------------------------------------------------------------------------
80 -- f3
81 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
82 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
83 --
84 SIGNAL sample_f3_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 SIGNAL sample_f3_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
86 SIGNAL sample_f3_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f3_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 -----------------------------------------------------------------------------
89
90 -----------------------------------------------------------------------------
91 -- SPECTRAL MATRIX
92 -----------------------------------------------------------------------------
93 SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
94 SIGNAL fifo_empty : STD_LOGIC;
95 SIGNAL fifo_ren : STD_LOGIC;
96 SIGNAL header : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 SIGNAL header_val : STD_LOGIC;
98 SIGNAL header_ack : STD_LOGIC;
99
100 -----------------------------------------------------------------------------
101 -- APB REG
102 -----------------------------------------------------------------------------
103 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
104 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
105 SIGNAL ready_matrix_f1 : STD_LOGIC;
106 SIGNAL ready_matrix_f2 : STD_LOGIC;
107 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
108 SIGNAL error_bad_component_error : STD_LOGIC;
109 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
111 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
112 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
113 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
114 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
115 SIGNAL status_error_bad_component_error : STD_LOGIC;
116 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
117 SIGNAL config_active_interruption_onError : STD_LOGIC;
118 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
119 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
122
123 BEGIN
124
125 -----------------------------------------------------------------------------
126 -- CNA + FILTER
127 -----------------------------------------------------------------------------
128 lpp_top_acq_1 : lpp_top_acq
129 GENERIC MAP (
130 tech => tech)
131 PORT MAP (
132 cnv_run => cnv_run,
133 cnv => cnv,
134 sck => sck,
135 sdo => sdo,
136 cnv_clk => cnv_clk,
137 cnv_rstn => cnv_rstn,
138 clk => clk,
139 rstn => rstn,
140
141 sample_f0_0_wen => sample_f0_0_wen,
142 sample_f0_1_wen => sample_f0_1_wen,
143 sample_f0_wdata => sample_f0_wdata,
144 sample_f1_wen => sample_f1_wen,
145 sample_f1_wdata => sample_f1_wdata,
146 sample_f2_wen => sample_f2_wen,
147 sample_f2_wdata => sample_f2_wdata,
148 sample_f3_wen => sample_f3_wen,
149 sample_f3_wdata => sample_f3_wdata);
150
151 -----------------------------------------------------------------------------
152 -- FIFO
153 -----------------------------------------------------------------------------
154
155 lppFIFO_f0_0 : lppFIFOxN
156 GENERIC MAP (
157 tech => tech,
158 Data_sz => 18,
159 FifoCnt => 5,
160 Enable_ReUse => '0')
161 PORT MAP (
162 rst => rstn,
163 wclk => clk,
164 rclk => clk,
165 ReUse => (OTHERS => '0'),
166
167 wen => sample_f0_0_wen,
168 ren => sample_f0_0_ren,
169 wdata => sample_f0_wdata,
170 rdata => sample_f0_0_rdata,
171 full => sample_f0_0_full,
172 empty => sample_f0_0_empty);
173
174 lppFIFO_f0_1 : lppFIFOxN
175 GENERIC MAP (
176 tech => tech,
177 Data_sz => 18,
178 FifoCnt => 5,
179 Enable_ReUse => '0')
180 PORT MAP (
181 rst => rstn,
182 wclk => clk,
183 rclk => clk,
184 ReUse => (OTHERS => '0'),
185
186 wen => sample_f0_1_wen,
187 ren => sample_f0_1_ren,
188 wdata => sample_f0_wdata,
189 rdata => sample_f0_1_rdata,
190 full => sample_f0_1_full,
191 empty => sample_f0_1_empty);
192
193 lppFIFO_f1 : lppFIFOxN
194 GENERIC MAP (
195 tech => tech,
196 Data_sz => 18,
197 FifoCnt => 5,
198 Enable_ReUse => '0')
199 PORT MAP (
200 rst => rstn,
201 wclk => clk,
202 rclk => clk,
203 ReUse => (OTHERS => '0'),
204
205 wen => sample_f1_wen,
206 ren => sample_f1_ren,
207 wdata => sample_f1_wdata,
208 rdata => sample_f1_rdata,
209 full => sample_f1_full,
210 empty => sample_f1_empty);
211
212 lppFIFO_f3 : lppFIFOxN
213 GENERIC MAP (
214 tech => tech,
215 Data_sz => 18,
216 FifoCnt => 5,
217 Enable_ReUse => '0')
218 PORT MAP (
219 rst => rstn,
220 wclk => clk,
221 rclk => clk,
222 ReUse => (OTHERS => '0'),
223
224 wen => sample_f3_wen,
225 ren => sample_f3_ren,
226 wdata => sample_f3_wdata,
227 rdata => sample_f3_rdata,
228 full => sample_f3_full,
229 empty => sample_f3_empty);
230
231 -----------------------------------------------------------------------------
232 -- SPECTRAL MATRIX
233 -----------------------------------------------------------------------------
234
235 -----------------------------------------------------------------------------
236 -- DMA SPECTRAL MATRIX
237 -----------------------------------------------------------------------------
238 lpp_dma_ip_1 : lpp_dma_ip
239 GENERIC MAP (
240 tech => tech,
241 hindex => hindex_SpectralMatrix)
242 PORT MAP (
243 HCLK => clk,
244 HRESETn => rstn,
245 AHB_Master_In => AHB_DMA_SpectralMatrix_In,
246 AHB_Master_Out => AHB_DMA_SpectralMatrix_Out,
247
248 -- Connect to Spectral Matrix --
249 fifo_data => fifo_data,
250 fifo_empty => fifo_empty,
251 fifo_ren => fifo_ren,
252 header => header,
253 header_val => header_val,
254 header_ack => header_ack,
255
256 -- APB REG
257
258 ready_matrix_f0_0 => ready_matrix_f0_0,
259 ready_matrix_f0_1 => ready_matrix_f0_1,
260 ready_matrix_f1 => ready_matrix_f1,
261 ready_matrix_f2 => ready_matrix_f2,
262 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
263 error_bad_component_error => error_bad_component_error,
264 debug_reg => debug_reg,
265 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
266 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
267 status_ready_matrix_f1 => status_ready_matrix_f1,
268 status_ready_matrix_f2 => status_ready_matrix_f2,
269 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
270 status_error_bad_component_error => status_error_bad_component_error,
271 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
272 config_active_interruption_onError => config_active_interruption_onError,
273 addr_matrix_f0_0 => addr_matrix_f0_0,
274 addr_matrix_f0_1 => addr_matrix_f0_1,
275 addr_matrix_f1 => addr_matrix_f1,
276 addr_matrix_f2 => addr_matrix_f2);
277
278 lpp_top_apbreg_1 : lpp_top_apbreg
279 GENERIC MAP (
280 pindex => pindex,
281 paddr => paddr,
282 pmask => pmask,
283 pirq => pirq)
284 PORT MAP (
285 HCLK => clk,
286 HRESETn => rstn,
287 apbi => apbi,
288 apbo => apbo,
289
290 ready_matrix_f0_0 => ready_matrix_f0_0,
291 ready_matrix_f0_1 => ready_matrix_f0_1,
292 ready_matrix_f1 => ready_matrix_f1,
293 ready_matrix_f2 => ready_matrix_f2,
294 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
295 error_bad_component_error => error_bad_component_error,
296 debug_reg => debug_reg,
297 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
298 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
299 status_ready_matrix_f1 => status_ready_matrix_f1,
300 status_ready_matrix_f2 => status_ready_matrix_f2,
301 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
302 status_error_bad_component_error => status_error_bad_component_error,
303 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
304 config_active_interruption_onError => config_active_interruption_onError,
305 addr_matrix_f0_0 => addr_matrix_f0_0,
306 addr_matrix_f0_1 => addr_matrix_f0_1,
307 addr_matrix_f1 => addr_matrix_f1,
308 addr_matrix_f2 => addr_matrix_f2);
309
310
311 --TODO : add the irq alert for DMA matrix transfert ending
312 --TODO : add 5 bit register into APB to control the DATA SHIPING
313 --TODO : add Spectral Matrix (FFT + SP)
314 --TODO : add DMA for WaveForms Picker
315 --TODO : add APB Reg to control WaveForms Picker
316 --TODO : add WaveForms Picker
317
318 END tb;
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1 SCRIPTSDIR=scripts/
2 LIBDIR=lib/
3 BOARDSDIR=boards/
4 DESIGNSDIR=designs/
5
6
7
8 .PHONY:doc
9
10
11 all: help
12
13 help:
14 @echo
15 @echo " batch targets:"
16 @echo
17 @echo " make link : link lpp library to GRLIB at : $(GRLIB)"
18 @echo " make Patch-GRLIB : install library into GRLIB at : $(GRLIB)"
19 @echo " make dist : create a tar file for using into an other computer"
20 @echo " make Patched-dist : create a tar file for with a patched grlib for using"
21 @echo " into an other computer"
22 @echo " make allGPL : add a GPL HEADER in all vhdl Files"
23 @echo " make init : add a GPL HEADER in all vhdl Files, init all files"
24 @echo " make doc : make documentation for VHDL IPs"
25 @echo " make pdf : make pdf documentation for VHDL IPs"
26 @echo " make C-libs : make C drivers for APB devices"
27 @echo " binary files availiable on VHD_Lib/LPP_DRIVERS/lib ./includes"
28 @echo
29
30
31
32 allGPL:
33 @echo "Scanning VHDL files ..."
34 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R vhd lib
35 @echo "Scanning C files ..."
36 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R c LPP_drivers
37 @echo "Scanning H files ..."
38 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R h LPP_drivers
39
40 init: C-libs
41 sh $(SCRIPTSDIR)/vhdlsynPatcher.sh
42 sh $(SCRIPTSDIR)/makeDirs.sh lib/lpp
43
44 C-libs:APB_devs
45 make -C LPP_drivers
46
47
48 APB_devs:
49 sh $(SCRIPTSDIR)/APB_DEV_UPDATER.sh
50
51
52 Patch-GRLIB: init doc
53 sh $(SCRIPTSDIR)/patch.sh $(GRLIB)
54
55 link:
56 sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB)
57
58 dist: init
59 tar -cvzf ./../lpp-lib.tgz ./../VHD_Lib/*
60
61
62 Patched-dist: Patch-GRLIB
63 tar -cvzf ./../lpp-patched-GRLIB.tgz $(GRLIB)/*
64
65
66 doc:
67 mkdir -p doc/html
68 cp doc/ressources/*.jpg doc/html/
69 cp doc/ressources/doxygen.css doc/html/
70 make -C lib/lpp doc
71 make -C LPP_drivers doc
72
73
74 pdf: doc
75 sh $(SCRIPTSDIR)/doc.sh
76
77
78
79
80
1 SCRIPTSDIR=scripts/
2 LIBDIR=lib/
3 BOARDSDIR=boards/
4 DESIGNSDIR=designs/
5
6
7 .PHONY:doc
8
9
10 all: help
11
12 help:
13 @echo
14 @echo " batch targets:"
15 @echo
16 @echo " make link : link lpp library to GRLIB at : $(GRLIB)"
17 @echo " make Patch-GRLIB : install library into GRLIB at : $(GRLIB)"
18 @echo " make dist : create a tar file for using into an other computer"
19 @echo " make Patched-dist : create a tar file for with a patched grlib for using"
20 @echo " into an other computer"
21 @echo " make allGPL : add a GPL HEADER in all vhdl Files"
22 @echo " make init : add a GPL HEADER in all vhdl Files, init all files"
23 @echo " make doc : make documentation for VHDL IPs"
24 @echo " make pdf : make pdf documentation for VHDL IPs"
25 @echo " make C-libs : make C drivers for APB devices"
26 @echo " binary files availiable on VHD_Lib/LPP_DRIVERS/lib ./includes"
27 @echo
28
29
30
31 allGPL:
32 @echo "Scanning VHDL files ..."
33 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R vhd lib
34 @echo "Scanning C files ..."
35 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R c LPP_drivers
36 @echo "Scanning H files ..."
37 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R h LPP_drivers
38
39 init: C-libs
40 sh $(SCRIPTSDIR)/vhdlsynPatcher.sh
41 sh $(SCRIPTSDIR)/makeDirs.sh lib/lpp
42
43 C-libs:APB_devs
44 make -C LPP_drivers
45
46
47 APB_devs:
48 sh $(SCRIPTSDIR)/APB_DEV_UPDATER.sh
49
50
51 Patch-GRLIB: init doc
52 sh $(SCRIPTSDIR)/patch.sh $(GRLIB)
53
54 link:
55 sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB)
56 sh $(SCRIPTSDIR)/patchboards.sh $(GRLIB)
57
58 dist: init
59 tar -cvzf ./../lpp-lib.tgz ./../VHD_Lib/*
60
61
62 Patched-dist: Patch-GRLIB
63 tar -cvzf ./../lpp-patched-GRLIB.tgz $(GRLIB)/*
64
65
66 doc:
67 mkdir -p doc/html
68 cp doc/ressources/*.jpg doc/html/
69 cp doc/ressources/doxygen.css doc/html/
70 make -C lib/lpp doc
71 make -C LPP_drivers doc
72
73
74 pdf: doc
75 sh $(SCRIPTSDIR)/doc.sh
76
77
78
79
80
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@@ -1,48 +1,49
1 1
2 2 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd
3 3 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd
4 4 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd
5 5 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd
6 6 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd
7 7 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd
8 8 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd
9 9 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd
10 10 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd
11 11 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd
12 12 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd
13 13 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd
14 14 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd
15 15 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd
16 16 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd
17 17
18 18 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd
19 19 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd
20 20 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd
21 21 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd
22 22 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd
23 23
24 24 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd
25 25 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd
26 26 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd
27 27 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd
28 28
29 29 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd
30 30 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd
31 31 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd
32 32
33
33 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd
34 34
35 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd
35 vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
36 vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd
36 37
37 38 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd
38 39 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd
39 40 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd
40 41
41 42 vcom -quiet -93 -work work Top_Data_Acquisition.vhd
42 43 vcom -quiet -93 -work work TB_Data_Acquisition.vhd
43 44
44 vsim work.TB_Data_Acquisition
45 #vsim work.TB_Data_Acquisition
45 46
46 log -r *
47 do wave_data_acquisition.do
48 run 5 ms No newline at end of file
47 #log -r *
48 #do wave_data_acquisition.do
49 #run 5 ms No newline at end of file
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@@ -1,190 +1,186
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23 -- 1.0 - initial version
24 24 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
25 25 -------------------------------------------------------------------------------
26 26 LIBRARY ieee;
27 27 USE ieee.std_logic_1164.ALL;
28 28 USE ieee.numeric_std.ALL;
29 29 LIBRARY grlib;
30 30 USE grlib.amba.ALL;
31 31 USE grlib.stdlib.ALL;
32 32 USE grlib.devices.ALL;
33 33 USE GRLIB.DMA2AHB_Package.ALL;
34 34 --USE GRLIB.DMA2AHB_TestPackage.ALL;
35 35 LIBRARY lpp;
36 36 USE lpp.lpp_amba.ALL;
37 37 USE lpp.apb_devices_list.ALL;
38 38 USE lpp.lpp_memory.ALL;
39 39 USE lpp.lpp_dma_pkg.ALL;
40 40 LIBRARY techmap;
41 41 USE techmap.gencomp.ALL;
42 42
43 43
44 44 ENTITY lpp_dma IS
45 45 GENERIC (
46 46 tech : INTEGER := inferred;
47 47 hindex : INTEGER := 2;
48 48 pindex : INTEGER := 4;
49 49 paddr : INTEGER := 4;
50 50 pmask : INTEGER := 16#fff#;
51 51 pirq : INTEGER := 0);
52 52 PORT (
53 53 -- AMBA AHB system signals
54 54 HCLK : IN STD_ULOGIC;
55 55 HRESETn : IN STD_ULOGIC;
56 56
57 57 -- AMBA APB Slave Interface
58 58 apbi : IN apb_slv_in_type;
59 59 apbo : OUT apb_slv_out_type;
60 60
61 61 -- AMBA AHB Master Interface
62 62 AHB_Master_In : IN AHB_Mst_In_Type;
63 63 AHB_Master_Out : OUT AHB_Mst_Out_Type;
64 64
65 65 -- fifo interface
66 66 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
67 67 fifo_empty : IN STD_LOGIC;
68 68 fifo_ren : OUT STD_LOGIC;
69 69
70 70 -- header
71 71 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 72 header_val : IN STD_LOGIC;
73 73 header_ack : OUT STD_LOGIC
74 74 );
75 75 END;
76 76
77 77 ARCHITECTURE Behavioral OF lpp_dma IS
78 78
79 79 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
80 80 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
81 81 SIGNAL ready_matrix_f1 : STD_LOGIC;
82 82 SIGNAL ready_matrix_f2 : STD_LOGIC;
83 83 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
84 84 SIGNAL error_bad_component_error : STD_LOGIC;
85 85
86 86 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
87 87
88 88 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
89 89 SIGNAL config_active_interruption_onError : STD_LOGIC;
90 90 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
91 91 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
92 92 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
93 93 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
94 94 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
95 95 SIGNAL status_error_bad_component_error : STD_LOGIC;
96 96 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 97 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 98 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 99 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
100 100
101 101 BEGIN
102 102
103 103 -----------------------------------------------------------------------------
104 104 -- LPP DMA IP
105 105 -----------------------------------------------------------------------------
106 106
107 lpp_dma_ip_1: ENTITY work.lpp_dma_ip
107 lpp_dma_ip_1: lpp_dma_ip
108 108 GENERIC MAP (
109 109 tech => tech,
110 hindex => hindex,
111 pindex => pindex,
112 paddr => paddr,
113 pmask => pmask,
114 pirq => pirq)
110 hindex => hindex)
115 111 PORT MAP (
116 112 HCLK => HCLK,
117 113 HRESETn => HRESETn,
118 114 AHB_Master_In => AHB_Master_In,
119 115 AHB_Master_Out => AHB_Master_Out,
120 116 fifo_data => fifo_data,
121 117 fifo_empty => fifo_empty,
122 118 fifo_ren => fifo_ren,
123 119 header => header,
124 120 header_val => header_val,
125 121 header_ack => header_ack,
126 122 -------------------------------------------------------------------------
127 123 -- REG
128 124 ready_matrix_f0_0 => ready_matrix_f0_0,
129 125 ready_matrix_f0_1 => ready_matrix_f0_1,
130 126 ready_matrix_f1 => ready_matrix_f1,
131 127 ready_matrix_f2 => ready_matrix_f2,
132 128 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
133 129 error_bad_component_error => error_bad_component_error,
134 130
135 131 debug_reg => debug_reg,
136 132
137 133 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
138 134 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
139 135 status_ready_matrix_f1 => status_ready_matrix_f1,
140 136 status_ready_matrix_f2 => status_ready_matrix_f2,
141 137 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
142 138 status_error_bad_component_error => status_error_bad_component_error,
143 139 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
144 140 config_active_interruption_onError => config_active_interruption_onError,
145 141 addr_matrix_f0_0 => addr_matrix_f0_0,
146 142 addr_matrix_f0_1 => addr_matrix_f0_1,
147 143 addr_matrix_f1 => addr_matrix_f1,
148 144 addr_matrix_f2 => addr_matrix_f2);
149 145
150 146 -----------------------------------------------------------------------------
151 147 -- APB REGISTER
152 148 -----------------------------------------------------------------------------
153 149
154 150 lpp_dma_apbreg_1 : lpp_dma_apbreg
155 151 GENERIC MAP (
156 152 pindex => pindex,
157 153 paddr => paddr,
158 154 pmask => pmask,
159 155 pirq => pirq)
160 156 PORT MAP (
161 157 HCLK => HCLK,
162 158 HRESETn => HRESETn,
163 159 apbi => apbi,
164 160 apbo => apbo,
165 161 -- IN
166 162 ready_matrix_f0_0 => ready_matrix_f0_0,
167 163 ready_matrix_f0_1 => ready_matrix_f0_1,
168 164 ready_matrix_f1 => ready_matrix_f1,
169 165 ready_matrix_f2 => ready_matrix_f2,
170 166 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
171 167 error_bad_component_error => error_bad_component_error,
172 168 --
173 169 debug_reg => debug_reg,
174 170 -- OUT
175 171 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
176 172 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
177 173 status_ready_matrix_f1 => status_ready_matrix_f1,
178 174 status_ready_matrix_f2 => status_ready_matrix_f2,
179 175 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
180 176 status_error_bad_component_error => status_error_bad_component_error,
181 177 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, -- TODO
182 178 config_active_interruption_onError => config_active_interruption_onError, -- TODO
183 179 addr_matrix_f0_0 => addr_matrix_f0_0,
184 180 addr_matrix_f0_1 => addr_matrix_f0_1,
185 181 addr_matrix_f1 => addr_matrix_f1,
186 182 addr_matrix_f2 => addr_matrix_f2);
187 183
188 184 -----------------------------------------------------------------------------
189 185
190 186 END Behavioral;
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@@ -1,355 +1,352
1 1
2 2 ------------------------------------------------------------------------------
3 3 -- This file is a part of the LPP VHDL IP LIBRARY
4 4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 5 --
6 6 -- This program is free software; you can redistribute it and/or modify
7 7 -- it under the terms of the GNU General Public License as published by
8 8 -- the Free Software Foundation; either version 3 of the License, or
9 9 -- (at your option) any later version.
10 10 --
11 11 -- This program is distributed in the hope that it will be useful,
12 12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 14 -- GNU General Public License for more details.
15 15 --
16 16 -- You should have received a copy of the GNU General Public License
17 17 -- along with this program; if not, write to the Free Software
18 18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 19 -------------------------------------------------------------------------------
20 20 -- Author : Jean-christophe Pellion
21 21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 22 -- jean-christophe.pellion@easii-ic.com
23 23 -------------------------------------------------------------------------------
24 24 -- 1.0 - initial version
25 25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 26 -------------------------------------------------------------------------------
27 27 LIBRARY ieee;
28 28 USE ieee.std_logic_1164.ALL;
29 29 USE ieee.numeric_std.ALL;
30 30 LIBRARY grlib;
31 31 USE grlib.amba.ALL;
32 32 USE grlib.stdlib.ALL;
33 33 USE grlib.devices.ALL;
34 34 USE GRLIB.DMA2AHB_Package.ALL;
35 35 --USE GRLIB.DMA2AHB_TestPackage.ALL;
36 36 LIBRARY lpp;
37 37 USE lpp.lpp_amba.ALL;
38 38 USE lpp.apb_devices_list.ALL;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_dma_pkg.ALL;
41 41 LIBRARY techmap;
42 42 USE techmap.gencomp.ALL;
43 43
44 44
45 45 ENTITY lpp_dma_ip IS
46 46 GENERIC (
47 47 tech : INTEGER := inferred;
48 hindex : INTEGER := 2;
49 pindex : INTEGER := 4;
50 paddr : INTEGER := 4;
51 pmask : INTEGER := 16#fff#;
52 pirq : INTEGER := 0);
48 hindex : INTEGER := 2
49 );
53 50 PORT (
54 51 -- AMBA AHB system signals
55 52 HCLK : IN STD_ULOGIC;
56 53 HRESETn : IN STD_ULOGIC;
57 54
58 55 -- AMBA AHB Master Interface
59 56 AHB_Master_In : IN AHB_Mst_In_Type;
60 57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
61 58
62 59 -- fifo interface
63 60 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
64 61 fifo_empty : IN STD_LOGIC;
65 62 fifo_ren : OUT STD_LOGIC;
66 63
67 64 -- header
68 65 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
69 66 header_val : IN STD_LOGIC;
70 67 header_ack : OUT STD_LOGIC;
71 68
72 69 -- Reg out
73 70 ready_matrix_f0_0 : OUT STD_LOGIC;
74 71 ready_matrix_f0_1 : OUT STD_LOGIC;
75 72 ready_matrix_f1 : OUT STD_LOGIC;
76 73 ready_matrix_f2 : OUT STD_LOGIC;
77 74 error_anticipating_empty_fifo : OUT STD_LOGIC;
78 75 error_bad_component_error : OUT STD_LOGIC;
79 76 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 77
81 78 -- Reg In
82 79 status_ready_matrix_f0_0 :IN STD_LOGIC;
83 80 status_ready_matrix_f0_1 :IN STD_LOGIC;
84 81 status_ready_matrix_f1 :IN STD_LOGIC;
85 82 status_ready_matrix_f2 :IN STD_LOGIC;
86 83 status_error_anticipating_empty_fifo :IN STD_LOGIC;
87 84 status_error_bad_component_error :IN STD_LOGIC;
88 85
89 86 config_active_interruption_onNewMatrix : IN STD_LOGIC;
90 87 config_active_interruption_onError : IN STD_LOGIC;
91 88 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 89 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
93 90 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
94 91 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
95 92 );
96 93 END;
97 94
98 95 ARCHITECTURE Behavioral OF lpp_dma_ip IS
99 96 -----------------------------------------------------------------------------
100 97 SIGNAL DMAIn : DMA_In_Type;
101 98 SIGNAL header_dmai : DMA_In_Type;
102 99 SIGNAL component_dmai : DMA_In_Type;
103 100 SIGNAL DMAOut : DMA_OUt_Type;
104 101 -----------------------------------------------------------------------------
105 102
106 103 -----------------------------------------------------------------------------
107 104 -----------------------------------------------------------------------------
108 105 TYPE state_DMAWriteBurst IS (IDLE,
109 106 TRASH_FIFO,
110 107 WAIT_HEADER_ACK,
111 108 SEND_DATA,
112 109 WAIT_DATA_ACK,
113 110 CHECK_LENGTH
114 111 );
115 112 SIGNAL state : state_DMAWriteBurst := IDLE;
116 113
117 114 SIGNAL nbSend : INTEGER;
118 115 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
119 116 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
120 117 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
121 118 SIGNAL header_check_ok : STD_LOGIC;
122 119 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
123 120 SIGNAL send_matrix : STD_LOGIC;
124 121 SIGNAL request : STD_LOGIC;
125 122 SIGNAL remaining_data_request : INTEGER;
126 123 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
127 124 -----------------------------------------------------------------------------
128 125 -----------------------------------------------------------------------------
129 126 SIGNAL header_select : STD_LOGIC;
130 127
131 128 SIGNAL header_send : STD_LOGIC;
132 129 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 130 SIGNAL header_send_ok : STD_LOGIC;
134 131 SIGNAL header_send_ko : STD_LOGIC;
135 132
136 133 SIGNAL component_send : STD_LOGIC;
137 134 SIGNAL component_send_ok : STD_LOGIC;
138 135 SIGNAL component_send_ko : STD_LOGIC;
139 136 -----------------------------------------------------------------------------
140 137 SIGNAL fifo_ren_trash : STD_LOGIC;
141 138 SIGNAL component_fifo_ren : STD_LOGIC;
142 139
143 140 -----------------------------------------------------------------------------
144 141 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 142
146 143 BEGIN
147 144
148 145 -----------------------------------------------------------------------------
149 146 -- DMA to AHB interface
150 147 -----------------------------------------------------------------------------
151 148
152 149 DMA2AHB_1 : DMA2AHB
153 150 GENERIC MAP (
154 151 hindex => hindex,
155 152 vendorid => VENDOR_LPP,
156 153 deviceid => 0,
157 154 version => 0,
158 155 syncrst => 1,
159 156 boundary => 1) -- FIX 11/01/2013
160 157 PORT MAP (
161 158 HCLK => HCLK,
162 159 HRESETn => HRESETn,
163 160 DMAIn => DMAIn,
164 161 DMAOut => DMAOut,
165 162 AHBIn => AHB_Master_In,
166 163 AHBOut => AHB_Master_Out);
167 164
168 165 debug_reg <= debug_reg_s;
169 166
170 167 debug_info: PROCESS (HCLK, HRESETn)
171 168 BEGIN -- PROCESS debug_info
172 169 IF HRESETn = '0' THEN -- asynchronous reset (active low)
173 170 debug_reg <= (OTHERS => '0');
174 171 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
175 172 debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry );
176 173 debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ;
177 174 IF state = TRASH_FIFO THEN debug_reg(2) <= '1'; END IF;
178 175 debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko);
179 176 debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok);
180 177 debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko);
181 178 debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok);
182 179
183 180 debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1');
184 181 END IF;
185 182 END PROCESS debug_info;
186 183
187 184
188 185 matrix_type <= header(1 DOWNTO 0);
189 186 component_type <= header(5 DOWNTO 2);
190 187
191 188 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
192 189 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
193 190 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
194 191 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
195 192 '0';
196 193
197 194 header_check_ok <= '0' WHEN component_type = "1111" ELSE
198 195 '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE
199 196 '1' WHEN component_type = component_type_pre + "0001" ELSE
200 197 '0';
201 198
202 199 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
203 200 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
204 201 addr_matrix_f1 WHEN matrix_type = "10" ELSE
205 202 addr_matrix_f2 WHEN matrix_type = "11" ELSE
206 203 (OTHERS => '0');
207 204
208 205 -----------------------------------------------------------------------------
209 206 -- DMA control
210 207 -----------------------------------------------------------------------------
211 208 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
212 209 BEGIN -- PROCESS DMAWriteBurst_p
213 210 IF HRESETn = '0' THEN -- asynchronous reset (active low)
214 211 state <= IDLE;
215 212 header_ack <= '0';
216 213 ready_matrix_f0_0 <= '0';
217 214 ready_matrix_f0_1 <= '0';
218 215 ready_matrix_f1 <= '0';
219 216 ready_matrix_f2 <= '0';
220 217 error_anticipating_empty_fifo <= '0';
221 218 error_bad_component_error <= '0';
222 219 component_type_pre <= "1110";
223 220 fifo_ren_trash <= '1';
224 221 component_send <= '0';
225 222 address <= (OTHERS => '0');
226 223 header_select <= '0';
227 224 header_send <= '0';
228 225 header_data <= (OTHERS => '0');
229 226 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
230 227
231 228 CASE state IS
232 229 WHEN IDLE =>
233 230 ready_matrix_f0_0 <= '0';
234 231 ready_matrix_f0_1 <= '0';
235 232 ready_matrix_f1 <= '0';
236 233 ready_matrix_f2 <= '0';
237 234 error_bad_component_error <= '0';
238 235 header_select <= '1';
239 236 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
240 237 IF header_check_ok = '1' THEN
241 238 header_data <= header;
242 239 component_type_pre <= header(5 DOWNTO 2);
243 240 header_ack <= '1';
244 241 --
245 242 header_send <= '1';
246 243 IF component_type = "0000" THEN
247 244 address <= address_matrix;
248 245 END IF;
249 246 header_data <= header;
250 247 --
251 248 state <= WAIT_HEADER_ACK;
252 249 ELSE
253 250 error_bad_component_error <= '1';
254 251 component_type_pre <= "1110";
255 252 header_ack <= '1';
256 253 state <= TRASH_FIFO;
257 254 END IF;
258 255 END IF;
259 256
260 257 WHEN TRASH_FIFO =>
261 258 error_bad_component_error <= '0';
262 259 error_anticipating_empty_fifo <= '0';
263 260 IF fifo_empty = '1' THEN
264 261 state <= IDLE;
265 262 fifo_ren_trash <= '1';
266 263 ELSE
267 264 fifo_ren_trash <= '0';
268 265 END IF;
269 266
270 267 WHEN WAIT_HEADER_ACK =>
271 268 header_send <= '0';
272 269 IF header_send_ko = '1' THEN
273 270 state <= TRASH_FIFO;
274 271 error_anticipating_empty_fifo <= '1';
275 272 -- TODO : error sending header
276 273 ELSIF header_send_ok = '1' THEN
277 274 header_select <= '0';
278 275 state <= SEND_DATA;
279 276 address <= address + 4;
280 277 END IF;
281 278
282 279 WHEN SEND_DATA =>
283 280 IF fifo_empty = '1' THEN
284 281 state <= IDLE;
285 282 IF component_type = "1110" THEN
286 283 CASE matrix_type IS
287 284 WHEN "00" => ready_matrix_f0_0 <= '1';
288 285 WHEN "01" => ready_matrix_f0_1 <= '1';
289 286 WHEN "10" => ready_matrix_f1 <= '1';
290 287 WHEN "11" => ready_matrix_f2 <= '1';
291 288 WHEN OTHERS => NULL;
292 289 END CASE;
293 290 END IF;
294 291 ELSE
295 292 component_send <= '1';
296 293 address <= address;
297 294 state <= WAIT_DATA_ACK;
298 295 END IF;
299 296
300 297 WHEN WAIT_DATA_ACK =>
301 298 component_send <= '0';
302 299 IF component_send_ok = '1' THEN
303 300 address <= address + 64;
304 301 state <= SEND_DATA;
305 302 ELSIF component_send_ko = '1' THEN
306 303 error_anticipating_empty_fifo <= '0';
307 304 state <= TRASH_FIFO;
308 305 END IF;
309 306
310 307 WHEN CHECK_LENGTH =>
311 308 state <= IDLE;
312 309 WHEN OTHERS => NULL;
313 310 END CASE;
314 311
315 312 END IF;
316 313 END PROCESS DMAWriteFSM_p;
317 314
318 315 -----------------------------------------------------------------------------
319 316 -- SEND 1 word by DMA
320 317 -----------------------------------------------------------------------------
321 318 lpp_dma_send_1word_1 : lpp_dma_send_1word
322 319 PORT MAP (
323 320 HCLK => HCLK,
324 321 HRESETn => HRESETn,
325 322 DMAIn => header_dmai,
326 323 DMAOut => DMAOut,
327 324
328 325 send => header_send,
329 326 address => address,
330 327 data => header_data,
331 328 send_ok => header_send_ok,
332 329 send_ko => header_send_ko
333 330 );
334 331
335 332 -----------------------------------------------------------------------------
336 333 -- SEND 16 word by DMA (in burst mode)
337 334 -----------------------------------------------------------------------------
338 335 lpp_dma_send_16word_1 : lpp_dma_send_16word
339 336 PORT MAP (
340 337 HCLK => HCLK,
341 338 HRESETn => HRESETn,
342 339 DMAIn => component_dmai,
343 340 DMAOut => DMAOut,
344 341
345 342 send => component_send,
346 343 address => address,
347 344 data => fifo_data,
348 345 ren => component_fifo_ren,
349 346 send_ok => component_send_ok,
350 347 send_ko => component_send_ko);
351 348
352 349 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
353 350 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
354 351
355 352 END Behavioral;
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@@ -1,204 +1,200
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE std.textio.ALL;
28 28 LIBRARY grlib;
29 29 USE grlib.amba.ALL;
30 30 USE grlib.stdlib.ALL;
31 31 USE GRLIB.DMA2AHB_Package.ALL;
32 32 LIBRARY techmap;
33 33 USE techmap.gencomp.ALL;
34 34 LIBRARY lpp;
35 35 USE lpp.lpp_amba.ALL;
36 36 USE lpp.apb_devices_list.ALL;
37 37 USE lpp.lpp_memory.ALL;
38 38
39 39 PACKAGE lpp_dma_pkg IS
40 40
41 41 COMPONENT lpp_dma
42 42 GENERIC (
43 43 tech : INTEGER;
44 44 hindex : INTEGER;
45 45 pindex : INTEGER;
46 46 paddr : INTEGER;
47 47 pmask : INTEGER;
48 48 pirq : INTEGER);
49 49 PORT (
50 50 HCLK : IN STD_ULOGIC;
51 51 HRESETn : IN STD_ULOGIC;
52 52 apbi : IN apb_slv_in_type;
53 53 apbo : OUT apb_slv_out_type;
54 54 AHB_Master_In : IN AHB_Mst_In_Type;
55 55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
56 56 -- fifo interface
57 57 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 58 fifo_empty : IN STD_LOGIC;
59 59 fifo_ren : OUT STD_LOGIC;
60 60 -- header
61 61 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 62 header_val : IN STD_LOGIC;
63 63 header_ack : OUT STD_LOGIC);
64 64 END COMPONENT;
65 65
66 66 COMPONENT fifo_test_dma
67 67 GENERIC (
68 68 tech : INTEGER;
69 69 pindex : INTEGER;
70 70 paddr : INTEGER;
71 71 pmask : INTEGER);
72 72 PORT (
73 73 HCLK : IN STD_ULOGIC;
74 74 HRESETn : IN STD_ULOGIC;
75 75 apbi : IN apb_slv_in_type;
76 76 apbo : OUT apb_slv_out_type;
77 77 -- fifo interface
78 78 fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 79 fifo_empty : OUT STD_LOGIC;
80 80 fifo_ren : IN STD_LOGIC;
81 81 -- header
82 82 header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 83 header_val : OUT STD_LOGIC;
84 84 header_ack : IN STD_LOGIC
85 85 );
86 86 END COMPONENT;
87 87
88 88 COMPONENT lpp_dma_apbreg
89 89 GENERIC (
90 90 pindex : INTEGER;
91 91 paddr : INTEGER;
92 92 pmask : INTEGER;
93 93 pirq : INTEGER);
94 94 PORT (
95 95 HCLK : IN STD_ULOGIC;
96 96 HRESETn : IN STD_ULOGIC;
97 97 apbi : IN apb_slv_in_type;
98 98 apbo : OUT apb_slv_out_type;
99 99 -- IN
100 100 ready_matrix_f0_0 : IN STD_LOGIC;
101 101 ready_matrix_f0_1 : IN STD_LOGIC;
102 102 ready_matrix_f1 : IN STD_LOGIC;
103 103 ready_matrix_f2 : IN STD_LOGIC;
104 104 error_anticipating_empty_fifo : IN STD_LOGIC;
105 105 error_bad_component_error : IN STD_LOGIC;
106 106 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
107 107
108 108 -- OUT
109 109 status_ready_matrix_f0_0 : OUT STD_LOGIC;
110 110 status_ready_matrix_f0_1 : OUT STD_LOGIC;
111 111 status_ready_matrix_f1 : OUT STD_LOGIC;
112 112 status_ready_matrix_f2 : OUT STD_LOGIC;
113 113 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
114 114 status_error_bad_component_error : OUT STD_LOGIC;
115 115
116 116 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
117 117 config_active_interruption_onError : OUT STD_LOGIC;
118 118 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 119 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 120 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
122 122 );
123 123 END COMPONENT;
124 124
125 125 COMPONENT lpp_dma_send_1word
126 126 PORT (
127 127 HCLK : IN STD_ULOGIC;
128 128 HRESETn : IN STD_ULOGIC;
129 129 DMAIn : OUT DMA_In_Type;
130 130 DMAOut : IN DMA_OUt_Type;
131 131 send : IN STD_LOGIC;
132 132 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 133 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
134 134 send_ok : OUT STD_LOGIC;
135 135 send_ko : OUT STD_LOGIC);
136 136 END COMPONENT;
137 137
138 138 COMPONENT lpp_dma_send_16word
139 139 PORT (
140 140 HCLK : IN STD_ULOGIC;
141 141 HRESETn : IN STD_ULOGIC;
142 142 DMAIn : OUT DMA_In_Type;
143 143 DMAOut : IN DMA_OUt_Type;
144 144 send : IN STD_LOGIC;
145 145 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
146 146 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
147 147 ren : OUT STD_LOGIC;
148 148 send_ok : OUT STD_LOGIC;
149 149 send_ko : OUT STD_LOGIC);
150 150 END COMPONENT;
151 151
152 152 COMPONENT fifo_latency_correction
153 153 PORT (
154 154 HCLK : IN STD_ULOGIC;
155 155 HRESETn : IN STD_ULOGIC;
156 156 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
157 157 fifo_empty : IN STD_LOGIC;
158 158 fifo_ren : OUT STD_LOGIC;
159 159 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
160 160 dma_empty : OUT STD_LOGIC;
161 161 dma_ren : IN STD_LOGIC);
162 162 END COMPONENT;
163 163
164 164 COMPONENT lpp_dma_ip
165 165 GENERIC (
166 166 tech : INTEGER;
167 hindex : INTEGER;
168 pindex : INTEGER;
169 paddr : INTEGER;
170 pmask : INTEGER;
171 pirq : INTEGER);
167 hindex : INTEGER);
172 168 PORT (
173 169 HCLK : IN STD_ULOGIC;
174 170 HRESETn : IN STD_ULOGIC;
175 171 AHB_Master_In : IN AHB_Mst_In_Type;
176 172 AHB_Master_Out : OUT AHB_Mst_Out_Type;
177 173 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
178 174 fifo_empty : IN STD_LOGIC;
179 175 fifo_ren : OUT STD_LOGIC;
180 176 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
181 177 header_val : IN STD_LOGIC;
182 178 header_ack : OUT STD_LOGIC;
183 179 ready_matrix_f0_0 : OUT STD_LOGIC;
184 180 ready_matrix_f0_1 : OUT STD_LOGIC;
185 181 ready_matrix_f1 : OUT STD_LOGIC;
186 182 ready_matrix_f2 : OUT STD_LOGIC;
187 183 error_anticipating_empty_fifo : OUT STD_LOGIC;
188 184 error_bad_component_error : OUT STD_LOGIC;
189 185 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
190 186 status_ready_matrix_f0_0 : IN STD_LOGIC;
191 187 status_ready_matrix_f0_1 : IN STD_LOGIC;
192 188 status_ready_matrix_f1 : IN STD_LOGIC;
193 189 status_ready_matrix_f2 : IN STD_LOGIC;
194 190 status_error_anticipating_empty_fifo : IN STD_LOGIC;
195 191 status_error_bad_component_error : IN STD_LOGIC;
196 192 config_active_interruption_onNewMatrix : IN STD_LOGIC;
197 193 config_active_interruption_onError : IN STD_LOGIC;
198 194 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
199 195 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
200 196 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
201 197 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
202 198 END COMPONENT;
203 199
204 200 END;
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@@ -1,354 +1,332
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 LIBRARY lpp;
4 4 USE lpp.lpp_ad_conv.ALL;
5 5 USE lpp.iir_filter.ALL;
6 6 USE lpp.FILTERcfg.ALL;
7 7 USE lpp.lpp_memory.ALL;
8 8 USE lpp.lpp_top_lfr_pkg.ALL;
9 9 LIBRARY techmap;
10 10 USE techmap.gencomp.ALL;
11 11
12 12 ENTITY lpp_top_acq IS
13 13 GENERIC(
14 14 tech : INTEGER := 0
15 15 );
16 16 PORT (
17 17 -- ADS7886
18 18 cnv_run : IN STD_LOGIC;
19 19 cnv : OUT STD_LOGIC;
20 20 sck : OUT STD_LOGIC;
21 21 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
22 22 --
23 cnv_clk : IN STD_LOGIC;
23 cnv_clk : IN STD_LOGIC; -- 49 MHz
24 24 cnv_rstn : IN STD_LOGIC;
25 25 --
26 clk : IN STD_LOGIC;
26 clk : IN STD_LOGIC; -- 25 MHz
27 27 rstn : IN STD_LOGIC;
28 28 --
29 29 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30 30 sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
31 31 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
32 32 --
33 33 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
34 34 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
35 35 --
36 36 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
37 37 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
38 38 --
39 39 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
40 40 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0)
41 41 );
42 42 END lpp_top_acq;
43 43
44 44 ARCHITECTURE tb OF lpp_top_acq IS
45 45
46 46 COMPONENT Downsampling
47 47 GENERIC (
48 48 ChanelCount : INTEGER;
49 49 SampleSize : INTEGER;
50 50 DivideParam : INTEGER);
51 51 PORT (
52 52 clk : IN STD_LOGIC;
53 53 rstn : IN STD_LOGIC;
54 54 sample_in_val : IN STD_LOGIC;
55 55 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
56 56 sample_out_val : OUT STD_LOGIC;
57 57 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
58 58 END COMPONENT;
59 59
60 60 -----------------------------------------------------------------------------
61 61 CONSTANT ChanelCount : INTEGER := 8;
62 62 CONSTANT ncycle_cnv_high : INTEGER := 79;
63 63 CONSTANT ncycle_cnv : INTEGER := 500;
64 64
65 65 -----------------------------------------------------------------------------
66 66 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
67 67 SIGNAL sample_val : STD_LOGIC;
68 68 SIGNAL sample_val_delay : STD_LOGIC;
69 69 -----------------------------------------------------------------------------
70 70 CONSTANT Coef_SZ : INTEGER := 9;
71 71 CONSTANT CoefCntPerCel : INTEGER := 6;
72 72 CONSTANT CoefPerCel : INTEGER := 5;
73 73 CONSTANT Cels_count : INTEGER := 5;
74 74
75 -- SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
76 SIGNAL coefs_JC : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
75 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
77 76 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
78 -- SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 77 --
80 SIGNAL sample_filter_JC_out_val : STD_LOGIC;
81 SIGNAL sample_filter_JC_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
78 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
79 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
82 80 --
83 SIGNAL sample_filter_JC_out_r_val : STD_LOGIC;
84 SIGNAL sample_filter_JC_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
81 SIGNAL sample_filter_v2_out_r_val : STD_LOGIC;
82 SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
85 83 -----------------------------------------------------------------------------
86 84 SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
87 85 SIGNAL sample_downsampling_out_val : STD_LOGIC;
88 86 SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
89 87 --
90 88 SIGNAL sample_f0_val : STD_LOGIC;
91 89 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
92 90 --
93 91 SIGNAL sample_f0_0_val : STD_LOGIC;
94 92 SIGNAL sample_f0_1_val : STD_LOGIC;
95 93 SIGNAL counter_f0 : INTEGER;
96 94 -----------------------------------------------------------------------------
97 95 SIGNAL sample_f1_val : STD_LOGIC;
98 96 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
99 97 --
100 98 SIGNAL sample_f2_val : STD_LOGIC;
101 99 SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
102 100 --
103 101 SIGNAL sample_f3_val : STD_LOGIC;
104 102 SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
105 103
106 104 BEGIN
107 105
108 106 -- component instantiation
109 107 -----------------------------------------------------------------------------
110 108 DIGITAL_acquisition : ADS7886_drvr
111 109 GENERIC MAP (
112 110 ChanelCount => ChanelCount,
113 111 ncycle_cnv_high => ncycle_cnv_high,
114 112 ncycle_cnv => ncycle_cnv)
115 113 PORT MAP (
116 114 cnv_clk => cnv_clk, --
117 115 cnv_rstn => cnv_rstn, --
118 116 cnv_run => cnv_run, --
119 117 cnv => cnv, --
120 118 clk => clk, --
121 119 rstn => rstn, --
122 120 sck => sck, --
123 121 sdo => sdo(ChanelCount-1 DOWNTO 0), --
124 122 sample => sample,
125 123 sample_val => sample_val);
126 124
127 125 -----------------------------------------------------------------------------
128 126
129 127 PROCESS (clk, rstn)
130 128 BEGIN -- PROCESS
131 129 IF rstn = '0' THEN -- asynchronous reset (active low)
132 130 sample_val_delay <= '0';
133 131 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
134 132 sample_val_delay <= sample_val;
135 133 END IF;
136 134 END PROCESS;
137 135
138 136 -----------------------------------------------------------------------------
139 137 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
140 138 SampleLoop : FOR j IN 0 TO 15 GENERATE
141 139 sample_filter_in(i, j) <= sample(i)(j);
142 140 END GENERATE;
143 141
144 142 sample_filter_in(i, 16) <= sample(i)(15);
145 143 sample_filter_in(i, 17) <= sample(i)(15);
146 144 END GENERATE;
147
148 -- coefs <= CoefsInitValCst;
149 coefs_JC <= CoefsInitValCst_JC;
150
151 --FILTER : IIR_CEL_CTRLR
152 -- GENERIC MAP (
153 -- tech => 0,
154 -- Sample_SZ => 18,
155 -- ChanelsCount => ChanelCount,
156 -- Coef_SZ => Coef_SZ,
157 -- CoefCntPerCel => CoefCntPerCel,
158 -- Cels_count => Cels_count,
159 -- Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis
160 -- PORT MAP (
161 -- reset => rstn,
162 -- clk => clk,
163 -- sample_clk => sample_val_delay,
164 -- sample_in => sample_filter_in,
165 -- sample_out => sample_filter_out,
166 -- virg_pos => 7,
167 -- GOtest => OPEN,
168 -- coefs => coefs);
145
146 coefs_v2 <= CoefsInitValCst_v2;
169 147
170 148 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
171 149 GENERIC MAP (
172 150 tech => 0,
173 151 Mem_use => use_CEL,
174 152 Sample_SZ => 18,
175 153 Coef_SZ => Coef_SZ,
176 154 Coef_Nb => 25, -- TODO
177 155 Coef_sel_SZ => 5, -- TODO
178 156 Cels_count => Cels_count,
179 157 ChanelsCount => ChanelCount)
180 158 PORT MAP (
181 159 rstn => rstn,
182 160 clk => clk,
183 161 virg_pos => 7,
184 coefs => coefs_JC,
162 coefs => coefs_v2,
185 163 sample_in_val => sample_val_delay,
186 164 sample_in => sample_filter_in,
187 sample_out_val => sample_filter_JC_out_val,
188 sample_out => sample_filter_JC_out);
165 sample_out_val => sample_filter_v2_out_val,
166 sample_out => sample_filter_v2_out);
189 167
190 168 -----------------------------------------------------------------------------
191 169 PROCESS (clk, rstn)
192 170 BEGIN -- PROCESS
193 171 IF rstn = '0' THEN -- asynchronous reset (active low)
194 sample_filter_JC_out_r_val <= '0';
172 sample_filter_v2_out_r_val <= '0';
195 173 rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
196 174 rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
197 sample_filter_JC_out_r(I, J) <= '0';
175 sample_filter_v2_out_r(I, J) <= '0';
198 176 END LOOP rst_all_bits;
199 177 END LOOP rst_all_chanel;
200 178 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
201 sample_filter_JC_out_r_val <= sample_filter_JC_out_val;
202 IF sample_filter_JC_out_val = '1' THEN
203 sample_filter_JC_out_r <= sample_filter_JC_out;
179 sample_filter_v2_out_r_val <= sample_filter_v2_out_val;
180 IF sample_filter_v2_out_val = '1' THEN
181 sample_filter_v2_out_r <= sample_filter_v2_out;
204 182 END IF;
205 183 END IF;
206 184 END PROCESS;
207 185
208 186 -----------------------------------------------------------------------------
209 187 -- F0 -- @24.576 kHz
210 188 -----------------------------------------------------------------------------
211 189 Downsampling_f0 : Downsampling
212 190 GENERIC MAP (
213 191 ChanelCount => ChanelCount,
214 192 SampleSize => 18,
215 193 DivideParam => 4)
216 194 PORT MAP (
217 195 clk => clk,
218 196 rstn => rstn,
219 sample_in_val => sample_filter_JC_out_val ,
220 sample_in => sample_filter_JC_out,
197 sample_in_val => sample_filter_v2_out_val ,
198 sample_in => sample_filter_v2_out,
221 199 sample_out_val => sample_f0_val,
222 200 sample_out => sample_f0);
223 201
224 202 all_bit_sample_f0 : FOR I IN 17 DOWNTO 0 GENERATE
225 203 sample_f0_wdata(I) <= sample_f0(0, I);
226 204 sample_f0_wdata(18*1+I) <= sample_f0(1, I);
227 205 sample_f0_wdata(18*2+I) <= sample_f0(2, I);
228 206 sample_f0_wdata(18*3+I) <= sample_f0(6, I);
229 207 sample_f0_wdata(18*4+I) <= sample_f0(7, I);
230 208 END GENERATE all_bit_sample_f0;
231 209
232 210 PROCESS (clk, rstn)
233 211 BEGIN -- PROCESS
234 212 IF rstn = '0' THEN -- asynchronous reset (active low)
235 213 counter_f0 <= 0;
236 214 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
237 215 IF sample_f0_val = '1' THEN
238 216 IF counter_f0 = 511 THEN
239 217 counter_f0 <= 0;
240 218 ELSE
241 219 counter_f0 <= counter_f0 + 1;
242 220 END IF;
243 221 END IF;
244 222 END IF;
245 223 END PROCESS;
246 224
247 225 sample_f0_0_val <= sample_f0_val WHEN counter_f0 < 256 ELSE '0';
248 226 sample_f0_0_wen <= NOT(sample_f0_0_val) &
249 227 NOT(sample_f0_0_val) &
250 228 NOT(sample_f0_0_val) &
251 229 NOT(sample_f0_0_val) &
252 230 NOT(sample_f0_0_val);
253 231
254 232 sample_f0_1_val <= sample_f0_val WHEN counter_f0 > 255 ELSE '0';
255 233 sample_f0_1_wen <= NOT(sample_f0_1_val) &
256 234 NOT(sample_f0_1_val) &
257 235 NOT(sample_f0_1_val) &
258 236 NOT(sample_f0_1_val) &
259 237 NOT(sample_f0_1_val);
260 238
261 239
262 240 -----------------------------------------------------------------------------
263 241 -- F1 -- @4096 Hz
264 242 -----------------------------------------------------------------------------
265 243 Downsampling_f1 : Downsampling
266 244 GENERIC MAP (
267 245 ChanelCount => ChanelCount,
268 246 SampleSize => 18,
269 247 DivideParam => 6)
270 248 PORT MAP (
271 249 clk => clk,
272 250 rstn => rstn,
273 251 sample_in_val => sample_f0_val ,
274 252 sample_in => sample_f0,
275 253 sample_out_val => sample_f1_val,
276 254 sample_out => sample_f1);
277 255
278 256 sample_f1_wen <= NOT(sample_f1_val) &
279 257 NOT(sample_f1_val) &
280 258 NOT(sample_f1_val) &
281 259 NOT(sample_f1_val) &
282 260 NOT(sample_f1_val);
283 261
284 262 all_bit_sample_f1 : FOR I IN 17 DOWNTO 0 GENERATE
285 263 sample_f1_wdata(I) <= sample_f1(0, I);
286 264 sample_f1_wdata(18*1+I) <= sample_f1(1, I);
287 265 sample_f1_wdata(18*2+I) <= sample_f1(2, I);
288 266 sample_f1_wdata(18*3+I) <= sample_f1(6, I);
289 267 sample_f1_wdata(18*4+I) <= sample_f1(7, I);
290 268 END GENERATE all_bit_sample_f1;
291 269
292 270 -----------------------------------------------------------------------------
293 271 -- F2 -- @16 Hz
294 272 -----------------------------------------------------------------------------
295 273 Downsampling_f2 : Downsampling
296 274 GENERIC MAP (
297 275 ChanelCount => ChanelCount,
298 276 SampleSize => 18,
299 277 DivideParam => 256)
300 278 PORT MAP (
301 279 clk => clk,
302 280 rstn => rstn,
303 281 sample_in_val => sample_f1_val ,
304 282 sample_in => sample_f1,
305 283 sample_out_val => sample_f2_val,
306 284 sample_out => sample_f2);
307 285
308 286 sample_f2_wen <= NOT(sample_f2_val) &
309 287 NOT(sample_f2_val) &
310 288 NOT(sample_f2_val) &
311 289 NOT(sample_f2_val) &
312 290 NOT(sample_f2_val);
313 291
314 292 all_bit_sample_f2 : FOR I IN 17 DOWNTO 0 GENERATE
315 293 sample_f2_wdata(I) <= sample_f2(0, I);
316 294 sample_f2_wdata(18*1+I) <= sample_f2(1, I);
317 295 sample_f2_wdata(18*2+I) <= sample_f2(2, I);
318 296 sample_f2_wdata(18*3+I) <= sample_f2(6, I);
319 297 sample_f2_wdata(18*4+I) <= sample_f2(7, I);
320 298 END GENERATE all_bit_sample_f2;
321 299
322 300 -----------------------------------------------------------------------------
323 301 -- F3 -- @256 Hz
324 302 -----------------------------------------------------------------------------
325 303 Downsampling_f3 : Downsampling
326 304 GENERIC MAP (
327 305 ChanelCount => ChanelCount,
328 306 SampleSize => 18,
329 307 DivideParam => 96)
330 308 PORT MAP (
331 309 clk => clk,
332 310 rstn => rstn,
333 311 sample_in_val => sample_f0_val ,
334 312 sample_in => sample_f0,
335 313 sample_out_val => sample_f3_val,
336 314 sample_out => sample_f3);
337 315
338 316 sample_f3_wen <= (NOT sample_f3_val) &
339 317 (NOT sample_f3_val) &
340 318 (NOT sample_f3_val) &
341 319 (NOT sample_f3_val) &
342 320 (NOT sample_f3_val);
343 321
344 322 all_bit_sample_f3 : FOR I IN 17 DOWNTO 0 GENERATE
345 323 sample_f3_wdata(I) <= sample_f3(0, I);
346 324 sample_f3_wdata(18*1+I) <= sample_f3(1, I);
347 325 sample_f3_wdata(18*2+I) <= sample_f3(2, I);
348 326 sample_f3_wdata(18*3+I) <= sample_f3(6, I);
349 327 sample_f3_wdata(18*4+I) <= sample_f3(7, I);
350 328 END GENERATE all_bit_sample_f3;
351 329
352 330
353 331
354 332 END tb;
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@@ -1,36 +1,68
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 LIBRARY lpp;
4 4 USE lpp.lpp_ad_conv.ALL;
5 5 USE lpp.iir_filter.ALL;
6 6 USE lpp.FILTERcfg.ALL;
7 7 USE lpp.lpp_memory.ALL;
8 8 LIBRARY techmap;
9 9 USE techmap.gencomp.ALL;
10 10
11 11 PACKAGE lpp_top_lfr_pkg IS
12 12
13 13 COMPONENT lpp_top_acq
14 14 GENERIC (
15 15 tech : integer);
16 16 PORT (
17 17 cnv_run : IN STD_LOGIC;
18 18 cnv : OUT STD_LOGIC;
19 19 sck : OUT STD_LOGIC;
20 20 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
21 21 cnv_clk : IN STD_LOGIC;
22 22 cnv_rstn : IN STD_LOGIC;
23 23 clk : IN STD_LOGIC;
24 24 rstn : IN STD_LOGIC;
25 25 sample_f0_0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
26 26 sample_f0_1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
27 27 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
28 28 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
29 29 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
30 30 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 31 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
32 32 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 33 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0));
34 34 END COMPONENT;
35 35
36 COMPONENT lpp_top_apbreg
37 GENERIC (
38 pindex : INTEGER;
39 paddr : INTEGER;
40 pmask : INTEGER;
41 pirq : INTEGER);
42 PORT (
43 HCLK : IN STD_ULOGIC;
44 HRESETn : IN STD_ULOGIC;
45 apbi : IN apb_slv_in_type;
46 apbo : OUT apb_slv_out_type;
47 ready_matrix_f0_0 : IN STD_LOGIC;
48 ready_matrix_f0_1 : IN STD_LOGIC;
49 ready_matrix_f1 : IN STD_LOGIC;
50 ready_matrix_f2 : IN STD_LOGIC;
51 error_anticipating_empty_fifo : IN STD_LOGIC;
52 error_bad_component_error : IN STD_LOGIC;
53 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
54 status_ready_matrix_f0_0 : OUT STD_LOGIC;
55 status_ready_matrix_f0_1 : OUT STD_LOGIC;
56 status_ready_matrix_f1 : OUT STD_LOGIC;
57 status_ready_matrix_f2 : OUT STD_LOGIC;
58 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
59 status_error_bad_component_error : OUT STD_LOGIC;
60 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
61 config_active_interruption_onError : OUT STD_LOGIC;
62 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
65 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
66 END COMPONENT;
67
36 68 END lpp_top_lfr_pkg;
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@@ -1,2 +1,3
1 1 lpp_top_lfr_pkg.vhd
2 2 lpp_top_acq.vhd
3 lpp_top_lfr.vhd
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