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r336:d05a1ff29f0e (MINI-LFR) WFP_MS-0-1-9 JC
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_time_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 166 SIGNAL sample_val : STD_LOGIC;
167 167 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 168 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 169 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 170
171 171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 172
173 173 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 174 -----------------------------------------------------------------------------
175 175
176 176 BEGIN -- beh
177 177
178 178 -----------------------------------------------------------------------------
179 179 -- CLK
180 180 -----------------------------------------------------------------------------
181 181
182 182 PROCESS(clk_50)
183 183 BEGIN
184 184 IF clk_50'EVENT AND clk_50 = '1' THEN
185 185 clk_50_s <= NOT clk_50_s;
186 186 END IF;
187 187 END PROCESS;
188 188
189 189 PROCESS(clk_50_s)
190 190 BEGIN
191 191 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
192 192 clk_25 <= NOT clk_25;
193 193 END IF;
194 194 END PROCESS;
195 195
196 196 PROCESS(clk_49)
197 197 BEGIN
198 198 IF clk_49'EVENT AND clk_49 = '1' THEN
199 199 clk_24 <= NOT clk_24;
200 200 END IF;
201 201 END PROCESS;
202 202
203 203 -----------------------------------------------------------------------------
204 204
205 205 PROCESS (clk_25, reset)
206 206 BEGIN -- PROCESS
207 207 IF reset = '0' THEN -- asynchronous reset (active low)
208 208 LED0 <= '0';
209 209 LED1 <= '0';
210 210 LED2 <= '0';
211 211 --IO1 <= '0';
212 212 --IO2 <= '1';
213 213 --IO3 <= '0';
214 214 --IO4 <= '0';
215 215 --IO5 <= '0';
216 216 --IO6 <= '0';
217 217 --IO7 <= '0';
218 218 --IO8 <= '0';
219 219 --IO9 <= '0';
220 220 --IO10 <= '0';
221 221 --IO11 <= '0';
222 222 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
223 223 LED0 <= '0';
224 224 LED1 <= '1';
225 225 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
226 226 --IO1 <= '1';
227 227 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
228 228 --IO3 <= ADC_SDO(0);
229 229 --IO4 <= ADC_SDO(1);
230 230 --IO5 <= ADC_SDO(2);
231 231 --IO6 <= ADC_SDO(3);
232 232 --IO7 <= ADC_SDO(4);
233 233 --IO8 <= ADC_SDO(5);
234 234 --IO9 <= ADC_SDO(6);
235 235 --IO10 <= ADC_SDO(7);
236 236 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
237 237 END IF;
238 238 END PROCESS;
239 239
240 240 PROCESS (clk_24, reset)
241 241 BEGIN -- PROCESS
242 242 IF reset = '0' THEN -- asynchronous reset (active low)
243 243 I00_s <= '0';
244 244 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
245 245 I00_s <= NOT I00_s ;
246 246 END IF;
247 247 END PROCESS;
248 248 -- IO0 <= I00_s;
249 249
250 250 --UARTs
251 251 nCTS1 <= '1';
252 252 nCTS2 <= '1';
253 253 nDCD2 <= '1';
254 254
255 255 --EXT CONNECTOR
256 256
257 257 --SPACE WIRE
258 258
259 259 leon3_soc_1 : leon3_soc
260 260 GENERIC MAP (
261 261 fabtech => apa3e,
262 262 memtech => apa3e,
263 263 padtech => inferred,
264 264 clktech => inferred,
265 265 disas => 0,
266 266 dbguart => 0,
267 267 pclow => 2,
268 268 clk_freq => 25000,
269 269 NB_CPU => 1,
270 270 ENABLE_FPU => 1,
271 271 FPU_NETLIST => 0,
272 272 ENABLE_DSU => 1,
273 273 ENABLE_AHB_UART => 1,
274 274 ENABLE_APB_UART => 1,
275 275 ENABLE_IRQMP => 1,
276 276 ENABLE_GPT => 1,
277 277 NB_AHB_MASTER => NB_AHB_MASTER,
278 278 NB_AHB_SLAVE => NB_AHB_SLAVE,
279 279 NB_APB_SLAVE => NB_APB_SLAVE)
280 280 PORT MAP (
281 281 clk => clk_25,
282 282 reset => reset,
283 283 errorn => errorn,
284 284 ahbrxd => TXD1,
285 285 ahbtxd => RXD1,
286 286 urxd1 => TXD2,
287 287 utxd1 => RXD2,
288 288 address => SRAM_A,
289 289 data => SRAM_DQ,
290 290 nSRAM_BE0 => SRAM_nBE(0),
291 291 nSRAM_BE1 => SRAM_nBE(1),
292 292 nSRAM_BE2 => SRAM_nBE(2),
293 293 nSRAM_BE3 => SRAM_nBE(3),
294 294 nSRAM_WE => SRAM_nWE,
295 295 nSRAM_CE => SRAM_CE,
296 296 nSRAM_OE => SRAM_nOE,
297 297
298 298 apbi_ext => apbi_ext,
299 299 apbo_ext => apbo_ext,
300 300 ahbi_s_ext => ahbi_s_ext,
301 301 ahbo_s_ext => ahbo_s_ext,
302 302 ahbi_m_ext => ahbi_m_ext,
303 303 ahbo_m_ext => ahbo_m_ext);
304 304
305 305 -------------------------------------------------------------------------------
306 306 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
307 307 -------------------------------------------------------------------------------
308 308 apb_lfr_time_management_1 : apb_lfr_time_management
309 309 GENERIC MAP (
310 310 pindex => 6,
311 311 paddr => 6,
312 312 pmask => 16#fff#,
313 313 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
314 314 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
315 315 PORT MAP (
316 316 clk25MHz => clk_25,
317 317 clk24_576MHz => clk_24, -- 49.152MHz/2
318 318 resetn => reset,
319 319 grspw_tick => swno.tickout,
320 320 apbi => apbi_ext,
321 321 apbo => apbo_ext(6),
322 322 coarse_time => coarse_time,
323 323 fine_time => fine_time);
324 324
325 325 -----------------------------------------------------------------------
326 326 --- SpaceWire --------------------------------------------------------
327 327 -----------------------------------------------------------------------
328 328
329 329 SPW_EN <= '1';
330 330
331 331 spw_clk <= clk_50_s;
332 332 spw_rxtxclk <= spw_clk;
333 333 spw_rxclkn <= NOT spw_rxtxclk;
334 334
335 335 -- PADS for SPW1
336 336 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
337 337 PORT MAP (SPW_NOM_DIN, dtmp(0));
338 338 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
339 339 PORT MAP (SPW_NOM_SIN, stmp(0));
340 340 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
341 341 PORT MAP (SPW_NOM_DOUT, swno.d(0));
342 342 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
343 343 PORT MAP (SPW_NOM_SOUT, swno.s(0));
344 344 -- PADS FOR SPW2
345 345 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
346 346 PORT MAP (SPW_RED_SIN, dtmp(1));
347 347 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
348 348 PORT MAP (SPW_RED_DIN, stmp(1));
349 349 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
350 350 PORT MAP (SPW_RED_DOUT, swno.d(1));
351 351 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
352 352 PORT MAP (SPW_RED_SOUT, swno.s(1));
353 353
354 354 -- GRSPW PHY
355 355 --spw1_input: if CFG_SPW_GRSPW = 1 generate
356 356 spw_inputloop : FOR j IN 0 TO 1 GENERATE
357 357 spw_phy0 : grspw_phy
358 358 GENERIC MAP(
359 359 tech => apa3e,
360 360 rxclkbuftype => 1,
361 361 scantest => 0)
362 362 PORT MAP(
363 363 rxrst => swno.rxrst,
364 364 di => dtmp(j),
365 365 si => stmp(j),
366 366 rxclko => spw_rxclk(j),
367 367 do => swni.d(j),
368 368 ndo => swni.nd(j*5+4 DOWNTO j*5),
369 369 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
370 370 END GENERATE spw_inputloop;
371 371
372 372 -- SPW core
373 373 sw0 : grspwm GENERIC MAP(
374 374 tech => apa3e,
375 375 hindex => 1,
376 376 pindex => 5,
377 377 paddr => 5,
378 378 pirq => 11,
379 379 sysfreq => 25000, -- CPU_FREQ
380 380 rmap => 1,
381 381 rmapcrc => 1,
382 382 fifosize1 => 16,
383 383 fifosize2 => 16,
384 384 rxclkbuftype => 1,
385 385 rxunaligned => 0,
386 386 rmapbufs => 4,
387 387 ft => 0,
388 388 netlist => 0,
389 389 ports => 2,
390 390 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
391 391 memtech => apa3e,
392 392 destkey => 2,
393 393 spwcore => 1
394 394 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
395 395 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
396 396 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
397 397 )
398 398 PORT MAP(reset, clk_25, spw_rxclk(0),
399 399 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
400 400 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
401 401 swni, swno);
402 402
403 403 swni.tickin <= '0';
404 404 swni.rmapen <= '1';
405 405 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
406 406 swni.tickinraw <= '0';
407 407 swni.timein <= (OTHERS => '0');
408 408 swni.dcrstval <= (OTHERS => '0');
409 409 swni.timerrstval <= (OTHERS => '0');
410 410
411 411 -------------------------------------------------------------------------------
412 412 -- LFR ------------------------------------------------------------------------
413 413 -------------------------------------------------------------------------------
414 414 lpp_lfr_1 : lpp_lfr
415 415 GENERIC MAP (
416 416 Mem_use => use_RAM,
417 417 nb_data_by_buffer_size => 32,
418 418 nb_word_by_buffer_size => 30,
419 419 nb_snapshot_param_size => 32,
420 420 delta_vector_size => 32,
421 421 delta_vector_size_f0_2 => 7, -- log2(96)
422 422 pindex => 15,
423 423 paddr => 15,
424 424 pmask => 16#fff#,
425 425 pirq_ms => 6,
426 426 pirq_wfp => 14,
427 427 hindex => 2,
428 top_lfr_version => X"000107") -- aa.bb.cc version
428 top_lfr_version => X"000109") -- aa.bb.cc version
429 429 PORT MAP (
430 430 clk => clk_25,
431 431 rstn => reset,
432 432 sample_B => sample(2 DOWNTO 0),
433 433 sample_E => sample(7 DOWNTO 3),
434 434 sample_val => sample_val,
435 435 apbi => apbi_ext,
436 436 apbo => apbo_ext(15),
437 437 ahbi => ahbi_m_ext,
438 438 ahbo => ahbo_m_ext(2),
439 439 coarse_time => coarse_time,
440 440 fine_time => fine_time,
441 441 data_shaping_BW => bias_fail_sw_sig,
442 442 observation_reg => observation_reg);
443 443
444 444 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
445 445 GENERIC MAP(
446 446 ChannelCount => 8,
447 447 SampleNbBits => 14,
448 448 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
449 449 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
450 450 PORT MAP (
451 451 -- CONV
452 452 cnv_clk => clk_24,
453 453 cnv_rstn => reset,
454 454 cnv => ADC_nCS_sig,
455 455 -- DATA
456 456 clk => clk_25,
457 457 rstn => reset,
458 458 sck => ADC_CLK_sig,
459 459 sdo => ADC_SDO_sig,
460 460 -- SAMPLE
461 461 sample => sample,
462 462 sample_val => sample_val);
463 463
464 464 --IO10 <= ADC_SDO_sig(5);
465 465 --IO9 <= ADC_SDO_sig(4);
466 466 --IO8 <= ADC_SDO_sig(3);
467 467
468 468 ADC_nCS <= ADC_nCS_sig;
469 469 ADC_CLK <= ADC_CLK_sig;
470 470 ADC_SDO_sig <= ADC_SDO;
471 471
472 472 ----------------------------------------------------------------------
473 473 --- GPIO -----------------------------------------------------------
474 474 ----------------------------------------------------------------------
475 475
476 476 grgpio0 : grgpio
477 477 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
478 478 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
479 479
480 480 --pio_pad_0 : iopad
481 481 -- GENERIC MAP (tech => CFG_PADTECH)
482 482 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
483 483 --pio_pad_1 : iopad
484 484 -- GENERIC MAP (tech => CFG_PADTECH)
485 485 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
486 486 --pio_pad_2 : iopad
487 487 -- GENERIC MAP (tech => CFG_PADTECH)
488 488 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
489 489 --pio_pad_3 : iopad
490 490 -- GENERIC MAP (tech => CFG_PADTECH)
491 491 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
492 492 --pio_pad_4 : iopad
493 493 -- GENERIC MAP (tech => CFG_PADTECH)
494 494 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
495 495 --pio_pad_5 : iopad
496 496 -- GENERIC MAP (tech => CFG_PADTECH)
497 497 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
498 498 --pio_pad_6 : iopad
499 499 -- GENERIC MAP (tech => CFG_PADTECH)
500 500 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
501 501 --pio_pad_7 : iopad
502 502 -- GENERIC MAP (tech => CFG_PADTECH)
503 503 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
504 504
505 505 PROCESS (clk_25, reset)
506 506 BEGIN -- PROCESS
507 507 IF reset = '0' THEN -- asynchronous reset (active low)
508 508 IO0 <= '0';
509 509 IO1 <= '0';
510 510 IO2 <= '0';
511 511 IO3 <= '0';
512 512 IO4 <= '0';
513 513 IO5 <= '0';
514 514 IO6 <= '0';
515 515 IO7 <= '0';
516 516 IO8 <= '0';
517 517 IO9 <= '0';
518 518 IO10 <= '0';
519 519 IO11 <= '0';
520 520 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
521 521 CASE gpioo.dout(1 DOWNTO 0) IS
522 522 WHEN "00" =>
523 523 IO0 <= observation_reg(0 );
524 524 IO1 <= observation_reg(1 );
525 525 IO2 <= observation_reg(2 );
526 526 IO3 <= observation_reg(3 );
527 527 IO4 <= observation_reg(4 );
528 528 IO5 <= observation_reg(5 );
529 529 IO6 <= observation_reg(6 );
530 530 IO7 <= observation_reg(7 );
531 531 IO8 <= observation_reg(8 );
532 532 IO9 <= observation_reg(9 );
533 533 IO10 <= observation_reg(10);
534 534 IO11 <= observation_reg(11);
535 535 WHEN "01" =>
536 536 IO0 <= observation_reg(0 + 12);
537 537 IO1 <= observation_reg(1 + 12);
538 538 IO2 <= observation_reg(2 + 12);
539 539 IO3 <= observation_reg(3 + 12);
540 540 IO4 <= observation_reg(4 + 12);
541 541 IO5 <= observation_reg(5 + 12);
542 542 IO6 <= observation_reg(6 + 12);
543 543 IO7 <= observation_reg(7 + 12);
544 544 IO8 <= observation_reg(8 + 12);
545 545 IO9 <= observation_reg(9 + 12);
546 546 IO10 <= observation_reg(10 + 12);
547 547 IO11 <= observation_reg(11 + 12);
548 548 WHEN "10" =>
549 549 IO0 <= observation_reg(0 + 12 + 12);
550 550 IO1 <= observation_reg(1 + 12 + 12);
551 551 IO2 <= observation_reg(2 + 12 + 12);
552 552 IO3 <= observation_reg(3 + 12 + 12);
553 553 IO4 <= observation_reg(4 + 12 + 12);
554 554 IO5 <= observation_reg(5 + 12 + 12);
555 555 IO6 <= observation_reg(6 + 12 + 12);
556 556 IO7 <= observation_reg(7 + 12 + 12);
557 557 IO8 <= '0';
558 558 IO9 <= '0';
559 559 IO10 <= '0';
560 560 IO11 <= '0';
561 561 WHEN "11" =>
562 562 IO0 <= '0';
563 563 IO1 <= '0';
564 564 IO2 <= '0';
565 565 IO3 <= '0';
566 566 IO4 <= '0';
567 567 IO5 <= '0';
568 568 IO6 <= '0';
569 569 IO7 <= '0';
570 570 IO8 <= '0';
571 571 IO9 <= '0';
572 572 IO10 <= '0';
573 573 IO11 <= '0';
574 574 WHEN OTHERS => NULL;
575 575 END CASE;
576 576
577 577 END IF;
578 578 END PROCESS;
579 579
580 580 END beh; No newline at end of file
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@@ -1,292 +1,352
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22
23 23 LIBRARY IEEE;
24 24 USE IEEE.STD_LOGIC_1164.ALL;
25 25 USE IEEE.NUMERIC_STD.ALL;
26 26
27 27 LIBRARY grlib;
28 28 USE grlib.amba.ALL;
29 29 USE grlib.stdlib.ALL;
30 30 USE grlib.devices.ALL;
31 31
32 32 LIBRARY lpp;
33 33 USE lpp.lpp_lfr_time_management.ALL;
34 34
35 35 ENTITY TB IS
36 36
37 37 PORT (
38 38 SIM_OK : OUT STD_LOGIC
39 39 );
40 40
41 41 END TB;
42 42
43 43
44 44 ARCHITECTURE beh OF TB IS
45 45
46 46 SIGNAL clk25MHz : STD_LOGIC := '0';
47 47 SIGNAL clk24_576MHz : STD_LOGIC := '0';
48 48 SIGNAL resetn : STD_LOGIC;
49 49 SIGNAL grspw_tick : STD_LOGIC;
50 50 SIGNAL apbi : apb_slv_in_type;
51 51 SIGNAL apbo : apb_slv_out_type;
52 52 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
53 53 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
54 54
55 55 SIGNAL TB_string : STRING(1 TO 8):= "12345678";
56 56
57 57 SIGNAL coarse_time_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
58 58 SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
59 59 SIGNAL global_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
60 60 SIGNAL global_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
61 61 SIGNAL tick_ongoing : STD_LOGIC;
62 62
63 63 SIGNAL ASSERTION_1 : STD_LOGIC;
64 64 SIGNAL ASSERTION_2 : STD_LOGIC;
65 65 SIGNAL ASSERTION_3 : STD_LOGIC;
66 66
67 67 BEGIN -- beh
68 68
69 69 apb_lfr_time_management_1: apb_lfr_time_management
70 70 GENERIC MAP (
71 71 pindex => 0,
72 72 paddr => 0,
73 73 pmask => 16#fff#,
74 74 FIRST_DIVISION => 20,
75 75 NB_SECOND_DESYNC => 4)
76 76 PORT MAP (
77 77 clk25MHz => clk25MHz,
78 78 clk24_576MHz => clk24_576MHz,
79 79 resetn => resetn,
80 80 grspw_tick => grspw_tick,
81 81 apbi => apbi,
82 82 apbo => apbo,
83 83 coarse_time => coarse_time,
84 84 fine_time => fine_time);
85 85
86 86 clk25MHz <= NOT clk25MHz AFTER 20000 ps;
87 87 clk24_576MHz <= NOT clk24_576MHz AFTER 20345 ps;
88 88
89 89
90 90
91 91
92 92 PROCESS
93 93 BEGIN -- PROCESS
94 94 WAIT UNTIL clk25MHz = '1';
95 95 TB_string <= "RESET ";
96 96
97 97 resetn <= '0';
98 98
99 99 apbi.psel(0) <= '0';
100 100 apbi.pwrite <= '0';
101 101 apbi.penable <= '0';
102 102 apbi.paddr <= (OTHERS => '0');
103 103 apbi.pwdata <= (OTHERS => '0');
104 104 grspw_tick <= '0';
105 105 WAIT UNTIL clk25MHz = '1';
106 106 WAIT UNTIL clk25MHz = '1';
107 107 resetn <= '1';
108 108 WAIT FOR 60 ms;
109 109 ---------------------------------------------------------------------------
110 110 -- DESYNC TO SYNC
111 111 ---------------------------------------------------------------------------
112 112 WAIT UNTIL clk25MHz = '1';
113 113 TB_string <= "TICK 1 ";
114 114 grspw_tick <= '1';------------------------------------------------------1
115 115 WAIT UNTIL clk25MHz = '1';
116 116 grspw_tick <= '0';
117 117 WAIT FOR 53333 us;
118 118 WAIT UNTIL clk25MHz = '1';
119 119 TB_string <= "TICK 2 ";
120 120 grspw_tick <= '1';------------------------------------------------------2
121 121 WAIT UNTIL clk25MHz = '1';
122 122 grspw_tick <= '0';
123 123 WAIT FOR 56000 us;
124 124 WAIT UNTIL clk25MHz = '1';
125 125 TB_string <= "TICK 3 ";
126 126 grspw_tick <= '1';------------------------------------------------------3
127 127 WAIT UNTIL clk25MHz = '1';
128 128 grspw_tick <= '0';
129 129 WAIT FOR 200 ms;
130 130 WAIT UNTIL clk25MHz = '1';
131 131 TB_string <= "CT new ";
132 132 -- WRITE NEW COARSE_TIME
133 133 apbi.psel(0) <= '1';
134 134 apbi.pwrite <= '1';
135 135 apbi.penable <= '1';
136 136 apbi.paddr <= X"00000004";
137 137 apbi.pwdata <= X"00001234";
138 138 WAIT UNTIL clk25MHz = '1';
139 139 apbi.psel(0) <= '0';
140 140 apbi.pwrite <= '0';
141 141 apbi.penable <= '0';
142 142 apbi.paddr <= (OTHERS => '0');
143 143 apbi.pwdata <= (OTHERS => '0');
144 144 WAIT UNTIL clk25MHz = '1';
145 145
146 146 WAIT FOR 10 ms;
147 147 WAIT UNTIL clk25MHz = '1';
148 148 TB_string <= "TICK 4 ";
149 149 grspw_tick <= '1';------------------------------------------------------3
150 150 WAIT UNTIL clk25MHz = '1';
151 151 grspw_tick <= '0';
152
153
154 WAIT FOR 250 ms;
155 WAIT UNTIL clk25MHz = '1';
156 TB_string <= "CT new ";
157 -- WRITE NEW COARSE_TIME
158 apbi.psel(0) <= '1';
159 apbi.pwrite <= '1';
160 apbi.penable <= '1';
161 apbi.paddr <= X"00000004";
162 apbi.pwdata <= X"80005678";
163 WAIT UNTIL clk25MHz = '1';
164 apbi.psel(0) <= '0';
165 apbi.pwrite <= '0';
166 apbi.penable <= '0';
167 apbi.paddr <= (OTHERS => '0');
168 apbi.pwdata <= (OTHERS => '0');
169 WAIT UNTIL clk25MHz = '1';
170
171 WAIT FOR 10 ms;
172 WAIT UNTIL clk25MHz = '1';
173 TB_string <= "TICK 5 ";
174 grspw_tick <= '1';------------------------------------------------------3
175 WAIT UNTIL clk25MHz = '1';
176 grspw_tick <= '0';
177
178
179 WAIT FOR 20 ms;
180 WAIT UNTIL clk25MHz = '1';
181 TB_string <= "CT new ";
182 -- WRITE NEW COARSE_TIME
183 apbi.psel(0) <= '1';
184 apbi.pwrite <= '1';
185 apbi.penable <= '1';
186 apbi.paddr <= X"00000004";
187 apbi.pwdata <= X"00005678";
188 WAIT UNTIL clk25MHz = '1';
189 apbi.psel(0) <= '0';
190 apbi.pwrite <= '0';
191 apbi.penable <= '0';
192 apbi.paddr <= (OTHERS => '0');
193 apbi.pwdata <= (OTHERS => '0');
194 WAIT UNTIL clk25MHz = '1';
195
196 WAIT FOR 25 ms;
197 WAIT UNTIL clk25MHz = '1';
198 TB_string <= "Soft RST";
199 -- WRITE SOFT RESET
200 apbi.psel(0) <= '1';
201 apbi.pwrite <= '1';
202 apbi.penable <= '1';
203 apbi.paddr <= X"00000000";
204 apbi.pwdata <= X"00000002";
205 WAIT UNTIL clk25MHz = '1';
206 apbi.psel(0) <= '0';
207 apbi.pwrite <= '0';
208 apbi.penable <= '0';
209 apbi.paddr <= (OTHERS => '0');
210 apbi.pwdata <= (OTHERS => '0');
211 WAIT UNTIL clk25MHz = '1';
152 212
153 213 WAIT FOR 250 ms;
154 214 TB_string <= "READ 1 ";
155 215 apbi.psel(0) <= '1';
156 216 apbi.pwrite <= '0';
157 217 apbi.penable <= '1';
158 218 apbi.paddr <= X"00000008";
159 219 WAIT UNTIL clk25MHz = '1';
160 220 apbi.psel(0) <= '0';
161 221 apbi.pwrite <= '0';
162 222 apbi.penable <= '0';
163 223 apbi.paddr <= (OTHERS => '0');
164 224 WAIT UNTIL clk25MHz = '1';
165 225 WAIT FOR 250 ms;
166 226 TB_string <= "READ 2 ";
167 227 apbi.psel(0) <= '1';
168 228 apbi.pwrite <= '0';
169 229 apbi.penable <= '1';
170 230 apbi.paddr <= X"00000008";
171 231 WAIT UNTIL clk25MHz = '1';
172 232 apbi.psel(0) <= '0';
173 233 apbi.pwrite <= '0';
174 234 apbi.penable <= '0';
175 235 apbi.paddr <= (OTHERS => '0');
176 236 WAIT UNTIL clk25MHz = '1';
177 237 WAIT FOR 250 ms;
178 238 TB_string <= "READ 3 ";
179 239 apbi.psel(0) <= '1';
180 240 apbi.pwrite <= '0';
181 241 apbi.penable <= '1';
182 242 apbi.paddr <= X"00000008";
183 243 WAIT UNTIL clk25MHz = '1';
184 244 apbi.psel(0) <= '0';
185 245 apbi.pwrite <= '0';
186 246 apbi.penable <= '0';
187 247 apbi.paddr <= (OTHERS => '0');
188 248 WAIT UNTIL clk25MHz = '1';
189 249
190 250
191 251
192 252 REPORT "*** END simulation ***" SEVERITY failure;
193 253 WAIT;
194 254
195 255 END PROCESS;
196 256
197 257
198 258 -----------------------------------------------------------------------------
199 259 --
200 260 -----------------------------------------------------------------------------
201 261
202 262 global_time <= coarse_time & fine_time;
203 263
204 264 PROCESS (clk25MHz, resetn)
205 265 BEGIN -- PROCESS
206 266 IF resetn = '0' THEN -- asynchronous reset (active low)
207 267 coarse_time_reg <= (OTHERS => '0');
208 268 fine_time_reg <= (OTHERS => '0');
209 269 global_time_reg <= (OTHERS => '0');
210 270 tick_ongoing <= '0';
211 271 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
212 272 global_time_reg <= global_time;
213 273 coarse_time_reg <= coarse_time;
214 274 fine_time_reg <= fine_time;
215 275 IF grspw_tick ='1' THEN
216 276 tick_ongoing <= '1';
217 277 ELSIF tick_ongoing = '1' THEN
218 278 IF (fine_time_reg /= fine_time) OR (coarse_time_reg /= coarse_time) THEN
219 279 tick_ongoing <= '0';
220 280 END IF;
221 281 END IF;
222 282
223 283 END IF;
224 284 END PROCESS;
225 285
226 286 -----------------------------------------------------------------------------
227 287 -- ASSERTION 1 :
228 288 -- Coarse_time "changed" => FINE_TIME = 0
229 289 -- False after a TRANSITION !
230 290 -----------------------------------------------------------------------------
231 291 PROCESS (clk25MHz, resetn)
232 292 BEGIN -- PROCESS
233 293 IF resetn = '0' THEN -- asynchronous reset (active low)
234 294 ASSERTION_1 <= '1';
235 295 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
236 296 IF coarse_time /= coarse_time_reg THEN
237 297 IF fine_time /= X"0000" THEN
238 298 IF fine_time /= X"0041" THEN
239 299 ASSERTION_1 <= '0';
240 300 ELSE
241 301 ASSERTION_1 <= 'U';
242 302 END IF;
243 303 ELSE
244 304 ASSERTION_1 <= '1';
245 305 END IF;
246 306 END IF;
247 307 END IF;
248 308 END PROCESS;
249 309
250 310 -----------------------------------------------------------------------------
251 311 -- ASSERTION 2 :
252 312 -- tick => next(FINE_TIME) = 0
253 313 -----------------------------------------------------------------------------
254 314 PROCESS (clk25MHz, resetn)
255 315 BEGIN -- PROCESS
256 316 IF resetn = '0' THEN -- asynchronous reset (active low)
257 317 ASSERTION_2 <= '1';
258 318 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
259 319 IF tick_ongoing = '1' THEN
260 320 IF fine_time_reg /= fine_time OR coarse_time_reg /= coarse_time THEN
261 321 IF fine_time /= X"0000" THEN
262 322 ASSERTION_2 <= '0';
263 323 END IF;
264 324 END IF;
265 325 END IF;
266 326 END IF;
267 327 END PROCESS;
268 328
269 329 -----------------------------------------------------------------------------
270 330 -- ASSERTION 3 :
271 331 -- next(TIME) > TIME
272 332 -- false if resynchro, or new coarse_time
273 333 -----------------------------------------------------------------------------
274 334 PROCESS (clk25MHz, resetn)
275 335 BEGIN -- PROCESS
276 336 IF resetn = '0' THEN -- asynchronous reset (active low)
277 337 ASSERTION_3 <= '1';
278 338 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
279 339 ASSERTION_3 <= '1';
280 340 IF global_time_reg(46 DOWNTO 0) > global_time(46 DOWNTO 0) THEN
281 341 IF global_time(47) = '0' AND global_time_reg(47) = '1' THEN
282 342 ASSERTION_3 <= 'U'; -- RESYNCHRO ....
283 343 ELSE
284 344 ASSERTION_3 <= '0';
285 345 END IF;
286 346 END IF;
287 347 END IF;
288 348 END PROCESS;
289 349
290 350
291 351 END beh;
292 352
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@@ -1,276 +1,317
1 1 ----------------------------------------------------------------------------------
2 2 -- Company:
3 3 -- Engineer:
4 4 --
5 5 -- Create Date: 11:17:05 07/02/2012
6 6 -- Design Name:
7 7 -- Module Name: apb_lfr_time_management - Behavioral
8 8 -- Project Name:
9 9 -- Target Devices:
10 10 -- Tool versions:
11 11 -- Description:
12 12 --
13 13 -- Dependencies:
14 14 --
15 15 -- Revision:
16 16 -- Revision 0.01 - File Created
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 20 LIBRARY IEEE;
21 21 USE IEEE.STD_LOGIC_1164.ALL;
22 22 USE IEEE.NUMERIC_STD.ALL;
23 23 LIBRARY grlib;
24 24 USE grlib.amba.ALL;
25 25 USE grlib.stdlib.ALL;
26 26 USE grlib.devices.ALL;
27 27 LIBRARY lpp;
28 28 USE lpp.apb_devices_list.ALL;
29 29 USE lpp.general_purpose.ALL;
30 30 USE lpp.lpp_lfr_time_management.ALL;
31 31
32 32 ENTITY apb_lfr_time_management IS
33 33
34 34 GENERIC(
35 35 pindex : INTEGER := 0; --! APB slave index
36 36 paddr : INTEGER := 0; --! ADDR field of the APB BAR
37 37 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
38 38 FIRST_DIVISION : INTEGER := 374;
39 39 NB_SECOND_DESYNC : INTEGER := 60
40 40 );
41 41
42 42 PORT (
43 43 clk25MHz : IN STD_LOGIC; --! Clock
44 44 clk24_576MHz : IN STD_LOGIC; --! secondary clock
45 45 resetn : IN STD_LOGIC; --! Reset
46 46
47 47 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
48 48
49 49 apbi : IN apb_slv_in_type; --! APB slave input signals
50 50 apbo : OUT apb_slv_out_type; --! APB slave output signals
51 51
52 52 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
53 53 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
54 54 );
55 55
56 56 END apb_lfr_time_management;
57 57
58 58 ARCHITECTURE Behavioral OF apb_lfr_time_management IS
59 59
60 60 CONSTANT REVISION : INTEGER := 1;
61 61 CONSTANT pconfig : apb_config_type := (
62 62 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, 0),
63 63 1 => apb_iobar(paddr, pmask)
64 64 );
65 65
66 66 TYPE apb_lfr_time_management_Reg IS RECORD
67 67 ctrl : STD_LOGIC;
68 coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
68 soft_reset : STD_LOGIC;
69 coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0);
69 70 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
70 71 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
71 72 END RECORD;
72 73 SIGNAL r : apb_lfr_time_management_Reg;
73 74
74 75 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
75 76 SIGNAL force_tick : STD_LOGIC;
76 77 SIGNAL previous_force_tick : STD_LOGIC;
77 78 SIGNAL soft_tick : STD_LOGIC;
78 79
79 80 SIGNAL coarsetime_reg_updated : STD_LOGIC;
80 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
81 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0);
81 82
82 83 --SIGNAL coarse_time_new : STD_LOGIC;
83 84 SIGNAL coarse_time_new_49 : STD_LOGIC;
84 85 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 86 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
86 87
87 88 --SIGNAL fine_time_new : STD_LOGIC;
88 89 --SIGNAL fine_time_new_temp : STD_LOGIC;
89 90 SIGNAL fine_time_new_49 : STD_LOGIC;
90 91 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
91 92 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
92 93 SIGNAL tick : STD_LOGIC;
93 94 SIGNAL new_timecode : STD_LOGIC;
94 95 SIGNAL new_coarsetime : STD_LOGIC;
95 96
96 97 SIGNAL time_new_49 : STD_LOGIC;
97 98 SIGNAL time_new : STD_LOGIC;
99
100 -----------------------------------------------------------------------------
101 SIGNAL force_reset : STD_LOGIC;
102 SIGNAL previous_force_reset : STD_LOGIC;
103 SIGNAL soft_reset : STD_LOGIC;
104 SIGNAL soft_reset_sync : STD_LOGIC;
105 -----------------------------------------------------------------------------
106
107 SIGNAL rstn_LFR_TM : STD_LOGIC;
98 108
99 109 BEGIN
100 110
101 111 PROCESS(resetn, clk25MHz)
102 112 BEGIN
103 113
104 114 IF resetn = '0' THEN
105 115 Rdata <= (OTHERS => '0');
106 r.coarse_time_load <= x"80000000";
116 r.coarse_time_load <= (OTHERS => '0');
117 r.soft_reset <= '0';
107 118 r.ctrl <= '0';
108 119 force_tick <= '0';
109 120 previous_force_tick <= '0';
110 121 soft_tick <= '0';
111 122
112 123 coarsetime_reg_updated <= '0';
113 124
114 125 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
115 126 coarsetime_reg_updated <= '0';
116 127
117 128 force_tick <= r.ctrl;
118 129 previous_force_tick <= force_tick;
119 130 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
120 131 soft_tick <= '1';
121 132 ELSE
122 133 soft_tick <= '0';
123 134 END IF;
135
136 force_reset <= r.soft_reset;
137 previous_force_reset <= force_reset;
138 IF (previous_force_reset = '0') AND (force_reset = '1') THEN
139 soft_reset <= '1';
140 ELSE
141 soft_reset <= '0';
142 END IF;
124 143
125 144 --APB Write OP
126 145 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
127 146 CASE apbi.paddr(7 DOWNTO 2) IS
128 147 WHEN "000000" =>
129 r.ctrl <= apbi.pwdata(0);
148 r.ctrl <= apbi.pwdata(0);
149 r.soft_reset <= apbi.pwdata(1);
130 150 WHEN "000001" =>
131 r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0);
151 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
132 152 coarsetime_reg_updated <= '1';
133 153 WHEN OTHERS =>
134 154 NULL;
135 155 END CASE;
136 ELSIF r.ctrl = '1' THEN
137 r.ctrl <= '0';
156 ELSE
157 IF r.ctrl = '1' THEN
158 r.ctrl <= '0';
159 END if;
160 IF r.soft_reset = '1' THEN
161 r.soft_reset <= '0';
162 END if;
138 163 END IF;
139 164
140 165 --APB READ OP
141 166 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
142 167 CASE apbi.paddr(7 DOWNTO 2) IS
143 168 WHEN "000000" =>
144 169 Rdata(0) <= r.ctrl;
170 Rdata(1) <= r.soft_reset;
145 171 Rdata(31 DOWNTO 1) <= (others => '0');
146 172 WHEN "000001" =>
147 Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0);
173 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
148 174 WHEN "000010" =>
149 175 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
150 176 WHEN "000011" =>
151 177 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
152 178 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
153 179 WHEN OTHERS =>
154 180 Rdata(31 DOWNTO 0) <= (others => '0');
155 181 END CASE;
156 182 END IF;
157 183
158 184 END IF;
159 185 END PROCESS;
160 186
161 187 apbo.prdata <= Rdata;
162 188 apbo.pconfig <= pconfig;
163 189 apbo.pindex <= pindex;
164 190
165 191 -----------------------------------------------------------------------------
166 192 -- IN
167 193 coarse_time <= r.coarse_time;
168 194 fine_time <= r.fine_time;
169 195 coarsetime_reg <= r.coarse_time_load;
170 196 -----------------------------------------------------------------------------
171 197
172 198 -----------------------------------------------------------------------------
173 199 -- OUT
174 200 r.coarse_time <= coarse_time_s;
175 201 r.fine_time <= fine_time_s;
176 202 -----------------------------------------------------------------------------
177 203
178 204 -----------------------------------------------------------------------------
179 205 tick <= grspw_tick OR soft_tick;
180 206
181 207 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
182 208 GENERIC MAP (
183 209 NB_FF_OF_SYNC => 2)
184 210 PORT MAP (
185 211 clk_in => clk25MHz,
186 212 clk_out => clk24_576MHz,
187 213 rstn => resetn,
188 214 sin => tick,
189 215 sout => new_timecode);
190 216
191 217 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
192 218 GENERIC MAP (
193 219 NB_FF_OF_SYNC => 2)
194 220 PORT MAP (
195 221 clk_in => clk25MHz,
196 222 clk_out => clk24_576MHz,
197 223 rstn => resetn,
198 224 sin => coarsetime_reg_updated,
199 225 sout => new_coarsetime);
200 ----------------------------------------------------------------------------
226
227 SYNC_VALID_BIT_3 : SYNC_VALID_BIT
228 GENERIC MAP (
229 NB_FF_OF_SYNC => 2)
230 PORT MAP (
231 clk_in => clk25MHz,
232 clk_out => clk24_576MHz,
233 rstn => resetn,
234 sin => soft_reset,
235 sout => soft_reset_sync);
201 236
202 237 -----------------------------------------------------------------------------
203 238 --SYNC_FF_1 : SYNC_FF
204 239 -- GENERIC MAP (
205 240 -- NB_FF_OF_SYNC => 2)
206 241 -- PORT MAP (
207 242 -- clk => clk25MHz,
208 243 -- rstn => resetn,
209 244 -- A => fine_time_new_49,
210 245 -- A_sync => fine_time_new_temp);
211 246
212 247 --lpp_front_detection_1 : lpp_front_detection
213 248 -- PORT MAP (
214 249 -- clk => clk25MHz,
215 250 -- rstn => resetn,
216 251 -- sin => fine_time_new_temp,
217 252 -- sout => fine_time_new);
218 253
219 254 --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
220 255 -- GENERIC MAP (
221 256 -- NB_FF_OF_SYNC => 2)
222 257 -- PORT MAP (
223 258 -- clk_in => clk24_576MHz,
224 259 -- clk_out => clk25MHz,
225 260 -- rstn => resetn,
226 261 -- sin => coarse_time_new_49,
227 262 -- sout => coarse_time_new);
228 263
229 264 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
230 265
231 266 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
232 267 GENERIC MAP (
233 268 NB_FF_OF_SYNC => 2)
234 269 PORT MAP (
235 270 clk_in => clk24_576MHz,
236 271 clk_out => clk25MHz,
237 272 rstn => resetn,
238 273 sin => time_new_49,
239 274 sout => time_new);
240 275
241 276
242 277
243 278 PROCESS (clk25MHz, resetn)
244 279 BEGIN -- PROCESS
245 280 IF resetn = '0' THEN -- asynchronous reset (active low)
246 281 fine_time_s <= (OTHERS => '0');
247 282 coarse_time_s <= (OTHERS => '0');
248 283 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
249 284 IF time_new = '1' THEN
250 285 fine_time_s <= fine_time_49;
251 286 coarse_time_s <= coarse_time_49;
252 287 END IF;
253 288 END IF;
254 289 END PROCESS;
255 290
291
292 rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE
293 '0' WHEN soft_reset_sync = '1' ELSE
294 '1';
295
296
256 297 -----------------------------------------------------------------------------
257 298 -- LFR_TIME_MANAGMENT
258 299 -----------------------------------------------------------------------------
259 300 lfr_time_management_1 : lfr_time_management
260 301 GENERIC MAP (
261 302 FIRST_DIVISION => FIRST_DIVISION,
262 303 NB_SECOND_DESYNC => NB_SECOND_DESYNC)
263 304 PORT MAP (
264 305 clk => clk24_576MHz,
265 rstn => resetn,
306 rstn => rstn_LFR_TM,
266 307
267 308 tick => new_timecode,
268 309 new_coarsetime => new_coarsetime,
269 coarsetime_reg => coarsetime_reg(31 DOWNTO 0),
310 coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
270 311
271 312 fine_time => fine_time_49,
272 313 fine_time_new => fine_time_new_49,
273 314 coarse_time => coarse_time_49,
274 315 coarse_time_new => coarse_time_new_49);
275 316
276 317 END Behavioral;
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@@ -1,99 +1,108
1 1 LIBRARY IEEE;
2 2 USE IEEE.STD_LOGIC_1164.ALL;
3 3 USE IEEE.NUMERIC_STD.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.general_purpose.ALL;
7 7
8 8 ENTITY coarse_time_counter IS
9 9 GENERIC (
10 10 NB_SECOND_DESYNC : INTEGER := 60);
11 11
12 12 PORT (
13 13 clk : IN STD_LOGIC;
14 14 rstn : IN STD_LOGIC;
15 15
16 16 tick : IN STD_LOGIC;
17 17 set_TCU : IN STD_LOGIC;
18 set_TCU_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
18 new_TCU : IN STD_LOGIC;
19 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
19 20 CT_add1 : IN STD_LOGIC;
20 21 fsm_desync : IN STD_LOGIC;
21 22 FT_max : IN STD_LOGIC;
22 23
23 24 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
24 25 coarse_time_new : OUT STD_LOGIC
25 26
26 27 );
27 28
28 29 END coarse_time_counter;
29 30
30 31 ARCHITECTURE beh OF coarse_time_counter IS
31 32
32 33 SIGNAL add1_bit31 : STD_LOGIC;
33 34 SIGNAL nb_second_counter : STD_LOGIC_VECTOR(5 DOWNTO 0);
34 35 SIGNAL coarse_time_new_counter : STD_LOGIC;
35 36 SIGNAL coarse_time_31 : STD_LOGIC;
36 37 SIGNAL coarse_time_31_reg : STD_LOGIC;
37 38
38 39 SIGNAL set_synchronized : STD_LOGIC;
39 40 SIGNAL set_synchronized_value : STD_LOGIC_VECTOR(5 DOWNTO 0);
40 41
41 42 --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60
42 43 BEGIN -- beh
43 44
45 -----------------------------------------------------------------------------
46 -- COARSE_TIME( 30 DOWNTO 0)
47 -----------------------------------------------------------------------------
44 48 counter_1 : general_counter
45 49 GENERIC MAP (
46 50 CYCLIC => '1',
47 51 NB_BITS_COUNTER => 31)
48 52 PORT MAP (
49 53 clk => clk,
50 54 rstn => rstn,
51 55 RST_VALUE => (OTHERS => '0'),
52 56 MAX_VALUE => "111" & X"FFFFFFF" ,
53 57 set => set_TCU,
54 58 set_value => set_TCU_value(30 DOWNTO 0),
55 59 add1 => CT_add1,
56 60 counter => coarse_time(30 DOWNTO 0));
57 61
58 62
59 63 add1_bit31 <= '1' WHEN fsm_desync = '1' AND FT_max = '1' ELSE '0';
60 64
65 -----------------------------------------------------------------------------
66 -- COARSE_TIME(31)
67 -----------------------------------------------------------------------------
61 68
62 set_synchronized <= (tick AND (NOT coarse_time_31)) OR (coarse_time_31 AND set_TCU);
63 set_synchronized_value <= STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) WHEN (set_TCU AND set_TCU_value(31)) = '1' ELSE
64 (OTHERS => '0');
69 --set_synchronized <= (tick AND (NOT coarse_time_31)) OR (coarse_time_31 AND set_TCU);
70 --set_synchronized_value <= STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) WHEN (set_TCU AND set_TCU_value(31)) = '1' ELSE
71 -- (OTHERS => '0');
72 set_synchronized <= tick AND ((NOT coarse_time_31) OR (coarse_time_31 AND new_TCU));
73 set_synchronized_value <= (OTHERS => '0');
65 74
66 75 counter_2 : general_counter
67 76 GENERIC MAP (
68 77 CYCLIC => '0',
69 78 NB_BITS_COUNTER => 6)
70 79 PORT MAP (
71 80 clk => clk,
72 81 rstn => rstn,
73 82 RST_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)),
74 83 MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)),
75 84 set => set_synchronized,
76 85 set_value => set_synchronized_value,
77 86 add1 => add1_bit31,
78 87 counter => nb_second_counter);
79 88
80 89 coarse_time_31 <= '1' WHEN nb_second_counter = STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) ELSE '0';
81 90 coarse_time(31) <= coarse_time_31;
82 91 coarse_time_new <= coarse_time_new_counter OR (coarse_time_31 XOR coarse_time_31_reg);
83 92
84 93 PROCESS (clk, rstn)
85 94 BEGIN -- PROCESS
86 95 IF rstn = '0' THEN -- asynchronous reset (active low)
87 96 coarse_time_new_counter <= '0';
88 97 coarse_time_31_reg <= '0';
89 98 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
90 99 coarse_time_31_reg <= coarse_time_31;
91 100 IF set_TCU = '1' OR CT_add1 = '1' THEN
92 101 coarse_time_new_counter <= '1';
93 102 ELSE
94 103 coarse_time_new_counter <= '0';
95 104 END IF;
96 105 END IF;
97 106 END PROCESS;
98 107
99 108 END beh;
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@@ -1,173 +1,174
1 1 ----------------------------------------------------------------------------------
2 2 -- Company:
3 3 -- Engineer:
4 4 --
5 5 -- Create Date: 11:14:05 07/02/2012
6 6 -- Design Name:
7 7 -- Module Name: lfr_time_management - Behavioral
8 8 -- Project Name:
9 9 -- Target Devices:
10 10 -- Tool versions:
11 11 -- Description:
12 12 --
13 13 -- Dependencies:
14 14 --
15 15 -- Revision:
16 16 -- Revision 0.01 - File Created
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 20 LIBRARY IEEE;
21 21 USE IEEE.STD_LOGIC_1164.ALL;
22 22 USE IEEE.NUMERIC_STD.ALL;
23 23 LIBRARY lpp;
24 24 USE lpp.lpp_lfr_time_management.ALL;
25 25
26 26 ENTITY lfr_time_management IS
27 27 GENERIC (
28 28 FIRST_DIVISION : INTEGER := 374;
29 29 NB_SECOND_DESYNC : INTEGER := 60);
30 30 PORT (
31 31 clk : IN STD_LOGIC;
32 32 rstn : IN STD_LOGIC;
33 33
34 34 tick : IN STD_LOGIC; -- transition signal information
35 35
36 36 new_coarsetime : IN STD_LOGIC; -- transition signal information
37 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
37 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
38 38
39 39 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
40 40 fine_time_new : OUT STD_LOGIC;
41 41 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
42 42 coarse_time_new : OUT STD_LOGIC
43 43 );
44 44 END lfr_time_management;
45 45
46 46 ARCHITECTURE Behavioral OF lfr_time_management IS
47 47
48 48 SIGNAL FT_max : STD_LOGIC;
49 49 SIGNAL FT_half : STD_LOGIC;
50 50 SIGNAL FT_wait : STD_LOGIC;
51 51
52 52 TYPE state_fsm_time_management IS (DESYNC, TRANSITION, SYNC);
53 53 SIGNAL state : state_fsm_time_management;
54 54
55 55 SIGNAL fsm_desync : STD_LOGIC;
56 56 SIGNAL fsm_transition : STD_LOGIC;
57 57
58 58 SIGNAL set_TCU : STD_LOGIC;
59 59 SIGNAL CT_add1 : STD_LOGIC;
60 60
61 61 SIGNAL new_coarsetime_reg : STD_LOGIC;
62 62
63 63 BEGIN
64 64
65 65 -----------------------------------------------------------------------------
66 66 --
67 67 -----------------------------------------------------------------------------
68 68 PROCESS (clk, rstn)
69 69 BEGIN -- PROCESS
70 70 IF rstn = '0' THEN -- asynchronous reset (active low)
71 71 new_coarsetime_reg <= '0';
72 72 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
73 73 IF new_coarsetime = '1' THEN
74 74 new_coarsetime_reg <= '1';
75 75 ELSIF tick = '1' THEN
76 76 new_coarsetime_reg <= '0';
77 77 END IF;
78 78 END IF;
79 79 END PROCESS;
80 80
81 81 -----------------------------------------------------------------------------
82 82 -- FINE_TIME
83 83 -----------------------------------------------------------------------------
84 84 fine_time_counter_1: fine_time_counter
85 85 GENERIC MAP (
86 86 WAITING_TIME => X"0040",
87 87 FIRST_DIVISION => FIRST_DIVISION)
88 88 PORT MAP (
89 89 clk => clk,
90 90 rstn => rstn,
91 91 tick => tick,
92 92 fsm_transition => fsm_transition, -- todo
93 93 FT_max => FT_max,
94 94 FT_half => FT_half,
95 95 FT_wait => FT_wait,
96 96 fine_time => fine_time,
97 97 fine_time_new => fine_time_new);
98 98
99 99 -----------------------------------------------------------------------------
100 100 -- COARSE_TIME
101 101 -----------------------------------------------------------------------------
102 102 coarse_time_counter_1: coarse_time_counter
103 103 GENERIC MAP(
104 104 NB_SECOND_DESYNC => NB_SECOND_DESYNC )
105 105 PORT MAP (
106 106 clk => clk,
107 107 rstn => rstn,
108 108 tick => tick,
109 109 set_TCU => set_TCU, -- todo
110 new_TCU => new_coarsetime_reg,
110 111 set_TCU_value => coarsetime_reg, -- todo
111 112 CT_add1 => CT_add1, -- todo
112 113 fsm_desync => fsm_desync, -- todo
113 114 FT_max => FT_max,
114 115 coarse_time => coarse_time,
115 116 coarse_time_new => coarse_time_new);
116 117
117 118 -----------------------------------------------------------------------------
118 119 -- FSM
119 120 -----------------------------------------------------------------------------
120 121 fsm_desync <= '1' WHEN state = DESYNC ELSE '0';
121 122 fsm_transition <= '1' WHEN state = TRANSITION ELSE '0';
122 123
123 124 PROCESS (clk, rstn)
124 125 BEGIN -- PROCESS
125 126 IF rstn = '0' THEN -- asynchronous reset (active low)
126 127 state <= DESYNC;
127 128 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
128 129 --CT_add1 <= '0';
129 130 set_TCU <= '0';
130 131 CASE state IS
131 132 WHEN DESYNC =>
132 133 IF tick = '1' THEN
133 134 state <= SYNC;
134 135 set_TCU <= new_coarsetime_reg;
135 136 --IF new_coarsetime = '0' AND FT_half = '1' THEN
136 137 -- CT_add1 <= '1';
137 138 --END IF;
138 139 --ELSIF FT_max = '1' THEN
139 140 -- CT_add1 <= '1';
140 141 END IF;
141 142 WHEN TRANSITION =>
142 143 IF tick = '1' THEN
143 144 state <= SYNC;
144 145 set_TCU <= new_coarsetime_reg;
145 146 --IF new_coarsetime = '0' THEN
146 147 -- CT_add1 <= '1';
147 148 --END IF;
148 149 ELSIF FT_wait = '1' THEN
149 150 --CT_add1 <= '1';
150 151 state <= DESYNC;
151 152 END IF;
152 153 WHEN SYNC =>
153 154 IF tick = '1' THEN
154 155 set_TCU <= new_coarsetime_reg;
155 156 --IF new_coarsetime = '0' THEN
156 157 -- CT_add1 <= '1';
157 158 --END IF;
158 159 ELSIF FT_max = '1' THEN
159 160 state <= TRANSITION;
160 161 END IF;
161 162 WHEN OTHERS => NULL;
162 163 END CASE;
163 164 END IF;
164 165 END PROCESS;
165 166
166 167
167 168 CT_add1 <= '1' WHEN state = SYNC AND tick = '1' AND new_coarsetime_reg = '0' ELSE
168 169 '1' WHEN state = DESYNC AND tick = '1' AND new_coarsetime_reg = '0' AND FT_half = '1' ELSE
169 170 '1' WHEN state = DESYNC AND tick = '0' AND FT_max = '1' ELSE
170 171 '1' WHEN state = TRANSITION AND tick = '1' AND new_coarsetime_reg = '0' ELSE
171 172 '1' WHEN state = TRANSITION AND tick = '0' AND FT_wait = '1' ELSE
172 173 '0';
173 174 END Behavioral;
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@@ -1,101 +1,102
1 1 ----------------------------------------------------------------------------------
2 2 -- Company:
3 3 -- Engineer:
4 4 --
5 5 -- Create Date: 13:04:01 07/02/2012
6 6 -- Design Name:
7 7 -- Module Name: lpp_lfr_time_management - Behavioral
8 8 -- Project Name:
9 9 -- Target Devices:
10 10 -- Tool versions:
11 11 -- Description:
12 12 --
13 13 -- Dependencies:
14 14 --
15 15 -- Revision:
16 16 -- Revision 0.01 - File Created
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 20 LIBRARY IEEE;
21 21 USE IEEE.STD_LOGIC_1164.ALL;
22 22 LIBRARY grlib;
23 23 USE grlib.amba.ALL;
24 24 USE grlib.stdlib.ALL;
25 25 USE grlib.devices.ALL;
26 26
27 27 PACKAGE lpp_lfr_time_management IS
28 28
29 29 --***************************
30 30 -- APB_LFR_TIME_MANAGEMENT
31 31
32 32 COMPONENT apb_lfr_time_management IS
33 33 GENERIC(
34 34 pindex : INTEGER := 0; --! APB slave index
35 35 paddr : INTEGER := 0; --! ADDR field of the APB BAR
36 36 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 37 FIRST_DIVISION : INTEGER;
38 38 NB_SECOND_DESYNC : INTEGER);
39 39 PORT (
40 40 clk25MHz : IN STD_LOGIC; --! Clock
41 41 clk24_576MHz : IN STD_LOGIC; --! secondary clock
42 42 resetn : IN STD_LOGIC; --! Reset
43 43 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
44 44 apbi : IN apb_slv_in_type; --! APB slave input signals
45 45 apbo : OUT apb_slv_out_type; --! APB slave output signals
46 46 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
47 47 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
48 48 );
49 49 END COMPONENT;
50 50
51 51 COMPONENT lfr_time_management
52 52 GENERIC (
53 53 FIRST_DIVISION : INTEGER;
54 54 NB_SECOND_DESYNC : INTEGER);
55 55 PORT (
56 56 clk : IN STD_LOGIC;
57 57 rstn : IN STD_LOGIC;
58 58 tick : IN STD_LOGIC;
59 59 new_coarsetime : IN STD_LOGIC;
60 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
61 61 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
62 62 fine_time_new : OUT STD_LOGIC;
63 63 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 64 coarse_time_new : OUT STD_LOGIC);
65 65 END COMPONENT;
66 66
67 67 COMPONENT coarse_time_counter
68 68 GENERIC (
69 69 NB_SECOND_DESYNC : INTEGER );
70 70 PORT (
71 71 clk : IN STD_LOGIC;
72 72 rstn : IN STD_LOGIC;
73 73 tick : IN STD_LOGIC;
74 74 set_TCU : IN STD_LOGIC;
75 set_TCU_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
75 new_TCU : IN STD_LOGIC;
76 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
76 77 CT_add1 : IN STD_LOGIC;
77 78 fsm_desync : IN STD_LOGIC;
78 79 FT_max : IN STD_LOGIC;
79 80 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 81 coarse_time_new : OUT STD_LOGIC);
81 82 END COMPONENT;
82 83
83 84 COMPONENT fine_time_counter
84 85 GENERIC (
85 86 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0);
86 87 FIRST_DIVISION : INTEGER );
87 88 PORT (
88 89 clk : IN STD_LOGIC;
89 90 rstn : IN STD_LOGIC;
90 91 tick : IN STD_LOGIC;
91 92 fsm_transition : IN STD_LOGIC;
92 93 FT_max : OUT STD_LOGIC;
93 94 FT_half : OUT STD_LOGIC;
94 95 FT_wait : OUT STD_LOGIC;
95 96 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
96 97 fine_time_new : OUT STD_LOGIC);
97 98 END COMPONENT;
98 99
99 100
100 101 END lpp_lfr_time_management;
101 102
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