HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r524:cca844e6506f

add leon3ft into leon3_soc (and option IS_RADHARD to use leon3 or leon3ft)

pellion -

r524:cca844e6506f JC

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r524:cca844e6506f

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designs/LFR-em-WFP_MS/LFR-em.vhd +1 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                     Mail : jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY gaisler;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.spacewire.ALL;
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.lpp_lfr_pkg.ALL;  -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
             USE lpp.lpp_top_lfr_pkg.ALL;            -- contains top_wf_picker
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_lfr_management.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
             ENTITY LFR_em IS
               PORT (
                 clk100MHz    : IN STD_ULOGIC;
                 clk49_152MHz : IN STD_ULOGIC;
                 reset        : IN STD_ULOGIC;
                 -- TAG --------------------------------------------------------------------
                 TAG1           : IN    STD_ULOGIC;  -- DSU rx data
                 TAG3           : OUT   STD_ULOGIC;  -- DSU tx data
                 -- UART APB ---------------------------------------------------------------
                 TAG2           : IN    STD_ULOGIC;  -- UART1 rx data
                 TAG4           : OUT   STD_ULOGIC;  -- UART1 tx data
                 -- RAM --------------------------------------------------------------------
                 address        : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
                 data           : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 nSRAM_BE0      : OUT   STD_LOGIC;
                 nSRAM_BE1      : OUT   STD_LOGIC;
                 nSRAM_BE2      : OUT   STD_LOGIC;
                 nSRAM_BE3      : OUT   STD_LOGIC;
                 nSRAM_WE       : OUT   STD_LOGIC;
                 nSRAM_CE       : OUT   STD_LOGIC;
                 nSRAM_OE       : OUT   STD_LOGIC;
                 -- SPW --------------------------------------------------------------------
                 spw1_din       : IN    STD_LOGIC;
                 spw1_sin       : IN    STD_LOGIC;
                 spw1_dout      : OUT   STD_LOGIC;
                 spw1_sout      : OUT   STD_LOGIC;
                 spw2_din       : IN    STD_LOGIC;
                 spw2_sin       : IN    STD_LOGIC;
                 spw2_dout      : OUT   STD_LOGIC;
                 spw2_sout      : OUT   STD_LOGIC;
                 -- ADC --------------------------------------------------------------------
                 bias_fail_sw   : OUT   STD_LOGIC;
                 ADC_OEB_bar_CH : OUT   STD_LOGIC_VECTOR(7 DOWNTO 0);
                 ADC_smpclk     : OUT   STD_LOGIC;
                 ADC_data       : IN    STD_LOGIC_VECTOR(13 DOWNTO 0);
                 -- HK ---------------------------------------------------------------------
                 HK_smpclk      : OUT   STD_LOGIC;
                 ADC_OEB_bar_HK : OUT   STD_LOGIC;
                 HK_SEL         : OUT   STD_LOGIC_VECTOR(1 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 TAG8           : OUT   STD_LOGIC;
                 led            : OUT   STD_LOGIC_VECTOR(2 DOWNTO 0)
                 );
             END LFR_em;
             ARCHITECTURE beh OF LFR_em IS
               SIGNAL clk_50_s    : STD_LOGIC := '0';
               SIGNAL clk_25      : STD_LOGIC := '0';
               SIGNAL clk_24      : STD_LOGIC := '0';
               -----------------------------------------------------------------------------
               SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL fine_time   : STD_LOGIC_VECTOR(15 DOWNTO 0);
               -- CONSTANTS
               CONSTANT CFG_PADTECH   : INTEGER := inferred;
               CONSTANT NB_APB_SLAVE  : INTEGER := 11;  -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
               CONSTANT NB_AHB_SLAVE  : INTEGER := 1;
               CONSTANT NB_AHB_MASTER : INTEGER := 2;   -- 2 = grspw + waveform picker
               SIGNAL apbi_ext   : apb_slv_in_type;
               SIGNAL apbo_ext   : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5)  := (OTHERS => apb_none);
               SIGNAL ahbi_s_ext : ahb_slv_in_type;
               SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3)  := (OTHERS => ahbs_none);
               SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
               SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
             -- Spacewire signals
               SIGNAL dtmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL stmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxclk   : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxtxclk : STD_ULOGIC;
               SIGNAL spw_rxclkn  : STD_ULOGIC;
               SIGNAL spw_clk     : STD_LOGIC;
               SIGNAL swni        : grspw_in_type;
               SIGNAL swno        : grspw_out_type;
             --GPIO
               SIGNAL gpioi : gpio_in_type;
               SIGNAL gpioo : gpio_out_type;
             -- AD Converter ADS7886
               SIGNAL sample      : Samples14v(8 DOWNTO 0);
               SIGNAL sample_s    : Samples(8 DOWNTO 0);
               SIGNAL sample_val  : STD_LOGIC;
               SIGNAL  ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL rstn : STD_LOGIC;
               SIGNAL LFR_soft_rstn : STD_LOGIC;
               SIGNAL LFR_rstn      : STD_LOGIC;
               SIGNAL ADC_smpclk_s : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               -- CLK
               -----------------------------------------------------------------------------
               rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
               PROCESS(clk100MHz)
               BEGIN
                 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
                   clk_50_s <= NOT clk_50_s;
                 END IF;
               END PROCESS;
               PROCESS(clk_50_s)
               BEGIN
                 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
                   clk_25 <= NOT clk_25;
                 END IF;
               END PROCESS;
               PROCESS(clk49_152MHz)
               BEGIN
                 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
                   clk_24 <= NOT clk_24;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               PROCESS (clk_25, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   led(0) <= '0';
                   led(1) <= '0';
                   led(2) <= '0';
                 ELSIF clk_25'EVENT AND clk_25 = '1' THEN  -- rising clock edge
                   led(0) <= '0';
                   led(1) <= '1';
                   led(2) <= '1';
                 END IF;
               END PROCESS;
               --
               leon3_soc_1 : leon3_soc
                 GENERIC MAP (
                   fabtech         => apa3e,
                   memtech         => apa3e,
                   padtech         => inferred,
                   clktech         => inferred,
                   disas           => 0,
                   dbguart         => 0,
                   pclow           => 2,
                   clk_freq        => 25000,
                   NB_CPU          => 1,
                   ENABLE_FPU      => 1,
                   FPU_NETLIST     => 0,
                   ENABLE_DSU      => 1,
                   ENABLE_AHB_UART => 1,
                   ENABLE_APB_UART => 1,
                   ENABLE_IRQMP    => 1,
                   ENABLE_GPT      => 1,
                   NB_AHB_MASTER   => NB_AHB_MASTER,
                   NB_AHB_SLAVE    => NB_AHB_SLAVE,
                   NB_APB_SLAVE    => NB_APB_SLAVE,
                   ADDRESS_SIZE    => 20,
                   USES_IAP_MEMCTRLR => 0)
                 PORT MAP (
                   clk    => clk_25,
                   reset  => rstn,
                   errorn => OPEN,
                   ahbrxd => TAG1,
                   ahbtxd => TAG3,
                   urxd1  => TAG2,
                   utxd1  => TAG4,
                   address   => address,
                   data      => data,
                   nSRAM_BE0 => nSRAM_BE0,
                   nSRAM_BE1 => nSRAM_BE1,
                   nSRAM_BE2 => nSRAM_BE2,
                   nSRAM_BE3 => nSRAM_BE3,
                   nSRAM_WE  => nSRAM_WE,
                   nSRAM_CE  => nSRAM_CE_s,
                   nSRAM_OE  => nSRAM_OE,
                   nSRAM_READY => '0',
                   SRAM_MBE    => OPEN,
                   apbi_ext   => apbi_ext,
                   apbo_ext   => apbo_ext,
                   ahbi_s_ext => ahbi_s_ext,
                   ahbo_s_ext => ahbo_s_ext,
                   ahbi_m_ext => ahbi_m_ext,
                   ahbo_m_ext => ahbo_m_ext);
               nSRAM_CE <= nSRAM_CE_s(0);
             -------------------------------------------------------------------------------
             -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
             -------------------------------------------------------------------------------
               apb_lfr_management_1 : apb_lfr_management
                 GENERIC MAP (
                   pindex           => 6,
                   paddr            => 6,
                   pmask            => 16#fff#,
                   FIRST_DIVISION   => 374,  -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
                   NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
                 PORT MAP (
                   clk25MHz      => clk_25,
                   clk24_576MHz  => clk_24,          -- 49.152MHz/2
                   resetn        => rstn,
                   grspw_tick    => swno.tickout,
                   apbi          => apbi_ext,
                   apbo          => apbo_ext(6),
                   HK_sample     => sample_s(8),
                   HK_val        => sample_val,
                   HK_sel        => HK_SEL,
                   coarse_time   => coarse_time,
                   fine_time     => fine_time,
                   LFR_soft_rstn => LFR_soft_rstn
                   );
             -----------------------------------------------------------------------
             ---  SpaceWire --------------------------------------------------------
             -----------------------------------------------------------------------
             --  SPW_EN <= '1';
               spw_clk     <= clk_50_s;
               spw_rxtxclk <= spw_clk;
               spw_rxclkn  <= NOT spw_rxtxclk;
               -- PADS for SPW1
               spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_din, dtmp(0));
               spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_sin, stmp(0));
               spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_dout, swno.d(0));
               spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_sout, swno.s(0));
               -- PADS FOR SPW2
               spw2_rxd_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (spw2_din, dtmp(1));
               spw2_rxs_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (spw2_sin, stmp(1));
               spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw2_dout, swno.d(1));
               spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw2_sout, swno.s(1));
               -- GRSPW PHY
               --spw1_input: if CFG_SPW_GRSPW = 1 generate
               spw_inputloop : FOR j IN 0 TO 1 GENERATE
                 spw_phy0 : grspw_phy
                   GENERIC MAP(
                     tech         => apa3e,
                     rxclkbuftype => 1,
                     scantest     => 0)
                   PORT MAP(
                     rxrst    => swno.rxrst,
                     di       => dtmp(j),
                     si       => stmp(j),
                     rxclko   => spw_rxclk(j),
                     do       => swni.d(j),
                     ndo      => swni.nd(j*5+4 DOWNTO j*5),
                     dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
               END GENERATE spw_inputloop;
               -- SPW core
               sw0 : grspwm GENERIC MAP(
                 tech         => apa3e,
                 hindex       => 1,
                 pindex       => 5,
                 paddr        => 5,
                 pirq         => 11,
                 sysfreq      => 25000,              -- CPU_FREQ
                 rmap         => 1,
                 rmapcrc      => 1,
                 fifosize1    => 16,
                 fifosize2    => 16,
                 rxclkbuftype => 1,
                 rxunaligned  => 0,
                 rmapbufs     => 4,
                 ft           => 0,
                 netlist      => 0,
                 ports        => 2,
                 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
                 memtech      => apa3e,
                 destkey      => 2,
                 spwcore      => 1
                 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
                 --output_type => CFG_SPW_OUTPUT,  -- not used byt the spw core 1
                 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
                 )
                 PORT MAP(rstn, clk_25, spw_rxclk(0),
                          spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
                          ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
                          swni, swno);
               swni.tickin      <= '0';
               swni.rmapen      <= '1';
               swni.clkdiv10    <= "00000100";       -- 10 MHz / (4 + 1) = 10 MHz
               swni.tickinraw   <= '0';
               swni.timein      <= (OTHERS => '0');
               swni.dcrstval    <= (OTHERS => '0');
               swni.timerrstval <= (OTHERS => '0');
             -------------------------------------------------------------------------------
             -- LFR ------------------------------------------------------------------------
             -------------------------------------------------------------------------------
               LFR_rstn <= LFR_soft_rstn AND rstn;
               lpp_lfr_1 : lpp_lfr
                 GENERIC MAP (
                   Mem_use                => use_RAM,
                   nb_data_by_buffer_size => 32,
                   --nb_word_by_buffer_size => 30,
                   nb_snapshot_param_size => 32,
                   delta_vector_size      => 32,
                   delta_vector_size_f0_2 => 7,          -- log2(96)
                   pindex                 => 15,
                   paddr                  => 15,
                   pmask                  => 16#fff#,
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"010135")  -- aa.bb.cc version
+                  top_lfr_version        => X"010138")  -- aa.bb.cc version
                                                         -- AA : BOARD NUMBER
                                                         --      0 => MINI_LFR
                                                         --      1 => EM
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => LFR_rstn,
                   sample_B        => sample_s(2 DOWNTO 0),
                   sample_E        => sample_s(7 DOWNTO 3),
                   sample_val      => sample_val,
                   apbi            => apbi_ext,
                   apbo            => apbo_ext(15),
                   ahbi            => ahbi_m_ext,
                   ahbo            => ahbo_m_ext(2),
                   coarse_time     => coarse_time,
                   fine_time       => fine_time,
                   data_shaping_BW => bias_fail_sw,
                   debug_vector    => OPEN,
                   debug_vector_ms => OPEN);     --,
               --observation_vector_0 => OPEN,
               --observation_vector_1 => OPEN,
               --observation_reg => observation_reg);
               all_sample : FOR I IN 7 DOWNTO 0 GENERATE
                 sample_s(I) <= sample(I) & '0' & '0';
               END GENERATE all_sample;
               sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
                 GENERIC MAP (
                   ChanelCount     => 9,
                   ncycle_cnv_high => 13,
                   ncycle_cnv      => 25,
                   FILTER_ENABLED  => 16#FF#)
                 PORT MAP (
                   cnv_clk    => clk_24,
                   cnv_rstn   => rstn,
                   cnv        => ADC_smpclk_s,
                   clk        => clk_25,
                   rstn       => rstn,
                   ADC_data   => ADC_data,
                   ADC_nOE    => ADC_OEB_bar_CH_s,
                   sample     => sample,
                   sample_val => sample_val);
               ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
               ADC_smpclk <= ADC_smpclk_s;
               HK_smpclk  <= ADC_smpclk_s;
               TAG8 <= ADC_smpclk_s;
               -----------------------------------------------------------------------------
               -- HK
               -----------------------------------------------------------------------------
               ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
             END beh;

designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +3 -4

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                     Mail : jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY gaisler;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.spacewire.ALL;
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.lpp_lfr_pkg.ALL;  -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
             USE lpp.lpp_top_lfr_pkg.ALL;            -- contains top_wf_picker
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_lfr_management.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
             ENTITY MINI_LFR_top IS
               PORT (
                 clk_50 : IN  STD_LOGIC;
                 clk_49 : IN  STD_LOGIC;
                 reset  : IN  STD_LOGIC;
                 --BPs
                 BP0    : IN  STD_LOGIC;
                 BP1    : IN  STD_LOGIC;
                 --LEDs
                 LED0   : OUT STD_LOGIC;
                 LED1   : OUT STD_LOGIC;
                 LED2   : OUT STD_LOGIC;
                 --UARTs
                 TXD1   : IN  STD_LOGIC;
                 RXD1   : OUT STD_LOGIC;
                 nCTS1  : OUT STD_LOGIC;
                 nRTS1  : IN  STD_LOGIC;
                 TXD2  : IN  STD_LOGIC;
                 RXD2  : OUT STD_LOGIC;
                 nCTS2 : OUT STD_LOGIC;
                 nDTR2 : IN  STD_LOGIC;
                 nRTS2 : IN  STD_LOGIC;
                 nDCD2 : OUT STD_LOGIC;
                 --EXT CONNECTOR
                 IO0  : INOUT STD_LOGIC;
                 IO1  : INOUT STD_LOGIC;
                 IO2  : INOUT STD_LOGIC;
                 IO3  : INOUT STD_LOGIC;
                 IO4  : INOUT STD_LOGIC;
                 IO5  : INOUT STD_LOGIC;
                 IO6  : INOUT STD_LOGIC;
                 IO7  : INOUT STD_LOGIC;
                 IO8  : INOUT STD_LOGIC;
                 IO9  : INOUT STD_LOGIC;
                 IO10 : INOUT STD_LOGIC;
                 IO11 : INOUT STD_LOGIC;
                 --SPACE WIRE
                 SPW_EN       : OUT STD_LOGIC;       -- 0 => off
                 SPW_NOM_DIN  : IN  STD_LOGIC;       -- NOMINAL LINK
                 SPW_NOM_SIN  : IN  STD_LOGIC;
                 SPW_NOM_DOUT : OUT STD_LOGIC;
                 SPW_NOM_SOUT : OUT STD_LOGIC;
                 SPW_RED_DIN  : IN  STD_LOGIC;       -- REDUNDANT LINK
                 SPW_RED_SIN  : IN  STD_LOGIC;
                 SPW_RED_DOUT : OUT STD_LOGIC;
                 SPW_RED_SOUT : OUT STD_LOGIC;
                 -- MINI LFR ADC INPUTS
                 ADC_nCS      : OUT STD_LOGIC;
                 ADC_CLK      : OUT STD_LOGIC;
                 ADC_SDO      : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
                 -- SRAM
                 SRAM_nWE : OUT   STD_LOGIC;
                 SRAM_CE  : OUT   STD_LOGIC;
                 SRAM_nOE : OUT   STD_LOGIC;
                 SRAM_nBE : OUT   STD_LOGIC_VECTOR(3 DOWNTO 0);
                 SRAM_A   : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
                 SRAM_DQ  : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
                 );
             END MINI_LFR_top;
             ARCHITECTURE beh OF MINI_LFR_top IS
               SIGNAL clk_50_s    : STD_LOGIC := '0';
               SIGNAL clk_25      : STD_LOGIC := '0';
               SIGNAL clk_24      : STD_LOGIC := '0';
               -----------------------------------------------------------------------------
               SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL fine_time   : STD_LOGIC_VECTOR(15 DOWNTO 0);
               --
               SIGNAL errorn      : STD_LOGIC;
               -- UART AHB ---------------------------------------------------------------
             --  SIGNAL ahbrxd      : STD_ULOGIC;      -- DSU rx data
             --  SIGNAL ahbtxd      : STD_ULOGIC;      -- DSU tx data
               -- UART APB ---------------------------------------------------------------
             --  SIGNAL urxd1 : STD_ULOGIC;            -- UART1 rx data
             --  SIGNAL utxd1 : STD_ULOGIC;            -- UART1 tx data
               --
               SIGNAL I00_s : STD_LOGIC;
               -- CONSTANTS
               CONSTANT CFG_PADTECH   : INTEGER := inferred;
               --
               CONSTANT NB_APB_SLAVE  : INTEGER := 11;  -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
               CONSTANT NB_AHB_SLAVE  : INTEGER := 1;
               CONSTANT NB_AHB_MASTER : INTEGER := 2;   -- 2 = grspw + waveform picker
               SIGNAL apbi_ext   : apb_slv_in_type;
               SIGNAL apbo_ext   : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);  --  := (OTHERS => apb_none);
               SIGNAL ahbi_s_ext : ahb_slv_in_type;
               SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);  --  := (OTHERS => ahbs_none);
               SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
               SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1);  -- := (OTHERS => ahbm_none);
             -- Spacewire signals
               SIGNAL dtmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL stmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxclk   : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxtxclk : STD_ULOGIC;
               SIGNAL spw_rxclkn  : STD_ULOGIC;
               SIGNAL spw_clk     : STD_LOGIC;
               SIGNAL swni        : grspw_in_type;
               SIGNAL swno        : grspw_out_type;
             --  SIGNAL clkmn                : STD_ULOGIC;
             --  SIGNAL txclk                : STD_ULOGIC;
             --GPIO
               SIGNAL gpioi : gpio_in_type;
               SIGNAL gpioo : gpio_out_type;
             -- AD Converter ADS7886
               SIGNAL sample      : Samples14v(7 DOWNTO 0);
               SIGNAL sample_s    : Samples(7 DOWNTO 0);
               SIGNAL sample_val  : STD_LOGIC;
               SIGNAL ADC_nCS_sig : STD_LOGIC;
               SIGNAL ADC_CLK_sig : STD_LOGIC;
               SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
               SIGNAL bias_fail_sw_sig : STD_LOGIC;
               SIGNAL observation_reg      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
               SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL LFR_soft_rstn : STD_LOGIC;
               SIGNAL LFR_rstn      : STD_LOGIC;
               SIGNAL rstn_25    : STD_LOGIC;
               SIGNAL rstn_25_d1 : STD_LOGIC;
               SIGNAL rstn_25_d2 : STD_LOGIC;
               SIGNAL rstn_25_d3 : STD_LOGIC;
               SIGNAL rstn_50    : STD_LOGIC;
               SIGNAL rstn_50_d1 : STD_LOGIC;
               SIGNAL rstn_50_d2 : STD_LOGIC;
               SIGNAL rstn_50_d3 : STD_LOGIC;
               SIGNAL lfr_debug_vector    : STD_LOGIC_VECTOR(11 DOWNTO 0);
               SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
               --
               SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
               --
               SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL HK_SEL    : STD_LOGIC_VECTOR( 1 DOWNTO 0);
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               -- CLK
               -----------------------------------------------------------------------------
               --PROCESS(clk_50)
               --BEGIN
               --  IF clk_50'EVENT AND clk_50 = '1' THEN
               --    clk_50_s <= NOT clk_50_s;
               --  END IF;
               --END PROCESS;
               --PROCESS(clk_50_s)
               --BEGIN
               --  IF clk_50_s'EVENT AND clk_50_s = '1' THEN
               --    clk_25 <= NOT clk_25;
               --  END IF;
               --END PROCESS;
               --PROCESS(clk_49)
               --BEGIN
               --  IF clk_49'EVENT AND clk_49 = '1' THEN
               --    clk_24 <= NOT clk_24;
               --  END IF;
               --END PROCESS;
               --PROCESS(clk_25)
               --BEGIN
               --  IF clk_25'EVENT AND clk_25 = '1' THEN
               --    rstn_25 <= reset;
               --  END IF;
               --END PROCESS;
               PROCESS (clk_50, reset)
               BEGIN  -- PROCESS
                 IF reset = '0' THEN                 -- asynchronous reset (active low)
                   clk_50_s   <= '0';
                   rstn_50    <= '0';
                   rstn_50_d1 <= '0';
                   rstn_50_d2 <= '0';
                   rstn_50_d3 <= '0';
                 ELSIF clk_50'EVENT AND clk_50 = '1' THEN  -- rising clock edge
                   clk_50_s   <= NOT clk_50_s;
                   rstn_50_d1 <= '1';
                   rstn_50_d2 <= rstn_50_d1;
                   rstn_50_d3 <= rstn_50_d2;
                   rstn_50    <= rstn_50_d3;
                 END IF;
               END PROCESS;
               PROCESS (clk_50_s, rstn_50)
               BEGIN  -- PROCESS
                 IF rstn_50 = '0' THEN               -- asynchronous reset (active low)
                   clk_25     <= '0';
                   rstn_25    <= '0';
                   rstn_25_d1 <= '0';
                   rstn_25_d2 <= '0';
                   rstn_25_d3 <= '0';
                 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN  -- rising clock edge
                   clk_25     <= NOT clk_25;
                   rstn_25_d1 <= '1';
                   rstn_25_d2 <= rstn_25_d1;
                   rstn_25_d3 <= rstn_25_d2;
                   rstn_25    <= rstn_25_d3;
                 END IF;
               END PROCESS;
               PROCESS (clk_49, reset)
               BEGIN  -- PROCESS
                 IF reset = '0' THEN                 -- asynchronous reset (active low)
                   clk_24 <= '0';
                 ELSIF clk_49'EVENT AND clk_49 = '1' THEN  -- rising clock edge
                   clk_24 <= NOT clk_24;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               PROCESS (clk_25, rstn_25)
               BEGIN  -- PROCESS
                 IF rstn_25 = '0' THEN               -- asynchronous reset (active low)
                   LED0 <= '0';
                   LED1 <= '0';
                   LED2 <= '0';
                   --IO1  <= '0';
                   --IO2  <= '1';
                   --IO3  <= '0';
                   --IO4  <= '0';
                   --IO5  <= '0';
                   --IO6  <= '0';
                   --IO7  <= '0';
                   --IO8  <= '0';
                   --IO9  <= '0';
                   --IO10 <= '0';
                   --IO11 <= '0';
                 ELSIF clk_25'EVENT AND clk_25 = '1' THEN  -- rising clock edge
                   LED0 <= '0';
                   LED1 <= '1';
                   LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
                   --IO1  <= '1';
                   --IO2  <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
                   --IO3  <= ADC_SDO(0);
                   --IO4  <= ADC_SDO(1);
                   --IO5  <= ADC_SDO(2);
                   --IO6  <= ADC_SDO(3);
                   --IO7  <= ADC_SDO(4);
                   --IO8  <= ADC_SDO(5);
                   --IO9  <= ADC_SDO(6);
                   --IO10 <= ADC_SDO(7);
                   --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
                 END IF;
               END PROCESS;
               PROCESS (clk_24, rstn_25)
               BEGIN  -- PROCESS
                 IF rstn_25 = '0' THEN               -- asynchronous reset (active low)
                   I00_s <= '0';
                 ELSIF clk_24'EVENT AND clk_24 = '1' THEN  -- rising clock edge
                   I00_s <= NOT I00_s;
                 END IF;
               END PROCESS;
             --  IO0 <= I00_s;
               --UARTs
               nCTS1 <= '1';
               nCTS2 <= '1';
               nDCD2 <= '1';
-              --EXT CONNECTOR
+              --
-              --SPACE WIRE
               leon3_soc_1 : leon3_soc
                 GENERIC MAP (
                   fabtech         => apa3e,
                   memtech         => apa3e,
                   padtech         => inferred,
                   clktech         => inferred,
                   disas           => 0,
                   dbguart         => 0,
                   pclow           => 2,
                   clk_freq        => 25000,
+                  IS_RADHARD      => 1,
                   NB_CPU          => 1,
                   ENABLE_FPU      => 1,
                   FPU_NETLIST     => 0,
                   ENABLE_DSU      => 1,
                   ENABLE_AHB_UART => 1,
                   ENABLE_APB_UART => 1,
                   ENABLE_IRQMP    => 1,
                   ENABLE_GPT      => 1,
                   NB_AHB_MASTER   => NB_AHB_MASTER,
                   NB_AHB_SLAVE    => NB_AHB_SLAVE,
                   NB_APB_SLAVE    => NB_APB_SLAVE,
                   ADDRESS_SIZE    => 20,
                   USES_IAP_MEMCTRLR => 0)
                 PORT MAP (
                   clk       => clk_25,
                   reset     => rstn_25,
                   errorn    => errorn,
                   ahbrxd    => TXD1,
                   ahbtxd    => RXD1,
                   urxd1     => TXD2,
                   utxd1     => RXD2,
                   address   => SRAM_A,
                   data      => SRAM_DQ,
                   nSRAM_BE0 => SRAM_nBE(0),
                   nSRAM_BE1 => SRAM_nBE(1),
                   nSRAM_BE2 => SRAM_nBE(2),
                   nSRAM_BE3 => SRAM_nBE(3),
                   nSRAM_WE  => SRAM_nWE,
                   nSRAM_CE  => SRAM_CE_s,
                   nSRAM_OE  => SRAM_nOE,
                   nSRAM_READY => '0',
                   SRAM_MBE    => OPEN,
                   apbi_ext   => apbi_ext,
                   apbo_ext   => apbo_ext,
                   ahbi_s_ext => ahbi_s_ext,
                   ahbo_s_ext => ahbo_s_ext,
                   ahbi_m_ext => ahbi_m_ext,
                   ahbo_m_ext => ahbo_m_ext);
               SRAM_CE <= SRAM_CE_s(0);
             -------------------------------------------------------------------------------
             -- APB_LFR_MANAGEMENT ---------------------------------------------------------
             -------------------------------------------------------------------------------
               apb_lfr_management_1 : apb_lfr_management
                 GENERIC MAP (
                   pindex           => 6,
                   paddr            => 6,
                   pmask            => 16#fff#,
                   FIRST_DIVISION   => 374,  -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
                   NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
                 PORT MAP (
                   clk25MHz      => clk_25,
                   clk24_576MHz  => clk_24,          -- 49.152MHz/2
                   resetn        => rstn_25,
                   grspw_tick    => swno.tickout,
                   apbi          => apbi_ext,
                   apbo          => apbo_ext(6),
                   HK_sample     => sample_hk,
                   HK_val        => sample_val,
                   HK_sel        => HK_SEL,
                   coarse_time   => coarse_time,
                   fine_time     => fine_time,
                   LFR_soft_rstn => LFR_soft_rstn
                   );
             -----------------------------------------------------------------------
             ---  SpaceWire --------------------------------------------------------
             -----------------------------------------------------------------------
               SPW_EN <= '1';
               spw_clk     <= clk_50_s;
               spw_rxtxclk <= spw_clk;
               spw_rxclkn  <= NOT spw_rxtxclk;
               -- PADS for SPW1
               spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_DIN, dtmp(0));
               spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_SIN, stmp(0));
               spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_DOUT, swno.d(0));
               spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_SOUT, swno.s(0));
               -- PADS FOR SPW2
               spw2_rxd_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (SPW_RED_SIN, dtmp(1));
               spw2_rxs_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (SPW_RED_DIN, stmp(1));
               spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_RED_DOUT, swno.d(1));
               spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_RED_SOUT, swno.s(1));
               -- GRSPW PHY
               --spw1_input: if CFG_SPW_GRSPW = 1 generate
               spw_inputloop : FOR j IN 0 TO 1 GENERATE
                 spw_phy0 : grspw_phy
                   GENERIC MAP(
                     tech         => apa3e,
                     rxclkbuftype => 1,
                     scantest     => 0)
                   PORT MAP(
                     rxrst    => swno.rxrst,
                     di       => dtmp(j),
                     si       => stmp(j),
                     rxclko   => spw_rxclk(j),
                     do       => swni.d(j),
                     ndo      => swni.nd(j*5+4 DOWNTO j*5),
                     dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
               END GENERATE spw_inputloop;
               swni.rmapnodeaddr <= (OTHERS => '0');
               -- SPW core
               sw0 : grspwm GENERIC MAP(
                 tech         => apa3e,
                 hindex       => 1,
                 pindex       => 5,
                 paddr        => 5,
                 pirq         => 11,
                 sysfreq      => 25000,              -- CPU_FREQ
                 rmap         => 1,
                 rmapcrc      => 1,
                 fifosize1    => 16,
                 fifosize2    => 16,
                 rxclkbuftype => 1,
                 rxunaligned  => 0,
                 rmapbufs     => 4,
                 ft           => 0,
                 netlist      => 0,
                 ports        => 2,
                 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
                 memtech      => apa3e,
                 destkey      => 2,
                 spwcore      => 1
                 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
                 --output_type => CFG_SPW_OUTPUT,  -- not used byt the spw core 1
                 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
                 )
                 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
                          spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
                          ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
                          swni, swno);
               swni.tickin      <= '0';
               swni.rmapen      <= '1';
               swni.clkdiv10    <= "00000100";       -- 10 MHz / (4 + 1) = 10 MHz
               swni.tickinraw   <= '0';
               swni.timein      <= (OTHERS => '0');
               swni.dcrstval    <= (OTHERS => '0');
               swni.timerrstval <= (OTHERS => '0');
             -------------------------------------------------------------------------------
             -- LFR ------------------------------------------------------------------------
             -------------------------------------------------------------------------------
               LFR_rstn <= LFR_soft_rstn AND rstn_25;
               --LFR_rstn <= rstn_25;
               lpp_lfr_1 : lpp_lfr
                 GENERIC MAP (
                   Mem_use                => use_RAM,
                   nb_data_by_buffer_size => 32,
                   nb_snapshot_param_size => 32,
                   delta_vector_size      => 32,
                   delta_vector_size_f0_2 => 7,          -- log2(96)
                   pindex                 => 15,
                   paddr                  => 15,
                   pmask                  => 16#fff#,
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
                   top_lfr_version        => X"000138")  -- aa.bb.cc version
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => LFR_rstn,
                   sample_B        => sample_s(2 DOWNTO 0),
                   sample_E        => sample_s(7 DOWNTO 3),
                   sample_val      => sample_val,
                   apbi            => apbi_ext,
                   apbo            => apbo_ext(15),
                   ahbi            => ahbi_m_ext,
                   ahbo            => ahbo_m_ext(2),
                   coarse_time     => coarse_time,
                   fine_time       => fine_time,
                   data_shaping_BW => bias_fail_sw_sig,
                   debug_vector    => lfr_debug_vector,
                   debug_vector_ms => lfr_debug_vector_ms
                   );
               observation_reg(11 DOWNTO 0)      <= lfr_debug_vector;
               observation_reg(31 DOWNTO 12)     <= (OTHERS => '0');
               observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
               observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
               IO0                               <= rstn_25;
               IO1                               <= lfr_debug_vector_ms(0);  -- LFR MS FFT data_valid
               IO2                               <= lfr_debug_vector_ms(0);  -- LFR MS FFT ready
               IO3                               <= lfr_debug_vector(0);  -- LFR APBREG error_buffer_full
               IO4                               <= lfr_debug_vector(1);  -- LFR APBREG reg_sp.status_error_buffer_full
               IO5                               <= lfr_debug_vector(8);  -- LFR APBREG  ready_matrix_f2
               IO6                               <= lfr_debug_vector(9);  -- LFR APBREG reg0_ready_matrix_f2
               IO7                               <= lfr_debug_vector(10);  -- LFR APBREG reg0_ready_matrix_f2
               all_sample : FOR I IN 7 DOWNTO 0 GENERATE
                 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
               END GENERATE all_sample;
               top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
                 GENERIC MAP(
                   ChannelCount    => 8,
                   SampleNbBits    => 14,
                   ncycle_cnv_high => 40,  -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
                   ncycle_cnv      => 249)           -- 49 152 000 / 98304 /2
                 PORT MAP (
                   -- CONV
                   cnv_clk    => clk_24,
                   cnv_rstn   => rstn_25,
                   cnv        => ADC_nCS_sig,
                   -- DATA
                   clk        => clk_25,
                   rstn       => rstn_25,
                   sck        => ADC_CLK_sig,
                   sdo        => ADC_SDO_sig,
                   -- SAMPLE
                   sample     => sample,
                   sample_val => sample_val);
               --IO10 <= ADC_SDO_sig(5);
               --IO9  <= ADC_SDO_sig(4);
               --IO8  <= ADC_SDO_sig(3);
               ADC_nCS     <= ADC_nCS_sig;
               ADC_CLK     <= ADC_CLK_sig;
               ADC_SDO_sig <= ADC_SDO;
               sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
                            "0010001000100010" WHEN HK_SEL = "01" ELSE
                            "0100010001000100" WHEN HK_SEL = "10" ELSE
                            (OTHERS => '0');
             ----------------------------------------------------------------------
             ---  GPIO  -----------------------------------------------------------
             ----------------------------------------------------------------------
               grgpio0 : grgpio
                 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
                 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
               gpioi.sig_en <= (OTHERS => '0');
               gpioi.sig_in <= (OTHERS => '0');
               gpioi.din    <= (OTHERS => '0');
               --pio_pad_0 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
               --pio_pad_1 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
               --pio_pad_2 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
               --pio_pad_3 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
               --pio_pad_4 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
               --pio_pad_5 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
               --pio_pad_6 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
               --pio_pad_7 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
               PROCESS (clk_25, rstn_25)
               BEGIN  -- PROCESS
                 IF rstn_25 = '0' THEN               -- asynchronous reset (active low)
                   --    --IO0  <= '0';
                   --    IO1  <= '0';
                   --    IO2  <= '0';
                   --    IO3  <= '0';
                   --    IO4  <= '0';
                   --    IO5  <= '0';
                   --    IO6  <= '0';
                   --    IO7  <= '0';
                   IO8  <= '0';
                   IO9  <= '0';
                   IO10 <= '0';
                   IO11 <= '0';
                 ELSIF clk_25'EVENT AND clk_25 = '1' THEN  -- rising clock edge
                   CASE gpioo.dout(2 DOWNTO 0) IS
                     WHEN "011" =>
                       --        --IO0  <= observation_reg(0 );
                       --        IO1  <= observation_reg(1 );
                       --        IO2  <= observation_reg(2 );
                       --        IO3  <= observation_reg(3 );
                       --        IO4  <= observation_reg(4 );
                       --        IO5  <= observation_reg(5 );
                       --        IO6  <= observation_reg(6 );
                       --        IO7  <= observation_reg(7 );
                       IO8  <= observation_reg(8);
                       IO9  <= observation_reg(9);
                       IO10 <= observation_reg(10);
                       IO11 <= observation_reg(11);
                     WHEN "001" =>
                       --        --IO0  <= observation_reg(0  + 12);
                       --        IO1  <= observation_reg(1  + 12);
                       --        IO2  <= observation_reg(2  + 12);
                       --        IO3  <= observation_reg(3  + 12);
                       --        IO4  <= observation_reg(4  + 12);
                       --        IO5  <= observation_reg(5  + 12);
                       --        IO6  <= observation_reg(6  + 12);
                       --        IO7  <= observation_reg(7  + 12);
                       IO8  <= observation_reg(8 + 12);
                       IO9  <= observation_reg(9 + 12);
                       IO10 <= observation_reg(10 + 12);
                       IO11 <= observation_reg(11 + 12);
                     WHEN "010" =>
                       --        --IO0  <= observation_reg(0  + 12 + 12);
                       --        IO1  <= observation_reg(1  + 12 + 12);
                       --        IO2  <= observation_reg(2  + 12 + 12);
                       --        IO3  <= observation_reg(3  + 12 + 12);
                       --        IO4  <= observation_reg(4  + 12 + 12);
                       --        IO5  <= observation_reg(5  + 12 + 12);
                       --        IO6  <= observation_reg(6  + 12 + 12);
                       --        IO7  <= observation_reg(7  + 12 + 12);
                       IO8  <= '0';
                       IO9  <= '0';
                       IO10 <= '0';
                       IO11 <= '0';
                     WHEN "000" =>
                       --        --IO0  <= observation_vector_0(0 );
                       --        IO1  <= observation_vector_0(1 );
                       --        IO2  <= observation_vector_0(2 );
                       --        IO3  <= observation_vector_0(3 );
                       --        IO4  <= observation_vector_0(4 );
                       --        IO5  <= observation_vector_0(5 );
                       --        IO6  <= observation_vector_0(6 );
                       --        IO7  <= observation_vector_0(7 );
                       IO8  <= observation_vector_0(8);
                       IO9  <= observation_vector_0(9);
                       IO10 <= observation_vector_0(10);
                       IO11 <= observation_vector_0(11);
                     WHEN "100" =>
                       --        --IO0  <= observation_vector_1(0 );
                       --        IO1  <= observation_vector_1(1 );
                       --        IO2  <= observation_vector_1(2 );
                       --        IO3  <= observation_vector_1(3 );
                       --        IO4  <= observation_vector_1(4 );
                       --        IO5  <= observation_vector_1(5 );
                       --        IO6  <= observation_vector_1(6 );
                       --        IO7  <= observation_vector_1(7 );
                       IO8  <= observation_vector_1(8);
                       IO9  <= observation_vector_1(9);
                       IO10 <= observation_vector_1(10);
                       IO11 <= observation_vector_1(11);
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
                 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
                   apbo_ext(I) <= apb_none;
                 END GENERATE apbo_ext_not_used;
               END GENERATE all_apbo_ext;
               all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
                 ahbo_s_ext(I) <= ahbs_none;
               END GENERATE all_ahbo_ext;
               all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
                 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
                   ahbo_m_ext(I) <= ahbm_none;
                 END GENERATE ahbo_m_ext_not_used;
               END GENERATE all_ahbo_m_ext;
             END beh;

lib/lpp/lpp_leon3_soc/leon3_soc.vhd +286 -211

             -----------------------------------------------------------------------------
             --  LEON3 Demonstration design
             --  Copyright (C) 2004 Jiri Gaisler, Gaisler Research
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 2 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY gaisler;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.spacewire.ALL;              -- PLE
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
             LIBRARY iap;
-            USE iap.memctrl.all;
+            USE iap.memctrl.ALL;
             ENTITY leon3_soc IS
               GENERIC (
-                fabtech : INTEGER := apa3e;
+                fabtech           : INTEGER := apa3e;
-                memtech : INTEGER := apa3e;
+                memtech           : INTEGER := apa3e;
-                padtech : INTEGER := inferred;
+                padtech           : INTEGER := inferred;
-                clktech : INTEGER := inferred;
+                clktech           : INTEGER := inferred;
-                disas   : INTEGER := 0;     -- Enable disassembly to console
+                disas             : INTEGER := 0;      -- Enable disassembly to console
-                dbguart : INTEGER := 0;     -- Print UART on console
+                dbguart           : INTEGER := 0;      -- Print UART on console
-                pclow   : INTEGER := 2;
+                pclow             : INTEGER := 2;
                 --
-                clk_freq : INTEGER := 25000;       --kHz
+                clk_freq          : INTEGER := 25000;  --kHz
+                --
+                IS_RADHARD        : INTEGER := 0;
                 --
-                NB_CPU      : INTEGER := 1;
+                NB_CPU            : INTEGER := 1;
-                ENABLE_FPU  : INTEGER := 1;
+                ENABLE_FPU        : INTEGER := 1;
-                FPU_NETLIST : INTEGER := 1;
+                FPU_NETLIST       : INTEGER := 1;
-                ENABLE_DSU : INTEGER := 1;
+                ENABLE_DSU        : INTEGER := 1;
-                ENABLE_AHB_UART : INTEGER := 1;
+                ENABLE_AHB_UART   : INTEGER := 1;
-                ENABLE_APB_UART : INTEGER := 1;
+                ENABLE_APB_UART   : INTEGER := 1;
-                ENABLE_IRQMP : INTEGER := 1;
+                ENABLE_IRQMP      : INTEGER := 1;
-                ENABLE_GPT : INTEGER := 1;
+                ENABLE_GPT        : INTEGER := 1;
                 --
-                NB_AHB_MASTER : INTEGER := 1;
+                NB_AHB_MASTER     : INTEGER := 1;
-                NB_AHB_SLAVE  : INTEGER := 1;
+                NB_AHB_SLAVE      : INTEGER := 1;
-                NB_APB_SLAVE  : INTEGER := 1;
+                NB_APB_SLAVE      : INTEGER := 1;
                 --
                 ADDRESS_SIZE      : INTEGER := 20;
                 USES_IAP_MEMCTRLR : INTEGER := 0
                 );
               PORT (
-                clk    : IN STD_ULOGIC;
+                clk   : IN STD_ULOGIC;
-                reset  : IN STD_ULOGIC;
+                reset : IN STD_ULOGIC;
                 errorn : OUT STD_ULOGIC;
                 -- UART AHB ---------------------------------------------------------------
                 ahbrxd : IN  STD_ULOGIC;            -- DSU rx data
                 ahbtxd : OUT STD_ULOGIC;            -- DSU tx data
                 -- UART APB ---------------------------------------------------------------
                 urxd1 : IN  STD_ULOGIC;             -- UART1 rx data
                 utxd1 : OUT STD_ULOGIC;             -- UART1 tx data
                 -- RAM --------------------------------------------------------------------
                 address     : OUT   STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
                 data        : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 nSRAM_BE0   : OUT   STD_LOGIC;
                 nSRAM_BE1   : OUT   STD_LOGIC;
                 nSRAM_BE2   : OUT   STD_LOGIC;
                 nSRAM_BE3   : OUT   STD_LOGIC;
                 nSRAM_WE    : OUT   STD_LOGIC;
-                nSRAM_CE    : OUT   STD_LOGIC_VECTOR(1 downto 0);
+                nSRAM_CE    : OUT   STD_LOGIC_VECTOR(1 DOWNTO 0);
                 nSRAM_OE    : OUT   STD_LOGIC;
                 nSRAM_READY : IN    STD_LOGIC;
                 SRAM_MBE    : INOUT STD_LOGIC;
                 -- APB --------------------------------------------------------------------
-                apbi_ext    : OUT apb_slv_in_type;
+                apbi_ext    : OUT   apb_slv_in_type;
-                apbo_ext    : IN  soc_apb_slv_out_vector(NB_APB_SLAVE-1+5  DOWNTO 5);
+                apbo_ext    : IN    soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
                 -- AHB_Slave --------------------------------------------------------------
-                ahbi_s_ext  : OUT ahb_slv_in_type;
+                ahbi_s_ext  : OUT   ahb_slv_in_type;
-                ahbo_s_ext  : IN  soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3  DOWNTO 3);
+                ahbo_s_ext  : IN    soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
                 -- AHB_Master -------------------------------------------------------------
-                ahbi_m_ext  : OUT AHB_Mst_In_Type;
+                ahbi_m_ext  : OUT   AHB_Mst_In_Type;
-                ahbo_m_ext  : IN  soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
+                ahbo_m_ext  : IN    soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
                 );
             END;
             ARCHITECTURE Behavioral OF leon3_soc IS
               -----------------------------------------------------------------------------
               -- CONFIG -------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- Clock generator
-              constant CFG_CLKMUL : integer := (1);
+              CONSTANT CFG_CLKMUL    : INTEGER := (1);
-              constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
+              CONSTANT CFG_CLKDIV    : INTEGER := (1);  -- divide 50MHz by 2 to get 25MHz
-              constant CFG_OCLKDIV : integer := (1);
+              CONSTANT CFG_OCLKDIV   : INTEGER := (1);
-              constant CFG_CLK_NOFB : integer := 0;
+              CONSTANT CFG_CLK_NOFB  : INTEGER := 0;
               -- LEON3 processor core
-              constant CFG_LEON3 : integer := 1;
+              CONSTANT CFG_LEON3     : INTEGER := 1;
-              constant CFG_NCPU  : integer := NB_CPU;
+              CONSTANT CFG_NCPU      : INTEGER := NB_CPU;
-              constant CFG_NWIN  : integer := (8); -- to be compatible with BCC and RCC
+              CONSTANT CFG_NWIN      : INTEGER := (8);  -- to be compatible with BCC and RCC
-              constant CFG_V8    : integer := 0;
+              CONSTANT CFG_V8        : INTEGER := 0;
-              constant CFG_MAC   : integer := 0;
+              CONSTANT CFG_MAC       : INTEGER := 0;
-              constant CFG_SVT    : integer := 0;
+              CONSTANT CFG_SVT       : INTEGER := 0;
-              constant CFG_RSTADDR : integer := 16#00000#;
+              CONSTANT CFG_RSTADDR   : INTEGER := 16#00000#;
-              constant CFG_LDDEL : integer := (1);
+              CONSTANT CFG_LDDEL     : INTEGER := (1);
-              constant CFG_NWP : integer := (0);
+              CONSTANT CFG_NWP       : INTEGER := (0);
-              constant CFG_PWD : integer := 1*2;
+              CONSTANT CFG_PWD       : INTEGER := 1*2;
-              constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
+              CONSTANT CFG_FPU       : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
               -- 1*(8 + 16 * 0) => grfpu-light
               -- 1*(8 + 16 * 1) => netlist
               -- 0*(8 + 16 * 0) => No FPU
               -- 0*(8 + 16 * 1) => No FPU;
-              constant CFG_ICEN : integer := 1;
+              CONSTANT CFG_ICEN      : INTEGER := 1;
-              constant CFG_ISETS : integer := 1;
+              CONSTANT CFG_ISETS     : INTEGER := 1;
-              constant CFG_ISETSZ : integer := 4;
+              CONSTANT CFG_ISETSZ    : INTEGER := 4;
-              constant CFG_ILINE : integer := 4;
+              CONSTANT CFG_ILINE     : INTEGER := 4;
-              constant CFG_IREPL : integer := 0;
+              CONSTANT CFG_IREPL     : INTEGER := 0;
-              constant CFG_ILOCK : integer := 0;
+              CONSTANT CFG_ILOCK     : INTEGER := 0;
-              constant CFG_ILRAMEN : integer := 0;
+              CONSTANT CFG_ILRAMEN   : INTEGER := 0;
-              constant CFG_ILRAMADDR: integer := 16#8E#;
+              CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
-              constant CFG_ILRAMSZ : integer := 1;
+              CONSTANT CFG_ILRAMSZ   : INTEGER := 1;
-              constant CFG_DCEN : integer := 1;
+              CONSTANT CFG_DCEN      : INTEGER := 1;
-              constant CFG_DSETS : integer := 1;
+              CONSTANT CFG_DSETS     : INTEGER := 1;
-              constant CFG_DSETSZ : integer := 4;
+              CONSTANT CFG_DSETSZ    : INTEGER := 4;
-              constant CFG_DLINE : integer := 4;
+              CONSTANT CFG_DLINE     : INTEGER := 4;
-              constant CFG_DREPL : integer := 0;
+              CONSTANT CFG_DREPL     : INTEGER := 0;
-              constant CFG_DLOCK : integer := 0;
+              CONSTANT CFG_DLOCK     : INTEGER := 0;
-              constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
+              CONSTANT CFG_DSNOOP    : INTEGER := 0 + 0 + 4*0;
-              constant CFG_DLRAMEN : integer := 0;
+              CONSTANT CFG_DLRAMEN   : INTEGER := 0;
-              constant CFG_DLRAMADDR: integer := 16#8F#;
+              CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
-              constant CFG_DLRAMSZ : integer := 1;
+              CONSTANT CFG_DLRAMSZ   : INTEGER := 1;
-              constant CFG_MMUEN : integer := 0;
+              CONSTANT CFG_MMUEN     : INTEGER := 0;
-              constant CFG_ITLBNUM : integer := 2;
+              CONSTANT CFG_ITLBNUM   : INTEGER := 2;
-              constant CFG_DTLBNUM : integer := 2;
+              CONSTANT CFG_DTLBNUM   : INTEGER := 2;
-              constant CFG_TLB_TYPE : integer := 1 + 0*2;
+              CONSTANT CFG_TLB_TYPE  : INTEGER := 1 + 0*2;
-              constant CFG_TLB_REP : integer := 1;
+              CONSTANT CFG_TLB_REP   : INTEGER := 1;
-              constant CFG_DSU : integer := ENABLE_DSU;
+              CONSTANT CFG_DSU   : INTEGER := ENABLE_DSU;
-              constant CFG_ITBSZ : integer := 0;
+              CONSTANT CFG_ITBSZ : INTEGER := 0;
-              constant CFG_ATBSZ : integer := 0;
+              CONSTANT CFG_ATBSZ : INTEGER := 0;
               -- AMBA settings
-              constant CFG_DEFMST : integer := (0);
+              CONSTANT CFG_DEFMST  : INTEGER := (0);
-              constant CFG_RROBIN : integer := 1;
+              CONSTANT CFG_RROBIN  : INTEGER := 1;
-              constant CFG_SPLIT : integer := 0;
+              CONSTANT CFG_SPLIT   : INTEGER := 0;
-              constant CFG_AHBIO : integer := 16#FFF#;
+              CONSTANT CFG_AHBIO   : INTEGER := 16#FFF#;
-              constant CFG_APBADDR : integer := 16#800#;
+              CONSTANT CFG_APBADDR : INTEGER := 16#800#;
               -- DSU UART
-              constant CFG_AHB_UART : integer := ENABLE_AHB_UART;
+              CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
               -- LEON2 memory controller
-              constant CFG_MCTRL_SDEN : integer := 0;
+              CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
               -- UART 1
-              constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART;
+              CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
-              constant CFG_UART1_FIFO : integer := 1;
+              CONSTANT CFG_UART1_FIFO   : INTEGER := 1;
               -- LEON3 interrupt controller
-              constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP;
+              CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
               -- Modular timer
-              constant CFG_GPT_ENABLE : integer := ENABLE_GPT;
+              CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
-              constant CFG_GPT_NTIM : integer := (2);
+              CONSTANT CFG_GPT_NTIM   : INTEGER := (2);
-              constant CFG_GPT_SW : integer := (8);
+              CONSTANT CFG_GPT_SW     : INTEGER := (8);
-              constant CFG_GPT_TW : integer := (32);
+              CONSTANT CFG_GPT_TW     : INTEGER := (32);
-              constant CFG_GPT_IRQ : integer := (8);
+              CONSTANT CFG_GPT_IRQ    : INTEGER := (8);
-              constant CFG_GPT_SEPIRQ : integer := 1;
+              CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
-              constant CFG_GPT_WDOGEN : integer := 0;
+              CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
-              constant CFG_GPT_WDOG : integer := 16#0#;
+              CONSTANT CFG_GPT_WDOG   : INTEGER := 16#0#;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- SIGNALs
               -----------------------------------------------------------------------------
-              CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
+              CONSTANT maxahbmsp  : INTEGER            := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
               -- CLK & RST --
-              SIGNAL clk2x      : STD_ULOGIC;
+              SIGNAL   clk2x      : STD_ULOGIC;
-              SIGNAL clkmn       : STD_ULOGIC;
+              SIGNAL   clkmn      : STD_ULOGIC;
-              SIGNAL clkm       : STD_ULOGIC;
+              SIGNAL   clkm       : STD_ULOGIC;
-              SIGNAL rstn       : STD_ULOGIC;
+              SIGNAL   rstn       : STD_ULOGIC;
-              SIGNAL rstraw     : STD_ULOGIC;
+              SIGNAL   rstraw     : STD_ULOGIC;
-              SIGNAL pciclk     : STD_ULOGIC;
+              SIGNAL   pciclk     : STD_ULOGIC;
-              SIGNAL sdclkl     : STD_ULOGIC;
+              SIGNAL   sdclkl     : STD_ULOGIC;
-              SIGNAL cgi        : clkgen_in_type;
+              SIGNAL   cgi        : clkgen_in_type;
-              SIGNAL cgo        : clkgen_out_type;
+              SIGNAL   cgo        : clkgen_out_type;
               --- AHB / APB
-              SIGNAL apbi       : apb_slv_in_type;
+              SIGNAL   apbi       : apb_slv_in_type;
-              SIGNAL apbo       : apb_slv_out_vector := (OTHERS => apb_none);
+              SIGNAL   apbo       : apb_slv_out_vector := (OTHERS => apb_none);
-              SIGNAL ahbsi      : ahb_slv_in_type;
+              SIGNAL   ahbsi      : ahb_slv_in_type;
-              SIGNAL ahbso      : ahb_slv_out_vector := (OTHERS => ahbs_none);
+              SIGNAL   ahbso      : ahb_slv_out_vector := (OTHERS => ahbs_none);
-              SIGNAL ahbmi      : ahb_mst_in_type;
+              SIGNAL   ahbmi      : ahb_mst_in_type;
-              SIGNAL ahbmo      : ahb_mst_out_vector := (OTHERS => ahbm_none);
+              SIGNAL   ahbmo      : ahb_mst_out_vector := (OTHERS => ahbm_none);
               --UART
-              SIGNAL ahbuarti   : uart_in_type;
+              SIGNAL   ahbuarti   : uart_in_type;
-              SIGNAL ahbuarto   : uart_out_type;
+              SIGNAL   ahbuarto   : uart_out_type;
-              SIGNAL apbuarti   : uart_in_type;
+              SIGNAL   apbuarti   : uart_in_type;
-              SIGNAL apbuarto   : uart_out_type;
+              SIGNAL   apbuarto   : uart_out_type;
               --MEM CTRLR
-              SIGNAL memi       : memory_in_type;
+              SIGNAL   memi       : memory_in_type;
-              SIGNAL memo       : memory_out_type;
+              SIGNAL   memo       : memory_out_type;
-              SIGNAL wpo        : wprot_out_type;
+              SIGNAL   wpo        : wprot_out_type;
-              SIGNAL sdo        : sdram_out_type;
+              SIGNAL   sdo        : sdram_out_type;
-              SIGNAl mbe        : std_logic;        -- enable memory programming
+              SIGNAL   mbe        : STD_LOGIC;      -- enable memory programming
-              SIGNAL mbe_drive  : std_logic;       -- drive the MBE memory signal
+              SIGNAL   mbe_drive  : STD_LOGIC;      -- drive the MBE memory signal
-              SIGNAL nSRAM_CE_s  : STD_LOGIC_VECTOR(1 downto 0);
+              SIGNAL   nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
-              SIGNAL nSRAM_OE_s    : STD_LOGIC;
+              SIGNAL   nSRAM_OE_s : STD_LOGIC;
               --IRQ
-              SIGNAL irqi       : irq_in_vector(0 TO CFG_NCPU-1);
+              SIGNAL   irqi       : irq_in_vector(0 TO CFG_NCPU-1);
-              SIGNAL irqo       : irq_out_vector(0 TO CFG_NCPU-1);
+              SIGNAL   irqo       : irq_out_vector(0 TO CFG_NCPU-1);
               --Timer
-              SIGNAL gpti       : gptimer_in_type;
+              SIGNAL   gpti       : gptimer_in_type;
-              SIGNAL gpto       : gptimer_out_type;
+              SIGNAL   gpto       : gptimer_out_type;
               --DSU
-              SIGNAL dbgi       : l3_debug_in_vector(0 TO CFG_NCPU-1);
+              SIGNAL   dbgi       : l3_debug_in_vector(0 TO CFG_NCPU-1);
-              SIGNAL dbgo       : l3_debug_out_vector(0 TO CFG_NCPU-1);
+              SIGNAL   dbgo       : l3_debug_out_vector(0 TO CFG_NCPU-1);
-              SIGNAL dsui       : dsu_in_type;
+              SIGNAL   dsui       : dsu_in_type;
-              SIGNAL dsuo       : dsu_out_type;
+              SIGNAL   dsuo       : dsu_out_type;
               -----------------------------------------------------------------------------
             BEGIN
             ----------------------------------------------------------------------
             ---  Reset and Clock generation  -------------------------------------
             ----------------------------------------------------------------------
               cgi.pllctrl <= "00";
               cgi.pllrst  <= rstraw;
               rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
               clkgen0 : clkgen                      -- clock generator
                 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
                              CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
                 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
             ----------------------------------------------------------------------
             ---  LEON3 processor / DSU / IRQ  ------------------------------------
             ----------------------------------------------------------------------
               l3 : IF CFG_LEON3 = 1 GENERATE
                 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
-                  u0 : leon3s                       -- LEON3 processor
+                  leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
-                    GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
+                    u0 : leon3s                       -- LEON3 processor
-, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
+                      GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
-                                 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
+, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
-                                 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
+                                   CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
-                                 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
+                                   CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
-                                 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
+                                   CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
-                    PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
+                                   CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
-                              irqi(i), irqo(i), dbgi(i), dbgo(i));
+                      PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
+                                irqi(i), irqo(i), dbgi(i), dbgo(i));
+                  END GENERATE leon3_non_radhard;
+                  leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
+                    cpu : ENTITY gaisler.leon3ft
+                      GENERIC MAP (
+                        HINDEX     => i,  --: integer;             --CPU_HINDEX,
+                        FABTECH    => fabtech,        --CFG_TECH,
+                        MEMTECH    => memtech,        --CFG_TECH,
+                        NWINDOWS   => CFG_NWIN,       --CFG_NWIN,
+                        DSU        => CFG_DSU,        --condSel (HAS_DEBUG, 1, 0),
+                        FPU        => CFG_FPU,        --CFG_FPU,
+                        V8         => CFG_V8,         --CFG_V8,
+                        CP         => 0,              --CFG_CP,
+                        MAC        => CFG_MAC,        --CFG_MAC,
+                        PCLOW      => pclow,          --CFG_PCLOW,
+                        NOTAG      => 0,              --CFG_NOTAG,
+                        NWP        => CFG_NWP,        --CFG_NWP,
+                        ICEN       => CFG_ICEN,       --CFG_ICEN,
+                        IREPL      => CFG_IREPL,      --CFG_IREPL,
+                        ISETS      => CFG_ISETS,      --CFG_ISETS,
+                        ILINESIZE  => CFG_ILINE,      --CFG_ILINE,
+                        ISETSIZE   => CFG_ISETSZ,     --CFG_ISETSZ,
+                        ISETLOCK   => CFG_ILOCK,      --CFG_ILOCK,
+                        DCEN       => CFG_DCEN,       --CFG_DCEN,
+                        DREPL      => CFG_DREPL,      --CFG_DREPL,
+                        DSETS      => CFG_DSETS,      --CFG_DSETS,
+                        DLINESIZE  => CFG_DLINE,      --CFG_DLINE,
+                        DSETSIZE   => CFG_DSETSZ,     --CFG_DSETSZ,
+                        DSETLOCK   => CFG_DLOCK,      --CFG_DLOCK,
+                        DSNOOP     => CFG_DSNOOP,     --CFG_DSNOOP,
+                        ILRAM      => CFG_ILRAMEN,    --CFG_ILRAMEN,
+                        ILRAMSIZE  => CFG_ILRAMSZ,    --CFG_ILRAMSZ,
+                        ILRAMSTART => CFG_ILRAMADDR,  --CFG_ILRAMADDR,
+                        DLRAM      => CFG_DLRAMEN,    --CFG_DLRAMEN,
+                        DLRAMSIZE  => CFG_DLRAMSZ,    --CFG_DLRAMSZ,
+                        DLRAMSTART => CFG_DLRAMADDR,  --CFG_DLRAMADDR,
+                        MMUEN      => CFG_MMUEN,      --CFG_MMUEN,
+                        ITLBNUM    => CFG_ITLBNUM,    --CFG_ITLBNUM,
+                        DTLBNUM    => CFG_DTLBNUM,    --CFG_DTLBNUM,
+                        TLB_TYPE   => CFG_TLB_TYPE,   --CFG_TLB_TYPE,
+                        TLB_REP    => CFG_TLB_REP,    --CFG_TLB_REP,
+                        LDDEL      => CFG_LDDEL,      --CFG_LDDEL,
+                        DISAS      => disas,          --condSel (SIM_ENABLED, 1, 0),
+                        TBUF       => CFG_ITBSZ,      --CFG_ITBSZ,
+                        PWD        => CFG_PWD,        --CFG_PWD,
+                        SVT        => CFG_SVT,        --CFG_SVT,
+                        RSTADDR    => CFG_RSTADDR,    --CFG_RSTADDR,
+                        SMP        => CFG_NCPU-1,     --CFG_NCPU-1,
+                        IUFT       => 2,  --: integer range 0 to 4;--CFG_IUFT_EN,
+                        FPFT       => 1,  --: integer range 0 to 4;--CFG_FPUFT_EN,
+                        CMFT       => 1,  --: integer range 0 to 1;--CFG_CACHE_FT_EN,
+                        IUINJ      => 0,  --: integer;             --CFG_RF_ERRINJ,
+                        CEINJ      => 0,  --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
+                        CACHED     => 0,  --: integer;             --CFG_DFIXED,
+                        NETLIST    => 0,  --: integer;             --CFG_LEON3_NETLIST,
+                        SCANTEST   => 0,  --: integer;             --CFG_SCANTEST,
+                        MMUPGSZ    => 0,  --: integer range 0 to 5;--CFG_MMU_PAGE,
+                        BP         => 1)              --CFG_BP
+                      PORT MAP (                      --
+                        rstn  => rstn,                --rst_n,
+                        clk   => clkm,                --clk,
+                        ahbi  => ahbmi,               --ahbmi,
+                        ahbo  => ahbmo(i),             --ahbmo(CPU_HINDEX),
+                        ahbsi => ahbsi,               --ahbsi,
+                        ahbso => ahbso,               --ahbso,
+                        irqi  => irqi(i),             --irqi(CPU_HINDEX),
+                        irqo  => irqo(i),             --irqo(CPU_HINDEX),
+                        dbgi  => dbgi(i),             --dbgi(CPU_HINDEX),
+                        dbgo  => dbgo(i),             --dbgo(CPU_HINDEX),
+                        gclk  => clkm                 --clk
+                        );
+                  END GENERATE leon3_radhard_i;
                 END GENERATE;
                 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
                 dsugen : IF CFG_DSU = 1 GENERATE
                   dsu0 : dsu3                       -- LEON3 Debug Support Unit
                     GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
                                  ncpu   => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
                     PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
                   dsui.enable <= '1';
                   dsui.break  <= '0';
                 END GENERATE;
               END GENERATE;
               nodsu : IF CFG_DSU = 0 GENERATE
-                ahbso(2) <= ahbs_none;
+                ahbso(2)    <= ahbs_none;
-                dsuo.tstop <= '0';
+                dsuo.tstop  <= '0';
                 dsuo.active <= '0';
               END GENERATE;
               irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
                 irqctrl0 : irqmp                    -- interrupt controller
                   GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
                   PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
               END GENERATE;
               irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
                 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
                   irqi(i).irl <= "0000";
                 END GENERATE;
                 apbo(2) <= apb_none;
               END GENERATE;
             ----------------------------------------------------------------------
             ---  Memory controllers  ---------------------------------------------
             ----------------------------------------------------------------------
-            ESAMEMCT: IF USES_IAP_MEMCTRLR =0 GENERATE
+              ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE
-              memctrlr : mctrl GENERIC MAP (
+                memctrlr : mctrl GENERIC MAP (
-                hindex  => 0,
+                  hindex  => 0,
-                pindex  => 0,
+                  pindex  => 0,
-                paddr   => 0,
+                  paddr   => 0,
-                srbanks => 1
+                  srbanks => 1
+                  )
-                PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
+                  PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
-               memi.bexcn  <= '1';
+                memi.bexcn <= '1';
-               memi.brdyn  <= '1';
+                memi.brdyn <= '1';
-              nSRAM_CE_s <= NOT (memo.ramsn(1 downto 0));
+                nSRAM_CE_s <= NOT (memo.ramsn(1 DOWNTO 0));
-              nSRAM_OE_s <= memo.ramoen(0);
+                nSRAM_OE_s <= memo.ramoen(0);
-            END GENERATE;
+              END GENERATE;
-            IAPMEMCT: IF USES_IAP_MEMCTRLR =1 GENERATE
+              IAPMEMCT : IF USES_IAP_MEMCTRLR = 1 GENERATE
-              memctrlr : srctrle_0ws
+                memctrlr : srctrle_0ws
-              GENERIC MAP(
+                  GENERIC MAP(
-                hindex  => 0,
+                    hindex   => 0,
-                pindex  => 0,
+                    pindex   => 0,
-                paddr   => 0,
+                    paddr    => 0,
-                srbanks => 2,
+                    srbanks  => 2,
-                banksz  => 8, --512k * 32
+                    banksz   => 8,                  --512k * 32
-                rmw     => 1,
+                    rmw      => 1,
-                --Aeroflex memory generics:
+                    --Aeroflex memory generics:
-                mprog   => 1,   -- program memory by default values after reset
+                    mprog    => 1,          -- program memory by default values after reset
-                mpsrate => 12,  -- default scrub rate period
+                    mpsrate  => 12,                 -- default scrub rate period
-                mpb2s   => 4,   -- default busy to scrub delay
+                    mpb2s    => 4,                  -- default busy to scrub delay
-                mpapb   => 1,   -- instantiate apb register
+                    mpapb    => 1,                  -- instantiate apb register
-                mchipcnt => 2,
+                    mchipcnt => 2,
-                mpenall => 1    -- when 0 program only E1 chip, else program all dies
+                    mpenall  => 1  -- when 0 program only E1 chip, else program all dies
+                    )
-              PORT MAP (
+                  PORT MAP (
-                rst     => rstn,
+                    rst       => rstn,
-                clk     => clkm,
+                    clk       => clkm,
-                ahbsi   => ahbsi,
+                    ahbsi     => ahbsi,
-                ahbso   => ahbso(0),
+                    ahbso     => ahbso(0),
-                apbi    => apbi,
+                    apbi      => apbi,
-                apbo    => apbo(0),
+                    apbo      => apbo(0),
-                sri     => memi,
+                    sri       => memi,
-                sro     => memo,
+                    sro       => memo,
-                --Aeroflex memory signals:
+                    --Aeroflex memory signals:
-                ucerr   => open,        -- uncorrectable error signal
+                    ucerr     => OPEN,              -- uncorrectable error signal
-                mbe     => mbe,        -- enable memory programming
+                    mbe       => mbe,               -- enable memory programming
-                mbe_drive => mbe_drive      -- drive the MBE memory signal
+                    mbe_drive => mbe_drive          -- drive the MBE memory signal
-              );
+                    );
-              memi.brdyn  <= nSRAM_READY;
+                memi.brdyn <= nSRAM_READY;
-              mbe_pad : iopad
+                mbe_pad : iopad
-              GENERIC MAP(tech => padtech)
+                  GENERIC MAP(tech => padtech)
-              PORT MAP(pad => SRAM_MBE,
+                  PORT MAP(pad => SRAM_MBE,
-                       i   => mbe,
+                           i   => mbe,
-                       en  => mbe_drive,
+                           en  => mbe_drive,
-                       o   => memi.bexcn );
+                           o   => memi.bexcn);
-              nSRAM_CE_s <= (memo.ramsn(1 downto 0));
+                nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
-              nSRAM_OE_s <= memo.oen;
+                nSRAM_OE_s <= memo.oen;
-            END GENERATE;
+              END GENERATE;
               memi.writen <= '1';
               memi.wrn    <= "1111";
               memi.bwidth <= "10";
               bdr : FOR i IN 0 TO 3 GENERATE
-                data_pad : iopadv GENERIC MAP (tech => padtech, width => 8,oepol=> USES_IAP_MEMCTRLR)
+                data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
                   PORT MAP (
                     data(31-i*8 DOWNTO 24-i*8),
                     memo.data(31-i*8 DOWNTO 24-i*8),
                     memo.bdrive(i),
                     memi.data(31-i*8 DOWNTO 24-i*8));
               END GENERATE;
               addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
                 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
-              rams_pad : outpadv GENERIC MAP (tech => padtech,width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
+              rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
-              oen_pad  : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
+              oen_pad  : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
-              nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
+              nBWE_pad : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_WE, memo.writen);
-              nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
+              nBWa_pad : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
-              nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
+              nBWb_pad : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
-              nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
+              nBWc_pad : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
-              nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
+              nBWd_pad : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
             ----------------------------------------------------------------------
             ---  AHB CONTROLLER  -------------------------------------------------
             ----------------------------------------------------------------------
               ahb0 : ahbctrl                        -- AHB arbiter/multiplexer
                 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
                              rrobin  => CFG_RROBIN, ioaddr => CFG_AHBIO,
                              ioen    => 0, nahbm => maxahbmsp, nahbs => 8)
                 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
             ----------------------------------------------------------------------
             ---  AHB UART  -------------------------------------------------------
             ----------------------------------------------------------------------
               dcomgen : IF CFG_AHB_UART = 1 GENERATE
                 dcom0 : ahbuart
                   GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
                   PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
                 dsurx_pad : inpad GENERIC MAP (tech  => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
                 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
               END GENERATE;
               nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
             ----------------------------------------------------------------------
             ---  APB Bridge  -----------------------------------------------------
             ----------------------------------------------------------------------
               apb0 : apbctrl                        -- AHB/APB bridge
                 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
                 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
             ----------------------------------------------------------------------
             ---  GPT Timer  ------------------------------------------------------
             ----------------------------------------------------------------------
               gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
                 timer0 : gptimer                    -- timer unit
                   GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
                                sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
                                nbits  => CFG_GPT_TW)
                   PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
                 gpti.dhalt  <= dsuo.tstop;
                 gpti.extclk <= '0';
               END GENERATE;
               notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
             ----------------------------------------------------------------------
             ---  APB UART  -------------------------------------------------------
             ----------------------------------------------------------------------
               ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
                 uart1 : apbuart                     -- UART 1
                   GENERIC MAP (pindex   => 1, paddr => 1, pirq => 2, console => dbguart,
                                fifosize => CFG_UART1_FIFO)
                   PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
                 apbuarti.rxd    <= urxd1;
                 apbuarti.extclk <= '0';
                 utxd1           <= apbuarto.txd;
                 apbuarti.ctsn   <= '0';
               END GENERATE;
               noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
             -------------------------------------------------------------------------------
             -- AMBA BUS -------------------------------------------------------------------
             -------------------------------------------------------------------------------
               -- APB --------------------------------------------------------------------
-              apbi_ext   <= apbi;
+              apbi_ext <= apbi;
-              all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
+              all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
-                max_16_apb: IF I + 5 < 16 GENERATE
+                max_16_apb : IF I + 5 < 16 GENERATE
-                  apbo(I+5)<= apbo_ext(I+5);
+                  apbo(I+5) <= apbo_ext(I+5);
                 END GENERATE max_16_apb;
               END GENERATE all_apb;
               -- AHB_Slave --------------------------------------------------------------
               ahbi_s_ext <= ahbsi;
-              all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
+              all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
-                max_16_ahbs: IF I + 3 < 16 GENERATE
+                max_16_ahbs : IF I + 3 < 16 GENERATE
                   ahbso(I+3) <= ahbo_s_ext(I+3);
                 END GENERATE max_16_ahbs;
               END GENERATE all_ahbs;
               -- AHB_Master -------------------------------------------------------------
               ahbi_m_ext <= ahbmi;
-              all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
+              all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
-                max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
+                max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
                   ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
                 END GENERATE max_16_ahbm;
               END GENERATE all_ahbm;
-            END Behavioral;
  No newline at end of file
+            END Behavioral;

lib/lpp/lpp_leon3_soc/leon3ft_soc.vhd +140 -71

             -----------------------------------------------------------------------------
             --  LEON3 Demonstration design
             --  Copyright (C) 2004 Jiri Gaisler, Gaisler Research
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 2 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY gaisler;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.spacewire.ALL;              -- PLE
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
             ENTITY leon3ft_soc IS
               GENERIC (
                 fabtech         : INTEGER := apa3e;
                 memtech         : INTEGER := apa3e;
                 padtech         : INTEGER := inferred;
                 clktech         : INTEGER := inferred;
                 disas           : INTEGER := 0;      -- Enable disassembly to console
                 dbguart         : INTEGER := 0;      -- Print UART on console
                 pclow           : INTEGER := 2;
                 --
                 clk_freq        : INTEGER := 25000;  --kHz
                 --
                 NB_CPU          : INTEGER := 1;
                 ENABLE_FPU      : INTEGER := 1;
                 FPU_NETLIST     : INTEGER := 1;
                 ENABLE_DSU      : INTEGER := 1;
                 ENABLE_AHB_UART : INTEGER := 1;
                 ENABLE_APB_UART : INTEGER := 1;
                 ENABLE_IRQMP    : INTEGER := 1;
                 ENABLE_GPT      : INTEGER := 1;
                 --
                 NB_AHB_MASTER   : INTEGER := 11;
                 NB_AHB_SLAVE    : INTEGER := 1;
                 NB_APB_SLAVE    : INTEGER := 2
                 );
               PORT (
                 clk   : IN STD_ULOGIC;
                 reset : IN STD_ULOGIC;
                 errorn : OUT STD_ULOGIC;
                 -- UART AHB ---------------------------------------------------------------
                 ahbrxd : IN  STD_ULOGIC;            -- DSU rx data
                 ahbtxd : OUT STD_ULOGIC;            -- DSU tx data
                 -- UART APB ---------------------------------------------------------------
                 urxd1 : IN  STD_ULOGIC;             -- UART1 rx data
                 utxd1 : OUT STD_ULOGIC;             -- UART1 tx data
                 -- RAM --------------------------------------------------------------------
                 address   : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
                 data      : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 nSRAM_BE0 : OUT   STD_LOGIC;
                 nSRAM_BE1 : OUT   STD_LOGIC;
                 nSRAM_BE2 : OUT   STD_LOGIC;
                 nSRAM_BE3 : OUT   STD_LOGIC;
                 nSRAM_WE  : OUT   STD_LOGIC;
                 nSRAM_CE  : OUT   STD_LOGIC;
                 nSRAM_OE  : OUT   STD_LOGIC;
                 -- APB --------------------------------------------------------------------
                 apbi_ext   : OUT apb_slv_in_type;
                 apbo_ext   : IN  soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
                 -- AHB_Slave --------------------------------------------------------------
                 ahbi_s_ext : OUT ahb_slv_in_type;
                 ahbo_s_ext : IN  soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
                 -- AHB_Master -------------------------------------------------------------
                 ahbi_m_ext : OUT AHB_Mst_In_Type;
                 ahbo_m_ext : IN  soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
                 );
             END;
             ARCHITECTURE Behavioral OF leon3ft_soc IS
               -----------------------------------------------------------------------------
               -- CONFIG -------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- Clock generator
               CONSTANT CFG_CLKMUL    : INTEGER := (1);
               CONSTANT CFG_CLKDIV    : INTEGER := (1);  -- divide 50MHz by 2 to get 25MHz
               CONSTANT CFG_OCLKDIV   : INTEGER := (1);
               CONSTANT CFG_CLK_NOFB  : INTEGER := 0;
               -- LEON3 processor core
               CONSTANT CFG_LEON3     : INTEGER := 1;
               CONSTANT CFG_NCPU      : INTEGER := NB_CPU;
               CONSTANT CFG_NWIN      : INTEGER := (8);  -- to be compatible with BCC and RCC
               CONSTANT CFG_V8        : INTEGER := 0;
               CONSTANT CFG_MAC       : INTEGER := 0;
               CONSTANT CFG_SVT       : INTEGER := 0;
               CONSTANT CFG_RSTADDR   : INTEGER := 16#00000#;
               CONSTANT CFG_LDDEL     : INTEGER := (1);
               CONSTANT CFG_NWP       : INTEGER := (0);
               CONSTANT CFG_PWD       : INTEGER := 1*2;
               CONSTANT CFG_FPU       : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
               -- 1*(8 + 16 * 0) => grfpu-light
               -- 1*(8 + 16 * 1) => netlist
               -- 0*(8 + 16 * 0) => No FPU
               -- 0*(8 + 16 * 1) => No FPU;
               CONSTANT CFG_ICEN      : INTEGER := 1;
               CONSTANT CFG_ISETS     : INTEGER := 1;
               CONSTANT CFG_ISETSZ    : INTEGER := 4;
               CONSTANT CFG_ILINE     : INTEGER := 4;
               CONSTANT CFG_IREPL     : INTEGER := 0;
               CONSTANT CFG_ILOCK     : INTEGER := 0;
               CONSTANT CFG_ILRAMEN   : INTEGER := 0;
               CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
               CONSTANT CFG_ILRAMSZ   : INTEGER := 1;
               CONSTANT CFG_DCEN      : INTEGER := 1;
               CONSTANT CFG_DSETS     : INTEGER := 1;
               CONSTANT CFG_DSETSZ    : INTEGER := 4;
               CONSTANT CFG_DLINE     : INTEGER := 4;
               CONSTANT CFG_DREPL     : INTEGER := 0;
               CONSTANT CFG_DLOCK     : INTEGER := 0;
               CONSTANT CFG_DSNOOP    : INTEGER := 0 + 0 + 4*0;
               CONSTANT CFG_DLRAMEN   : INTEGER := 0;
               CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
               CONSTANT CFG_DLRAMSZ   : INTEGER := 1;
               CONSTANT CFG_MMUEN     : INTEGER := 0;
               CONSTANT CFG_ITLBNUM   : INTEGER := 2;
               CONSTANT CFG_DTLBNUM   : INTEGER := 2;
               CONSTANT CFG_TLB_TYPE  : INTEGER := 1 + 0*2;
               CONSTANT CFG_TLB_REP   : INTEGER := 1;
               CONSTANT CFG_DSU   : INTEGER := ENABLE_DSU;
               CONSTANT CFG_ITBSZ : INTEGER := 0;
               CONSTANT CFG_ATBSZ : INTEGER := 0;
               -- AMBA settings
               CONSTANT CFG_DEFMST  : INTEGER := (0);
               CONSTANT CFG_RROBIN  : INTEGER := 1;
               CONSTANT CFG_SPLIT   : INTEGER := 0;
               CONSTANT CFG_AHBIO   : INTEGER := 16#FFF#;
               CONSTANT CFG_APBADDR : INTEGER := 16#800#;
               -- DSU UART
               CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
               -- LEON2 memory controller
               CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
               -- UART 1
               CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
               CONSTANT CFG_UART1_FIFO   : INTEGER := 1;
               -- LEON3 interrupt controller
               CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
               -- Modular timer
               CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
               CONSTANT CFG_GPT_NTIM   : INTEGER := (2);
               CONSTANT CFG_GPT_SW     : INTEGER := (8);
               CONSTANT CFG_GPT_TW     : INTEGER := (32);
               CONSTANT CFG_GPT_IRQ    : INTEGER := (8);
               CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
               CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
               CONSTANT CFG_GPT_WDOG   : INTEGER := 16#0#;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- SIGNALs
               -----------------------------------------------------------------------------
               CONSTANT maxahbmsp : INTEGER            := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
               -- CLK & RST --
               SIGNAL   clk2x     : STD_ULOGIC;
               SIGNAL   clkmn     : STD_ULOGIC;
               SIGNAL   clkm      : STD_ULOGIC;
               SIGNAL   rstn      : STD_ULOGIC;
               SIGNAL   rstraw    : STD_ULOGIC;
               SIGNAL   pciclk    : STD_ULOGIC;
               SIGNAL   sdclkl    : STD_ULOGIC;
               SIGNAL   cgi       : clkgen_in_type;
               SIGNAL   cgo       : clkgen_out_type;
               --- AHB / APB
               SIGNAL   apbi      : apb_slv_in_type;
               SIGNAL   apbo      : apb_slv_out_vector := (OTHERS => apb_none);
               SIGNAL   ahbsi     : ahb_slv_in_type;
               SIGNAL   ahbso     : ahb_slv_out_vector := (OTHERS => ahbs_none);
               SIGNAL   ahbmi     : ahb_mst_in_type;
               SIGNAL   ahbmo     : ahb_mst_out_vector := (OTHERS => ahbm_none);
               --UART
               SIGNAL   ahbuarti  : uart_in_type;
               SIGNAL   ahbuarto  : uart_out_type;
               SIGNAL   apbuarti  : uart_in_type;
               SIGNAL   apbuarto  : uart_out_type;
               --MEM CTRLR
               SIGNAL   memi      : memory_in_type;
               SIGNAL   memo      : memory_out_type;
               SIGNAL   wpo       : wprot_out_type;
               SIGNAL   sdo       : sdram_out_type;
               --IRQ
               SIGNAL   irqi      : irq_in_vector(0 TO CFG_NCPU-1);
               SIGNAL   irqo      : irq_out_vector(0 TO CFG_NCPU-1);
               --Timer
               SIGNAL   gpti      : gptimer_in_type;
               SIGNAL   gpto      : gptimer_out_type;
               --DSU
               SIGNAL   dbgi      : l3_debug_in_vector(0 TO CFG_NCPU-1);
               SIGNAL   dbgo      : l3_debug_out_vector(0 TO CFG_NCPU-1);
               SIGNAL   dsui      : dsu_in_type;
               SIGNAL   dsuo      : dsu_out_type;
               -----------------------------------------------------------------------------
               SIGNAL nSRAM_CE_s : STD_LOGIC;
             BEGIN
             ----------------------------------------------------------------------
             ---  Reset and Clock generation  -------------------------------------
             ----------------------------------------------------------------------
               cgi.pllctrl <= "00";
               cgi.pllrst  <= rstraw;
               rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
               clkgen0 : clkgen                      -- clock generator
                 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
                              CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
                 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
             ----------------------------------------------------------------------
             ---  LEON3 processor / DSU / IRQ  ------------------------------------
             ----------------------------------------------------------------------
               l3 : IF CFG_LEON3 = 1 GENERATE
-                cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
+                cpu: entity gaisler.leon3ft
-                  u0 : leon3ft
+                  generic map (
-                    GENERIC MAP (
+                    HINDEX          =>  i, --: integer;             --CPU_HINDEX,
-                      hindex     => i, --: integer;
+                    FABTECH         =>  fabtech,                    --CFG_TECH,
-                      fabtech    => fabtech,
+                    MEMTECH         =>  memtech,                    --CFG_TECH,
-                      memtech    => memtech,
+                    NWINDOWS        =>  CFG_NWIN,                   --CFG_NWIN,
-                      nwindows   => CFG_NWIN,
+                    DSU             =>  CFG_DSU,                    --condSel (HAS_DEBUG, 1, 0),
-                      dsu        => CFG_DSU,
+                    FPU             =>  CFG_FPU,                    --CFG_FPU,
-                      fpu        => CFG_FPU,
+                    V8              =>  CFG_V8,                     --CFG_V8,
-                      v8         => CFG_V8,
+                    CP              =>  0,                          --CFG_CP,
-                      cp         => 0,
+                    MAC             =>  CFG_MAC,                    --CFG_MAC,
-                      mac        => CFG_MAC,
+                    PCLOW           =>  pclow,                      --CFG_PCLOW,
-                      pclow      => pclow,
+                    NOTAG           =>  0,                          --CFG_NOTAG,
-                      notag      => 0,
+                    NWP             =>  CFG_NWP,                    --CFG_NWP,
-                      nwp        => CFG_NWP,
+                    ICEN            =>  CFG_ICEN,                   --CFG_ICEN,
-                      icen       => CFG_ICEN,
+                    IREPL           =>  CFG_IREPL,                  --CFG_IREPL,
-                      irepl      => CFG_IREPL,
+                    ISETS           =>  CFG_ISETS,                  --CFG_ISETS,
-                      isets      => CFG_ISETS,
+                    ILINESIZE       =>  CFG_ILINE,                  --CFG_ILINE,
-                      ilinesize  => CFG_ILINE,
+                    ISETSIZE        =>  CFG_ISETSZ,                 --CFG_ISETSZ,
-                      isetsize   => CFG_ISETSZ,
+                    ISETLOCK        =>  CFG_ILOCK,                  --CFG_ILOCK,
-                      isetlock   => CFG_ILOCK,
+                    DCEN            =>  CFG_DCEN,                   --CFG_DCEN,
-                      dcen       => CFG_DCEN,
+                    DREPL           =>  CFG_DREPL,                  --CFG_DREPL,
-                      drepl      => CFG_DREPL,
+                    DSETS           =>  CFG_DSETS,                  --CFG_DSETS,
-                      dsets      => CFG_DSETS,
+                    DLINESIZE       =>  CFG_DLINE,                  --CFG_DLINE,
-                      dlinesize  => CFG_DLINE,
+                    DSETSIZE        =>  CFG_DSETSZ,                 --CFG_DSETSZ,
-                      dsetsize   => CFG_DSETSZ,
+                    DSETLOCK        =>  CFG_DLOCK,                  --CFG_DLOCK,
-                      dsetlock   => CFG_DLOCK,
+                    DSNOOP          =>  CFG_DSNOOP,                 --CFG_DSNOOP,
-                      dsnoop     => CFG_DSNOOP,
+                    ILRAM           =>  CFG_ILRAMEN,                --CFG_ILRAMEN,
-                      ilram      => CFG_ILRAMEN,
+                    ILRAMSIZE       =>  CFG_ILRAMSZ,                --CFG_ILRAMSZ,
-                      ilramsize  => CFG_ILRAMSZ,
+                    ILRAMSTART      =>  CFG_ILRAMADDR,              --CFG_ILRAMADDR,
-                      ilramstart => CFG_ILRAMADDR,
+                    DLRAM           =>  CFG_DLRAMEN,                --CFG_DLRAMEN,
-                      dlram      => CFG_DLRAMEN,
+                    DLRAMSIZE       =>  CFG_DLRAMSZ,                --CFG_DLRAMSZ,
-                      dlramsize  => CFG_DLRAMSZ,
+                    DLRAMSTART      =>  CFG_DLRAMADDR,              --CFG_DLRAMADDR,
-                      dlramstart => CFG_DLRAMADDR,
+                    MMUEN           =>  CFG_MMUEN,                  --CFG_MMUEN,
-                      mmuen      => CFG_MMUEN,
+                    ITLBNUM         =>  CFG_ITLBNUM,                --CFG_ITLBNUM,
-                      itlbnum    => CFG_ITLBNUM,
+                    DTLBNUM         =>  CFG_DTLBNUM,                --CFG_DTLBNUM,
-                      dtlbnum    => CFG_DTLBNUM,
+                    TLB_TYPE        =>  CFG_TLB_TYPE,               --CFG_TLB_TYPE,
-                      tlb_type   => CFG_TLB_TYPE,
+                    TLB_REP         =>  CFG_TLB_REP,                --CFG_TLB_REP,
-                      tlb_rep    => CFG_TLB_REP,
+                    LDDEL           =>  CFG_LDDEL,                  --CFG_LDDEL,
-                      lddel      => CFG_LDDEL,
+                    DISAS           =>  disas,                      --condSel (SIM_ENABLED, 1, 0),
-                      disas      => disas,
+                    TBUF            =>  CFG_ITBSZ,                  --CFG_ITBSZ,
-                      tbuf       => CFG_ITBSZ,
+                    PWD             =>  CFG_PWD,                    --CFG_PWD,
-                      pwd        => CFG_PWD,
+                    SVT             =>  CFG_SVT,                    --CFG_SVT,
-                      svt        => CFG_SVT,
+                    RSTADDR         =>  CFG_RSTADDR,                --CFG_RSTADDR,
-                      rstaddr    => CFG_RSTADDR,
+                    SMP             =>  CFG_NCPU-1,                 --CFG_NCPU-1,
-                      smp        => CFG_NCPU-1,
+                    IUFT		=>  2, --: integer range 0 to 4;--CFG_IUFT_EN,
-                      iuft       => 2, --: integer range 0 to 4;
+                    FPFT		=>  1, --: integer range 0 to 4;--CFG_FPUFT_EN,
-                      fpft       => 1, --: integer range 0 to 4;
+                    CMFT		=>  1, --: integer range 0 to 1;--CFG_CACHE_FT_EN,
-                      cmft       => 1, --: integer range 0 to 1;
+                    IUINJ		=>  0, --: integer;             --CFG_RF_ERRINJ,
-                      iuinj      => 0, --: integer;
+                    CEINJ		=>  0, --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
-                      ceinj      => 0, --: integer range 0 to 3;
+                    CACHED          =>  0, --: integer;             --CFG_DFIXED,
-                      cached     => 0, --: integer;
+                    NETLIST		=>  0, --: integer;             --CFG_LEON3_NETLIST,
-                      netlist    => 0, --: integer;
+                    SCANTEST        =>  0, --: integer;             --CFG_SCANTEST,
-                      scantest   => 0, --: integer;
+                    MMUPGSZ         =>  0, --: integer range 0 to 5;--CFG_MMU_PAGE,
-                      mmupgsz    => 0, --: integer range 0 to 5;
+                    BP              =>  1)--CFG_BP
-                      bp         => 1)   --: integer);
+                    )                   --
-                    PORT MAP (
+                  port map (            --
-                      clk   => clkm,
+                    rstn            =>  clkm,   --rst_n,
-                      rstn  => rstn,
+                    clk             =>  rstn,   --clk,
-                      ahbi  => ahbmi,
+                    ahbi            =>  ahbmi,  --ahbmi,
-                      ahbo  => ahbmo(i),
+                    ahbo            =>  ahbmo(i)--ahbmo(CPU_HINDEX),
-                      ahbsi => ahbsi,
+                    ahbsi           =>  ahbsi,  --ahbsi,
-                      ahbso => ahbso,
+                    ahbso           =>  ahbso,  --ahbso,
-                      irqi  => irqi(i),
+                    irqi            =>  irqi(i),--irqi(CPU_HINDEX),
-                      irqo  => irqo(i),
+                    irqo            =>  irqo(i),--irqo(CPU_HINDEX),
-                      dbgi  => dbgi(i),
+                    dbgi            =>  dbgi(i),--dbgi(CPU_HINDEX),
-                      dbgo  => dbgo(i),
+                    dbgo            =>  dbgo(i),--dbgo(CPU_HINDEX),
-                      gclk  => clkm
+                    gclk            =>  clkm--clk
-                      );
+                    );
+                --cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
+                --  u0 : leon3ft
+                --    GENERIC MAP (
+                --      hindex     => i, --: integer;
+                --      fabtech    => fabtech,
+                --      memtech    => memtech,
+                --      nwindows   => CFG_NWIN,
+                --      dsu        => CFG_DSU,
+                --      fpu        => CFG_FPU,
+                --      v8         => CFG_V8,
+                --      cp         => 0,
+                --      mac        => CFG_MAC,
+                --      pclow      => pclow,
+                --      notag      => 0,
+                --      nwp        => CFG_NWP,
+                --      icen       => CFG_ICEN,
+                --      irepl      => CFG_IREPL,
+                --      isets      => CFG_ISETS,
+                --      ilinesize  => CFG_ILINE,
+                --      isetsize   => CFG_ISETSZ,
+                --      isetlock   => CFG_ILOCK,
+                --      dcen       => CFG_DCEN,
+                --      drepl      => CFG_DREPL,
+                --      dsets      => CFG_DSETS,
+                --      dlinesize  => CFG_DLINE,
+                --      dsetsize   => CFG_DSETSZ,
+                --      dsetlock   => CFG_DLOCK,
+                --      dsnoop     => CFG_DSNOOP,
+                --      ilram      => CFG_ILRAMEN,
+                --      ilramsize  => CFG_ILRAMSZ,
+                --      ilramstart => CFG_ILRAMADDR,
+                --      dlram      => CFG_DLRAMEN,
+                --      dlramsize  => CFG_DLRAMSZ,
+                --      dlramstart => CFG_DLRAMADDR,
+                --      mmuen      => CFG_MMUEN,
+                --      itlbnum    => CFG_ITLBNUM,
+                --      dtlbnum    => CFG_DTLBNUM,
+                --      tlb_type   => CFG_TLB_TYPE,
+                --      tlb_rep    => CFG_TLB_REP,
+                --      lddel      => CFG_LDDEL,
+                --      disas      => disas,
+                --      tbuf       => CFG_ITBSZ,
+                --      pwd        => CFG_PWD,
+                --      svt        => CFG_SVT,
+                --      rstaddr    => CFG_RSTADDR,
+                --      smp        => CFG_NCPU-1,
+                --      iuft       => 2, --: integer range 0 to 4;
+                --      fpft       => 1, --: integer range 0 to 4;
+                --      cmft       => 1, --: integer range 0 to 1;
+                --      iuinj      => 0, --: integer;
+                --      ceinj      => 0, --: integer range 0 to 3;
+                --      cached     => 0, --: integer;
+                --      netlist    => 0, --: integer;
+                --      scantest   => 0, --: integer;
+                --      mmupgsz    => 0, --: integer range 0 to 5;
+                --      bp         => 1)   --: integer);
+                --    PORT MAP (
+                --      clk   => clkm,
+                --      rstn  => rstn,
+                --      ahbi  => ahbmi,
+                --      ahbo  => ahbmo(i),
+                --      ahbsi => ahbsi,
+                --      ahbso => ahbso,
+                --      irqi  => irqi(i),
+                --      irqo  => irqo(i),
+                --      dbgi  => dbgi(i),
+                --      dbgo  => dbgo(i),
+                --      gclk  => clkm
+                --      );
                 END GENERATE;
                 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
                 dsugen : IF CFG_DSU = 1 GENERATE
                   dsu0 : dsu3                       -- LEON3 Debug Support Unit
                     GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
                                  ncpu   => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
                     PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
                   dsui.enable <= '1';
                   dsui.break  <= '0';
                 END GENERATE;
               END GENERATE;
               nodsu : IF CFG_DSU = 0 GENERATE
                 ahbso(2)    <= ahbs_none;
                 dsuo.tstop  <= '0';
                 dsuo.active <= '0';
               END GENERATE;
               irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
                 irqctrl0 : irqmp                    -- interrupt controller
                   GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
                   PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
               END GENERATE;
               irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
                 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
                   irqi(i).irl <= "0000";
                 END GENERATE;
                 apbo(2) <= apb_none;
               END GENERATE;
             ----------------------------------------------------------------------
             ---  Memory controllers  ---------------------------------------------
             ----------------------------------------------------------------------
               memctrlr : mctrl GENERIC MAP (
                 hindex  => 0,
                 pindex  => 0,
                 paddr   => 0,
                 srbanks => 1
                 )
                 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
               memi.brdyn  <= '1';
               memi.bexcn  <= '1';
               memi.writen <= '1';
               memi.wrn    <= "1111";
               memi.bwidth <= "10";
               bdr : FOR i IN 0 TO 3 GENERATE
                 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
                   PORT MAP (
                     data(31-i*8 DOWNTO 24-i*8),
                     memo.data(31-i*8 DOWNTO 24-i*8),
                     memo.bdrive(i),
                     memi.data(31-i*8 DOWNTO 24-i*8));
               END GENERATE;
               addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
                 PORT MAP (address, memo.address(21 DOWNTO 2));
               nSRAM_CE_s <= NOT(memo.ramsn(0));
               rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s);
               oen_pad  : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
               nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
               nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
               nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
               nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
               nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
             ----------------------------------------------------------------------
             ---  AHB CONTROLLER  -------------------------------------------------
             ----------------------------------------------------------------------
               ahb0 : ahbctrl                        -- AHB arbiter/multiplexer
                 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
                              rrobin  => CFG_RROBIN, ioaddr => CFG_AHBIO,
                              ioen    => 0, nahbm => maxahbmsp, nahbs => 8)
                 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
             ----------------------------------------------------------------------
             ---  AHB UART  -------------------------------------------------------
             ----------------------------------------------------------------------
               dcomgen : IF CFG_AHB_UART = 1 GENERATE
                 dcom0 : ahbuart
                   GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
                   PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
                 dsurx_pad : inpad GENERIC MAP (tech  => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
                 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
               END GENERATE;
               nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
             ----------------------------------------------------------------------
             ---  APB Bridge  -----------------------------------------------------
             ----------------------------------------------------------------------
               apb0 : apbctrl                        -- AHB/APB bridge
                 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
                 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
             ----------------------------------------------------------------------
             ---  GPT Timer  ------------------------------------------------------
             ----------------------------------------------------------------------
               gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
                 timer0 : gptimer                    -- timer unit
                   GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
                                sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
                                nbits  => CFG_GPT_TW)
                   PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
                 gpti.dhalt  <= dsuo.tstop;
                 gpti.extclk <= '0';
               END GENERATE;
               notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
             ----------------------------------------------------------------------
             ---  APB UART  -------------------------------------------------------
             ----------------------------------------------------------------------
               ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
                 uart1 : apbuart                     -- UART 1
                   GENERIC MAP (pindex   => 1, paddr => 1, pirq => 2, console => dbguart,
                                fifosize => CFG_UART1_FIFO)
                   PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
                 apbuarti.rxd    <= urxd1;
                 apbuarti.extclk <= '0';
                 utxd1           <= apbuarto.txd;
                 apbuarti.ctsn   <= '0';
               END GENERATE;
               noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
             -------------------------------------------------------------------------------
             -- AMBA BUS -------------------------------------------------------------------
             -------------------------------------------------------------------------------
               -- APB --------------------------------------------------------------------
               apbi_ext <= apbi;
               all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
                 max_16_apb : IF I + 5 < 16 GENERATE
                   apbo(I+5) <= apbo_ext(I+5);
                 END GENERATE max_16_apb;
               END GENERATE all_apb;
               -- AHB_Slave --------------------------------------------------------------
               ahbi_s_ext <= ahbsi;
               all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
                 max_16_ahbs : IF I + 3 < 16 GENERATE
                   ahbso(I+3) <= ahbo_s_ext(I+3);
                 END GENERATE max_16_ahbs;
               END GENERATE all_ahbs;
               -- AHB_Master -------------------------------------------------------------
               ahbi_m_ext <= ahbmi;
               all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
                 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
                   ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
                 END GENERATE max_16_ahbm;
               END GENERATE all_ahbm;
-            END Behavioral;
  No newline at end of file
+            END Behavioral;

lib/lpp/lpp_leon3_soc/lpp_leon3_soc_pkg.vhd +47 -46

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             -- Author : Jean-christophe Pellion
             -- Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --          jean-christophe.pellion@easii-ic.com
             ----------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             PACKAGE lpp_leon3_soc_pkg IS
               type soc_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type;
               type soc_ahb_slv_out_vector is array (natural range <>) of ahb_slv_out_type;
               type soc_apb_slv_out_vector is array (natural range <>) of apb_slv_out_type;
               COMPONENT leon3_soc
                 GENERIC (
                   fabtech         : INTEGER;
                   memtech         : INTEGER;
                   padtech         : INTEGER;
                   clktech         : INTEGER;
                   disas           : INTEGER;
                   dbguart         : INTEGER;
                   pclow           : INTEGER;
                   clk_freq        : INTEGER;
+                  IS_RADHARD      : INTEGER;
                   NB_CPU          : INTEGER;
                   ENABLE_FPU      : INTEGER;
                   FPU_NETLIST     : INTEGER;
                   ENABLE_DSU      : INTEGER;
                   ENABLE_AHB_UART : INTEGER;
                   ENABLE_APB_UART : INTEGER;
                   ENABLE_IRQMP    : INTEGER;
                   ENABLE_GPT      : INTEGER;
                   NB_AHB_MASTER   : INTEGER;
                   NB_AHB_SLAVE    : INTEGER;
                   NB_APB_SLAVE    : INTEGER;
                   ADDRESS_SIZE    : INTEGER;
                   USES_IAP_MEMCTRLR : INTEGER
                 );
               PORT (
                 clk    : IN STD_ULOGIC;
                 reset  : IN STD_ULOGIC;
                 errorn : OUT STD_ULOGIC;
                 -- UART AHB ---------------------------------------------------------------
                 ahbrxd : IN  STD_ULOGIC;            -- DSU rx data
                 ahbtxd : OUT STD_ULOGIC;            -- DSU tx data
                 -- UART APB ---------------------------------------------------------------
                 urxd1 : IN  STD_ULOGIC;             -- UART1 rx data
                 utxd1 : OUT STD_ULOGIC;             -- UART1 tx data
                 -- RAM --------------------------------------------------------------------
                 address     : OUT   STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
                 data        : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 nSRAM_BE0   : OUT   STD_LOGIC;
                 nSRAM_BE1   : OUT   STD_LOGIC;
                 nSRAM_BE2   : OUT   STD_LOGIC;
                 nSRAM_BE3   : OUT   STD_LOGIC;
                 nSRAM_WE    : OUT   STD_LOGIC;
                 nSRAM_CE    : OUT   STD_LOGIC_VECTOR(1 downto 0);
                 nSRAM_OE    : OUT   STD_LOGIC;
                 nSRAM_READY : IN    STD_LOGIC;
                 SRAM_MBE    : INOUT STD_LOGIC;
                 -- APB --------------------------------------------------------------------
                 apbi_ext    : OUT apb_slv_in_type;
                 apbo_ext    : IN  soc_apb_slv_out_vector(NB_APB_SLAVE-1+5  DOWNTO 5);
                 -- AHB_Slave --------------------------------------------------------------
                 ahbi_s_ext  : OUT ahb_slv_in_type;
                 ahbo_s_ext  : IN  soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3  DOWNTO 3);
                 -- AHB_Master -------------------------------------------------------------
                 ahbi_m_ext  : OUT AHB_Mst_In_Type;
                 ahbo_m_ext  : IN  soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
               END COMPONENT;
-              COMPONENT leon3ft_soc
+              --COMPONENT leon3ft_soc
-                GENERIC (
+              --  GENERIC (
-                  fabtech         : INTEGER;
+              --    fabtech         : INTEGER;
-                  memtech         : INTEGER;
+              --    memtech         : INTEGER;
-                  padtech         : INTEGER;
+              --    padtech         : INTEGER;
-                  clktech         : INTEGER;
+              --    clktech         : INTEGER;
-                  disas           : INTEGER;
+              --    disas           : INTEGER;
-                  dbguart         : INTEGER;
+              --    dbguart         : INTEGER;
-                  pclow           : INTEGER;
+              --    pclow           : INTEGER;
-                  clk_freq        : INTEGER;
+              --    clk_freq        : INTEGER;
-                  NB_CPU          : INTEGER;
+              --    NB_CPU          : INTEGER;
-                  ENABLE_FPU      : INTEGER;
+              --    ENABLE_FPU      : INTEGER;
-                  FPU_NETLIST     : INTEGER;
+              --    FPU_NETLIST     : INTEGER;
-                  ENABLE_DSU      : INTEGER;
+              --    ENABLE_DSU      : INTEGER;
-                  ENABLE_AHB_UART : INTEGER;
+              --    ENABLE_AHB_UART : INTEGER;
-                  ENABLE_APB_UART : INTEGER;
+              --    ENABLE_APB_UART : INTEGER;
-                  ENABLE_IRQMP    : INTEGER;
+              --    ENABLE_IRQMP    : INTEGER;
-                  ENABLE_GPT      : INTEGER;
+              --    ENABLE_GPT      : INTEGER;
-                  NB_AHB_MASTER   : INTEGER;
+              --    NB_AHB_MASTER   : INTEGER;
-                  NB_AHB_SLAVE    : INTEGER;
+              --    NB_AHB_SLAVE    : INTEGER;
-                  NB_APB_SLAVE    : INTEGER);
+              --    NB_APB_SLAVE    : INTEGER);
-                PORT (
+              --  PORT (
-                  clk        : IN    STD_ULOGIC;
+              --    clk        : IN    STD_ULOGIC;
-                  reset      : IN    STD_ULOGIC;
+              --    reset      : IN    STD_ULOGIC;
-                  errorn     : OUT   STD_ULOGIC;
+              --    errorn     : OUT   STD_ULOGIC;
-                  ahbrxd     : IN    STD_ULOGIC;
+              --    ahbrxd     : IN    STD_ULOGIC;
-                  ahbtxd     : OUT   STD_ULOGIC;
+              --    ahbtxd     : OUT   STD_ULOGIC;
-                  urxd1      : IN    STD_ULOGIC;
+              --    urxd1      : IN    STD_ULOGIC;
-                  utxd1      : OUT   STD_ULOGIC;
+              --    utxd1      : OUT   STD_ULOGIC;
-                  address    : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
+              --    address    : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
-                  data       : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+              --    data       : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-                  nSRAM_BE0  : OUT   STD_LOGIC;
+              --    nSRAM_BE0  : OUT   STD_LOGIC;
-                  nSRAM_BE1  : OUT   STD_LOGIC;
+              --    nSRAM_BE1  : OUT   STD_LOGIC;
-                  nSRAM_BE2  : OUT   STD_LOGIC;
+              --    nSRAM_BE2  : OUT   STD_LOGIC;
-                  nSRAM_BE3  : OUT   STD_LOGIC;
+              --    nSRAM_BE3  : OUT   STD_LOGIC;
-                  nSRAM_WE   : OUT   STD_LOGIC;
+              --    nSRAM_WE   : OUT   STD_LOGIC;
-                  nSRAM_CE   : OUT   STD_LOGIC;
+              --    nSRAM_CE   : OUT   STD_LOGIC;
-                  nSRAM_OE   : OUT   STD_LOGIC;
+              --    nSRAM_OE   : OUT   STD_LOGIC;
-                  apbi_ext   : OUT   apb_slv_in_type;
+              --    apbi_ext   : OUT   apb_slv_in_type;
-                  apbo_ext   : IN    soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
+              --    apbo_ext   : IN    soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
-                  ahbi_s_ext : OUT   ahb_slv_in_type;
+              --    ahbi_s_ext : OUT   ahb_slv_in_type;
-                  ahbo_s_ext : IN    soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
+              --    ahbo_s_ext : IN    soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
-                  ahbi_m_ext : OUT   AHB_Mst_In_Type;
+              --    ahbi_m_ext : OUT   AHB_Mst_In_Type;
-                  ahbo_m_ext : IN    soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
+              --    ahbo_m_ext : IN    soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
-              END COMPONENT;
+              --END COMPONENT;
-            END;
  No newline at end of file
+            END;

lib/lpp/lpp_leon3_soc/vhdlsyn.txt 0 -1

             lpp_leon3_soc_pkg.vhd
             leon3_soc.vhd
-            leon3ft_soc.vhd

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